LegalizeDAG.cpp revision 92d63ccfc7d86d39bc0b806bf7e9fac13dd2d7b5
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/Analysis/DebugInfo.h" 15#include "llvm/CodeGen/Analysis.h" 16#include "llvm/CodeGen/MachineFunction.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/SelectionDAG.h" 19#include "llvm/Target/TargetFrameLowering.h" 20#include "llvm/Target/TargetLowering.h" 21#include "llvm/Target/TargetData.h" 22#include "llvm/Target/TargetMachine.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/DerivedTypes.h" 26#include "llvm/LLVMContext.h" 27#include "llvm/Support/Debug.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/MathExtras.h" 30#include "llvm/Support/raw_ostream.h" 31#include "llvm/ADT/DenseMap.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/SmallPtrSet.h" 34using namespace llvm; 35 36//===----------------------------------------------------------------------===// 37/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 38/// hacks on it until the target machine can handle it. This involves 39/// eliminating value sizes the machine cannot handle (promoting small sizes to 40/// large sizes or splitting up large values into small values) as well as 41/// eliminating operations the machine cannot handle. 42/// 43/// This code also does a small amount of optimization and recognition of idioms 44/// as part of its processing. For example, if a target does not support a 45/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 46/// will attempt merge setcc and brc instructions into brcc's. 47/// 48namespace { 49class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener { 50 const TargetMachine &TM; 51 const TargetLowering &TLI; 52 SelectionDAG &DAG; 53 54 /// LegalizePosition - The iterator for walking through the node list. 55 SelectionDAG::allnodes_iterator LegalizePosition; 56 57 /// LegalizedNodes - The set of nodes which have already been legalized. 58 SmallPtrSet<SDNode *, 16> LegalizedNodes; 59 60 // Libcall insertion helpers. 61 62public: 63 explicit SelectionDAGLegalize(SelectionDAG &DAG); 64 65 void LegalizeDAG(); 66 67private: 68 /// LegalizeOp - Legalizes the given operation. 69 void LegalizeOp(SDNode *Node); 70 71 SDValue OptimizeFloatStore(StoreSDNode *ST); 72 73 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 74 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 75 /// is necessary to spill the vector being inserted into to memory, perform 76 /// the insert there, and then read the result back. 77 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 78 SDValue Idx, DebugLoc dl); 79 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 80 SDValue Idx, DebugLoc dl); 81 82 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 83 /// performs the same shuffe in terms of order or result bytes, but on a type 84 /// whose vector element type is narrower than the original shuffle type. 85 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 86 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 87 SDValue N1, SDValue N2, 88 ArrayRef<int> Mask) const; 89 90 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 91 DebugLoc dl); 92 93 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 94 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, 95 unsigned NumOps, bool isSigned, DebugLoc dl); 96 97 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC, 98 SDNode *Node, bool isSigned); 99 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 100 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 101 RTLIB::Libcall Call_PPCF128); 102 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 103 RTLIB::Libcall Call_I8, 104 RTLIB::Libcall Call_I16, 105 RTLIB::Libcall Call_I32, 106 RTLIB::Libcall Call_I64, 107 RTLIB::Libcall Call_I128); 108 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results); 109 110 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 111 SDValue ExpandBUILD_VECTOR(SDNode *Node); 112 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 113 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 114 SmallVectorImpl<SDValue> &Results); 115 SDValue ExpandFCOPYSIGN(SDNode *Node); 116 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 117 DebugLoc dl); 118 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 119 DebugLoc dl); 120 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 121 DebugLoc dl); 122 123 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 124 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 125 126 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 127 SDValue ExpandInsertToVectorThroughStack(SDValue Op); 128 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 129 130 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP); 131 132 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node); 133 134 void ExpandNode(SDNode *Node); 135 void PromoteNode(SDNode *Node); 136 137 void ForgetNode(SDNode *N) { 138 LegalizedNodes.erase(N); 139 if (LegalizePosition == SelectionDAG::allnodes_iterator(N)) 140 ++LegalizePosition; 141 } 142 143public: 144 // DAGUpdateListener implementation. 145 virtual void NodeDeleted(SDNode *N, SDNode *E) { 146 ForgetNode(N); 147 } 148 virtual void NodeUpdated(SDNode *N) {} 149 150 // Node replacement helpers 151 void ReplacedNode(SDNode *N) { 152 if (N->use_empty()) { 153 DAG.RemoveDeadNode(N); 154 } else { 155 ForgetNode(N); 156 } 157 } 158 void ReplaceNode(SDNode *Old, SDNode *New) { 159 DAG.ReplaceAllUsesWith(Old, New); 160 ReplacedNode(Old); 161 } 162 void ReplaceNode(SDValue Old, SDValue New) { 163 DAG.ReplaceAllUsesWith(Old, New); 164 ReplacedNode(Old.getNode()); 165 } 166 void ReplaceNode(SDNode *Old, const SDValue *New) { 167 DAG.ReplaceAllUsesWith(Old, New); 168 ReplacedNode(Old); 169 } 170}; 171} 172 173/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 174/// performs the same shuffe in terms of order or result bytes, but on a type 175/// whose vector element type is narrower than the original shuffle type. 176/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 177SDValue 178SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 179 SDValue N1, SDValue N2, 180 ArrayRef<int> Mask) const { 181 unsigned NumMaskElts = VT.getVectorNumElements(); 182 unsigned NumDestElts = NVT.getVectorNumElements(); 183 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 184 185 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 186 187 if (NumEltsGrowth == 1) 188 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 189 190 SmallVector<int, 8> NewMask; 191 for (unsigned i = 0; i != NumMaskElts; ++i) { 192 int Idx = Mask[i]; 193 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 194 if (Idx < 0) 195 NewMask.push_back(-1); 196 else 197 NewMask.push_back(Idx * NumEltsGrowth + j); 198 } 199 } 200 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 201 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 202 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 203} 204 205SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 206 : SelectionDAG::DAGUpdateListener(dag), 207 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 208 DAG(dag) { 209} 210 211void SelectionDAGLegalize::LegalizeDAG() { 212 DAG.AssignTopologicalOrder(); 213 214 // Visit all the nodes. We start in topological order, so that we see 215 // nodes with their original operands intact. Legalization can produce 216 // new nodes which may themselves need to be legalized. Iterate until all 217 // nodes have been legalized. 218 for (;;) { 219 bool AnyLegalized = false; 220 for (LegalizePosition = DAG.allnodes_end(); 221 LegalizePosition != DAG.allnodes_begin(); ) { 222 --LegalizePosition; 223 224 SDNode *N = LegalizePosition; 225 if (LegalizedNodes.insert(N)) { 226 AnyLegalized = true; 227 LegalizeOp(N); 228 } 229 } 230 if (!AnyLegalized) 231 break; 232 233 } 234 235 // Remove dead nodes now. 236 DAG.RemoveDeadNodes(); 237} 238 239/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 240/// a load from the constant pool. 241SDValue 242SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) { 243 bool Extend = false; 244 DebugLoc dl = CFP->getDebugLoc(); 245 246 // If a FP immediate is precise when represented as a float and if the 247 // target can do an extending load from float to double, we put it into 248 // the constant pool as a float, even if it's is statically typed as a 249 // double. This shrinks FP constants and canonicalizes them for targets where 250 // an FP extending load is the same cost as a normal load (such as on the x87 251 // fp stack or PPC FP unit). 252 EVT VT = CFP->getValueType(0); 253 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 254 if (!UseCP) { 255 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 256 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 257 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 258 } 259 260 EVT OrigVT = VT; 261 EVT SVT = VT; 262 while (SVT != MVT::f32) { 263 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 264 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) && 265 // Only do this if the target has a native EXTLOAD instruction from 266 // smaller type. 267 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 268 TLI.ShouldShrinkFPConstant(OrigVT)) { 269 Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 270 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 271 VT = SVT; 272 Extend = true; 273 } 274 } 275 276 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 277 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 278 if (Extend) { 279 SDValue Result = 280 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, 281 DAG.getEntryNode(), 282 CPIdx, MachinePointerInfo::getConstantPool(), 283 VT, false, false, Alignment); 284 return Result; 285 } 286 SDValue Result = 287 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 288 MachinePointerInfo::getConstantPool(), false, false, false, 289 Alignment); 290 return Result; 291} 292 293/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 294static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 295 const TargetLowering &TLI, 296 SelectionDAGLegalize *DAGLegalize) { 297 assert(ST->getAddressingMode() == ISD::UNINDEXED && 298 "unaligned indexed stores not implemented!"); 299 SDValue Chain = ST->getChain(); 300 SDValue Ptr = ST->getBasePtr(); 301 SDValue Val = ST->getValue(); 302 EVT VT = Val.getValueType(); 303 int Alignment = ST->getAlignment(); 304 DebugLoc dl = ST->getDebugLoc(); 305 if (ST->getMemoryVT().isFloatingPoint() || 306 ST->getMemoryVT().isVector()) { 307 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 308 if (TLI.isTypeLegal(intVT)) { 309 // Expand to a bitconvert of the value to the integer type of the 310 // same size, then a (misaligned) int store. 311 // FIXME: Does not handle truncating floating point stores! 312 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); 313 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(), 314 ST->isVolatile(), ST->isNonTemporal(), Alignment); 315 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result); 316 return; 317 } 318 // Do a (aligned) store to a stack slot, then copy from the stack slot 319 // to the final destination using (unaligned) integer loads and stores. 320 EVT StoredVT = ST->getMemoryVT(); 321 EVT RegVT = 322 TLI.getRegisterType(*DAG.getContext(), 323 EVT::getIntegerVT(*DAG.getContext(), 324 StoredVT.getSizeInBits())); 325 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 326 unsigned RegBytes = RegVT.getSizeInBits() / 8; 327 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 328 329 // Make sure the stack slot is also aligned for the register type. 330 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 331 332 // Perform the original store, only redirected to the stack slot. 333 SDValue Store = DAG.getTruncStore(Chain, dl, 334 Val, StackPtr, MachinePointerInfo(), 335 StoredVT, false, false, 0); 336 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 337 SmallVector<SDValue, 8> Stores; 338 unsigned Offset = 0; 339 340 // Do all but one copies using the full register width. 341 for (unsigned i = 1; i < NumRegs; i++) { 342 // Load one integer register's worth from the stack slot. 343 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, 344 MachinePointerInfo(), 345 false, false, false, 0); 346 // Store it to the final location. Remember the store. 347 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 348 ST->getPointerInfo().getWithOffset(Offset), 349 ST->isVolatile(), ST->isNonTemporal(), 350 MinAlign(ST->getAlignment(), Offset))); 351 // Increment the pointers. 352 Offset += RegBytes; 353 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 354 Increment); 355 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 356 } 357 358 // The last store may be partial. Do a truncating store. On big-endian 359 // machines this requires an extending load from the stack slot to ensure 360 // that the bits are in the right place. 361 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 362 8 * (StoredBytes - Offset)); 363 364 // Load from the stack slot. 365 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 366 MachinePointerInfo(), 367 MemVT, false, false, 0); 368 369 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 370 ST->getPointerInfo() 371 .getWithOffset(Offset), 372 MemVT, ST->isVolatile(), 373 ST->isNonTemporal(), 374 MinAlign(ST->getAlignment(), Offset))); 375 // The order of the stores doesn't matter - say it with a TokenFactor. 376 SDValue Result = 377 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 378 Stores.size()); 379 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result); 380 return; 381 } 382 assert(ST->getMemoryVT().isInteger() && 383 !ST->getMemoryVT().isVector() && 384 "Unaligned store of unknown type."); 385 // Get the half-size VT 386 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 387 int NumBits = NewStoredVT.getSizeInBits(); 388 int IncrementSize = NumBits / 8; 389 390 // Divide the stored value in two parts. 391 SDValue ShiftAmount = DAG.getConstant(NumBits, 392 TLI.getShiftAmountTy(Val.getValueType())); 393 SDValue Lo = Val; 394 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 395 396 // Store the two parts 397 SDValue Store1, Store2; 398 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 399 ST->getPointerInfo(), NewStoredVT, 400 ST->isVolatile(), ST->isNonTemporal(), Alignment); 401 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 402 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 403 Alignment = MinAlign(Alignment, IncrementSize); 404 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 405 ST->getPointerInfo().getWithOffset(IncrementSize), 406 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 407 Alignment); 408 409 SDValue Result = 410 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 411 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result); 412} 413 414/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 415static void 416ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 417 const TargetLowering &TLI, 418 SDValue &ValResult, SDValue &ChainResult) { 419 assert(LD->getAddressingMode() == ISD::UNINDEXED && 420 "unaligned indexed loads not implemented!"); 421 SDValue Chain = LD->getChain(); 422 SDValue Ptr = LD->getBasePtr(); 423 EVT VT = LD->getValueType(0); 424 EVT LoadedVT = LD->getMemoryVT(); 425 DebugLoc dl = LD->getDebugLoc(); 426 if (VT.isFloatingPoint() || VT.isVector()) { 427 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 428 if (TLI.isTypeLegal(intVT)) { 429 // Expand to a (misaligned) integer load of the same size, 430 // then bitconvert to floating point or vector. 431 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(), 432 LD->isVolatile(), 433 LD->isNonTemporal(), 434 LD->isInvariant(), LD->getAlignment()); 435 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); 436 if (VT.isFloatingPoint() && LoadedVT != VT) 437 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 438 439 ValResult = Result; 440 ChainResult = Chain; 441 return; 442 } 443 444 // Copy the value to a (aligned) stack slot using (unaligned) integer 445 // loads and stores, then do a (aligned) load from the stack slot. 446 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 447 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 448 unsigned RegBytes = RegVT.getSizeInBits() / 8; 449 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 450 451 // Make sure the stack slot is also aligned for the register type. 452 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 453 454 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 455 SmallVector<SDValue, 8> Stores; 456 SDValue StackPtr = StackBase; 457 unsigned Offset = 0; 458 459 // Do all but one copies using the full register width. 460 for (unsigned i = 1; i < NumRegs; i++) { 461 // Load one integer register's worth from the original location. 462 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, 463 LD->getPointerInfo().getWithOffset(Offset), 464 LD->isVolatile(), LD->isNonTemporal(), 465 LD->isInvariant(), 466 MinAlign(LD->getAlignment(), Offset)); 467 // Follow the load with a store to the stack slot. Remember the store. 468 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 469 MachinePointerInfo(), false, false, 0)); 470 // Increment the pointers. 471 Offset += RegBytes; 472 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 473 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 474 Increment); 475 } 476 477 // The last copy may be partial. Do an extending load. 478 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 479 8 * (LoadedBytes - Offset)); 480 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 481 LD->getPointerInfo().getWithOffset(Offset), 482 MemVT, LD->isVolatile(), 483 LD->isNonTemporal(), 484 MinAlign(LD->getAlignment(), Offset)); 485 // Follow the load with a store to the stack slot. Remember the store. 486 // On big-endian machines this requires a truncating store to ensure 487 // that the bits end up in the right place. 488 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 489 MachinePointerInfo(), MemVT, 490 false, false, 0)); 491 492 // The order of the stores doesn't matter - say it with a TokenFactor. 493 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 494 Stores.size()); 495 496 // Finally, perform the original load only redirected to the stack slot. 497 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 498 MachinePointerInfo(), LoadedVT, false, false, 0); 499 500 // Callers expect a MERGE_VALUES node. 501 ValResult = Load; 502 ChainResult = TF; 503 return; 504 } 505 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 506 "Unaligned load of unsupported type."); 507 508 // Compute the new VT that is half the size of the old one. This is an 509 // integer MVT. 510 unsigned NumBits = LoadedVT.getSizeInBits(); 511 EVT NewLoadedVT; 512 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 513 NumBits >>= 1; 514 515 unsigned Alignment = LD->getAlignment(); 516 unsigned IncrementSize = NumBits / 8; 517 ISD::LoadExtType HiExtType = LD->getExtensionType(); 518 519 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 520 if (HiExtType == ISD::NON_EXTLOAD) 521 HiExtType = ISD::ZEXTLOAD; 522 523 // Load the value in two parts 524 SDValue Lo, Hi; 525 if (TLI.isLittleEndian()) { 526 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), 527 NewLoadedVT, LD->isVolatile(), 528 LD->isNonTemporal(), Alignment); 529 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 530 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 531 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, 532 LD->getPointerInfo().getWithOffset(IncrementSize), 533 NewLoadedVT, LD->isVolatile(), 534 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 535 } else { 536 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(), 537 NewLoadedVT, LD->isVolatile(), 538 LD->isNonTemporal(), Alignment); 539 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 540 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 541 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, 542 LD->getPointerInfo().getWithOffset(IncrementSize), 543 NewLoadedVT, LD->isVolatile(), 544 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 545 } 546 547 // aggregate the two parts 548 SDValue ShiftAmount = DAG.getConstant(NumBits, 549 TLI.getShiftAmountTy(Hi.getValueType())); 550 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 551 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 552 553 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 554 Hi.getValue(1)); 555 556 ValResult = Result; 557 ChainResult = TF; 558} 559 560/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 561/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 562/// is necessary to spill the vector being inserted into to memory, perform 563/// the insert there, and then read the result back. 564SDValue SelectionDAGLegalize:: 565PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 566 DebugLoc dl) { 567 SDValue Tmp1 = Vec; 568 SDValue Tmp2 = Val; 569 SDValue Tmp3 = Idx; 570 571 // If the target doesn't support this, we have to spill the input vector 572 // to a temporary stack slot, update the element, then reload it. This is 573 // badness. We could also load the value into a vector register (either 574 // with a "move to register" or "extload into register" instruction, then 575 // permute it into place, if the idx is a constant and if the idx is 576 // supported by the target. 577 EVT VT = Tmp1.getValueType(); 578 EVT EltVT = VT.getVectorElementType(); 579 EVT IdxVT = Tmp3.getValueType(); 580 EVT PtrVT = TLI.getPointerTy(); 581 SDValue StackPtr = DAG.CreateStackTemporary(VT); 582 583 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 584 585 // Store the vector. 586 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 587 MachinePointerInfo::getFixedStack(SPFI), 588 false, false, 0); 589 590 // Truncate or zero extend offset to target pointer type. 591 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 592 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 593 // Add the offset to the index. 594 unsigned EltSize = EltVT.getSizeInBits()/8; 595 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 596 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 597 // Store the scalar value. 598 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT, 599 false, false, 0); 600 // Load the updated vector. 601 return DAG.getLoad(VT, dl, Ch, StackPtr, 602 MachinePointerInfo::getFixedStack(SPFI), false, false, 603 false, 0); 604} 605 606 607SDValue SelectionDAGLegalize:: 608ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 609 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 610 // SCALAR_TO_VECTOR requires that the type of the value being inserted 611 // match the element type of the vector being created, except for 612 // integers in which case the inserted value can be over width. 613 EVT EltVT = Vec.getValueType().getVectorElementType(); 614 if (Val.getValueType() == EltVT || 615 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 616 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 617 Vec.getValueType(), Val); 618 619 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 620 // We generate a shuffle of InVec and ScVec, so the shuffle mask 621 // should be 0,1,2,3,4,5... with the appropriate element replaced with 622 // elt 0 of the RHS. 623 SmallVector<int, 8> ShufOps; 624 for (unsigned i = 0; i != NumElts; ++i) 625 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 626 627 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 628 &ShufOps[0]); 629 } 630 } 631 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 632} 633 634SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 635 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 636 // FIXME: We shouldn't do this for TargetConstantFP's. 637 // FIXME: move this to the DAG Combiner! Note that we can't regress due 638 // to phase ordering between legalized code and the dag combiner. This 639 // probably means that we need to integrate dag combiner and legalizer 640 // together. 641 // We generally can't do this one for long doubles. 642 SDValue Tmp1 = ST->getChain(); 643 SDValue Tmp2 = ST->getBasePtr(); 644 SDValue Tmp3; 645 unsigned Alignment = ST->getAlignment(); 646 bool isVolatile = ST->isVolatile(); 647 bool isNonTemporal = ST->isNonTemporal(); 648 DebugLoc dl = ST->getDebugLoc(); 649 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 650 if (CFP->getValueType(0) == MVT::f32 && 651 TLI.isTypeLegal(MVT::i32)) { 652 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 653 bitcastToAPInt().zextOrTrunc(32), 654 MVT::i32); 655 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 656 isVolatile, isNonTemporal, Alignment); 657 } 658 659 if (CFP->getValueType(0) == MVT::f64) { 660 // If this target supports 64-bit registers, do a single 64-bit store. 661 if (TLI.isTypeLegal(MVT::i64)) { 662 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 663 zextOrTrunc(64), MVT::i64); 664 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 665 isVolatile, isNonTemporal, Alignment); 666 } 667 668 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) { 669 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 670 // stores. If the target supports neither 32- nor 64-bits, this 671 // xform is certainly not worth it. 672 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 673 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32); 674 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 675 if (TLI.isBigEndian()) std::swap(Lo, Hi); 676 677 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile, 678 isNonTemporal, Alignment); 679 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 680 DAG.getIntPtrConstant(4)); 681 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, 682 ST->getPointerInfo().getWithOffset(4), 683 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 684 685 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 686 } 687 } 688 } 689 return SDValue(0, 0); 690} 691 692/// LegalizeOp - Return a legal replacement for the given operation, with 693/// all legal operands. 694void SelectionDAGLegalize::LegalizeOp(SDNode *Node) { 695 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 696 return; 697 698 DebugLoc dl = Node->getDebugLoc(); 699 700 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 701 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) == 702 TargetLowering::TypeLegal && 703 "Unexpected illegal type!"); 704 705 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 706 assert((TLI.getTypeAction(*DAG.getContext(), 707 Node->getOperand(i).getValueType()) == 708 TargetLowering::TypeLegal || 709 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 710 "Unexpected illegal type!"); 711 712 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 713 bool isCustom = false; 714 715 // Figure out the correct action; the way to query this varies by opcode 716 TargetLowering::LegalizeAction Action = TargetLowering::Legal; 717 bool SimpleFinishLegalizing = true; 718 switch (Node->getOpcode()) { 719 case ISD::INTRINSIC_W_CHAIN: 720 case ISD::INTRINSIC_WO_CHAIN: 721 case ISD::INTRINSIC_VOID: 722 case ISD::STACKSAVE: 723 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 724 break; 725 case ISD::VAARG: 726 Action = TLI.getOperationAction(Node->getOpcode(), 727 Node->getValueType(0)); 728 if (Action != TargetLowering::Promote) 729 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 730 break; 731 case ISD::SINT_TO_FP: 732 case ISD::UINT_TO_FP: 733 case ISD::EXTRACT_VECTOR_ELT: 734 Action = TLI.getOperationAction(Node->getOpcode(), 735 Node->getOperand(0).getValueType()); 736 break; 737 case ISD::FP_ROUND_INREG: 738 case ISD::SIGN_EXTEND_INREG: { 739 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 740 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 741 break; 742 } 743 case ISD::ATOMIC_STORE: { 744 Action = TLI.getOperationAction(Node->getOpcode(), 745 Node->getOperand(2).getValueType()); 746 break; 747 } 748 case ISD::SELECT_CC: 749 case ISD::SETCC: 750 case ISD::BR_CC: { 751 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 752 Node->getOpcode() == ISD::SETCC ? 2 : 1; 753 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 754 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 755 ISD::CondCode CCCode = 756 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 757 Action = TLI.getCondCodeAction(CCCode, OpVT); 758 if (Action == TargetLowering::Legal) { 759 if (Node->getOpcode() == ISD::SELECT_CC) 760 Action = TLI.getOperationAction(Node->getOpcode(), 761 Node->getValueType(0)); 762 else 763 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 764 } 765 break; 766 } 767 case ISD::LOAD: 768 case ISD::STORE: 769 // FIXME: Model these properly. LOAD and STORE are complicated, and 770 // STORE expects the unlegalized operand in some cases. 771 SimpleFinishLegalizing = false; 772 break; 773 case ISD::CALLSEQ_START: 774 case ISD::CALLSEQ_END: 775 // FIXME: This shouldn't be necessary. These nodes have special properties 776 // dealing with the recursive nature of legalization. Removing this 777 // special case should be done as part of making LegalizeDAG non-recursive. 778 SimpleFinishLegalizing = false; 779 break; 780 case ISD::EXTRACT_ELEMENT: 781 case ISD::FLT_ROUNDS_: 782 case ISD::SADDO: 783 case ISD::SSUBO: 784 case ISD::UADDO: 785 case ISD::USUBO: 786 case ISD::SMULO: 787 case ISD::UMULO: 788 case ISD::FPOWI: 789 case ISD::MERGE_VALUES: 790 case ISD::EH_RETURN: 791 case ISD::FRAME_TO_ARGS_OFFSET: 792 case ISD::EH_SJLJ_SETJMP: 793 case ISD::EH_SJLJ_LONGJMP: 794 // These operations lie about being legal: when they claim to be legal, 795 // they should actually be expanded. 796 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 797 if (Action == TargetLowering::Legal) 798 Action = TargetLowering::Expand; 799 break; 800 case ISD::INIT_TRAMPOLINE: 801 case ISD::ADJUST_TRAMPOLINE: 802 case ISD::FRAMEADDR: 803 case ISD::RETURNADDR: 804 // These operations lie about being legal: when they claim to be legal, 805 // they should actually be custom-lowered. 806 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 807 if (Action == TargetLowering::Legal) 808 Action = TargetLowering::Custom; 809 break; 810 default: 811 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 812 Action = TargetLowering::Legal; 813 } else { 814 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 815 } 816 break; 817 } 818 819 if (SimpleFinishLegalizing) { 820 SDNode *NewNode = Node; 821 switch (Node->getOpcode()) { 822 default: break; 823 case ISD::SHL: 824 case ISD::SRL: 825 case ISD::SRA: 826 case ISD::ROTL: 827 case ISD::ROTR: 828 // Legalizing shifts/rotates requires adjusting the shift amount 829 // to the appropriate width. 830 if (!Node->getOperand(1).getValueType().isVector()) { 831 SDValue SAO = 832 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(), 833 Node->getOperand(1)); 834 HandleSDNode Handle(SAO); 835 LegalizeOp(SAO.getNode()); 836 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0), 837 Handle.getValue()); 838 } 839 break; 840 case ISD::SRL_PARTS: 841 case ISD::SRA_PARTS: 842 case ISD::SHL_PARTS: 843 // Legalizing shifts/rotates requires adjusting the shift amount 844 // to the appropriate width. 845 if (!Node->getOperand(2).getValueType().isVector()) { 846 SDValue SAO = 847 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(), 848 Node->getOperand(2)); 849 HandleSDNode Handle(SAO); 850 LegalizeOp(SAO.getNode()); 851 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0), 852 Node->getOperand(1), 853 Handle.getValue()); 854 } 855 break; 856 } 857 858 if (NewNode != Node) { 859 DAG.ReplaceAllUsesWith(Node, NewNode); 860 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 861 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i)); 862 ReplacedNode(Node); 863 Node = NewNode; 864 } 865 switch (Action) { 866 case TargetLowering::Legal: 867 return; 868 case TargetLowering::Custom: 869 // FIXME: The handling for custom lowering with multiple results is 870 // a complete mess. 871 Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG); 872 if (Tmp1.getNode()) { 873 SmallVector<SDValue, 8> ResultVals; 874 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 875 if (e == 1) 876 ResultVals.push_back(Tmp1); 877 else 878 ResultVals.push_back(Tmp1.getValue(i)); 879 } 880 if (Tmp1.getNode() != Node || Tmp1.getResNo() != 0) { 881 DAG.ReplaceAllUsesWith(Node, ResultVals.data()); 882 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 883 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]); 884 ReplacedNode(Node); 885 } 886 return; 887 } 888 889 // FALL THROUGH 890 case TargetLowering::Expand: 891 ExpandNode(Node); 892 return; 893 case TargetLowering::Promote: 894 PromoteNode(Node); 895 return; 896 } 897 } 898 899 switch (Node->getOpcode()) { 900 default: 901#ifndef NDEBUG 902 dbgs() << "NODE: "; 903 Node->dump( &DAG); 904 dbgs() << "\n"; 905#endif 906 llvm_unreachable("Do not know how to legalize this operator!"); 907 908 case ISD::CALLSEQ_START: 909 case ISD::CALLSEQ_END: 910 break; 911 case ISD::LOAD: { 912 LoadSDNode *LD = cast<LoadSDNode>(Node); 913 Tmp1 = LD->getChain(); // Legalize the chain. 914 Tmp2 = LD->getBasePtr(); // Legalize the base pointer. 915 916 ISD::LoadExtType ExtType = LD->getExtensionType(); 917 if (ExtType == ISD::NON_EXTLOAD) { 918 EVT VT = Node->getValueType(0); 919 Tmp3 = SDValue(Node, 0); 920 Tmp4 = SDValue(Node, 1); 921 922 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 923 default: llvm_unreachable("This action is not supported yet!"); 924 case TargetLowering::Legal: 925 // If this is an unaligned load and the target doesn't support it, 926 // expand it. 927 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 928 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 929 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 930 if (LD->getAlignment() < ABIAlignment){ 931 ExpandUnalignedLoad(cast<LoadSDNode>(Node), 932 DAG, TLI, Tmp3, Tmp4); 933 } 934 } 935 break; 936 case TargetLowering::Custom: 937 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 938 if (Tmp1.getNode()) { 939 Tmp3 = Tmp1; 940 Tmp4 = Tmp1.getValue(1); 941 } 942 break; 943 case TargetLowering::Promote: { 944 // Only promote a load of vector type to another. 945 assert(VT.isVector() && "Cannot promote this load!"); 946 // Change base type to a different vector type. 947 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 948 949 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(), 950 LD->isVolatile(), LD->isNonTemporal(), 951 LD->isInvariant(), LD->getAlignment()); 952 Tmp3 = DAG.getNode(ISD::BITCAST, dl, VT, Tmp1); 953 Tmp4 = Tmp1.getValue(1); 954 break; 955 } 956 } 957 if (Tmp4.getNode() != Node) { 958 assert(Tmp3.getNode() != Node && "Load must be completely replaced"); 959 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp3); 960 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp4); 961 ReplacedNode(Node); 962 } 963 return; 964 } 965 966 EVT SrcVT = LD->getMemoryVT(); 967 unsigned SrcWidth = SrcVT.getSizeInBits(); 968 unsigned Alignment = LD->getAlignment(); 969 bool isVolatile = LD->isVolatile(); 970 bool isNonTemporal = LD->isNonTemporal(); 971 972 if (SrcWidth != SrcVT.getStoreSizeInBits() && 973 // Some targets pretend to have an i1 loading operation, and actually 974 // load an i8. This trick is correct for ZEXTLOAD because the top 7 975 // bits are guaranteed to be zero; it helps the optimizers understand 976 // that these bits are zero. It is also useful for EXTLOAD, since it 977 // tells the optimizers that those bits are undefined. It would be 978 // nice to have an effective generic way of getting these benefits... 979 // Until such a way is found, don't insist on promoting i1 here. 980 (SrcVT != MVT::i1 || 981 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 982 // Promote to a byte-sized load if not loading an integral number of 983 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 984 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 985 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 986 SDValue Ch; 987 988 // The extra bits are guaranteed to be zero, since we stored them that 989 // way. A zext load from NVT thus automatically gives zext from SrcVT. 990 991 ISD::LoadExtType NewExtType = 992 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 993 994 SDValue Result = 995 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 996 Tmp1, Tmp2, LD->getPointerInfo(), 997 NVT, isVolatile, isNonTemporal, Alignment); 998 999 Ch = Result.getValue(1); // The chain. 1000 1001 if (ExtType == ISD::SEXTLOAD) 1002 // Having the top bits zero doesn't help when sign extending. 1003 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1004 Result.getValueType(), 1005 Result, DAG.getValueType(SrcVT)); 1006 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1007 // All the top bits are guaranteed to be zero - inform the optimizers. 1008 Result = DAG.getNode(ISD::AssertZext, dl, 1009 Result.getValueType(), Result, 1010 DAG.getValueType(SrcVT)); 1011 1012 Tmp1 = Result; 1013 Tmp2 = Ch; 1014 } else if (SrcWidth & (SrcWidth - 1)) { 1015 // If not loading a power-of-2 number of bits, expand as two loads. 1016 assert(!SrcVT.isVector() && "Unsupported extload!"); 1017 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1018 assert(RoundWidth < SrcWidth); 1019 unsigned ExtraWidth = SrcWidth - RoundWidth; 1020 assert(ExtraWidth < RoundWidth); 1021 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1022 "Load size not an integral number of bytes!"); 1023 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1024 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1025 SDValue Lo, Hi, Ch; 1026 unsigned IncrementSize; 1027 1028 if (TLI.isLittleEndian()) { 1029 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1030 // Load the bottom RoundWidth bits. 1031 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), 1032 Tmp1, Tmp2, 1033 LD->getPointerInfo(), RoundVT, isVolatile, 1034 isNonTemporal, Alignment); 1035 1036 // Load the remaining ExtraWidth bits. 1037 IncrementSize = RoundWidth / 8; 1038 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1039 DAG.getIntPtrConstant(IncrementSize)); 1040 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1041 LD->getPointerInfo().getWithOffset(IncrementSize), 1042 ExtraVT, isVolatile, isNonTemporal, 1043 MinAlign(Alignment, IncrementSize)); 1044 1045 // Build a factor node to remember that this load is independent of 1046 // the other one. 1047 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1048 Hi.getValue(1)); 1049 1050 // Move the top bits to the right place. 1051 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1052 DAG.getConstant(RoundWidth, 1053 TLI.getShiftAmountTy(Hi.getValueType()))); 1054 1055 // Join the hi and lo parts. 1056 Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1057 } else { 1058 // Big endian - avoid unaligned loads. 1059 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1060 // Load the top RoundWidth bits. 1061 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1062 LD->getPointerInfo(), RoundVT, isVolatile, 1063 isNonTemporal, Alignment); 1064 1065 // Load the remaining ExtraWidth bits. 1066 IncrementSize = RoundWidth / 8; 1067 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1068 DAG.getIntPtrConstant(IncrementSize)); 1069 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, 1070 dl, Node->getValueType(0), Tmp1, Tmp2, 1071 LD->getPointerInfo().getWithOffset(IncrementSize), 1072 ExtraVT, isVolatile, isNonTemporal, 1073 MinAlign(Alignment, IncrementSize)); 1074 1075 // Build a factor node to remember that this load is independent of 1076 // the other one. 1077 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1078 Hi.getValue(1)); 1079 1080 // Move the top bits to the right place. 1081 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1082 DAG.getConstant(ExtraWidth, 1083 TLI.getShiftAmountTy(Hi.getValueType()))); 1084 1085 // Join the hi and lo parts. 1086 Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1087 } 1088 1089 Tmp2 = Ch; 1090 } else { 1091 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1092 default: llvm_unreachable("This action is not supported yet!"); 1093 case TargetLowering::Custom: 1094 isCustom = true; 1095 // FALLTHROUGH 1096 case TargetLowering::Legal: 1097 Tmp1 = SDValue(Node, 0); 1098 Tmp2 = SDValue(Node, 1); 1099 1100 if (isCustom) { 1101 Tmp3 = TLI.LowerOperation(SDValue(Node, 0), DAG); 1102 if (Tmp3.getNode()) { 1103 Tmp1 = Tmp3; 1104 Tmp2 = Tmp3.getValue(1); 1105 } 1106 } else { 1107 // If this is an unaligned load and the target doesn't support it, 1108 // expand it. 1109 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1110 Type *Ty = 1111 LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1112 unsigned ABIAlignment = 1113 TLI.getTargetData()->getABITypeAlignment(Ty); 1114 if (LD->getAlignment() < ABIAlignment){ 1115 ExpandUnalignedLoad(cast<LoadSDNode>(Node), 1116 DAG, TLI, Tmp1, Tmp2); 1117 } 1118 } 1119 } 1120 break; 1121 case TargetLowering::Expand: 1122 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) { 1123 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, 1124 LD->getPointerInfo(), 1125 LD->isVolatile(), LD->isNonTemporal(), 1126 LD->isInvariant(), LD->getAlignment()); 1127 unsigned ExtendOp; 1128 switch (ExtType) { 1129 case ISD::EXTLOAD: 1130 ExtendOp = (SrcVT.isFloatingPoint() ? 1131 ISD::FP_EXTEND : ISD::ANY_EXTEND); 1132 break; 1133 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break; 1134 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break; 1135 default: llvm_unreachable("Unexpected extend load type!"); 1136 } 1137 Tmp1 = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load); 1138 Tmp2 = Load.getValue(1); 1139 break; 1140 } 1141 1142 assert(!SrcVT.isVector() && 1143 "Vector Loads are handled in LegalizeVectorOps"); 1144 1145 // FIXME: This does not work for vectors on most targets. Sign- and 1146 // zero-extend operations are currently folded into extending loads, 1147 // whether they are legal or not, and then we end up here without any 1148 // support for legalizing them. 1149 assert(ExtType != ISD::EXTLOAD && 1150 "EXTLOAD should always be supported!"); 1151 // Turn the unsupported load into an EXTLOAD followed by an explicit 1152 // zero/sign extend inreg. 1153 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1154 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT, 1155 LD->isVolatile(), LD->isNonTemporal(), 1156 LD->getAlignment()); 1157 SDValue ValRes; 1158 if (ExtType == ISD::SEXTLOAD) 1159 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1160 Result.getValueType(), 1161 Result, DAG.getValueType(SrcVT)); 1162 else 1163 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType()); 1164 Tmp1 = ValRes; 1165 Tmp2 = Result.getValue(1); 1166 break; 1167 } 1168 } 1169 1170 // Since loads produce two values, make sure to remember that we legalized 1171 // both of them. 1172 if (Tmp2.getNode() != Node) { 1173 assert(Tmp1.getNode() != Node && "Load must be completely replaced"); 1174 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp1); 1175 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp2); 1176 ReplacedNode(Node); 1177 } 1178 break; 1179 } 1180 case ISD::STORE: { 1181 StoreSDNode *ST = cast<StoreSDNode>(Node); 1182 Tmp1 = ST->getChain(); 1183 Tmp2 = ST->getBasePtr(); 1184 unsigned Alignment = ST->getAlignment(); 1185 bool isVolatile = ST->isVolatile(); 1186 bool isNonTemporal = ST->isNonTemporal(); 1187 1188 if (!ST->isTruncatingStore()) { 1189 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1190 ReplaceNode(ST, OptStore); 1191 break; 1192 } 1193 1194 { 1195 Tmp3 = ST->getValue(); 1196 EVT VT = Tmp3.getValueType(); 1197 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1198 default: llvm_unreachable("This action is not supported yet!"); 1199 case TargetLowering::Legal: 1200 // If this is an unaligned store and the target doesn't support it, 1201 // expand it. 1202 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1203 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1204 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1205 if (ST->getAlignment() < ABIAlignment) 1206 ExpandUnalignedStore(cast<StoreSDNode>(Node), 1207 DAG, TLI, this); 1208 } 1209 break; 1210 case TargetLowering::Custom: 1211 Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG); 1212 if (Tmp1.getNode()) 1213 ReplaceNode(SDValue(Node, 0), Tmp1); 1214 break; 1215 case TargetLowering::Promote: { 1216 assert(VT.isVector() && "Unknown legal promote case!"); 1217 Tmp3 = DAG.getNode(ISD::BITCAST, dl, 1218 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1219 SDValue Result = 1220 DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1221 ST->getPointerInfo(), isVolatile, 1222 isNonTemporal, Alignment); 1223 ReplaceNode(SDValue(Node, 0), Result); 1224 break; 1225 } 1226 } 1227 break; 1228 } 1229 } else { 1230 Tmp3 = ST->getValue(); 1231 1232 EVT StVT = ST->getMemoryVT(); 1233 unsigned StWidth = StVT.getSizeInBits(); 1234 1235 if (StWidth != StVT.getStoreSizeInBits()) { 1236 // Promote to a byte-sized store with upper bits zero if not 1237 // storing an integral number of bytes. For example, promote 1238 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1239 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), 1240 StVT.getStoreSizeInBits()); 1241 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1242 SDValue Result = 1243 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 1244 NVT, isVolatile, isNonTemporal, Alignment); 1245 ReplaceNode(SDValue(Node, 0), Result); 1246 } else if (StWidth & (StWidth - 1)) { 1247 // If not storing a power-of-2 number of bits, expand as two stores. 1248 assert(!StVT.isVector() && "Unsupported truncstore!"); 1249 unsigned RoundWidth = 1 << Log2_32(StWidth); 1250 assert(RoundWidth < StWidth); 1251 unsigned ExtraWidth = StWidth - RoundWidth; 1252 assert(ExtraWidth < RoundWidth); 1253 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1254 "Store size not an integral number of bytes!"); 1255 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1256 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1257 SDValue Lo, Hi; 1258 unsigned IncrementSize; 1259 1260 if (TLI.isLittleEndian()) { 1261 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1262 // Store the bottom RoundWidth bits. 1263 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 1264 RoundVT, 1265 isVolatile, isNonTemporal, Alignment); 1266 1267 // Store the remaining ExtraWidth bits. 1268 IncrementSize = RoundWidth / 8; 1269 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1270 DAG.getIntPtrConstant(IncrementSize)); 1271 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1272 DAG.getConstant(RoundWidth, 1273 TLI.getShiftAmountTy(Tmp3.getValueType()))); 1274 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, 1275 ST->getPointerInfo().getWithOffset(IncrementSize), 1276 ExtraVT, isVolatile, isNonTemporal, 1277 MinAlign(Alignment, IncrementSize)); 1278 } else { 1279 // Big endian - avoid unaligned stores. 1280 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1281 // Store the top RoundWidth bits. 1282 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1283 DAG.getConstant(ExtraWidth, 1284 TLI.getShiftAmountTy(Tmp3.getValueType()))); 1285 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(), 1286 RoundVT, isVolatile, isNonTemporal, Alignment); 1287 1288 // Store the remaining ExtraWidth bits. 1289 IncrementSize = RoundWidth / 8; 1290 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1291 DAG.getIntPtrConstant(IncrementSize)); 1292 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, 1293 ST->getPointerInfo().getWithOffset(IncrementSize), 1294 ExtraVT, isVolatile, isNonTemporal, 1295 MinAlign(Alignment, IncrementSize)); 1296 } 1297 1298 // The order of the stores doesn't matter. 1299 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1300 ReplaceNode(SDValue(Node, 0), Result); 1301 } else { 1302 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1303 default: llvm_unreachable("This action is not supported yet!"); 1304 case TargetLowering::Legal: 1305 // If this is an unaligned store and the target doesn't support it, 1306 // expand it. 1307 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1308 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1309 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1310 if (ST->getAlignment() < ABIAlignment) 1311 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this); 1312 } 1313 break; 1314 case TargetLowering::Custom: 1315 ReplaceNode(SDValue(Node, 0), 1316 TLI.LowerOperation(SDValue(Node, 0), DAG)); 1317 break; 1318 case TargetLowering::Expand: 1319 assert(!StVT.isVector() && 1320 "Vector Stores are handled in LegalizeVectorOps"); 1321 1322 // TRUNCSTORE:i16 i32 -> STORE i16 1323 assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!"); 1324 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1325 SDValue Result = 1326 DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), 1327 isVolatile, isNonTemporal, Alignment); 1328 ReplaceNode(SDValue(Node, 0), Result); 1329 break; 1330 } 1331 } 1332 } 1333 break; 1334 } 1335 } 1336} 1337 1338SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1339 SDValue Vec = Op.getOperand(0); 1340 SDValue Idx = Op.getOperand(1); 1341 DebugLoc dl = Op.getDebugLoc(); 1342 // Store the value to a temporary stack slot, then LOAD the returned part. 1343 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1344 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1345 MachinePointerInfo(), false, false, 0); 1346 1347 // Add the offset to the index. 1348 unsigned EltSize = 1349 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1350 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1351 DAG.getConstant(EltSize, Idx.getValueType())); 1352 1353 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1354 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1355 else 1356 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1357 1358 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1359 1360 if (Op.getValueType().isVector()) 1361 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(), 1362 false, false, false, 0); 1363 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1364 MachinePointerInfo(), 1365 Vec.getValueType().getVectorElementType(), 1366 false, false, 0); 1367} 1368 1369SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) { 1370 assert(Op.getValueType().isVector() && "Non-vector insert subvector!"); 1371 1372 SDValue Vec = Op.getOperand(0); 1373 SDValue Part = Op.getOperand(1); 1374 SDValue Idx = Op.getOperand(2); 1375 DebugLoc dl = Op.getDebugLoc(); 1376 1377 // Store the value to a temporary stack slot, then LOAD the returned part. 1378 1379 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1380 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 1381 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI); 1382 1383 // First store the whole vector. 1384 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo, 1385 false, false, 0); 1386 1387 // Then store the inserted part. 1388 1389 // Add the offset to the index. 1390 unsigned EltSize = 1391 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1392 1393 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1394 DAG.getConstant(EltSize, Idx.getValueType())); 1395 1396 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1397 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1398 else 1399 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1400 1401 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, 1402 StackPtr); 1403 1404 // Store the subvector. 1405 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr, 1406 MachinePointerInfo(), false, false, 0); 1407 1408 // Finally, load the updated vector. 1409 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo, 1410 false, false, false, 0); 1411} 1412 1413SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1414 // We can't handle this case efficiently. Allocate a sufficiently 1415 // aligned object on the stack, store each element into it, then load 1416 // the result as a vector. 1417 // Create the stack frame object. 1418 EVT VT = Node->getValueType(0); 1419 EVT EltVT = VT.getVectorElementType(); 1420 DebugLoc dl = Node->getDebugLoc(); 1421 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1422 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1423 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI); 1424 1425 // Emit a store of each element to the stack slot. 1426 SmallVector<SDValue, 8> Stores; 1427 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1428 // Store (in the right endianness) the elements to memory. 1429 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1430 // Ignore undef elements. 1431 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1432 1433 unsigned Offset = TypeByteSize*i; 1434 1435 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1436 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1437 1438 // If the destination vector element type is narrower than the source 1439 // element type, only store the bits necessary. 1440 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1441 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1442 Node->getOperand(i), Idx, 1443 PtrInfo.getWithOffset(Offset), 1444 EltVT, false, false, 0)); 1445 } else 1446 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1447 Node->getOperand(i), Idx, 1448 PtrInfo.getWithOffset(Offset), 1449 false, false, 0)); 1450 } 1451 1452 SDValue StoreChain; 1453 if (!Stores.empty()) // Not all undef elements? 1454 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1455 &Stores[0], Stores.size()); 1456 else 1457 StoreChain = DAG.getEntryNode(); 1458 1459 // Result is a load from the stack slot. 1460 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, 1461 false, false, false, 0); 1462} 1463 1464SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1465 DebugLoc dl = Node->getDebugLoc(); 1466 SDValue Tmp1 = Node->getOperand(0); 1467 SDValue Tmp2 = Node->getOperand(1); 1468 1469 // Get the sign bit of the RHS. First obtain a value that has the same 1470 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1471 SDValue SignBit; 1472 EVT FloatVT = Tmp2.getValueType(); 1473 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1474 if (TLI.isTypeLegal(IVT)) { 1475 // Convert to an integer with the same sign bit. 1476 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2); 1477 } else { 1478 // Store the float to memory, then load the sign part out as an integer. 1479 MVT LoadTy = TLI.getPointerTy(); 1480 // First create a temporary that is aligned for both the load and store. 1481 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1482 // Then store the float to it. 1483 SDValue Ch = 1484 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(), 1485 false, false, 0); 1486 if (TLI.isBigEndian()) { 1487 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1488 // Load out a legal integer with the same sign bit as the float. 1489 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(), 1490 false, false, false, 0); 1491 } else { // Little endian 1492 SDValue LoadPtr = StackPtr; 1493 // The float may be wider than the integer we are going to load. Advance 1494 // the pointer so that the loaded integer will contain the sign bit. 1495 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1496 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1497 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1498 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1499 // Load a legal integer containing the sign bit. 1500 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(), 1501 false, false, false, 0); 1502 // Move the sign bit to the top bit of the loaded integer. 1503 unsigned BitShift = LoadTy.getSizeInBits() - 1504 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1505 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1506 if (BitShift) 1507 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1508 DAG.getConstant(BitShift, 1509 TLI.getShiftAmountTy(SignBit.getValueType()))); 1510 } 1511 } 1512 // Now get the sign bit proper, by seeing whether the value is negative. 1513 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1514 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1515 ISD::SETLT); 1516 // Get the absolute value of the result. 1517 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1518 // Select between the nabs and abs value based on the sign bit of 1519 // the input. 1520 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1521 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1522 AbsVal); 1523} 1524 1525void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1526 SmallVectorImpl<SDValue> &Results) { 1527 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1528 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1529 " not tell us which reg is the stack pointer!"); 1530 DebugLoc dl = Node->getDebugLoc(); 1531 EVT VT = Node->getValueType(0); 1532 SDValue Tmp1 = SDValue(Node, 0); 1533 SDValue Tmp2 = SDValue(Node, 1); 1534 SDValue Tmp3 = Node->getOperand(2); 1535 SDValue Chain = Tmp1.getOperand(0); 1536 1537 // Chain the dynamic stack allocation so that it doesn't modify the stack 1538 // pointer when other instructions are using the stack. 1539 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1540 1541 SDValue Size = Tmp2.getOperand(1); 1542 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1543 Chain = SP.getValue(1); 1544 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1545 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 1546 if (Align > StackAlign) 1547 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1548 DAG.getConstant(-(uint64_t)Align, VT)); 1549 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1550 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1551 1552 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1553 DAG.getIntPtrConstant(0, true), SDValue()); 1554 1555 Results.push_back(Tmp1); 1556 Results.push_back(Tmp2); 1557} 1558 1559/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1560/// condition code CC on the current target. This routine expands SETCC with 1561/// illegal condition code into AND / OR of multiple SETCC values. 1562void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1563 SDValue &LHS, SDValue &RHS, 1564 SDValue &CC, 1565 DebugLoc dl) { 1566 EVT OpVT = LHS.getValueType(); 1567 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1568 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1569 default: llvm_unreachable("Unknown condition code action!"); 1570 case TargetLowering::Legal: 1571 // Nothing to do. 1572 break; 1573 case TargetLowering::Expand: { 1574 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1575 unsigned Opc = 0; 1576 switch (CCCode) { 1577 default: llvm_unreachable("Don't know how to expand this condition!"); 1578 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1579 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1580 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1581 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1582 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1583 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1584 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1585 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1586 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1587 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1588 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1589 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1590 // FIXME: Implement more expansions. 1591 } 1592 1593 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1594 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1595 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1596 RHS = SDValue(); 1597 CC = SDValue(); 1598 break; 1599 } 1600 } 1601} 1602 1603/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1604/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1605/// a load from the stack slot to DestVT, extending it if needed. 1606/// The resultant code need not be legal. 1607SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1608 EVT SlotVT, 1609 EVT DestVT, 1610 DebugLoc dl) { 1611 // Create the stack frame object. 1612 unsigned SrcAlign = 1613 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1614 getTypeForEVT(*DAG.getContext())); 1615 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1616 1617 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1618 int SPFI = StackPtrFI->getIndex(); 1619 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI); 1620 1621 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1622 unsigned SlotSize = SlotVT.getSizeInBits(); 1623 unsigned DestSize = DestVT.getSizeInBits(); 1624 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); 1625 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType); 1626 1627 // Emit a store to the stack slot. Use a truncstore if the input value is 1628 // later than DestVT. 1629 SDValue Store; 1630 1631 if (SrcSize > SlotSize) 1632 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1633 PtrInfo, SlotVT, false, false, SrcAlign); 1634 else { 1635 assert(SrcSize == SlotSize && "Invalid store"); 1636 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1637 PtrInfo, false, false, SrcAlign); 1638 } 1639 1640 // Result is a load from the stack slot. 1641 if (SlotSize == DestSize) 1642 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, 1643 false, false, false, DestAlign); 1644 1645 assert(SlotSize < DestSize && "Unknown extension!"); 1646 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, 1647 PtrInfo, SlotVT, false, false, DestAlign); 1648} 1649 1650SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1651 DebugLoc dl = Node->getDebugLoc(); 1652 // Create a vector sized/aligned stack slot, store the value to element #0, 1653 // then load the whole vector back out. 1654 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1655 1656 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1657 int SPFI = StackPtrFI->getIndex(); 1658 1659 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1660 StackPtr, 1661 MachinePointerInfo::getFixedStack(SPFI), 1662 Node->getValueType(0).getVectorElementType(), 1663 false, false, 0); 1664 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1665 MachinePointerInfo::getFixedStack(SPFI), 1666 false, false, false, 0); 1667} 1668 1669 1670/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1671/// support the operation, but do support the resultant vector type. 1672SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1673 unsigned NumElems = Node->getNumOperands(); 1674 SDValue Value1, Value2; 1675 DebugLoc dl = Node->getDebugLoc(); 1676 EVT VT = Node->getValueType(0); 1677 EVT OpVT = Node->getOperand(0).getValueType(); 1678 EVT EltVT = VT.getVectorElementType(); 1679 1680 // If the only non-undef value is the low element, turn this into a 1681 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1682 bool isOnlyLowElement = true; 1683 bool MoreThanTwoValues = false; 1684 bool isConstant = true; 1685 for (unsigned i = 0; i < NumElems; ++i) { 1686 SDValue V = Node->getOperand(i); 1687 if (V.getOpcode() == ISD::UNDEF) 1688 continue; 1689 if (i > 0) 1690 isOnlyLowElement = false; 1691 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1692 isConstant = false; 1693 1694 if (!Value1.getNode()) { 1695 Value1 = V; 1696 } else if (!Value2.getNode()) { 1697 if (V != Value1) 1698 Value2 = V; 1699 } else if (V != Value1 && V != Value2) { 1700 MoreThanTwoValues = true; 1701 } 1702 } 1703 1704 if (!Value1.getNode()) 1705 return DAG.getUNDEF(VT); 1706 1707 if (isOnlyLowElement) 1708 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1709 1710 // If all elements are constants, create a load from the constant pool. 1711 if (isConstant) { 1712 SmallVector<Constant*, 16> CV; 1713 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1714 if (ConstantFPSDNode *V = 1715 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1716 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1717 } else if (ConstantSDNode *V = 1718 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1719 if (OpVT==EltVT) 1720 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1721 else { 1722 // If OpVT and EltVT don't match, EltVT is not legal and the 1723 // element values have been promoted/truncated earlier. Undo this; 1724 // we don't want a v16i8 to become a v16i32 for example. 1725 const ConstantInt *CI = V->getConstantIntValue(); 1726 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1727 CI->getZExtValue())); 1728 } 1729 } else { 1730 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1731 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1732 CV.push_back(UndefValue::get(OpNTy)); 1733 } 1734 } 1735 Constant *CP = ConstantVector::get(CV); 1736 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1737 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1738 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1739 MachinePointerInfo::getConstantPool(), 1740 false, false, false, Alignment); 1741 } 1742 1743 if (!MoreThanTwoValues) { 1744 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1745 for (unsigned i = 0; i < NumElems; ++i) { 1746 SDValue V = Node->getOperand(i); 1747 if (V.getOpcode() == ISD::UNDEF) 1748 continue; 1749 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1750 } 1751 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1752 // Get the splatted value into the low element of a vector register. 1753 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1754 SDValue Vec2; 1755 if (Value2.getNode()) 1756 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1757 else 1758 Vec2 = DAG.getUNDEF(VT); 1759 1760 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1761 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1762 } 1763 } 1764 1765 // Otherwise, we can't handle this case efficiently. 1766 return ExpandVectorBuildThroughStack(Node); 1767} 1768 1769// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1770// does not fit into a register, return the lo part and set the hi part to the 1771// by-reg argument. If it does fit into a single register, return the result 1772// and leave the Hi part unset. 1773SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1774 bool isSigned) { 1775 TargetLowering::ArgListTy Args; 1776 TargetLowering::ArgListEntry Entry; 1777 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1778 EVT ArgVT = Node->getOperand(i).getValueType(); 1779 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1780 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1781 Entry.isSExt = isSigned; 1782 Entry.isZExt = !isSigned; 1783 Args.push_back(Entry); 1784 } 1785 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1786 TLI.getPointerTy()); 1787 1788 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1789 1790 // By default, the input chain to this libcall is the entry node of the 1791 // function. If the libcall is going to be emitted as a tail call then 1792 // TLI.isUsedByReturnOnly will change it to the right chain if the return 1793 // node which is being folded has a non-entry input chain. 1794 SDValue InChain = DAG.getEntryNode(); 1795 1796 // isTailCall may be true since the callee does not reference caller stack 1797 // frame. Check if it's in the right position. 1798 SDValue TCChain = InChain; 1799 bool isTailCall = isInTailCallPosition(DAG, Node, TCChain, TLI); 1800 if (isTailCall) 1801 InChain = TCChain; 1802 1803 std::pair<SDValue, SDValue> CallInfo = 1804 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1805 0, TLI.getLibcallCallingConv(LC), isTailCall, 1806 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 1807 Callee, Args, DAG, Node->getDebugLoc()); 1808 1809 if (!CallInfo.second.getNode()) 1810 // It's a tailcall, return the chain (which is the DAG root). 1811 return DAG.getRoot(); 1812 1813 return CallInfo.first; 1814} 1815 1816/// ExpandLibCall - Generate a libcall taking the given operands as arguments 1817/// and returning a result of type RetVT. 1818SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, 1819 const SDValue *Ops, unsigned NumOps, 1820 bool isSigned, DebugLoc dl) { 1821 TargetLowering::ArgListTy Args; 1822 Args.reserve(NumOps); 1823 1824 TargetLowering::ArgListEntry Entry; 1825 for (unsigned i = 0; i != NumOps; ++i) { 1826 Entry.Node = Ops[i]; 1827 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); 1828 Entry.isSExt = isSigned; 1829 Entry.isZExt = !isSigned; 1830 Args.push_back(Entry); 1831 } 1832 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1833 TLI.getPointerTy()); 1834 1835 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 1836 std::pair<SDValue,SDValue> CallInfo = 1837 TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, 1838 false, 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 1839 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 1840 Callee, Args, DAG, dl); 1841 1842 return CallInfo.first; 1843} 1844 1845// ExpandChainLibCall - Expand a node into a call to a libcall. Similar to 1846// ExpandLibCall except that the first operand is the in-chain. 1847std::pair<SDValue, SDValue> 1848SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC, 1849 SDNode *Node, 1850 bool isSigned) { 1851 SDValue InChain = Node->getOperand(0); 1852 1853 TargetLowering::ArgListTy Args; 1854 TargetLowering::ArgListEntry Entry; 1855 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) { 1856 EVT ArgVT = Node->getOperand(i).getValueType(); 1857 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1858 Entry.Node = Node->getOperand(i); 1859 Entry.Ty = ArgTy; 1860 Entry.isSExt = isSigned; 1861 Entry.isZExt = !isSigned; 1862 Args.push_back(Entry); 1863 } 1864 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1865 TLI.getPointerTy()); 1866 1867 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1868 std::pair<SDValue, SDValue> CallInfo = 1869 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1870 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 1871 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 1872 Callee, Args, DAG, Node->getDebugLoc()); 1873 1874 return CallInfo; 1875} 1876 1877SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1878 RTLIB::Libcall Call_F32, 1879 RTLIB::Libcall Call_F64, 1880 RTLIB::Libcall Call_F80, 1881 RTLIB::Libcall Call_PPCF128) { 1882 RTLIB::Libcall LC; 1883 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1884 default: llvm_unreachable("Unexpected request for libcall!"); 1885 case MVT::f32: LC = Call_F32; break; 1886 case MVT::f64: LC = Call_F64; break; 1887 case MVT::f80: LC = Call_F80; break; 1888 case MVT::ppcf128: LC = Call_PPCF128; break; 1889 } 1890 return ExpandLibCall(LC, Node, false); 1891} 1892 1893SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 1894 RTLIB::Libcall Call_I8, 1895 RTLIB::Libcall Call_I16, 1896 RTLIB::Libcall Call_I32, 1897 RTLIB::Libcall Call_I64, 1898 RTLIB::Libcall Call_I128) { 1899 RTLIB::Libcall LC; 1900 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1901 default: llvm_unreachable("Unexpected request for libcall!"); 1902 case MVT::i8: LC = Call_I8; break; 1903 case MVT::i16: LC = Call_I16; break; 1904 case MVT::i32: LC = Call_I32; break; 1905 case MVT::i64: LC = Call_I64; break; 1906 case MVT::i128: LC = Call_I128; break; 1907 } 1908 return ExpandLibCall(LC, Node, isSigned); 1909} 1910 1911/// isDivRemLibcallAvailable - Return true if divmod libcall is available. 1912static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned, 1913 const TargetLowering &TLI) { 1914 RTLIB::Libcall LC; 1915 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1916 default: llvm_unreachable("Unexpected request for libcall!"); 1917 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; 1918 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; 1919 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; 1920 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; 1921 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break; 1922 } 1923 1924 return TLI.getLibcallName(LC) != 0; 1925} 1926 1927/// UseDivRem - Only issue divrem libcall if both quotient and remainder are 1928/// needed. 1929static bool UseDivRem(SDNode *Node, bool isSigned, bool isDIV) { 1930 unsigned OtherOpcode = 0; 1931 if (isSigned) 1932 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV; 1933 else 1934 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV; 1935 1936 SDValue Op0 = Node->getOperand(0); 1937 SDValue Op1 = Node->getOperand(1); 1938 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(), 1939 UE = Op0.getNode()->use_end(); UI != UE; ++UI) { 1940 SDNode *User = *UI; 1941 if (User == Node) 1942 continue; 1943 if (User->getOpcode() == OtherOpcode && 1944 User->getOperand(0) == Op0 && 1945 User->getOperand(1) == Op1) 1946 return true; 1947 } 1948 return false; 1949} 1950 1951/// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem 1952/// pairs. 1953void 1954SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node, 1955 SmallVectorImpl<SDValue> &Results) { 1956 unsigned Opcode = Node->getOpcode(); 1957 bool isSigned = Opcode == ISD::SDIVREM; 1958 1959 RTLIB::Libcall LC; 1960 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1961 default: llvm_unreachable("Unexpected request for libcall!"); 1962 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; 1963 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; 1964 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; 1965 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; 1966 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break; 1967 } 1968 1969 // The input chain to this libcall is the entry node of the function. 1970 // Legalizing the call will automatically add the previous call to the 1971 // dependence. 1972 SDValue InChain = DAG.getEntryNode(); 1973 1974 EVT RetVT = Node->getValueType(0); 1975 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 1976 1977 TargetLowering::ArgListTy Args; 1978 TargetLowering::ArgListEntry Entry; 1979 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1980 EVT ArgVT = Node->getOperand(i).getValueType(); 1981 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1982 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1983 Entry.isSExt = isSigned; 1984 Entry.isZExt = !isSigned; 1985 Args.push_back(Entry); 1986 } 1987 1988 // Also pass the return address of the remainder. 1989 SDValue FIPtr = DAG.CreateStackTemporary(RetVT); 1990 Entry.Node = FIPtr; 1991 Entry.Ty = RetTy->getPointerTo(); 1992 Entry.isSExt = isSigned; 1993 Entry.isZExt = !isSigned; 1994 Args.push_back(Entry); 1995 1996 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1997 TLI.getPointerTy()); 1998 1999 DebugLoc dl = Node->getDebugLoc(); 2000 std::pair<SDValue, SDValue> CallInfo = 2001 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 2002 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 2003 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2004 Callee, Args, DAG, dl); 2005 2006 // Remainder is loaded back from the stack frame. 2007 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, 2008 MachinePointerInfo(), false, false, false, 0); 2009 Results.push_back(CallInfo.first); 2010 Results.push_back(Rem); 2011} 2012 2013/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 2014/// INT_TO_FP operation of the specified operand when the target requests that 2015/// we expand it. At this point, we know that the result and operand types are 2016/// legal for the target. 2017SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 2018 SDValue Op0, 2019 EVT DestVT, 2020 DebugLoc dl) { 2021 if (Op0.getValueType() == MVT::i32) { 2022 // simple 32-bit [signed|unsigned] integer to float/double expansion 2023 2024 // Get the stack frame index of a 8 byte buffer. 2025 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 2026 2027 // word offset constant for Hi/Lo address computation 2028 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 2029 // set up Hi and Lo (into buffer) address based on endian 2030 SDValue Hi = StackSlot; 2031 SDValue Lo = DAG.getNode(ISD::ADD, dl, 2032 TLI.getPointerTy(), StackSlot, WordOff); 2033 if (TLI.isLittleEndian()) 2034 std::swap(Hi, Lo); 2035 2036 // if signed map to unsigned space 2037 SDValue Op0Mapped; 2038 if (isSigned) { 2039 // constant used to invert sign bit (signed to unsigned mapping) 2040 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 2041 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 2042 } else { 2043 Op0Mapped = Op0; 2044 } 2045 // store the lo of the constructed double - based on integer input 2046 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 2047 Op0Mapped, Lo, MachinePointerInfo(), 2048 false, false, 0); 2049 // initial hi portion of constructed double 2050 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2051 // store the hi of the constructed double - biased exponent 2052 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi, 2053 MachinePointerInfo(), 2054 false, false, 0); 2055 // load the constructed double 2056 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, 2057 MachinePointerInfo(), false, false, false, 0); 2058 // FP constant to bias correct the final result 2059 SDValue Bias = DAG.getConstantFP(isSigned ? 2060 BitsToDouble(0x4330000080000000ULL) : 2061 BitsToDouble(0x4330000000000000ULL), 2062 MVT::f64); 2063 // subtract the bias 2064 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2065 // final result 2066 SDValue Result; 2067 // handle final rounding 2068 if (DestVT == MVT::f64) { 2069 // do nothing 2070 Result = Sub; 2071 } else if (DestVT.bitsLT(MVT::f64)) { 2072 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2073 DAG.getIntPtrConstant(0)); 2074 } else if (DestVT.bitsGT(MVT::f64)) { 2075 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2076 } 2077 return Result; 2078 } 2079 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2080 // Code below here assumes !isSigned without checking again. 2081 2082 // Implementation of unsigned i64 to f64 following the algorithm in 2083 // __floatundidf in compiler_rt. This implementation has the advantage 2084 // of performing rounding correctly, both in the default rounding mode 2085 // and in all alternate rounding modes. 2086 // TODO: Generalize this for use with other types. 2087 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2088 SDValue TwoP52 = 2089 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2090 SDValue TwoP84PlusTwoP52 = 2091 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2092 SDValue TwoP84 = 2093 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2094 2095 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2096 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2097 DAG.getConstant(32, MVT::i64)); 2098 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2099 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2100 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr); 2101 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr); 2102 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, 2103 TwoP84PlusTwoP52); 2104 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2105 } 2106 2107 // Implementation of unsigned i64 to f32. 2108 // TODO: Generalize this for use with other types. 2109 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { 2110 // For unsigned conversions, convert them to signed conversions using the 2111 // algorithm from the x86_64 __floatundidf in compiler_rt. 2112 if (!isSigned) { 2113 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); 2114 2115 SDValue ShiftConst = 2116 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType())); 2117 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst); 2118 SDValue AndConst = DAG.getConstant(1, MVT::i64); 2119 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst); 2120 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr); 2121 2122 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or); 2123 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt); 2124 2125 // TODO: This really should be implemented using a branch rather than a 2126 // select. We happen to get lucky and machinesink does the right 2127 // thing most of the time. This would be a good candidate for a 2128 //pseudo-op, or, even better, for whole-function isel. 2129 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2130 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT); 2131 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast); 2132 } 2133 2134 // Otherwise, implement the fully general conversion. 2135 2136 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2137 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64)); 2138 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, 2139 DAG.getConstant(UINT64_C(0x800), MVT::i64)); 2140 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2141 DAG.getConstant(UINT64_C(0x7ff), MVT::i64)); 2142 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2143 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); 2144 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0); 2145 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2146 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64), 2147 ISD::SETUGE); 2148 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0); 2149 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType()); 2150 2151 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2152 DAG.getConstant(32, SHVT)); 2153 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); 2154 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); 2155 SDValue TwoP32 = 2156 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64); 2157 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); 2158 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); 2159 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); 2160 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); 2161 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, 2162 DAG.getIntPtrConstant(0)); 2163 } 2164 2165 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2166 2167 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2168 Op0, DAG.getConstant(0, Op0.getValueType()), 2169 ISD::SETLT); 2170 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2171 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2172 SignSet, Four, Zero); 2173 2174 // If the sign bit of the integer is set, the large number will be treated 2175 // as a negative number. To counteract this, the dynamic code adds an 2176 // offset depending on the data type. 2177 uint64_t FF; 2178 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2179 default: llvm_unreachable("Unsupported integer type!"); 2180 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2181 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2182 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2183 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2184 } 2185 if (TLI.isLittleEndian()) FF <<= 32; 2186 Constant *FudgeFactor = ConstantInt::get( 2187 Type::getInt64Ty(*DAG.getContext()), FF); 2188 2189 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2190 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2191 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2192 Alignment = std::min(Alignment, 4u); 2193 SDValue FudgeInReg; 2194 if (DestVT == MVT::f32) 2195 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2196 MachinePointerInfo::getConstantPool(), 2197 false, false, false, Alignment); 2198 else { 2199 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2200 DAG.getEntryNode(), CPIdx, 2201 MachinePointerInfo::getConstantPool(), 2202 MVT::f32, false, false, Alignment); 2203 HandleSDNode Handle(Load); 2204 LegalizeOp(Load.getNode()); 2205 FudgeInReg = Handle.getValue(); 2206 } 2207 2208 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2209} 2210 2211/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2212/// *INT_TO_FP operation of the specified operand when the target requests that 2213/// we promote it. At this point, we know that the result and operand types are 2214/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2215/// operation that takes a larger input. 2216SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2217 EVT DestVT, 2218 bool isSigned, 2219 DebugLoc dl) { 2220 // First step, figure out the appropriate *INT_TO_FP operation to use. 2221 EVT NewInTy = LegalOp.getValueType(); 2222 2223 unsigned OpToUse = 0; 2224 2225 // Scan for the appropriate larger type to use. 2226 while (1) { 2227 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2228 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2229 2230 // If the target supports SINT_TO_FP of this type, use it. 2231 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2232 OpToUse = ISD::SINT_TO_FP; 2233 break; 2234 } 2235 if (isSigned) continue; 2236 2237 // If the target supports UINT_TO_FP of this type, use it. 2238 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2239 OpToUse = ISD::UINT_TO_FP; 2240 break; 2241 } 2242 2243 // Otherwise, try a larger type. 2244 } 2245 2246 // Okay, we found the operation and type to use. Zero extend our input to the 2247 // desired type then run the operation on it. 2248 return DAG.getNode(OpToUse, dl, DestVT, 2249 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2250 dl, NewInTy, LegalOp)); 2251} 2252 2253/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2254/// FP_TO_*INT operation of the specified operand when the target requests that 2255/// we promote it. At this point, we know that the result and operand types are 2256/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2257/// operation that returns a larger result. 2258SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2259 EVT DestVT, 2260 bool isSigned, 2261 DebugLoc dl) { 2262 // First step, figure out the appropriate FP_TO*INT operation to use. 2263 EVT NewOutTy = DestVT; 2264 2265 unsigned OpToUse = 0; 2266 2267 // Scan for the appropriate larger type to use. 2268 while (1) { 2269 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2270 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2271 2272 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2273 OpToUse = ISD::FP_TO_SINT; 2274 break; 2275 } 2276 2277 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2278 OpToUse = ISD::FP_TO_UINT; 2279 break; 2280 } 2281 2282 // Otherwise, try a larger type. 2283 } 2284 2285 2286 // Okay, we found the operation and type to use. 2287 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2288 2289 // Truncate the result of the extended FP_TO_*INT operation to the desired 2290 // size. 2291 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2292} 2293 2294/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2295/// 2296SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2297 EVT VT = Op.getValueType(); 2298 EVT SHVT = TLI.getShiftAmountTy(VT); 2299 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2300 switch (VT.getSimpleVT().SimpleTy) { 2301 default: llvm_unreachable("Unhandled Expand type in BSWAP!"); 2302 case MVT::i16: 2303 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2304 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2305 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2306 case MVT::i32: 2307 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2308 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2309 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2310 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2311 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2312 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2313 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2314 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2315 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2316 case MVT::i64: 2317 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2318 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2319 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2320 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2321 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2322 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2323 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2324 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2325 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2326 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2327 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2328 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2329 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2330 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2331 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2332 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2333 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2334 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2335 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2336 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2337 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2338 } 2339} 2340 2341/// SplatByte - Distribute ByteVal over NumBits bits. 2342// FIXME: Move this helper to a common place. 2343static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) { 2344 APInt Val = APInt(NumBits, ByteVal); 2345 unsigned Shift = 8; 2346 for (unsigned i = NumBits; i > 8; i >>= 1) { 2347 Val = (Val << Shift) | Val; 2348 Shift <<= 1; 2349 } 2350 return Val; 2351} 2352 2353/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2354/// 2355SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2356 DebugLoc dl) { 2357 switch (Opc) { 2358 default: llvm_unreachable("Cannot expand this yet!"); 2359 case ISD::CTPOP: { 2360 EVT VT = Op.getValueType(); 2361 EVT ShVT = TLI.getShiftAmountTy(VT); 2362 unsigned Len = VT.getSizeInBits(); 2363 2364 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 && 2365 "CTPOP not implemented for this type."); 2366 2367 // This is the "best" algorithm from 2368 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel 2369 2370 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT); 2371 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT); 2372 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT); 2373 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT); 2374 2375 // v = v - ((v >> 1) & 0x55555555...) 2376 Op = DAG.getNode(ISD::SUB, dl, VT, Op, 2377 DAG.getNode(ISD::AND, dl, VT, 2378 DAG.getNode(ISD::SRL, dl, VT, Op, 2379 DAG.getConstant(1, ShVT)), 2380 Mask55)); 2381 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...) 2382 Op = DAG.getNode(ISD::ADD, dl, VT, 2383 DAG.getNode(ISD::AND, dl, VT, Op, Mask33), 2384 DAG.getNode(ISD::AND, dl, VT, 2385 DAG.getNode(ISD::SRL, dl, VT, Op, 2386 DAG.getConstant(2, ShVT)), 2387 Mask33)); 2388 // v = (v + (v >> 4)) & 0x0F0F0F0F... 2389 Op = DAG.getNode(ISD::AND, dl, VT, 2390 DAG.getNode(ISD::ADD, dl, VT, Op, 2391 DAG.getNode(ISD::SRL, dl, VT, Op, 2392 DAG.getConstant(4, ShVT))), 2393 Mask0F); 2394 // v = (v * 0x01010101...) >> (Len - 8) 2395 Op = DAG.getNode(ISD::SRL, dl, VT, 2396 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01), 2397 DAG.getConstant(Len - 8, ShVT)); 2398 2399 return Op; 2400 } 2401 case ISD::CTLZ_ZERO_UNDEF: 2402 // This trivially expands to CTLZ. 2403 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op); 2404 case ISD::CTLZ: { 2405 // for now, we do this: 2406 // x = x | (x >> 1); 2407 // x = x | (x >> 2); 2408 // ... 2409 // x = x | (x >>16); 2410 // x = x | (x >>32); // for 64-bit input 2411 // return popcount(~x); 2412 // 2413 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2414 EVT VT = Op.getValueType(); 2415 EVT ShVT = TLI.getShiftAmountTy(VT); 2416 unsigned len = VT.getSizeInBits(); 2417 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2418 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2419 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2420 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2421 } 2422 Op = DAG.getNOT(dl, Op, VT); 2423 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2424 } 2425 case ISD::CTTZ_ZERO_UNDEF: 2426 // This trivially expands to CTTZ. 2427 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op); 2428 case ISD::CTTZ: { 2429 // for now, we use: { return popcount(~x & (x - 1)); } 2430 // unless the target has ctlz but not ctpop, in which case we use: 2431 // { return 32 - nlz(~x & (x-1)); } 2432 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2433 EVT VT = Op.getValueType(); 2434 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2435 DAG.getNOT(dl, Op, VT), 2436 DAG.getNode(ISD::SUB, dl, VT, Op, 2437 DAG.getConstant(1, VT))); 2438 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2439 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2440 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2441 return DAG.getNode(ISD::SUB, dl, VT, 2442 DAG.getConstant(VT.getSizeInBits(), VT), 2443 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2444 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2445 } 2446 } 2447} 2448 2449std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) { 2450 unsigned Opc = Node->getOpcode(); 2451 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 2452 RTLIB::Libcall LC; 2453 2454 switch (Opc) { 2455 default: 2456 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 2457 case ISD::ATOMIC_SWAP: 2458 switch (VT.SimpleTy) { 2459 default: llvm_unreachable("Unexpected value type for atomic!"); 2460 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 2461 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 2462 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 2463 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 2464 } 2465 break; 2466 case ISD::ATOMIC_CMP_SWAP: 2467 switch (VT.SimpleTy) { 2468 default: llvm_unreachable("Unexpected value type for atomic!"); 2469 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 2470 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 2471 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 2472 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 2473 } 2474 break; 2475 case ISD::ATOMIC_LOAD_ADD: 2476 switch (VT.SimpleTy) { 2477 default: llvm_unreachable("Unexpected value type for atomic!"); 2478 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 2479 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 2480 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 2481 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 2482 } 2483 break; 2484 case ISD::ATOMIC_LOAD_SUB: 2485 switch (VT.SimpleTy) { 2486 default: llvm_unreachable("Unexpected value type for atomic!"); 2487 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 2488 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 2489 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 2490 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 2491 } 2492 break; 2493 case ISD::ATOMIC_LOAD_AND: 2494 switch (VT.SimpleTy) { 2495 default: llvm_unreachable("Unexpected value type for atomic!"); 2496 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 2497 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 2498 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 2499 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 2500 } 2501 break; 2502 case ISD::ATOMIC_LOAD_OR: 2503 switch (VT.SimpleTy) { 2504 default: llvm_unreachable("Unexpected value type for atomic!"); 2505 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 2506 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 2507 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 2508 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 2509 } 2510 break; 2511 case ISD::ATOMIC_LOAD_XOR: 2512 switch (VT.SimpleTy) { 2513 default: llvm_unreachable("Unexpected value type for atomic!"); 2514 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 2515 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 2516 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 2517 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 2518 } 2519 break; 2520 case ISD::ATOMIC_LOAD_NAND: 2521 switch (VT.SimpleTy) { 2522 default: llvm_unreachable("Unexpected value type for atomic!"); 2523 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 2524 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 2525 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 2526 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 2527 } 2528 break; 2529 } 2530 2531 return ExpandChainLibCall(LC, Node, false); 2532} 2533 2534void SelectionDAGLegalize::ExpandNode(SDNode *Node) { 2535 SmallVector<SDValue, 8> Results; 2536 DebugLoc dl = Node->getDebugLoc(); 2537 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2538 switch (Node->getOpcode()) { 2539 case ISD::CTPOP: 2540 case ISD::CTLZ: 2541 case ISD::CTLZ_ZERO_UNDEF: 2542 case ISD::CTTZ: 2543 case ISD::CTTZ_ZERO_UNDEF: 2544 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2545 Results.push_back(Tmp1); 2546 break; 2547 case ISD::BSWAP: 2548 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2549 break; 2550 case ISD::FRAMEADDR: 2551 case ISD::RETURNADDR: 2552 case ISD::FRAME_TO_ARGS_OFFSET: 2553 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2554 break; 2555 case ISD::FLT_ROUNDS_: 2556 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2557 break; 2558 case ISD::EH_RETURN: 2559 case ISD::EH_LABEL: 2560 case ISD::PREFETCH: 2561 case ISD::VAEND: 2562 case ISD::EH_SJLJ_LONGJMP: 2563 // If the target didn't expand these, there's nothing to do, so just 2564 // preserve the chain and be done. 2565 Results.push_back(Node->getOperand(0)); 2566 break; 2567 case ISD::EH_SJLJ_SETJMP: 2568 // If the target didn't expand this, just return 'zero' and preserve the 2569 // chain. 2570 Results.push_back(DAG.getConstant(0, MVT::i32)); 2571 Results.push_back(Node->getOperand(0)); 2572 break; 2573 case ISD::ATOMIC_FENCE: 2574 case ISD::MEMBARRIER: { 2575 // If the target didn't lower this, lower it to '__sync_synchronize()' call 2576 // FIXME: handle "fence singlethread" more efficiently. 2577 TargetLowering::ArgListTy Args; 2578 std::pair<SDValue, SDValue> CallResult = 2579 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2580 false, false, false, false, 0, CallingConv::C, 2581 /*isTailCall=*/false, 2582 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2583 DAG.getExternalSymbol("__sync_synchronize", 2584 TLI.getPointerTy()), 2585 Args, DAG, dl); 2586 Results.push_back(CallResult.second); 2587 break; 2588 } 2589 case ISD::ATOMIC_LOAD: { 2590 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP. 2591 SDValue Zero = DAG.getConstant(0, Node->getValueType(0)); 2592 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 2593 cast<AtomicSDNode>(Node)->getMemoryVT(), 2594 Node->getOperand(0), 2595 Node->getOperand(1), Zero, Zero, 2596 cast<AtomicSDNode>(Node)->getMemOperand(), 2597 cast<AtomicSDNode>(Node)->getOrdering(), 2598 cast<AtomicSDNode>(Node)->getSynchScope()); 2599 Results.push_back(Swap.getValue(0)); 2600 Results.push_back(Swap.getValue(1)); 2601 break; 2602 } 2603 case ISD::ATOMIC_STORE: { 2604 // There is no libcall for atomic store; fake it with ATOMIC_SWAP. 2605 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 2606 cast<AtomicSDNode>(Node)->getMemoryVT(), 2607 Node->getOperand(0), 2608 Node->getOperand(1), Node->getOperand(2), 2609 cast<AtomicSDNode>(Node)->getMemOperand(), 2610 cast<AtomicSDNode>(Node)->getOrdering(), 2611 cast<AtomicSDNode>(Node)->getSynchScope()); 2612 Results.push_back(Swap.getValue(1)); 2613 break; 2614 } 2615 // By default, atomic intrinsics are marked Legal and lowered. Targets 2616 // which don't support them directly, however, may want libcalls, in which 2617 // case they mark them Expand, and we get here. 2618 case ISD::ATOMIC_SWAP: 2619 case ISD::ATOMIC_LOAD_ADD: 2620 case ISD::ATOMIC_LOAD_SUB: 2621 case ISD::ATOMIC_LOAD_AND: 2622 case ISD::ATOMIC_LOAD_OR: 2623 case ISD::ATOMIC_LOAD_XOR: 2624 case ISD::ATOMIC_LOAD_NAND: 2625 case ISD::ATOMIC_LOAD_MIN: 2626 case ISD::ATOMIC_LOAD_MAX: 2627 case ISD::ATOMIC_LOAD_UMIN: 2628 case ISD::ATOMIC_LOAD_UMAX: 2629 case ISD::ATOMIC_CMP_SWAP: { 2630 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node); 2631 Results.push_back(Tmp.first); 2632 Results.push_back(Tmp.second); 2633 break; 2634 } 2635 case ISD::DYNAMIC_STACKALLOC: 2636 ExpandDYNAMIC_STACKALLOC(Node, Results); 2637 break; 2638 case ISD::MERGE_VALUES: 2639 for (unsigned i = 0; i < Node->getNumValues(); i++) 2640 Results.push_back(Node->getOperand(i)); 2641 break; 2642 case ISD::UNDEF: { 2643 EVT VT = Node->getValueType(0); 2644 if (VT.isInteger()) 2645 Results.push_back(DAG.getConstant(0, VT)); 2646 else { 2647 assert(VT.isFloatingPoint() && "Unknown value type!"); 2648 Results.push_back(DAG.getConstantFP(0, VT)); 2649 } 2650 break; 2651 } 2652 case ISD::TRAP: { 2653 // If this operation is not supported, lower it to 'abort()' call 2654 TargetLowering::ArgListTy Args; 2655 std::pair<SDValue, SDValue> CallResult = 2656 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2657 false, false, false, false, 0, CallingConv::C, 2658 /*isTailCall=*/false, 2659 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2660 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2661 Args, DAG, dl); 2662 Results.push_back(CallResult.second); 2663 break; 2664 } 2665 case ISD::FP_ROUND: 2666 case ISD::BITCAST: 2667 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2668 Node->getValueType(0), dl); 2669 Results.push_back(Tmp1); 2670 break; 2671 case ISD::FP_EXTEND: 2672 Tmp1 = EmitStackConvert(Node->getOperand(0), 2673 Node->getOperand(0).getValueType(), 2674 Node->getValueType(0), dl); 2675 Results.push_back(Tmp1); 2676 break; 2677 case ISD::SIGN_EXTEND_INREG: { 2678 // NOTE: we could fall back on load/store here too for targets without 2679 // SAR. However, it is doubtful that any exist. 2680 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2681 EVT VT = Node->getValueType(0); 2682 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT); 2683 if (VT.isVector()) 2684 ShiftAmountTy = VT; 2685 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2686 ExtraVT.getScalarType().getSizeInBits(); 2687 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2688 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2689 Node->getOperand(0), ShiftCst); 2690 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2691 Results.push_back(Tmp1); 2692 break; 2693 } 2694 case ISD::FP_ROUND_INREG: { 2695 // The only way we can lower this is to turn it into a TRUNCSTORE, 2696 // EXTLOAD pair, targeting a temporary location (a stack slot). 2697 2698 // NOTE: there is a choice here between constantly creating new stack 2699 // slots and always reusing the same one. We currently always create 2700 // new ones, as reuse may inhibit scheduling. 2701 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2702 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2703 Node->getValueType(0), dl); 2704 Results.push_back(Tmp1); 2705 break; 2706 } 2707 case ISD::SINT_TO_FP: 2708 case ISD::UINT_TO_FP: 2709 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2710 Node->getOperand(0), Node->getValueType(0), dl); 2711 Results.push_back(Tmp1); 2712 break; 2713 case ISD::FP_TO_UINT: { 2714 SDValue True, False; 2715 EVT VT = Node->getOperand(0).getValueType(); 2716 EVT NVT = Node->getValueType(0); 2717 APFloat apf(APInt::getNullValue(VT.getSizeInBits())); 2718 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2719 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2720 Tmp1 = DAG.getConstantFP(apf, VT); 2721 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2722 Node->getOperand(0), 2723 Tmp1, ISD::SETLT); 2724 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2725 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2726 DAG.getNode(ISD::FSUB, dl, VT, 2727 Node->getOperand(0), Tmp1)); 2728 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2729 DAG.getConstant(x, NVT)); 2730 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2731 Results.push_back(Tmp1); 2732 break; 2733 } 2734 case ISD::VAARG: { 2735 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2736 EVT VT = Node->getValueType(0); 2737 Tmp1 = Node->getOperand(0); 2738 Tmp2 = Node->getOperand(1); 2739 unsigned Align = Node->getConstantOperandVal(3); 2740 2741 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, 2742 MachinePointerInfo(V), 2743 false, false, false, 0); 2744 SDValue VAList = VAListLoad; 2745 2746 if (Align > TLI.getMinStackArgumentAlignment()) { 2747 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2748 2749 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2750 DAG.getConstant(Align - 1, 2751 TLI.getPointerTy())); 2752 2753 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList, 2754 DAG.getConstant(-(int64_t)Align, 2755 TLI.getPointerTy())); 2756 } 2757 2758 // Increment the pointer, VAList, to the next vaarg 2759 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2760 DAG.getConstant(TLI.getTargetData()-> 2761 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2762 TLI.getPointerTy())); 2763 // Store the incremented VAList to the legalized pointer 2764 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, 2765 MachinePointerInfo(V), false, false, 0); 2766 // Load the actual argument out of the pointer VAList 2767 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(), 2768 false, false, false, 0)); 2769 Results.push_back(Results[0].getValue(1)); 2770 break; 2771 } 2772 case ISD::VACOPY: { 2773 // This defaults to loading a pointer from the input and storing it to the 2774 // output, returning the chain. 2775 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2776 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2777 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2778 Node->getOperand(2), MachinePointerInfo(VS), 2779 false, false, false, 0); 2780 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), 2781 MachinePointerInfo(VD), false, false, 0); 2782 Results.push_back(Tmp1); 2783 break; 2784 } 2785 case ISD::EXTRACT_VECTOR_ELT: 2786 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2787 // This must be an access of the only element. Return it. 2788 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), 2789 Node->getOperand(0)); 2790 else 2791 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2792 Results.push_back(Tmp1); 2793 break; 2794 case ISD::EXTRACT_SUBVECTOR: 2795 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2796 break; 2797 case ISD::INSERT_SUBVECTOR: 2798 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0))); 2799 break; 2800 case ISD::CONCAT_VECTORS: { 2801 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2802 break; 2803 } 2804 case ISD::SCALAR_TO_VECTOR: 2805 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2806 break; 2807 case ISD::INSERT_VECTOR_ELT: 2808 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2809 Node->getOperand(1), 2810 Node->getOperand(2), dl)); 2811 break; 2812 case ISD::VECTOR_SHUFFLE: { 2813 SmallVector<int, 32> NewMask; 2814 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask(); 2815 2816 EVT VT = Node->getValueType(0); 2817 EVT EltVT = VT.getVectorElementType(); 2818 SDValue Op0 = Node->getOperand(0); 2819 SDValue Op1 = Node->getOperand(1); 2820 if (!TLI.isTypeLegal(EltVT)) { 2821 2822 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT); 2823 2824 // BUILD_VECTOR operands are allowed to be wider than the element type. 2825 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it 2826 if (NewEltVT.bitsLT(EltVT)) { 2827 2828 // Convert shuffle node. 2829 // If original node was v4i64 and the new EltVT is i32, 2830 // cast operands to v8i32 and re-build the mask. 2831 2832 // Calculate new VT, the size of the new VT should be equal to original. 2833 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT, 2834 VT.getSizeInBits()/NewEltVT.getSizeInBits()); 2835 assert(NewVT.bitsEq(VT)); 2836 2837 // cast operands to new VT 2838 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); 2839 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); 2840 2841 // Convert the shuffle mask 2842 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements(); 2843 2844 // EltVT gets smaller 2845 assert(factor > 0); 2846 2847 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) { 2848 if (Mask[i] < 0) { 2849 for (unsigned fi = 0; fi < factor; ++fi) 2850 NewMask.push_back(Mask[i]); 2851 } 2852 else { 2853 for (unsigned fi = 0; fi < factor; ++fi) 2854 NewMask.push_back(Mask[i]*factor+fi); 2855 } 2856 } 2857 Mask = NewMask; 2858 VT = NewVT; 2859 } 2860 EltVT = NewEltVT; 2861 } 2862 unsigned NumElems = VT.getVectorNumElements(); 2863 SmallVector<SDValue, 16> Ops; 2864 for (unsigned i = 0; i != NumElems; ++i) { 2865 if (Mask[i] < 0) { 2866 Ops.push_back(DAG.getUNDEF(EltVT)); 2867 continue; 2868 } 2869 unsigned Idx = Mask[i]; 2870 if (Idx < NumElems) 2871 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2872 Op0, 2873 DAG.getIntPtrConstant(Idx))); 2874 else 2875 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2876 Op1, 2877 DAG.getIntPtrConstant(Idx - NumElems))); 2878 } 2879 2880 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2881 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type. 2882 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1); 2883 Results.push_back(Tmp1); 2884 break; 2885 } 2886 case ISD::EXTRACT_ELEMENT: { 2887 EVT OpTy = Node->getOperand(0).getValueType(); 2888 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2889 // 1 -> Hi 2890 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2891 DAG.getConstant(OpTy.getSizeInBits()/2, 2892 TLI.getShiftAmountTy(Node->getOperand(0).getValueType()))); 2893 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2894 } else { 2895 // 0 -> Lo 2896 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2897 Node->getOperand(0)); 2898 } 2899 Results.push_back(Tmp1); 2900 break; 2901 } 2902 case ISD::STACKSAVE: 2903 // Expand to CopyFromReg if the target set 2904 // StackPointerRegisterToSaveRestore. 2905 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2906 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2907 Node->getValueType(0))); 2908 Results.push_back(Results[0].getValue(1)); 2909 } else { 2910 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2911 Results.push_back(Node->getOperand(0)); 2912 } 2913 break; 2914 case ISD::STACKRESTORE: 2915 // Expand to CopyToReg if the target set 2916 // StackPointerRegisterToSaveRestore. 2917 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2918 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2919 Node->getOperand(1))); 2920 } else { 2921 Results.push_back(Node->getOperand(0)); 2922 } 2923 break; 2924 case ISD::FCOPYSIGN: 2925 Results.push_back(ExpandFCOPYSIGN(Node)); 2926 break; 2927 case ISD::FNEG: 2928 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2929 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2930 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2931 Node->getOperand(0)); 2932 Results.push_back(Tmp1); 2933 break; 2934 case ISD::FABS: { 2935 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2936 EVT VT = Node->getValueType(0); 2937 Tmp1 = Node->getOperand(0); 2938 Tmp2 = DAG.getConstantFP(0.0, VT); 2939 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2940 Tmp1, Tmp2, ISD::SETUGT); 2941 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2942 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2943 Results.push_back(Tmp1); 2944 break; 2945 } 2946 case ISD::FSQRT: 2947 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2948 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2949 break; 2950 case ISD::FSIN: 2951 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2952 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2953 break; 2954 case ISD::FCOS: 2955 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2956 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2957 break; 2958 case ISD::FLOG: 2959 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2960 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2961 break; 2962 case ISD::FLOG2: 2963 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2964 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2965 break; 2966 case ISD::FLOG10: 2967 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2968 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2969 break; 2970 case ISD::FEXP: 2971 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2972 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2973 break; 2974 case ISD::FEXP2: 2975 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2976 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2977 break; 2978 case ISD::FTRUNC: 2979 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2980 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2981 break; 2982 case ISD::FFLOOR: 2983 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2984 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2985 break; 2986 case ISD::FCEIL: 2987 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2988 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2989 break; 2990 case ISD::FRINT: 2991 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2992 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2993 break; 2994 case ISD::FNEARBYINT: 2995 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2996 RTLIB::NEARBYINT_F64, 2997 RTLIB::NEARBYINT_F80, 2998 RTLIB::NEARBYINT_PPCF128)); 2999 break; 3000 case ISD::FPOWI: 3001 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 3002 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 3003 break; 3004 case ISD::FPOW: 3005 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 3006 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 3007 break; 3008 case ISD::FDIV: 3009 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 3010 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 3011 break; 3012 case ISD::FREM: 3013 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 3014 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 3015 break; 3016 case ISD::FMA: 3017 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64, 3018 RTLIB::FMA_F80, RTLIB::FMA_PPCF128)); 3019 break; 3020 case ISD::FP16_TO_FP32: 3021 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 3022 break; 3023 case ISD::FP32_TO_FP16: 3024 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 3025 break; 3026 case ISD::ConstantFP: { 3027 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 3028 // Check to see if this FP immediate is already legal. 3029 // If this is a legal constant, turn it into a TargetConstantFP node. 3030 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 3031 Results.push_back(ExpandConstantFP(CFP, true)); 3032 break; 3033 } 3034 case ISD::EHSELECTION: { 3035 unsigned Reg = TLI.getExceptionSelectorRegister(); 3036 assert(Reg && "Can't expand to unknown register!"); 3037 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 3038 Node->getValueType(0))); 3039 Results.push_back(Results[0].getValue(1)); 3040 break; 3041 } 3042 case ISD::EXCEPTIONADDR: { 3043 unsigned Reg = TLI.getExceptionPointerRegister(); 3044 assert(Reg && "Can't expand to unknown register!"); 3045 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 3046 Node->getValueType(0))); 3047 Results.push_back(Results[0].getValue(1)); 3048 break; 3049 } 3050 case ISD::FSUB: { 3051 EVT VT = Node->getValueType(0); 3052 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) && 3053 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) && 3054 "Don't know how to expand this FP subtraction!"); 3055 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1)); 3056 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1); 3057 Results.push_back(Tmp1); 3058 break; 3059 } 3060 case ISD::SUB: { 3061 EVT VT = Node->getValueType(0); 3062 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 3063 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 3064 "Don't know how to expand this subtraction!"); 3065 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 3066 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 3067 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 3068 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 3069 break; 3070 } 3071 case ISD::UREM: 3072 case ISD::SREM: { 3073 EVT VT = Node->getValueType(0); 3074 SDVTList VTs = DAG.getVTList(VT, VT); 3075 bool isSigned = Node->getOpcode() == ISD::SREM; 3076 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 3077 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 3078 Tmp2 = Node->getOperand(0); 3079 Tmp3 = Node->getOperand(1); 3080 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) || 3081 (isDivRemLibcallAvailable(Node, isSigned, TLI) && 3082 UseDivRem(Node, isSigned, false))) { 3083 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 3084 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 3085 // X % Y -> X-X/Y*Y 3086 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 3087 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 3088 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 3089 } else if (isSigned) 3090 Tmp1 = ExpandIntLibCall(Node, true, 3091 RTLIB::SREM_I8, 3092 RTLIB::SREM_I16, RTLIB::SREM_I32, 3093 RTLIB::SREM_I64, RTLIB::SREM_I128); 3094 else 3095 Tmp1 = ExpandIntLibCall(Node, false, 3096 RTLIB::UREM_I8, 3097 RTLIB::UREM_I16, RTLIB::UREM_I32, 3098 RTLIB::UREM_I64, RTLIB::UREM_I128); 3099 Results.push_back(Tmp1); 3100 break; 3101 } 3102 case ISD::UDIV: 3103 case ISD::SDIV: { 3104 bool isSigned = Node->getOpcode() == ISD::SDIV; 3105 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 3106 EVT VT = Node->getValueType(0); 3107 SDVTList VTs = DAG.getVTList(VT, VT); 3108 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) || 3109 (isDivRemLibcallAvailable(Node, isSigned, TLI) && 3110 UseDivRem(Node, isSigned, true))) 3111 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 3112 Node->getOperand(1)); 3113 else if (isSigned) 3114 Tmp1 = ExpandIntLibCall(Node, true, 3115 RTLIB::SDIV_I8, 3116 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 3117 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 3118 else 3119 Tmp1 = ExpandIntLibCall(Node, false, 3120 RTLIB::UDIV_I8, 3121 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 3122 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 3123 Results.push_back(Tmp1); 3124 break; 3125 } 3126 case ISD::MULHU: 3127 case ISD::MULHS: { 3128 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 3129 ISD::SMUL_LOHI; 3130 EVT VT = Node->getValueType(0); 3131 SDVTList VTs = DAG.getVTList(VT, VT); 3132 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 3133 "If this wasn't legal, it shouldn't have been created!"); 3134 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 3135 Node->getOperand(1)); 3136 Results.push_back(Tmp1.getValue(1)); 3137 break; 3138 } 3139 case ISD::SDIVREM: 3140 case ISD::UDIVREM: 3141 // Expand into divrem libcall 3142 ExpandDivRemLibCall(Node, Results); 3143 break; 3144 case ISD::MUL: { 3145 EVT VT = Node->getValueType(0); 3146 SDVTList VTs = DAG.getVTList(VT, VT); 3147 // See if multiply or divide can be lowered using two-result operations. 3148 // We just need the low half of the multiply; try both the signed 3149 // and unsigned forms. If the target supports both SMUL_LOHI and 3150 // UMUL_LOHI, form a preference by checking which forms of plain 3151 // MULH it supports. 3152 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 3153 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 3154 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 3155 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 3156 unsigned OpToUse = 0; 3157 if (HasSMUL_LOHI && !HasMULHS) { 3158 OpToUse = ISD::SMUL_LOHI; 3159 } else if (HasUMUL_LOHI && !HasMULHU) { 3160 OpToUse = ISD::UMUL_LOHI; 3161 } else if (HasSMUL_LOHI) { 3162 OpToUse = ISD::SMUL_LOHI; 3163 } else if (HasUMUL_LOHI) { 3164 OpToUse = ISD::UMUL_LOHI; 3165 } 3166 if (OpToUse) { 3167 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 3168 Node->getOperand(1))); 3169 break; 3170 } 3171 Tmp1 = ExpandIntLibCall(Node, false, 3172 RTLIB::MUL_I8, 3173 RTLIB::MUL_I16, RTLIB::MUL_I32, 3174 RTLIB::MUL_I64, RTLIB::MUL_I128); 3175 Results.push_back(Tmp1); 3176 break; 3177 } 3178 case ISD::SADDO: 3179 case ISD::SSUBO: { 3180 SDValue LHS = Node->getOperand(0); 3181 SDValue RHS = Node->getOperand(1); 3182 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 3183 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3184 LHS, RHS); 3185 Results.push_back(Sum); 3186 EVT OType = Node->getValueType(1); 3187 3188 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 3189 3190 // LHSSign -> LHS >= 0 3191 // RHSSign -> RHS >= 0 3192 // SumSign -> Sum >= 0 3193 // 3194 // Add: 3195 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 3196 // Sub: 3197 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 3198 // 3199 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 3200 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 3201 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 3202 Node->getOpcode() == ISD::SADDO ? 3203 ISD::SETEQ : ISD::SETNE); 3204 3205 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 3206 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 3207 3208 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 3209 Results.push_back(Cmp); 3210 break; 3211 } 3212 case ISD::UADDO: 3213 case ISD::USUBO: { 3214 SDValue LHS = Node->getOperand(0); 3215 SDValue RHS = Node->getOperand(1); 3216 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 3217 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3218 LHS, RHS); 3219 Results.push_back(Sum); 3220 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 3221 Node->getOpcode () == ISD::UADDO ? 3222 ISD::SETULT : ISD::SETUGT)); 3223 break; 3224 } 3225 case ISD::UMULO: 3226 case ISD::SMULO: { 3227 EVT VT = Node->getValueType(0); 3228 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 3229 SDValue LHS = Node->getOperand(0); 3230 SDValue RHS = Node->getOperand(1); 3231 SDValue BottomHalf; 3232 SDValue TopHalf; 3233 static const unsigned Ops[2][3] = 3234 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 3235 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 3236 bool isSigned = Node->getOpcode() == ISD::SMULO; 3237 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 3238 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 3239 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 3240 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 3241 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 3242 RHS); 3243 TopHalf = BottomHalf.getValue(1); 3244 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), 3245 VT.getSizeInBits() * 2))) { 3246 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 3247 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 3248 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 3249 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3250 DAG.getIntPtrConstant(0)); 3251 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3252 DAG.getIntPtrConstant(1)); 3253 } else { 3254 // We can fall back to a libcall with an illegal type for the MUL if we 3255 // have a libcall big enough. 3256 // Also, we can fall back to a division in some cases, but that's a big 3257 // performance hit in the general case. 3258 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3259 if (WideVT == MVT::i16) 3260 LC = RTLIB::MUL_I16; 3261 else if (WideVT == MVT::i32) 3262 LC = RTLIB::MUL_I32; 3263 else if (WideVT == MVT::i64) 3264 LC = RTLIB::MUL_I64; 3265 else if (WideVT == MVT::i128) 3266 LC = RTLIB::MUL_I128; 3267 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!"); 3268 3269 // The high part is obtained by SRA'ing all but one of the bits of low 3270 // part. 3271 unsigned LoSize = VT.getSizeInBits(); 3272 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS, 3273 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 3274 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS, 3275 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 3276 3277 // Here we're passing the 2 arguments explicitly as 4 arguments that are 3278 // pre-lowered to the correct types. This all depends upon WideVT not 3279 // being a legal type for the architecture and thus has to be split to 3280 // two arguments. 3281 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS }; 3282 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl); 3283 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret, 3284 DAG.getIntPtrConstant(0)); 3285 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret, 3286 DAG.getIntPtrConstant(1)); 3287 // Ret is a node with an illegal type. Because such things are not 3288 // generally permitted during this phase of legalization, delete the 3289 // node. The above EXTRACT_ELEMENT nodes should have been folded. 3290 DAG.DeleteNode(Ret.getNode()); 3291 } 3292 3293 if (isSigned) { 3294 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, 3295 TLI.getShiftAmountTy(BottomHalf.getValueType())); 3296 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 3297 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 3298 ISD::SETNE); 3299 } else { 3300 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 3301 DAG.getConstant(0, VT), ISD::SETNE); 3302 } 3303 Results.push_back(BottomHalf); 3304 Results.push_back(TopHalf); 3305 break; 3306 } 3307 case ISD::BUILD_PAIR: { 3308 EVT PairTy = Node->getValueType(0); 3309 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 3310 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 3311 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 3312 DAG.getConstant(PairTy.getSizeInBits()/2, 3313 TLI.getShiftAmountTy(PairTy))); 3314 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 3315 break; 3316 } 3317 case ISD::SELECT: 3318 Tmp1 = Node->getOperand(0); 3319 Tmp2 = Node->getOperand(1); 3320 Tmp3 = Node->getOperand(2); 3321 if (Tmp1.getOpcode() == ISD::SETCC) { 3322 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 3323 Tmp2, Tmp3, 3324 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 3325 } else { 3326 Tmp1 = DAG.getSelectCC(dl, Tmp1, 3327 DAG.getConstant(0, Tmp1.getValueType()), 3328 Tmp2, Tmp3, ISD::SETNE); 3329 } 3330 Results.push_back(Tmp1); 3331 break; 3332 case ISD::BR_JT: { 3333 SDValue Chain = Node->getOperand(0); 3334 SDValue Table = Node->getOperand(1); 3335 SDValue Index = Node->getOperand(2); 3336 3337 EVT PTy = TLI.getPointerTy(); 3338 3339 const TargetData &TD = *TLI.getTargetData(); 3340 unsigned EntrySize = 3341 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 3342 3343 Index = DAG.getNode(ISD::MUL, dl, PTy, 3344 Index, DAG.getConstant(EntrySize, PTy)); 3345 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 3346 3347 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 3348 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 3349 MachinePointerInfo::getJumpTable(), MemVT, 3350 false, false, 0); 3351 Addr = LD; 3352 if (TM.getRelocationModel() == Reloc::PIC_) { 3353 // For PIC, the sequence is: 3354 // BRIND(load(Jumptable + index) + RelocBase) 3355 // RelocBase can be JumpTable, GOT or some sort of global base. 3356 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 3357 TLI.getPICJumpTableRelocBase(Table, DAG)); 3358 } 3359 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 3360 Results.push_back(Tmp1); 3361 break; 3362 } 3363 case ISD::BRCOND: 3364 // Expand brcond's setcc into its constituent parts and create a BR_CC 3365 // Node. 3366 Tmp1 = Node->getOperand(0); 3367 Tmp2 = Node->getOperand(1); 3368 if (Tmp2.getOpcode() == ISD::SETCC) { 3369 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 3370 Tmp1, Tmp2.getOperand(2), 3371 Tmp2.getOperand(0), Tmp2.getOperand(1), 3372 Node->getOperand(2)); 3373 } else { 3374 // We test only the i1 bit. Skip the AND if UNDEF. 3375 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 : 3376 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2, 3377 DAG.getConstant(1, Tmp2.getValueType())); 3378 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 3379 DAG.getCondCode(ISD::SETNE), Tmp3, 3380 DAG.getConstant(0, Tmp3.getValueType()), 3381 Node->getOperand(2)); 3382 } 3383 Results.push_back(Tmp1); 3384 break; 3385 case ISD::SETCC: { 3386 Tmp1 = Node->getOperand(0); 3387 Tmp2 = Node->getOperand(1); 3388 Tmp3 = Node->getOperand(2); 3389 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 3390 3391 // If we expanded the SETCC into an AND/OR, return the new node 3392 if (Tmp2.getNode() == 0) { 3393 Results.push_back(Tmp1); 3394 break; 3395 } 3396 3397 // Otherwise, SETCC for the given comparison type must be completely 3398 // illegal; expand it into a SELECT_CC. 3399 EVT VT = Node->getValueType(0); 3400 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3401 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 3402 Results.push_back(Tmp1); 3403 break; 3404 } 3405 case ISD::SELECT_CC: { 3406 Tmp1 = Node->getOperand(0); // LHS 3407 Tmp2 = Node->getOperand(1); // RHS 3408 Tmp3 = Node->getOperand(2); // True 3409 Tmp4 = Node->getOperand(3); // False 3410 SDValue CC = Node->getOperand(4); 3411 3412 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 3413 Tmp1, Tmp2, CC, dl); 3414 3415 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 3416 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3417 CC = DAG.getCondCode(ISD::SETNE); 3418 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 3419 Tmp3, Tmp4, CC); 3420 Results.push_back(Tmp1); 3421 break; 3422 } 3423 case ISD::BR_CC: { 3424 Tmp1 = Node->getOperand(0); // Chain 3425 Tmp2 = Node->getOperand(2); // LHS 3426 Tmp3 = Node->getOperand(3); // RHS 3427 Tmp4 = Node->getOperand(1); // CC 3428 3429 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 3430 Tmp2, Tmp3, Tmp4, dl); 3431 3432 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 3433 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 3434 Tmp4 = DAG.getCondCode(ISD::SETNE); 3435 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3436 Tmp3, Node->getOperand(4)); 3437 Results.push_back(Tmp1); 3438 break; 3439 } 3440 case ISD::BUILD_VECTOR: 3441 Results.push_back(ExpandBUILD_VECTOR(Node)); 3442 break; 3443 case ISD::SRA: 3444 case ISD::SRL: 3445 case ISD::SHL: { 3446 // Scalarize vector SRA/SRL/SHL. 3447 EVT VT = Node->getValueType(0); 3448 assert(VT.isVector() && "Unable to legalize non-vector shift"); 3449 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal"); 3450 unsigned NumElem = VT.getVectorNumElements(); 3451 3452 SmallVector<SDValue, 8> Scalars; 3453 for (unsigned Idx = 0; Idx < NumElem; Idx++) { 3454 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 3455 VT.getScalarType(), 3456 Node->getOperand(0), DAG.getIntPtrConstant(Idx)); 3457 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 3458 VT.getScalarType(), 3459 Node->getOperand(1), DAG.getIntPtrConstant(Idx)); 3460 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl, 3461 VT.getScalarType(), Ex, Sh)); 3462 } 3463 SDValue Result = 3464 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), 3465 &Scalars[0], Scalars.size()); 3466 ReplaceNode(SDValue(Node, 0), Result); 3467 break; 3468 } 3469 case ISD::GLOBAL_OFFSET_TABLE: 3470 case ISD::GlobalAddress: 3471 case ISD::GlobalTLSAddress: 3472 case ISD::ExternalSymbol: 3473 case ISD::ConstantPool: 3474 case ISD::JumpTable: 3475 case ISD::INTRINSIC_W_CHAIN: 3476 case ISD::INTRINSIC_WO_CHAIN: 3477 case ISD::INTRINSIC_VOID: 3478 // FIXME: Custom lowering for these operations shouldn't return null! 3479 break; 3480 } 3481 3482 // Replace the original node with the legalized result. 3483 if (!Results.empty()) 3484 ReplaceNode(Node, Results.data()); 3485} 3486 3487void SelectionDAGLegalize::PromoteNode(SDNode *Node) { 3488 SmallVector<SDValue, 8> Results; 3489 EVT OVT = Node->getValueType(0); 3490 if (Node->getOpcode() == ISD::UINT_TO_FP || 3491 Node->getOpcode() == ISD::SINT_TO_FP || 3492 Node->getOpcode() == ISD::SETCC) { 3493 OVT = Node->getOperand(0).getValueType(); 3494 } 3495 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3496 DebugLoc dl = Node->getDebugLoc(); 3497 SDValue Tmp1, Tmp2, Tmp3; 3498 switch (Node->getOpcode()) { 3499 case ISD::CTTZ: 3500 case ISD::CTTZ_ZERO_UNDEF: 3501 case ISD::CTLZ: 3502 case ISD::CTLZ_ZERO_UNDEF: 3503 case ISD::CTPOP: 3504 // Zero extend the argument. 3505 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3506 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is 3507 // already the correct result. 3508 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3509 if (Node->getOpcode() == ISD::CTTZ) { 3510 // FIXME: This should set a bit in the zero extended value instead. 3511 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3512 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3513 ISD::SETEQ); 3514 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3515 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3516 } else if (Node->getOpcode() == ISD::CTLZ || 3517 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) { 3518 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3519 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3520 DAG.getConstant(NVT.getSizeInBits() - 3521 OVT.getSizeInBits(), NVT)); 3522 } 3523 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3524 break; 3525 case ISD::BSWAP: { 3526 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3527 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3528 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3529 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3530 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT))); 3531 Results.push_back(Tmp1); 3532 break; 3533 } 3534 case ISD::FP_TO_UINT: 3535 case ISD::FP_TO_SINT: 3536 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3537 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3538 Results.push_back(Tmp1); 3539 break; 3540 case ISD::UINT_TO_FP: 3541 case ISD::SINT_TO_FP: 3542 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3543 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3544 Results.push_back(Tmp1); 3545 break; 3546 case ISD::VAARG: { 3547 SDValue Chain = Node->getOperand(0); // Get the chain. 3548 SDValue Ptr = Node->getOperand(1); // Get the pointer. 3549 3550 unsigned TruncOp; 3551 if (OVT.isVector()) { 3552 TruncOp = ISD::BITCAST; 3553 } else { 3554 assert(OVT.isInteger() 3555 && "VAARG promotion is supported only for vectors or integer types"); 3556 TruncOp = ISD::TRUNCATE; 3557 } 3558 3559 // Perform the larger operation, then convert back 3560 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2), 3561 Node->getConstantOperandVal(3)); 3562 Chain = Tmp1.getValue(1); 3563 3564 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1); 3565 3566 // Modified the chain result - switch anything that used the old chain to 3567 // use the new one. 3568 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2); 3569 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain); 3570 ReplacedNode(Node); 3571 break; 3572 } 3573 case ISD::AND: 3574 case ISD::OR: 3575 case ISD::XOR: { 3576 unsigned ExtOp, TruncOp; 3577 if (OVT.isVector()) { 3578 ExtOp = ISD::BITCAST; 3579 TruncOp = ISD::BITCAST; 3580 } else { 3581 assert(OVT.isInteger() && "Cannot promote logic operation"); 3582 ExtOp = ISD::ANY_EXTEND; 3583 TruncOp = ISD::TRUNCATE; 3584 } 3585 // Promote each of the values to the new type. 3586 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3587 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3588 // Perform the larger operation, then convert back 3589 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3590 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3591 break; 3592 } 3593 case ISD::SELECT: { 3594 unsigned ExtOp, TruncOp; 3595 if (Node->getValueType(0).isVector()) { 3596 ExtOp = ISD::BITCAST; 3597 TruncOp = ISD::BITCAST; 3598 } else if (Node->getValueType(0).isInteger()) { 3599 ExtOp = ISD::ANY_EXTEND; 3600 TruncOp = ISD::TRUNCATE; 3601 } else { 3602 ExtOp = ISD::FP_EXTEND; 3603 TruncOp = ISD::FP_ROUND; 3604 } 3605 Tmp1 = Node->getOperand(0); 3606 // Promote each of the values to the new type. 3607 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3608 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3609 // Perform the larger operation, then round down. 3610 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3611 if (TruncOp != ISD::FP_ROUND) 3612 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3613 else 3614 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3615 DAG.getIntPtrConstant(0)); 3616 Results.push_back(Tmp1); 3617 break; 3618 } 3619 case ISD::VECTOR_SHUFFLE: { 3620 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask(); 3621 3622 // Cast the two input vectors. 3623 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0)); 3624 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1)); 3625 3626 // Convert the shuffle mask to the right # elements. 3627 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3628 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1); 3629 Results.push_back(Tmp1); 3630 break; 3631 } 3632 case ISD::SETCC: { 3633 unsigned ExtOp = ISD::FP_EXTEND; 3634 if (NVT.isInteger()) { 3635 ISD::CondCode CCCode = 3636 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3637 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3638 } 3639 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3640 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3641 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3642 Tmp1, Tmp2, Node->getOperand(2))); 3643 break; 3644 } 3645 case ISD::FDIV: 3646 case ISD::FREM: 3647 case ISD::FPOW: { 3648 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); 3649 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); 3650 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3651 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, 3652 Tmp3, DAG.getIntPtrConstant(0))); 3653 break; 3654 } 3655 case ISD::FLOG2: 3656 case ISD::FEXP2: 3657 case ISD::FLOG: 3658 case ISD::FEXP: { 3659 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); 3660 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3661 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, 3662 Tmp2, DAG.getIntPtrConstant(0))); 3663 break; 3664 } 3665 } 3666 3667 // Replace the original node with the legalized result. 3668 if (!Results.empty()) 3669 ReplaceNode(Node, Results.data()); 3670} 3671 3672// SelectionDAG::Legalize - This is the entry point for the file. 3673// 3674void SelectionDAG::Legalize() { 3675 /// run - This is the main entry point to this class. 3676 /// 3677 SelectionDAGLegalize(*this).LegalizeDAG(); 3678} 3679