LegalizeDAG.cpp revision 99c25b86aa85b0093f24b2394a5aa37f66294b2b
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned ValueTypeActions; 56 57 /// NeedsAnotherIteration - This is set when we expand a large integer 58 /// operation into smaller integer operations, but the smaller operations are 59 /// not set. This occurs only rarely in practice, for targets that don't have 60 /// 32-bit or larger integer registers. 61 bool NeedsAnotherIteration; 62 63 /// LegalizedNodes - For nodes that are of legal width, and that have more 64 /// than one use, this map indicates what regularized operand to use. This 65 /// allows us to avoid legalizing the same thing more than once. 66 std::map<SDOperand, SDOperand> LegalizedNodes; 67 68 /// PromotedNodes - For nodes that are below legal width, and that have more 69 /// than one use, this map indicates what promoted value to use. This allows 70 /// us to avoid promoting the same thing more than once. 71 std::map<SDOperand, SDOperand> PromotedNodes; 72 73 /// ExpandedNodes - For nodes that need to be expanded, and which have more 74 /// than one use, this map indicates which which operands are the expanded 75 /// version of the input. This allows us to avoid expanding the same node 76 /// more than once. 77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 78 79 void AddLegalizedOperand(SDOperand From, SDOperand To) { 80 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second; 81 assert(isNew && "Got into the map somehow?"); 82 } 83 void AddPromotedOperand(SDOperand From, SDOperand To) { 84 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 85 assert(isNew && "Got into the map somehow?"); 86 } 87 88public: 89 90 SelectionDAGLegalize(SelectionDAG &DAG); 91 92 /// Run - While there is still lowering to do, perform a pass over the DAG. 93 /// Most regularization can be done in a single pass, but targets that require 94 /// large values to be split into registers multiple times (e.g. i64 -> 4x 95 /// i16) require iteration for these values (the first iteration will demote 96 /// to i32, the second will demote to i16). 97 void Run() { 98 do { 99 NeedsAnotherIteration = false; 100 LegalizeDAG(); 101 } while (NeedsAnotherIteration); 102 } 103 104 /// getTypeAction - Return how we should legalize values of this type, either 105 /// it is already legal or we need to expand it into multiple registers of 106 /// smaller integer type, or we need to promote it to a larger type. 107 LegalizeAction getTypeAction(MVT::ValueType VT) const { 108 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 109 } 110 111 /// isTypeLegal - Return true if this type is legal on this target. 112 /// 113 bool isTypeLegal(MVT::ValueType VT) const { 114 return getTypeAction(VT) == Legal; 115 } 116 117private: 118 void LegalizeDAG(); 119 120 SDOperand LegalizeOp(SDOperand O); 121 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 122 SDOperand PromoteOp(SDOperand O); 123 124 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 125 SDOperand &Hi); 126 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 127 SDOperand Source); 128 129 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 130 SDOperand LegalOp, 131 MVT::ValueType DestVT); 132 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 133 bool isSigned); 134 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 135 bool isSigned); 136 137 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 138 SDOperand &Lo, SDOperand &Hi); 139 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 140 SDOperand &Lo, SDOperand &Hi); 141 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 142 SDOperand &Lo, SDOperand &Hi); 143 144 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 145 146 SDOperand getIntPtrConstant(uint64_t Val) { 147 return DAG.getConstant(Val, TLI.getPointerTy()); 148 } 149}; 150} 151 152 153SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 154 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 155 ValueTypeActions(TLI.getValueTypeActions()) { 156 assert(MVT::LAST_VALUETYPE <= 16 && 157 "Too many value types for ValueTypeActions to hold!"); 158} 159 160/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 161/// INT_TO_FP operation of the specified operand when the target requests that 162/// we expand it. At this point, we know that the result and operand types are 163/// legal for the target. 164SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 165 SDOperand Op0, 166 MVT::ValueType DestVT) { 167 if (Op0.getValueType() == MVT::i32) { 168 // simple 32-bit [signed|unsigned] integer to float/double expansion 169 170 // get the stack frame index of a 8 byte buffer 171 MachineFunction &MF = DAG.getMachineFunction(); 172 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 173 // get address of 8 byte buffer 174 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 175 // word offset constant for Hi/Lo address computation 176 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 177 // set up Hi and Lo (into buffer) address based on endian 178 SDOperand Hi, Lo; 179 if (TLI.isLittleEndian()) { 180 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 181 Lo = StackSlot; 182 } else { 183 Hi = StackSlot; 184 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 185 } 186 // if signed map to unsigned space 187 SDOperand Op0Mapped; 188 if (isSigned) { 189 // constant used to invert sign bit (signed to unsigned mapping) 190 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 191 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 192 } else { 193 Op0Mapped = Op0; 194 } 195 // store the lo of the constructed double - based on integer input 196 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 197 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 198 // initial hi portion of constructed double 199 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 200 // store the hi of the constructed double - biased exponent 201 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 202 InitialHi, Hi, DAG.getSrcValue(NULL)); 203 // load the constructed double 204 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 205 DAG.getSrcValue(NULL)); 206 // FP constant to bias correct the final result 207 SDOperand Bias = DAG.getConstantFP(isSigned ? 208 BitsToDouble(0x4330000080000000ULL) 209 : BitsToDouble(0x4330000000000000ULL), 210 MVT::f64); 211 // subtract the bias 212 SDOperand Sub = DAG.getNode(ISD::SUB, MVT::f64, Load, Bias); 213 // final result 214 SDOperand Result; 215 // handle final rounding 216 if (DestVT == MVT::f64) { 217 // do nothing 218 Result = Sub; 219 } else { 220 // if f32 then cast to f32 221 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 222 } 223 NeedsAnotherIteration = true; 224 return Result; 225 } 226 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 227 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 228 229 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 230 DAG.getConstant(0, Op0.getValueType()), 231 ISD::SETLT); 232 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 233 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 234 SignSet, Four, Zero); 235 236 // If the sign bit of the integer is set, the large number will be treated 237 // as a negative number. To counteract this, the dynamic code adds an 238 // offset depending on the data type. 239 uint64_t FF; 240 switch (Op0.getValueType()) { 241 default: assert(0 && "Unsupported integer type!"); 242 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 243 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 244 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 245 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 246 } 247 if (TLI.isLittleEndian()) FF <<= 32; 248 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 249 250 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 251 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 252 SDOperand FudgeInReg; 253 if (DestVT == MVT::f32) 254 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 255 DAG.getSrcValue(NULL)); 256 else { 257 assert(DestVT == MVT::f64 && "Unexpected conversion"); 258 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 259 DAG.getEntryNode(), CPIdx, 260 DAG.getSrcValue(NULL), MVT::f32)); 261 } 262 263 NeedsAnotherIteration = true; 264 return DAG.getNode(ISD::ADD, DestVT, Tmp1, FudgeInReg); 265} 266 267/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 268/// *INT_TO_FP operation of the specified operand when the target requests that 269/// we promote it. At this point, we know that the result and operand types are 270/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 271/// operation that takes a larger input. 272SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 273 MVT::ValueType DestVT, 274 bool isSigned) { 275 // First step, figure out the appropriate *INT_TO_FP operation to use. 276 MVT::ValueType NewInTy = LegalOp.getValueType(); 277 278 unsigned OpToUse = 0; 279 280 // Scan for the appropriate larger type to use. 281 while (1) { 282 NewInTy = (MVT::ValueType)(NewInTy+1); 283 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 284 285 // If the target supports SINT_TO_FP of this type, use it. 286 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 287 default: break; 288 case TargetLowering::Legal: 289 if (!TLI.isTypeLegal(NewInTy)) 290 break; // Can't use this datatype. 291 // FALL THROUGH. 292 case TargetLowering::Custom: 293 OpToUse = ISD::SINT_TO_FP; 294 break; 295 } 296 if (OpToUse) break; 297 if (isSigned) continue; 298 299 // If the target supports UINT_TO_FP of this type, use it. 300 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 301 default: break; 302 case TargetLowering::Legal: 303 if (!TLI.isTypeLegal(NewInTy)) 304 break; // Can't use this datatype. 305 // FALL THROUGH. 306 case TargetLowering::Custom: 307 OpToUse = ISD::UINT_TO_FP; 308 break; 309 } 310 if (OpToUse) break; 311 312 // Otherwise, try a larger type. 313 } 314 315 // Make sure to legalize any nodes we create here in the next pass. 316 NeedsAnotherIteration = true; 317 318 // Okay, we found the operation and type to use. Zero extend our input to the 319 // desired type then run the operation on it. 320 return DAG.getNode(OpToUse, DestVT, 321 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 322 NewInTy, LegalOp)); 323} 324 325/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 326/// FP_TO_*INT operation of the specified operand when the target requests that 327/// we promote it. At this point, we know that the result and operand types are 328/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 329/// operation that returns a larger result. 330SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 331 MVT::ValueType DestVT, 332 bool isSigned) { 333 // First step, figure out the appropriate FP_TO*INT operation to use. 334 MVT::ValueType NewOutTy = DestVT; 335 336 unsigned OpToUse = 0; 337 338 // Scan for the appropriate larger type to use. 339 while (1) { 340 NewOutTy = (MVT::ValueType)(NewOutTy+1); 341 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 342 343 // If the target supports FP_TO_SINT returning this type, use it. 344 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 345 default: break; 346 case TargetLowering::Legal: 347 if (!TLI.isTypeLegal(NewOutTy)) 348 break; // Can't use this datatype. 349 // FALL THROUGH. 350 case TargetLowering::Custom: 351 OpToUse = ISD::FP_TO_SINT; 352 break; 353 } 354 if (OpToUse) break; 355 356 // If the target supports FP_TO_UINT of this type, use it. 357 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 358 default: break; 359 case TargetLowering::Legal: 360 if (!TLI.isTypeLegal(NewOutTy)) 361 break; // Can't use this datatype. 362 // FALL THROUGH. 363 case TargetLowering::Custom: 364 OpToUse = ISD::FP_TO_UINT; 365 break; 366 } 367 if (OpToUse) break; 368 369 // Otherwise, try a larger type. 370 } 371 372 // Make sure to legalize any nodes we create here in the next pass. 373 NeedsAnotherIteration = true; 374 375 // Okay, we found the operation and type to use. Truncate the result of the 376 // extended FP_TO_*INT operation to the desired size. 377 return DAG.getNode(ISD::TRUNCATE, DestVT, 378 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 379} 380 381 382void SelectionDAGLegalize::LegalizeDAG() { 383 SDOperand OldRoot = DAG.getRoot(); 384 SDOperand NewRoot = LegalizeOp(OldRoot); 385 DAG.setRoot(NewRoot); 386 387 ExpandedNodes.clear(); 388 LegalizedNodes.clear(); 389 PromotedNodes.clear(); 390 391 // Remove dead nodes now. 392 DAG.RemoveDeadNodes(OldRoot.Val); 393} 394 395SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 396 assert(isTypeLegal(Op.getValueType()) && 397 "Caller should expand or promote operands that are not legal!"); 398 SDNode *Node = Op.Val; 399 400 // If this operation defines any values that cannot be represented in a 401 // register on this target, make sure to expand or promote them. 402 if (Node->getNumValues() > 1) { 403 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 404 switch (getTypeAction(Node->getValueType(i))) { 405 case Legal: break; // Nothing to do. 406 case Expand: { 407 SDOperand T1, T2; 408 ExpandOp(Op.getValue(i), T1, T2); 409 assert(LegalizedNodes.count(Op) && 410 "Expansion didn't add legal operands!"); 411 return LegalizedNodes[Op]; 412 } 413 case Promote: 414 PromoteOp(Op.getValue(i)); 415 assert(LegalizedNodes.count(Op) && 416 "Expansion didn't add legal operands!"); 417 return LegalizedNodes[Op]; 418 } 419 } 420 421 // Note that LegalizeOp may be reentered even from single-use nodes, which 422 // means that we always must cache transformed nodes. 423 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 424 if (I != LegalizedNodes.end()) return I->second; 425 426 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 427 428 SDOperand Result = Op; 429 430 switch (Node->getOpcode()) { 431 default: 432 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 433 // If this is a target node, legalize it by legalizing the operands then 434 // passing it through. 435 std::vector<SDOperand> Ops; 436 bool Changed = false; 437 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 438 Ops.push_back(LegalizeOp(Node->getOperand(i))); 439 Changed = Changed || Node->getOperand(i) != Ops.back(); 440 } 441 if (Changed) 442 if (Node->getNumValues() == 1) 443 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 444 else { 445 std::vector<MVT::ValueType> VTs(Node->value_begin(), 446 Node->value_end()); 447 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 448 } 449 450 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 451 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 452 return Result.getValue(Op.ResNo); 453 } 454 // Otherwise this is an unhandled builtin node. splat. 455 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 456 assert(0 && "Do not know how to legalize this operator!"); 457 abort(); 458 case ISD::EntryToken: 459 case ISD::FrameIndex: 460 case ISD::GlobalAddress: 461 case ISD::ExternalSymbol: 462 case ISD::ConstantPool: // Nothing to do. 463 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!"); 464 break; 465 case ISD::AssertSext: 466 case ISD::AssertZext: 467 Tmp1 = LegalizeOp(Node->getOperand(0)); 468 if (Tmp1 != Node->getOperand(0)) 469 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 470 Node->getOperand(1)); 471 break; 472 case ISD::CopyFromReg: 473 Tmp1 = LegalizeOp(Node->getOperand(0)); 474 if (Tmp1 != Node->getOperand(0)) 475 Result = DAG.getCopyFromReg(Tmp1, 476 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 477 Node->getValueType(0)); 478 else 479 Result = Op.getValue(0); 480 481 // Since CopyFromReg produces two values, make sure to remember that we 482 // legalized both of them. 483 AddLegalizedOperand(Op.getValue(0), Result); 484 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 485 return Result.getValue(Op.ResNo); 486 case ISD::ImplicitDef: 487 Tmp1 = LegalizeOp(Node->getOperand(0)); 488 if (Tmp1 != Node->getOperand(0)) 489 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other, 490 Tmp1, Node->getOperand(1)); 491 break; 492 case ISD::UNDEF: { 493 MVT::ValueType VT = Op.getValueType(); 494 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 495 default: assert(0 && "This action is not supported yet!"); 496 case TargetLowering::Expand: 497 case TargetLowering::Promote: 498 if (MVT::isInteger(VT)) 499 Result = DAG.getConstant(0, VT); 500 else if (MVT::isFloatingPoint(VT)) 501 Result = DAG.getConstantFP(0, VT); 502 else 503 assert(0 && "Unknown value type!"); 504 break; 505 case TargetLowering::Legal: 506 break; 507 } 508 break; 509 } 510 case ISD::Constant: 511 // We know we don't need to expand constants here, constants only have one 512 // value and we check that it is fine above. 513 514 // FIXME: Maybe we should handle things like targets that don't support full 515 // 32-bit immediates? 516 break; 517 case ISD::ConstantFP: { 518 // Spill FP immediates to the constant pool if the target cannot directly 519 // codegen them. Targets often have some immediate values that can be 520 // efficiently generated into an FP register without a load. We explicitly 521 // leave these constants as ConstantFP nodes for the target to deal with. 522 523 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 524 525 // Check to see if this FP immediate is already legal. 526 bool isLegal = false; 527 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 528 E = TLI.legal_fpimm_end(); I != E; ++I) 529 if (CFP->isExactlyValue(*I)) { 530 isLegal = true; 531 break; 532 } 533 534 if (!isLegal) { 535 // Otherwise we need to spill the constant to memory. 536 bool Extend = false; 537 538 // If a FP immediate is precise when represented as a float, we put it 539 // into the constant pool as a float, even if it's is statically typed 540 // as a double. 541 MVT::ValueType VT = CFP->getValueType(0); 542 bool isDouble = VT == MVT::f64; 543 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 544 Type::FloatTy, CFP->getValue()); 545 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 546 // Only do this if the target has a native EXTLOAD instruction from 547 // f32. 548 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 549 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 550 VT = MVT::f32; 551 Extend = true; 552 } 553 554 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 555 if (Extend) { 556 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 557 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 558 } else { 559 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 560 DAG.getSrcValue(NULL)); 561 } 562 } 563 break; 564 } 565 case ISD::TokenFactor: { 566 std::vector<SDOperand> Ops; 567 bool Changed = false; 568 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 569 SDOperand Op = Node->getOperand(i); 570 // Fold single-use TokenFactor nodes into this token factor as we go. 571 // FIXME: This is something that the DAGCombiner should do!! 572 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 573 Changed = true; 574 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 575 Ops.push_back(LegalizeOp(Op.getOperand(j))); 576 } else { 577 Ops.push_back(LegalizeOp(Op)); // Legalize the operands 578 Changed |= Ops[i] != Op; 579 } 580 } 581 if (Changed) 582 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 583 break; 584 } 585 586 case ISD::CALLSEQ_START: 587 case ISD::CALLSEQ_END: 588 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 589 // Do not try to legalize the target-specific arguments (#1+) 590 Tmp2 = Node->getOperand(0); 591 if (Tmp1 != Tmp2) { 592 Node->setAdjCallChain(Tmp1); 593 594 // If moving the operand from pointing to Tmp2 dropped its use count to 1, 595 // this will cause the maps used to memoize results to get confused. 596 // Create and add a dummy use, just to increase its use count. This will 597 // be removed at the end of legalize when dead nodes are removed. 598 if (Tmp2.Val->hasOneUse()) 599 DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp2, 600 DAG.getConstant(0, MVT::i32)); 601 } 602 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These 603 // nodes are treated specially and are mutated in place. This makes the dag 604 // legalization process more efficient and also makes libcall insertion 605 // easier. 606 break; 607 case ISD::DYNAMIC_STACKALLOC: 608 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 609 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 610 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 611 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 612 Tmp3 != Node->getOperand(2)) { 613 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 614 std::vector<SDOperand> Ops; 615 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 616 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 617 } else 618 Result = Op.getValue(0); 619 620 // Since this op produces two values, make sure to remember that we 621 // legalized both of them. 622 AddLegalizedOperand(SDOperand(Node, 0), Result); 623 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 624 return Result.getValue(Op.ResNo); 625 626 case ISD::TAILCALL: 627 case ISD::CALL: { 628 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 629 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 630 631 bool Changed = false; 632 std::vector<SDOperand> Ops; 633 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 634 Ops.push_back(LegalizeOp(Node->getOperand(i))); 635 Changed |= Ops.back() != Node->getOperand(i); 636 } 637 638 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 639 std::vector<MVT::ValueType> RetTyVTs; 640 RetTyVTs.reserve(Node->getNumValues()); 641 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 642 RetTyVTs.push_back(Node->getValueType(i)); 643 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 644 Node->getOpcode() == ISD::TAILCALL), 0); 645 } else { 646 Result = Result.getValue(0); 647 } 648 // Since calls produce multiple values, make sure to remember that we 649 // legalized all of them. 650 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 651 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 652 return Result.getValue(Op.ResNo); 653 } 654 case ISD::BR: 655 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 656 if (Tmp1 != Node->getOperand(0)) 657 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 658 break; 659 660 case ISD::BRCOND: 661 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 662 663 switch (getTypeAction(Node->getOperand(1).getValueType())) { 664 case Expand: assert(0 && "It's impossible to expand bools"); 665 case Legal: 666 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 667 break; 668 case Promote: 669 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 670 break; 671 } 672 673 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 674 default: assert(0 && "This action is not supported yet!"); 675 case TargetLowering::Expand: 676 // Expand brcond's setcc into its constituent parts and create a BR_CC 677 // Node. 678 if (Tmp2.getOpcode() == ISD::SETCC) { 679 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 680 Tmp2.getOperand(0), Tmp2.getOperand(1), 681 Node->getOperand(2)); 682 } else { 683 // Make sure the condition is either zero or one. It may have been 684 // promoted from something else. 685 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 686 687 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 688 DAG.getCondCode(ISD::SETNE), Tmp2, 689 DAG.getConstant(0, Tmp2.getValueType()), 690 Node->getOperand(2)); 691 } 692 break; 693 case TargetLowering::Legal: 694 // Basic block destination (Op#2) is always legal. 695 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 696 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 697 Node->getOperand(2)); 698 break; 699 } 700 break; 701 case ISD::BR_CC: 702 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 703 704 if (isTypeLegal(Node->getOperand(2).getValueType())) { 705 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 706 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 707 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 708 Tmp3 != Node->getOperand(3)) { 709 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 710 Tmp2, Tmp3, Node->getOperand(4)); 711 } 712 break; 713 } else { 714 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 715 Node->getOperand(2), // LHS 716 Node->getOperand(3), // RHS 717 Node->getOperand(1))); 718 // If we get a SETCC back from legalizing the SETCC node we just 719 // created, then use its LHS, RHS, and CC directly in creating a new 720 // node. Otherwise, select between the true and false value based on 721 // comparing the result of the legalized with zero. 722 if (Tmp2.getOpcode() == ISD::SETCC) { 723 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 724 Tmp2.getOperand(0), Tmp2.getOperand(1), 725 Node->getOperand(4)); 726 } else { 727 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 728 DAG.getCondCode(ISD::SETNE), 729 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 730 Node->getOperand(4)); 731 } 732 } 733 break; 734 case ISD::BRCONDTWOWAY: 735 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 736 switch (getTypeAction(Node->getOperand(1).getValueType())) { 737 case Expand: assert(0 && "It's impossible to expand bools"); 738 case Legal: 739 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 740 break; 741 case Promote: 742 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 743 break; 744 } 745 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 746 // pair. 747 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 748 case TargetLowering::Promote: 749 default: assert(0 && "This action is not supported yet!"); 750 case TargetLowering::Legal: 751 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 752 std::vector<SDOperand> Ops; 753 Ops.push_back(Tmp1); 754 Ops.push_back(Tmp2); 755 Ops.push_back(Node->getOperand(2)); 756 Ops.push_back(Node->getOperand(3)); 757 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 758 } 759 break; 760 case TargetLowering::Expand: 761 // If BRTWOWAY_CC is legal for this target, then simply expand this node 762 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 763 // BRCOND/BR pair. 764 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 765 if (Tmp2.getOpcode() == ISD::SETCC) { 766 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 767 Tmp2.getOperand(0), Tmp2.getOperand(1), 768 Node->getOperand(2), Node->getOperand(3)); 769 } else { 770 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 771 DAG.getConstant(0, Tmp2.getValueType()), 772 Node->getOperand(2), Node->getOperand(3)); 773 } 774 } else { 775 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 776 Node->getOperand(2)); 777 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 778 } 779 break; 780 } 781 break; 782 case ISD::BRTWOWAY_CC: 783 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 784 if (isTypeLegal(Node->getOperand(2).getValueType())) { 785 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 786 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 787 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 788 Tmp3 != Node->getOperand(3)) { 789 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3, 790 Node->getOperand(4), Node->getOperand(5)); 791 } 792 break; 793 } else { 794 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 795 Node->getOperand(2), // LHS 796 Node->getOperand(3), // RHS 797 Node->getOperand(1))); 798 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 799 // pair. 800 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 801 default: assert(0 && "This action is not supported yet!"); 802 case TargetLowering::Legal: 803 // If we get a SETCC back from legalizing the SETCC node we just 804 // created, then use its LHS, RHS, and CC directly in creating a new 805 // node. Otherwise, select between the true and false value based on 806 // comparing the result of the legalized with zero. 807 if (Tmp2.getOpcode() == ISD::SETCC) { 808 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 809 Tmp2.getOperand(0), Tmp2.getOperand(1), 810 Node->getOperand(4), Node->getOperand(5)); 811 } else { 812 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 813 DAG.getConstant(0, Tmp2.getValueType()), 814 Node->getOperand(4), Node->getOperand(5)); 815 } 816 break; 817 case TargetLowering::Expand: 818 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 819 Node->getOperand(4)); 820 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 821 break; 822 } 823 } 824 break; 825 case ISD::LOAD: 826 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 827 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 828 829 if (Tmp1 != Node->getOperand(0) || 830 Tmp2 != Node->getOperand(1)) 831 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, 832 Node->getOperand(2)); 833 else 834 Result = SDOperand(Node, 0); 835 836 // Since loads produce two values, make sure to remember that we legalized 837 // both of them. 838 AddLegalizedOperand(SDOperand(Node, 0), Result); 839 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 840 return Result.getValue(Op.ResNo); 841 842 case ISD::EXTLOAD: 843 case ISD::SEXTLOAD: 844 case ISD::ZEXTLOAD: { 845 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 846 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 847 848 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 849 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 850 default: assert(0 && "This action is not supported yet!"); 851 case TargetLowering::Promote: 852 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 853 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 854 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 855 // Since loads produce two values, make sure to remember that we legalized 856 // both of them. 857 AddLegalizedOperand(SDOperand(Node, 0), Result); 858 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 859 return Result.getValue(Op.ResNo); 860 861 case TargetLowering::Legal: 862 if (Tmp1 != Node->getOperand(0) || 863 Tmp2 != Node->getOperand(1)) 864 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 865 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 866 else 867 Result = SDOperand(Node, 0); 868 869 // Since loads produce two values, make sure to remember that we legalized 870 // both of them. 871 AddLegalizedOperand(SDOperand(Node, 0), Result); 872 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 873 return Result.getValue(Op.ResNo); 874 case TargetLowering::Expand: 875 //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 876 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 877 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 878 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 879 if (Op.ResNo) 880 return Load.getValue(1); 881 return Result; 882 } 883 assert(Node->getOpcode() != ISD::EXTLOAD && 884 "EXTLOAD should always be supported!"); 885 // Turn the unsupported load into an EXTLOAD followed by an explicit 886 // zero/sign extend inreg. 887 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 888 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 889 SDOperand ValRes; 890 if (Node->getOpcode() == ISD::SEXTLOAD) 891 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 892 Result, DAG.getValueType(SrcVT)); 893 else 894 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 895 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 896 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 897 if (Op.ResNo) 898 return Result.getValue(1); 899 return ValRes; 900 } 901 assert(0 && "Unreachable"); 902 } 903 case ISD::EXTRACT_ELEMENT: 904 // Get both the low and high parts. 905 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 906 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 907 Result = Tmp2; // 1 -> Hi 908 else 909 Result = Tmp1; // 0 -> Lo 910 break; 911 912 case ISD::CopyToReg: 913 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 914 915 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 916 "Register type must be legal!"); 917 // Legalize the incoming value (must be legal). 918 Tmp2 = LegalizeOp(Node->getOperand(2)); 919 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2)) 920 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1, 921 Node->getOperand(1), Tmp2); 922 break; 923 924 case ISD::RET: 925 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 926 switch (Node->getNumOperands()) { 927 case 2: // ret val 928 switch (getTypeAction(Node->getOperand(1).getValueType())) { 929 case Legal: 930 Tmp2 = LegalizeOp(Node->getOperand(1)); 931 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 932 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 933 break; 934 case Expand: { 935 SDOperand Lo, Hi; 936 ExpandOp(Node->getOperand(1), Lo, Hi); 937 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 938 break; 939 } 940 case Promote: 941 Tmp2 = PromoteOp(Node->getOperand(1)); 942 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 943 break; 944 } 945 break; 946 case 1: // ret void 947 if (Tmp1 != Node->getOperand(0)) 948 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 949 break; 950 default: { // ret <values> 951 std::vector<SDOperand> NewValues; 952 NewValues.push_back(Tmp1); 953 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 954 switch (getTypeAction(Node->getOperand(i).getValueType())) { 955 case Legal: 956 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 957 break; 958 case Expand: { 959 SDOperand Lo, Hi; 960 ExpandOp(Node->getOperand(i), Lo, Hi); 961 NewValues.push_back(Lo); 962 NewValues.push_back(Hi); 963 break; 964 } 965 case Promote: 966 assert(0 && "Can't promote multiple return value yet!"); 967 } 968 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 969 break; 970 } 971 } 972 break; 973 case ISD::STORE: 974 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 975 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 976 977 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 978 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 979 if (CFP->getValueType(0) == MVT::f32) { 980 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 981 DAG.getConstant(FloatToBits(CFP->getValue()), 982 MVT::i32), 983 Tmp2, 984 Node->getOperand(3)); 985 } else { 986 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 987 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 988 DAG.getConstant(DoubleToBits(CFP->getValue()), 989 MVT::i64), 990 Tmp2, 991 Node->getOperand(3)); 992 } 993 Node = Result.Val; 994 } 995 996 switch (getTypeAction(Node->getOperand(1).getValueType())) { 997 case Legal: { 998 SDOperand Val = LegalizeOp(Node->getOperand(1)); 999 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 1000 Tmp2 != Node->getOperand(2)) 1001 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 1002 Node->getOperand(3)); 1003 break; 1004 } 1005 case Promote: 1006 // Truncate the value and store the result. 1007 Tmp3 = PromoteOp(Node->getOperand(1)); 1008 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1009 Node->getOperand(3), 1010 DAG.getValueType(Node->getOperand(1).getValueType())); 1011 break; 1012 1013 case Expand: 1014 SDOperand Lo, Hi; 1015 ExpandOp(Node->getOperand(1), Lo, Hi); 1016 1017 if (!TLI.isLittleEndian()) 1018 std::swap(Lo, Hi); 1019 1020 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1021 Node->getOperand(3)); 1022 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1023 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1024 getIntPtrConstant(IncrementSize)); 1025 assert(isTypeLegal(Tmp2.getValueType()) && 1026 "Pointers must be legal!"); 1027 //Again, claiming both parts of the store came form the same Instr 1028 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1029 Node->getOperand(3)); 1030 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1031 break; 1032 } 1033 break; 1034 case ISD::PCMARKER: 1035 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1036 if (Tmp1 != Node->getOperand(0)) 1037 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 1038 break; 1039 case ISD::TRUNCSTORE: 1040 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1041 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1042 1043 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1044 case Legal: 1045 Tmp2 = LegalizeOp(Node->getOperand(1)); 1046 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1047 Tmp3 != Node->getOperand(2)) 1048 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1049 Node->getOperand(3), Node->getOperand(4)); 1050 break; 1051 case Promote: 1052 case Expand: 1053 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 1054 } 1055 break; 1056 case ISD::SELECT: 1057 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1058 case Expand: assert(0 && "It's impossible to expand bools"); 1059 case Legal: 1060 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1061 break; 1062 case Promote: 1063 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1064 break; 1065 } 1066 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1067 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1068 1069 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1070 default: assert(0 && "This action is not supported yet!"); 1071 case TargetLowering::Expand: 1072 if (Tmp1.getOpcode() == ISD::SETCC) { 1073 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1074 Tmp2, Tmp3, 1075 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1076 } else { 1077 // Make sure the condition is either zero or one. It may have been 1078 // promoted from something else. 1079 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1080 Result = DAG.getSelectCC(Tmp1, 1081 DAG.getConstant(0, Tmp1.getValueType()), 1082 Tmp2, Tmp3, ISD::SETNE); 1083 } 1084 break; 1085 case TargetLowering::Legal: 1086 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1087 Tmp3 != Node->getOperand(2)) 1088 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 1089 Tmp1, Tmp2, Tmp3); 1090 break; 1091 case TargetLowering::Promote: { 1092 MVT::ValueType NVT = 1093 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1094 unsigned ExtOp, TruncOp; 1095 if (MVT::isInteger(Tmp2.getValueType())) { 1096 ExtOp = ISD::ANY_EXTEND; 1097 TruncOp = ISD::TRUNCATE; 1098 } else { 1099 ExtOp = ISD::FP_EXTEND; 1100 TruncOp = ISD::FP_ROUND; 1101 } 1102 // Promote each of the values to the new type. 1103 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1104 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1105 // Perform the larger operation, then round down. 1106 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1107 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1108 break; 1109 } 1110 } 1111 break; 1112 case ISD::SELECT_CC: 1113 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1114 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1115 1116 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1117 // Everything is legal, see if we should expand this op or something. 1118 switch (TLI.getOperationAction(ISD::SELECT_CC, 1119 Node->getOperand(0).getValueType())) { 1120 default: assert(0 && "This action is not supported yet!"); 1121 case TargetLowering::Custom: { 1122 SDOperand Tmp = 1123 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), 1124 Node->getOperand(0), 1125 Node->getOperand(1), Tmp3, Tmp4, 1126 Node->getOperand(4)), DAG); 1127 if (Tmp.Val) { 1128 Result = LegalizeOp(Tmp); 1129 break; 1130 } 1131 } // FALLTHROUGH if the target can't lower this operation after all. 1132 case TargetLowering::Legal: 1133 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1134 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1135 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1136 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { 1137 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2, 1138 Tmp3, Tmp4, Node->getOperand(4)); 1139 } 1140 break; 1141 } 1142 break; 1143 } else { 1144 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1145 Node->getOperand(0), // LHS 1146 Node->getOperand(1), // RHS 1147 Node->getOperand(4))); 1148 // If we get a SETCC back from legalizing the SETCC node we just 1149 // created, then use its LHS, RHS, and CC directly in creating a new 1150 // node. Otherwise, select between the true and false value based on 1151 // comparing the result of the legalized with zero. 1152 if (Tmp1.getOpcode() == ISD::SETCC) { 1153 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1154 Tmp1.getOperand(0), Tmp1.getOperand(1), 1155 Tmp3, Tmp4, Tmp1.getOperand(2)); 1156 } else { 1157 Result = DAG.getSelectCC(Tmp1, 1158 DAG.getConstant(0, Tmp1.getValueType()), 1159 Tmp3, Tmp4, ISD::SETNE); 1160 } 1161 } 1162 break; 1163 case ISD::SETCC: 1164 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1165 case Legal: 1166 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1167 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1168 break; 1169 case Promote: 1170 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1171 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1172 1173 // If this is an FP compare, the operands have already been extended. 1174 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1175 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1176 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1177 1178 // Otherwise, we have to insert explicit sign or zero extends. Note 1179 // that we could insert sign extends for ALL conditions, but zero extend 1180 // is cheaper on many machines (an AND instead of two shifts), so prefer 1181 // it. 1182 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1183 default: assert(0 && "Unknown integer comparison!"); 1184 case ISD::SETEQ: 1185 case ISD::SETNE: 1186 case ISD::SETUGE: 1187 case ISD::SETUGT: 1188 case ISD::SETULE: 1189 case ISD::SETULT: 1190 // ALL of these operations will work if we either sign or zero extend 1191 // the operands (including the unsigned comparisons!). Zero extend is 1192 // usually a simpler/cheaper operation, so prefer it. 1193 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1194 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1195 break; 1196 case ISD::SETGE: 1197 case ISD::SETGT: 1198 case ISD::SETLT: 1199 case ISD::SETLE: 1200 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1201 DAG.getValueType(VT)); 1202 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1203 DAG.getValueType(VT)); 1204 break; 1205 } 1206 } 1207 break; 1208 case Expand: 1209 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1210 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1211 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1212 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1213 case ISD::SETEQ: 1214 case ISD::SETNE: 1215 if (RHSLo == RHSHi) 1216 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1217 if (RHSCST->isAllOnesValue()) { 1218 // Comparison to -1. 1219 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1220 Tmp2 = RHSLo; 1221 break; 1222 } 1223 1224 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1225 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1226 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1227 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1228 break; 1229 default: 1230 // If this is a comparison of the sign bit, just look at the top part. 1231 // X > -1, x < 0 1232 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1233 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1234 CST->getValue() == 0) || // X < 0 1235 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1236 (CST->isAllOnesValue()))) { // X > -1 1237 Tmp1 = LHSHi; 1238 Tmp2 = RHSHi; 1239 break; 1240 } 1241 1242 // FIXME: This generated code sucks. 1243 ISD::CondCode LowCC; 1244 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1245 default: assert(0 && "Unknown integer setcc!"); 1246 case ISD::SETLT: 1247 case ISD::SETULT: LowCC = ISD::SETULT; break; 1248 case ISD::SETGT: 1249 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1250 case ISD::SETLE: 1251 case ISD::SETULE: LowCC = ISD::SETULE; break; 1252 case ISD::SETGE: 1253 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1254 } 1255 1256 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1257 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1258 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1259 1260 // NOTE: on targets without efficient SELECT of bools, we can always use 1261 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1262 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1263 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1264 Node->getOperand(2)); 1265 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1266 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1267 Result, Tmp1, Tmp2)); 1268 return Result; 1269 } 1270 } 1271 1272 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) { 1273 default: 1274 assert(0 && "Cannot handle this action for SETCC yet!"); 1275 break; 1276 case TargetLowering::Promote: 1277 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1278 Node->getOperand(2)); 1279 break; 1280 case TargetLowering::Legal: 1281 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1282 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1283 Node->getOperand(2)); 1284 break; 1285 case TargetLowering::Expand: 1286 // Expand a setcc node into a select_cc of the same condition, lhs, and 1287 // rhs that selects between const 1 (true) and const 0 (false). 1288 MVT::ValueType VT = Node->getValueType(0); 1289 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1290 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1291 Node->getOperand(2)); 1292 Result = LegalizeOp(Result); 1293 break; 1294 } 1295 break; 1296 1297 case ISD::MEMSET: 1298 case ISD::MEMCPY: 1299 case ISD::MEMMOVE: { 1300 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1301 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1302 1303 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1304 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1305 case Expand: assert(0 && "Cannot expand a byte!"); 1306 case Legal: 1307 Tmp3 = LegalizeOp(Node->getOperand(2)); 1308 break; 1309 case Promote: 1310 Tmp3 = PromoteOp(Node->getOperand(2)); 1311 break; 1312 } 1313 } else { 1314 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1315 } 1316 1317 SDOperand Tmp4; 1318 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1319 case Expand: { 1320 // Length is too big, just take the lo-part of the length. 1321 SDOperand HiPart; 1322 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1323 break; 1324 } 1325 case Legal: 1326 Tmp4 = LegalizeOp(Node->getOperand(3)); 1327 break; 1328 case Promote: 1329 Tmp4 = PromoteOp(Node->getOperand(3)); 1330 break; 1331 } 1332 1333 SDOperand Tmp5; 1334 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1335 case Expand: assert(0 && "Cannot expand this yet!"); 1336 case Legal: 1337 Tmp5 = LegalizeOp(Node->getOperand(4)); 1338 break; 1339 case Promote: 1340 Tmp5 = PromoteOp(Node->getOperand(4)); 1341 break; 1342 } 1343 1344 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1345 default: assert(0 && "This action not implemented for this operation!"); 1346 case TargetLowering::Custom: { 1347 SDOperand Tmp = 1348 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 1349 Tmp2, Tmp3, Tmp4, Tmp5), DAG); 1350 if (Tmp.Val) { 1351 Result = LegalizeOp(Tmp); 1352 break; 1353 } 1354 // FALLTHROUGH if the target thinks it is legal. 1355 } 1356 case TargetLowering::Legal: 1357 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1358 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 1359 Tmp5 != Node->getOperand(4)) { 1360 std::vector<SDOperand> Ops; 1361 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 1362 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 1363 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 1364 } 1365 break; 1366 case TargetLowering::Expand: { 1367 // Otherwise, the target does not support this operation. Lower the 1368 // operation to an explicit libcall as appropriate. 1369 MVT::ValueType IntPtr = TLI.getPointerTy(); 1370 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1371 std::vector<std::pair<SDOperand, const Type*> > Args; 1372 1373 const char *FnName = 0; 1374 if (Node->getOpcode() == ISD::MEMSET) { 1375 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1376 // Extend the ubyte argument to be an int value for the call. 1377 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1378 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1379 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1380 1381 FnName = "memset"; 1382 } else if (Node->getOpcode() == ISD::MEMCPY || 1383 Node->getOpcode() == ISD::MEMMOVE) { 1384 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1385 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1386 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1387 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1388 } else { 1389 assert(0 && "Unknown op!"); 1390 } 1391 1392 std::pair<SDOperand,SDOperand> CallResult = 1393 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1394 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1395 Result = CallResult.second; 1396 NeedsAnotherIteration = true; 1397 break; 1398 } 1399 } 1400 break; 1401 } 1402 1403 case ISD::READPORT: 1404 Tmp1 = LegalizeOp(Node->getOperand(0)); 1405 Tmp2 = LegalizeOp(Node->getOperand(1)); 1406 1407 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1408 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1409 std::vector<SDOperand> Ops; 1410 Ops.push_back(Tmp1); 1411 Ops.push_back(Tmp2); 1412 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1413 } else 1414 Result = SDOperand(Node, 0); 1415 // Since these produce two values, make sure to remember that we legalized 1416 // both of them. 1417 AddLegalizedOperand(SDOperand(Node, 0), Result); 1418 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1419 return Result.getValue(Op.ResNo); 1420 case ISD::WRITEPORT: 1421 Tmp1 = LegalizeOp(Node->getOperand(0)); 1422 Tmp2 = LegalizeOp(Node->getOperand(1)); 1423 Tmp3 = LegalizeOp(Node->getOperand(2)); 1424 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1425 Tmp3 != Node->getOperand(2)) 1426 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1427 break; 1428 1429 case ISD::READIO: 1430 Tmp1 = LegalizeOp(Node->getOperand(0)); 1431 Tmp2 = LegalizeOp(Node->getOperand(1)); 1432 1433 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1434 case TargetLowering::Custom: 1435 default: assert(0 && "This action not implemented for this operation!"); 1436 case TargetLowering::Legal: 1437 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1438 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1439 std::vector<SDOperand> Ops; 1440 Ops.push_back(Tmp1); 1441 Ops.push_back(Tmp2); 1442 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1443 } else 1444 Result = SDOperand(Node, 0); 1445 break; 1446 case TargetLowering::Expand: 1447 // Replace this with a load from memory. 1448 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 1449 Node->getOperand(1), DAG.getSrcValue(NULL)); 1450 Result = LegalizeOp(Result); 1451 break; 1452 } 1453 1454 // Since these produce two values, make sure to remember that we legalized 1455 // both of them. 1456 AddLegalizedOperand(SDOperand(Node, 0), Result); 1457 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1458 return Result.getValue(Op.ResNo); 1459 1460 case ISD::WRITEIO: 1461 Tmp1 = LegalizeOp(Node->getOperand(0)); 1462 Tmp2 = LegalizeOp(Node->getOperand(1)); 1463 Tmp3 = LegalizeOp(Node->getOperand(2)); 1464 1465 switch (TLI.getOperationAction(Node->getOpcode(), 1466 Node->getOperand(1).getValueType())) { 1467 case TargetLowering::Custom: 1468 default: assert(0 && "This action not implemented for this operation!"); 1469 case TargetLowering::Legal: 1470 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1471 Tmp3 != Node->getOperand(2)) 1472 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1473 break; 1474 case TargetLowering::Expand: 1475 // Replace this with a store to memory. 1476 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 1477 Node->getOperand(1), Node->getOperand(2), 1478 DAG.getSrcValue(NULL)); 1479 Result = LegalizeOp(Result); 1480 break; 1481 } 1482 break; 1483 1484 case ISD::ADD_PARTS: 1485 case ISD::SUB_PARTS: 1486 case ISD::SHL_PARTS: 1487 case ISD::SRA_PARTS: 1488 case ISD::SRL_PARTS: { 1489 std::vector<SDOperand> Ops; 1490 bool Changed = false; 1491 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1492 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1493 Changed |= Ops.back() != Node->getOperand(i); 1494 } 1495 if (Changed) { 1496 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1497 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 1498 } 1499 1500 // Since these produce multiple values, make sure to remember that we 1501 // legalized all of them. 1502 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1503 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1504 return Result.getValue(Op.ResNo); 1505 } 1506 1507 // Binary operators 1508 case ISD::ADD: 1509 case ISD::SUB: 1510 case ISD::MUL: 1511 case ISD::MULHS: 1512 case ISD::MULHU: 1513 case ISD::UDIV: 1514 case ISD::SDIV: 1515 case ISD::AND: 1516 case ISD::OR: 1517 case ISD::XOR: 1518 case ISD::SHL: 1519 case ISD::SRL: 1520 case ISD::SRA: 1521 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1522 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1523 case Expand: assert(0 && "Not possible"); 1524 case Legal: 1525 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1526 break; 1527 case Promote: 1528 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 1529 break; 1530 } 1531 if (Tmp1 != Node->getOperand(0) || 1532 Tmp2 != Node->getOperand(1)) 1533 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 1534 break; 1535 1536 case ISD::UREM: 1537 case ISD::SREM: 1538 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1539 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1540 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1541 case TargetLowering::Legal: 1542 if (Tmp1 != Node->getOperand(0) || 1543 Tmp2 != Node->getOperand(1)) 1544 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1545 Tmp2); 1546 break; 1547 case TargetLowering::Promote: 1548 case TargetLowering::Custom: 1549 assert(0 && "Cannot promote/custom handle this yet!"); 1550 case TargetLowering::Expand: 1551 if (MVT::isInteger(Node->getValueType(0))) { 1552 MVT::ValueType VT = Node->getValueType(0); 1553 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 1554 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 1555 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 1556 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 1557 } else { 1558 // Floating point mod -> fmod libcall. 1559 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 1560 SDOperand Dummy; 1561 Result = ExpandLibCall(FnName, Node, Dummy); 1562 } 1563 break; 1564 } 1565 break; 1566 1567 case ISD::CTPOP: 1568 case ISD::CTTZ: 1569 case ISD::CTLZ: 1570 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1571 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1572 case TargetLowering::Legal: 1573 if (Tmp1 != Node->getOperand(0)) 1574 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1575 break; 1576 case TargetLowering::Promote: { 1577 MVT::ValueType OVT = Tmp1.getValueType(); 1578 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1579 1580 // Zero extend the argument. 1581 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1582 // Perform the larger operation, then subtract if needed. 1583 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1584 switch(Node->getOpcode()) 1585 { 1586 case ISD::CTPOP: 1587 Result = Tmp1; 1588 break; 1589 case ISD::CTTZ: 1590 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 1591 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 1592 DAG.getConstant(getSizeInBits(NVT), NVT), 1593 ISD::SETEQ); 1594 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 1595 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 1596 break; 1597 case ISD::CTLZ: 1598 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 1599 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 1600 DAG.getConstant(getSizeInBits(NVT) - 1601 getSizeInBits(OVT), NVT)); 1602 break; 1603 } 1604 break; 1605 } 1606 case TargetLowering::Custom: 1607 assert(0 && "Cannot custom handle this yet!"); 1608 case TargetLowering::Expand: 1609 switch(Node->getOpcode()) 1610 { 1611 case ISD::CTPOP: { 1612 static const uint64_t mask[6] = { 1613 0x5555555555555555ULL, 0x3333333333333333ULL, 1614 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 1615 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 1616 }; 1617 MVT::ValueType VT = Tmp1.getValueType(); 1618 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1619 unsigned len = getSizeInBits(VT); 1620 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1621 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 1622 Tmp2 = DAG.getConstant(mask[i], VT); 1623 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1624 Tmp1 = DAG.getNode(ISD::ADD, VT, 1625 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 1626 DAG.getNode(ISD::AND, VT, 1627 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 1628 Tmp2)); 1629 } 1630 Result = Tmp1; 1631 break; 1632 } 1633 case ISD::CTLZ: { 1634 /* for now, we do this: 1635 x = x | (x >> 1); 1636 x = x | (x >> 2); 1637 ... 1638 x = x | (x >>16); 1639 x = x | (x >>32); // for 64-bit input 1640 return popcount(~x); 1641 1642 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ 1643 MVT::ValueType VT = Tmp1.getValueType(); 1644 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1645 unsigned len = getSizeInBits(VT); 1646 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1647 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1648 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, 1649 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); 1650 } 1651 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); 1652 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1653 break; 1654 } 1655 case ISD::CTTZ: { 1656 // for now, we use: { return popcount(~x & (x - 1)); } 1657 // unless the target has ctlz but not ctpop, in which case we use: 1658 // { return 32 - nlz(~x & (x-1)); } 1659 // see also http://www.hackersdelight.org/HDcode/ntz.cc 1660 MVT::ValueType VT = Tmp1.getValueType(); 1661 Tmp2 = DAG.getConstant(~0ULL, VT); 1662 Tmp3 = DAG.getNode(ISD::AND, VT, 1663 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), 1664 DAG.getNode(ISD::SUB, VT, Tmp1, 1665 DAG.getConstant(1, VT))); 1666 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead 1667 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 1668 TLI.isOperationLegal(ISD::CTLZ, VT)) { 1669 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, 1670 DAG.getConstant(getSizeInBits(VT), VT), 1671 DAG.getNode(ISD::CTLZ, VT, Tmp3))); 1672 } else { 1673 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1674 } 1675 break; 1676 } 1677 default: 1678 assert(0 && "Cannot expand this yet!"); 1679 break; 1680 } 1681 break; 1682 } 1683 break; 1684 1685 // Unary operators 1686 case ISD::FABS: 1687 case ISD::FNEG: 1688 case ISD::FSQRT: 1689 case ISD::FSIN: 1690 case ISD::FCOS: 1691 Tmp1 = LegalizeOp(Node->getOperand(0)); 1692 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1693 case TargetLowering::Legal: 1694 if (Tmp1 != Node->getOperand(0)) 1695 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1696 break; 1697 case TargetLowering::Promote: 1698 case TargetLowering::Custom: 1699 assert(0 && "Cannot promote/custom handle this yet!"); 1700 case TargetLowering::Expand: 1701 switch(Node->getOpcode()) { 1702 case ISD::FNEG: { 1703 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 1704 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 1705 Result = LegalizeOp(DAG.getNode(ISD::SUB, Node->getValueType(0), 1706 Tmp2, Tmp1)); 1707 break; 1708 } 1709 case ISD::FABS: { 1710 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 1711 MVT::ValueType VT = Node->getValueType(0); 1712 Tmp2 = DAG.getConstantFP(0.0, VT); 1713 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 1714 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 1715 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 1716 Result = LegalizeOp(Result); 1717 break; 1718 } 1719 case ISD::FSQRT: 1720 case ISD::FSIN: 1721 case ISD::FCOS: { 1722 MVT::ValueType VT = Node->getValueType(0); 1723 const char *FnName = 0; 1724 switch(Node->getOpcode()) { 1725 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 1726 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 1727 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 1728 default: assert(0 && "Unreachable!"); 1729 } 1730 SDOperand Dummy; 1731 Result = ExpandLibCall(FnName, Node, Dummy); 1732 break; 1733 } 1734 default: 1735 assert(0 && "Unreachable!"); 1736 } 1737 break; 1738 } 1739 break; 1740 1741 // Conversion operators. The source and destination have different types. 1742 case ISD::SINT_TO_FP: 1743 case ISD::UINT_TO_FP: { 1744 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 1745 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1746 case Legal: 1747 switch (TLI.getOperationAction(Node->getOpcode(), 1748 Node->getOperand(0).getValueType())) { 1749 default: assert(0 && "Unknown operation action!"); 1750 case TargetLowering::Expand: 1751 Result = ExpandLegalINT_TO_FP(isSigned, 1752 LegalizeOp(Node->getOperand(0)), 1753 Node->getValueType(0)); 1754 AddLegalizedOperand(Op, Result); 1755 return Result; 1756 case TargetLowering::Promote: 1757 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 1758 Node->getValueType(0), 1759 isSigned); 1760 AddLegalizedOperand(Op, Result); 1761 return Result; 1762 case TargetLowering::Legal: 1763 break; 1764 } 1765 1766 Tmp1 = LegalizeOp(Node->getOperand(0)); 1767 if (Tmp1 != Node->getOperand(0)) 1768 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1769 break; 1770 case Expand: 1771 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 1772 Node->getValueType(0), Node->getOperand(0)); 1773 break; 1774 case Promote: 1775 if (isSigned) { 1776 Result = PromoteOp(Node->getOperand(0)); 1777 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1778 Result, DAG.getValueType(Node->getOperand(0).getValueType())); 1779 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 1780 } else { 1781 Result = PromoteOp(Node->getOperand(0)); 1782 Result = DAG.getZeroExtendInReg(Result, 1783 Node->getOperand(0).getValueType()); 1784 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 1785 } 1786 break; 1787 } 1788 break; 1789 } 1790 case ISD::TRUNCATE: 1791 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1792 case Legal: 1793 Tmp1 = LegalizeOp(Node->getOperand(0)); 1794 if (Tmp1 != Node->getOperand(0)) 1795 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1796 break; 1797 case Expand: 1798 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1799 1800 // Since the result is legal, we should just be able to truncate the low 1801 // part of the source. 1802 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 1803 break; 1804 case Promote: 1805 Result = PromoteOp(Node->getOperand(0)); 1806 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 1807 break; 1808 } 1809 break; 1810 1811 case ISD::FP_TO_SINT: 1812 case ISD::FP_TO_UINT: 1813 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1814 case Legal: 1815 Tmp1 = LegalizeOp(Node->getOperand(0)); 1816 1817 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 1818 default: assert(0 && "Unknown operation action!"); 1819 case TargetLowering::Expand: 1820 if (Node->getOpcode() == ISD::FP_TO_UINT) { 1821 SDOperand True, False; 1822 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1823 MVT::ValueType NVT = Node->getValueType(0); 1824 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 1825 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 1826 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 1827 Node->getOperand(0), Tmp2, ISD::SETLT); 1828 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 1829 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 1830 DAG.getNode(ISD::SUB, VT, Node->getOperand(0), 1831 Tmp2)); 1832 False = DAG.getNode(ISD::XOR, NVT, False, 1833 DAG.getConstant(1ULL << ShiftAmt, NVT)); 1834 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False)); 1835 return Result; 1836 } else { 1837 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 1838 } 1839 break; 1840 case TargetLowering::Promote: 1841 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 1842 Node->getOpcode() == ISD::FP_TO_SINT); 1843 AddLegalizedOperand(Op, Result); 1844 return Result; 1845 case TargetLowering::Custom: { 1846 SDOperand Tmp = 1847 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1848 Tmp = TLI.LowerOperation(Tmp, DAG); 1849 if (Tmp.Val) { 1850 AddLegalizedOperand(Op, Tmp); 1851 NeedsAnotherIteration = true; 1852 return Tmp; 1853 } else { 1854 // The target thinks this is legal afterall. 1855 break; 1856 } 1857 } 1858 case TargetLowering::Legal: 1859 break; 1860 } 1861 1862 if (Tmp1 != Node->getOperand(0)) 1863 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1864 break; 1865 case Expand: 1866 assert(0 && "Shouldn't need to expand other operators here!"); 1867 case Promote: 1868 Result = PromoteOp(Node->getOperand(0)); 1869 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 1870 break; 1871 } 1872 break; 1873 1874 case ISD::ANY_EXTEND: 1875 case ISD::ZERO_EXTEND: 1876 case ISD::SIGN_EXTEND: 1877 case ISD::FP_EXTEND: 1878 case ISD::FP_ROUND: 1879 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1880 case Legal: 1881 Tmp1 = LegalizeOp(Node->getOperand(0)); 1882 if (Tmp1 != Node->getOperand(0)) 1883 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1884 break; 1885 case Expand: 1886 assert(0 && "Shouldn't need to expand other operators here!"); 1887 1888 case Promote: 1889 switch (Node->getOpcode()) { 1890 case ISD::ANY_EXTEND: 1891 Result = PromoteOp(Node->getOperand(0)); 1892 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 1893 break; 1894 case ISD::ZERO_EXTEND: 1895 Result = PromoteOp(Node->getOperand(0)); 1896 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 1897 Result = DAG.getZeroExtendInReg(Result, 1898 Node->getOperand(0).getValueType()); 1899 break; 1900 case ISD::SIGN_EXTEND: 1901 Result = PromoteOp(Node->getOperand(0)); 1902 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 1903 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1904 Result, 1905 DAG.getValueType(Node->getOperand(0).getValueType())); 1906 break; 1907 case ISD::FP_EXTEND: 1908 Result = PromoteOp(Node->getOperand(0)); 1909 if (Result.getValueType() != Op.getValueType()) 1910 // Dynamically dead while we have only 2 FP types. 1911 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 1912 break; 1913 case ISD::FP_ROUND: 1914 Result = PromoteOp(Node->getOperand(0)); 1915 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 1916 break; 1917 } 1918 } 1919 break; 1920 case ISD::FP_ROUND_INREG: 1921 case ISD::SIGN_EXTEND_INREG: { 1922 Tmp1 = LegalizeOp(Node->getOperand(0)); 1923 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 1924 1925 // If this operation is not supported, convert it to a shl/shr or load/store 1926 // pair. 1927 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 1928 default: assert(0 && "This action not supported for this op yet!"); 1929 case TargetLowering::Legal: 1930 if (Tmp1 != Node->getOperand(0)) 1931 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1932 DAG.getValueType(ExtraVT)); 1933 break; 1934 case TargetLowering::Expand: 1935 // If this is an integer extend and shifts are supported, do that. 1936 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 1937 // NOTE: we could fall back on load/store here too for targets without 1938 // SAR. However, it is doubtful that any exist. 1939 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 1940 MVT::getSizeInBits(ExtraVT); 1941 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 1942 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 1943 Node->getOperand(0), ShiftCst); 1944 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 1945 Result, ShiftCst); 1946 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 1947 // The only way we can lower this is to turn it into a STORETRUNC, 1948 // EXTLOAD pair, targetting a temporary location (a stack slot). 1949 1950 // NOTE: there is a choice here between constantly creating new stack 1951 // slots and always reusing the same one. We currently always create 1952 // new ones, as reuse may inhibit scheduling. 1953 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 1954 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 1955 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 1956 MachineFunction &MF = DAG.getMachineFunction(); 1957 int SSFI = 1958 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 1959 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 1960 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 1961 Node->getOperand(0), StackSlot, 1962 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 1963 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1964 Result, StackSlot, DAG.getSrcValue(NULL), 1965 ExtraVT); 1966 } else { 1967 assert(0 && "Unknown op"); 1968 } 1969 Result = LegalizeOp(Result); 1970 break; 1971 } 1972 break; 1973 } 1974 } 1975 1976 // Note that LegalizeOp may be reentered even from single-use nodes, which 1977 // means that we always must cache transformed nodes. 1978 AddLegalizedOperand(Op, Result); 1979 return Result; 1980} 1981 1982/// PromoteOp - Given an operation that produces a value in an invalid type, 1983/// promote it to compute the value into a larger type. The produced value will 1984/// have the correct bits for the low portion of the register, but no guarantee 1985/// is made about the top bits: it may be zero, sign-extended, or garbage. 1986SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 1987 MVT::ValueType VT = Op.getValueType(); 1988 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1989 assert(getTypeAction(VT) == Promote && 1990 "Caller should expand or legalize operands that are not promotable!"); 1991 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 1992 "Cannot promote to smaller type!"); 1993 1994 SDOperand Tmp1, Tmp2, Tmp3; 1995 1996 SDOperand Result; 1997 SDNode *Node = Op.Val; 1998 1999 if (1 || !Node->hasOneUse()) { 2000 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2001 if (I != PromotedNodes.end()) return I->second; 2002 } else { 2003 assert(!PromotedNodes.count(Op) && "Repromoted this node??"); 2004 } 2005 2006 // Promotion needs an optimization step to clean up after it, and is not 2007 // careful to avoid operations the target does not support. Make sure that 2008 // all generated operations are legalized in the next iteration. 2009 NeedsAnotherIteration = true; 2010 2011 switch (Node->getOpcode()) { 2012 case ISD::CopyFromReg: 2013 assert(0 && "CopyFromReg must be legal!"); 2014 default: 2015 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2016 assert(0 && "Do not know how to promote this operator!"); 2017 abort(); 2018 case ISD::UNDEF: 2019 Result = DAG.getNode(ISD::UNDEF, NVT); 2020 break; 2021 case ISD::Constant: 2022 if (VT != MVT::i1) 2023 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2024 else 2025 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2026 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2027 break; 2028 case ISD::ConstantFP: 2029 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2030 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2031 break; 2032 2033 case ISD::SETCC: 2034 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2035 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2036 Node->getOperand(1), Node->getOperand(2)); 2037 Result = LegalizeOp(Result); 2038 break; 2039 2040 case ISD::TRUNCATE: 2041 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2042 case Legal: 2043 Result = LegalizeOp(Node->getOperand(0)); 2044 assert(Result.getValueType() >= NVT && 2045 "This truncation doesn't make sense!"); 2046 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2047 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2048 break; 2049 case Promote: 2050 // The truncation is not required, because we don't guarantee anything 2051 // about high bits anyway. 2052 Result = PromoteOp(Node->getOperand(0)); 2053 break; 2054 case Expand: 2055 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2056 // Truncate the low part of the expanded value to the result type 2057 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2058 } 2059 break; 2060 case ISD::SIGN_EXTEND: 2061 case ISD::ZERO_EXTEND: 2062 case ISD::ANY_EXTEND: 2063 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2064 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2065 case Legal: 2066 // Input is legal? Just do extend all the way to the larger type. 2067 Result = LegalizeOp(Node->getOperand(0)); 2068 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2069 break; 2070 case Promote: 2071 // Promote the reg if it's smaller. 2072 Result = PromoteOp(Node->getOperand(0)); 2073 // The high bits are not guaranteed to be anything. Insert an extend. 2074 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2075 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2076 DAG.getValueType(Node->getOperand(0).getValueType())); 2077 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2078 Result = DAG.getZeroExtendInReg(Result, 2079 Node->getOperand(0).getValueType()); 2080 break; 2081 } 2082 break; 2083 2084 case ISD::FP_EXTEND: 2085 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2086 case ISD::FP_ROUND: 2087 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2088 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2089 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2090 case Legal: 2091 // Input is legal? Do an FP_ROUND_INREG. 2092 Result = LegalizeOp(Node->getOperand(0)); 2093 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2094 DAG.getValueType(VT)); 2095 break; 2096 } 2097 break; 2098 2099 case ISD::SINT_TO_FP: 2100 case ISD::UINT_TO_FP: 2101 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2102 case Legal: 2103 Result = LegalizeOp(Node->getOperand(0)); 2104 // No extra round required here. 2105 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2106 break; 2107 2108 case Promote: 2109 Result = PromoteOp(Node->getOperand(0)); 2110 if (Node->getOpcode() == ISD::SINT_TO_FP) 2111 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2112 Result, 2113 DAG.getValueType(Node->getOperand(0).getValueType())); 2114 else 2115 Result = DAG.getZeroExtendInReg(Result, 2116 Node->getOperand(0).getValueType()); 2117 // No extra round required here. 2118 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2119 break; 2120 case Expand: 2121 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2122 Node->getOperand(0)); 2123 // Round if we cannot tolerate excess precision. 2124 if (NoExcessFPPrecision) 2125 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2126 DAG.getValueType(VT)); 2127 break; 2128 } 2129 break; 2130 2131 case ISD::FP_TO_SINT: 2132 case ISD::FP_TO_UINT: 2133 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2134 case Legal: 2135 Tmp1 = LegalizeOp(Node->getOperand(0)); 2136 break; 2137 case Promote: 2138 // The input result is prerounded, so we don't have to do anything 2139 // special. 2140 Tmp1 = PromoteOp(Node->getOperand(0)); 2141 break; 2142 case Expand: 2143 assert(0 && "not implemented"); 2144 } 2145 // If we're promoting a UINT to a larger size, check to see if the new node 2146 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2147 // we can use that instead. This allows us to generate better code for 2148 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2149 // legal, such as PowerPC. 2150 if (Node->getOpcode() == ISD::FP_TO_UINT && 2151 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2152 TLI.isOperationLegal(ISD::FP_TO_SINT, NVT)) { 2153 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2154 } else { 2155 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2156 } 2157 break; 2158 2159 case ISD::FABS: 2160 case ISD::FNEG: 2161 Tmp1 = PromoteOp(Node->getOperand(0)); 2162 assert(Tmp1.getValueType() == NVT); 2163 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2164 // NOTE: we do not have to do any extra rounding here for 2165 // NoExcessFPPrecision, because we know the input will have the appropriate 2166 // precision, and these operations don't modify precision at all. 2167 break; 2168 2169 case ISD::FSQRT: 2170 case ISD::FSIN: 2171 case ISD::FCOS: 2172 Tmp1 = PromoteOp(Node->getOperand(0)); 2173 assert(Tmp1.getValueType() == NVT); 2174 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2175 if(NoExcessFPPrecision) 2176 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2177 DAG.getValueType(VT)); 2178 break; 2179 2180 case ISD::AND: 2181 case ISD::OR: 2182 case ISD::XOR: 2183 case ISD::ADD: 2184 case ISD::SUB: 2185 case ISD::MUL: 2186 // The input may have strange things in the top bits of the registers, but 2187 // these operations don't care. They may have wierd bits going out, but 2188 // that too is okay if they are integer operations. 2189 Tmp1 = PromoteOp(Node->getOperand(0)); 2190 Tmp2 = PromoteOp(Node->getOperand(1)); 2191 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2192 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2193 2194 // However, if this is a floating point operation, they will give excess 2195 // precision that we may not be able to tolerate. If we DO allow excess 2196 // precision, just leave it, otherwise excise it. 2197 // FIXME: Why would we need to round FP ops more than integer ones? 2198 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2199 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2200 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2201 DAG.getValueType(VT)); 2202 break; 2203 2204 case ISD::SDIV: 2205 case ISD::SREM: 2206 // These operators require that their input be sign extended. 2207 Tmp1 = PromoteOp(Node->getOperand(0)); 2208 Tmp2 = PromoteOp(Node->getOperand(1)); 2209 if (MVT::isInteger(NVT)) { 2210 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2211 DAG.getValueType(VT)); 2212 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2213 DAG.getValueType(VT)); 2214 } 2215 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2216 2217 // Perform FP_ROUND: this is probably overly pessimistic. 2218 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2219 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2220 DAG.getValueType(VT)); 2221 break; 2222 2223 case ISD::UDIV: 2224 case ISD::UREM: 2225 // These operators require that their input be zero extended. 2226 Tmp1 = PromoteOp(Node->getOperand(0)); 2227 Tmp2 = PromoteOp(Node->getOperand(1)); 2228 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2229 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2230 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2231 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2232 break; 2233 2234 case ISD::SHL: 2235 Tmp1 = PromoteOp(Node->getOperand(0)); 2236 Tmp2 = LegalizeOp(Node->getOperand(1)); 2237 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 2238 break; 2239 case ISD::SRA: 2240 // The input value must be properly sign extended. 2241 Tmp1 = PromoteOp(Node->getOperand(0)); 2242 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2243 DAG.getValueType(VT)); 2244 Tmp2 = LegalizeOp(Node->getOperand(1)); 2245 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 2246 break; 2247 case ISD::SRL: 2248 // The input value must be properly zero extended. 2249 Tmp1 = PromoteOp(Node->getOperand(0)); 2250 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2251 Tmp2 = LegalizeOp(Node->getOperand(1)); 2252 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 2253 break; 2254 case ISD::LOAD: 2255 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2256 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2257 // FIXME: When the DAG combiner exists, change this to use EXTLOAD! 2258 if (MVT::isInteger(NVT)) 2259 Result = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Tmp1, Tmp2, 2260 Node->getOperand(2), VT); 2261 else 2262 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2, 2263 Node->getOperand(2), VT); 2264 2265 // Remember that we legalized the chain. 2266 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2267 break; 2268 case ISD::SELECT: 2269 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2270 case Expand: assert(0 && "It's impossible to expand bools"); 2271 case Legal: 2272 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 2273 break; 2274 case Promote: 2275 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2276 break; 2277 } 2278 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 2279 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 2280 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 2281 break; 2282 case ISD::SELECT_CC: 2283 Tmp2 = PromoteOp(Node->getOperand(2)); // True 2284 Tmp3 = PromoteOp(Node->getOperand(3)); // False 2285 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 2286 Node->getOperand(1), Tmp2, Tmp3, 2287 Node->getOperand(4)); 2288 break; 2289 case ISD::TAILCALL: 2290 case ISD::CALL: { 2291 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2292 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 2293 2294 std::vector<SDOperand> Ops; 2295 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 2296 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2297 2298 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 2299 "Can only promote single result calls"); 2300 std::vector<MVT::ValueType> RetTyVTs; 2301 RetTyVTs.reserve(2); 2302 RetTyVTs.push_back(NVT); 2303 RetTyVTs.push_back(MVT::Other); 2304 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 2305 Node->getOpcode() == ISD::TAILCALL); 2306 Result = SDOperand(NC, 0); 2307 2308 // Insert the new chain mapping. 2309 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2310 break; 2311 } 2312 case ISD::CTPOP: 2313 case ISD::CTTZ: 2314 case ISD::CTLZ: 2315 Tmp1 = Node->getOperand(0); 2316 //Zero extend the argument 2317 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2318 // Perform the larger operation, then subtract if needed. 2319 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2320 switch(Node->getOpcode()) 2321 { 2322 case ISD::CTPOP: 2323 Result = Tmp1; 2324 break; 2325 case ISD::CTTZ: 2326 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2327 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2328 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 2329 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2330 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 2331 break; 2332 case ISD::CTLZ: 2333 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2334 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2335 DAG.getConstant(getSizeInBits(NVT) - 2336 getSizeInBits(VT), NVT)); 2337 break; 2338 } 2339 break; 2340 } 2341 2342 assert(Result.Val && "Didn't set a result!"); 2343 AddPromotedOperand(Op, Result); 2344 return Result; 2345} 2346 2347/// ExpandAddSub - Find a clever way to expand this add operation into 2348/// subcomponents. 2349void SelectionDAGLegalize:: 2350ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 2351 SDOperand &Lo, SDOperand &Hi) { 2352 // Expand the subcomponents. 2353 SDOperand LHSL, LHSH, RHSL, RHSH; 2354 ExpandOp(LHS, LHSL, LHSH); 2355 ExpandOp(RHS, RHSL, RHSH); 2356 2357 // FIXME: this should be moved to the dag combiner someday. 2358 assert(NodeOp == ISD::ADD_PARTS || NodeOp == ISD::SUB_PARTS); 2359 if (LHSL.getValueType() == MVT::i32) { 2360 SDOperand LowEl; 2361 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHSL)) 2362 if (C->getValue() == 0) 2363 LowEl = RHSL; 2364 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHSL)) 2365 if (C->getValue() == 0) 2366 LowEl = LHSL; 2367 if (LowEl.Val) { 2368 // Turn this into an add/sub of the high part only. 2369 SDOperand HiEl = 2370 DAG.getNode(NodeOp == ISD::ADD_PARTS ? ISD::ADD : ISD::SUB, 2371 LowEl.getValueType(), LHSH, RHSH); 2372 Lo = LowEl; 2373 Hi = HiEl; 2374 return; 2375 } 2376 } 2377 2378 std::vector<SDOperand> Ops; 2379 Ops.push_back(LHSL); 2380 Ops.push_back(LHSH); 2381 Ops.push_back(RHSL); 2382 Ops.push_back(RHSH); 2383 2384 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2385 Lo = DAG.getNode(NodeOp, VTs, Ops); 2386 Hi = Lo.getValue(1); 2387} 2388 2389void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 2390 SDOperand Op, SDOperand Amt, 2391 SDOperand &Lo, SDOperand &Hi) { 2392 // Expand the subcomponents. 2393 SDOperand LHSL, LHSH; 2394 ExpandOp(Op, LHSL, LHSH); 2395 2396 std::vector<SDOperand> Ops; 2397 Ops.push_back(LHSL); 2398 Ops.push_back(LHSH); 2399 Ops.push_back(Amt); 2400 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2401 Lo = DAG.getNode(NodeOp, VTs, Ops); 2402 Hi = Lo.getValue(1); 2403} 2404 2405 2406/// ExpandShift - Try to find a clever way to expand this shift operation out to 2407/// smaller elements. If we can't find a way that is more efficient than a 2408/// libcall on this target, return false. Otherwise, return true with the 2409/// low-parts expanded into Lo and Hi. 2410bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 2411 SDOperand &Lo, SDOperand &Hi) { 2412 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 2413 "This is not a shift!"); 2414 2415 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 2416 SDOperand ShAmt = LegalizeOp(Amt); 2417 MVT::ValueType ShTy = ShAmt.getValueType(); 2418 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 2419 unsigned NVTBits = MVT::getSizeInBits(NVT); 2420 2421 // Handle the case when Amt is an immediate. Other cases are currently broken 2422 // and are disabled. 2423 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 2424 unsigned Cst = CN->getValue(); 2425 // Expand the incoming operand to be shifted, so that we have its parts 2426 SDOperand InL, InH; 2427 ExpandOp(Op, InL, InH); 2428 switch(Opc) { 2429 case ISD::SHL: 2430 if (Cst > VTBits) { 2431 Lo = DAG.getConstant(0, NVT); 2432 Hi = DAG.getConstant(0, NVT); 2433 } else if (Cst > NVTBits) { 2434 Lo = DAG.getConstant(0, NVT); 2435 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 2436 } else if (Cst == NVTBits) { 2437 Lo = DAG.getConstant(0, NVT); 2438 Hi = InL; 2439 } else { 2440 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 2441 Hi = DAG.getNode(ISD::OR, NVT, 2442 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 2443 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 2444 } 2445 return true; 2446 case ISD::SRL: 2447 if (Cst > VTBits) { 2448 Lo = DAG.getConstant(0, NVT); 2449 Hi = DAG.getConstant(0, NVT); 2450 } else if (Cst > NVTBits) { 2451 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 2452 Hi = DAG.getConstant(0, NVT); 2453 } else if (Cst == NVTBits) { 2454 Lo = InH; 2455 Hi = DAG.getConstant(0, NVT); 2456 } else { 2457 Lo = DAG.getNode(ISD::OR, NVT, 2458 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2459 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2460 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 2461 } 2462 return true; 2463 case ISD::SRA: 2464 if (Cst > VTBits) { 2465 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 2466 DAG.getConstant(NVTBits-1, ShTy)); 2467 } else if (Cst > NVTBits) { 2468 Lo = DAG.getNode(ISD::SRA, NVT, InH, 2469 DAG.getConstant(Cst-NVTBits, ShTy)); 2470 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2471 DAG.getConstant(NVTBits-1, ShTy)); 2472 } else if (Cst == NVTBits) { 2473 Lo = InH; 2474 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2475 DAG.getConstant(NVTBits-1, ShTy)); 2476 } else { 2477 Lo = DAG.getNode(ISD::OR, NVT, 2478 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2479 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2480 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 2481 } 2482 return true; 2483 } 2484 } 2485 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 2486 // so disable it for now. Currently targets are handling this via SHL_PARTS 2487 // and friends. 2488 return false; 2489 2490 // If we have an efficient select operation (or if the selects will all fold 2491 // away), lower to some complex code, otherwise just emit the libcall. 2492 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt)) 2493 return false; 2494 2495 SDOperand InL, InH; 2496 ExpandOp(Op, InL, InH); 2497 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 2498 DAG.getConstant(NVTBits, ShTy), ShAmt); 2499 2500 // Compare the unmasked shift amount against 32. 2501 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt, 2502 DAG.getConstant(NVTBits, ShTy), ISD::SETGE); 2503 2504 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 2505 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 2506 DAG.getConstant(NVTBits-1, ShTy)); 2507 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 2508 DAG.getConstant(NVTBits-1, ShTy)); 2509 } 2510 2511 if (Opc == ISD::SHL) { 2512 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 2513 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 2514 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 2515 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 2516 2517 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2518 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 2519 } else { 2520 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 2521 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt, 2522 DAG.getConstant(32, ShTy), 2523 ISD::SETEQ), 2524 DAG.getConstant(0, NVT), 2525 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 2526 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 2527 HiLoPart, 2528 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 2529 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 2530 2531 SDOperand HiPart; 2532 if (Opc == ISD::SRA) 2533 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 2534 DAG.getConstant(NVTBits-1, ShTy)); 2535 else 2536 HiPart = DAG.getConstant(0, NVT); 2537 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2538 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 2539 } 2540 return true; 2541} 2542 2543/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 2544/// NodeDepth) node that is an CallSeqStart operation and occurs later than 2545/// Found. 2546static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) { 2547 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 2548 2549 // If we found an CALLSEQ_START, we already know this node occurs later 2550 // than the Found node. Just remember this node and return. 2551 if (Node->getOpcode() == ISD::CALLSEQ_START) { 2552 Found = Node; 2553 return; 2554 } 2555 2556 // Otherwise, scan the operands of Node to see if any of them is a call. 2557 assert(Node->getNumOperands() != 0 && 2558 "All leaves should have depth equal to the entry node!"); 2559 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 2560 FindLatestCallSeqStart(Node->getOperand(i).Val, Found); 2561 2562 // Tail recurse for the last iteration. 2563 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 2564 Found); 2565} 2566 2567 2568/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 2569/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 2570/// than Found. 2571static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 2572 std::set<SDNode*> &Visited) { 2573 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 2574 !Visited.insert(Node).second) return; 2575 2576 // If we found an CALLSEQ_END, we already know this node occurs earlier 2577 // than the Found node. Just remember this node and return. 2578 if (Node->getOpcode() == ISD::CALLSEQ_END) { 2579 Found = Node; 2580 return; 2581 } 2582 2583 // Otherwise, scan the operands of Node to see if any of them is a call. 2584 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 2585 if (UI == E) return; 2586 for (--E; UI != E; ++UI) 2587 FindEarliestCallSeqEnd(*UI, Found, Visited); 2588 2589 // Tail recurse for the last iteration. 2590 FindEarliestCallSeqEnd(*UI, Found, Visited); 2591} 2592 2593/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 2594/// find the CALLSEQ_END node that terminates the call sequence. 2595static SDNode *FindCallSeqEnd(SDNode *Node) { 2596 if (Node->getOpcode() == ISD::CALLSEQ_END) 2597 return Node; 2598 if (Node->use_empty()) 2599 return 0; // No CallSeqEnd 2600 2601 if (Node->hasOneUse()) // Simple case, only has one user to check. 2602 return FindCallSeqEnd(*Node->use_begin()); 2603 2604 SDOperand TheChain(Node, Node->getNumValues()-1); 2605 if (TheChain.getValueType() != MVT::Other) 2606 TheChain = SDOperand(Node, 0); 2607 assert(TheChain.getValueType() == MVT::Other && "Is not a token chain!"); 2608 2609 for (SDNode::use_iterator UI = Node->use_begin(), 2610 E = Node->use_end(); UI != E; ++UI) { 2611 2612 // Make sure to only follow users of our token chain. 2613 SDNode *User = *UI; 2614 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 2615 if (User->getOperand(i) == TheChain) 2616 if (SDNode *Result = FindCallSeqEnd(User)) 2617 return Result; 2618 } 2619 return 0; 2620} 2621 2622/// FindCallSeqStart - Given a chained node that is part of a call sequence, 2623/// find the CALLSEQ_START node that initiates the call sequence. 2624static SDNode *FindCallSeqStart(SDNode *Node) { 2625 assert(Node && "Didn't find callseq_start for a call??"); 2626 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 2627 2628 assert(Node->getOperand(0).getValueType() == MVT::Other && 2629 "Node doesn't have a token chain argument!"); 2630 return FindCallSeqStart(Node->getOperand(0).Val); 2631} 2632 2633 2634/// FindInputOutputChains - If we are replacing an operation with a call we need 2635/// to find the call that occurs before and the call that occurs after it to 2636/// properly serialize the calls in the block. The returned operand is the 2637/// input chain value for the new call (e.g. the entry node or the previous 2638/// call), and OutChain is set to be the chain node to update to point to the 2639/// end of the call chain. 2640static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 2641 SDOperand Entry) { 2642 SDNode *LatestCallSeqStart = Entry.Val; 2643 SDNode *LatestCallSeqEnd = 0; 2644 FindLatestCallSeqStart(OpNode, LatestCallSeqStart); 2645 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 2646 2647 // It is possible that no ISD::CALLSEQ_START was found because there is no 2648 // previous call in the function. LatestCallStackDown may in that case be 2649 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 2650 // unless LatestCallStackDown is an CALLSEQ_START. 2651 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) 2652 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 2653 else 2654 LatestCallSeqEnd = Entry.Val; 2655 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 2656 2657 // Finally, find the first call that this must come before, first we find the 2658 // CallSeqEnd that ends the call. 2659 OutChain = 0; 2660 std::set<SDNode*> Visited; 2661 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 2662 2663 // If we found one, translate from the adj up to the callseq_start. 2664 if (OutChain) 2665 OutChain = FindCallSeqStart(OutChain); 2666 2667 return SDOperand(LatestCallSeqEnd, 0); 2668} 2669 2670/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 2671void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 2672 SDNode *OutChain) { 2673 // Nothing to splice it into? 2674 if (OutChain == 0) return; 2675 2676 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 2677 //OutChain->dump(); 2678 2679 // Form a token factor node merging the old inval and the new inval. 2680 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 2681 OutChain->getOperand(0)); 2682 // Change the node to refer to the new token. 2683 OutChain->setAdjCallChain(InToken); 2684} 2685 2686 2687// ExpandLibCall - Expand a node into a call to a libcall. If the result value 2688// does not fit into a register, return the lo part and set the hi part to the 2689// by-reg argument. If it does fit into a single register, return the result 2690// and leave the Hi part unset. 2691SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 2692 SDOperand &Hi) { 2693 SDNode *OutChain; 2694 SDOperand InChain = FindInputOutputChains(Node, OutChain, 2695 DAG.getEntryNode()); 2696 if (InChain.Val == 0) 2697 InChain = DAG.getEntryNode(); 2698 2699 TargetLowering::ArgListTy Args; 2700 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2701 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 2702 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 2703 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 2704 } 2705 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 2706 2707 // Splice the libcall in wherever FindInputOutputChains tells us to. 2708 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 2709 std::pair<SDOperand,SDOperand> CallInfo = 2710 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 2711 Callee, Args, DAG); 2712 2713 SDOperand Result; 2714 switch (getTypeAction(CallInfo.first.getValueType())) { 2715 default: assert(0 && "Unknown thing"); 2716 case Legal: 2717 Result = CallInfo.first; 2718 break; 2719 case Promote: 2720 assert(0 && "Cannot promote this yet!"); 2721 case Expand: 2722 ExpandOp(CallInfo.first, Result, Hi); 2723 CallInfo.second = LegalizeOp(CallInfo.second); 2724 break; 2725 } 2726 2727 SpliceCallInto(CallInfo.second, OutChain); 2728 NeedsAnotherIteration = true; 2729 return Result; 2730} 2731 2732 2733/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 2734/// destination type is legal. 2735SDOperand SelectionDAGLegalize:: 2736ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 2737 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 2738 assert(getTypeAction(Source.getValueType()) == Expand && 2739 "This is not an expansion!"); 2740 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 2741 2742 if (!isSigned) { 2743 assert(Source.getValueType() == MVT::i64 && 2744 "This only works for 64-bit -> FP"); 2745 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 2746 // incoming integer is set. To handle this, we dynamically test to see if 2747 // it is set, and, if so, add a fudge factor. 2748 SDOperand Lo, Hi; 2749 ExpandOp(Source, Lo, Hi); 2750 2751 // If this is unsigned, and not supported, first perform the conversion to 2752 // signed, then adjust the result if the sign bit is set. 2753 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 2754 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 2755 2756 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 2757 DAG.getConstant(0, Hi.getValueType()), 2758 ISD::SETLT); 2759 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 2760 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 2761 SignSet, Four, Zero); 2762 uint64_t FF = 0x5f800000ULL; 2763 if (TLI.isLittleEndian()) FF <<= 32; 2764 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 2765 2766 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2767 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 2768 SDOperand FudgeInReg; 2769 if (DestTy == MVT::f32) 2770 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 2771 DAG.getSrcValue(NULL)); 2772 else { 2773 assert(DestTy == MVT::f64 && "Unexpected conversion"); 2774 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 2775 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 2776 } 2777 return DAG.getNode(ISD::ADD, DestTy, SignedConv, FudgeInReg); 2778 } 2779 2780 // Check to see if the target has a custom way to lower this. If so, use it. 2781 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 2782 default: assert(0 && "This action not implemented for this operation!"); 2783 case TargetLowering::Legal: 2784 case TargetLowering::Expand: 2785 break; // This case is handled below. 2786 case TargetLowering::Custom: { 2787 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 2788 Source), DAG); 2789 if (NV.Val) 2790 return LegalizeOp(NV); 2791 break; // The target decided this was legal after all 2792 } 2793 } 2794 2795 // Expand the source, then glue it back together for the call. We must expand 2796 // the source in case it is shared (this pass of legalize must traverse it). 2797 SDOperand SrcLo, SrcHi; 2798 ExpandOp(Source, SrcLo, SrcHi); 2799 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 2800 2801 SDNode *OutChain = 0; 2802 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 2803 DAG.getEntryNode()); 2804 const char *FnName = 0; 2805 if (DestTy == MVT::f32) 2806 FnName = "__floatdisf"; 2807 else { 2808 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 2809 FnName = "__floatdidf"; 2810 } 2811 2812 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 2813 2814 TargetLowering::ArgListTy Args; 2815 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 2816 2817 Args.push_back(std::make_pair(Source, ArgTy)); 2818 2819 // We don't care about token chains for libcalls. We just use the entry 2820 // node as our input and ignore the output chain. This allows us to place 2821 // calls wherever we need them to satisfy data dependences. 2822 const Type *RetTy = MVT::getTypeForValueType(DestTy); 2823 2824 std::pair<SDOperand,SDOperand> CallResult = 2825 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 2826 Callee, Args, DAG); 2827 2828 SpliceCallInto(CallResult.second, OutChain); 2829 return CallResult.first; 2830} 2831 2832 2833 2834/// ExpandOp - Expand the specified SDOperand into its two component pieces 2835/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 2836/// LegalizeNodes map is filled in for any results that are not expanded, the 2837/// ExpandedNodes map is filled in for any results that are expanded, and the 2838/// Lo/Hi values are returned. 2839void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 2840 MVT::ValueType VT = Op.getValueType(); 2841 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2842 SDNode *Node = Op.Val; 2843 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 2844 assert(MVT::isInteger(VT) && "Cannot expand FP values!"); 2845 assert(MVT::isInteger(NVT) && NVT < VT && 2846 "Cannot expand to FP value or to larger int value!"); 2847 2848 // If there is more than one use of this, see if we already expanded it. 2849 // There is no use remembering values that only have a single use, as the map 2850 // entries will never be reused. 2851 if (1 || !Node->hasOneUse()) { 2852 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 2853 = ExpandedNodes.find(Op); 2854 if (I != ExpandedNodes.end()) { 2855 Lo = I->second.first; 2856 Hi = I->second.second; 2857 return; 2858 } 2859 } else { 2860 assert(!ExpandedNodes.count(Op) && "Re-expanding a node!"); 2861 } 2862 2863 // Expanding to multiple registers needs to perform an optimization step, and 2864 // is not careful to avoid operations the target does not support. Make sure 2865 // that all generated operations are legalized in the next iteration. 2866 NeedsAnotherIteration = true; 2867 2868 switch (Node->getOpcode()) { 2869 case ISD::CopyFromReg: 2870 assert(0 && "CopyFromReg must be legal!"); 2871 default: 2872 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2873 assert(0 && "Do not know how to expand this operator!"); 2874 abort(); 2875 case ISD::UNDEF: 2876 Lo = DAG.getNode(ISD::UNDEF, NVT); 2877 Hi = DAG.getNode(ISD::UNDEF, NVT); 2878 break; 2879 case ISD::Constant: { 2880 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 2881 Lo = DAG.getConstant(Cst, NVT); 2882 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 2883 break; 2884 } 2885 2886 case ISD::BUILD_PAIR: 2887 // Legalize both operands. FIXME: in the future we should handle the case 2888 // where the two elements are not legal. 2889 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 2890 Lo = LegalizeOp(Node->getOperand(0)); 2891 Hi = LegalizeOp(Node->getOperand(1)); 2892 break; 2893 2894 case ISD::CTPOP: 2895 ExpandOp(Node->getOperand(0), Lo, Hi); 2896 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 2897 DAG.getNode(ISD::CTPOP, NVT, Lo), 2898 DAG.getNode(ISD::CTPOP, NVT, Hi)); 2899 Hi = DAG.getConstant(0, NVT); 2900 break; 2901 2902 case ISD::CTLZ: { 2903 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 2904 ExpandOp(Node->getOperand(0), Lo, Hi); 2905 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 2906 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 2907 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 2908 ISD::SETNE); 2909 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 2910 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 2911 2912 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 2913 Hi = DAG.getConstant(0, NVT); 2914 break; 2915 } 2916 2917 case ISD::CTTZ: { 2918 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 2919 ExpandOp(Node->getOperand(0), Lo, Hi); 2920 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 2921 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 2922 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 2923 ISD::SETNE); 2924 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 2925 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 2926 2927 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 2928 Hi = DAG.getConstant(0, NVT); 2929 break; 2930 } 2931 2932 case ISD::LOAD: { 2933 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2934 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2935 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 2936 2937 // Increment the pointer to the other half. 2938 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 2939 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2940 getIntPtrConstant(IncrementSize)); 2941 //Is this safe? declaring that the two parts of the split load 2942 //are from the same instruction? 2943 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 2944 2945 // Build a factor node to remember that this load is independent of the 2946 // other one. 2947 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2948 Hi.getValue(1)); 2949 2950 // Remember that we legalized the chain. 2951 AddLegalizedOperand(Op.getValue(1), TF); 2952 if (!TLI.isLittleEndian()) 2953 std::swap(Lo, Hi); 2954 break; 2955 } 2956 case ISD::TAILCALL: 2957 case ISD::CALL: { 2958 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2959 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 2960 2961 bool Changed = false; 2962 std::vector<SDOperand> Ops; 2963 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 2964 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2965 Changed |= Ops.back() != Node->getOperand(i); 2966 } 2967 2968 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 2969 "Can only expand a call once so far, not i64 -> i16!"); 2970 2971 std::vector<MVT::ValueType> RetTyVTs; 2972 RetTyVTs.reserve(3); 2973 RetTyVTs.push_back(NVT); 2974 RetTyVTs.push_back(NVT); 2975 RetTyVTs.push_back(MVT::Other); 2976 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops, 2977 Node->getOpcode() == ISD::TAILCALL); 2978 Lo = SDOperand(NC, 0); 2979 Hi = SDOperand(NC, 1); 2980 2981 // Insert the new chain mapping. 2982 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 2983 break; 2984 } 2985 case ISD::AND: 2986 case ISD::OR: 2987 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 2988 SDOperand LL, LH, RL, RH; 2989 ExpandOp(Node->getOperand(0), LL, LH); 2990 ExpandOp(Node->getOperand(1), RL, RH); 2991 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 2992 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 2993 break; 2994 } 2995 case ISD::SELECT: { 2996 SDOperand C, LL, LH, RL, RH; 2997 2998 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2999 case Expand: assert(0 && "It's impossible to expand bools"); 3000 case Legal: 3001 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 3002 break; 3003 case Promote: 3004 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 3005 break; 3006 } 3007 ExpandOp(Node->getOperand(1), LL, LH); 3008 ExpandOp(Node->getOperand(2), RL, RH); 3009 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 3010 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 3011 break; 3012 } 3013 case ISD::SELECT_CC: { 3014 SDOperand TL, TH, FL, FH; 3015 ExpandOp(Node->getOperand(2), TL, TH); 3016 ExpandOp(Node->getOperand(3), FL, FH); 3017 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3018 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3019 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3020 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3021 Lo = LegalizeOp(Lo); 3022 Hi = LegalizeOp(Hi); 3023 break; 3024 } 3025 case ISD::ANY_EXTEND: { 3026 SDOperand In; 3027 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3028 case Expand: assert(0 && "expand-expand not implemented yet!"); 3029 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3030 case Promote: 3031 In = PromoteOp(Node->getOperand(0)); 3032 break; 3033 } 3034 3035 // The low part is any extension of the input (which degenerates to a copy). 3036 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In); 3037 // The high part is undefined. 3038 Hi = DAG.getNode(ISD::UNDEF, NVT); 3039 break; 3040 } 3041 case ISD::SIGN_EXTEND: { 3042 SDOperand In; 3043 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3044 case Expand: assert(0 && "expand-expand not implemented yet!"); 3045 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3046 case Promote: 3047 In = PromoteOp(Node->getOperand(0)); 3048 // Emit the appropriate sign_extend_inreg to get the value we want. 3049 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 3050 DAG.getValueType(Node->getOperand(0).getValueType())); 3051 break; 3052 } 3053 3054 // The low part is just a sign extension of the input (which degenerates to 3055 // a copy). 3056 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 3057 3058 // The high part is obtained by SRA'ing all but one of the bits of the lo 3059 // part. 3060 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3061 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3062 TLI.getShiftAmountTy())); 3063 break; 3064 } 3065 case ISD::ZERO_EXTEND: { 3066 SDOperand In; 3067 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3068 case Expand: assert(0 && "expand-expand not implemented yet!"); 3069 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3070 case Promote: 3071 In = PromoteOp(Node->getOperand(0)); 3072 // Emit the appropriate zero_extend_inreg to get the value we want. 3073 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 3074 break; 3075 } 3076 3077 // The low part is just a zero extension of the input (which degenerates to 3078 // a copy). 3079 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 3080 3081 // The high part is just a zero. 3082 Hi = DAG.getConstant(0, NVT); 3083 break; 3084 } 3085 // These operators cannot be expanded directly, emit them as calls to 3086 // library functions. 3087 case ISD::FP_TO_SINT: 3088 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 3089 SDOperand Op; 3090 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3091 case Expand: assert(0 && "cannot expand FP!"); 3092 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3093 case Promote: Op = PromoteOp(Node->getOperand(0)); break; 3094 } 3095 3096 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 3097 3098 // Now that the custom expander is done, expand the result, which is still 3099 // VT. 3100 if (Op.Val) { 3101 ExpandOp(Op, Lo, Hi); 3102 break; 3103 } 3104 } 3105 3106 if (Node->getOperand(0).getValueType() == MVT::f32) 3107 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 3108 else 3109 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 3110 break; 3111 3112 case ISD::FP_TO_UINT: 3113 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 3114 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, 3115 LegalizeOp(Node->getOperand(0))); 3116 // Now that the custom expander is done, expand the result, which is still 3117 // VT. 3118 Op = TLI.LowerOperation(Op, DAG); 3119 if (Op.Val) { 3120 ExpandOp(Op, Lo, Hi); 3121 break; 3122 } 3123 } 3124 3125 if (Node->getOperand(0).getValueType() == MVT::f32) 3126 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 3127 else 3128 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 3129 break; 3130 3131 case ISD::SHL: 3132 // If the target wants custom lowering, do so. 3133 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 3134 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), 3135 LegalizeOp(Node->getOperand(1))); 3136 Op = TLI.LowerOperation(Op, DAG); 3137 if (Op.Val) { 3138 // Now that the custom expander is done, expand the result, which is 3139 // still VT. 3140 ExpandOp(Op, Lo, Hi); 3141 break; 3142 } 3143 } 3144 3145 // If we can emit an efficient shift operation, do so now. 3146 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3147 break; 3148 3149 // If this target supports SHL_PARTS, use it. 3150 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) { 3151 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 3152 Lo, Hi); 3153 break; 3154 } 3155 3156 // Otherwise, emit a libcall. 3157 Lo = ExpandLibCall("__ashldi3", Node, Hi); 3158 break; 3159 3160 case ISD::SRA: 3161 // If the target wants custom lowering, do so. 3162 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 3163 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), 3164 LegalizeOp(Node->getOperand(1))); 3165 Op = TLI.LowerOperation(Op, DAG); 3166 if (Op.Val) { 3167 // Now that the custom expander is done, expand the result, which is 3168 // still VT. 3169 ExpandOp(Op, Lo, Hi); 3170 break; 3171 } 3172 } 3173 3174 // If we can emit an efficient shift operation, do so now. 3175 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3176 break; 3177 3178 // If this target supports SRA_PARTS, use it. 3179 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) { 3180 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 3181 Lo, Hi); 3182 break; 3183 } 3184 3185 // Otherwise, emit a libcall. 3186 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 3187 break; 3188 case ISD::SRL: 3189 // If the target wants custom lowering, do so. 3190 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 3191 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), 3192 LegalizeOp(Node->getOperand(1))); 3193 Op = TLI.LowerOperation(Op, DAG); 3194 if (Op.Val) { 3195 // Now that the custom expander is done, expand the result, which is 3196 // still VT. 3197 ExpandOp(Op, Lo, Hi); 3198 break; 3199 } 3200 } 3201 3202 // If we can emit an efficient shift operation, do so now. 3203 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3204 break; 3205 3206 // If this target supports SRL_PARTS, use it. 3207 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) { 3208 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 3209 Lo, Hi); 3210 break; 3211 } 3212 3213 // Otherwise, emit a libcall. 3214 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 3215 break; 3216 3217 case ISD::ADD: 3218 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 3219 Lo, Hi); 3220 break; 3221 case ISD::SUB: 3222 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 3223 Lo, Hi); 3224 break; 3225 case ISD::MUL: { 3226 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 3227 SDOperand LL, LH, RL, RH; 3228 ExpandOp(Node->getOperand(0), LL, LH); 3229 ExpandOp(Node->getOperand(1), RL, RH); 3230 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 3231 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 3232 // extended the sign bit of the low half through the upper half, and if so 3233 // emit a MULHS instead of the alternate sequence that is valid for any 3234 // i64 x i64 multiply. 3235 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 3236 // is RH an extension of the sign bit of RL? 3237 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 3238 RH.getOperand(1).getOpcode() == ISD::Constant && 3239 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 3240 // is LH an extension of the sign bit of LL? 3241 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 3242 LH.getOperand(1).getOpcode() == ISD::Constant && 3243 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 3244 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 3245 } else { 3246 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 3247 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 3248 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 3249 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 3250 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 3251 } 3252 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 3253 } else { 3254 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 3255 } 3256 break; 3257 } 3258 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 3259 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 3260 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 3261 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 3262 } 3263 3264 // Remember in a map if the values will be reused later. 3265 if (1 || !Node->hasOneUse()) { 3266 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 3267 std::make_pair(Lo, Hi))).second; 3268 assert(isNew && "Value already expanded?!?"); 3269 } 3270} 3271 3272 3273// SelectionDAG::Legalize - This is the entry point for the file. 3274// 3275void SelectionDAG::Legalize() { 3276 /// run - This is the main entry point to this class. 3277 /// 3278 SelectionDAGLegalize(*this).Run(); 3279} 3280 3281