LegalizeDAG.cpp revision 9b0f0b5e1505dcd4ec0da87ea9e29c59d98a8d27
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SelectionDAG::Legalize method.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/SelectionDAG.h"
15#include "llvm/CodeGen/MachineFunction.h"
16#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/CodeGen/MachineJumpTableInfo.h"
18#include "llvm/CodeGen/MachineModuleInfo.h"
19#include "llvm/CodeGen/PseudoSourceValue.h"
20#include "llvm/Target/TargetFrameInfo.h"
21#include "llvm/Target/TargetLowering.h"
22#include "llvm/Target/TargetData.h"
23#include "llvm/Target/TargetMachine.h"
24#include "llvm/Target/TargetOptions.h"
25#include "llvm/Target/TargetSubtarget.h"
26#include "llvm/CallingConv.h"
27#include "llvm/Constants.h"
28#include "llvm/DerivedTypes.h"
29#include "llvm/Support/CommandLine.h"
30#include "llvm/Support/Compiler.h"
31#include "llvm/Support/MathExtras.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/SmallVector.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include <map>
36using namespace llvm;
37
38//===----------------------------------------------------------------------===//
39/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40/// hacks on it until the target machine can handle it.  This involves
41/// eliminating value sizes the machine cannot handle (promoting small sizes to
42/// large sizes or splitting up large values into small values) as well as
43/// eliminating operations the machine cannot handle.
44///
45/// This code also does a small amount of optimization and recognition of idioms
46/// as part of its processing.  For example, if a target does not support a
47/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48/// will attempt merge setcc and brc instructions into brcc's.
49///
50namespace {
51class VISIBILITY_HIDDEN SelectionDAGLegalize {
52  TargetLowering &TLI;
53  SelectionDAG &DAG;
54
55  // Libcall insertion helpers.
56
57  /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58  /// legalized.  We use this to ensure that calls are properly serialized
59  /// against each other, including inserted libcalls.
60  SDValue LastCALLSEQ_END;
61
62  /// IsLegalizingCall - This member is used *only* for purposes of providing
63  /// helpful assertions that a libcall isn't created while another call is
64  /// being legalized (which could lead to non-serialized call sequences).
65  bool IsLegalizingCall;
66
67  enum LegalizeAction {
68    Legal,      // The target natively supports this operation.
69    Promote,    // This operation should be executed in a larger type.
70    Expand      // Try to expand this to other ops, otherwise use a libcall.
71  };
72
73  /// ValueTypeActions - This is a bitvector that contains two bits for each
74  /// value type, where the two bits correspond to the LegalizeAction enum.
75  /// This can be queried with "getTypeAction(VT)".
76  TargetLowering::ValueTypeActionImpl ValueTypeActions;
77
78  /// LegalizedNodes - For nodes that are of legal width, and that have more
79  /// than one use, this map indicates what regularized operand to use.  This
80  /// allows us to avoid legalizing the same thing more than once.
81  DenseMap<SDValue, SDValue> LegalizedNodes;
82
83  /// PromotedNodes - For nodes that are below legal width, and that have more
84  /// than one use, this map indicates what promoted value to use.  This allows
85  /// us to avoid promoting the same thing more than once.
86  DenseMap<SDValue, SDValue> PromotedNodes;
87
88  /// ExpandedNodes - For nodes that need to be expanded this map indicates
89  /// which operands are the expanded version of the input.  This allows
90  /// us to avoid expanding the same node more than once.
91  DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
92
93  /// SplitNodes - For vector nodes that need to be split, this map indicates
94  /// which operands are the split version of the input.  This allows us
95  /// to avoid splitting the same node more than once.
96  std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
97
98  /// ScalarizedNodes - For nodes that need to be converted from vector types to
99  /// scalar types, this contains the mapping of ones we have already
100  /// processed to the result.
101  std::map<SDValue, SDValue> ScalarizedNodes;
102
103  /// WidenNodes - For nodes that need to be widened from one vector type to
104  /// another, this contains the mapping of those that we have already widen.
105  /// This allows us to avoid widening more than once.
106  std::map<SDValue, SDValue> WidenNodes;
107
108  void AddLegalizedOperand(SDValue From, SDValue To) {
109    LegalizedNodes.insert(std::make_pair(From, To));
110    // If someone requests legalization of the new node, return itself.
111    if (From != To)
112      LegalizedNodes.insert(std::make_pair(To, To));
113  }
114  void AddPromotedOperand(SDValue From, SDValue To) {
115    bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
116    assert(isNew && "Got into the map somehow?");
117    isNew = isNew;
118    // If someone requests legalization of the new node, return itself.
119    LegalizedNodes.insert(std::make_pair(To, To));
120  }
121  void AddWidenedOperand(SDValue From, SDValue To) {
122    bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
123    assert(isNew && "Got into the map somehow?");
124    isNew = isNew;
125    // If someone requests legalization of the new node, return itself.
126    LegalizedNodes.insert(std::make_pair(To, To));
127  }
128
129public:
130  explicit SelectionDAGLegalize(SelectionDAG &DAG);
131
132  /// getTypeAction - Return how we should legalize values of this type, either
133  /// it is already legal or we need to expand it into multiple registers of
134  /// smaller integer type, or we need to promote it to a larger type.
135  LegalizeAction getTypeAction(MVT VT) const {
136    return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
137  }
138
139  /// isTypeLegal - Return true if this type is legal on this target.
140  ///
141  bool isTypeLegal(MVT VT) const {
142    return getTypeAction(VT) == Legal;
143  }
144
145  void LegalizeDAG();
146
147private:
148  /// HandleOp - Legalize, Promote, or Expand the specified operand as
149  /// appropriate for its type.
150  void HandleOp(SDValue Op);
151
152  /// LegalizeOp - We know that the specified value has a legal type.
153  /// Recursively ensure that the operands have legal types, then return the
154  /// result.
155  SDValue LegalizeOp(SDValue O);
156
157  /// UnrollVectorOp - We know that the given vector has a legal type, however
158  /// the operation it performs is not legal and is an operation that we have
159  /// no way of lowering.  "Unroll" the vector, splitting out the scalars and
160  /// operating on each element individually.
161  SDValue UnrollVectorOp(SDValue O);
162
163  /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
164  /// insertion index for the INSERT_VECTOR_ELT instruction.  In this case, it
165  /// is necessary to spill the vector being inserted into to memory, perform
166  /// the insert there, and then read the result back.
167  SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
168                                           SDValue Idx);
169
170  /// PromoteOp - Given an operation that produces a value in an invalid type,
171  /// promote it to compute the value into a larger type.  The produced value
172  /// will have the correct bits for the low portion of the register, but no
173  /// guarantee is made about the top bits: it may be zero, sign-extended, or
174  /// garbage.
175  SDValue PromoteOp(SDValue O);
176
177  /// ExpandOp - Expand the specified SDValue into its two component pieces
178  /// Lo&Hi.  Note that the Op MUST be an expanded type.  As a result of this,
179  /// the LegalizedNodes map is filled in for any results that are not expanded,
180  /// the ExpandedNodes map is filled in for any results that are expanded, and
181  /// the Lo/Hi values are returned.   This applies to integer types and Vector
182  /// types.
183  void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
184
185  /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
186  /// (e.g., v3i32 to v4i32).  The produced value will have the correct value
187  /// for the existing elements but no guarantee is made about the new elements
188  /// at the end of the vector: it may be zero, ones, or garbage. This is useful
189  /// when we have an instruction operating on an illegal vector type and we
190  /// want to widen it to do the computation on a legal wider vector type.
191  SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
192
193  /// SplitVectorOp - Given an operand of vector type, break it down into
194  /// two smaller values.
195  void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
196
197  /// ScalarizeVectorOp - Given an operand of single-element vector type
198  /// (e.g. v1f32), convert it into the equivalent operation that returns a
199  /// scalar (e.g. f32) value.
200  SDValue ScalarizeVectorOp(SDValue O);
201
202  /// Useful 16 element vector type that is used to pass operands for widening.
203  typedef SmallVector<SDValue, 16> SDValueVector;
204
205  /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
206  /// the LdChain contains a single load and false if it contains a token
207  /// factor for multiple loads. It takes
208  ///   Result:  location to return the result
209  ///   LdChain: location to return the load chain
210  ///   Op:      load operation to widen
211  ///   NVT:     widen vector result type we want for the load
212  bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
213                         SDValue Op, MVT NVT);
214
215  /// Helper genWidenVectorLoads - Helper function to generate a set of
216  /// loads to load a vector with a resulting wider type. It takes
217  ///   LdChain: list of chains for the load we have generated
218  ///   Chain:   incoming chain for the ld vector
219  ///   BasePtr: base pointer to load from
220  ///   SV:      memory disambiguation source value
221  ///   SVOffset:  memory disambiugation offset
222  ///   Alignment: alignment of the memory
223  ///   isVolatile: volatile load
224  ///   LdWidth:    width of memory that we want to load
225  ///   ResType:    the wider result result type for the resulting loaded vector
226  SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
227                                SDValue BasePtr, const Value *SV,
228                                int SVOffset, unsigned Alignment,
229                                bool isVolatile, unsigned LdWidth,
230                                MVT ResType);
231
232  /// StoreWidenVectorOp - Stores a widen vector into non widen memory
233  /// location. It takes
234  ///     ST:      store node that we want to replace
235  ///     Chain:   incoming store chain
236  ///     BasePtr: base address of where we want to store into
237  SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
238                               SDValue BasePtr);
239
240  /// Helper genWidenVectorStores - Helper function to generate a set of
241  /// stores to store a widen vector into non widen memory
242  // It takes
243  //   StChain: list of chains for the stores we have generated
244  //   Chain:   incoming chain for the ld vector
245  //   BasePtr: base pointer to load from
246  //   SV:      memory disambiguation source value
247  //   SVOffset:   memory disambiugation offset
248  //   Alignment:  alignment of the memory
249  //   isVolatile: volatile lod
250  //   ValOp:   value to store
251  //   StWidth: width of memory that we want to store
252  void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
253                            SDValue BasePtr, const Value *SV,
254                            int SVOffset, unsigned Alignment,
255                            bool isVolatile, SDValue ValOp,
256                            unsigned StWidth);
257
258  /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
259  /// specified mask and type.  Targets can specify exactly which masks they
260  /// support and the code generator is tasked with not creating illegal masks.
261  ///
262  /// Note that this will also return true for shuffles that are promoted to a
263  /// different type.
264  ///
265  /// If this is a legal shuffle, this method returns the (possibly promoted)
266  /// build_vector Mask.  If it's not a legal shuffle, it returns null.
267  SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
268
269  bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
270                                    SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
271
272  void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
273  void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC);
274  void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) {
275    LegalizeSetCCOperands(LHS, RHS, CC);
276    LegalizeSetCCCondCode(VT, LHS, RHS, CC);
277  }
278
279  SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
280                          SDValue &Hi);
281  SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
282
283  SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
284  SDValue ExpandBUILD_VECTOR(SDNode *Node);
285  SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
286  SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
287  SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
288  SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
289  SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
290
291  SDValue ExpandBSWAP(SDValue Op);
292  SDValue ExpandBitCount(unsigned Opc, SDValue Op);
293  bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
294                   SDValue &Lo, SDValue &Hi);
295  void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
296                        SDValue &Lo, SDValue &Hi);
297
298  SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
299  SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
300};
301}
302
303/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
304/// specified mask and type.  Targets can specify exactly which masks they
305/// support and the code generator is tasked with not creating illegal masks.
306///
307/// Note that this will also return true for shuffles that are promoted to a
308/// different type.
309SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
310  switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
311  default: return 0;
312  case TargetLowering::Legal:
313  case TargetLowering::Custom:
314    break;
315  case TargetLowering::Promote: {
316    // If this is promoted to a different type, convert the shuffle mask and
317    // ask if it is legal in the promoted type!
318    MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
319    MVT EltVT = NVT.getVectorElementType();
320
321    // If we changed # elements, change the shuffle mask.
322    unsigned NumEltsGrowth =
323      NVT.getVectorNumElements() / VT.getVectorNumElements();
324    assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
325    if (NumEltsGrowth > 1) {
326      // Renumber the elements.
327      SmallVector<SDValue, 8> Ops;
328      for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
329        SDValue InOp = Mask.getOperand(i);
330        for (unsigned j = 0; j != NumEltsGrowth; ++j) {
331          if (InOp.getOpcode() == ISD::UNDEF)
332            Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
333          else {
334            unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
335            Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
336          }
337        }
338      }
339      Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
340    }
341    VT = NVT;
342    break;
343  }
344  }
345  return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
346}
347
348SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
349  : TLI(dag.getTargetLoweringInfo()), DAG(dag),
350    ValueTypeActions(TLI.getValueTypeActions()) {
351  assert(MVT::LAST_VALUETYPE <= 32 &&
352         "Too many value types for ValueTypeActions to hold!");
353}
354
355void SelectionDAGLegalize::LegalizeDAG() {
356  LastCALLSEQ_END = DAG.getEntryNode();
357  IsLegalizingCall = false;
358
359  // The legalize process is inherently a bottom-up recursive process (users
360  // legalize their uses before themselves).  Given infinite stack space, we
361  // could just start legalizing on the root and traverse the whole graph.  In
362  // practice however, this causes us to run out of stack space on large basic
363  // blocks.  To avoid this problem, compute an ordering of the nodes where each
364  // node is only legalized after all of its operands are legalized.
365  DAG.AssignTopologicalOrder();
366  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
367       E = prior(DAG.allnodes_end()); I != next(E); ++I)
368    HandleOp(SDValue(I, 0));
369
370  // Finally, it's possible the root changed.  Get the new root.
371  SDValue OldRoot = DAG.getRoot();
372  assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
373  DAG.setRoot(LegalizedNodes[OldRoot]);
374
375  ExpandedNodes.clear();
376  LegalizedNodes.clear();
377  PromotedNodes.clear();
378  SplitNodes.clear();
379  ScalarizedNodes.clear();
380  WidenNodes.clear();
381
382  // Remove dead nodes now.
383  DAG.RemoveDeadNodes();
384}
385
386
387/// FindCallEndFromCallStart - Given a chained node that is part of a call
388/// sequence, find the CALLSEQ_END node that terminates the call sequence.
389static SDNode *FindCallEndFromCallStart(SDNode *Node) {
390  if (Node->getOpcode() == ISD::CALLSEQ_END)
391    return Node;
392  if (Node->use_empty())
393    return 0;   // No CallSeqEnd
394
395  // The chain is usually at the end.
396  SDValue TheChain(Node, Node->getNumValues()-1);
397  if (TheChain.getValueType() != MVT::Other) {
398    // Sometimes it's at the beginning.
399    TheChain = SDValue(Node, 0);
400    if (TheChain.getValueType() != MVT::Other) {
401      // Otherwise, hunt for it.
402      for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
403        if (Node->getValueType(i) == MVT::Other) {
404          TheChain = SDValue(Node, i);
405          break;
406        }
407
408      // Otherwise, we walked into a node without a chain.
409      if (TheChain.getValueType() != MVT::Other)
410        return 0;
411    }
412  }
413
414  for (SDNode::use_iterator UI = Node->use_begin(),
415       E = Node->use_end(); UI != E; ++UI) {
416
417    // Make sure to only follow users of our token chain.
418    SDNode *User = *UI;
419    for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
420      if (User->getOperand(i) == TheChain)
421        if (SDNode *Result = FindCallEndFromCallStart(User))
422          return Result;
423  }
424  return 0;
425}
426
427/// FindCallStartFromCallEnd - Given a chained node that is part of a call
428/// sequence, find the CALLSEQ_START node that initiates the call sequence.
429static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
430  assert(Node && "Didn't find callseq_start for a call??");
431  if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
432
433  assert(Node->getOperand(0).getValueType() == MVT::Other &&
434         "Node doesn't have a token chain argument!");
435  return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
436}
437
438/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
439/// see if any uses can reach Dest.  If no dest operands can get to dest,
440/// legalize them, legalize ourself, and return false, otherwise, return true.
441///
442/// Keep track of the nodes we fine that actually do lead to Dest in
443/// NodesLeadingTo.  This avoids retraversing them exponential number of times.
444///
445bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
446                                     SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
447  if (N == Dest) return true;  // N certainly leads to Dest :)
448
449  // If we've already processed this node and it does lead to Dest, there is no
450  // need to reprocess it.
451  if (NodesLeadingTo.count(N)) return true;
452
453  // If the first result of this node has been already legalized, then it cannot
454  // reach N.
455  switch (getTypeAction(N->getValueType(0))) {
456  case Legal:
457    if (LegalizedNodes.count(SDValue(N, 0))) return false;
458    break;
459  case Promote:
460    if (PromotedNodes.count(SDValue(N, 0))) return false;
461    break;
462  case Expand:
463    if (ExpandedNodes.count(SDValue(N, 0))) return false;
464    break;
465  }
466
467  // Okay, this node has not already been legalized.  Check and legalize all
468  // operands.  If none lead to Dest, then we can legalize this node.
469  bool OperandsLeadToDest = false;
470  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
471    OperandsLeadToDest |=     // If an operand leads to Dest, so do we.
472      LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
473
474  if (OperandsLeadToDest) {
475    NodesLeadingTo.insert(N);
476    return true;
477  }
478
479  // Okay, this node looks safe, legalize it and return false.
480  HandleOp(SDValue(N, 0));
481  return false;
482}
483
484/// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
485/// appropriate for its type.
486void SelectionDAGLegalize::HandleOp(SDValue Op) {
487  MVT VT = Op.getValueType();
488  switch (getTypeAction(VT)) {
489  default: assert(0 && "Bad type action!");
490  case Legal:   (void)LegalizeOp(Op); break;
491  case Promote:
492    if (!VT.isVector()) {
493      (void)PromoteOp(Op);
494      break;
495    }
496    else  {
497      // See if we can widen otherwise use Expand to either scalarize or split
498      MVT WidenVT = TLI.getWidenVectorType(VT);
499      if (WidenVT != MVT::Other) {
500        (void) WidenVectorOp(Op, WidenVT);
501        break;
502      }
503      // else fall thru to expand since we can't widen the vector
504    }
505  case Expand:
506    if (!VT.isVector()) {
507      // If this is an illegal scalar, expand it into its two component
508      // pieces.
509      SDValue X, Y;
510      if (Op.getOpcode() == ISD::TargetConstant)
511        break;  // Allow illegal target nodes.
512      ExpandOp(Op, X, Y);
513    } else if (VT.getVectorNumElements() == 1) {
514      // If this is an illegal single element vector, convert it to a
515      // scalar operation.
516      (void)ScalarizeVectorOp(Op);
517    } else {
518      // This is an illegal multiple element vector.
519      // Split it in half and legalize both parts.
520      SDValue X, Y;
521      SplitVectorOp(Op, X, Y);
522    }
523    break;
524  }
525}
526
527/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
528/// a load from the constant pool.
529static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
530                                  SelectionDAG &DAG, TargetLowering &TLI) {
531  bool Extend = false;
532
533  // If a FP immediate is precise when represented as a float and if the
534  // target can do an extending load from float to double, we put it into
535  // the constant pool as a float, even if it's is statically typed as a
536  // double.  This shrinks FP constants and canonicalizes them for targets where
537  // an FP extending load is the same cost as a normal load (such as on the x87
538  // fp stack or PPC FP unit).
539  MVT VT = CFP->getValueType(0);
540  ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
541  if (!UseCP) {
542    if (VT!=MVT::f64 && VT!=MVT::f32)
543      assert(0 && "Invalid type expansion");
544    return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
545                           (VT == MVT::f64) ? MVT::i64 : MVT::i32);
546  }
547
548  MVT OrigVT = VT;
549  MVT SVT = VT;
550  while (SVT != MVT::f32) {
551    SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
552    if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
553        // Only do this if the target has a native EXTLOAD instruction from
554        // smaller type.
555        TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
556        TLI.ShouldShrinkFPConstant(OrigVT)) {
557      const Type *SType = SVT.getTypeForMVT();
558      LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
559      VT = SVT;
560      Extend = true;
561    }
562  }
563
564  SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
565  unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
566  if (Extend)
567    return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
568                          CPIdx, PseudoSourceValue::getConstantPool(),
569                          0, VT, false, Alignment);
570  return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
571                     PseudoSourceValue::getConstantPool(), 0, false, Alignment);
572}
573
574
575/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
576/// operations.
577static
578SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
579                                    SelectionDAG &DAG, TargetLowering &TLI) {
580  MVT VT = Node->getValueType(0);
581  MVT SrcVT = Node->getOperand(1).getValueType();
582  assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
583         "fcopysign expansion only supported for f32 and f64");
584  MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
585
586  // First get the sign bit of second operand.
587  SDValue Mask1 = (SrcVT == MVT::f64)
588    ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
589    : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
590  Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
591  SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
592  SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
593  // Shift right or sign-extend it if the two operands have different types.
594  int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
595  if (SizeDiff > 0) {
596    SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
597                          DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
598    SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
599  } else if (SizeDiff < 0) {
600    SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
601    SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
602                          DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
603  }
604
605  // Clear the sign bit of first operand.
606  SDValue Mask2 = (VT == MVT::f64)
607    ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
608    : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
609  Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
610  SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
611  Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
612
613  // Or the value with the sign bit.
614  Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
615  return Result;
616}
617
618/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
619static
620SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
621                             TargetLowering &TLI) {
622  SDValue Chain = ST->getChain();
623  SDValue Ptr = ST->getBasePtr();
624  SDValue Val = ST->getValue();
625  MVT VT = Val.getValueType();
626  int Alignment = ST->getAlignment();
627  int SVOffset = ST->getSrcValueOffset();
628  if (ST->getMemoryVT().isFloatingPoint() ||
629      ST->getMemoryVT().isVector()) {
630    // Expand to a bitconvert of the value to the integer type of the
631    // same size, then a (misaligned) int store.
632    MVT intVT;
633    if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
634      intVT = MVT::i128;
635    else if (VT.is64BitVector() || VT==MVT::f64)
636      intVT = MVT::i64;
637    else if (VT==MVT::f32)
638      intVT = MVT::i32;
639    else
640      assert(0 && "Unaligned store of unsupported type");
641
642    SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
643    return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
644                        SVOffset, ST->isVolatile(), Alignment);
645  }
646  assert(ST->getMemoryVT().isInteger() &&
647         !ST->getMemoryVT().isVector() &&
648         "Unaligned store of unknown type.");
649  // Get the half-size VT
650  MVT NewStoredVT =
651    (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
652  int NumBits = NewStoredVT.getSizeInBits();
653  int IncrementSize = NumBits / 8;
654
655  // Divide the stored value in two parts.
656  SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
657  SDValue Lo = Val;
658  SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
659
660  // Store the two parts
661  SDValue Store1, Store2;
662  Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
663                             ST->getSrcValue(), SVOffset, NewStoredVT,
664                             ST->isVolatile(), Alignment);
665  Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
666                    DAG.getConstant(IncrementSize, TLI.getPointerTy()));
667  Alignment = MinAlign(Alignment, IncrementSize);
668  Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
669                             ST->getSrcValue(), SVOffset + IncrementSize,
670                             NewStoredVT, ST->isVolatile(), Alignment);
671
672  return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
673}
674
675/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
676static
677SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
678                            TargetLowering &TLI) {
679  int SVOffset = LD->getSrcValueOffset();
680  SDValue Chain = LD->getChain();
681  SDValue Ptr = LD->getBasePtr();
682  MVT VT = LD->getValueType(0);
683  MVT LoadedVT = LD->getMemoryVT();
684  if (VT.isFloatingPoint() || VT.isVector()) {
685    // Expand to a (misaligned) integer load of the same size,
686    // then bitconvert to floating point or vector.
687    MVT intVT;
688    if (LoadedVT.is128BitVector() ||
689         LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
690      intVT = MVT::i128;
691    else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
692      intVT = MVT::i64;
693    else if (LoadedVT == MVT::f32)
694      intVT = MVT::i32;
695    else
696      assert(0 && "Unaligned load of unsupported type");
697
698    SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
699                                    SVOffset, LD->isVolatile(),
700                                    LD->getAlignment());
701    SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
702    if (VT.isFloatingPoint() && LoadedVT != VT)
703      Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
704
705    SDValue Ops[] = { Result, Chain };
706    return DAG.getMergeValues(Ops, 2);
707  }
708  assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
709         "Unaligned load of unsupported type.");
710
711  // Compute the new VT that is half the size of the old one.  This is an
712  // integer MVT.
713  unsigned NumBits = LoadedVT.getSizeInBits();
714  MVT NewLoadedVT;
715  NewLoadedVT = MVT::getIntegerVT(NumBits/2);
716  NumBits >>= 1;
717
718  unsigned Alignment = LD->getAlignment();
719  unsigned IncrementSize = NumBits / 8;
720  ISD::LoadExtType HiExtType = LD->getExtensionType();
721
722  // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
723  if (HiExtType == ISD::NON_EXTLOAD)
724    HiExtType = ISD::ZEXTLOAD;
725
726  // Load the value in two parts
727  SDValue Lo, Hi;
728  if (TLI.isLittleEndian()) {
729    Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
730                        SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
731    Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
732                      DAG.getConstant(IncrementSize, TLI.getPointerTy()));
733    Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
734                        SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
735                        MinAlign(Alignment, IncrementSize));
736  } else {
737    Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
738                        NewLoadedVT,LD->isVolatile(), Alignment);
739    Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
740                      DAG.getConstant(IncrementSize, TLI.getPointerTy()));
741    Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
742                        SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
743                        MinAlign(Alignment, IncrementSize));
744  }
745
746  // aggregate the two parts
747  SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
748  SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
749  Result = DAG.getNode(ISD::OR, VT, Result, Lo);
750
751  SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
752                             Hi.getValue(1));
753
754  SDValue Ops[] = { Result, TF };
755  return DAG.getMergeValues(Ops, 2);
756}
757
758/// UnrollVectorOp - We know that the given vector has a legal type, however
759/// the operation it performs is not legal and is an operation that we have
760/// no way of lowering.  "Unroll" the vector, splitting out the scalars and
761/// operating on each element individually.
762SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
763  MVT VT = Op.getValueType();
764  assert(isTypeLegal(VT) &&
765         "Caller should expand or promote operands that are not legal!");
766  assert(Op.getNode()->getNumValues() == 1 &&
767         "Can't unroll a vector with multiple results!");
768  unsigned NE = VT.getVectorNumElements();
769  MVT EltVT = VT.getVectorElementType();
770
771  SmallVector<SDValue, 8> Scalars;
772  SmallVector<SDValue, 4> Operands(Op.getNumOperands());
773  for (unsigned i = 0; i != NE; ++i) {
774    for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
775      SDValue Operand = Op.getOperand(j);
776      MVT OperandVT = Operand.getValueType();
777      if (OperandVT.isVector()) {
778        // A vector operand; extract a single element.
779        MVT OperandEltVT = OperandVT.getVectorElementType();
780        Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
781                                  OperandEltVT,
782                                  Operand,
783                                  DAG.getConstant(i, MVT::i32));
784      } else {
785        // A scalar operand; just use it as is.
786        Operands[j] = Operand;
787      }
788    }
789    Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
790                                  &Operands[0], Operands.size()));
791  }
792
793  return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
794}
795
796/// GetFPLibCall - Return the right libcall for the given floating point type.
797static RTLIB::Libcall GetFPLibCall(MVT VT,
798                                   RTLIB::Libcall Call_F32,
799                                   RTLIB::Libcall Call_F64,
800                                   RTLIB::Libcall Call_F80,
801                                   RTLIB::Libcall Call_PPCF128) {
802  return
803    VT == MVT::f32 ? Call_F32 :
804    VT == MVT::f64 ? Call_F64 :
805    VT == MVT::f80 ? Call_F80 :
806    VT == MVT::ppcf128 ? Call_PPCF128 :
807    RTLIB::UNKNOWN_LIBCALL;
808}
809
810/// PerformInsertVectorEltInMemory - Some target cannot handle a variable
811/// insertion index for the INSERT_VECTOR_ELT instruction.  In this case, it
812/// is necessary to spill the vector being inserted into to memory, perform
813/// the insert there, and then read the result back.
814SDValue SelectionDAGLegalize::
815PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
816  SDValue Tmp1 = Vec;
817  SDValue Tmp2 = Val;
818  SDValue Tmp3 = Idx;
819
820  // If the target doesn't support this, we have to spill the input vector
821  // to a temporary stack slot, update the element, then reload it.  This is
822  // badness.  We could also load the value into a vector register (either
823  // with a "move to register" or "extload into register" instruction, then
824  // permute it into place, if the idx is a constant and if the idx is
825  // supported by the target.
826  MVT VT    = Tmp1.getValueType();
827  MVT EltVT = VT.getVectorElementType();
828  MVT IdxVT = Tmp3.getValueType();
829  MVT PtrVT = TLI.getPointerTy();
830  SDValue StackPtr = DAG.CreateStackTemporary(VT);
831
832  int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
833
834  // Store the vector.
835  SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
836                            PseudoSourceValue::getFixedStack(SPFI), 0);
837
838  // Truncate or zero extend offset to target pointer type.
839  unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
840  Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
841  // Add the offset to the index.
842  unsigned EltSize = EltVT.getSizeInBits()/8;
843  Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
844  SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
845  // Store the scalar value.
846  Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
847                         PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
848  // Load the updated vector.
849  return DAG.getLoad(VT, Ch, StackPtr,
850                     PseudoSourceValue::getFixedStack(SPFI), 0);
851}
852
853/// LegalizeOp - We know that the specified value has a legal type, and
854/// that its operands are legal.  Now ensure that the operation itself
855/// is legal, recursively ensuring that the operands' operations remain
856/// legal.
857SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
858  if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
859    return Op;
860
861  assert(isTypeLegal(Op.getValueType()) &&
862         "Caller should expand or promote operands that are not legal!");
863  SDNode *Node = Op.getNode();
864
865  // If this operation defines any values that cannot be represented in a
866  // register on this target, make sure to expand or promote them.
867  if (Node->getNumValues() > 1) {
868    for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
869      if (getTypeAction(Node->getValueType(i)) != Legal) {
870        HandleOp(Op.getValue(i));
871        assert(LegalizedNodes.count(Op) &&
872               "Handling didn't add legal operands!");
873        return LegalizedNodes[Op];
874      }
875  }
876
877  // Note that LegalizeOp may be reentered even from single-use nodes, which
878  // means that we always must cache transformed nodes.
879  DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
880  if (I != LegalizedNodes.end()) return I->second;
881
882  SDValue Tmp1, Tmp2, Tmp3, Tmp4;
883  SDValue Result = Op;
884  bool isCustom = false;
885
886  switch (Node->getOpcode()) {
887  case ISD::FrameIndex:
888  case ISD::EntryToken:
889  case ISD::Register:
890  case ISD::BasicBlock:
891  case ISD::TargetFrameIndex:
892  case ISD::TargetJumpTable:
893  case ISD::TargetConstant:
894  case ISD::TargetConstantFP:
895  case ISD::TargetConstantPool:
896  case ISD::TargetGlobalAddress:
897  case ISD::TargetGlobalTLSAddress:
898  case ISD::TargetExternalSymbol:
899  case ISD::VALUETYPE:
900  case ISD::SRCVALUE:
901  case ISD::MEMOPERAND:
902  case ISD::CONDCODE:
903  case ISD::ARG_FLAGS:
904    // Primitives must all be legal.
905    assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
906           "This must be legal!");
907    break;
908  default:
909    if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
910      // If this is a target node, legalize it by legalizing the operands then
911      // passing it through.
912      SmallVector<SDValue, 8> Ops;
913      for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
914        Ops.push_back(LegalizeOp(Node->getOperand(i)));
915
916      Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
917
918      for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
919        AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
920      return Result.getValue(Op.getResNo());
921    }
922    // Otherwise this is an unhandled builtin node.  splat.
923#ifndef NDEBUG
924    cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
925#endif
926    assert(0 && "Do not know how to legalize this operator!");
927    abort();
928  case ISD::GLOBAL_OFFSET_TABLE:
929  case ISD::GlobalAddress:
930  case ISD::GlobalTLSAddress:
931  case ISD::ExternalSymbol:
932  case ISD::ConstantPool:
933  case ISD::JumpTable: // Nothing to do.
934    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
935    default: assert(0 && "This action is not supported yet!");
936    case TargetLowering::Custom:
937      Tmp1 = TLI.LowerOperation(Op, DAG);
938      if (Tmp1.getNode()) Result = Tmp1;
939      // FALLTHROUGH if the target doesn't want to lower this op after all.
940    case TargetLowering::Legal:
941      break;
942    }
943    break;
944  case ISD::FRAMEADDR:
945  case ISD::RETURNADDR:
946    // The only option for these nodes is to custom lower them.  If the target
947    // does not custom lower them, then return zero.
948    Tmp1 = TLI.LowerOperation(Op, DAG);
949    if (Tmp1.getNode())
950      Result = Tmp1;
951    else
952      Result = DAG.getConstant(0, TLI.getPointerTy());
953    break;
954  case ISD::FRAME_TO_ARGS_OFFSET: {
955    MVT VT = Node->getValueType(0);
956    switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
957    default: assert(0 && "This action is not supported yet!");
958    case TargetLowering::Custom:
959      Result = TLI.LowerOperation(Op, DAG);
960      if (Result.getNode()) break;
961      // Fall Thru
962    case TargetLowering::Legal:
963      Result = DAG.getConstant(0, VT);
964      break;
965    }
966    }
967    break;
968  case ISD::EXCEPTIONADDR: {
969    Tmp1 = LegalizeOp(Node->getOperand(0));
970    MVT VT = Node->getValueType(0);
971    switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
972    default: assert(0 && "This action is not supported yet!");
973    case TargetLowering::Expand: {
974        unsigned Reg = TLI.getExceptionAddressRegister();
975        Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
976      }
977      break;
978    case TargetLowering::Custom:
979      Result = TLI.LowerOperation(Op, DAG);
980      if (Result.getNode()) break;
981      // Fall Thru
982    case TargetLowering::Legal: {
983      SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
984      Result = DAG.getMergeValues(Ops, 2);
985      break;
986    }
987    }
988    }
989    if (Result.getNode()->getNumValues() == 1) break;
990
991    assert(Result.getNode()->getNumValues() == 2 &&
992           "Cannot return more than two values!");
993
994    // Since we produced two values, make sure to remember that we
995    // legalized both of them.
996    Tmp1 = LegalizeOp(Result);
997    Tmp2 = LegalizeOp(Result.getValue(1));
998    AddLegalizedOperand(Op.getValue(0), Tmp1);
999    AddLegalizedOperand(Op.getValue(1), Tmp2);
1000    return Op.getResNo() ? Tmp2 : Tmp1;
1001  case ISD::EHSELECTION: {
1002    Tmp1 = LegalizeOp(Node->getOperand(0));
1003    Tmp2 = LegalizeOp(Node->getOperand(1));
1004    MVT VT = Node->getValueType(0);
1005    switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1006    default: assert(0 && "This action is not supported yet!");
1007    case TargetLowering::Expand: {
1008        unsigned Reg = TLI.getExceptionSelectorRegister();
1009        Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
1010      }
1011      break;
1012    case TargetLowering::Custom:
1013      Result = TLI.LowerOperation(Op, DAG);
1014      if (Result.getNode()) break;
1015      // Fall Thru
1016    case TargetLowering::Legal: {
1017      SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1018      Result = DAG.getMergeValues(Ops, 2);
1019      break;
1020    }
1021    }
1022    }
1023    if (Result.getNode()->getNumValues() == 1) break;
1024
1025    assert(Result.getNode()->getNumValues() == 2 &&
1026           "Cannot return more than two values!");
1027
1028    // Since we produced two values, make sure to remember that we
1029    // legalized both of them.
1030    Tmp1 = LegalizeOp(Result);
1031    Tmp2 = LegalizeOp(Result.getValue(1));
1032    AddLegalizedOperand(Op.getValue(0), Tmp1);
1033    AddLegalizedOperand(Op.getValue(1), Tmp2);
1034    return Op.getResNo() ? Tmp2 : Tmp1;
1035  case ISD::EH_RETURN: {
1036    MVT VT = Node->getValueType(0);
1037    // The only "good" option for this node is to custom lower it.
1038    switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1039    default: assert(0 && "This action is not supported at all!");
1040    case TargetLowering::Custom:
1041      Result = TLI.LowerOperation(Op, DAG);
1042      if (Result.getNode()) break;
1043      // Fall Thru
1044    case TargetLowering::Legal:
1045      // Target does not know, how to lower this, lower to noop
1046      Result = LegalizeOp(Node->getOperand(0));
1047      break;
1048    }
1049    }
1050    break;
1051  case ISD::AssertSext:
1052  case ISD::AssertZext:
1053    Tmp1 = LegalizeOp(Node->getOperand(0));
1054    Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1055    break;
1056  case ISD::MERGE_VALUES:
1057    // Legalize eliminates MERGE_VALUES nodes.
1058    Result = Node->getOperand(Op.getResNo());
1059    break;
1060  case ISD::CopyFromReg:
1061    Tmp1 = LegalizeOp(Node->getOperand(0));
1062    Result = Op.getValue(0);
1063    if (Node->getNumValues() == 2) {
1064      Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1065    } else {
1066      assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1067      if (Node->getNumOperands() == 3) {
1068        Tmp2 = LegalizeOp(Node->getOperand(2));
1069        Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1070      } else {
1071        Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1072      }
1073      AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1074    }
1075    // Since CopyFromReg produces two values, make sure to remember that we
1076    // legalized both of them.
1077    AddLegalizedOperand(Op.getValue(0), Result);
1078    AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1079    return Result.getValue(Op.getResNo());
1080  case ISD::UNDEF: {
1081    MVT VT = Op.getValueType();
1082    switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1083    default: assert(0 && "This action is not supported yet!");
1084    case TargetLowering::Expand:
1085      if (VT.isInteger())
1086        Result = DAG.getConstant(0, VT);
1087      else if (VT.isFloatingPoint())
1088        Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1089                                   VT);
1090      else
1091        assert(0 && "Unknown value type!");
1092      break;
1093    case TargetLowering::Legal:
1094      break;
1095    }
1096    break;
1097  }
1098
1099  case ISD::INTRINSIC_W_CHAIN:
1100  case ISD::INTRINSIC_WO_CHAIN:
1101  case ISD::INTRINSIC_VOID: {
1102    SmallVector<SDValue, 8> Ops;
1103    for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1104      Ops.push_back(LegalizeOp(Node->getOperand(i)));
1105    Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1106
1107    // Allow the target to custom lower its intrinsics if it wants to.
1108    if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1109        TargetLowering::Custom) {
1110      Tmp3 = TLI.LowerOperation(Result, DAG);
1111      if (Tmp3.getNode()) Result = Tmp3;
1112    }
1113
1114    if (Result.getNode()->getNumValues() == 1) break;
1115
1116    // Must have return value and chain result.
1117    assert(Result.getNode()->getNumValues() == 2 &&
1118           "Cannot return more than two values!");
1119
1120    // Since loads produce two values, make sure to remember that we
1121    // legalized both of them.
1122    AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1123    AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1124    return Result.getValue(Op.getResNo());
1125  }
1126
1127  case ISD::DBG_STOPPOINT:
1128    assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1129    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the input chain.
1130
1131    switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1132    case TargetLowering::Promote:
1133    default: assert(0 && "This action is not supported yet!");
1134    case TargetLowering::Expand: {
1135      MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1136      bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1137      bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1138
1139      const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1140      if (MMI && (useDEBUG_LOC || useLABEL)) {
1141        const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1142        unsigned SrcFile = MMI->RecordSource(CompileUnit);
1143
1144        unsigned Line = DSP->getLine();
1145        unsigned Col = DSP->getColumn();
1146
1147        if (useDEBUG_LOC) {
1148          SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1149                              DAG.getConstant(Col, MVT::i32),
1150                              DAG.getConstant(SrcFile, MVT::i32) };
1151          Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1152        } else {
1153          unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1154          Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1155        }
1156      } else {
1157        Result = Tmp1;  // chain
1158      }
1159      break;
1160    }
1161    case TargetLowering::Legal: {
1162      LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1163      if (Action == Legal && Tmp1 == Node->getOperand(0))
1164        break;
1165
1166      SmallVector<SDValue, 8> Ops;
1167      Ops.push_back(Tmp1);
1168      if (Action == Legal) {
1169        Ops.push_back(Node->getOperand(1));  // line # must be legal.
1170        Ops.push_back(Node->getOperand(2));  // col # must be legal.
1171      } else {
1172        // Otherwise promote them.
1173        Ops.push_back(PromoteOp(Node->getOperand(1)));
1174        Ops.push_back(PromoteOp(Node->getOperand(2)));
1175      }
1176      Ops.push_back(Node->getOperand(3));  // filename must be legal.
1177      Ops.push_back(Node->getOperand(4));  // working dir # must be legal.
1178      Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1179      break;
1180    }
1181    }
1182    break;
1183
1184  case ISD::DECLARE:
1185    assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1186    switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1187    default: assert(0 && "This action is not supported yet!");
1188    case TargetLowering::Legal:
1189      Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1190      Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the address.
1191      Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the variable.
1192      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1193      break;
1194    case TargetLowering::Expand:
1195      Result = LegalizeOp(Node->getOperand(0));
1196      break;
1197    }
1198    break;
1199
1200  case ISD::DEBUG_LOC:
1201    assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1202    switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1203    default: assert(0 && "This action is not supported yet!");
1204    case TargetLowering::Legal: {
1205      LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1206      Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1207      if (Action == Legal && Tmp1 == Node->getOperand(0))
1208        break;
1209      if (Action == Legal) {
1210        Tmp2 = Node->getOperand(1);
1211        Tmp3 = Node->getOperand(2);
1212        Tmp4 = Node->getOperand(3);
1213      } else {
1214        Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the line #.
1215        Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the col #.
1216        Tmp4 = LegalizeOp(Node->getOperand(3));  // Legalize the source file id.
1217      }
1218      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1219      break;
1220    }
1221    }
1222    break;
1223
1224  case ISD::DBG_LABEL:
1225  case ISD::EH_LABEL:
1226    assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1227    switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1228    default: assert(0 && "This action is not supported yet!");
1229    case TargetLowering::Legal:
1230      Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1231      Result = DAG.UpdateNodeOperands(Result, Tmp1);
1232      break;
1233    case TargetLowering::Expand:
1234      Result = LegalizeOp(Node->getOperand(0));
1235      break;
1236    }
1237    break;
1238
1239  case ISD::PREFETCH:
1240    assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1241    switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1242    default: assert(0 && "This action is not supported yet!");
1243    case TargetLowering::Legal:
1244      Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1245      Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the address.
1246      Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the rw specifier.
1247      Tmp4 = LegalizeOp(Node->getOperand(3));  // Legalize locality specifier.
1248      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1249      break;
1250    case TargetLowering::Expand:
1251      // It's a noop.
1252      Result = LegalizeOp(Node->getOperand(0));
1253      break;
1254    }
1255    break;
1256
1257  case ISD::MEMBARRIER: {
1258    assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1259    switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1260    default: assert(0 && "This action is not supported yet!");
1261    case TargetLowering::Legal: {
1262      SDValue Ops[6];
1263      Ops[0] = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1264      for (int x = 1; x < 6; ++x) {
1265        Ops[x] = Node->getOperand(x);
1266        if (!isTypeLegal(Ops[x].getValueType()))
1267          Ops[x] = PromoteOp(Ops[x]);
1268      }
1269      Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1270      break;
1271    }
1272    case TargetLowering::Expand:
1273      //There is no libgcc call for this op
1274      Result = Node->getOperand(0);  // Noop
1275    break;
1276    }
1277    break;
1278  }
1279
1280  case ISD::ATOMIC_CMP_SWAP_8:
1281  case ISD::ATOMIC_CMP_SWAP_16:
1282  case ISD::ATOMIC_CMP_SWAP_32:
1283  case ISD::ATOMIC_CMP_SWAP_64: {
1284    unsigned int num_operands = 4;
1285    assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1286    SDValue Ops[4];
1287    for (unsigned int x = 0; x < num_operands; ++x)
1288      Ops[x] = LegalizeOp(Node->getOperand(x));
1289    Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1290
1291    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1292      default: assert(0 && "This action is not supported yet!");
1293      case TargetLowering::Custom:
1294        Result = TLI.LowerOperation(Result, DAG);
1295        break;
1296      case TargetLowering::Legal:
1297        break;
1298    }
1299    AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1300    AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1301    return Result.getValue(Op.getResNo());
1302  }
1303  case ISD::ATOMIC_LOAD_ADD_8:
1304  case ISD::ATOMIC_LOAD_SUB_8:
1305  case ISD::ATOMIC_LOAD_AND_8:
1306  case ISD::ATOMIC_LOAD_OR_8:
1307  case ISD::ATOMIC_LOAD_XOR_8:
1308  case ISD::ATOMIC_LOAD_NAND_8:
1309  case ISD::ATOMIC_LOAD_MIN_8:
1310  case ISD::ATOMIC_LOAD_MAX_8:
1311  case ISD::ATOMIC_LOAD_UMIN_8:
1312  case ISD::ATOMIC_LOAD_UMAX_8:
1313  case ISD::ATOMIC_SWAP_8:
1314  case ISD::ATOMIC_LOAD_ADD_16:
1315  case ISD::ATOMIC_LOAD_SUB_16:
1316  case ISD::ATOMIC_LOAD_AND_16:
1317  case ISD::ATOMIC_LOAD_OR_16:
1318  case ISD::ATOMIC_LOAD_XOR_16:
1319  case ISD::ATOMIC_LOAD_NAND_16:
1320  case ISD::ATOMIC_LOAD_MIN_16:
1321  case ISD::ATOMIC_LOAD_MAX_16:
1322  case ISD::ATOMIC_LOAD_UMIN_16:
1323  case ISD::ATOMIC_LOAD_UMAX_16:
1324  case ISD::ATOMIC_SWAP_16:
1325  case ISD::ATOMIC_LOAD_ADD_32:
1326  case ISD::ATOMIC_LOAD_SUB_32:
1327  case ISD::ATOMIC_LOAD_AND_32:
1328  case ISD::ATOMIC_LOAD_OR_32:
1329  case ISD::ATOMIC_LOAD_XOR_32:
1330  case ISD::ATOMIC_LOAD_NAND_32:
1331  case ISD::ATOMIC_LOAD_MIN_32:
1332  case ISD::ATOMIC_LOAD_MAX_32:
1333  case ISD::ATOMIC_LOAD_UMIN_32:
1334  case ISD::ATOMIC_LOAD_UMAX_32:
1335  case ISD::ATOMIC_SWAP_32:
1336  case ISD::ATOMIC_LOAD_ADD_64:
1337  case ISD::ATOMIC_LOAD_SUB_64:
1338  case ISD::ATOMIC_LOAD_AND_64:
1339  case ISD::ATOMIC_LOAD_OR_64:
1340  case ISD::ATOMIC_LOAD_XOR_64:
1341  case ISD::ATOMIC_LOAD_NAND_64:
1342  case ISD::ATOMIC_LOAD_MIN_64:
1343  case ISD::ATOMIC_LOAD_MAX_64:
1344  case ISD::ATOMIC_LOAD_UMIN_64:
1345  case ISD::ATOMIC_LOAD_UMAX_64:
1346  case ISD::ATOMIC_SWAP_64: {
1347    unsigned int num_operands = 3;
1348    assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1349    SDValue Ops[3];
1350    for (unsigned int x = 0; x < num_operands; ++x)
1351      Ops[x] = LegalizeOp(Node->getOperand(x));
1352    Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1353
1354    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1355    default: assert(0 && "This action is not supported yet!");
1356    case TargetLowering::Custom:
1357      Result = TLI.LowerOperation(Result, DAG);
1358      break;
1359    case TargetLowering::Legal:
1360      break;
1361    }
1362    AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1363    AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1364    return Result.getValue(Op.getResNo());
1365  }
1366  case ISD::Constant: {
1367    ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1368    unsigned opAction =
1369      TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1370
1371    // We know we don't need to expand constants here, constants only have one
1372    // value and we check that it is fine above.
1373
1374    if (opAction == TargetLowering::Custom) {
1375      Tmp1 = TLI.LowerOperation(Result, DAG);
1376      if (Tmp1.getNode())
1377        Result = Tmp1;
1378    }
1379    break;
1380  }
1381  case ISD::ConstantFP: {
1382    // Spill FP immediates to the constant pool if the target cannot directly
1383    // codegen them.  Targets often have some immediate values that can be
1384    // efficiently generated into an FP register without a load.  We explicitly
1385    // leave these constants as ConstantFP nodes for the target to deal with.
1386    ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1387
1388    switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1389    default: assert(0 && "This action is not supported yet!");
1390    case TargetLowering::Legal:
1391      break;
1392    case TargetLowering::Custom:
1393      Tmp3 = TLI.LowerOperation(Result, DAG);
1394      if (Tmp3.getNode()) {
1395        Result = Tmp3;
1396        break;
1397      }
1398      // FALLTHROUGH
1399    case TargetLowering::Expand: {
1400      // Check to see if this FP immediate is already legal.
1401      bool isLegal = false;
1402      for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1403             E = TLI.legal_fpimm_end(); I != E; ++I) {
1404        if (CFP->isExactlyValue(*I)) {
1405          isLegal = true;
1406          break;
1407        }
1408      }
1409      // If this is a legal constant, turn it into a TargetConstantFP node.
1410      if (isLegal)
1411        break;
1412      Result = ExpandConstantFP(CFP, true, DAG, TLI);
1413    }
1414    }
1415    break;
1416  }
1417  case ISD::TokenFactor:
1418    if (Node->getNumOperands() == 2) {
1419      Tmp1 = LegalizeOp(Node->getOperand(0));
1420      Tmp2 = LegalizeOp(Node->getOperand(1));
1421      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1422    } else if (Node->getNumOperands() == 3) {
1423      Tmp1 = LegalizeOp(Node->getOperand(0));
1424      Tmp2 = LegalizeOp(Node->getOperand(1));
1425      Tmp3 = LegalizeOp(Node->getOperand(2));
1426      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1427    } else {
1428      SmallVector<SDValue, 8> Ops;
1429      // Legalize the operands.
1430      for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1431        Ops.push_back(LegalizeOp(Node->getOperand(i)));
1432      Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1433    }
1434    break;
1435
1436  case ISD::FORMAL_ARGUMENTS:
1437  case ISD::CALL:
1438    // The only option for this is to custom lower it.
1439    Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1440    assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1441    // A call within a calling sequence must be legalized to something
1442    // other than the normal CALLSEQ_END.  Violating this gets Legalize
1443    // into an infinite loop.
1444    assert ((!IsLegalizingCall ||
1445             Node->getOpcode() != ISD::CALL ||
1446             Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1447            "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1448
1449    // The number of incoming and outgoing values should match; unless the final
1450    // outgoing value is a flag.
1451    assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1452            (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1453             Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1454               MVT::Flag)) &&
1455           "Lowering call/formal_arguments produced unexpected # results!");
1456
1457    // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1458    // remember that we legalized all of them, so it doesn't get relegalized.
1459    for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1460      if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1461        continue;
1462      Tmp1 = LegalizeOp(Tmp3.getValue(i));
1463      if (Op.getResNo() == i)
1464        Tmp2 = Tmp1;
1465      AddLegalizedOperand(SDValue(Node, i), Tmp1);
1466    }
1467    return Tmp2;
1468   case ISD::EXTRACT_SUBREG: {
1469      Tmp1 = LegalizeOp(Node->getOperand(0));
1470      ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1471      assert(idx && "Operand must be a constant");
1472      Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1473      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1474    }
1475    break;
1476  case ISD::INSERT_SUBREG: {
1477      Tmp1 = LegalizeOp(Node->getOperand(0));
1478      Tmp2 = LegalizeOp(Node->getOperand(1));
1479      ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1480      assert(idx && "Operand must be a constant");
1481      Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1482      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1483    }
1484    break;
1485  case ISD::BUILD_VECTOR:
1486    switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1487    default: assert(0 && "This action is not supported yet!");
1488    case TargetLowering::Custom:
1489      Tmp3 = TLI.LowerOperation(Result, DAG);
1490      if (Tmp3.getNode()) {
1491        Result = Tmp3;
1492        break;
1493      }
1494      // FALLTHROUGH
1495    case TargetLowering::Expand:
1496      Result = ExpandBUILD_VECTOR(Result.getNode());
1497      break;
1498    }
1499    break;
1500  case ISD::INSERT_VECTOR_ELT:
1501    Tmp1 = LegalizeOp(Node->getOperand(0));  // InVec
1502    Tmp3 = LegalizeOp(Node->getOperand(2));  // InEltNo
1503
1504    // The type of the value to insert may not be legal, even though the vector
1505    // type is legal.  Legalize/Promote accordingly.  We do not handle Expand
1506    // here.
1507    switch (getTypeAction(Node->getOperand(1).getValueType())) {
1508    default: assert(0 && "Cannot expand insert element operand");
1509    case Legal:   Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1510    case Promote: Tmp2 = PromoteOp(Node->getOperand(1));  break;
1511    case Expand:
1512      // FIXME: An alternative would be to check to see if the target is not
1513      // going to custom lower this operation, we could bitcast to half elt
1514      // width and perform two inserts at that width, if that is legal.
1515      Tmp2 = Node->getOperand(1);
1516      break;
1517    }
1518    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1519
1520    switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1521                                   Node->getValueType(0))) {
1522    default: assert(0 && "This action is not supported yet!");
1523    case TargetLowering::Legal:
1524      break;
1525    case TargetLowering::Custom:
1526      Tmp4 = TLI.LowerOperation(Result, DAG);
1527      if (Tmp4.getNode()) {
1528        Result = Tmp4;
1529        break;
1530      }
1531      // FALLTHROUGH
1532    case TargetLowering::Promote:
1533      // Fall thru for vector case
1534    case TargetLowering::Expand: {
1535      // If the insert index is a constant, codegen this as a scalar_to_vector,
1536      // then a shuffle that inserts it into the right position in the vector.
1537      if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1538        // SCALAR_TO_VECTOR requires that the type of the value being inserted
1539        // match the element type of the vector being created.
1540        if (Tmp2.getValueType() ==
1541            Op.getValueType().getVectorElementType()) {
1542          SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1543                                        Tmp1.getValueType(), Tmp2);
1544
1545          unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1546          MVT ShufMaskVT =
1547            MVT::getIntVectorWithNumElements(NumElts);
1548          MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1549
1550          // We generate a shuffle of InVec and ScVec, so the shuffle mask
1551          // should be 0,1,2,3,4,5... with the appropriate element replaced with
1552          // elt 0 of the RHS.
1553          SmallVector<SDValue, 8> ShufOps;
1554          for (unsigned i = 0; i != NumElts; ++i) {
1555            if (i != InsertPos->getZExtValue())
1556              ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1557            else
1558              ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1559          }
1560          SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1561                                           &ShufOps[0], ShufOps.size());
1562
1563          Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1564                               Tmp1, ScVec, ShufMask);
1565          Result = LegalizeOp(Result);
1566          break;
1567        }
1568      }
1569      Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1570      break;
1571    }
1572    }
1573    break;
1574  case ISD::SCALAR_TO_VECTOR:
1575    if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1576      Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1577      break;
1578    }
1579
1580    Tmp1 = LegalizeOp(Node->getOperand(0));  // InVal
1581    Result = DAG.UpdateNodeOperands(Result, Tmp1);
1582    switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1583                                   Node->getValueType(0))) {
1584    default: assert(0 && "This action is not supported yet!");
1585    case TargetLowering::Legal:
1586      break;
1587    case TargetLowering::Custom:
1588      Tmp3 = TLI.LowerOperation(Result, DAG);
1589      if (Tmp3.getNode()) {
1590        Result = Tmp3;
1591        break;
1592      }
1593      // FALLTHROUGH
1594    case TargetLowering::Expand:
1595      Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1596      break;
1597    }
1598    break;
1599  case ISD::VECTOR_SHUFFLE:
1600    Tmp1 = LegalizeOp(Node->getOperand(0));   // Legalize the input vectors,
1601    Tmp2 = LegalizeOp(Node->getOperand(1));   // but not the shuffle mask.
1602    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1603
1604    // Allow targets to custom lower the SHUFFLEs they support.
1605    switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1606    default: assert(0 && "Unknown operation action!");
1607    case TargetLowering::Legal:
1608      assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1609             "vector shuffle should not be created if not legal!");
1610      break;
1611    case TargetLowering::Custom:
1612      Tmp3 = TLI.LowerOperation(Result, DAG);
1613      if (Tmp3.getNode()) {
1614        Result = Tmp3;
1615        break;
1616      }
1617      // FALLTHROUGH
1618    case TargetLowering::Expand: {
1619      MVT VT = Node->getValueType(0);
1620      MVT EltVT = VT.getVectorElementType();
1621      MVT PtrVT = TLI.getPointerTy();
1622      SDValue Mask = Node->getOperand(2);
1623      unsigned NumElems = Mask.getNumOperands();
1624      SmallVector<SDValue,8> Ops;
1625      for (unsigned i = 0; i != NumElems; ++i) {
1626        SDValue Arg = Mask.getOperand(i);
1627        if (Arg.getOpcode() == ISD::UNDEF) {
1628          Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1629        } else {
1630          assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1631          unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1632          if (Idx < NumElems)
1633            Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1634                                      DAG.getConstant(Idx, PtrVT)));
1635          else
1636            Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1637                                      DAG.getConstant(Idx - NumElems, PtrVT)));
1638        }
1639      }
1640      Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1641      break;
1642    }
1643    case TargetLowering::Promote: {
1644      // Change base type to a different vector type.
1645      MVT OVT = Node->getValueType(0);
1646      MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1647
1648      // Cast the two input vectors.
1649      Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1650      Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1651
1652      // Convert the shuffle mask to the right # elements.
1653      Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1654      assert(Tmp3.getNode() && "Shuffle not legal?");
1655      Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1656      Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1657      break;
1658    }
1659    }
1660    break;
1661
1662  case ISD::EXTRACT_VECTOR_ELT:
1663    Tmp1 = Node->getOperand(0);
1664    Tmp2 = LegalizeOp(Node->getOperand(1));
1665    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1666    Result = ExpandEXTRACT_VECTOR_ELT(Result);
1667    break;
1668
1669  case ISD::EXTRACT_SUBVECTOR:
1670    Tmp1 = Node->getOperand(0);
1671    Tmp2 = LegalizeOp(Node->getOperand(1));
1672    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1673    Result = ExpandEXTRACT_SUBVECTOR(Result);
1674    break;
1675
1676  case ISD::CONCAT_VECTORS: {
1677    // Use extract/insert/build vector for now. We might try to be
1678    // more clever later.
1679    MVT PtrVT = TLI.getPointerTy();
1680    SmallVector<SDValue, 8> Ops;
1681    unsigned NumOperands = Node->getNumOperands();
1682    for (unsigned i=0; i < NumOperands; ++i) {
1683      SDValue SubOp = Node->getOperand(i);
1684      MVT VVT = SubOp.getNode()->getValueType(0);
1685      MVT EltVT = VVT.getVectorElementType();
1686      unsigned NumSubElem = VVT.getVectorNumElements();
1687      for (unsigned j=0; j < NumSubElem; ++j) {
1688        Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp,
1689                                  DAG.getConstant(j, PtrVT)));
1690      }
1691    }
1692    return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
1693                      &Ops[0], Ops.size()));
1694  }
1695
1696  case ISD::CALLSEQ_START: {
1697    SDNode *CallEnd = FindCallEndFromCallStart(Node);
1698
1699    // Recursively Legalize all of the inputs of the call end that do not lead
1700    // to this call start.  This ensures that any libcalls that need be inserted
1701    // are inserted *before* the CALLSEQ_START.
1702    {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1703    for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1704      LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1705                                   NodesLeadingTo);
1706    }
1707
1708    // Now that we legalized all of the inputs (which may have inserted
1709    // libcalls) create the new CALLSEQ_START node.
1710    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1711
1712    // Merge in the last call, to ensure that this call start after the last
1713    // call ended.
1714    if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1715      Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1716      Tmp1 = LegalizeOp(Tmp1);
1717    }
1718
1719    // Do not try to legalize the target-specific arguments (#1+).
1720    if (Tmp1 != Node->getOperand(0)) {
1721      SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1722      Ops[0] = Tmp1;
1723      Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1724    }
1725
1726    // Remember that the CALLSEQ_START is legalized.
1727    AddLegalizedOperand(Op.getValue(0), Result);
1728    if (Node->getNumValues() == 2)    // If this has a flag result, remember it.
1729      AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1730
1731    // Now that the callseq_start and all of the non-call nodes above this call
1732    // sequence have been legalized, legalize the call itself.  During this
1733    // process, no libcalls can/will be inserted, guaranteeing that no calls
1734    // can overlap.
1735    assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1736    // Note that we are selecting this call!
1737    LastCALLSEQ_END = SDValue(CallEnd, 0);
1738    IsLegalizingCall = true;
1739
1740    // Legalize the call, starting from the CALLSEQ_END.
1741    LegalizeOp(LastCALLSEQ_END);
1742    assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1743    return Result;
1744  }
1745  case ISD::CALLSEQ_END:
1746    // If the CALLSEQ_START node hasn't been legalized first, legalize it.  This
1747    // will cause this node to be legalized as well as handling libcalls right.
1748    if (LastCALLSEQ_END.getNode() != Node) {
1749      LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1750      DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1751      assert(I != LegalizedNodes.end() &&
1752             "Legalizing the call start should have legalized this node!");
1753      return I->second;
1754    }
1755
1756    // Otherwise, the call start has been legalized and everything is going
1757    // according to plan.  Just legalize ourselves normally here.
1758    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1759    // Do not try to legalize the target-specific arguments (#1+), except for
1760    // an optional flag input.
1761    if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1762      if (Tmp1 != Node->getOperand(0)) {
1763        SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1764        Ops[0] = Tmp1;
1765        Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1766      }
1767    } else {
1768      Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1769      if (Tmp1 != Node->getOperand(0) ||
1770          Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1771        SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1772        Ops[0] = Tmp1;
1773        Ops.back() = Tmp2;
1774        Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1775      }
1776    }
1777    assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1778    // This finishes up call legalization.
1779    IsLegalizingCall = false;
1780
1781    // If the CALLSEQ_END node has a flag, remember that we legalized it.
1782    AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1783    if (Node->getNumValues() == 2)
1784      AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1785    return Result.getValue(Op.getResNo());
1786  case ISD::DYNAMIC_STACKALLOC: {
1787    MVT VT = Node->getValueType(0);
1788    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1789    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the size.
1790    Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the alignment.
1791    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1792
1793    Tmp1 = Result.getValue(0);
1794    Tmp2 = Result.getValue(1);
1795    switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1796    default: assert(0 && "This action is not supported yet!");
1797    case TargetLowering::Expand: {
1798      unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1799      assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1800             " not tell us which reg is the stack pointer!");
1801      SDValue Chain = Tmp1.getOperand(0);
1802
1803      // Chain the dynamic stack allocation so that it doesn't modify the stack
1804      // pointer when other instructions are using the stack.
1805      Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1806
1807      SDValue Size  = Tmp2.getOperand(1);
1808      SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1809      Chain = SP.getValue(1);
1810      unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1811      unsigned StackAlign =
1812        TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1813      if (Align > StackAlign)
1814        SP = DAG.getNode(ISD::AND, VT, SP,
1815                         DAG.getConstant(-(uint64_t)Align, VT));
1816      Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size);       // Value
1817      Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1);     // Output chain
1818
1819      Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1820                                DAG.getIntPtrConstant(0, true), SDValue());
1821
1822      Tmp1 = LegalizeOp(Tmp1);
1823      Tmp2 = LegalizeOp(Tmp2);
1824      break;
1825    }
1826    case TargetLowering::Custom:
1827      Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1828      if (Tmp3.getNode()) {
1829        Tmp1 = LegalizeOp(Tmp3);
1830        Tmp2 = LegalizeOp(Tmp3.getValue(1));
1831      }
1832      break;
1833    case TargetLowering::Legal:
1834      break;
1835    }
1836    // Since this op produce two values, make sure to remember that we
1837    // legalized both of them.
1838    AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1839    AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1840    return Op.getResNo() ? Tmp2 : Tmp1;
1841  }
1842  case ISD::INLINEASM: {
1843    SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1844    bool Changed = false;
1845    // Legalize all of the operands of the inline asm, in case they are nodes
1846    // that need to be expanded or something.  Note we skip the asm string and
1847    // all of the TargetConstant flags.
1848    SDValue Op = LegalizeOp(Ops[0]);
1849    Changed = Op != Ops[0];
1850    Ops[0] = Op;
1851
1852    bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1853    for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1854      unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1855      for (++i; NumVals; ++i, --NumVals) {
1856        SDValue Op = LegalizeOp(Ops[i]);
1857        if (Op != Ops[i]) {
1858          Changed = true;
1859          Ops[i] = Op;
1860        }
1861      }
1862    }
1863
1864    if (HasInFlag) {
1865      Op = LegalizeOp(Ops.back());
1866      Changed |= Op != Ops.back();
1867      Ops.back() = Op;
1868    }
1869
1870    if (Changed)
1871      Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1872
1873    // INLINE asm returns a chain and flag, make sure to add both to the map.
1874    AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1875    AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1876    return Result.getValue(Op.getResNo());
1877  }
1878  case ISD::BR:
1879    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1880    // Ensure that libcalls are emitted before a branch.
1881    Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1882    Tmp1 = LegalizeOp(Tmp1);
1883    LastCALLSEQ_END = DAG.getEntryNode();
1884
1885    Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1886    break;
1887  case ISD::BRIND:
1888    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1889    // Ensure that libcalls are emitted before a branch.
1890    Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1891    Tmp1 = LegalizeOp(Tmp1);
1892    LastCALLSEQ_END = DAG.getEntryNode();
1893
1894    switch (getTypeAction(Node->getOperand(1).getValueType())) {
1895    default: assert(0 && "Indirect target must be legal type (pointer)!");
1896    case Legal:
1897      Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1898      break;
1899    }
1900    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1901    break;
1902  case ISD::BR_JT:
1903    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1904    // Ensure that libcalls are emitted before a branch.
1905    Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1906    Tmp1 = LegalizeOp(Tmp1);
1907    LastCALLSEQ_END = DAG.getEntryNode();
1908
1909    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the jumptable node.
1910    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1911
1912    switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1913    default: assert(0 && "This action is not supported yet!");
1914    case TargetLowering::Legal: break;
1915    case TargetLowering::Custom:
1916      Tmp1 = TLI.LowerOperation(Result, DAG);
1917      if (Tmp1.getNode()) Result = Tmp1;
1918      break;
1919    case TargetLowering::Expand: {
1920      SDValue Chain = Result.getOperand(0);
1921      SDValue Table = Result.getOperand(1);
1922      SDValue Index = Result.getOperand(2);
1923
1924      MVT PTy = TLI.getPointerTy();
1925      MachineFunction &MF = DAG.getMachineFunction();
1926      unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1927      Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1928      SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1929
1930      SDValue LD;
1931      switch (EntrySize) {
1932      default: assert(0 && "Size of jump table not supported yet."); break;
1933      case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1934                               PseudoSourceValue::getJumpTable(), 0); break;
1935      case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1936                               PseudoSourceValue::getJumpTable(), 0); break;
1937      }
1938
1939      Addr = LD;
1940      if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1941        // For PIC, the sequence is:
1942        // BRIND(load(Jumptable + index) + RelocBase)
1943        // RelocBase can be JumpTable, GOT or some sort of global base.
1944        if (PTy != MVT::i32)
1945          Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1946        Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1947                           TLI.getPICJumpTableRelocBase(Table, DAG));
1948      }
1949      Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1950    }
1951    }
1952    break;
1953  case ISD::BRCOND:
1954    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1955    // Ensure that libcalls are emitted before a return.
1956    Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1957    Tmp1 = LegalizeOp(Tmp1);
1958    LastCALLSEQ_END = DAG.getEntryNode();
1959
1960    switch (getTypeAction(Node->getOperand(1).getValueType())) {
1961    case Expand: assert(0 && "It's impossible to expand bools");
1962    case Legal:
1963      Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1964      break;
1965    case Promote: {
1966      Tmp2 = PromoteOp(Node->getOperand(1));  // Promote the condition.
1967
1968      // The top bits of the promoted condition are not necessarily zero, ensure
1969      // that the value is properly zero extended.
1970      unsigned BitWidth = Tmp2.getValueSizeInBits();
1971      if (!DAG.MaskedValueIsZero(Tmp2,
1972                                 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1973        Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1974      break;
1975    }
1976    }
1977
1978    // Basic block destination (Op#2) is always legal.
1979    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1980
1981    switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1982    default: assert(0 && "This action is not supported yet!");
1983    case TargetLowering::Legal: break;
1984    case TargetLowering::Custom:
1985      Tmp1 = TLI.LowerOperation(Result, DAG);
1986      if (Tmp1.getNode()) Result = Tmp1;
1987      break;
1988    case TargetLowering::Expand:
1989      // Expand brcond's setcc into its constituent parts and create a BR_CC
1990      // Node.
1991      if (Tmp2.getOpcode() == ISD::SETCC) {
1992        Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1993                             Tmp2.getOperand(0), Tmp2.getOperand(1),
1994                             Node->getOperand(2));
1995      } else {
1996        Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1997                             DAG.getCondCode(ISD::SETNE), Tmp2,
1998                             DAG.getConstant(0, Tmp2.getValueType()),
1999                             Node->getOperand(2));
2000      }
2001      break;
2002    }
2003    break;
2004  case ISD::BR_CC:
2005    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
2006    // Ensure that libcalls are emitted before a branch.
2007    Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2008    Tmp1 = LegalizeOp(Tmp1);
2009    Tmp2 = Node->getOperand(2);              // LHS
2010    Tmp3 = Node->getOperand(3);              // RHS
2011    Tmp4 = Node->getOperand(1);              // CC
2012
2013    LegalizeSetCC(TLI.getSetCCResultType(Tmp2), Tmp2, Tmp3, Tmp4);
2014    LastCALLSEQ_END = DAG.getEntryNode();
2015
2016    // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2017    // the LHS is a legal SETCC itself.  In this case, we need to compare
2018    // the result against zero to select between true and false values.
2019    if (Tmp3.getNode() == 0) {
2020      Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2021      Tmp4 = DAG.getCondCode(ISD::SETNE);
2022    }
2023
2024    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2025                                    Node->getOperand(4));
2026
2027    switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2028    default: assert(0 && "Unexpected action for BR_CC!");
2029    case TargetLowering::Legal: break;
2030    case TargetLowering::Custom:
2031      Tmp4 = TLI.LowerOperation(Result, DAG);
2032      if (Tmp4.getNode()) Result = Tmp4;
2033      break;
2034    }
2035    break;
2036  case ISD::LOAD: {
2037    LoadSDNode *LD = cast<LoadSDNode>(Node);
2038    Tmp1 = LegalizeOp(LD->getChain());   // Legalize the chain.
2039    Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2040
2041    ISD::LoadExtType ExtType = LD->getExtensionType();
2042    if (ExtType == ISD::NON_EXTLOAD) {
2043      MVT VT = Node->getValueType(0);
2044      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2045      Tmp3 = Result.getValue(0);
2046      Tmp4 = Result.getValue(1);
2047
2048      switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2049      default: assert(0 && "This action is not supported yet!");
2050      case TargetLowering::Legal:
2051        // If this is an unaligned load and the target doesn't support it,
2052        // expand it.
2053        if (!TLI.allowsUnalignedMemoryAccesses()) {
2054          unsigned ABIAlignment = TLI.getTargetData()->
2055            getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2056          if (LD->getAlignment() < ABIAlignment){
2057            Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2058                                         TLI);
2059            Tmp3 = Result.getOperand(0);
2060            Tmp4 = Result.getOperand(1);
2061            Tmp3 = LegalizeOp(Tmp3);
2062            Tmp4 = LegalizeOp(Tmp4);
2063          }
2064        }
2065        break;
2066      case TargetLowering::Custom:
2067        Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2068        if (Tmp1.getNode()) {
2069          Tmp3 = LegalizeOp(Tmp1);
2070          Tmp4 = LegalizeOp(Tmp1.getValue(1));
2071        }
2072        break;
2073      case TargetLowering::Promote: {
2074        // Only promote a load of vector type to another.
2075        assert(VT.isVector() && "Cannot promote this load!");
2076        // Change base type to a different vector type.
2077        MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2078
2079        Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
2080                           LD->getSrcValueOffset(),
2081                           LD->isVolatile(), LD->getAlignment());
2082        Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
2083        Tmp4 = LegalizeOp(Tmp1.getValue(1));
2084        break;
2085      }
2086      }
2087      // Since loads produce two values, make sure to remember that we
2088      // legalized both of them.
2089      AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2090      AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2091      return Op.getResNo() ? Tmp4 : Tmp3;
2092    } else {
2093      MVT SrcVT = LD->getMemoryVT();
2094      unsigned SrcWidth = SrcVT.getSizeInBits();
2095      int SVOffset = LD->getSrcValueOffset();
2096      unsigned Alignment = LD->getAlignment();
2097      bool isVolatile = LD->isVolatile();
2098
2099      if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2100          // Some targets pretend to have an i1 loading operation, and actually
2101          // load an i8.  This trick is correct for ZEXTLOAD because the top 7
2102          // bits are guaranteed to be zero; it helps the optimizers understand
2103          // that these bits are zero.  It is also useful for EXTLOAD, since it
2104          // tells the optimizers that those bits are undefined.  It would be
2105          // nice to have an effective generic way of getting these benefits...
2106          // Until such a way is found, don't insist on promoting i1 here.
2107          (SrcVT != MVT::i1 ||
2108           TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2109        // Promote to a byte-sized load if not loading an integral number of
2110        // bytes.  For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2111        unsigned NewWidth = SrcVT.getStoreSizeInBits();
2112        MVT NVT = MVT::getIntegerVT(NewWidth);
2113        SDValue Ch;
2114
2115        // The extra bits are guaranteed to be zero, since we stored them that
2116        // way.  A zext load from NVT thus automatically gives zext from SrcVT.
2117
2118        ISD::LoadExtType NewExtType =
2119          ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2120
2121        Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2122                                Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2123                                NVT, isVolatile, Alignment);
2124
2125        Ch = Result.getValue(1); // The chain.
2126
2127        if (ExtType == ISD::SEXTLOAD)
2128          // Having the top bits zero doesn't help when sign extending.
2129          Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2130                               Result, DAG.getValueType(SrcVT));
2131        else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2132          // All the top bits are guaranteed to be zero - inform the optimizers.
2133          Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2134                               DAG.getValueType(SrcVT));
2135
2136        Tmp1 = LegalizeOp(Result);
2137        Tmp2 = LegalizeOp(Ch);
2138      } else if (SrcWidth & (SrcWidth - 1)) {
2139        // If not loading a power-of-2 number of bits, expand as two loads.
2140        assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2141               "Unsupported extload!");
2142        unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2143        assert(RoundWidth < SrcWidth);
2144        unsigned ExtraWidth = SrcWidth - RoundWidth;
2145        assert(ExtraWidth < RoundWidth);
2146        assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2147               "Load size not an integral number of bytes!");
2148        MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2149        MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2150        SDValue Lo, Hi, Ch;
2151        unsigned IncrementSize;
2152
2153        if (TLI.isLittleEndian()) {
2154          // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2155          // Load the bottom RoundWidth bits.
2156          Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2157                              LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2158                              Alignment);
2159
2160          // Load the remaining ExtraWidth bits.
2161          IncrementSize = RoundWidth / 8;
2162          Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2163                             DAG.getIntPtrConstant(IncrementSize));
2164          Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2165                              LD->getSrcValue(), SVOffset + IncrementSize,
2166                              ExtraVT, isVolatile,
2167                              MinAlign(Alignment, IncrementSize));
2168
2169          // Build a factor node to remember that this load is independent of the
2170          // other one.
2171          Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2172                           Hi.getValue(1));
2173
2174          // Move the top bits to the right place.
2175          Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2176                           DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2177
2178          // Join the hi and lo parts.
2179          Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2180        } else {
2181          // Big endian - avoid unaligned loads.
2182          // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2183          // Load the top RoundWidth bits.
2184          Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2185                              LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2186                              Alignment);
2187
2188          // Load the remaining ExtraWidth bits.
2189          IncrementSize = RoundWidth / 8;
2190          Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2191                             DAG.getIntPtrConstant(IncrementSize));
2192          Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2193                              LD->getSrcValue(), SVOffset + IncrementSize,
2194                              ExtraVT, isVolatile,
2195                              MinAlign(Alignment, IncrementSize));
2196
2197          // Build a factor node to remember that this load is independent of the
2198          // other one.
2199          Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2200                           Hi.getValue(1));
2201
2202          // Move the top bits to the right place.
2203          Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2204                           DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2205
2206          // Join the hi and lo parts.
2207          Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2208        }
2209
2210        Tmp1 = LegalizeOp(Result);
2211        Tmp2 = LegalizeOp(Ch);
2212      } else {
2213        switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2214        default: assert(0 && "This action is not supported yet!");
2215        case TargetLowering::Custom:
2216          isCustom = true;
2217          // FALLTHROUGH
2218        case TargetLowering::Legal:
2219          Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2220          Tmp1 = Result.getValue(0);
2221          Tmp2 = Result.getValue(1);
2222
2223          if (isCustom) {
2224            Tmp3 = TLI.LowerOperation(Result, DAG);
2225            if (Tmp3.getNode()) {
2226              Tmp1 = LegalizeOp(Tmp3);
2227              Tmp2 = LegalizeOp(Tmp3.getValue(1));
2228            }
2229          } else {
2230            // If this is an unaligned load and the target doesn't support it,
2231            // expand it.
2232            if (!TLI.allowsUnalignedMemoryAccesses()) {
2233              unsigned ABIAlignment = TLI.getTargetData()->
2234                getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2235              if (LD->getAlignment() < ABIAlignment){
2236                Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2237                                             TLI);
2238                Tmp1 = Result.getOperand(0);
2239                Tmp2 = Result.getOperand(1);
2240                Tmp1 = LegalizeOp(Tmp1);
2241                Tmp2 = LegalizeOp(Tmp2);
2242              }
2243            }
2244          }
2245          break;
2246        case TargetLowering::Expand:
2247          // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2248          if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2249            SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2250                                         LD->getSrcValueOffset(),
2251                                         LD->isVolatile(), LD->getAlignment());
2252            Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2253            Tmp1 = LegalizeOp(Result);  // Relegalize new nodes.
2254            Tmp2 = LegalizeOp(Load.getValue(1));
2255            break;
2256          }
2257          assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2258          // Turn the unsupported load into an EXTLOAD followed by an explicit
2259          // zero/sign extend inreg.
2260          Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2261                                  Tmp1, Tmp2, LD->getSrcValue(),
2262                                  LD->getSrcValueOffset(), SrcVT,
2263                                  LD->isVolatile(), LD->getAlignment());
2264          SDValue ValRes;
2265          if (ExtType == ISD::SEXTLOAD)
2266            ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2267                                 Result, DAG.getValueType(SrcVT));
2268          else
2269            ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2270          Tmp1 = LegalizeOp(ValRes);  // Relegalize new nodes.
2271          Tmp2 = LegalizeOp(Result.getValue(1));  // Relegalize new nodes.
2272          break;
2273        }
2274      }
2275
2276      // Since loads produce two values, make sure to remember that we legalized
2277      // both of them.
2278      AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2279      AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2280      return Op.getResNo() ? Tmp2 : Tmp1;
2281    }
2282  }
2283  case ISD::EXTRACT_ELEMENT: {
2284    MVT OpTy = Node->getOperand(0).getValueType();
2285    switch (getTypeAction(OpTy)) {
2286    default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2287    case Legal:
2288      if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2289        // 1 -> Hi
2290        Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2291                             DAG.getConstant(OpTy.getSizeInBits()/2,
2292                                             TLI.getShiftAmountTy()));
2293        Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2294      } else {
2295        // 0 -> Lo
2296        Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2297                             Node->getOperand(0));
2298      }
2299      break;
2300    case Expand:
2301      // Get both the low and high parts.
2302      ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2303      if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2304        Result = Tmp2;  // 1 -> Hi
2305      else
2306        Result = Tmp1;  // 0 -> Lo
2307      break;
2308    }
2309    break;
2310  }
2311
2312  case ISD::CopyToReg:
2313    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
2314
2315    assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2316           "Register type must be legal!");
2317    // Legalize the incoming value (must be a legal type).
2318    Tmp2 = LegalizeOp(Node->getOperand(2));
2319    if (Node->getNumValues() == 1) {
2320      Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2321    } else {
2322      assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2323      if (Node->getNumOperands() == 4) {
2324        Tmp3 = LegalizeOp(Node->getOperand(3));
2325        Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2326                                        Tmp3);
2327      } else {
2328        Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2329      }
2330
2331      // Since this produces two values, make sure to remember that we legalized
2332      // both of them.
2333      AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2334      AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2335      return Result;
2336    }
2337    break;
2338
2339  case ISD::RET:
2340    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
2341
2342    // Ensure that libcalls are emitted before a return.
2343    Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2344    Tmp1 = LegalizeOp(Tmp1);
2345    LastCALLSEQ_END = DAG.getEntryNode();
2346
2347    switch (Node->getNumOperands()) {
2348    case 3:  // ret val
2349      Tmp2 = Node->getOperand(1);
2350      Tmp3 = Node->getOperand(2);  // Signness
2351      switch (getTypeAction(Tmp2.getValueType())) {
2352      case Legal:
2353        Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2354        break;
2355      case Expand:
2356        if (!Tmp2.getValueType().isVector()) {
2357          SDValue Lo, Hi;
2358          ExpandOp(Tmp2, Lo, Hi);
2359
2360          // Big endian systems want the hi reg first.
2361          if (TLI.isBigEndian())
2362            std::swap(Lo, Hi);
2363
2364          if (Hi.getNode())
2365            Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2366          else
2367            Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2368          Result = LegalizeOp(Result);
2369        } else {
2370          SDNode *InVal = Tmp2.getNode();
2371          int InIx = Tmp2.getResNo();
2372          unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2373          MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2374
2375          // Figure out if there is a simple type corresponding to this Vector
2376          // type.  If so, convert to the vector type.
2377          MVT TVT = MVT::getVectorVT(EVT, NumElems);
2378          if (TLI.isTypeLegal(TVT)) {
2379            // Turn this into a return of the vector type.
2380            Tmp2 = LegalizeOp(Tmp2);
2381            Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2382          } else if (NumElems == 1) {
2383            // Turn this into a return of the scalar type.
2384            Tmp2 = ScalarizeVectorOp(Tmp2);
2385            Tmp2 = LegalizeOp(Tmp2);
2386            Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2387
2388            // FIXME: Returns of gcc generic vectors smaller than a legal type
2389            // should be returned in integer registers!
2390
2391            // The scalarized value type may not be legal, e.g. it might require
2392            // promotion or expansion.  Relegalize the return.
2393            Result = LegalizeOp(Result);
2394          } else {
2395            // FIXME: Returns of gcc generic vectors larger than a legal vector
2396            // type should be returned by reference!
2397            SDValue Lo, Hi;
2398            SplitVectorOp(Tmp2, Lo, Hi);
2399            Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2400            Result = LegalizeOp(Result);
2401          }
2402        }
2403        break;
2404      case Promote:
2405        Tmp2 = PromoteOp(Node->getOperand(1));
2406        Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2407        Result = LegalizeOp(Result);
2408        break;
2409      }
2410      break;
2411    case 1:  // ret void
2412      Result = DAG.UpdateNodeOperands(Result, Tmp1);
2413      break;
2414    default: { // ret <values>
2415      SmallVector<SDValue, 8> NewValues;
2416      NewValues.push_back(Tmp1);
2417      for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2418        switch (getTypeAction(Node->getOperand(i).getValueType())) {
2419        case Legal:
2420          NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2421          NewValues.push_back(Node->getOperand(i+1));
2422          break;
2423        case Expand: {
2424          SDValue Lo, Hi;
2425          assert(!Node->getOperand(i).getValueType().isExtended() &&
2426                 "FIXME: TODO: implement returning non-legal vector types!");
2427          ExpandOp(Node->getOperand(i), Lo, Hi);
2428          NewValues.push_back(Lo);
2429          NewValues.push_back(Node->getOperand(i+1));
2430          if (Hi.getNode()) {
2431            NewValues.push_back(Hi);
2432            NewValues.push_back(Node->getOperand(i+1));
2433          }
2434          break;
2435        }
2436        case Promote:
2437          assert(0 && "Can't promote multiple return value yet!");
2438        }
2439
2440      if (NewValues.size() == Node->getNumOperands())
2441        Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2442      else
2443        Result = DAG.getNode(ISD::RET, MVT::Other,
2444                             &NewValues[0], NewValues.size());
2445      break;
2446    }
2447    }
2448
2449    if (Result.getOpcode() == ISD::RET) {
2450      switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2451      default: assert(0 && "This action is not supported yet!");
2452      case TargetLowering::Legal: break;
2453      case TargetLowering::Custom:
2454        Tmp1 = TLI.LowerOperation(Result, DAG);
2455        if (Tmp1.getNode()) Result = Tmp1;
2456        break;
2457      }
2458    }
2459    break;
2460  case ISD::STORE: {
2461    StoreSDNode *ST = cast<StoreSDNode>(Node);
2462    Tmp1 = LegalizeOp(ST->getChain());    // Legalize the chain.
2463    Tmp2 = LegalizeOp(ST->getBasePtr());  // Legalize the pointer.
2464    int SVOffset = ST->getSrcValueOffset();
2465    unsigned Alignment = ST->getAlignment();
2466    bool isVolatile = ST->isVolatile();
2467
2468    if (!ST->isTruncatingStore()) {
2469      // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2470      // FIXME: We shouldn't do this for TargetConstantFP's.
2471      // FIXME: move this to the DAG Combiner!  Note that we can't regress due
2472      // to phase ordering between legalized code and the dag combiner.  This
2473      // probably means that we need to integrate dag combiner and legalizer
2474      // together.
2475      // We generally can't do this one for long doubles.
2476      if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2477        if (CFP->getValueType(0) == MVT::f32 &&
2478            getTypeAction(MVT::i32) == Legal) {
2479          Tmp3 = DAG.getConstant(CFP->getValueAPF().
2480                                          bitcastToAPInt().zextOrTrunc(32),
2481                                  MVT::i32);
2482          Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2483                                SVOffset, isVolatile, Alignment);
2484          break;
2485        } else if (CFP->getValueType(0) == MVT::f64) {
2486          // If this target supports 64-bit registers, do a single 64-bit store.
2487          if (getTypeAction(MVT::i64) == Legal) {
2488            Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2489                                     zextOrTrunc(64), MVT::i64);
2490            Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2491                                  SVOffset, isVolatile, Alignment);
2492            break;
2493          } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2494            // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2495            // stores.  If the target supports neither 32- nor 64-bits, this
2496            // xform is certainly not worth it.
2497            const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2498            SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2499            SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2500            if (TLI.isBigEndian()) std::swap(Lo, Hi);
2501
2502            Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2503                              SVOffset, isVolatile, Alignment);
2504            Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2505                               DAG.getIntPtrConstant(4));
2506            Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2507                              isVolatile, MinAlign(Alignment, 4U));
2508
2509            Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2510            break;
2511          }
2512        }
2513      }
2514
2515      switch (getTypeAction(ST->getMemoryVT())) {
2516      case Legal: {
2517        Tmp3 = LegalizeOp(ST->getValue());
2518        Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2519                                        ST->getOffset());
2520
2521        MVT VT = Tmp3.getValueType();
2522        switch (TLI.getOperationAction(ISD::STORE, VT)) {
2523        default: assert(0 && "This action is not supported yet!");
2524        case TargetLowering::Legal:
2525          // If this is an unaligned store and the target doesn't support it,
2526          // expand it.
2527          if (!TLI.allowsUnalignedMemoryAccesses()) {
2528            unsigned ABIAlignment = TLI.getTargetData()->
2529              getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2530            if (ST->getAlignment() < ABIAlignment)
2531              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2532                                            TLI);
2533          }
2534          break;
2535        case TargetLowering::Custom:
2536          Tmp1 = TLI.LowerOperation(Result, DAG);
2537          if (Tmp1.getNode()) Result = Tmp1;
2538          break;
2539        case TargetLowering::Promote:
2540          assert(VT.isVector() && "Unknown legal promote case!");
2541          Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2542                             TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2543          Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2544                                ST->getSrcValue(), SVOffset, isVolatile,
2545                                Alignment);
2546          break;
2547        }
2548        break;
2549      }
2550      case Promote:
2551        if (!ST->getMemoryVT().isVector()) {
2552          // Truncate the value and store the result.
2553          Tmp3 = PromoteOp(ST->getValue());
2554          Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2555                                     SVOffset, ST->getMemoryVT(),
2556                                     isVolatile, Alignment);
2557          break;
2558        }
2559        // Fall thru to expand for vector
2560      case Expand: {
2561        unsigned IncrementSize = 0;
2562        SDValue Lo, Hi;
2563
2564        // If this is a vector type, then we have to calculate the increment as
2565        // the product of the element size in bytes, and the number of elements
2566        // in the high half of the vector.
2567        if (ST->getValue().getValueType().isVector()) {
2568          SDNode *InVal = ST->getValue().getNode();
2569          int InIx = ST->getValue().getResNo();
2570          MVT InVT = InVal->getValueType(InIx);
2571          unsigned NumElems = InVT.getVectorNumElements();
2572          MVT EVT = InVT.getVectorElementType();
2573
2574          // Figure out if there is a simple type corresponding to this Vector
2575          // type.  If so, convert to the vector type.
2576          MVT TVT = MVT::getVectorVT(EVT, NumElems);
2577          if (TLI.isTypeLegal(TVT)) {
2578            // Turn this into a normal store of the vector type.
2579            Tmp3 = LegalizeOp(ST->getValue());
2580            Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2581                                  SVOffset, isVolatile, Alignment);
2582            Result = LegalizeOp(Result);
2583            break;
2584          } else if (NumElems == 1) {
2585            // Turn this into a normal store of the scalar type.
2586            Tmp3 = ScalarizeVectorOp(ST->getValue());
2587            Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2588                                  SVOffset, isVolatile, Alignment);
2589            // The scalarized value type may not be legal, e.g. it might require
2590            // promotion or expansion.  Relegalize the scalar store.
2591            Result = LegalizeOp(Result);
2592            break;
2593          } else {
2594            // Check if we have widen this node with another value
2595            std::map<SDValue, SDValue>::iterator I =
2596              WidenNodes.find(ST->getValue());
2597            if (I != WidenNodes.end()) {
2598              Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2599              break;
2600            }
2601            else {
2602              SplitVectorOp(ST->getValue(), Lo, Hi);
2603              IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2604                              EVT.getSizeInBits()/8;
2605            }
2606          }
2607        } else {
2608          ExpandOp(ST->getValue(), Lo, Hi);
2609          IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2610
2611          if (Hi.getNode() && TLI.isBigEndian())
2612            std::swap(Lo, Hi);
2613        }
2614
2615        Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2616                          SVOffset, isVolatile, Alignment);
2617
2618        if (Hi.getNode() == NULL) {
2619          // Must be int <-> float one-to-one expansion.
2620          Result = Lo;
2621          break;
2622        }
2623
2624        Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2625                           DAG.getIntPtrConstant(IncrementSize));
2626        assert(isTypeLegal(Tmp2.getValueType()) &&
2627               "Pointers must be legal!");
2628        SVOffset += IncrementSize;
2629        Alignment = MinAlign(Alignment, IncrementSize);
2630        Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2631                          SVOffset, isVolatile, Alignment);
2632        Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2633        break;
2634      }  // case Expand
2635      }
2636    } else {
2637      switch (getTypeAction(ST->getValue().getValueType())) {
2638      case Legal:
2639        Tmp3 = LegalizeOp(ST->getValue());
2640        break;
2641      case Promote:
2642        if (!ST->getValue().getValueType().isVector()) {
2643          // We can promote the value, the truncstore will still take care of it.
2644          Tmp3 = PromoteOp(ST->getValue());
2645          break;
2646        }
2647        // Vector case falls through to expand
2648      case Expand:
2649        // Just store the low part.  This may become a non-trunc store, so make
2650        // sure to use getTruncStore, not UpdateNodeOperands below.
2651        ExpandOp(ST->getValue(), Tmp3, Tmp4);
2652        return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2653                                 SVOffset, MVT::i8, isVolatile, Alignment);
2654      }
2655
2656      MVT StVT = ST->getMemoryVT();
2657      unsigned StWidth = StVT.getSizeInBits();
2658
2659      if (StWidth != StVT.getStoreSizeInBits()) {
2660        // Promote to a byte-sized store with upper bits zero if not
2661        // storing an integral number of bytes.  For example, promote
2662        // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2663        MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2664        Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2665        Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2666                                   SVOffset, NVT, isVolatile, Alignment);
2667      } else if (StWidth & (StWidth - 1)) {
2668        // If not storing a power-of-2 number of bits, expand as two stores.
2669        assert(StVT.isExtended() && !StVT.isVector() &&
2670               "Unsupported truncstore!");
2671        unsigned RoundWidth = 1 << Log2_32(StWidth);
2672        assert(RoundWidth < StWidth);
2673        unsigned ExtraWidth = StWidth - RoundWidth;
2674        assert(ExtraWidth < RoundWidth);
2675        assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2676               "Store size not an integral number of bytes!");
2677        MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2678        MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2679        SDValue Lo, Hi;
2680        unsigned IncrementSize;
2681
2682        if (TLI.isLittleEndian()) {
2683          // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2684          // Store the bottom RoundWidth bits.
2685          Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2686                                 SVOffset, RoundVT,
2687                                 isVolatile, Alignment);
2688
2689          // Store the remaining ExtraWidth bits.
2690          IncrementSize = RoundWidth / 8;
2691          Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2692                             DAG.getIntPtrConstant(IncrementSize));
2693          Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2694                           DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2695          Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2696                                 SVOffset + IncrementSize, ExtraVT, isVolatile,
2697                                 MinAlign(Alignment, IncrementSize));
2698        } else {
2699          // Big endian - avoid unaligned stores.
2700          // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2701          // Store the top RoundWidth bits.
2702          Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2703                           DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2704          Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2705                                 RoundVT, isVolatile, Alignment);
2706
2707          // Store the remaining ExtraWidth bits.
2708          IncrementSize = RoundWidth / 8;
2709          Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2710                             DAG.getIntPtrConstant(IncrementSize));
2711          Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2712                                 SVOffset + IncrementSize, ExtraVT, isVolatile,
2713                                 MinAlign(Alignment, IncrementSize));
2714        }
2715
2716        // The order of the stores doesn't matter.
2717        Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2718      } else {
2719        if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2720            Tmp2 != ST->getBasePtr())
2721          Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2722                                          ST->getOffset());
2723
2724        switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2725        default: assert(0 && "This action is not supported yet!");
2726        case TargetLowering::Legal:
2727          // If this is an unaligned store and the target doesn't support it,
2728          // expand it.
2729          if (!TLI.allowsUnalignedMemoryAccesses()) {
2730            unsigned ABIAlignment = TLI.getTargetData()->
2731              getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2732            if (ST->getAlignment() < ABIAlignment)
2733              Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2734                                            TLI);
2735          }
2736          break;
2737        case TargetLowering::Custom:
2738          Result = TLI.LowerOperation(Result, DAG);
2739          break;
2740        case Expand:
2741          // TRUNCSTORE:i16 i32 -> STORE i16
2742          assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2743          Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2744          Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2745                                isVolatile, Alignment);
2746          break;
2747        }
2748      }
2749    }
2750    break;
2751  }
2752  case ISD::PCMARKER:
2753    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
2754    Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2755    break;
2756  case ISD::STACKSAVE:
2757    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
2758    Result = DAG.UpdateNodeOperands(Result, Tmp1);
2759    Tmp1 = Result.getValue(0);
2760    Tmp2 = Result.getValue(1);
2761
2762    switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2763    default: assert(0 && "This action is not supported yet!");
2764    case TargetLowering::Legal: break;
2765    case TargetLowering::Custom:
2766      Tmp3 = TLI.LowerOperation(Result, DAG);
2767      if (Tmp3.getNode()) {
2768        Tmp1 = LegalizeOp(Tmp3);
2769        Tmp2 = LegalizeOp(Tmp3.getValue(1));
2770      }
2771      break;
2772    case TargetLowering::Expand:
2773      // Expand to CopyFromReg if the target set
2774      // StackPointerRegisterToSaveRestore.
2775      if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2776        Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2777                                  Node->getValueType(0));
2778        Tmp2 = Tmp1.getValue(1);
2779      } else {
2780        Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2781        Tmp2 = Node->getOperand(0);
2782      }
2783      break;
2784    }
2785
2786    // Since stacksave produce two values, make sure to remember that we
2787    // legalized both of them.
2788    AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2789    AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2790    return Op.getResNo() ? Tmp2 : Tmp1;
2791
2792  case ISD::STACKRESTORE:
2793    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
2794    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
2795    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2796
2797    switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2798    default: assert(0 && "This action is not supported yet!");
2799    case TargetLowering::Legal: break;
2800    case TargetLowering::Custom:
2801      Tmp1 = TLI.LowerOperation(Result, DAG);
2802      if (Tmp1.getNode()) Result = Tmp1;
2803      break;
2804    case TargetLowering::Expand:
2805      // Expand to CopyToReg if the target set
2806      // StackPointerRegisterToSaveRestore.
2807      if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2808        Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2809      } else {
2810        Result = Tmp1;
2811      }
2812      break;
2813    }
2814    break;
2815
2816  case ISD::READCYCLECOUNTER:
2817    Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2818    Result = DAG.UpdateNodeOperands(Result, Tmp1);
2819    switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2820                                   Node->getValueType(0))) {
2821    default: assert(0 && "This action is not supported yet!");
2822    case TargetLowering::Legal:
2823      Tmp1 = Result.getValue(0);
2824      Tmp2 = Result.getValue(1);
2825      break;
2826    case TargetLowering::Custom:
2827      Result = TLI.LowerOperation(Result, DAG);
2828      Tmp1 = LegalizeOp(Result.getValue(0));
2829      Tmp2 = LegalizeOp(Result.getValue(1));
2830      break;
2831    }
2832
2833    // Since rdcc produce two values, make sure to remember that we legalized
2834    // both of them.
2835    AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2836    AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2837    return Result;
2838
2839  case ISD::SELECT:
2840    switch (getTypeAction(Node->getOperand(0).getValueType())) {
2841    case Expand: assert(0 && "It's impossible to expand bools");
2842    case Legal:
2843      Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2844      break;
2845    case Promote: {
2846      assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2847      Tmp1 = PromoteOp(Node->getOperand(0));  // Promote the condition.
2848      // Make sure the condition is either zero or one.
2849      unsigned BitWidth = Tmp1.getValueSizeInBits();
2850      if (!DAG.MaskedValueIsZero(Tmp1,
2851                                 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2852        Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2853      break;
2854    }
2855    }
2856    Tmp2 = LegalizeOp(Node->getOperand(1));   // TrueVal
2857    Tmp3 = LegalizeOp(Node->getOperand(2));   // FalseVal
2858
2859    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2860
2861    switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2862    default: assert(0 && "This action is not supported yet!");
2863    case TargetLowering::Legal: break;
2864    case TargetLowering::Custom: {
2865      Tmp1 = TLI.LowerOperation(Result, DAG);
2866      if (Tmp1.getNode()) Result = Tmp1;
2867      break;
2868    }
2869    case TargetLowering::Expand:
2870      if (Tmp1.getOpcode() == ISD::SETCC) {
2871        Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2872                              Tmp2, Tmp3,
2873                              cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2874      } else {
2875        Result = DAG.getSelectCC(Tmp1,
2876                                 DAG.getConstant(0, Tmp1.getValueType()),
2877                                 Tmp2, Tmp3, ISD::SETNE);
2878      }
2879      break;
2880    case TargetLowering::Promote: {
2881      MVT NVT =
2882        TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2883      unsigned ExtOp, TruncOp;
2884      if (Tmp2.getValueType().isVector()) {
2885        ExtOp   = ISD::BIT_CONVERT;
2886        TruncOp = ISD::BIT_CONVERT;
2887      } else if (Tmp2.getValueType().isInteger()) {
2888        ExtOp   = ISD::ANY_EXTEND;
2889        TruncOp = ISD::TRUNCATE;
2890      } else {
2891        ExtOp   = ISD::FP_EXTEND;
2892        TruncOp = ISD::FP_ROUND;
2893      }
2894      // Promote each of the values to the new type.
2895      Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2896      Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2897      // Perform the larger operation, then round down.
2898      Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2899      if (TruncOp != ISD::FP_ROUND)
2900        Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2901      else
2902        Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2903                             DAG.getIntPtrConstant(0));
2904      break;
2905    }
2906    }
2907    break;
2908  case ISD::SELECT_CC: {
2909    Tmp1 = Node->getOperand(0);               // LHS
2910    Tmp2 = Node->getOperand(1);               // RHS
2911    Tmp3 = LegalizeOp(Node->getOperand(2));   // True
2912    Tmp4 = LegalizeOp(Node->getOperand(3));   // False
2913    SDValue CC = Node->getOperand(4);
2914
2915    LegalizeSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, CC);
2916
2917    // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2918    // the LHS is a legal SETCC itself.  In this case, we need to compare
2919    // the result against zero to select between true and false values.
2920    if (Tmp2.getNode() == 0) {
2921      Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2922      CC = DAG.getCondCode(ISD::SETNE);
2923    }
2924    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2925
2926    // Everything is legal, see if we should expand this op or something.
2927    switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2928    default: assert(0 && "This action is not supported yet!");
2929    case TargetLowering::Legal: break;
2930    case TargetLowering::Custom:
2931      Tmp1 = TLI.LowerOperation(Result, DAG);
2932      if (Tmp1.getNode()) Result = Tmp1;
2933      break;
2934    }
2935    break;
2936  }
2937  case ISD::SETCC:
2938    Tmp1 = Node->getOperand(0);
2939    Tmp2 = Node->getOperand(1);
2940    Tmp3 = Node->getOperand(2);
2941    LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3);
2942
2943    // If we had to Expand the SetCC operands into a SELECT node, then it may
2944    // not always be possible to return a true LHS & RHS.  In this case, just
2945    // return the value we legalized, returned in the LHS
2946    if (Tmp2.getNode() == 0) {
2947      Result = Tmp1;
2948      break;
2949    }
2950
2951    switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2952    default: assert(0 && "Cannot handle this action for SETCC yet!");
2953    case TargetLowering::Custom:
2954      isCustom = true;
2955      // FALLTHROUGH.
2956    case TargetLowering::Legal:
2957      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2958      if (isCustom) {
2959        Tmp4 = TLI.LowerOperation(Result, DAG);
2960        if (Tmp4.getNode()) Result = Tmp4;
2961      }
2962      break;
2963    case TargetLowering::Promote: {
2964      // First step, figure out the appropriate operation to use.
2965      // Allow SETCC to not be supported for all legal data types
2966      // Mostly this targets FP
2967      MVT NewInTy = Node->getOperand(0).getValueType();
2968      MVT OldVT = NewInTy; OldVT = OldVT;
2969
2970      // Scan for the appropriate larger type to use.
2971      while (1) {
2972        NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2973
2974        assert(NewInTy.isInteger() == OldVT.isInteger() &&
2975               "Fell off of the edge of the integer world");
2976        assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2977               "Fell off of the edge of the floating point world");
2978
2979        // If the target supports SETCC of this type, use it.
2980        if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2981          break;
2982      }
2983      if (NewInTy.isInteger())
2984        assert(0 && "Cannot promote Legal Integer SETCC yet");
2985      else {
2986        Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2987        Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2988      }
2989      Tmp1 = LegalizeOp(Tmp1);
2990      Tmp2 = LegalizeOp(Tmp2);
2991      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2992      Result = LegalizeOp(Result);
2993      break;
2994    }
2995    case TargetLowering::Expand:
2996      // Expand a setcc node into a select_cc of the same condition, lhs, and
2997      // rhs that selects between const 1 (true) and const 0 (false).
2998      MVT VT = Node->getValueType(0);
2999      Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
3000                           DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3001                           Tmp3);
3002      break;
3003    }
3004    break;
3005  case ISD::VSETCC: {
3006    Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
3007    Tmp2 = LegalizeOp(Node->getOperand(1));   // RHS
3008    SDValue CC = Node->getOperand(2);
3009
3010    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3011
3012    // Everything is legal, see if we should expand this op or something.
3013    switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3014    default: assert(0 && "This action is not supported yet!");
3015    case TargetLowering::Legal: break;
3016    case TargetLowering::Custom:
3017      Tmp1 = TLI.LowerOperation(Result, DAG);
3018      if (Tmp1.getNode()) Result = Tmp1;
3019      break;
3020    }
3021    break;
3022  }
3023
3024  case ISD::SHL_PARTS:
3025  case ISD::SRA_PARTS:
3026  case ISD::SRL_PARTS: {
3027    SmallVector<SDValue, 8> Ops;
3028    bool Changed = false;
3029    for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3030      Ops.push_back(LegalizeOp(Node->getOperand(i)));
3031      Changed |= Ops.back() != Node->getOperand(i);
3032    }
3033    if (Changed)
3034      Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3035
3036    switch (TLI.getOperationAction(Node->getOpcode(),
3037                                   Node->getValueType(0))) {
3038    default: assert(0 && "This action is not supported yet!");
3039    case TargetLowering::Legal: break;
3040    case TargetLowering::Custom:
3041      Tmp1 = TLI.LowerOperation(Result, DAG);
3042      if (Tmp1.getNode()) {
3043        SDValue Tmp2, RetVal(0, 0);
3044        for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3045          Tmp2 = LegalizeOp(Tmp1.getValue(i));
3046          AddLegalizedOperand(SDValue(Node, i), Tmp2);
3047          if (i == Op.getResNo())
3048            RetVal = Tmp2;
3049        }
3050        assert(RetVal.getNode() && "Illegal result number");
3051        return RetVal;
3052      }
3053      break;
3054    }
3055
3056    // Since these produce multiple values, make sure to remember that we
3057    // legalized all of them.
3058    for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3059      AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3060    return Result.getValue(Op.getResNo());
3061  }
3062
3063    // Binary operators
3064  case ISD::ADD:
3065  case ISD::SUB:
3066  case ISD::MUL:
3067  case ISD::MULHS:
3068  case ISD::MULHU:
3069  case ISD::UDIV:
3070  case ISD::SDIV:
3071  case ISD::AND:
3072  case ISD::OR:
3073  case ISD::XOR:
3074  case ISD::SHL:
3075  case ISD::SRL:
3076  case ISD::SRA:
3077  case ISD::FADD:
3078  case ISD::FSUB:
3079  case ISD::FMUL:
3080  case ISD::FDIV:
3081  case ISD::FPOW:
3082    Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
3083    switch (getTypeAction(Node->getOperand(1).getValueType())) {
3084    case Expand: assert(0 && "Not possible");
3085    case Legal:
3086      Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3087      break;
3088    case Promote:
3089      Tmp2 = PromoteOp(Node->getOperand(1));  // Promote the RHS.
3090      break;
3091    }
3092
3093    if ((Node->getOpcode() == ISD::SHL ||
3094         Node->getOpcode() == ISD::SRL ||
3095         Node->getOpcode() == ISD::SRA) &&
3096        !Node->getValueType(0).isVector()) {
3097      if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType()))
3098        Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2);
3099      else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType()))
3100        Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2);
3101    }
3102
3103    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3104
3105    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3106    default: assert(0 && "BinOp legalize operation not supported");
3107    case TargetLowering::Legal: break;
3108    case TargetLowering::Custom:
3109      Tmp1 = TLI.LowerOperation(Result, DAG);
3110      if (Tmp1.getNode()) {
3111        Result = Tmp1;
3112        break;
3113      }
3114      // Fall through if the custom lower can't deal with the operation
3115    case TargetLowering::Expand: {
3116      MVT VT = Op.getValueType();
3117
3118      // See if multiply or divide can be lowered using two-result operations.
3119      SDVTList VTs = DAG.getVTList(VT, VT);
3120      if (Node->getOpcode() == ISD::MUL) {
3121        // We just need the low half of the multiply; try both the signed
3122        // and unsigned forms. If the target supports both SMUL_LOHI and
3123        // UMUL_LOHI, form a preference by checking which forms of plain
3124        // MULH it supports.
3125        bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
3126        bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
3127        bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
3128        bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
3129        unsigned OpToUse = 0;
3130        if (HasSMUL_LOHI && !HasMULHS) {
3131          OpToUse = ISD::SMUL_LOHI;
3132        } else if (HasUMUL_LOHI && !HasMULHU) {
3133          OpToUse = ISD::UMUL_LOHI;
3134        } else if (HasSMUL_LOHI) {
3135          OpToUse = ISD::SMUL_LOHI;
3136        } else if (HasUMUL_LOHI) {
3137          OpToUse = ISD::UMUL_LOHI;
3138        }
3139        if (OpToUse) {
3140          Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3141          break;
3142        }
3143      }
3144      if (Node->getOpcode() == ISD::MULHS &&
3145          TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3146        Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3147                         1);
3148        break;
3149      }
3150      if (Node->getOpcode() == ISD::MULHU &&
3151          TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3152        Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3153                         1);
3154        break;
3155      }
3156      if (Node->getOpcode() == ISD::SDIV &&
3157          TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3158        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
3159                         0);
3160        break;
3161      }
3162      if (Node->getOpcode() == ISD::UDIV &&
3163          TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3164        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
3165                         0);
3166        break;
3167      }
3168
3169      // Check to see if we have a libcall for this operator.
3170      RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3171      bool isSigned = false;
3172      switch (Node->getOpcode()) {
3173      case ISD::UDIV:
3174      case ISD::SDIV:
3175        if (VT == MVT::i32) {
3176          LC = Node->getOpcode() == ISD::UDIV
3177               ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3178          isSigned = Node->getOpcode() == ISD::SDIV;
3179        }
3180        break;
3181      case ISD::MUL:
3182        if (VT == MVT::i32)
3183          LC = RTLIB::MUL_I32;
3184        break;
3185      case ISD::FPOW:
3186        LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3187                          RTLIB::POW_PPCF128);
3188        break;
3189      default: break;
3190      }
3191      if (LC != RTLIB::UNKNOWN_LIBCALL) {
3192        SDValue Dummy;
3193        Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3194        break;
3195      }
3196
3197      assert(Node->getValueType(0).isVector() &&
3198             "Cannot expand this binary operator!");
3199      // Expand the operation into a bunch of nasty scalar code.
3200      Result = LegalizeOp(UnrollVectorOp(Op));
3201      break;
3202    }
3203    case TargetLowering::Promote: {
3204      switch (Node->getOpcode()) {
3205      default:  assert(0 && "Do not know how to promote this BinOp!");
3206      case ISD::AND:
3207      case ISD::OR:
3208      case ISD::XOR: {
3209        MVT OVT = Node->getValueType(0);
3210        MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3211        assert(OVT.isVector() && "Cannot promote this BinOp!");
3212        // Bit convert each of the values to the new type.
3213        Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3214        Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3215        Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3216        // Bit convert the result back the original type.
3217        Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3218        break;
3219      }
3220      }
3221    }
3222    }
3223    break;
3224
3225  case ISD::SMUL_LOHI:
3226  case ISD::UMUL_LOHI:
3227  case ISD::SDIVREM:
3228  case ISD::UDIVREM:
3229    // These nodes will only be produced by target-specific lowering, so
3230    // they shouldn't be here if they aren't legal.
3231    assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3232           "This must be legal!");
3233
3234    Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
3235    Tmp2 = LegalizeOp(Node->getOperand(1));   // RHS
3236    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3237    break;
3238
3239  case ISD::FCOPYSIGN:  // FCOPYSIGN does not require LHS/RHS to match type!
3240    Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
3241    switch (getTypeAction(Node->getOperand(1).getValueType())) {
3242      case Expand: assert(0 && "Not possible");
3243      case Legal:
3244        Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3245        break;
3246      case Promote:
3247        Tmp2 = PromoteOp(Node->getOperand(1));  // Promote the RHS.
3248        break;
3249    }
3250
3251    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3252
3253    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3254    default: assert(0 && "Operation not supported");
3255    case TargetLowering::Custom:
3256      Tmp1 = TLI.LowerOperation(Result, DAG);
3257      if (Tmp1.getNode()) Result = Tmp1;
3258      break;
3259    case TargetLowering::Legal: break;
3260    case TargetLowering::Expand: {
3261      // If this target supports fabs/fneg natively and select is cheap,
3262      // do this efficiently.
3263      if (!TLI.isSelectExpensive() &&
3264          TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3265          TargetLowering::Legal &&
3266          TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3267          TargetLowering::Legal) {
3268        // Get the sign bit of the RHS.
3269        MVT IVT =
3270          Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3271        SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3272        SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3273                               SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3274        // Get the absolute value of the result.
3275        SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3276        // Select between the nabs and abs value based on the sign bit of
3277        // the input.
3278        Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3279                             DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3280                                         AbsVal),
3281                             AbsVal);
3282        Result = LegalizeOp(Result);
3283        break;
3284      }
3285
3286      // Otherwise, do bitwise ops!
3287      MVT NVT =
3288        Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3289      Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3290      Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3291      Result = LegalizeOp(Result);
3292      break;
3293    }
3294    }
3295    break;
3296
3297  case ISD::ADDC:
3298  case ISD::SUBC:
3299    Tmp1 = LegalizeOp(Node->getOperand(0));
3300    Tmp2 = LegalizeOp(Node->getOperand(1));
3301    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3302    Tmp3 = Result.getValue(0);
3303    Tmp4 = Result.getValue(1);
3304
3305    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3306    default: assert(0 && "This action is not supported yet!");
3307    case TargetLowering::Legal:
3308      break;
3309    case TargetLowering::Custom:
3310      Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3311      if (Tmp1.getNode() != NULL) {
3312        Tmp3 = LegalizeOp(Tmp1);
3313        Tmp4 = LegalizeOp(Tmp1.getValue(1));
3314      }
3315      break;
3316    }
3317    // Since this produces two values, make sure to remember that we legalized
3318    // both of them.
3319    AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3320    AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3321    return Op.getResNo() ? Tmp4 : Tmp3;
3322
3323  case ISD::ADDE:
3324  case ISD::SUBE:
3325    Tmp1 = LegalizeOp(Node->getOperand(0));
3326    Tmp2 = LegalizeOp(Node->getOperand(1));
3327    Tmp3 = LegalizeOp(Node->getOperand(2));
3328    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3329    Tmp3 = Result.getValue(0);
3330    Tmp4 = Result.getValue(1);
3331
3332    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3333    default: assert(0 && "This action is not supported yet!");
3334    case TargetLowering::Legal:
3335      break;
3336    case TargetLowering::Custom:
3337      Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3338      if (Tmp1.getNode() != NULL) {
3339        Tmp3 = LegalizeOp(Tmp1);
3340        Tmp4 = LegalizeOp(Tmp1.getValue(1));
3341      }
3342      break;
3343    }
3344    // Since this produces two values, make sure to remember that we legalized
3345    // both of them.
3346    AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3347    AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3348    return Op.getResNo() ? Tmp4 : Tmp3;
3349
3350  case ISD::BUILD_PAIR: {
3351    MVT PairTy = Node->getValueType(0);
3352    // TODO: handle the case where the Lo and Hi operands are not of legal type
3353    Tmp1 = LegalizeOp(Node->getOperand(0));   // Lo
3354    Tmp2 = LegalizeOp(Node->getOperand(1));   // Hi
3355    switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3356    case TargetLowering::Promote:
3357    case TargetLowering::Custom:
3358      assert(0 && "Cannot promote/custom this yet!");
3359    case TargetLowering::Legal:
3360      if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3361        Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3362      break;
3363    case TargetLowering::Expand:
3364      Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3365      Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3366      Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3367                         DAG.getConstant(PairTy.getSizeInBits()/2,
3368                                         TLI.getShiftAmountTy()));
3369      Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3370      break;
3371    }
3372    break;
3373  }
3374
3375  case ISD::UREM:
3376  case ISD::SREM:
3377  case ISD::FREM:
3378    Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
3379    Tmp2 = LegalizeOp(Node->getOperand(1));   // RHS
3380
3381    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3382    case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3383    case TargetLowering::Custom:
3384      isCustom = true;
3385      // FALLTHROUGH
3386    case TargetLowering::Legal:
3387      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3388      if (isCustom) {
3389        Tmp1 = TLI.LowerOperation(Result, DAG);
3390        if (Tmp1.getNode()) Result = Tmp1;
3391      }
3392      break;
3393    case TargetLowering::Expand: {
3394      unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3395      bool isSigned = DivOpc == ISD::SDIV;
3396      MVT VT = Node->getValueType(0);
3397
3398      // See if remainder can be lowered using two-result operations.
3399      SDVTList VTs = DAG.getVTList(VT, VT);
3400      if (Node->getOpcode() == ISD::SREM &&
3401          TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3402        Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3403        break;
3404      }
3405      if (Node->getOpcode() == ISD::UREM &&
3406          TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3407        Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3408        break;
3409      }
3410
3411      if (VT.isInteger()) {
3412        if (TLI.getOperationAction(DivOpc, VT) ==
3413            TargetLowering::Legal) {
3414          // X % Y -> X-X/Y*Y
3415          Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3416          Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3417          Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3418        } else if (VT.isVector()) {
3419          Result = LegalizeOp(UnrollVectorOp(Op));
3420        } else {
3421          assert(VT == MVT::i32 &&
3422                 "Cannot expand this binary operator!");
3423          RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3424            ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3425          SDValue Dummy;
3426          Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3427        }
3428      } else {
3429        assert(VT.isFloatingPoint() &&
3430               "remainder op must have integer or floating-point type");
3431        if (VT.isVector()) {
3432          Result = LegalizeOp(UnrollVectorOp(Op));
3433        } else {
3434          // Floating point mod -> fmod libcall.
3435          RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3436                                           RTLIB::REM_F80, RTLIB::REM_PPCF128);
3437          SDValue Dummy;
3438          Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3439        }
3440      }
3441      break;
3442    }
3443    }
3444    break;
3445  case ISD::VAARG: {
3446    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
3447    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
3448
3449    MVT VT = Node->getValueType(0);
3450    switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3451    default: assert(0 && "This action is not supported yet!");
3452    case TargetLowering::Custom:
3453      isCustom = true;
3454      // FALLTHROUGH
3455    case TargetLowering::Legal:
3456      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3457      Result = Result.getValue(0);
3458      Tmp1 = Result.getValue(1);
3459
3460      if (isCustom) {
3461        Tmp2 = TLI.LowerOperation(Result, DAG);
3462        if (Tmp2.getNode()) {
3463          Result = LegalizeOp(Tmp2);
3464          Tmp1 = LegalizeOp(Tmp2.getValue(1));
3465        }
3466      }
3467      break;
3468    case TargetLowering::Expand: {
3469      const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3470      SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3471      // Increment the pointer, VAList, to the next vaarg
3472      Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3473        DAG.getConstant(TLI.getTargetData()->getABITypeSize(VT.getTypeForMVT()),
3474                        TLI.getPointerTy()));
3475      // Store the incremented VAList to the legalized pointer
3476      Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3477      // Load the actual argument out of the pointer VAList
3478      Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3479      Tmp1 = LegalizeOp(Result.getValue(1));
3480      Result = LegalizeOp(Result);
3481      break;
3482    }
3483    }
3484    // Since VAARG produces two values, make sure to remember that we
3485    // legalized both of them.
3486    AddLegalizedOperand(SDValue(Node, 0), Result);
3487    AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3488    return Op.getResNo() ? Tmp1 : Result;
3489  }
3490
3491  case ISD::VACOPY:
3492    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
3493    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the dest pointer.
3494    Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the source pointer.
3495
3496    switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3497    default: assert(0 && "This action is not supported yet!");
3498    case TargetLowering::Custom:
3499      isCustom = true;
3500      // FALLTHROUGH
3501    case TargetLowering::Legal:
3502      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3503                                      Node->getOperand(3), Node->getOperand(4));
3504      if (isCustom) {
3505        Tmp1 = TLI.LowerOperation(Result, DAG);
3506        if (Tmp1.getNode()) Result = Tmp1;
3507      }
3508      break;
3509    case TargetLowering::Expand:
3510      // This defaults to loading a pointer from the input and storing it to the
3511      // output, returning the chain.
3512      const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3513      const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3514      Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3515      Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3516      break;
3517    }
3518    break;
3519
3520  case ISD::VAEND:
3521    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
3522    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
3523
3524    switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3525    default: assert(0 && "This action is not supported yet!");
3526    case TargetLowering::Custom:
3527      isCustom = true;
3528      // FALLTHROUGH
3529    case TargetLowering::Legal:
3530      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3531      if (isCustom) {
3532        Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3533        if (Tmp1.getNode()) Result = Tmp1;
3534      }
3535      break;
3536    case TargetLowering::Expand:
3537      Result = Tmp1; // Default to a no-op, return the chain
3538      break;
3539    }
3540    break;
3541
3542  case ISD::VASTART:
3543    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
3544    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
3545
3546    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3547
3548    switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3549    default: assert(0 && "This action is not supported yet!");
3550    case TargetLowering::Legal: break;
3551    case TargetLowering::Custom:
3552      Tmp1 = TLI.LowerOperation(Result, DAG);
3553      if (Tmp1.getNode()) Result = Tmp1;
3554      break;
3555    }
3556    break;
3557
3558  case ISD::ROTL:
3559  case ISD::ROTR:
3560    Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
3561    Tmp2 = LegalizeOp(Node->getOperand(1));   // RHS
3562    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3563    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3564    default:
3565      assert(0 && "ROTL/ROTR legalize operation not supported");
3566      break;
3567    case TargetLowering::Legal:
3568      break;
3569    case TargetLowering::Custom:
3570      Tmp1 = TLI.LowerOperation(Result, DAG);
3571      if (Tmp1.getNode()) Result = Tmp1;
3572      break;
3573    case TargetLowering::Promote:
3574      assert(0 && "Do not know how to promote ROTL/ROTR");
3575      break;
3576    case TargetLowering::Expand:
3577      assert(0 && "Do not know how to expand ROTL/ROTR");
3578      break;
3579    }
3580    break;
3581
3582  case ISD::BSWAP:
3583    Tmp1 = LegalizeOp(Node->getOperand(0));   // Op
3584    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3585    case TargetLowering::Custom:
3586      assert(0 && "Cannot custom legalize this yet!");
3587    case TargetLowering::Legal:
3588      Result = DAG.UpdateNodeOperands(Result, Tmp1);
3589      break;
3590    case TargetLowering::Promote: {
3591      MVT OVT = Tmp1.getValueType();
3592      MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3593      unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3594
3595      Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3596      Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3597      Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3598                           DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3599      break;
3600    }
3601    case TargetLowering::Expand:
3602      Result = ExpandBSWAP(Tmp1);
3603      break;
3604    }
3605    break;
3606
3607  case ISD::CTPOP:
3608  case ISD::CTTZ:
3609  case ISD::CTLZ:
3610    Tmp1 = LegalizeOp(Node->getOperand(0));   // Op
3611    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3612    case TargetLowering::Custom:
3613    case TargetLowering::Legal:
3614      Result = DAG.UpdateNodeOperands(Result, Tmp1);
3615      if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3616          TargetLowering::Custom) {
3617        Tmp1 = TLI.LowerOperation(Result, DAG);
3618        if (Tmp1.getNode()) {
3619          Result = Tmp1;
3620        }
3621      }
3622      break;
3623    case TargetLowering::Promote: {
3624      MVT OVT = Tmp1.getValueType();
3625      MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3626
3627      // Zero extend the argument.
3628      Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3629      // Perform the larger operation, then subtract if needed.
3630      Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3631      switch (Node->getOpcode()) {
3632      case ISD::CTPOP:
3633        Result = Tmp1;
3634        break;
3635      case ISD::CTTZ:
3636        //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3637        Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3638                            DAG.getConstant(NVT.getSizeInBits(), NVT),
3639                            ISD::SETEQ);
3640        Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3641                             DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3642        break;
3643      case ISD::CTLZ:
3644        // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3645        Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3646                             DAG.getConstant(NVT.getSizeInBits() -
3647                                             OVT.getSizeInBits(), NVT));
3648        break;
3649      }
3650      break;
3651    }
3652    case TargetLowering::Expand:
3653      Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3654      break;
3655    }
3656    break;
3657
3658    // Unary operators
3659  case ISD::FABS:
3660  case ISD::FNEG:
3661  case ISD::FSQRT:
3662  case ISD::FSIN:
3663  case ISD::FCOS:
3664  case ISD::FLOG:
3665  case ISD::FLOG2:
3666  case ISD::FLOG10:
3667  case ISD::FEXP:
3668  case ISD::FEXP2:
3669  case ISD::FTRUNC:
3670  case ISD::FFLOOR:
3671  case ISD::FCEIL:
3672  case ISD::FRINT:
3673  case ISD::FNEARBYINT:
3674    Tmp1 = LegalizeOp(Node->getOperand(0));
3675    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3676    case TargetLowering::Promote:
3677    case TargetLowering::Custom:
3678     isCustom = true;
3679     // FALLTHROUGH
3680    case TargetLowering::Legal:
3681      Result = DAG.UpdateNodeOperands(Result, Tmp1);
3682      if (isCustom) {
3683        Tmp1 = TLI.LowerOperation(Result, DAG);
3684        if (Tmp1.getNode()) Result = Tmp1;
3685      }
3686      break;
3687    case TargetLowering::Expand:
3688      switch (Node->getOpcode()) {
3689      default: assert(0 && "Unreachable!");
3690      case ISD::FNEG:
3691        // Expand Y = FNEG(X) ->  Y = SUB -0.0, X
3692        Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3693        Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3694        break;
3695      case ISD::FABS: {
3696        // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3697        MVT VT = Node->getValueType(0);
3698        Tmp2 = DAG.getConstantFP(0.0, VT);
3699        Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3700                            ISD::SETUGT);
3701        Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3702        Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3703        break;
3704      }
3705      case ISD::FSQRT:
3706      case ISD::FSIN:
3707      case ISD::FCOS:
3708      case ISD::FLOG:
3709      case ISD::FLOG2:
3710      case ISD::FLOG10:
3711      case ISD::FEXP:
3712      case ISD::FEXP2:
3713      case ISD::FTRUNC:
3714      case ISD::FFLOOR:
3715      case ISD::FCEIL:
3716      case ISD::FRINT:
3717      case ISD::FNEARBYINT: {
3718        MVT VT = Node->getValueType(0);
3719
3720        // Expand unsupported unary vector operators by unrolling them.
3721        if (VT.isVector()) {
3722          Result = LegalizeOp(UnrollVectorOp(Op));
3723          break;
3724        }
3725
3726        RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3727        switch(Node->getOpcode()) {
3728        case ISD::FSQRT:
3729          LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3730                            RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3731          break;
3732        case ISD::FSIN:
3733          LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3734                            RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3735          break;
3736        case ISD::FCOS:
3737          LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3738                            RTLIB::COS_F80, RTLIB::COS_PPCF128);
3739          break;
3740        case ISD::FLOG:
3741          LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3742                            RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3743          break;
3744        case ISD::FLOG2:
3745          LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3746                            RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3747          break;
3748        case ISD::FLOG10:
3749          LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3750                            RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3751          break;
3752        case ISD::FEXP:
3753          LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3754                            RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3755          break;
3756        case ISD::FEXP2:
3757          LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3758                            RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3759          break;
3760        case ISD::FTRUNC:
3761          LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3762                            RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3763          break;
3764        case ISD::FFLOOR:
3765          LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3766                            RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3767          break;
3768        case ISD::FCEIL:
3769          LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3770                            RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3771          break;
3772        case ISD::FRINT:
3773          LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3774                            RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3775          break;
3776        case ISD::FNEARBYINT:
3777          LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3778                            RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3779          break;
3780      break;
3781        default: assert(0 && "Unreachable!");
3782        }
3783        SDValue Dummy;
3784        Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3785        break;
3786      }
3787      }
3788      break;
3789    }
3790    break;
3791  case ISD::FPOWI: {
3792    MVT VT = Node->getValueType(0);
3793
3794    // Expand unsupported unary vector operators by unrolling them.
3795    if (VT.isVector()) {
3796      Result = LegalizeOp(UnrollVectorOp(Op));
3797      break;
3798    }
3799
3800    // We always lower FPOWI into a libcall.  No target support for it yet.
3801    RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3802                                     RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3803    SDValue Dummy;
3804    Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3805    break;
3806  }
3807  case ISD::BIT_CONVERT:
3808    if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3809      Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3810                                Node->getValueType(0));
3811    } else if (Op.getOperand(0).getValueType().isVector()) {
3812      // The input has to be a vector type, we have to either scalarize it, pack
3813      // it, or convert it based on whether the input vector type is legal.
3814      SDNode *InVal = Node->getOperand(0).getNode();
3815      int InIx = Node->getOperand(0).getResNo();
3816      unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3817      MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3818
3819      // Figure out if there is a simple type corresponding to this Vector
3820      // type.  If so, convert to the vector type.
3821      MVT TVT = MVT::getVectorVT(EVT, NumElems);
3822      if (TLI.isTypeLegal(TVT)) {
3823        // Turn this into a bit convert of the vector input.
3824        Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3825                             LegalizeOp(Node->getOperand(0)));
3826        break;
3827      } else if (NumElems == 1) {
3828        // Turn this into a bit convert of the scalar input.
3829        Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3830                             ScalarizeVectorOp(Node->getOperand(0)));
3831        break;
3832      } else {
3833        // FIXME: UNIMP!  Store then reload
3834        assert(0 && "Cast from unsupported vector type not implemented yet!");
3835      }
3836    } else {
3837      switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3838                                     Node->getOperand(0).getValueType())) {
3839      default: assert(0 && "Unknown operation action!");
3840      case TargetLowering::Expand:
3841        Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3842                                  Node->getValueType(0));
3843        break;
3844      case TargetLowering::Legal:
3845        Tmp1 = LegalizeOp(Node->getOperand(0));
3846        Result = DAG.UpdateNodeOperands(Result, Tmp1);
3847        break;
3848      }
3849    }
3850    break;
3851  case ISD::CONVERT_RNDSAT: {
3852    ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
3853    switch (CvtCode) {
3854    default: assert(0 && "Unknown cvt code!");
3855    case ISD::CVT_SF:
3856    case ISD::CVT_UF:
3857      break;
3858    case ISD::CVT_FF:
3859    case ISD::CVT_FS:
3860    case ISD::CVT_FU:
3861    case ISD::CVT_SS:
3862    case ISD::CVT_SU:
3863    case ISD::CVT_US:
3864    case ISD::CVT_UU: {
3865      SDValue DTyOp = Node->getOperand(1);
3866      SDValue STyOp = Node->getOperand(2);
3867      SDValue RndOp = Node->getOperand(3);
3868      SDValue SatOp = Node->getOperand(4);
3869      switch (getTypeAction(Node->getOperand(0).getValueType())) {
3870      case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3871      case Legal:
3872        Tmp1 = LegalizeOp(Node->getOperand(0));
3873        Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
3874                                        RndOp, SatOp);
3875        if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3876            TargetLowering::Custom) {
3877          Tmp1 = TLI.LowerOperation(Result, DAG);
3878          if (Tmp1.getNode()) Result = Tmp1;
3879        }
3880        break;
3881      case Promote:
3882        Result = PromoteOp(Node->getOperand(0));
3883        // For FP, make Op1 a i32
3884
3885        Result = DAG.getConvertRndSat(Result.getValueType(), Result,
3886                                      DTyOp, STyOp, RndOp, SatOp, CvtCode);
3887        break;
3888      }
3889      break;
3890    }
3891    } // end switch CvtCode
3892    break;
3893  }
3894    // Conversion operators.  The source and destination have different types.
3895  case ISD::SINT_TO_FP:
3896  case ISD::UINT_TO_FP: {
3897    bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3898    Result = LegalizeINT_TO_FP(Result, isSigned,
3899                               Node->getValueType(0), Node->getOperand(0));
3900    break;
3901  }
3902  case ISD::TRUNCATE:
3903    switch (getTypeAction(Node->getOperand(0).getValueType())) {
3904    case Legal:
3905      Tmp1 = LegalizeOp(Node->getOperand(0));
3906      Result = DAG.UpdateNodeOperands(Result, Tmp1);
3907      break;
3908    case Expand:
3909      ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3910
3911      // Since the result is legal, we should just be able to truncate the low
3912      // part of the source.
3913      Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3914      break;
3915    case Promote:
3916      Result = PromoteOp(Node->getOperand(0));
3917      Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3918      break;
3919    }
3920    break;
3921
3922  case ISD::FP_TO_SINT:
3923  case ISD::FP_TO_UINT:
3924    switch (getTypeAction(Node->getOperand(0).getValueType())) {
3925    case Legal:
3926      Tmp1 = LegalizeOp(Node->getOperand(0));
3927
3928      switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3929      default: assert(0 && "Unknown operation action!");
3930      case TargetLowering::Custom:
3931        isCustom = true;
3932        // FALLTHROUGH
3933      case TargetLowering::Legal:
3934        Result = DAG.UpdateNodeOperands(Result, Tmp1);
3935        if (isCustom) {
3936          Tmp1 = TLI.LowerOperation(Result, DAG);
3937          if (Tmp1.getNode()) Result = Tmp1;
3938        }
3939        break;
3940      case TargetLowering::Promote:
3941        Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3942                                       Node->getOpcode() == ISD::FP_TO_SINT);
3943        break;
3944      case TargetLowering::Expand:
3945        if (Node->getOpcode() == ISD::FP_TO_UINT) {
3946          SDValue True, False;
3947          MVT VT =  Node->getOperand(0).getValueType();
3948          MVT NVT = Node->getValueType(0);
3949          const uint64_t zero[] = {0, 0};
3950          APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3951          APInt x = APInt::getSignBit(NVT.getSizeInBits());
3952          (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3953          Tmp2 = DAG.getConstantFP(apf, VT);
3954          Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3955                            Node->getOperand(0), Tmp2, ISD::SETLT);
3956          True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3957          False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3958                              DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3959                                          Tmp2));
3960          False = DAG.getNode(ISD::XOR, NVT, False,
3961                              DAG.getConstant(x, NVT));
3962          Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3963          break;
3964        } else {
3965          assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3966        }
3967        break;
3968      }
3969      break;
3970    case Expand: {
3971      MVT VT = Op.getValueType();
3972      MVT OVT = Node->getOperand(0).getValueType();
3973      // Convert ppcf128 to i32
3974      if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3975        if (Node->getOpcode() == ISD::FP_TO_SINT) {
3976          Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3977                               Node->getOperand(0), DAG.getValueType(MVT::f64));
3978          Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3979                               DAG.getIntPtrConstant(1));
3980          Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3981        } else {
3982          const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3983          APFloat apf = APFloat(APInt(128, 2, TwoE31));
3984          Tmp2 = DAG.getConstantFP(apf, OVT);
3985          //  X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3986          // FIXME: generated code sucks.
3987          Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3988                               DAG.getNode(ISD::ADD, MVT::i32,
3989                                 DAG.getNode(ISD::FP_TO_SINT, VT,
3990                                   DAG.getNode(ISD::FSUB, OVT,
3991                                                 Node->getOperand(0), Tmp2)),
3992                                 DAG.getConstant(0x80000000, MVT::i32)),
3993                               DAG.getNode(ISD::FP_TO_SINT, VT,
3994                                           Node->getOperand(0)),
3995                               DAG.getCondCode(ISD::SETGE));
3996        }
3997        break;
3998      }
3999      // Convert f32 / f64 to i32 / i64 / i128.
4000      RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4001        RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4002      assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4003      SDValue Dummy;
4004      Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4005      break;
4006    }
4007    case Promote:
4008      Tmp1 = PromoteOp(Node->getOperand(0));
4009      Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4010      Result = LegalizeOp(Result);
4011      break;
4012    }
4013    break;
4014
4015  case ISD::FP_EXTEND: {
4016    MVT DstVT = Op.getValueType();
4017    MVT SrcVT = Op.getOperand(0).getValueType();
4018    if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4019      // The only other way we can lower this is to turn it into a STORE,
4020      // LOAD pair, targetting a temporary location (a stack slot).
4021      Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
4022      break;
4023    }
4024    switch (getTypeAction(Node->getOperand(0).getValueType())) {
4025    case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4026    case Legal:
4027      Tmp1 = LegalizeOp(Node->getOperand(0));
4028      Result = DAG.UpdateNodeOperands(Result, Tmp1);
4029      break;
4030    case Promote:
4031      Tmp1 = PromoteOp(Node->getOperand(0));
4032      Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
4033      break;
4034    }
4035    break;
4036  }
4037  case ISD::FP_ROUND: {
4038    MVT DstVT = Op.getValueType();
4039    MVT SrcVT = Op.getOperand(0).getValueType();
4040    if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4041      if (SrcVT == MVT::ppcf128) {
4042        SDValue Lo;
4043        ExpandOp(Node->getOperand(0), Lo, Result);
4044        // Round it the rest of the way (e.g. to f32) if needed.
4045        if (DstVT!=MVT::f64)
4046          Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
4047        break;
4048      }
4049      // The only other way we can lower this is to turn it into a STORE,
4050      // LOAD pair, targetting a temporary location (a stack slot).
4051      Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
4052      break;
4053    }
4054    switch (getTypeAction(Node->getOperand(0).getValueType())) {
4055    case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4056    case Legal:
4057      Tmp1 = LegalizeOp(Node->getOperand(0));
4058      Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4059      break;
4060    case Promote:
4061      Tmp1 = PromoteOp(Node->getOperand(0));
4062      Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
4063                           Node->getOperand(1));
4064      break;
4065    }
4066    break;
4067  }
4068  case ISD::ANY_EXTEND:
4069  case ISD::ZERO_EXTEND:
4070  case ISD::SIGN_EXTEND:
4071    switch (getTypeAction(Node->getOperand(0).getValueType())) {
4072    case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4073    case Legal:
4074      Tmp1 = LegalizeOp(Node->getOperand(0));
4075      Result = DAG.UpdateNodeOperands(Result, Tmp1);
4076      if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4077          TargetLowering::Custom) {
4078        Tmp1 = TLI.LowerOperation(Result, DAG);
4079        if (Tmp1.getNode()) Result = Tmp1;
4080      }
4081      break;
4082    case Promote:
4083      switch (Node->getOpcode()) {
4084      case ISD::ANY_EXTEND:
4085        Tmp1 = PromoteOp(Node->getOperand(0));
4086        Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
4087        break;
4088      case ISD::ZERO_EXTEND:
4089        Result = PromoteOp(Node->getOperand(0));
4090        Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4091        Result = DAG.getZeroExtendInReg(Result,
4092                                        Node->getOperand(0).getValueType());
4093        break;
4094      case ISD::SIGN_EXTEND:
4095        Result = PromoteOp(Node->getOperand(0));
4096        Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4097        Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4098                             Result,
4099                          DAG.getValueType(Node->getOperand(0).getValueType()));
4100        break;
4101      }
4102    }
4103    break;
4104  case ISD::FP_ROUND_INREG:
4105  case ISD::SIGN_EXTEND_INREG: {
4106    Tmp1 = LegalizeOp(Node->getOperand(0));
4107    MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4108
4109    // If this operation is not supported, convert it to a shl/shr or load/store
4110    // pair.
4111    switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4112    default: assert(0 && "This action not supported for this op yet!");
4113    case TargetLowering::Legal:
4114      Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4115      break;
4116    case TargetLowering::Expand:
4117      // If this is an integer extend and shifts are supported, do that.
4118      if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4119        // NOTE: we could fall back on load/store here too for targets without
4120        // SAR.  However, it is doubtful that any exist.
4121        unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4122                            ExtraVT.getSizeInBits();
4123        SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4124        Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
4125                             Node->getOperand(0), ShiftCst);
4126        Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
4127                             Result, ShiftCst);
4128      } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4129        // The only way we can lower this is to turn it into a TRUNCSTORE,
4130        // EXTLOAD pair, targetting a temporary location (a stack slot).
4131
4132        // NOTE: there is a choice here between constantly creating new stack
4133        // slots and always reusing the same one.  We currently always create
4134        // new ones, as reuse may inhibit scheduling.
4135        Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4136                                  Node->getValueType(0));
4137      } else {
4138        assert(0 && "Unknown op");
4139      }
4140      break;
4141    }
4142    break;
4143  }
4144  case ISD::TRAMPOLINE: {
4145    SDValue Ops[6];
4146    for (unsigned i = 0; i != 6; ++i)
4147      Ops[i] = LegalizeOp(Node->getOperand(i));
4148    Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4149    // The only option for this node is to custom lower it.
4150    Result = TLI.LowerOperation(Result, DAG);
4151    assert(Result.getNode() && "Should always custom lower!");
4152
4153    // Since trampoline produces two values, make sure to remember that we
4154    // legalized both of them.
4155    Tmp1 = LegalizeOp(Result.getValue(1));
4156    Result = LegalizeOp(Result);
4157    AddLegalizedOperand(SDValue(Node, 0), Result);
4158    AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4159    return Op.getResNo() ? Tmp1 : Result;
4160  }
4161  case ISD::FLT_ROUNDS_: {
4162    MVT VT = Node->getValueType(0);
4163    switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4164    default: assert(0 && "This action not supported for this op yet!");
4165    case TargetLowering::Custom:
4166      Result = TLI.LowerOperation(Op, DAG);
4167      if (Result.getNode()) break;
4168      // Fall Thru
4169    case TargetLowering::Legal:
4170      // If this operation is not supported, lower it to constant 1
4171      Result = DAG.getConstant(1, VT);
4172      break;
4173    }
4174    break;
4175  }
4176  case ISD::TRAP: {
4177    MVT VT = Node->getValueType(0);
4178    switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4179    default: assert(0 && "This action not supported for this op yet!");
4180    case TargetLowering::Legal:
4181      Tmp1 = LegalizeOp(Node->getOperand(0));
4182      Result = DAG.UpdateNodeOperands(Result, Tmp1);
4183      break;
4184    case TargetLowering::Custom:
4185      Result = TLI.LowerOperation(Op, DAG);
4186      if (Result.getNode()) break;
4187      // Fall Thru
4188    case TargetLowering::Expand:
4189      // If this operation is not supported, lower it to 'abort()' call
4190      Tmp1 = LegalizeOp(Node->getOperand(0));
4191      TargetLowering::ArgListTy Args;
4192      std::pair<SDValue,SDValue> CallResult =
4193        TLI.LowerCallTo(Tmp1, Type::VoidTy,
4194                        false, false, false, false, CallingConv::C, false,
4195                        DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4196                        Args, DAG);
4197      Result = CallResult.second;
4198      break;
4199    }
4200    break;
4201  }
4202
4203  case ISD::SADDO: {
4204    MVT VT = Node->getValueType(0);
4205    switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4206    default: assert(0 && "This action not supported for this op yet!");
4207    case TargetLowering::Custom:
4208      Result = TLI.LowerOperation(Op, DAG);
4209      if (Result.getNode()) break;
4210      // FALLTHROUGH
4211    case TargetLowering::Legal: {
4212      SDValue LHS = LegalizeOp(Node->getOperand(0));
4213      SDValue RHS = LegalizeOp(Node->getOperand(1));
4214
4215      SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
4216      MVT OType = Node->getValueType(1);
4217
4218      SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4219
4220      //   LHSSign -> LHS >= 0
4221      //   RHSSign -> RHS >= 0
4222      //   SumSign -> Sum >= 0
4223      //
4224      //   Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4225      //
4226      SDValue LHSSign = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE);
4227      SDValue RHSSign = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE);
4228      SDValue SignsEq = DAG.getSetCC(OType, LHSSign, RHSSign, ISD::SETEQ);
4229
4230      SDValue SumSign = DAG.getSetCC(OType, Sum, Zero, ISD::SETGE);
4231      SDValue SumSignNE = DAG.getSetCC(OType, LHSSign, SumSign, ISD::SETNE);
4232
4233      SDValue Cmp = DAG.getNode(ISD::AND, OType, SignsEq, SumSignNE);
4234
4235      MVT ValueVTs[] = { LHS.getValueType(), OType };
4236      SDValue Ops[] = { Sum, Cmp };
4237
4238      Result = DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
4239      SDNode *RNode = Result.getNode();
4240      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4241      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4242      break;
4243    }
4244    }
4245
4246    break;
4247  }
4248  case ISD::UADDO: {
4249    MVT VT = Node->getValueType(0);
4250    switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4251    default: assert(0 && "This action not supported for this op yet!");
4252    case TargetLowering::Custom:
4253      Result = TLI.LowerOperation(Op, DAG);
4254      if (Result.getNode()) break;
4255      // FALLTHROUGH
4256    case TargetLowering::Legal: {
4257      SDValue LHS = LegalizeOp(Node->getOperand(0));
4258      SDValue RHS = LegalizeOp(Node->getOperand(1));
4259
4260      SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
4261      MVT OType = Node->getValueType(1);
4262      SDValue Cmp = DAG.getSetCC(OType, Sum, LHS, ISD::SETULT);
4263
4264      MVT ValueVTs[] = { LHS.getValueType(), OType };
4265      SDValue Ops[] = { Sum, Cmp };
4266
4267      Result = DAG.getMergeValues(DAG.getVTList(&ValueVTs[0], 2), &Ops[0], 2);
4268      SDNode *RNode = Result.getNode();
4269      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4270      DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4271      break;
4272    }
4273    }
4274
4275    break;
4276  }
4277  }
4278
4279  assert(Result.getValueType() == Op.getValueType() &&
4280         "Bad legalization!");
4281
4282  // Make sure that the generated code is itself legal.
4283  if (Result != Op)
4284    Result = LegalizeOp(Result);
4285
4286  // Note that LegalizeOp may be reentered even from single-use nodes, which
4287  // means that we always must cache transformed nodes.
4288  AddLegalizedOperand(Op, Result);
4289  return Result;
4290}
4291
4292/// PromoteOp - Given an operation that produces a value in an invalid type,
4293/// promote it to compute the value into a larger type.  The produced value will
4294/// have the correct bits for the low portion of the register, but no guarantee
4295/// is made about the top bits: it may be zero, sign-extended, or garbage.
4296SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4297  MVT VT = Op.getValueType();
4298  MVT NVT = TLI.getTypeToTransformTo(VT);
4299  assert(getTypeAction(VT) == Promote &&
4300         "Caller should expand or legalize operands that are not promotable!");
4301  assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4302         "Cannot promote to smaller type!");
4303
4304  SDValue Tmp1, Tmp2, Tmp3;
4305  SDValue Result;
4306  SDNode *Node = Op.getNode();
4307
4308  DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4309  if (I != PromotedNodes.end()) return I->second;
4310
4311  switch (Node->getOpcode()) {
4312  case ISD::CopyFromReg:
4313    assert(0 && "CopyFromReg must be legal!");
4314  default:
4315#ifndef NDEBUG
4316    cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4317#endif
4318    assert(0 && "Do not know how to promote this operator!");
4319    abort();
4320  case ISD::UNDEF:
4321    Result = DAG.getNode(ISD::UNDEF, NVT);
4322    break;
4323  case ISD::Constant:
4324    if (VT != MVT::i1)
4325      Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4326    else
4327      Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4328    assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4329    break;
4330  case ISD::ConstantFP:
4331    Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4332    assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4333    break;
4334
4335  case ISD::SETCC:
4336    assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4337           && "SetCC type is not legal??");
4338    Result = DAG.getNode(ISD::SETCC,
4339                         TLI.getSetCCResultType(Node->getOperand(0)),
4340                         Node->getOperand(0), Node->getOperand(1),
4341                         Node->getOperand(2));
4342    break;
4343
4344  case ISD::TRUNCATE:
4345    switch (getTypeAction(Node->getOperand(0).getValueType())) {
4346    case Legal:
4347      Result = LegalizeOp(Node->getOperand(0));
4348      assert(Result.getValueType().bitsGE(NVT) &&
4349             "This truncation doesn't make sense!");
4350      if (Result.getValueType().bitsGT(NVT))    // Truncate to NVT instead of VT
4351        Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4352      break;
4353    case Promote:
4354      // The truncation is not required, because we don't guarantee anything
4355      // about high bits anyway.
4356      Result = PromoteOp(Node->getOperand(0));
4357      break;
4358    case Expand:
4359      ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4360      // Truncate the low part of the expanded value to the result type
4361      Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4362    }
4363    break;
4364  case ISD::SIGN_EXTEND:
4365  case ISD::ZERO_EXTEND:
4366  case ISD::ANY_EXTEND:
4367    switch (getTypeAction(Node->getOperand(0).getValueType())) {
4368    case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4369    case Legal:
4370      // Input is legal?  Just do extend all the way to the larger type.
4371      Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4372      break;
4373    case Promote:
4374      // Promote the reg if it's smaller.
4375      Result = PromoteOp(Node->getOperand(0));
4376      // The high bits are not guaranteed to be anything.  Insert an extend.
4377      if (Node->getOpcode() == ISD::SIGN_EXTEND)
4378        Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4379                         DAG.getValueType(Node->getOperand(0).getValueType()));
4380      else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4381        Result = DAG.getZeroExtendInReg(Result,
4382                                        Node->getOperand(0).getValueType());
4383      break;
4384    }
4385    break;
4386  case ISD::CONVERT_RNDSAT: {
4387    ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4388    assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4389             CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4390             CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4391            "can only promote integers");
4392    Result = DAG.getConvertRndSat(NVT, Node->getOperand(0),
4393                                  Node->getOperand(1), Node->getOperand(2),
4394                                  Node->getOperand(3), Node->getOperand(4),
4395                                  CvtCode);
4396    break;
4397
4398  }
4399  case ISD::BIT_CONVERT:
4400    Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4401                              Node->getValueType(0));
4402    Result = PromoteOp(Result);
4403    break;
4404
4405  case ISD::FP_EXTEND:
4406    assert(0 && "Case not implemented.  Dynamically dead with 2 FP types!");
4407  case ISD::FP_ROUND:
4408    switch (getTypeAction(Node->getOperand(0).getValueType())) {
4409    case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4410    case Promote:  assert(0 && "Unreachable with 2 FP types!");
4411    case Legal:
4412      if (Node->getConstantOperandVal(1) == 0) {
4413        // Input is legal?  Do an FP_ROUND_INREG.
4414        Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4415                             DAG.getValueType(VT));
4416      } else {
4417        // Just remove the truncate, it isn't affecting the value.
4418        Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4419                             Node->getOperand(1));
4420      }
4421      break;
4422    }
4423    break;
4424  case ISD::SINT_TO_FP:
4425  case ISD::UINT_TO_FP:
4426    switch (getTypeAction(Node->getOperand(0).getValueType())) {
4427    case Legal:
4428      // No extra round required here.
4429      Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4430      break;
4431
4432    case Promote:
4433      Result = PromoteOp(Node->getOperand(0));
4434      if (Node->getOpcode() == ISD::SINT_TO_FP)
4435        Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4436                             Result,
4437                         DAG.getValueType(Node->getOperand(0).getValueType()));
4438      else
4439        Result = DAG.getZeroExtendInReg(Result,
4440                                        Node->getOperand(0).getValueType());
4441      // No extra round required here.
4442      Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4443      break;
4444    case Expand:
4445      Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4446                             Node->getOperand(0));
4447      // Round if we cannot tolerate excess precision.
4448      if (NoExcessFPPrecision)
4449        Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4450                             DAG.getValueType(VT));
4451      break;
4452    }
4453    break;
4454
4455  case ISD::SIGN_EXTEND_INREG:
4456    Result = PromoteOp(Node->getOperand(0));
4457    Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4458                         Node->getOperand(1));
4459    break;
4460  case ISD::FP_TO_SINT:
4461  case ISD::FP_TO_UINT:
4462    switch (getTypeAction(Node->getOperand(0).getValueType())) {
4463    case Legal:
4464    case Expand:
4465      Tmp1 = Node->getOperand(0);
4466      break;
4467    case Promote:
4468      // The input result is prerounded, so we don't have to do anything
4469      // special.
4470      Tmp1 = PromoteOp(Node->getOperand(0));
4471      break;
4472    }
4473    // If we're promoting a UINT to a larger size, check to see if the new node
4474    // will be legal.  If it isn't, check to see if FP_TO_SINT is legal, since
4475    // we can use that instead.  This allows us to generate better code for
4476    // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4477    // legal, such as PowerPC.
4478    if (Node->getOpcode() == ISD::FP_TO_UINT &&
4479        !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4480        (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4481         TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4482      Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4483    } else {
4484      Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4485    }
4486    break;
4487
4488  case ISD::FABS:
4489  case ISD::FNEG:
4490    Tmp1 = PromoteOp(Node->getOperand(0));
4491    assert(Tmp1.getValueType() == NVT);
4492    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4493    // NOTE: we do not have to do any extra rounding here for
4494    // NoExcessFPPrecision, because we know the input will have the appropriate
4495    // precision, and these operations don't modify precision at all.
4496    break;
4497
4498  case ISD::FLOG:
4499  case ISD::FLOG2:
4500  case ISD::FLOG10:
4501  case ISD::FEXP:
4502  case ISD::FEXP2:
4503  case ISD::FSQRT:
4504  case ISD::FSIN:
4505  case ISD::FCOS:
4506  case ISD::FTRUNC:
4507  case ISD::FFLOOR:
4508  case ISD::FCEIL:
4509  case ISD::FRINT:
4510  case ISD::FNEARBYINT:
4511    Tmp1 = PromoteOp(Node->getOperand(0));
4512    assert(Tmp1.getValueType() == NVT);
4513    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4514    if (NoExcessFPPrecision)
4515      Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4516                           DAG.getValueType(VT));
4517    break;
4518
4519  case ISD::FPOW:
4520  case ISD::FPOWI: {
4521    // Promote f32 pow(i) to f64 pow(i).  Note that this could insert a libcall
4522    // directly as well, which may be better.
4523    Tmp1 = PromoteOp(Node->getOperand(0));
4524    Tmp2 = Node->getOperand(1);
4525    if (Node->getOpcode() == ISD::FPOW)
4526      Tmp2 = PromoteOp(Tmp2);
4527    assert(Tmp1.getValueType() == NVT);
4528    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4529    if (NoExcessFPPrecision)
4530      Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4531                           DAG.getValueType(VT));
4532    break;
4533  }
4534
4535  case ISD::ATOMIC_CMP_SWAP_8:
4536  case ISD::ATOMIC_CMP_SWAP_16:
4537  case ISD::ATOMIC_CMP_SWAP_32:
4538  case ISD::ATOMIC_CMP_SWAP_64: {
4539    AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4540    Tmp2 = PromoteOp(Node->getOperand(2));
4541    Tmp3 = PromoteOp(Node->getOperand(3));
4542    Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4543                           AtomNode->getBasePtr(), Tmp2, Tmp3,
4544                           AtomNode->getSrcValue(),
4545                           AtomNode->getAlignment());
4546    // Remember that we legalized the chain.
4547    AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4548    break;
4549  }
4550  case ISD::ATOMIC_LOAD_ADD_8:
4551  case ISD::ATOMIC_LOAD_SUB_8:
4552  case ISD::ATOMIC_LOAD_AND_8:
4553  case ISD::ATOMIC_LOAD_OR_8:
4554  case ISD::ATOMIC_LOAD_XOR_8:
4555  case ISD::ATOMIC_LOAD_NAND_8:
4556  case ISD::ATOMIC_LOAD_MIN_8:
4557  case ISD::ATOMIC_LOAD_MAX_8:
4558  case ISD::ATOMIC_LOAD_UMIN_8:
4559  case ISD::ATOMIC_LOAD_UMAX_8:
4560  case ISD::ATOMIC_SWAP_8:
4561  case ISD::ATOMIC_LOAD_ADD_16:
4562  case ISD::ATOMIC_LOAD_SUB_16:
4563  case ISD::ATOMIC_LOAD_AND_16:
4564  case ISD::ATOMIC_LOAD_OR_16:
4565  case ISD::ATOMIC_LOAD_XOR_16:
4566  case ISD::ATOMIC_LOAD_NAND_16:
4567  case ISD::ATOMIC_LOAD_MIN_16:
4568  case ISD::ATOMIC_LOAD_MAX_16:
4569  case ISD::ATOMIC_LOAD_UMIN_16:
4570  case ISD::ATOMIC_LOAD_UMAX_16:
4571  case ISD::ATOMIC_SWAP_16:
4572  case ISD::ATOMIC_LOAD_ADD_32:
4573  case ISD::ATOMIC_LOAD_SUB_32:
4574  case ISD::ATOMIC_LOAD_AND_32:
4575  case ISD::ATOMIC_LOAD_OR_32:
4576  case ISD::ATOMIC_LOAD_XOR_32:
4577  case ISD::ATOMIC_LOAD_NAND_32:
4578  case ISD::ATOMIC_LOAD_MIN_32:
4579  case ISD::ATOMIC_LOAD_MAX_32:
4580  case ISD::ATOMIC_LOAD_UMIN_32:
4581  case ISD::ATOMIC_LOAD_UMAX_32:
4582  case ISD::ATOMIC_SWAP_32:
4583  case ISD::ATOMIC_LOAD_ADD_64:
4584  case ISD::ATOMIC_LOAD_SUB_64:
4585  case ISD::ATOMIC_LOAD_AND_64:
4586  case ISD::ATOMIC_LOAD_OR_64:
4587  case ISD::ATOMIC_LOAD_XOR_64:
4588  case ISD::ATOMIC_LOAD_NAND_64:
4589  case ISD::ATOMIC_LOAD_MIN_64:
4590  case ISD::ATOMIC_LOAD_MAX_64:
4591  case ISD::ATOMIC_LOAD_UMIN_64:
4592  case ISD::ATOMIC_LOAD_UMAX_64:
4593  case ISD::ATOMIC_SWAP_64: {
4594    AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4595    Tmp2 = PromoteOp(Node->getOperand(2));
4596    Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4597                           AtomNode->getBasePtr(), Tmp2,
4598                           AtomNode->getSrcValue(),
4599                           AtomNode->getAlignment());
4600    // Remember that we legalized the chain.
4601    AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4602    break;
4603  }
4604
4605  case ISD::AND:
4606  case ISD::OR:
4607  case ISD::XOR:
4608  case ISD::ADD:
4609  case ISD::SUB:
4610  case ISD::MUL:
4611    // The input may have strange things in the top bits of the registers, but
4612    // these operations don't care.  They may have weird bits going out, but
4613    // that too is okay if they are integer operations.
4614    Tmp1 = PromoteOp(Node->getOperand(0));
4615    Tmp2 = PromoteOp(Node->getOperand(1));
4616    assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4617    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4618    break;
4619  case ISD::FADD:
4620  case ISD::FSUB:
4621  case ISD::FMUL:
4622    Tmp1 = PromoteOp(Node->getOperand(0));
4623    Tmp2 = PromoteOp(Node->getOperand(1));
4624    assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4625    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4626
4627    // Floating point operations will give excess precision that we may not be
4628    // able to tolerate.  If we DO allow excess precision, just leave it,
4629    // otherwise excise it.
4630    // FIXME: Why would we need to round FP ops more than integer ones?
4631    //     Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4632    if (NoExcessFPPrecision)
4633      Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4634                           DAG.getValueType(VT));
4635    break;
4636
4637  case ISD::SDIV:
4638  case ISD::SREM:
4639    // These operators require that their input be sign extended.
4640    Tmp1 = PromoteOp(Node->getOperand(0));
4641    Tmp2 = PromoteOp(Node->getOperand(1));
4642    if (NVT.isInteger()) {
4643      Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4644                         DAG.getValueType(VT));
4645      Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4646                         DAG.getValueType(VT));
4647    }
4648    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4649
4650    // Perform FP_ROUND: this is probably overly pessimistic.
4651    if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4652      Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4653                           DAG.getValueType(VT));
4654    break;
4655  case ISD::FDIV:
4656  case ISD::FREM:
4657  case ISD::FCOPYSIGN:
4658    // These operators require that their input be fp extended.
4659    switch (getTypeAction(Node->getOperand(0).getValueType())) {
4660    case Expand: assert(0 && "not implemented");
4661    case Legal:   Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4662    case Promote: Tmp1 = PromoteOp(Node->getOperand(0));  break;
4663    }
4664    switch (getTypeAction(Node->getOperand(1).getValueType())) {
4665    case Expand: assert(0 && "not implemented");
4666    case Legal:   Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4667    case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4668    }
4669    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4670
4671    // Perform FP_ROUND: this is probably overly pessimistic.
4672    if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4673      Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4674                           DAG.getValueType(VT));
4675    break;
4676
4677  case ISD::UDIV:
4678  case ISD::UREM:
4679    // These operators require that their input be zero extended.
4680    Tmp1 = PromoteOp(Node->getOperand(0));
4681    Tmp2 = PromoteOp(Node->getOperand(1));
4682    assert(NVT.isInteger() && "Operators don't apply to FP!");
4683    Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4684    Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4685    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4686    break;
4687
4688  case ISD::SHL:
4689    Tmp1 = PromoteOp(Node->getOperand(0));
4690    Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4691    break;
4692  case ISD::SRA:
4693    // The input value must be properly sign extended.
4694    Tmp1 = PromoteOp(Node->getOperand(0));
4695    Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4696                       DAG.getValueType(VT));
4697    Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4698    break;
4699  case ISD::SRL:
4700    // The input value must be properly zero extended.
4701    Tmp1 = PromoteOp(Node->getOperand(0));
4702    Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4703    Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4704    break;
4705
4706  case ISD::VAARG:
4707    Tmp1 = Node->getOperand(0);   // Get the chain.
4708    Tmp2 = Node->getOperand(1);   // Get the pointer.
4709    if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4710      Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4711      Result = TLI.LowerOperation(Tmp3, DAG);
4712    } else {
4713      const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4714      SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4715      // Increment the pointer, VAList, to the next vaarg
4716      Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4717                         DAG.getConstant(VT.getSizeInBits()/8,
4718                                         TLI.getPointerTy()));
4719      // Store the incremented VAList to the legalized pointer
4720      Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4721      // Load the actual argument out of the pointer VAList
4722      Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4723    }
4724    // Remember that we legalized the chain.
4725    AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4726    break;
4727
4728  case ISD::LOAD: {
4729    LoadSDNode *LD = cast<LoadSDNode>(Node);
4730    ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4731      ? ISD::EXTLOAD : LD->getExtensionType();
4732    Result = DAG.getExtLoad(ExtType, NVT,
4733                            LD->getChain(), LD->getBasePtr(),
4734                            LD->getSrcValue(), LD->getSrcValueOffset(),
4735                            LD->getMemoryVT(),
4736                            LD->isVolatile(),
4737                            LD->getAlignment());
4738    // Remember that we legalized the chain.
4739    AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4740    break;
4741  }
4742  case ISD::SELECT: {
4743    Tmp2 = PromoteOp(Node->getOperand(1));   // Legalize the op0
4744    Tmp3 = PromoteOp(Node->getOperand(2));   // Legalize the op1
4745
4746    MVT VT2 = Tmp2.getValueType();
4747    assert(VT2 == Tmp3.getValueType()
4748           && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4749    // Ensure that the resulting node is at least the same size as the operands'
4750    // value types, because we cannot assume that TLI.getSetCCValueType() is
4751    // constant.
4752    Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4753    break;
4754  }
4755  case ISD::SELECT_CC:
4756    Tmp2 = PromoteOp(Node->getOperand(2));   // True
4757    Tmp3 = PromoteOp(Node->getOperand(3));   // False
4758    Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4759                         Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4760    break;
4761  case ISD::BSWAP:
4762    Tmp1 = Node->getOperand(0);
4763    Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4764    Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4765    Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4766                         DAG.getConstant(NVT.getSizeInBits() -
4767                                         VT.getSizeInBits(),
4768                                         TLI.getShiftAmountTy()));
4769    break;
4770  case ISD::CTPOP:
4771  case ISD::CTTZ:
4772  case ISD::CTLZ:
4773    // Zero extend the argument
4774    Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4775    // Perform the larger operation, then subtract if needed.
4776    Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4777    switch(Node->getOpcode()) {
4778    case ISD::CTPOP:
4779      Result = Tmp1;
4780      break;
4781    case ISD::CTTZ:
4782      // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4783      Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4784                          DAG.getConstant(NVT.getSizeInBits(), NVT),
4785                          ISD::SETEQ);
4786      Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4787                           DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4788      break;
4789    case ISD::CTLZ:
4790      //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4791      Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4792                           DAG.getConstant(NVT.getSizeInBits() -
4793                                           VT.getSizeInBits(), NVT));
4794      break;
4795    }
4796    break;
4797  case ISD::EXTRACT_SUBVECTOR:
4798    Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4799    break;
4800  case ISD::EXTRACT_VECTOR_ELT:
4801    Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4802    break;
4803  }
4804
4805  assert(Result.getNode() && "Didn't set a result!");
4806
4807  // Make sure the result is itself legal.
4808  Result = LegalizeOp(Result);
4809
4810  // Remember that we promoted this!
4811  AddPromotedOperand(Op, Result);
4812  return Result;
4813}
4814
4815/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4816/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4817/// based on the vector type. The return type of this matches the element type
4818/// of the vector, which may not be legal for the target.
4819SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4820  // We know that operand #0 is the Vec vector.  If the index is a constant
4821  // or if the invec is a supported hardware type, we can use it.  Otherwise,
4822  // lower to a store then an indexed load.
4823  SDValue Vec = Op.getOperand(0);
4824  SDValue Idx = Op.getOperand(1);
4825
4826  MVT TVT = Vec.getValueType();
4827  unsigned NumElems = TVT.getVectorNumElements();
4828
4829  switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4830  default: assert(0 && "This action is not supported yet!");
4831  case TargetLowering::Custom: {
4832    Vec = LegalizeOp(Vec);
4833    Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4834    SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4835    if (Tmp3.getNode())
4836      return Tmp3;
4837    break;
4838  }
4839  case TargetLowering::Legal:
4840    if (isTypeLegal(TVT)) {
4841      Vec = LegalizeOp(Vec);
4842      Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4843      return Op;
4844    }
4845    break;
4846  case TargetLowering::Promote:
4847    assert(TVT.isVector() && "not vector type");
4848    // fall thru to expand since vectors are by default are promote
4849  case TargetLowering::Expand:
4850    break;
4851  }
4852
4853  if (NumElems == 1) {
4854    // This must be an access of the only element.  Return it.
4855    Op = ScalarizeVectorOp(Vec);
4856  } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4857    unsigned NumLoElts =  1 << Log2_32(NumElems-1);
4858    ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4859    SDValue Lo, Hi;
4860    SplitVectorOp(Vec, Lo, Hi);
4861    if (CIdx->getZExtValue() < NumLoElts) {
4862      Vec = Lo;
4863    } else {
4864      Vec = Hi;
4865      Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
4866                            Idx.getValueType());
4867    }
4868
4869    // It's now an extract from the appropriate high or low part.  Recurse.
4870    Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4871    Op = ExpandEXTRACT_VECTOR_ELT(Op);
4872  } else {
4873    // Store the value to a temporary stack slot, then LOAD the scalar
4874    // element back out.
4875    SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4876    SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4877
4878    // Add the offset to the index.
4879    unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4880    Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4881                      DAG.getConstant(EltSize, Idx.getValueType()));
4882
4883    if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4884      Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4885    else
4886      Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4887
4888    StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4889
4890    Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4891  }
4892  return Op;
4893}
4894
4895/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation.  For now
4896/// we assume the operation can be split if it is not already legal.
4897SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
4898  // We know that operand #0 is the Vec vector.  For now we assume the index
4899  // is a constant and that the extracted result is a supported hardware type.
4900  SDValue Vec = Op.getOperand(0);
4901  SDValue Idx = LegalizeOp(Op.getOperand(1));
4902
4903  unsigned NumElems = Vec.getValueType().getVectorNumElements();
4904
4905  if (NumElems == Op.getValueType().getVectorNumElements()) {
4906    // This must be an access of the desired vector length.  Return it.
4907    return Vec;
4908  }
4909
4910  ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4911  SDValue Lo, Hi;
4912  SplitVectorOp(Vec, Lo, Hi);
4913  if (CIdx->getZExtValue() < NumElems/2) {
4914    Vec = Lo;
4915  } else {
4916    Vec = Hi;
4917    Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
4918                          Idx.getValueType());
4919  }
4920
4921  // It's now an extract from the appropriate high or low part.  Recurse.
4922  Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4923  return ExpandEXTRACT_SUBVECTOR(Op);
4924}
4925
4926/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4927/// with condition CC on the current target.  This usually involves legalizing
4928/// or promoting the arguments.  In the case where LHS and RHS must be expanded,
4929/// there may be no choice but to create a new SetCC node to represent the
4930/// legalized value of setcc lhs, rhs.  In this case, the value is returned in
4931/// LHS, and the SDValue returned in RHS has a nil SDNode value.
4932void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
4933                                                 SDValue &RHS,
4934                                                 SDValue &CC) {
4935  SDValue Tmp1, Tmp2, Tmp3, Result;
4936
4937  switch (getTypeAction(LHS.getValueType())) {
4938  case Legal:
4939    Tmp1 = LegalizeOp(LHS);   // LHS
4940    Tmp2 = LegalizeOp(RHS);   // RHS
4941    break;
4942  case Promote:
4943    Tmp1 = PromoteOp(LHS);   // LHS
4944    Tmp2 = PromoteOp(RHS);   // RHS
4945
4946    // If this is an FP compare, the operands have already been extended.
4947    if (LHS.getValueType().isInteger()) {
4948      MVT VT = LHS.getValueType();
4949      MVT NVT = TLI.getTypeToTransformTo(VT);
4950
4951      // Otherwise, we have to insert explicit sign or zero extends.  Note
4952      // that we could insert sign extends for ALL conditions, but zero extend
4953      // is cheaper on many machines (an AND instead of two shifts), so prefer
4954      // it.
4955      switch (cast<CondCodeSDNode>(CC)->get()) {
4956      default: assert(0 && "Unknown integer comparison!");
4957      case ISD::SETEQ:
4958      case ISD::SETNE:
4959      case ISD::SETUGE:
4960      case ISD::SETUGT:
4961      case ISD::SETULE:
4962      case ISD::SETULT:
4963        // ALL of these operations will work if we either sign or zero extend
4964        // the operands (including the unsigned comparisons!).  Zero extend is
4965        // usually a simpler/cheaper operation, so prefer it.
4966        Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4967        Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4968        break;
4969      case ISD::SETGE:
4970      case ISD::SETGT:
4971      case ISD::SETLT:
4972      case ISD::SETLE:
4973        Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4974                           DAG.getValueType(VT));
4975        Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4976                           DAG.getValueType(VT));
4977        Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
4978        Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
4979        break;
4980      }
4981    }
4982    break;
4983  case Expand: {
4984    MVT VT = LHS.getValueType();
4985    if (VT == MVT::f32 || VT == MVT::f64) {
4986      // Expand into one or more soft-fp libcall(s).
4987      RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
4988      switch (cast<CondCodeSDNode>(CC)->get()) {
4989      case ISD::SETEQ:
4990      case ISD::SETOEQ:
4991        LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4992        break;
4993      case ISD::SETNE:
4994      case ISD::SETUNE:
4995        LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4996        break;
4997      case ISD::SETGE:
4998      case ISD::SETOGE:
4999        LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5000        break;
5001      case ISD::SETLT:
5002      case ISD::SETOLT:
5003        LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5004        break;
5005      case ISD::SETLE:
5006      case ISD::SETOLE:
5007        LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5008        break;
5009      case ISD::SETGT:
5010      case ISD::SETOGT:
5011        LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5012        break;
5013      case ISD::SETUO:
5014        LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5015        break;
5016      case ISD::SETO:
5017        LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5018        break;
5019      default:
5020        LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5021        switch (cast<CondCodeSDNode>(CC)->get()) {
5022        case ISD::SETONE:
5023          // SETONE = SETOLT | SETOGT
5024          LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5025          // Fallthrough
5026        case ISD::SETUGT:
5027          LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5028          break;
5029        case ISD::SETUGE:
5030          LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5031          break;
5032        case ISD::SETULT:
5033          LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5034          break;
5035        case ISD::SETULE:
5036          LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5037          break;
5038        case ISD::SETUEQ:
5039          LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5040          break;
5041        default: assert(0 && "Unsupported FP setcc!");
5042        }
5043      }
5044
5045      SDValue Dummy;
5046      SDValue Ops[2] = { LHS, RHS };
5047      Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
5048                           false /*sign irrelevant*/, Dummy);
5049      Tmp2 = DAG.getConstant(0, MVT::i32);
5050      CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5051      if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5052        Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
5053                           CC);
5054        LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
5055                            false /*sign irrelevant*/, Dummy);
5056        Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
5057                           DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5058        Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
5059        Tmp2 = SDValue();
5060      }
5061      LHS = LegalizeOp(Tmp1);
5062      RHS = Tmp2;
5063      return;
5064    }
5065
5066    SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5067    ExpandOp(LHS, LHSLo, LHSHi);
5068    ExpandOp(RHS, RHSLo, RHSHi);
5069    ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5070
5071    if (VT==MVT::ppcf128) {
5072      // FIXME:  This generated code sucks.  We want to generate
5073      //         FCMPU crN, hi1, hi2
5074      //         BNE crN, L:
5075      //         FCMPU crN, lo1, lo2
5076      // The following can be improved, but not that much.
5077      Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5078                                                         ISD::SETOEQ);
5079      Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
5080      Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
5081      Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5082                                                         ISD::SETUNE);
5083      Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
5084      Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
5085      Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
5086      Tmp2 = SDValue();
5087      break;
5088    }
5089
5090    switch (CCCode) {
5091    case ISD::SETEQ:
5092    case ISD::SETNE:
5093      if (RHSLo == RHSHi)
5094        if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5095          if (RHSCST->isAllOnesValue()) {
5096            // Comparison to -1.
5097            Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
5098            Tmp2 = RHSLo;
5099            break;
5100          }
5101
5102      Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
5103      Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
5104      Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
5105      Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5106      break;
5107    default:
5108      // If this is a comparison of the sign bit, just look at the top part.
5109      // X > -1,  x < 0
5110      if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5111        if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5112             CST->isNullValue()) ||               // X < 0
5113            (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5114             CST->isAllOnesValue())) {            // X > -1
5115          Tmp1 = LHSHi;
5116          Tmp2 = RHSHi;
5117          break;
5118        }
5119
5120      // FIXME: This generated code sucks.
5121      ISD::CondCode LowCC;
5122      switch (CCCode) {
5123      default: assert(0 && "Unknown integer setcc!");
5124      case ISD::SETLT:
5125      case ISD::SETULT: LowCC = ISD::SETULT; break;
5126      case ISD::SETGT:
5127      case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5128      case ISD::SETLE:
5129      case ISD::SETULE: LowCC = ISD::SETULE; break;
5130      case ISD::SETGE:
5131      case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5132      }
5133
5134      // Tmp1 = lo(op1) < lo(op2)   // Always unsigned comparison
5135      // Tmp2 = hi(op1) < hi(op2)   // Signedness depends on operands
5136      // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5137
5138      // NOTE: on targets without efficient SELECT of bools, we can always use
5139      // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5140      TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5141      Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
5142                               LowCC, false, DagCombineInfo);
5143      if (!Tmp1.getNode())
5144        Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
5145      Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5146                               CCCode, false, DagCombineInfo);
5147      if (!Tmp2.getNode())
5148        Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
5149                           RHSHi,CC);
5150
5151      ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5152      ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5153      if ((Tmp1C && Tmp1C->isNullValue()) ||
5154          (Tmp2C && Tmp2C->isNullValue() &&
5155           (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5156            CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5157          (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5158           (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5159            CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5160        // low part is known false, returns high part.
5161        // For LE / GE, if high part is known false, ignore the low part.
5162        // For LT / GT, if high part is known true, ignore the low part.
5163        Tmp1 = Tmp2;
5164        Tmp2 = SDValue();
5165      } else {
5166        Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5167                                   ISD::SETEQ, false, DagCombineInfo);
5168        if (!Result.getNode())
5169          Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5170                              ISD::SETEQ);
5171        Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
5172                                        Result, Tmp1, Tmp2));
5173        Tmp1 = Result;
5174        Tmp2 = SDValue();
5175      }
5176    }
5177  }
5178  }
5179  LHS = Tmp1;
5180  RHS = Tmp2;
5181}
5182
5183/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5184/// condition code CC on the current target. This routine assumes LHS and rHS
5185/// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5186/// illegal condition code into AND / OR of multiple SETCC values.
5187void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5188                                                 SDValue &LHS, SDValue &RHS,
5189                                                 SDValue &CC) {
5190  MVT OpVT = LHS.getValueType();
5191  ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5192  switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5193  default: assert(0 && "Unknown condition code action!");
5194  case TargetLowering::Legal:
5195    // Nothing to do.
5196    break;
5197  case TargetLowering::Expand: {
5198    ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5199    unsigned Opc = 0;
5200    switch (CCCode) {
5201    default: assert(0 && "Don't know how to expand this condition!"); abort();
5202    case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO;  Opc = ISD::AND; break;
5203    case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO;  Opc = ISD::AND; break;
5204    case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO;  Opc = ISD::AND; break;
5205    case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO;  Opc = ISD::AND; break;
5206    case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO;  Opc = ISD::AND; break;
5207    case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO;  Opc = ISD::AND; break;
5208    case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR;  break;
5209    case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR;  break;
5210    case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR;  break;
5211    case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR;  break;
5212    case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR;  break;
5213    case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR;  break;
5214    // FIXME: Implement more expansions.
5215    }
5216
5217    SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1);
5218    SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2);
5219    LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2);
5220    RHS = SDValue();
5221    CC  = SDValue();
5222    break;
5223  }
5224  }
5225}
5226
5227/// EmitStackConvert - Emit a store/load combination to the stack.  This stores
5228/// SrcOp to a stack slot of type SlotVT, truncating it if needed.  It then does
5229/// a load from the stack slot to DestVT, extending it if needed.
5230/// The resultant code need not be legal.
5231SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5232                                               MVT SlotVT,
5233                                               MVT DestVT) {
5234  // Create the stack frame object.
5235  unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5236                                          SrcOp.getValueType().getTypeForMVT());
5237  SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5238
5239  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5240  int SPFI = StackPtrFI->getIndex();
5241
5242  unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5243  unsigned SlotSize = SlotVT.getSizeInBits();
5244  unsigned DestSize = DestVT.getSizeInBits();
5245  unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5246                                                        DestVT.getTypeForMVT());
5247
5248  // Emit a store to the stack slot.  Use a truncstore if the input value is
5249  // later than DestVT.
5250  SDValue Store;
5251
5252  if (SrcSize > SlotSize)
5253    Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
5254                              PseudoSourceValue::getFixedStack(SPFI), 0,
5255                              SlotVT, false, SrcAlign);
5256  else {
5257    assert(SrcSize == SlotSize && "Invalid store");
5258    Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
5259                         PseudoSourceValue::getFixedStack(SPFI), 0,
5260                         false, SrcAlign);
5261  }
5262
5263  // Result is a load from the stack slot.
5264  if (SlotSize == DestSize)
5265    return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
5266
5267  assert(SlotSize < DestSize && "Unknown extension!");
5268  return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
5269                        false, DestAlign);
5270}
5271
5272SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5273  // Create a vector sized/aligned stack slot, store the value to element #0,
5274  // then load the whole vector back out.
5275  SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5276
5277  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5278  int SPFI = StackPtrFI->getIndex();
5279
5280  SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
5281                              PseudoSourceValue::getFixedStack(SPFI), 0);
5282  return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
5283                     PseudoSourceValue::getFixedStack(SPFI), 0);
5284}
5285
5286
5287/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5288/// support the operation, but do support the resultant vector type.
5289SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5290
5291  // If the only non-undef value is the low element, turn this into a
5292  // SCALAR_TO_VECTOR node.  If this is { X, X, X, X }, determine X.
5293  unsigned NumElems = Node->getNumOperands();
5294  bool isOnlyLowElement = true;
5295  SDValue SplatValue = Node->getOperand(0);
5296
5297  // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5298  // and use a bitmask instead of a list of elements.
5299  std::map<SDValue, std::vector<unsigned> > Values;
5300  Values[SplatValue].push_back(0);
5301  bool isConstant = true;
5302  if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5303      SplatValue.getOpcode() != ISD::UNDEF)
5304    isConstant = false;
5305
5306  for (unsigned i = 1; i < NumElems; ++i) {
5307    SDValue V = Node->getOperand(i);
5308    Values[V].push_back(i);
5309    if (V.getOpcode() != ISD::UNDEF)
5310      isOnlyLowElement = false;
5311    if (SplatValue != V)
5312      SplatValue = SDValue(0,0);
5313
5314    // If this isn't a constant element or an undef, we can't use a constant
5315    // pool load.
5316    if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5317        V.getOpcode() != ISD::UNDEF)
5318      isConstant = false;
5319  }
5320
5321  if (isOnlyLowElement) {
5322    // If the low element is an undef too, then this whole things is an undef.
5323    if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5324      return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
5325    // Otherwise, turn this into a scalar_to_vector node.
5326    return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
5327                       Node->getOperand(0));
5328  }
5329
5330  // If all elements are constants, create a load from the constant pool.
5331  if (isConstant) {
5332    MVT VT = Node->getValueType(0);
5333    std::vector<Constant*> CV;
5334    for (unsigned i = 0, e = NumElems; i != e; ++i) {
5335      if (ConstantFPSDNode *V =
5336          dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5337        CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5338      } else if (ConstantSDNode *V =
5339                   dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5340        CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5341      } else {
5342        assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5343        const Type *OpNTy =
5344          Node->getOperand(0).getValueType().getTypeForMVT();
5345        CV.push_back(UndefValue::get(OpNTy));
5346      }
5347    }
5348    Constant *CP = ConstantVector::get(CV);
5349    SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5350    unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5351    return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5352                       PseudoSourceValue::getConstantPool(), 0,
5353                       false, Alignment);
5354  }
5355
5356  if (SplatValue.getNode()) {   // Splat of one value?
5357    // Build the shuffle constant vector: <0, 0, 0, 0>
5358    MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5359    SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5360    std::vector<SDValue> ZeroVec(NumElems, Zero);
5361    SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5362                                      &ZeroVec[0], ZeroVec.size());
5363
5364    // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5365    if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5366      // Get the splatted value into the low element of a vector register.
5367      SDValue LowValVec =
5368        DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5369
5370      // Return shuffle(LowValVec, undef, <0,0,0,0>)
5371      return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5372                         DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5373                         SplatMask);
5374    }
5375  }
5376
5377  // If there are only two unique elements, we may be able to turn this into a
5378  // vector shuffle.
5379  if (Values.size() == 2) {
5380    // Get the two values in deterministic order.
5381    SDValue Val1 = Node->getOperand(1);
5382    SDValue Val2;
5383    std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5384    if (MI->first != Val1)
5385      Val2 = MI->first;
5386    else
5387      Val2 = (++MI)->first;
5388
5389    // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5390    // vector shuffle has the undef vector on the RHS.
5391    if (Val1.getOpcode() == ISD::UNDEF)
5392      std::swap(Val1, Val2);
5393
5394    // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5395    MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5396    MVT MaskEltVT = MaskVT.getVectorElementType();
5397    std::vector<SDValue> MaskVec(NumElems);
5398
5399    // Set elements of the shuffle mask for Val1.
5400    std::vector<unsigned> &Val1Elts = Values[Val1];
5401    for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5402      MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5403
5404    // Set elements of the shuffle mask for Val2.
5405    std::vector<unsigned> &Val2Elts = Values[Val2];
5406    for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5407      if (Val2.getOpcode() != ISD::UNDEF)
5408        MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5409      else
5410        MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5411
5412    SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5413                                        &MaskVec[0], MaskVec.size());
5414
5415    // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5416    if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5417        isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5418      Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5419      Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5420      SDValue Ops[] = { Val1, Val2, ShuffleMask };
5421
5422      // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5423      return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5424    }
5425  }
5426
5427  // Otherwise, we can't handle this case efficiently.  Allocate a sufficiently
5428  // aligned object on the stack, store each element into it, then load
5429  // the result as a vector.
5430  MVT VT = Node->getValueType(0);
5431  // Create the stack frame object.
5432  SDValue FIPtr = DAG.CreateStackTemporary(VT);
5433
5434  // Emit a store of each element to the stack slot.
5435  SmallVector<SDValue, 8> Stores;
5436  unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5437  // Store (in the right endianness) the elements to memory.
5438  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5439    // Ignore undef elements.
5440    if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5441
5442    unsigned Offset = TypeByteSize*i;
5443
5444    SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5445    Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5446
5447    Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5448                                  NULL, 0));
5449  }
5450
5451  SDValue StoreChain;
5452  if (!Stores.empty())    // Not all undef elements?
5453    StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5454                             &Stores[0], Stores.size());
5455  else
5456    StoreChain = DAG.getEntryNode();
5457
5458  // Result is a load from the stack slot.
5459  return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5460}
5461
5462void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5463                                            SDValue Op, SDValue Amt,
5464                                            SDValue &Lo, SDValue &Hi) {
5465  // Expand the subcomponents.
5466  SDValue LHSL, LHSH;
5467  ExpandOp(Op, LHSL, LHSH);
5468
5469  SDValue Ops[] = { LHSL, LHSH, Amt };
5470  MVT VT = LHSL.getValueType();
5471  Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5472  Hi = Lo.getValue(1);
5473}
5474
5475
5476/// ExpandShift - Try to find a clever way to expand this shift operation out to
5477/// smaller elements.  If we can't find a way that is more efficient than a
5478/// libcall on this target, return false.  Otherwise, return true with the
5479/// low-parts expanded into Lo and Hi.
5480bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5481                                       SDValue &Lo, SDValue &Hi) {
5482  assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5483         "This is not a shift!");
5484
5485  MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5486  SDValue ShAmt = LegalizeOp(Amt);
5487  MVT ShTy = ShAmt.getValueType();
5488  unsigned ShBits = ShTy.getSizeInBits();
5489  unsigned VTBits = Op.getValueType().getSizeInBits();
5490  unsigned NVTBits = NVT.getSizeInBits();
5491
5492  // Handle the case when Amt is an immediate.
5493  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5494    unsigned Cst = CN->getZExtValue();
5495    // Expand the incoming operand to be shifted, so that we have its parts
5496    SDValue InL, InH;
5497    ExpandOp(Op, InL, InH);
5498    switch(Opc) {
5499    case ISD::SHL:
5500      if (Cst > VTBits) {
5501        Lo = DAG.getConstant(0, NVT);
5502        Hi = DAG.getConstant(0, NVT);
5503      } else if (Cst > NVTBits) {
5504        Lo = DAG.getConstant(0, NVT);
5505        Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5506      } else if (Cst == NVTBits) {
5507        Lo = DAG.getConstant(0, NVT);
5508        Hi = InL;
5509      } else {
5510        Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5511        Hi = DAG.getNode(ISD::OR, NVT,
5512           DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5513           DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5514      }
5515      return true;
5516    case ISD::SRL:
5517      if (Cst > VTBits) {
5518        Lo = DAG.getConstant(0, NVT);
5519        Hi = DAG.getConstant(0, NVT);
5520      } else if (Cst > NVTBits) {
5521        Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5522        Hi = DAG.getConstant(0, NVT);
5523      } else if (Cst == NVTBits) {
5524        Lo = InH;
5525        Hi = DAG.getConstant(0, NVT);
5526      } else {
5527        Lo = DAG.getNode(ISD::OR, NVT,
5528           DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5529           DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5530        Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5531      }
5532      return true;
5533    case ISD::SRA:
5534      if (Cst > VTBits) {
5535        Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5536                              DAG.getConstant(NVTBits-1, ShTy));
5537      } else if (Cst > NVTBits) {
5538        Lo = DAG.getNode(ISD::SRA, NVT, InH,
5539                           DAG.getConstant(Cst-NVTBits, ShTy));
5540        Hi = DAG.getNode(ISD::SRA, NVT, InH,
5541                              DAG.getConstant(NVTBits-1, ShTy));
5542      } else if (Cst == NVTBits) {
5543        Lo = InH;
5544        Hi = DAG.getNode(ISD::SRA, NVT, InH,
5545                              DAG.getConstant(NVTBits-1, ShTy));
5546      } else {
5547        Lo = DAG.getNode(ISD::OR, NVT,
5548           DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5549           DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5550        Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5551      }
5552      return true;
5553    }
5554  }
5555
5556  // Okay, the shift amount isn't constant.  However, if we can tell that it is
5557  // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5558  APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5559  APInt KnownZero, KnownOne;
5560  DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5561
5562  // If we know that if any of the high bits of the shift amount are one, then
5563  // we can do this as a couple of simple shifts.
5564  if (KnownOne.intersects(Mask)) {
5565    // Mask out the high bit, which we know is set.
5566    Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5567                      DAG.getConstant(~Mask, Amt.getValueType()));
5568
5569    // Expand the incoming operand to be shifted, so that we have its parts
5570    SDValue InL, InH;
5571    ExpandOp(Op, InL, InH);
5572    switch(Opc) {
5573    case ISD::SHL:
5574      Lo = DAG.getConstant(0, NVT);              // Low part is zero.
5575      Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5576      return true;
5577    case ISD::SRL:
5578      Hi = DAG.getConstant(0, NVT);              // Hi part is zero.
5579      Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5580      return true;
5581    case ISD::SRA:
5582      Hi = DAG.getNode(ISD::SRA, NVT, InH,       // Sign extend high part.
5583                       DAG.getConstant(NVTBits-1, Amt.getValueType()));
5584      Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5585      return true;
5586    }
5587  }
5588
5589  // If we know that the high bits of the shift amount are all zero, then we can
5590  // do this as a couple of simple shifts.
5591  if ((KnownZero & Mask) == Mask) {
5592    // Compute 32-amt.
5593    SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5594                                 DAG.getConstant(NVTBits, Amt.getValueType()),
5595                                 Amt);
5596
5597    // Expand the incoming operand to be shifted, so that we have its parts
5598    SDValue InL, InH;
5599    ExpandOp(Op, InL, InH);
5600    switch(Opc) {
5601    case ISD::SHL:
5602      Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5603      Hi = DAG.getNode(ISD::OR, NVT,
5604                       DAG.getNode(ISD::SHL, NVT, InH, Amt),
5605                       DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5606      return true;
5607    case ISD::SRL:
5608      Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5609      Lo = DAG.getNode(ISD::OR, NVT,
5610                       DAG.getNode(ISD::SRL, NVT, InL, Amt),
5611                       DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5612      return true;
5613    case ISD::SRA:
5614      Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5615      Lo = DAG.getNode(ISD::OR, NVT,
5616                       DAG.getNode(ISD::SRL, NVT, InL, Amt),
5617                       DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5618      return true;
5619    }
5620  }
5621
5622  return false;
5623}
5624
5625
5626// ExpandLibCall - Expand a node into a call to a libcall.  If the result value
5627// does not fit into a register, return the lo part and set the hi part to the
5628// by-reg argument.  If it does fit into a single register, return the result
5629// and leave the Hi part unset.
5630SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5631                                            bool isSigned, SDValue &Hi) {
5632  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5633  // The input chain to this libcall is the entry node of the function.
5634  // Legalizing the call will automatically add the previous call to the
5635  // dependence.
5636  SDValue InChain = DAG.getEntryNode();
5637
5638  TargetLowering::ArgListTy Args;
5639  TargetLowering::ArgListEntry Entry;
5640  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5641    MVT ArgVT = Node->getOperand(i).getValueType();
5642    const Type *ArgTy = ArgVT.getTypeForMVT();
5643    Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5644    Entry.isSExt = isSigned;
5645    Entry.isZExt = !isSigned;
5646    Args.push_back(Entry);
5647  }
5648  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5649                                         TLI.getPointerTy());
5650
5651  // Splice the libcall in wherever FindInputOutputChains tells us to.
5652  const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5653  std::pair<SDValue,SDValue> CallInfo =
5654    TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5655                    CallingConv::C, false, Callee, Args, DAG);
5656
5657  // Legalize the call sequence, starting with the chain.  This will advance
5658  // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5659  // was added by LowerCallTo (guaranteeing proper serialization of calls).
5660  LegalizeOp(CallInfo.second);
5661  SDValue Result;
5662  switch (getTypeAction(CallInfo.first.getValueType())) {
5663  default: assert(0 && "Unknown thing");
5664  case Legal:
5665    Result = CallInfo.first;
5666    break;
5667  case Expand:
5668    ExpandOp(CallInfo.first, Result, Hi);
5669    break;
5670  }
5671  return Result;
5672}
5673
5674/// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5675///
5676SDValue SelectionDAGLegalize::
5677LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5678  bool isCustom = false;
5679  SDValue Tmp1;
5680  switch (getTypeAction(Op.getValueType())) {
5681  case Legal:
5682    switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5683                                   Op.getValueType())) {
5684    default: assert(0 && "Unknown operation action!");
5685    case TargetLowering::Custom:
5686      isCustom = true;
5687      // FALLTHROUGH
5688    case TargetLowering::Legal:
5689      Tmp1 = LegalizeOp(Op);
5690      if (Result.getNode())
5691        Result = DAG.UpdateNodeOperands(Result, Tmp1);
5692      else
5693        Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5694                             DestTy, Tmp1);
5695      if (isCustom) {
5696        Tmp1 = TLI.LowerOperation(Result, DAG);
5697        if (Tmp1.getNode()) Result = Tmp1;
5698      }
5699      break;
5700    case TargetLowering::Expand:
5701      Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5702      break;
5703    case TargetLowering::Promote:
5704      Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5705      break;
5706    }
5707    break;
5708  case Expand:
5709    Result = ExpandIntToFP(isSigned, DestTy, Op);
5710    break;
5711  case Promote:
5712    Tmp1 = PromoteOp(Op);
5713    if (isSigned) {
5714      Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5715               Tmp1, DAG.getValueType(Op.getValueType()));
5716    } else {
5717      Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5718                                    Op.getValueType());
5719    }
5720    if (Result.getNode())
5721      Result = DAG.UpdateNodeOperands(Result, Tmp1);
5722    else
5723      Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5724                           DestTy, Tmp1);
5725    Result = LegalizeOp(Result);  // The 'op' is not necessarily legal!
5726    break;
5727  }
5728  return Result;
5729}
5730
5731/// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5732///
5733SDValue SelectionDAGLegalize::
5734ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5735  MVT SourceVT = Source.getValueType();
5736  bool ExpandSource = getTypeAction(SourceVT) == Expand;
5737
5738  // Expand unsupported int-to-fp vector casts by unrolling them.
5739  if (DestTy.isVector()) {
5740    if (!ExpandSource)
5741      return LegalizeOp(UnrollVectorOp(Source));
5742    MVT DestEltTy = DestTy.getVectorElementType();
5743    if (DestTy.getVectorNumElements() == 1) {
5744      SDValue Scalar = ScalarizeVectorOp(Source);
5745      SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5746                                         DestEltTy, Scalar);
5747      return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5748    }
5749    SDValue Lo, Hi;
5750    SplitVectorOp(Source, Lo, Hi);
5751    MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5752                                       DestTy.getVectorNumElements() / 2);
5753    SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5754    SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5755    return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult,
5756                                  HiResult));
5757  }
5758
5759  // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5760  if (!isSigned && SourceVT != MVT::i32) {
5761    // The integer value loaded will be incorrectly if the 'sign bit' of the
5762    // incoming integer is set.  To handle this, we dynamically test to see if
5763    // it is set, and, if so, add a fudge factor.
5764    SDValue Hi;
5765    if (ExpandSource) {
5766      SDValue Lo;
5767      ExpandOp(Source, Lo, Hi);
5768      Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5769    } else {
5770      // The comparison for the sign bit will use the entire operand.
5771      Hi = Source;
5772    }
5773
5774    // Check to see if the target has a custom way to lower this.  If so, use
5775    // it.  (Note we've already expanded the operand in this case.)
5776    switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5777    default: assert(0 && "This action not implemented for this operation!");
5778    case TargetLowering::Legal:
5779    case TargetLowering::Expand:
5780      break;   // This case is handled below.
5781    case TargetLowering::Custom: {
5782      SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
5783                                                    Source), DAG);
5784      if (NV.getNode())
5785        return LegalizeOp(NV);
5786      break;   // The target decided this was legal after all
5787    }
5788    }
5789
5790    // If this is unsigned, and not supported, first perform the conversion to
5791    // signed, then adjust the result if the sign bit is set.
5792    SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5793
5794    SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5795                                     DAG.getConstant(0, Hi.getValueType()),
5796                                     ISD::SETLT);
5797    SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5798    SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5799                                      SignSet, Four, Zero);
5800    uint64_t FF = 0x5f800000ULL;
5801    if (TLI.isLittleEndian()) FF <<= 32;
5802    static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5803
5804    SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5805    unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5806    CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5807    Alignment = std::min(Alignment, 4u);
5808    SDValue FudgeInReg;
5809    if (DestTy == MVT::f32)
5810      FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5811                               PseudoSourceValue::getConstantPool(), 0,
5812                               false, Alignment);
5813    else if (DestTy.bitsGT(MVT::f32))
5814      // FIXME: Avoid the extend by construction the right constantpool?
5815      FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5816                                  CPIdx,
5817                                  PseudoSourceValue::getConstantPool(), 0,
5818                                  MVT::f32, false, Alignment);
5819    else
5820      assert(0 && "Unexpected conversion");
5821
5822    MVT SCVT = SignedConv.getValueType();
5823    if (SCVT != DestTy) {
5824      // Destination type needs to be expanded as well. The FADD now we are
5825      // constructing will be expanded into a libcall.
5826      if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5827        assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5828        SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5829                                 SignedConv, SignedConv.getValue(1));
5830      }
5831      SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5832    }
5833    return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5834  }
5835
5836  // Check to see if the target has a custom way to lower this.  If so, use it.
5837  switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5838  default: assert(0 && "This action not implemented for this operation!");
5839  case TargetLowering::Legal:
5840  case TargetLowering::Expand:
5841    break;   // This case is handled below.
5842  case TargetLowering::Custom: {
5843    SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5844                                                  Source), DAG);
5845    if (NV.getNode())
5846      return LegalizeOp(NV);
5847    break;   // The target decided this was legal after all
5848  }
5849  }
5850
5851  // Expand the source, then glue it back together for the call.  We must expand
5852  // the source in case it is shared (this pass of legalize must traverse it).
5853  if (ExpandSource) {
5854    SDValue SrcLo, SrcHi;
5855    ExpandOp(Source, SrcLo, SrcHi);
5856    Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5857  }
5858
5859  RTLIB::Libcall LC = isSigned ?
5860    RTLIB::getSINTTOFP(SourceVT, DestTy) :
5861    RTLIB::getUINTTOFP(SourceVT, DestTy);
5862  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5863
5864  Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5865  SDValue HiPart;
5866  SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
5867  if (Result.getValueType() != DestTy && HiPart.getNode())
5868    Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5869  return Result;
5870}
5871
5872/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5873/// INT_TO_FP operation of the specified operand when the target requests that
5874/// we expand it.  At this point, we know that the result and operand types are
5875/// legal for the target.
5876SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5877                                                   SDValue Op0,
5878                                                   MVT DestVT) {
5879  if (Op0.getValueType() == MVT::i32) {
5880    // simple 32-bit [signed|unsigned] integer to float/double expansion
5881
5882    // Get the stack frame index of a 8 byte buffer.
5883    SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
5884
5885    // word offset constant for Hi/Lo address computation
5886    SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5887    // set up Hi and Lo (into buffer) address based on endian
5888    SDValue Hi = StackSlot;
5889    SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5890    if (TLI.isLittleEndian())
5891      std::swap(Hi, Lo);
5892
5893    // if signed map to unsigned space
5894    SDValue Op0Mapped;
5895    if (isSigned) {
5896      // constant used to invert sign bit (signed to unsigned mapping)
5897      SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5898      Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5899    } else {
5900      Op0Mapped = Op0;
5901    }
5902    // store the lo of the constructed double - based on integer input
5903    SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
5904                                    Op0Mapped, Lo, NULL, 0);
5905    // initial hi portion of constructed double
5906    SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5907    // store the hi of the constructed double - biased exponent
5908    SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5909    // load the constructed double
5910    SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5911    // FP constant to bias correct the final result
5912    SDValue Bias = DAG.getConstantFP(isSigned ?
5913                                            BitsToDouble(0x4330000080000000ULL)
5914                                          : BitsToDouble(0x4330000000000000ULL),
5915                                     MVT::f64);
5916    // subtract the bias
5917    SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5918    // final result
5919    SDValue Result;
5920    // handle final rounding
5921    if (DestVT == MVT::f64) {
5922      // do nothing
5923      Result = Sub;
5924    } else if (DestVT.bitsLT(MVT::f64)) {
5925      Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5926                           DAG.getIntPtrConstant(0));
5927    } else if (DestVT.bitsGT(MVT::f64)) {
5928      Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5929    }
5930    return Result;
5931  }
5932  assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5933  SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5934
5935  SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5936                                   DAG.getConstant(0, Op0.getValueType()),
5937                                   ISD::SETLT);
5938  SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5939  SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5940                                    SignSet, Four, Zero);
5941
5942  // If the sign bit of the integer is set, the large number will be treated
5943  // as a negative number.  To counteract this, the dynamic code adds an
5944  // offset depending on the data type.
5945  uint64_t FF;
5946  switch (Op0.getValueType().getSimpleVT()) {
5947  default: assert(0 && "Unsupported integer type!");
5948  case MVT::i8 : FF = 0x43800000ULL; break;  // 2^8  (as a float)
5949  case MVT::i16: FF = 0x47800000ULL; break;  // 2^16 (as a float)
5950  case MVT::i32: FF = 0x4F800000ULL; break;  // 2^32 (as a float)
5951  case MVT::i64: FF = 0x5F800000ULL; break;  // 2^64 (as a float)
5952  }
5953  if (TLI.isLittleEndian()) FF <<= 32;
5954  static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5955
5956  SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5957  unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5958  CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5959  Alignment = std::min(Alignment, 4u);
5960  SDValue FudgeInReg;
5961  if (DestVT == MVT::f32)
5962    FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5963                             PseudoSourceValue::getConstantPool(), 0,
5964                             false, Alignment);
5965  else {
5966    FudgeInReg =
5967      LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5968                                DAG.getEntryNode(), CPIdx,
5969                                PseudoSourceValue::getConstantPool(), 0,
5970                                MVT::f32, false, Alignment));
5971  }
5972
5973  return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5974}
5975
5976/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5977/// *INT_TO_FP operation of the specified operand when the target requests that
5978/// we promote it.  At this point, we know that the result and operand types are
5979/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5980/// operation that takes a larger input.
5981SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
5982                                                    MVT DestVT,
5983                                                    bool isSigned) {
5984  // First step, figure out the appropriate *INT_TO_FP operation to use.
5985  MVT NewInTy = LegalOp.getValueType();
5986
5987  unsigned OpToUse = 0;
5988
5989  // Scan for the appropriate larger type to use.
5990  while (1) {
5991    NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
5992    assert(NewInTy.isInteger() && "Ran out of possibilities!");
5993
5994    // If the target supports SINT_TO_FP of this type, use it.
5995    switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5996      default: break;
5997      case TargetLowering::Legal:
5998        if (!TLI.isTypeLegal(NewInTy))
5999          break;  // Can't use this datatype.
6000        // FALL THROUGH.
6001      case TargetLowering::Custom:
6002        OpToUse = ISD::SINT_TO_FP;
6003        break;
6004    }
6005    if (OpToUse) break;
6006    if (isSigned) continue;
6007
6008    // If the target supports UINT_TO_FP of this type, use it.
6009    switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6010      default: break;
6011      case TargetLowering::Legal:
6012        if (!TLI.isTypeLegal(NewInTy))
6013          break;  // Can't use this datatype.
6014        // FALL THROUGH.
6015      case TargetLowering::Custom:
6016        OpToUse = ISD::UINT_TO_FP;
6017        break;
6018    }
6019    if (OpToUse) break;
6020
6021    // Otherwise, try a larger type.
6022  }
6023
6024  // Okay, we found the operation and type to use.  Zero extend our input to the
6025  // desired type then run the operation on it.
6026  return DAG.getNode(OpToUse, DestVT,
6027                     DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6028                                 NewInTy, LegalOp));
6029}
6030
6031/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6032/// FP_TO_*INT operation of the specified operand when the target requests that
6033/// we promote it.  At this point, we know that the result and operand types are
6034/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6035/// operation that returns a larger result.
6036SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6037                                                    MVT DestVT,
6038                                                    bool isSigned) {
6039  // First step, figure out the appropriate FP_TO*INT operation to use.
6040  MVT NewOutTy = DestVT;
6041
6042  unsigned OpToUse = 0;
6043
6044  // Scan for the appropriate larger type to use.
6045  while (1) {
6046    NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6047    assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6048
6049    // If the target supports FP_TO_SINT returning this type, use it.
6050    switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6051    default: break;
6052    case TargetLowering::Legal:
6053      if (!TLI.isTypeLegal(NewOutTy))
6054        break;  // Can't use this datatype.
6055      // FALL THROUGH.
6056    case TargetLowering::Custom:
6057      OpToUse = ISD::FP_TO_SINT;
6058      break;
6059    }
6060    if (OpToUse) break;
6061
6062    // If the target supports FP_TO_UINT of this type, use it.
6063    switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6064    default: break;
6065    case TargetLowering::Legal:
6066      if (!TLI.isTypeLegal(NewOutTy))
6067        break;  // Can't use this datatype.
6068      // FALL THROUGH.
6069    case TargetLowering::Custom:
6070      OpToUse = ISD::FP_TO_UINT;
6071      break;
6072    }
6073    if (OpToUse) break;
6074
6075    // Otherwise, try a larger type.
6076  }
6077
6078
6079  // Okay, we found the operation and type to use.
6080  SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
6081
6082  // If the operation produces an invalid type, it must be custom lowered.  Use
6083  // the target lowering hooks to expand it.  Just keep the low part of the
6084  // expanded operation, we know that we're truncating anyway.
6085  if (getTypeAction(NewOutTy) == Expand) {
6086    Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(), DAG), 0);
6087    assert(Operation.getNode() && "Didn't return anything");
6088  }
6089
6090  // Truncate the result of the extended FP_TO_*INT operation to the desired
6091  // size.
6092  return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
6093}
6094
6095/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6096///
6097SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
6098  MVT VT = Op.getValueType();
6099  MVT SHVT = TLI.getShiftAmountTy();
6100  SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6101  switch (VT.getSimpleVT()) {
6102  default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6103  case MVT::i16:
6104    Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6105    Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6106    return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
6107  case MVT::i32:
6108    Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6109    Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6110    Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6111    Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6112    Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6113    Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6114    Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6115    Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6116    return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6117  case MVT::i64:
6118    Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
6119    Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
6120    Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6121    Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6122    Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6123    Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6124    Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
6125    Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
6126    Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6127    Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6128    Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6129    Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6130    Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6131    Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6132    Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
6133    Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
6134    Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6135    Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6136    Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
6137    Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6138    return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
6139  }
6140}
6141
6142/// ExpandBitCount - Expand the specified bitcount instruction into operations.
6143///
6144SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
6145  switch (Opc) {
6146  default: assert(0 && "Cannot expand this yet!");
6147  case ISD::CTPOP: {
6148    static const uint64_t mask[6] = {
6149      0x5555555555555555ULL, 0x3333333333333333ULL,
6150      0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6151      0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6152    };
6153    MVT VT = Op.getValueType();
6154    MVT ShVT = TLI.getShiftAmountTy();
6155    unsigned len = VT.getSizeInBits();
6156    for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6157      //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6158      SDValue Tmp2 = DAG.getConstant(mask[i], VT);
6159      SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6160      Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
6161                       DAG.getNode(ISD::AND, VT,
6162                                   DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
6163    }
6164    return Op;
6165  }
6166  case ISD::CTLZ: {
6167    // for now, we do this:
6168    // x = x | (x >> 1);
6169    // x = x | (x >> 2);
6170    // ...
6171    // x = x | (x >>16);
6172    // x = x | (x >>32); // for 64-bit input
6173    // return popcount(~x);
6174    //
6175    // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6176    MVT VT = Op.getValueType();
6177    MVT ShVT = TLI.getShiftAmountTy();
6178    unsigned len = VT.getSizeInBits();
6179    for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6180      SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6181      Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
6182    }
6183    Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
6184    return DAG.getNode(ISD::CTPOP, VT, Op);
6185  }
6186  case ISD::CTTZ: {
6187    // for now, we use: { return popcount(~x & (x - 1)); }
6188    // unless the target has ctlz but not ctpop, in which case we use:
6189    // { return 32 - nlz(~x & (x-1)); }
6190    // see also http://www.hackersdelight.org/HDcode/ntz.cc
6191    MVT VT = Op.getValueType();
6192    SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
6193    SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
6194                       DAG.getNode(ISD::XOR, VT, Op, Tmp2),
6195                       DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
6196    // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6197    if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
6198        TLI.isOperationLegal(ISD::CTLZ, VT))
6199      return DAG.getNode(ISD::SUB, VT,
6200                         DAG.getConstant(VT.getSizeInBits(), VT),
6201                         DAG.getNode(ISD::CTLZ, VT, Tmp3));
6202    return DAG.getNode(ISD::CTPOP, VT, Tmp3);
6203  }
6204  }
6205}
6206
6207/// ExpandOp - Expand the specified SDValue into its two component pieces
6208/// Lo&Hi.  Note that the Op MUST be an expanded type.  As a result of this, the
6209/// LegalizedNodes map is filled in for any results that are not expanded, the
6210/// ExpandedNodes map is filled in for any results that are expanded, and the
6211/// Lo/Hi values are returned.
6212void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6213  MVT VT = Op.getValueType();
6214  MVT NVT = TLI.getTypeToTransformTo(VT);
6215  SDNode *Node = Op.getNode();
6216  assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6217  assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6218         VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6219
6220  // See if we already expanded it.
6221  DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6222    = ExpandedNodes.find(Op);
6223  if (I != ExpandedNodes.end()) {
6224    Lo = I->second.first;
6225    Hi = I->second.second;
6226    return;
6227  }
6228
6229  switch (Node->getOpcode()) {
6230  case ISD::CopyFromReg:
6231    assert(0 && "CopyFromReg must be legal!");
6232  case ISD::FP_ROUND_INREG:
6233    if (VT == MVT::ppcf128 &&
6234        TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6235            TargetLowering::Custom) {
6236      SDValue SrcLo, SrcHi, Src;
6237      ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6238      Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
6239      SDValue Result = TLI.LowerOperation(
6240        DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
6241      assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6242      Lo = Result.getNode()->getOperand(0);
6243      Hi = Result.getNode()->getOperand(1);
6244      break;
6245    }
6246    // fall through
6247  default:
6248#ifndef NDEBUG
6249    cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6250#endif
6251    assert(0 && "Do not know how to expand this operator!");
6252    abort();
6253  case ISD::EXTRACT_ELEMENT:
6254    ExpandOp(Node->getOperand(0), Lo, Hi);
6255    if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6256      return ExpandOp(Hi, Lo, Hi);
6257    return ExpandOp(Lo, Lo, Hi);
6258  case ISD::EXTRACT_VECTOR_ELT:
6259    // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6260    Lo  = ExpandEXTRACT_VECTOR_ELT(Op);
6261    return ExpandOp(Lo, Lo, Hi);
6262  case ISD::UNDEF:
6263    Lo = DAG.getNode(ISD::UNDEF, NVT);
6264    Hi = DAG.getNode(ISD::UNDEF, NVT);
6265    break;
6266  case ISD::Constant: {
6267    unsigned NVTBits = NVT.getSizeInBits();
6268    const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6269    Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6270    Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6271    break;
6272  }
6273  case ISD::ConstantFP: {
6274    ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6275    if (CFP->getValueType(0) == MVT::ppcf128) {
6276      APInt api = CFP->getValueAPF().bitcastToAPInt();
6277      Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6278                             MVT::f64);
6279      Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6280                             MVT::f64);
6281      break;
6282    }
6283    Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6284    if (getTypeAction(Lo.getValueType()) == Expand)
6285      ExpandOp(Lo, Lo, Hi);
6286    break;
6287  }
6288  case ISD::BUILD_PAIR:
6289    // Return the operands.
6290    Lo = Node->getOperand(0);
6291    Hi = Node->getOperand(1);
6292    break;
6293
6294  case ISD::MERGE_VALUES:
6295    if (Node->getNumValues() == 1) {
6296      ExpandOp(Op.getOperand(0), Lo, Hi);
6297      break;
6298    }
6299    // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6300    assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6301           Op.getValue(1).getValueType() == MVT::Other &&
6302           "unhandled MERGE_VALUES");
6303    ExpandOp(Op.getOperand(0), Lo, Hi);
6304    // Remember that we legalized the chain.
6305    AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6306    break;
6307
6308  case ISD::SIGN_EXTEND_INREG:
6309    ExpandOp(Node->getOperand(0), Lo, Hi);
6310    // sext_inreg the low part if needed.
6311    Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
6312
6313    // The high part gets the sign extension from the lo-part.  This handles
6314    // things like sextinreg V:i64 from i8.
6315    Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6316                     DAG.getConstant(NVT.getSizeInBits()-1,
6317                                     TLI.getShiftAmountTy()));
6318    break;
6319
6320  case ISD::BSWAP: {
6321    ExpandOp(Node->getOperand(0), Lo, Hi);
6322    SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
6323    Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
6324    Lo = TempLo;
6325    break;
6326  }
6327
6328  case ISD::CTPOP:
6329    ExpandOp(Node->getOperand(0), Lo, Hi);
6330    Lo = DAG.getNode(ISD::ADD, NVT,          // ctpop(HL) -> ctpop(H)+ctpop(L)
6331                     DAG.getNode(ISD::CTPOP, NVT, Lo),
6332                     DAG.getNode(ISD::CTPOP, NVT, Hi));
6333    Hi = DAG.getConstant(0, NVT);
6334    break;
6335
6336  case ISD::CTLZ: {
6337    // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6338    ExpandOp(Node->getOperand(0), Lo, Hi);
6339    SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6340    SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
6341    SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
6342                                        ISD::SETNE);
6343    SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
6344    LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
6345
6346    Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
6347    Hi = DAG.getConstant(0, NVT);
6348    break;
6349  }
6350
6351  case ISD::CTTZ: {
6352    // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6353    ExpandOp(Node->getOperand(0), Lo, Hi);
6354    SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6355    SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
6356    SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
6357                                        ISD::SETNE);
6358    SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
6359    HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
6360
6361    Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
6362    Hi = DAG.getConstant(0, NVT);
6363    break;
6364  }
6365
6366  case ISD::VAARG: {
6367    SDValue Ch = Node->getOperand(0);   // Legalize the chain.
6368    SDValue Ptr = Node->getOperand(1);  // Legalize the pointer.
6369    Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6370    Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6371
6372    // Remember that we legalized the chain.
6373    Hi = LegalizeOp(Hi);
6374    AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6375    if (TLI.isBigEndian())
6376      std::swap(Lo, Hi);
6377    break;
6378  }
6379
6380  case ISD::LOAD: {
6381    LoadSDNode *LD = cast<LoadSDNode>(Node);
6382    SDValue Ch  = LD->getChain();    // Legalize the chain.
6383    SDValue Ptr = LD->getBasePtr();  // Legalize the pointer.
6384    ISD::LoadExtType ExtType = LD->getExtensionType();
6385    const Value *SV = LD->getSrcValue();
6386    int SVOffset = LD->getSrcValueOffset();
6387    unsigned Alignment = LD->getAlignment();
6388    bool isVolatile = LD->isVolatile();
6389
6390    if (ExtType == ISD::NON_EXTLOAD) {
6391      Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6392                       isVolatile, Alignment);
6393      if (VT == MVT::f32 || VT == MVT::f64) {
6394        // f32->i32 or f64->i64 one to one expansion.
6395        // Remember that we legalized the chain.
6396        AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6397        // Recursively expand the new load.
6398        if (getTypeAction(NVT) == Expand)
6399          ExpandOp(Lo, Lo, Hi);
6400        break;
6401      }
6402
6403      // Increment the pointer to the other half.
6404      unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6405      Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6406                        DAG.getIntPtrConstant(IncrementSize));
6407      SVOffset += IncrementSize;
6408      Alignment = MinAlign(Alignment, IncrementSize);
6409      Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6410                       isVolatile, Alignment);
6411
6412      // Build a factor node to remember that this load is independent of the
6413      // other one.
6414      SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6415                                 Hi.getValue(1));
6416
6417      // Remember that we legalized the chain.
6418      AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6419      if (TLI.isBigEndian())
6420        std::swap(Lo, Hi);
6421    } else {
6422      MVT EVT = LD->getMemoryVT();
6423
6424      if ((VT == MVT::f64 && EVT == MVT::f32) ||
6425          (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6426        // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6427        SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
6428                                     SVOffset, isVolatile, Alignment);
6429        // Remember that we legalized the chain.
6430        AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6431        ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6432        break;
6433      }
6434
6435      if (EVT == NVT)
6436        Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
6437                         SVOffset, isVolatile, Alignment);
6438      else
6439        Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
6440                            SVOffset, EVT, isVolatile,
6441                            Alignment);
6442
6443      // Remember that we legalized the chain.
6444      AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6445
6446      if (ExtType == ISD::SEXTLOAD) {
6447        // The high part is obtained by SRA'ing all but one of the bits of the
6448        // lo part.
6449        unsigned LoSize = Lo.getValueType().getSizeInBits();
6450        Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6451                         DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6452      } else if (ExtType == ISD::ZEXTLOAD) {
6453        // The high part is just a zero.
6454        Hi = DAG.getConstant(0, NVT);
6455      } else /* if (ExtType == ISD::EXTLOAD) */ {
6456        // The high part is undefined.
6457        Hi = DAG.getNode(ISD::UNDEF, NVT);
6458      }
6459    }
6460    break;
6461  }
6462  case ISD::AND:
6463  case ISD::OR:
6464  case ISD::XOR: {   // Simple logical operators -> two trivial pieces.
6465    SDValue LL, LH, RL, RH;
6466    ExpandOp(Node->getOperand(0), LL, LH);
6467    ExpandOp(Node->getOperand(1), RL, RH);
6468    Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6469    Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6470    break;
6471  }
6472  case ISD::SELECT: {
6473    SDValue LL, LH, RL, RH;
6474    ExpandOp(Node->getOperand(1), LL, LH);
6475    ExpandOp(Node->getOperand(2), RL, RH);
6476    if (getTypeAction(NVT) == Expand)
6477      NVT = TLI.getTypeToExpandTo(NVT);
6478    Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6479    if (VT != MVT::f32)
6480      Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6481    break;
6482  }
6483  case ISD::SELECT_CC: {
6484    SDValue TL, TH, FL, FH;
6485    ExpandOp(Node->getOperand(2), TL, TH);
6486    ExpandOp(Node->getOperand(3), FL, FH);
6487    if (getTypeAction(NVT) == Expand)
6488      NVT = TLI.getTypeToExpandTo(NVT);
6489    Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6490                     Node->getOperand(1), TL, FL, Node->getOperand(4));
6491    if (VT != MVT::f32)
6492      Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6493                       Node->getOperand(1), TH, FH, Node->getOperand(4));
6494    break;
6495  }
6496  case ISD::ANY_EXTEND:
6497    // The low part is any extension of the input (which degenerates to a copy).
6498    Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6499    // The high part is undefined.
6500    Hi = DAG.getNode(ISD::UNDEF, NVT);
6501    break;
6502  case ISD::SIGN_EXTEND: {
6503    // The low part is just a sign extension of the input (which degenerates to
6504    // a copy).
6505    Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6506
6507    // The high part is obtained by SRA'ing all but one of the bits of the lo
6508    // part.
6509    unsigned LoSize = Lo.getValueType().getSizeInBits();
6510    Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6511                     DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6512    break;
6513  }
6514  case ISD::ZERO_EXTEND:
6515    // The low part is just a zero extension of the input (which degenerates to
6516    // a copy).
6517    Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6518
6519    // The high part is just a zero.
6520    Hi = DAG.getConstant(0, NVT);
6521    break;
6522
6523  case ISD::TRUNCATE: {
6524    // The input value must be larger than this value.  Expand *it*.
6525    SDValue NewLo;
6526    ExpandOp(Node->getOperand(0), NewLo, Hi);
6527
6528    // The low part is now either the right size, or it is closer.  If not the
6529    // right size, make an illegal truncate so we recursively expand it.
6530    if (NewLo.getValueType() != Node->getValueType(0))
6531      NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6532    ExpandOp(NewLo, Lo, Hi);
6533    break;
6534  }
6535
6536  case ISD::BIT_CONVERT: {
6537    SDValue Tmp;
6538    if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6539      // If the target wants to, allow it to lower this itself.
6540      switch (getTypeAction(Node->getOperand(0).getValueType())) {
6541      case Expand: assert(0 && "cannot expand FP!");
6542      case Legal:   Tmp = LegalizeOp(Node->getOperand(0)); break;
6543      case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6544      }
6545      Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6546    }
6547
6548    // f32 / f64 must be expanded to i32 / i64.
6549    if (VT == MVT::f32 || VT == MVT::f64) {
6550      Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6551      if (getTypeAction(NVT) == Expand)
6552        ExpandOp(Lo, Lo, Hi);
6553      break;
6554    }
6555
6556    // If source operand will be expanded to the same type as VT, i.e.
6557    // i64 <- f64, i32 <- f32, expand the source operand instead.
6558    MVT VT0 = Node->getOperand(0).getValueType();
6559    if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6560      ExpandOp(Node->getOperand(0), Lo, Hi);
6561      break;
6562    }
6563
6564    // Turn this into a load/store pair by default.
6565    if (Tmp.getNode() == 0)
6566      Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6567
6568    ExpandOp(Tmp, Lo, Hi);
6569    break;
6570  }
6571
6572  case ISD::READCYCLECOUNTER: {
6573    assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6574                 TargetLowering::Custom &&
6575           "Must custom expand ReadCycleCounter");
6576    SDValue Tmp = TLI.LowerOperation(Op, DAG);
6577    assert(Tmp.getNode() && "Node must be custom expanded!");
6578    ExpandOp(Tmp.getValue(0), Lo, Hi);
6579    AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6580                        LegalizeOp(Tmp.getValue(1)));
6581    break;
6582  }
6583
6584  case ISD::ATOMIC_CMP_SWAP_64: {
6585    // This operation does not need a loop.
6586    SDValue Tmp = TLI.LowerOperation(Op, DAG);
6587    assert(Tmp.getNode() && "Node must be custom expanded!");
6588    ExpandOp(Tmp.getValue(0), Lo, Hi);
6589    AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6590                        LegalizeOp(Tmp.getValue(1)));
6591    break;
6592  }
6593
6594  case ISD::ATOMIC_LOAD_ADD_64:
6595  case ISD::ATOMIC_LOAD_SUB_64:
6596  case ISD::ATOMIC_LOAD_AND_64:
6597  case ISD::ATOMIC_LOAD_OR_64:
6598  case ISD::ATOMIC_LOAD_XOR_64:
6599  case ISD::ATOMIC_LOAD_NAND_64:
6600  case ISD::ATOMIC_SWAP_64: {
6601    // These operations require a loop to be generated.  We can't do that yet,
6602    // so substitute a target-dependent pseudo and expand that later.
6603    SDValue In2Lo, In2Hi, In2;
6604    ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6605    In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
6606    AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6607    SDValue Replace =
6608      DAG.getAtomic(Op.getOpcode(), Op.getOperand(0), Op.getOperand(1), In2,
6609                    Anode->getSrcValue(), Anode->getAlignment());
6610    SDValue Result = TLI.LowerOperation(Replace, DAG);
6611    ExpandOp(Result.getValue(0), Lo, Hi);
6612    // Remember that we legalized the chain.
6613    AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6614    break;
6615  }
6616
6617    // These operators cannot be expanded directly, emit them as calls to
6618    // library functions.
6619  case ISD::FP_TO_SINT: {
6620    if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6621      SDValue Op;
6622      switch (getTypeAction(Node->getOperand(0).getValueType())) {
6623      case Expand: assert(0 && "cannot expand FP!");
6624      case Legal:   Op = LegalizeOp(Node->getOperand(0)); break;
6625      case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6626      }
6627
6628      Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6629
6630      // Now that the custom expander is done, expand the result, which is still
6631      // VT.
6632      if (Op.getNode()) {
6633        ExpandOp(Op, Lo, Hi);
6634        break;
6635      }
6636    }
6637
6638    RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6639                                           VT);
6640    assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6641    Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6642    break;
6643  }
6644
6645  case ISD::FP_TO_UINT: {
6646    if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6647      SDValue Op;
6648      switch (getTypeAction(Node->getOperand(0).getValueType())) {
6649        case Expand: assert(0 && "cannot expand FP!");
6650        case Legal:   Op = LegalizeOp(Node->getOperand(0)); break;
6651        case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6652      }
6653
6654      Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6655
6656      // Now that the custom expander is done, expand the result.
6657      if (Op.getNode()) {
6658        ExpandOp(Op, Lo, Hi);
6659        break;
6660      }
6661    }
6662
6663    RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6664                                           VT);
6665    assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6666    Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6667    break;
6668  }
6669
6670  case ISD::SHL: {
6671    // If the target wants custom lowering, do so.
6672    SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6673    if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6674      SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6675      Op = TLI.LowerOperation(Op, DAG);
6676      if (Op.getNode()) {
6677        // Now that the custom expander is done, expand the result, which is
6678        // still VT.
6679        ExpandOp(Op, Lo, Hi);
6680        break;
6681      }
6682    }
6683
6684    // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6685    // this X << 1 as X+X.
6686    if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6687      if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6688          TLI.isOperationLegal(ISD::ADDE, NVT)) {
6689        SDValue LoOps[2], HiOps[3];
6690        ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6691        SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6692        LoOps[1] = LoOps[0];
6693        Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6694
6695        HiOps[1] = HiOps[0];
6696        HiOps[2] = Lo.getValue(1);
6697        Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6698        break;
6699      }
6700    }
6701
6702    // If we can emit an efficient shift operation, do so now.
6703    if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6704      break;
6705
6706    // If this target supports SHL_PARTS, use it.
6707    TargetLowering::LegalizeAction Action =
6708      TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6709    if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6710        Action == TargetLowering::Custom) {
6711      ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6712      break;
6713    }
6714
6715    // Otherwise, emit a libcall.
6716    Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6717    break;
6718  }
6719
6720  case ISD::SRA: {
6721    // If the target wants custom lowering, do so.
6722    SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6723    if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6724      SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6725      Op = TLI.LowerOperation(Op, DAG);
6726      if (Op.getNode()) {
6727        // Now that the custom expander is done, expand the result, which is
6728        // still VT.
6729        ExpandOp(Op, Lo, Hi);
6730        break;
6731      }
6732    }
6733
6734    // If we can emit an efficient shift operation, do so now.
6735    if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6736      break;
6737
6738    // If this target supports SRA_PARTS, use it.
6739    TargetLowering::LegalizeAction Action =
6740      TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6741    if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6742        Action == TargetLowering::Custom) {
6743      ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6744      break;
6745    }
6746
6747    // Otherwise, emit a libcall.
6748    Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6749    break;
6750  }
6751
6752  case ISD::SRL: {
6753    // If the target wants custom lowering, do so.
6754    SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6755    if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6756      SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6757      Op = TLI.LowerOperation(Op, DAG);
6758      if (Op.getNode()) {
6759        // Now that the custom expander is done, expand the result, which is
6760        // still VT.
6761        ExpandOp(Op, Lo, Hi);
6762        break;
6763      }
6764    }
6765
6766    // If we can emit an efficient shift operation, do so now.
6767    if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6768      break;
6769
6770    // If this target supports SRL_PARTS, use it.
6771    TargetLowering::LegalizeAction Action =
6772      TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6773    if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6774        Action == TargetLowering::Custom) {
6775      ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6776      break;
6777    }
6778
6779    // Otherwise, emit a libcall.
6780    Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6781    break;
6782  }
6783
6784  case ISD::ADD:
6785  case ISD::SUB: {
6786    // If the target wants to custom expand this, let them.
6787    if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6788            TargetLowering::Custom) {
6789      SDValue Result = TLI.LowerOperation(Op, DAG);
6790      if (Result.getNode()) {
6791        ExpandOp(Result, Lo, Hi);
6792        break;
6793      }
6794    }
6795    // Expand the subcomponents.
6796    SDValue LHSL, LHSH, RHSL, RHSH;
6797    ExpandOp(Node->getOperand(0), LHSL, LHSH);
6798    ExpandOp(Node->getOperand(1), RHSL, RHSH);
6799    SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6800    SDValue LoOps[2], HiOps[3];
6801    LoOps[0] = LHSL;
6802    LoOps[1] = RHSL;
6803    HiOps[0] = LHSH;
6804    HiOps[1] = RHSH;
6805
6806    //cascaded check to see if any smaller size has a a carry flag.
6807    unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
6808    bool hasCarry = false;
6809    for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
6810      MVT AVT = MVT::getIntegerVT(BitSize);
6811      if (TLI.isOperationLegal(OpV, AVT)) {
6812        hasCarry = true;
6813        break;
6814      }
6815    }
6816
6817    if(hasCarry) {
6818      if (Node->getOpcode() == ISD::ADD) {
6819        Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6820        HiOps[2] = Lo.getValue(1);
6821        Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6822      } else {
6823        Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6824        HiOps[2] = Lo.getValue(1);
6825        Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6826      }
6827      break;
6828    } else {
6829      if (Node->getOpcode() == ISD::ADD) {
6830        Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2);
6831        Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2);
6832        SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
6833                                    Lo, LoOps[0], ISD::SETULT);
6834        SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
6835                                     DAG.getConstant(1, NVT),
6836                                     DAG.getConstant(0, NVT));
6837        SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
6838                                    Lo, LoOps[1], ISD::SETULT);
6839        SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
6840                                    DAG.getConstant(1, NVT),
6841                                    Carry1);
6842        Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
6843      } else {
6844        Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2);
6845        Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2);
6846        SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
6847        SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
6848                                     DAG.getConstant(1, NVT),
6849                                     DAG.getConstant(0, NVT));
6850        Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
6851      }
6852      break;
6853    }
6854  }
6855
6856  case ISD::ADDC:
6857  case ISD::SUBC: {
6858    // Expand the subcomponents.
6859    SDValue LHSL, LHSH, RHSL, RHSH;
6860    ExpandOp(Node->getOperand(0), LHSL, LHSH);
6861    ExpandOp(Node->getOperand(1), RHSL, RHSH);
6862    SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6863    SDValue LoOps[2] = { LHSL, RHSL };
6864    SDValue HiOps[3] = { LHSH, RHSH };
6865
6866    if (Node->getOpcode() == ISD::ADDC) {
6867      Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6868      HiOps[2] = Lo.getValue(1);
6869      Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6870    } else {
6871      Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6872      HiOps[2] = Lo.getValue(1);
6873      Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6874    }
6875    // Remember that we legalized the flag.
6876    AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6877    break;
6878  }
6879  case ISD::ADDE:
6880  case ISD::SUBE: {
6881    // Expand the subcomponents.
6882    SDValue LHSL, LHSH, RHSL, RHSH;
6883    ExpandOp(Node->getOperand(0), LHSL, LHSH);
6884    ExpandOp(Node->getOperand(1), RHSL, RHSH);
6885    SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6886    SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6887    SDValue HiOps[3] = { LHSH, RHSH };
6888
6889    Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6890    HiOps[2] = Lo.getValue(1);
6891    Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6892
6893    // Remember that we legalized the flag.
6894    AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6895    break;
6896  }
6897  case ISD::MUL: {
6898    // If the target wants to custom expand this, let them.
6899    if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6900      SDValue New = TLI.LowerOperation(Op, DAG);
6901      if (New.getNode()) {
6902        ExpandOp(New, Lo, Hi);
6903        break;
6904      }
6905    }
6906
6907    bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6908    bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6909    bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6910    bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6911    if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6912      SDValue LL, LH, RL, RH;
6913      ExpandOp(Node->getOperand(0), LL, LH);
6914      ExpandOp(Node->getOperand(1), RL, RH);
6915      unsigned OuterBitSize = Op.getValueSizeInBits();
6916      unsigned InnerBitSize = RH.getValueSizeInBits();
6917      unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6918      unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6919      APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6920      if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6921          DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6922        // The inputs are both zero-extended.
6923        if (HasUMUL_LOHI) {
6924          // We can emit a umul_lohi.
6925          Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6926          Hi = SDValue(Lo.getNode(), 1);
6927          break;
6928        }
6929        if (HasMULHU) {
6930          // We can emit a mulhu+mul.
6931          Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6932          Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6933          break;
6934        }
6935      }
6936      if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6937        // The input values are both sign-extended.
6938        if (HasSMUL_LOHI) {
6939          // We can emit a smul_lohi.
6940          Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6941          Hi = SDValue(Lo.getNode(), 1);
6942          break;
6943        }
6944        if (HasMULHS) {
6945          // We can emit a mulhs+mul.
6946          Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6947          Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6948          break;
6949        }
6950      }
6951      if (HasUMUL_LOHI) {
6952        // Lo,Hi = umul LHS, RHS.
6953        SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6954                                         DAG.getVTList(NVT, NVT), LL, RL);
6955        Lo = UMulLOHI;
6956        Hi = UMulLOHI.getValue(1);
6957        RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6958        LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6959        Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6960        Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6961        break;
6962      }
6963      if (HasMULHU) {
6964        Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6965        Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6966        RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6967        LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6968        Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6969        Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6970        break;
6971      }
6972    }
6973
6974    // If nothing else, we can make a libcall.
6975    Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6976    break;
6977  }
6978  case ISD::SDIV:
6979    Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6980    break;
6981  case ISD::UDIV:
6982    Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6983    break;
6984  case ISD::SREM:
6985    Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6986    break;
6987  case ISD::UREM:
6988    Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6989    break;
6990
6991  case ISD::FADD:
6992    Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6993                                        RTLIB::ADD_F64,
6994                                        RTLIB::ADD_F80,
6995                                        RTLIB::ADD_PPCF128),
6996                       Node, false, Hi);
6997    break;
6998  case ISD::FSUB:
6999    Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7000                                        RTLIB::SUB_F64,
7001                                        RTLIB::SUB_F80,
7002                                        RTLIB::SUB_PPCF128),
7003                       Node, false, Hi);
7004    break;
7005  case ISD::FMUL:
7006    Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7007                                        RTLIB::MUL_F64,
7008                                        RTLIB::MUL_F80,
7009                                        RTLIB::MUL_PPCF128),
7010                       Node, false, Hi);
7011    break;
7012  case ISD::FDIV:
7013    Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7014                                        RTLIB::DIV_F64,
7015                                        RTLIB::DIV_F80,
7016                                        RTLIB::DIV_PPCF128),
7017                       Node, false, Hi);
7018    break;
7019  case ISD::FP_EXTEND: {
7020    if (VT == MVT::ppcf128) {
7021      assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7022             Node->getOperand(0).getValueType()==MVT::f64);
7023      const uint64_t zero = 0;
7024      if (Node->getOperand(0).getValueType()==MVT::f32)
7025        Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
7026      else
7027        Hi = Node->getOperand(0);
7028      Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7029      break;
7030    }
7031    RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7032    assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7033    Lo = ExpandLibCall(LC, Node, true, Hi);
7034    break;
7035  }
7036  case ISD::FP_ROUND: {
7037    RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7038                                          VT);
7039    assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7040    Lo = ExpandLibCall(LC, Node, true, Hi);
7041    break;
7042  }
7043  case ISD::FSQRT:
7044  case ISD::FSIN:
7045  case ISD::FCOS:
7046  case ISD::FLOG:
7047  case ISD::FLOG2:
7048  case ISD::FLOG10:
7049  case ISD::FEXP:
7050  case ISD::FEXP2:
7051  case ISD::FTRUNC:
7052  case ISD::FFLOOR:
7053  case ISD::FCEIL:
7054  case ISD::FRINT:
7055  case ISD::FNEARBYINT:
7056  case ISD::FPOW:
7057  case ISD::FPOWI: {
7058    RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7059    switch(Node->getOpcode()) {
7060    case ISD::FSQRT:
7061      LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7062                        RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7063      break;
7064    case ISD::FSIN:
7065      LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7066                        RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7067      break;
7068    case ISD::FCOS:
7069      LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7070                        RTLIB::COS_F80, RTLIB::COS_PPCF128);
7071      break;
7072    case ISD::FLOG:
7073      LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7074                        RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7075      break;
7076    case ISD::FLOG2:
7077      LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7078                        RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7079      break;
7080    case ISD::FLOG10:
7081      LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7082                        RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7083      break;
7084    case ISD::FEXP:
7085      LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7086                        RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7087      break;
7088    case ISD::FEXP2:
7089      LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7090                        RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7091      break;
7092    case ISD::FTRUNC:
7093      LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7094                        RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7095      break;
7096    case ISD::FFLOOR:
7097      LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7098                        RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7099      break;
7100    case ISD::FCEIL:
7101      LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7102                        RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7103      break;
7104    case ISD::FRINT:
7105      LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7106                        RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7107      break;
7108    case ISD::FNEARBYINT:
7109      LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7110                        RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7111      break;
7112    case ISD::FPOW:
7113      LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7114                        RTLIB::POW_PPCF128);
7115      break;
7116    case ISD::FPOWI:
7117      LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7118                        RTLIB::POWI_PPCF128);
7119      break;
7120    default: assert(0 && "Unreachable!");
7121    }
7122    Lo = ExpandLibCall(LC, Node, false, Hi);
7123    break;
7124  }
7125  case ISD::FABS: {
7126    if (VT == MVT::ppcf128) {
7127      SDValue Tmp;
7128      ExpandOp(Node->getOperand(0), Lo, Tmp);
7129      Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
7130      // lo = hi==fabs(hi) ? lo : -lo;
7131      Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
7132                    Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
7133                    DAG.getCondCode(ISD::SETEQ));
7134      break;
7135    }
7136    SDValue Mask = (VT == MVT::f64)
7137      ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7138      : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7139    Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7140    Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7141    Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
7142    if (getTypeAction(NVT) == Expand)
7143      ExpandOp(Lo, Lo, Hi);
7144    break;
7145  }
7146  case ISD::FNEG: {
7147    if (VT == MVT::ppcf128) {
7148      ExpandOp(Node->getOperand(0), Lo, Hi);
7149      Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
7150      Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
7151      break;
7152    }
7153    SDValue Mask = (VT == MVT::f64)
7154      ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7155      : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7156    Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7157    Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7158    Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
7159    if (getTypeAction(NVT) == Expand)
7160      ExpandOp(Lo, Lo, Hi);
7161    break;
7162  }
7163  case ISD::FCOPYSIGN: {
7164    Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7165    if (getTypeAction(NVT) == Expand)
7166      ExpandOp(Lo, Lo, Hi);
7167    break;
7168  }
7169  case ISD::SINT_TO_FP:
7170  case ISD::UINT_TO_FP: {
7171    bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7172    MVT SrcVT = Node->getOperand(0).getValueType();
7173
7174    // Promote the operand if needed.  Do this before checking for
7175    // ppcf128 so conversions of i16 and i8 work.
7176    if (getTypeAction(SrcVT) == Promote) {
7177      SDValue Tmp = PromoteOp(Node->getOperand(0));
7178      Tmp = isSigned
7179        ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
7180                      DAG.getValueType(SrcVT))
7181        : DAG.getZeroExtendInReg(Tmp, SrcVT);
7182      Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7183      SrcVT = Node->getOperand(0).getValueType();
7184    }
7185
7186    if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7187      static const uint64_t zero = 0;
7188      if (isSigned) {
7189        Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7190                                    Node->getOperand(0)));
7191        Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7192      } else {
7193        static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7194        Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7195                                    Node->getOperand(0)));
7196        Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7197        Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7198        // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7199        ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7200                             DAG.getConstant(0, MVT::i32),
7201                             DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7202                                         DAG.getConstantFP(
7203                                            APFloat(APInt(128, 2, TwoE32)),
7204                                            MVT::ppcf128)),
7205                             Hi,
7206                             DAG.getCondCode(ISD::SETLT)),
7207                 Lo, Hi);
7208      }
7209      break;
7210    }
7211    if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7212      // si64->ppcf128 done by libcall, below
7213      static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7214      ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
7215               Lo, Hi);
7216      Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7217      // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7218      ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7219                           DAG.getConstant(0, MVT::i64),
7220                           DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7221                                       DAG.getConstantFP(
7222                                          APFloat(APInt(128, 2, TwoE64)),
7223                                          MVT::ppcf128)),
7224                           Hi,
7225                           DAG.getCondCode(ISD::SETLT)),
7226               Lo, Hi);
7227      break;
7228    }
7229
7230    Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7231                       Node->getOperand(0));
7232    if (getTypeAction(Lo.getValueType()) == Expand)
7233      // float to i32 etc. can be 'expanded' to a single node.
7234      ExpandOp(Lo, Lo, Hi);
7235    break;
7236  }
7237  }
7238
7239  // Make sure the resultant values have been legalized themselves, unless this
7240  // is a type that requires multi-step expansion.
7241  if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7242    Lo = LegalizeOp(Lo);
7243    if (Hi.getNode())
7244      // Don't legalize the high part if it is expanded to a single node.
7245      Hi = LegalizeOp(Hi);
7246  }
7247
7248  // Remember in a map if the values will be reused later.
7249  bool isNew =
7250    ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7251  assert(isNew && "Value already expanded?!?");
7252  isNew = isNew;
7253}
7254
7255/// SplitVectorOp - Given an operand of vector type, break it down into
7256/// two smaller values, still of vector type.
7257void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7258                                         SDValue &Hi) {
7259  assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7260  SDNode *Node = Op.getNode();
7261  unsigned NumElements = Op.getValueType().getVectorNumElements();
7262  assert(NumElements > 1 && "Cannot split a single element vector!");
7263
7264  MVT NewEltVT = Op.getValueType().getVectorElementType();
7265
7266  unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7267  unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7268
7269  MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7270  MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7271
7272  // See if we already split it.
7273  std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7274    = SplitNodes.find(Op);
7275  if (I != SplitNodes.end()) {
7276    Lo = I->second.first;
7277    Hi = I->second.second;
7278    return;
7279  }
7280
7281  switch (Node->getOpcode()) {
7282  default:
7283#ifndef NDEBUG
7284    Node->dump(&DAG);
7285#endif
7286    assert(0 && "Unhandled operation in SplitVectorOp!");
7287  case ISD::UNDEF:
7288    Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
7289    Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
7290    break;
7291  case ISD::BUILD_PAIR:
7292    Lo = Node->getOperand(0);
7293    Hi = Node->getOperand(1);
7294    break;
7295  case ISD::INSERT_VECTOR_ELT: {
7296    if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7297      SplitVectorOp(Node->getOperand(0), Lo, Hi);
7298      unsigned Index = Idx->getZExtValue();
7299      SDValue ScalarOp = Node->getOperand(1);
7300      if (Index < NewNumElts_Lo)
7301        Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
7302                         DAG.getIntPtrConstant(Index));
7303      else
7304        Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
7305                         DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7306      break;
7307    }
7308    SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7309                                                   Node->getOperand(1),
7310                                                   Node->getOperand(2));
7311    SplitVectorOp(Tmp, Lo, Hi);
7312    break;
7313  }
7314  case ISD::VECTOR_SHUFFLE: {
7315    // Build the low part.
7316    SDValue Mask = Node->getOperand(2);
7317    SmallVector<SDValue, 8> Ops;
7318    MVT PtrVT = TLI.getPointerTy();
7319
7320    // Insert all of the elements from the input that are needed.  We use
7321    // buildvector of extractelement here because the input vectors will have
7322    // to be legalized, so this makes the code simpler.
7323    for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7324      SDValue IdxNode = Mask.getOperand(i);
7325      if (IdxNode.getOpcode() == ISD::UNDEF) {
7326        Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7327        continue;
7328      }
7329      unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7330      SDValue InVec = Node->getOperand(0);
7331      if (Idx >= NumElements) {
7332        InVec = Node->getOperand(1);
7333        Idx -= NumElements;
7334      }
7335      Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7336                                DAG.getConstant(Idx, PtrVT)));
7337    }
7338    Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
7339    Ops.clear();
7340
7341    for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7342      SDValue IdxNode = Mask.getOperand(i);
7343      if (IdxNode.getOpcode() == ISD::UNDEF) {
7344        Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7345        continue;
7346      }
7347      unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7348      SDValue InVec = Node->getOperand(0);
7349      if (Idx >= NumElements) {
7350        InVec = Node->getOperand(1);
7351        Idx -= NumElements;
7352      }
7353      Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7354                                DAG.getConstant(Idx, PtrVT)));
7355    }
7356    Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
7357    break;
7358  }
7359  case ISD::BUILD_VECTOR: {
7360    SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7361                                    Node->op_begin()+NewNumElts_Lo);
7362    Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
7363
7364    SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7365                                    Node->op_end());
7366    Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
7367    break;
7368  }
7369  case ISD::CONCAT_VECTORS: {
7370    // FIXME: Handle non-power-of-two vectors?
7371    unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7372    if (NewNumSubvectors == 1) {
7373      Lo = Node->getOperand(0);
7374      Hi = Node->getOperand(1);
7375    } else {
7376      SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7377                                    Node->op_begin()+NewNumSubvectors);
7378      Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
7379
7380      SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7381                                      Node->op_end());
7382      Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
7383    }
7384    break;
7385  }
7386  case ISD::EXTRACT_SUBVECTOR: {
7387    SDValue Vec = Op.getOperand(0);
7388    SDValue Idx = Op.getOperand(1);
7389    MVT     IdxVT = Idx.getValueType();
7390
7391    Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Lo, Vec, Idx);
7392    ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7393    if (CIdx) {
7394      Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec,
7395                       DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7396                                       IdxVT));
7397    } else {
7398      Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
7399                        DAG.getConstant(NewNumElts_Lo, IdxVT));
7400      Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, Idx);
7401    }
7402    break;
7403  }
7404  case ISD::SELECT: {
7405    SDValue Cond = Node->getOperand(0);
7406
7407    SDValue LL, LH, RL, RH;
7408    SplitVectorOp(Node->getOperand(1), LL, LH);
7409    SplitVectorOp(Node->getOperand(2), RL, RH);
7410
7411    if (Cond.getValueType().isVector()) {
7412      // Handle a vector merge.
7413      SDValue CL, CH;
7414      SplitVectorOp(Cond, CL, CH);
7415      Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
7416      Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
7417    } else {
7418      // Handle a simple select with vector operands.
7419      Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
7420      Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
7421    }
7422    break;
7423  }
7424  case ISD::SELECT_CC: {
7425    SDValue CondLHS = Node->getOperand(0);
7426    SDValue CondRHS = Node->getOperand(1);
7427    SDValue CondCode = Node->getOperand(4);
7428
7429    SDValue LL, LH, RL, RH;
7430    SplitVectorOp(Node->getOperand(2), LL, LH);
7431    SplitVectorOp(Node->getOperand(3), RL, RH);
7432
7433    // Handle a simple select with vector operands.
7434    Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
7435                     LL, RL, CondCode);
7436    Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
7437                     LH, RH, CondCode);
7438    break;
7439  }
7440  case ISD::VSETCC: {
7441    SDValue LL, LH, RL, RH;
7442    SplitVectorOp(Node->getOperand(0), LL, LH);
7443    SplitVectorOp(Node->getOperand(1), RL, RH);
7444    Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
7445    Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
7446    break;
7447  }
7448  case ISD::ADD:
7449  case ISD::SUB:
7450  case ISD::MUL:
7451  case ISD::FADD:
7452  case ISD::FSUB:
7453  case ISD::FMUL:
7454  case ISD::SDIV:
7455  case ISD::UDIV:
7456  case ISD::FDIV:
7457  case ISD::FPOW:
7458  case ISD::AND:
7459  case ISD::OR:
7460  case ISD::XOR:
7461  case ISD::UREM:
7462  case ISD::SREM:
7463  case ISD::FREM: {
7464    SDValue LL, LH, RL, RH;
7465    SplitVectorOp(Node->getOperand(0), LL, LH);
7466    SplitVectorOp(Node->getOperand(1), RL, RH);
7467
7468    Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
7469    Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
7470    break;
7471  }
7472  case ISD::FP_ROUND:
7473  case ISD::FPOWI: {
7474    SDValue L, H;
7475    SplitVectorOp(Node->getOperand(0), L, H);
7476
7477    Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
7478    Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
7479    break;
7480  }
7481  case ISD::CTTZ:
7482  case ISD::CTLZ:
7483  case ISD::CTPOP:
7484  case ISD::FNEG:
7485  case ISD::FABS:
7486  case ISD::FSQRT:
7487  case ISD::FSIN:
7488  case ISD::FCOS:
7489  case ISD::FLOG:
7490  case ISD::FLOG2:
7491  case ISD::FLOG10:
7492  case ISD::FEXP:
7493  case ISD::FEXP2:
7494  case ISD::FP_TO_SINT:
7495  case ISD::FP_TO_UINT:
7496  case ISD::SINT_TO_FP:
7497  case ISD::UINT_TO_FP:
7498  case ISD::TRUNCATE:
7499  case ISD::ANY_EXTEND:
7500  case ISD::SIGN_EXTEND:
7501  case ISD::ZERO_EXTEND:
7502  case ISD::FP_EXTEND: {
7503    SDValue L, H;
7504    SplitVectorOp(Node->getOperand(0), L, H);
7505
7506    Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
7507    Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
7508    break;
7509  }
7510  case ISD::CONVERT_RNDSAT: {
7511    ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7512    SDValue L, H;
7513    SplitVectorOp(Node->getOperand(0), L, H);
7514    SDValue DTyOpL =  DAG.getValueType(NewVT_Lo);
7515    SDValue DTyOpH =  DAG.getValueType(NewVT_Hi);
7516    SDValue STyOpL =  DAG.getValueType(L.getValueType());
7517    SDValue STyOpH =  DAG.getValueType(H.getValueType());
7518
7519    SDValue RndOp = Node->getOperand(3);
7520    SDValue SatOp = Node->getOperand(4);
7521
7522    Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL,
7523                              RndOp, SatOp, CvtCode);
7524    Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH,
7525                              RndOp, SatOp, CvtCode);
7526    break;
7527  }
7528  case ISD::LOAD: {
7529    LoadSDNode *LD = cast<LoadSDNode>(Node);
7530    SDValue Ch = LD->getChain();
7531    SDValue Ptr = LD->getBasePtr();
7532    ISD::LoadExtType ExtType = LD->getExtensionType();
7533    const Value *SV = LD->getSrcValue();
7534    int SVOffset = LD->getSrcValueOffset();
7535    MVT MemoryVT = LD->getMemoryVT();
7536    unsigned Alignment = LD->getAlignment();
7537    bool isVolatile = LD->isVolatile();
7538
7539    assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7540    SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7541
7542    MVT MemNewEltVT = MemoryVT.getVectorElementType();
7543    MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7544    MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7545
7546    Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
7547                     NewVT_Lo, Ch, Ptr, Offset,
7548                     SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7549    unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7550    Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
7551                      DAG.getIntPtrConstant(IncrementSize));
7552    SVOffset += IncrementSize;
7553    Alignment = MinAlign(Alignment, IncrementSize);
7554    Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
7555                     NewVT_Hi, Ch, Ptr, Offset,
7556                     SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7557
7558    // Build a factor node to remember that this load is independent of the
7559    // other one.
7560    SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
7561                               Hi.getValue(1));
7562
7563    // Remember that we legalized the chain.
7564    AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7565    break;
7566  }
7567  case ISD::BIT_CONVERT: {
7568    // We know the result is a vector.  The input may be either a vector or a
7569    // scalar value.
7570    SDValue InOp = Node->getOperand(0);
7571    if (!InOp.getValueType().isVector() ||
7572        InOp.getValueType().getVectorNumElements() == 1) {
7573      // The input is a scalar or single-element vector.
7574      // Lower to a store/load so that it can be split.
7575      // FIXME: this could be improved probably.
7576      unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7577                                            Op.getValueType().getTypeForMVT());
7578      SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7579      int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7580
7581      SDValue St = DAG.getStore(DAG.getEntryNode(),
7582                                  InOp, Ptr,
7583                                  PseudoSourceValue::getFixedStack(FI), 0);
7584      InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7585                         PseudoSourceValue::getFixedStack(FI), 0);
7586    }
7587    // Split the vector and convert each of the pieces now.
7588    SplitVectorOp(InOp, Lo, Hi);
7589    Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7590    Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7591    break;
7592  }
7593  }
7594
7595  // Remember in a map if the values will be reused later.
7596  bool isNew =
7597    SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7598  assert(isNew && "Value already split?!?");
7599  isNew = isNew;
7600}
7601
7602
7603/// ScalarizeVectorOp - Given an operand of single-element vector type
7604/// (e.g. v1f32), convert it into the equivalent operation that returns a
7605/// scalar (e.g. f32) value.
7606SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7607  assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7608  SDNode *Node = Op.getNode();
7609  MVT NewVT = Op.getValueType().getVectorElementType();
7610  assert(Op.getValueType().getVectorNumElements() == 1);
7611
7612  // See if we already scalarized it.
7613  std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7614  if (I != ScalarizedNodes.end()) return I->second;
7615
7616  SDValue Result;
7617  switch (Node->getOpcode()) {
7618  default:
7619#ifndef NDEBUG
7620    Node->dump(&DAG); cerr << "\n";
7621#endif
7622    assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7623  case ISD::ADD:
7624  case ISD::FADD:
7625  case ISD::SUB:
7626  case ISD::FSUB:
7627  case ISD::MUL:
7628  case ISD::FMUL:
7629  case ISD::SDIV:
7630  case ISD::UDIV:
7631  case ISD::FDIV:
7632  case ISD::SREM:
7633  case ISD::UREM:
7634  case ISD::FREM:
7635  case ISD::FPOW:
7636  case ISD::AND:
7637  case ISD::OR:
7638  case ISD::XOR:
7639    Result = DAG.getNode(Node->getOpcode(),
7640                         NewVT,
7641                         ScalarizeVectorOp(Node->getOperand(0)),
7642                         ScalarizeVectorOp(Node->getOperand(1)));
7643    break;
7644  case ISD::FNEG:
7645  case ISD::FABS:
7646  case ISD::FSQRT:
7647  case ISD::FSIN:
7648  case ISD::FCOS:
7649  case ISD::FLOG:
7650  case ISD::FLOG2:
7651  case ISD::FLOG10:
7652  case ISD::FEXP:
7653  case ISD::FEXP2:
7654  case ISD::FP_TO_SINT:
7655  case ISD::FP_TO_UINT:
7656  case ISD::SINT_TO_FP:
7657  case ISD::UINT_TO_FP:
7658  case ISD::SIGN_EXTEND:
7659  case ISD::ZERO_EXTEND:
7660  case ISD::ANY_EXTEND:
7661  case ISD::TRUNCATE:
7662  case ISD::FP_EXTEND:
7663    Result = DAG.getNode(Node->getOpcode(),
7664                         NewVT,
7665                         ScalarizeVectorOp(Node->getOperand(0)));
7666    break;
7667  case ISD::CONVERT_RNDSAT: {
7668    SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7669    Result = DAG.getConvertRndSat(NewVT, Op0,
7670                                  DAG.getValueType(NewVT),
7671                                  DAG.getValueType(Op0.getValueType()),
7672                                  Node->getOperand(3),
7673                                  Node->getOperand(4),
7674                                  cast<CvtRndSatSDNode>(Node)->getCvtCode());
7675    break;
7676  }
7677  case ISD::FPOWI:
7678  case ISD::FP_ROUND:
7679    Result = DAG.getNode(Node->getOpcode(),
7680                         NewVT,
7681                         ScalarizeVectorOp(Node->getOperand(0)),
7682                         Node->getOperand(1));
7683    break;
7684  case ISD::LOAD: {
7685    LoadSDNode *LD = cast<LoadSDNode>(Node);
7686    SDValue Ch = LegalizeOp(LD->getChain());     // Legalize the chain.
7687    SDValue Ptr = LegalizeOp(LD->getBasePtr());  // Legalize the pointer.
7688    ISD::LoadExtType ExtType = LD->getExtensionType();
7689    const Value *SV = LD->getSrcValue();
7690    int SVOffset = LD->getSrcValueOffset();
7691    MVT MemoryVT = LD->getMemoryVT();
7692    unsigned Alignment = LD->getAlignment();
7693    bool isVolatile = LD->isVolatile();
7694
7695    assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7696    SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7697
7698    Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7699                         NewVT, Ch, Ptr, Offset, SV, SVOffset,
7700                         MemoryVT.getVectorElementType(),
7701                         isVolatile, Alignment);
7702
7703    // Remember that we legalized the chain.
7704    AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7705    break;
7706  }
7707  case ISD::BUILD_VECTOR:
7708    Result = Node->getOperand(0);
7709    break;
7710  case ISD::INSERT_VECTOR_ELT:
7711    // Returning the inserted scalar element.
7712    Result = Node->getOperand(1);
7713    break;
7714  case ISD::CONCAT_VECTORS:
7715    assert(Node->getOperand(0).getValueType() == NewVT &&
7716           "Concat of non-legal vectors not yet supported!");
7717    Result = Node->getOperand(0);
7718    break;
7719  case ISD::VECTOR_SHUFFLE: {
7720    // Figure out if the scalar is the LHS or RHS and return it.
7721    SDValue EltNum = Node->getOperand(2).getOperand(0);
7722    if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7723      Result = ScalarizeVectorOp(Node->getOperand(1));
7724    else
7725      Result = ScalarizeVectorOp(Node->getOperand(0));
7726    break;
7727  }
7728  case ISD::EXTRACT_SUBVECTOR:
7729    Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, Node->getOperand(0),
7730                         Node->getOperand(1));
7731    break;
7732  case ISD::BIT_CONVERT: {
7733    SDValue Op0 = Op.getOperand(0);
7734    if (Op0.getValueType().getVectorNumElements() == 1)
7735      Op0 = ScalarizeVectorOp(Op0);
7736    Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7737    break;
7738  }
7739  case ISD::SELECT:
7740    Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7741                         ScalarizeVectorOp(Op.getOperand(1)),
7742                         ScalarizeVectorOp(Op.getOperand(2)));
7743    break;
7744  case ISD::SELECT_CC:
7745    Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7746                         Node->getOperand(1),
7747                         ScalarizeVectorOp(Op.getOperand(2)),
7748                         ScalarizeVectorOp(Op.getOperand(3)),
7749                         Node->getOperand(4));
7750    break;
7751  case ISD::VSETCC: {
7752    SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7753    SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7754    Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7755                         Op.getOperand(2));
7756    Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7757                         DAG.getConstant(-1ULL, NewVT),
7758                         DAG.getConstant(0ULL, NewVT));
7759    break;
7760  }
7761  }
7762
7763  if (TLI.isTypeLegal(NewVT))
7764    Result = LegalizeOp(Result);
7765  bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7766  assert(isNew && "Value already scalarized?");
7767  isNew = isNew;
7768  return Result;
7769}
7770
7771
7772SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
7773  std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
7774  if (I != WidenNodes.end()) return I->second;
7775
7776  MVT VT = Op.getValueType();
7777  assert(VT.isVector() && "Cannot widen non-vector type!");
7778
7779  SDValue Result;
7780  SDNode *Node = Op.getNode();
7781  MVT EVT = VT.getVectorElementType();
7782
7783  unsigned NumElts = VT.getVectorNumElements();
7784  unsigned NewNumElts = WidenVT.getVectorNumElements();
7785  assert(NewNumElts > NumElts  && "Cannot widen to smaller type!");
7786  assert(NewNumElts < 17);
7787
7788  // When widen is called, it is assumed that it is more efficient to use a
7789  // wide type.  The default action is to widen to operation to a wider legal
7790  // vector type and then do the operation if it is legal by calling LegalizeOp
7791  // again.  If there is no vector equivalent, we will unroll the operation, do
7792  // it, and rebuild the vector.  If most of the operations are vectorizible to
7793  // the legal type, the resulting code will be more efficient.  If this is not
7794  // the case, the resulting code will preform badly as we end up generating
7795  // code to pack/unpack the results. It is the function that calls widen
7796  // that is responsible for seeing this doesn't happen.
7797  switch (Node->getOpcode()) {
7798  default:
7799#ifndef NDEBUG
7800      Node->dump(&DAG);
7801#endif
7802      assert(0 && "Unexpected operation in WidenVectorOp!");
7803      break;
7804  case ISD::CopyFromReg:
7805    assert(0 && "CopyFromReg doesn't need widening!");
7806  case ISD::Constant:
7807  case ISD::ConstantFP:
7808    // To build a vector of these elements, clients should call BuildVector
7809    // and with each element instead of creating a node with a vector type
7810    assert(0 && "Unexpected operation in WidenVectorOp!");
7811  case ISD::VAARG:
7812    // Variable Arguments with vector types doesn't make any sense to me
7813    assert(0 && "Unexpected operation in WidenVectorOp!");
7814    break;
7815  case ISD::UNDEF:
7816    Result = DAG.getNode(ISD::UNDEF, WidenVT);
7817    break;
7818  case ISD::BUILD_VECTOR: {
7819    // Build a vector with undefined for the new nodes
7820    SDValueVector NewOps(Node->op_begin(), Node->op_end());
7821    for (unsigned i = NumElts; i < NewNumElts; ++i) {
7822      NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT));
7823    }
7824    Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size());
7825    break;
7826  }
7827  case ISD::INSERT_VECTOR_ELT: {
7828    SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7829    Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1,
7830                         Node->getOperand(1), Node->getOperand(2));
7831    break;
7832  }
7833  case ISD::VECTOR_SHUFFLE: {
7834    SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7835    SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
7836    // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
7837    // used as permutation array. We build the vector here instead of widening
7838    // because we don't want to legalize and have it turned to something else.
7839    SDValue PermOp = Node->getOperand(2);
7840    SDValueVector NewOps;
7841    MVT PVT = PermOp.getValueType().getVectorElementType();
7842    for (unsigned i = 0; i < NumElts; ++i) {
7843      if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
7844        NewOps.push_back(PermOp.getOperand(i));
7845      } else {
7846        unsigned Idx =
7847        cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
7848        if (Idx < NumElts) {
7849          NewOps.push_back(PermOp.getOperand(i));
7850        }
7851        else {
7852          NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
7853                                           PermOp.getOperand(i).getValueType()));
7854        }
7855      }
7856    }
7857    for (unsigned i = NumElts; i < NewNumElts; ++i) {
7858      NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT));
7859    }
7860
7861    SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR,
7862                               MVT::getVectorVT(PVT, NewOps.size()),
7863                               &NewOps[0], NewOps.size());
7864
7865    Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3);
7866    break;
7867  }
7868  case ISD::LOAD: {
7869    // If the load widen returns true, we can use a single load for the
7870    // vector.  Otherwise, it is returning a token factor for multiple
7871    // loads.
7872    SDValue TFOp;
7873    if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
7874      AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
7875    else
7876      AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
7877    break;
7878  }
7879
7880  case ISD::BIT_CONVERT: {
7881    SDValue Tmp1 = Node->getOperand(0);
7882    // Converts between two different types so we need to determine
7883    // the correct widen type for the input operand.
7884    MVT TVT = Tmp1.getValueType();
7885    assert(TVT.isVector() && "can not widen non vector type");
7886    MVT TEVT = TVT.getVectorElementType();
7887    assert(WidenVT.getSizeInBits() % EVT.getSizeInBits() == 0 &&
7888         "can not widen bit bit convert that are not multiple of element type");
7889    MVT TWidenVT =  MVT::getVectorVT(TEVT,
7890                                   WidenVT.getSizeInBits()/EVT.getSizeInBits());
7891    Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
7892    assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
7893    Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
7894
7895    TargetLowering::LegalizeAction action =
7896      TLI.getOperationAction(Node->getOpcode(), WidenVT);
7897    switch (action)  {
7898    default: assert(0 && "action not supported");
7899    case TargetLowering::Legal:
7900        break;
7901    case TargetLowering::Promote:
7902        // We defer the promotion to when we legalize the op
7903      break;
7904    case TargetLowering::Expand:
7905      // Expand the operation into a bunch of nasty scalar code.
7906      Result = LegalizeOp(UnrollVectorOp(Result));
7907      break;
7908    }
7909    break;
7910  }
7911
7912  case ISD::SINT_TO_FP:
7913  case ISD::UINT_TO_FP:
7914  case ISD::FP_TO_SINT:
7915  case ISD::FP_TO_UINT: {
7916    SDValue Tmp1 = Node->getOperand(0);
7917    // Converts between two different types so we need to determine
7918    // the correct widen type for the input operand.
7919    MVT TVT = Tmp1.getValueType();
7920    assert(TVT.isVector() && "can not widen non vector type");
7921    MVT TEVT = TVT.getVectorElementType();
7922    MVT TWidenVT =  MVT::getVectorVT(TEVT, NewNumElts);
7923    Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
7924    assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
7925    Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
7926
7927    TargetLowering::LegalizeAction action =
7928      TLI.getOperationAction(Node->getOpcode(), WidenVT);
7929    switch (action)  {
7930    default: assert(0 && "action not supported");
7931    case TargetLowering::Legal:
7932        break;
7933    case TargetLowering::Promote:
7934        // We defer the promotion to when we legalize the op
7935      break;
7936    case TargetLowering::Expand:
7937      // Expand the operation into a bunch of nasty scalar code.
7938      Result = LegalizeOp(UnrollVectorOp(Result));
7939      break;
7940    }
7941    break;
7942  }
7943
7944  case ISD::FP_EXTEND:
7945    assert(0 && "Case not implemented.  Dynamically dead with 2 FP types!");
7946  case ISD::TRUNCATE:
7947  case ISD::SIGN_EXTEND:
7948  case ISD::ZERO_EXTEND:
7949  case ISD::ANY_EXTEND:
7950  case ISD::FP_ROUND:
7951  case ISD::SIGN_EXTEND_INREG:
7952  case ISD::FABS:
7953  case ISD::FNEG:
7954  case ISD::FSQRT:
7955  case ISD::FSIN:
7956  case ISD::FCOS:
7957  case ISD::CTPOP:
7958  case ISD::CTTZ:
7959  case ISD::CTLZ: {
7960    // Unary op widening
7961    SDValue Tmp1;
7962    TargetLowering::LegalizeAction action =
7963      TLI.getOperationAction(Node->getOpcode(), WidenVT);
7964
7965    Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7966    assert(Tmp1.getValueType() == WidenVT);
7967    Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
7968    switch (action)  {
7969    default: assert(0 && "action not supported");
7970    case TargetLowering::Legal:
7971        break;
7972    case TargetLowering::Promote:
7973        // We defer the promotion to when we legalize the op
7974      break;
7975    case TargetLowering::Expand:
7976      // Expand the operation into a bunch of nasty scalar code.
7977      Result = LegalizeOp(UnrollVectorOp(Result));
7978      break;
7979    }
7980    break;
7981  }
7982  case ISD::CONVERT_RNDSAT: {
7983    SDValue RndOp = Node->getOperand(3);
7984    SDValue SatOp = Node->getOperand(4);
7985
7986    TargetLowering::LegalizeAction action =
7987      TLI.getOperationAction(Node->getOpcode(), WidenVT);
7988
7989    SDValue SrcOp = Node->getOperand(0);
7990
7991    // Converts between two different types so we need to determine
7992    // the correct widen type for the input operand.
7993    MVT SVT = SrcOp.getValueType();
7994    assert(SVT.isVector() && "can not widen non vector type");
7995    MVT SEVT = SVT.getVectorElementType();
7996    MVT SWidenVT =  MVT::getVectorVT(SEVT, NewNumElts);
7997
7998    SrcOp = WidenVectorOp(SrcOp, SWidenVT);
7999    assert(SrcOp.getValueType() == WidenVT);
8000    SDValue DTyOp = DAG.getValueType(WidenVT);
8001    SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8002    ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8003
8004    Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp,
8005                                  RndOp, SatOp, CvtCode);
8006    switch (action)  {
8007    default: assert(0 && "action not supported");
8008    case TargetLowering::Legal:
8009      break;
8010    case TargetLowering::Promote:
8011      // We defer the promotion to when we legalize the op
8012      break;
8013    case TargetLowering::Expand:
8014      // Expand the operation into a bunch of nasty scalar code.
8015      Result = LegalizeOp(UnrollVectorOp(Result));
8016      break;
8017    }
8018    break;
8019  }
8020  case ISD::FPOW:
8021  case ISD::FPOWI:
8022  case ISD::ADD:
8023  case ISD::SUB:
8024  case ISD::MUL:
8025  case ISD::MULHS:
8026  case ISD::MULHU:
8027  case ISD::AND:
8028  case ISD::OR:
8029  case ISD::XOR:
8030  case ISD::FADD:
8031  case ISD::FSUB:
8032  case ISD::FMUL:
8033  case ISD::SDIV:
8034  case ISD::SREM:
8035  case ISD::FDIV:
8036  case ISD::FREM:
8037  case ISD::FCOPYSIGN:
8038  case ISD::UDIV:
8039  case ISD::UREM:
8040  case ISD::BSWAP: {
8041    // Binary op widening
8042    TargetLowering::LegalizeAction action =
8043      TLI.getOperationAction(Node->getOpcode(), WidenVT);
8044
8045    SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8046    SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8047    assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8048    Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2);
8049    switch (action)  {
8050    default: assert(0 && "action not supported");
8051    case TargetLowering::Legal:
8052      break;
8053    case TargetLowering::Promote:
8054      // We defer the promotion to when we legalize the op
8055      break;
8056    case TargetLowering::Expand:
8057      // Expand the operation into a bunch of nasty scalar code by first
8058      // Widening to the right type and then unroll the beast.
8059      Result = LegalizeOp(UnrollVectorOp(Result));
8060      break;
8061    }
8062    break;
8063  }
8064
8065  case ISD::SHL:
8066  case ISD::SRA:
8067  case ISD::SRL: {
8068    // Binary op with one non vector operand
8069    TargetLowering::LegalizeAction action =
8070      TLI.getOperationAction(Node->getOpcode(), WidenVT);
8071
8072    SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8073    assert(Tmp1.getValueType() == WidenVT);
8074    Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Node->getOperand(1));
8075    switch (action)  {
8076    default: assert(0 && "action not supported");
8077    case TargetLowering::Legal:
8078      break;
8079    case TargetLowering::Promote:
8080       // We defer the promotion to when we legalize the op
8081      break;
8082    case TargetLowering::Expand:
8083      // Expand the operation into a bunch of nasty scalar code.
8084      Result = LegalizeOp(UnrollVectorOp(Result));
8085      break;
8086    }
8087    break;
8088  }
8089  case ISD::EXTRACT_VECTOR_ELT: {
8090    SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8091    assert(Tmp1.getValueType() == WidenVT);
8092    Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1));
8093    break;
8094  }
8095  case ISD::CONCAT_VECTORS: {
8096    // We concurrently support only widen on a multiple of the incoming vector.
8097    // We could widen on a multiple of the incoming operand if necessary.
8098    unsigned NumConcat = NewNumElts / NumElts;
8099    assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8100    std::vector<SDValue> UnOps(NumElts, DAG.getNode(ISD::UNDEF,
8101                               VT.getVectorElementType()));
8102    SDValue UndefVal = DAG.getNode(ISD::BUILD_VECTOR, VT,
8103                                   &UnOps[0], UnOps.size());
8104    SmallVector<SDValue, 8> MOps;
8105    MOps.push_back(Op);
8106    for (unsigned i = 1; i != NumConcat; ++i) {
8107      MOps.push_back(UndefVal);
8108    }
8109    Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8110                                    &MOps[0], MOps.size()));
8111    break;
8112  }
8113  case ISD::EXTRACT_SUBVECTOR: {
8114    SDValue Tmp1 = Node->getOperand(0);
8115    SDValue Idx = Node->getOperand(1);
8116    ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8117    if (CIdx && CIdx->getZExtValue() == 0) {
8118      // Since we are access the start of the vector, the incoming
8119      // vector type might be the proper.
8120      MVT Tmp1VT = Tmp1.getValueType();
8121      if (Tmp1VT == WidenVT)
8122        return Tmp1;
8123      else {
8124        unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8125        if (Tmp1VTNumElts < NewNumElts)
8126          Result = WidenVectorOp(Tmp1, WidenVT);
8127        else
8128          Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, Tmp1, Idx);
8129      }
8130    } else if (NewNumElts % NumElts == 0) {
8131      // Widen the extracted subvector.
8132      unsigned NumConcat = NewNumElts / NumElts;
8133      SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
8134      SmallVector<SDValue, 8> MOps;
8135      MOps.push_back(Op);
8136      for (unsigned i = 1; i != NumConcat; ++i) {
8137        MOps.push_back(UndefVal);
8138      }
8139      Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8140                                      &MOps[0], MOps.size()));
8141    } else {
8142      assert(0 && "can not widen extract subvector");
8143     // This could be implemented using insert and build vector but I would
8144     // like to see when this happens.
8145    }
8146    break;
8147  }
8148
8149  case ISD::SELECT: {
8150    TargetLowering::LegalizeAction action =
8151      TLI.getOperationAction(Node->getOpcode(), WidenVT);
8152
8153    // Determine new condition widen type and widen
8154    SDValue Cond1 = Node->getOperand(0);
8155    MVT CondVT = Cond1.getValueType();
8156    assert(CondVT.isVector() && "can not widen non vector type");
8157    MVT CondEVT = CondVT.getVectorElementType();
8158    MVT CondWidenVT =  MVT::getVectorVT(CondEVT, NewNumElts);
8159    Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8160    assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8161
8162    SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8163    SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8164    assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8165    Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2);
8166    switch (action)  {
8167    default: assert(0 && "action not supported");
8168    case TargetLowering::Legal:
8169      break;
8170    case TargetLowering::Promote:
8171      // We defer the promotion to when we legalize the op
8172      break;
8173    case TargetLowering::Expand:
8174      // Expand the operation into a bunch of nasty scalar code by first
8175      // Widening to the right type and then unroll the beast.
8176      Result = LegalizeOp(UnrollVectorOp(Result));
8177      break;
8178    }
8179    break;
8180  }
8181
8182  case ISD::SELECT_CC: {
8183    TargetLowering::LegalizeAction action =
8184      TLI.getOperationAction(Node->getOpcode(), WidenVT);
8185
8186    // Determine new condition widen type and widen
8187    SDValue Cond1 = Node->getOperand(0);
8188    SDValue Cond2 = Node->getOperand(1);
8189    MVT CondVT = Cond1.getValueType();
8190    assert(CondVT.isVector() && "can not widen non vector type");
8191    assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8192    MVT CondEVT = CondVT.getVectorElementType();
8193    MVT CondWidenVT =  MVT::getVectorVT(CondEVT, NewNumElts);
8194    Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8195    Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8196    assert(Cond1.getValueType() == CondWidenVT &&
8197           Cond2.getValueType() == CondWidenVT && "condition not widen");
8198
8199    SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8200    SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8201    assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8202           "operands not widen");
8203    Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1,
8204                         Tmp2, Node->getOperand(4));
8205    switch (action)  {
8206    default: assert(0 && "action not supported");
8207    case TargetLowering::Legal:
8208      break;
8209    case TargetLowering::Promote:
8210      // We defer the promotion to when we legalize the op
8211      break;
8212    case TargetLowering::Expand:
8213      // Expand the operation into a bunch of nasty scalar code by first
8214      // Widening to the right type and then unroll the beast.
8215      Result = LegalizeOp(UnrollVectorOp(Result));
8216      break;
8217    }
8218    break;
8219  }
8220  case ISD::VSETCC: {
8221    // Determine widen for the operand
8222    SDValue Tmp1 = Node->getOperand(0);
8223    MVT TmpVT = Tmp1.getValueType();
8224    assert(TmpVT.isVector() && "can not widen non vector type");
8225    MVT TmpEVT = TmpVT.getVectorElementType();
8226    MVT TmpWidenVT =  MVT::getVectorVT(TmpEVT, NewNumElts);
8227    Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8228    SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8229    Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2,
8230                         Node->getOperand(2));
8231    break;
8232  }
8233  case ISD::ATOMIC_CMP_SWAP_8:
8234  case ISD::ATOMIC_CMP_SWAP_16:
8235  case ISD::ATOMIC_CMP_SWAP_32:
8236  case ISD::ATOMIC_CMP_SWAP_64:
8237  case ISD::ATOMIC_LOAD_ADD_8:
8238  case ISD::ATOMIC_LOAD_SUB_8:
8239  case ISD::ATOMIC_LOAD_AND_8:
8240  case ISD::ATOMIC_LOAD_OR_8:
8241  case ISD::ATOMIC_LOAD_XOR_8:
8242  case ISD::ATOMIC_LOAD_NAND_8:
8243  case ISD::ATOMIC_LOAD_MIN_8:
8244  case ISD::ATOMIC_LOAD_MAX_8:
8245  case ISD::ATOMIC_LOAD_UMIN_8:
8246  case ISD::ATOMIC_LOAD_UMAX_8:
8247  case ISD::ATOMIC_SWAP_8:
8248  case ISD::ATOMIC_LOAD_ADD_16:
8249  case ISD::ATOMIC_LOAD_SUB_16:
8250  case ISD::ATOMIC_LOAD_AND_16:
8251  case ISD::ATOMIC_LOAD_OR_16:
8252  case ISD::ATOMIC_LOAD_XOR_16:
8253  case ISD::ATOMIC_LOAD_NAND_16:
8254  case ISD::ATOMIC_LOAD_MIN_16:
8255  case ISD::ATOMIC_LOAD_MAX_16:
8256  case ISD::ATOMIC_LOAD_UMIN_16:
8257  case ISD::ATOMIC_LOAD_UMAX_16:
8258  case ISD::ATOMIC_SWAP_16:
8259  case ISD::ATOMIC_LOAD_ADD_32:
8260  case ISD::ATOMIC_LOAD_SUB_32:
8261  case ISD::ATOMIC_LOAD_AND_32:
8262  case ISD::ATOMIC_LOAD_OR_32:
8263  case ISD::ATOMIC_LOAD_XOR_32:
8264  case ISD::ATOMIC_LOAD_NAND_32:
8265  case ISD::ATOMIC_LOAD_MIN_32:
8266  case ISD::ATOMIC_LOAD_MAX_32:
8267  case ISD::ATOMIC_LOAD_UMIN_32:
8268  case ISD::ATOMIC_LOAD_UMAX_32:
8269  case ISD::ATOMIC_SWAP_32:
8270  case ISD::ATOMIC_LOAD_ADD_64:
8271  case ISD::ATOMIC_LOAD_SUB_64:
8272  case ISD::ATOMIC_LOAD_AND_64:
8273  case ISD::ATOMIC_LOAD_OR_64:
8274  case ISD::ATOMIC_LOAD_XOR_64:
8275  case ISD::ATOMIC_LOAD_NAND_64:
8276  case ISD::ATOMIC_LOAD_MIN_64:
8277  case ISD::ATOMIC_LOAD_MAX_64:
8278  case ISD::ATOMIC_LOAD_UMIN_64:
8279  case ISD::ATOMIC_LOAD_UMAX_64:
8280  case ISD::ATOMIC_SWAP_64: {
8281    // For now, we assume that using vectors for these operations don't make
8282    // much sense so we just split it.  We return an empty result
8283    SDValue X, Y;
8284    SplitVectorOp(Op, X, Y);
8285    return Result;
8286    break;
8287  }
8288
8289  } // end switch (Node->getOpcode())
8290
8291  assert(Result.getNode() && "Didn't set a result!");
8292  if (Result != Op)
8293    Result = LegalizeOp(Result);
8294
8295  AddWidenedOperand(Op, Result);
8296  return Result;
8297}
8298
8299// Utility function to find a legal vector type and its associated element
8300// type from a preferred width and whose vector type must be the same size
8301// as the VVT.
8302//  TLI:   Target lowering used to determine legal types
8303//  Width: Preferred width of element type
8304//  VVT:   Vector value type whose size we must match.
8305// Returns VecEVT and EVT - the vector type and its associated element type
8306static void FindWidenVecType(TargetLowering &TLI, unsigned Width, MVT VVT,
8307                             MVT& EVT, MVT& VecEVT) {
8308  // We start with the preferred width, make it a power of 2 and see if
8309  // we can find a vector type of that width. If not, we reduce it by
8310  // another power of 2.  If we have widen the type, a vector of bytes should
8311  // always be legal.
8312  assert(TLI.isTypeLegal(VVT));
8313  unsigned EWidth = Width + 1;
8314  do {
8315    assert(EWidth > 0);
8316    EWidth =  (1 << Log2_32(EWidth-1));
8317    EVT = MVT::getIntegerVT(EWidth);
8318    unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8319    VecEVT = MVT::getVectorVT(EVT, NumEVT);
8320  } while (!TLI.isTypeLegal(VecEVT) ||
8321           VVT.getSizeInBits() != VecEVT.getSizeInBits());
8322}
8323
8324SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8325                                                    SDValue   Chain,
8326                                                    SDValue   BasePtr,
8327                                                    const Value *SV,
8328                                                    int         SVOffset,
8329                                                    unsigned    Alignment,
8330                                                    bool        isVolatile,
8331                                                    unsigned    LdWidth,
8332                                                    MVT         ResType) {
8333  // We assume that we have good rules to handle loading power of two loads so
8334  // we break down the operations to power of 2 loads.  The strategy is to
8335  // load the largest power of 2 that we can easily transform to a legal vector
8336  // and then insert into that vector, and the cast the result into the legal
8337  // vector that we want.  This avoids unnecessary stack converts.
8338  // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8339  //       the load is nonvolatile, we an use a wider load for the value.
8340  // Find a vector length we can load a large chunk
8341  MVT EVT, VecEVT;
8342  unsigned EVTWidth;
8343  FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8344  EVTWidth = EVT.getSizeInBits();
8345
8346  SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset,
8347                               isVolatile, Alignment);
8348  SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp);
8349  LdChain.push_back(LdOp.getValue(1));
8350
8351  // Check if we can load the element with one instruction
8352  if (LdWidth == EVTWidth) {
8353    return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8354  }
8355
8356  // The vector element order is endianness dependent.
8357  unsigned Idx = 1;
8358  LdWidth -= EVTWidth;
8359  unsigned Offset = 0;
8360
8361  while (LdWidth > 0) {
8362    unsigned Increment = EVTWidth / 8;
8363    Offset += Increment;
8364    BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8365                          DAG.getIntPtrConstant(Increment));
8366
8367    if (LdWidth < EVTWidth) {
8368      // Our current type we are using is too large, use a smaller size by
8369      // using a smaller power of 2
8370      unsigned oEVTWidth = EVTWidth;
8371      FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8372      EVTWidth = EVT.getSizeInBits();
8373      // Readjust position and vector position based on new load type
8374      Idx = Idx * (oEVTWidth/EVTWidth);
8375      VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8376    }
8377
8378    SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV,
8379                                 SVOffset+Offset, isVolatile,
8380                                 MinAlign(Alignment, Offset));
8381    LdChain.push_back(LdOp.getValue(1));
8382    VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp,
8383                        DAG.getIntPtrConstant(Idx++));
8384
8385    LdWidth -= EVTWidth;
8386  }
8387
8388  return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8389}
8390
8391bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8392                                             SDValue& TFOp,
8393                                             SDValue Op,
8394                                             MVT NVT) {
8395  // TODO: Add support for ConcatVec and the ability to load many vector
8396  //       types (e.g., v4i8).  This will not work when a vector register
8397  //       to memory mapping is strange (e.g., vector elements are not
8398  //       stored in some sequential order).
8399
8400  // It must be true that the widen vector type is bigger than where
8401  // we need to load from.
8402  LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8403  MVT LdVT = LD->getMemoryVT();
8404  assert(LdVT.isVector() && NVT.isVector());
8405  assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8406
8407  // Load information
8408  SDValue Chain = LD->getChain();
8409  SDValue BasePtr = LD->getBasePtr();
8410  int       SVOffset = LD->getSrcValueOffset();
8411  unsigned  Alignment = LD->getAlignment();
8412  bool      isVolatile = LD->isVolatile();
8413  const Value *SV = LD->getSrcValue();
8414  unsigned int LdWidth = LdVT.getSizeInBits();
8415
8416  // Load value as a large register
8417  SDValueVector LdChain;
8418  Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8419                               Alignment, isVolatile, LdWidth, NVT);
8420
8421  if (LdChain.size() == 1) {
8422    TFOp = LdChain[0];
8423    return true;
8424  }
8425  else {
8426    TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size());
8427    return false;
8428  }
8429}
8430
8431
8432void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8433                                                SDValue   Chain,
8434                                                SDValue   BasePtr,
8435                                                const Value *SV,
8436                                                int         SVOffset,
8437                                                unsigned    Alignment,
8438                                                bool        isVolatile,
8439                                                SDValue     ValOp,
8440                                                unsigned    StWidth) {
8441  // Breaks the stores into a series of power of 2 width stores.  For any
8442  // width, we convert the vector to the vector of element size that we
8443  // want to store.  This avoids requiring a stack convert.
8444
8445  // Find a width of the element type we can store with
8446  MVT VVT = ValOp.getValueType();
8447  MVT EVT, VecEVT;
8448  unsigned EVTWidth;
8449  FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8450  EVTWidth = EVT.getSizeInBits();
8451
8452  SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp);
8453  SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8454                            DAG.getIntPtrConstant(0));
8455  SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset,
8456                               isVolatile, Alignment);
8457  StChain.push_back(StOp);
8458
8459  // Check if we are done
8460  if (StWidth == EVTWidth) {
8461    return;
8462  }
8463
8464  unsigned Idx = 1;
8465  StWidth -= EVTWidth;
8466  unsigned Offset = 0;
8467
8468  while (StWidth > 0) {
8469    unsigned Increment = EVTWidth / 8;
8470    Offset += Increment;
8471    BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8472                          DAG.getIntPtrConstant(Increment));
8473
8474    if (StWidth < EVTWidth) {
8475      // Our current type we are using is too large, use a smaller size by
8476      // using a smaller power of 2
8477      unsigned oEVTWidth = EVTWidth;
8478      FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8479      EVTWidth = EVT.getSizeInBits();
8480      // Readjust position and vector position based on new load type
8481      Idx = Idx * (oEVTWidth/EVTWidth);
8482      VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8483    }
8484
8485    EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8486                      DAG.getIntPtrConstant(Idx++));
8487    StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV,
8488                                   SVOffset + Offset, isVolatile,
8489                                   MinAlign(Alignment, Offset)));
8490    StWidth -= EVTWidth;
8491  }
8492}
8493
8494
8495SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8496                                                   SDValue Chain,
8497                                                   SDValue BasePtr) {
8498  // TODO: It might be cleaner if we can use SplitVector and have more legal
8499  //        vector types that can be stored into memory (e.g., v4xi8 can
8500  //        be stored as a word). This will not work when a vector register
8501  //        to memory mapping is strange (e.g., vector elements are not
8502  //        stored in some sequential order).
8503
8504  MVT StVT = ST->getMemoryVT();
8505  SDValue ValOp = ST->getValue();
8506
8507  // Check if we have widen this node with another value
8508  std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8509  if (I != WidenNodes.end())
8510    ValOp = I->second;
8511
8512  MVT VVT = ValOp.getValueType();
8513
8514  // It must be true that we the widen vector type is bigger than where
8515  // we need to store.
8516  assert(StVT.isVector() && VVT.isVector());
8517  assert(StVT.getSizeInBits() < VVT.getSizeInBits());
8518  assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8519
8520  // Store value
8521  SDValueVector StChain;
8522  genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8523                       ST->getSrcValueOffset(), ST->getAlignment(),
8524                       ST->isVolatile(), ValOp, StVT.getSizeInBits());
8525  if (StChain.size() == 1)
8526    return StChain[0];
8527  else
8528    return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size());
8529}
8530
8531
8532// SelectionDAG::Legalize - This is the entry point for the file.
8533//
8534void SelectionDAG::Legalize() {
8535  /// run - This is the main entry point to this class.
8536  ///
8537  SelectionDAGLegalize(*this).LegalizeDAG();
8538}
8539
8540