LegalizeDAG.cpp revision 9b583b49103f21888ac3de3f7941a98a63a23aea
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineConstantPool.h" 16#include "llvm/CodeGen/MachineFunction.h" 17#include "llvm/CodeGen/MachineFrameInfo.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/Constants.h" 22#include <iostream> 23using namespace llvm; 24 25//===----------------------------------------------------------------------===// 26/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 27/// hacks on it until the target machine can handle it. This involves 28/// eliminating value sizes the machine cannot handle (promoting small sizes to 29/// large sizes or splitting up large values into small values) as well as 30/// eliminating operations the machine cannot handle. 31/// 32/// This code also does a small amount of optimization and recognition of idioms 33/// as part of its processing. For example, if a target does not support a 34/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 35/// will attempt merge setcc and brc instructions into brcc's. 36/// 37namespace { 38class SelectionDAGLegalize { 39 TargetLowering &TLI; 40 SelectionDAG &DAG; 41 42 /// LegalizeAction - This enum indicates what action we should take for each 43 /// value type the can occur in the program. 44 enum LegalizeAction { 45 Legal, // The target natively supports this value type. 46 Promote, // This should be promoted to the next larger type. 47 Expand, // This integer type should be broken into smaller pieces. 48 }; 49 50 /// ValueTypeActions - This is a bitvector that contains two bits for each 51 /// value type, where the two bits correspond to the LegalizeAction enum. 52 /// This can be queried with "getTypeAction(VT)". 53 unsigned ValueTypeActions; 54 55 /// NeedsAnotherIteration - This is set when we expand a large integer 56 /// operation into smaller integer operations, but the smaller operations are 57 /// not set. This occurs only rarely in practice, for targets that don't have 58 /// 32-bit or larger integer registers. 59 bool NeedsAnotherIteration; 60 61 /// LegalizedNodes - For nodes that are of legal width, and that have more 62 /// than one use, this map indicates what regularized operand to use. This 63 /// allows us to avoid legalizing the same thing more than once. 64 std::map<SDOperand, SDOperand> LegalizedNodes; 65 66 /// PromotedNodes - For nodes that are below legal width, and that have more 67 /// than one use, this map indicates what promoted value to use. This allows 68 /// us to avoid promoting the same thing more than once. 69 std::map<SDOperand, SDOperand> PromotedNodes; 70 71 /// ExpandedNodes - For nodes that need to be expanded, and which have more 72 /// than one use, this map indicates which which operands are the expanded 73 /// version of the input. This allows us to avoid expanding the same node 74 /// more than once. 75 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 76 77 void AddLegalizedOperand(SDOperand From, SDOperand To) { 78 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second; 79 assert(isNew && "Got into the map somehow?"); 80 } 81 void AddPromotedOperand(SDOperand From, SDOperand To) { 82 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 83 assert(isNew && "Got into the map somehow?"); 84 } 85 86public: 87 88 SelectionDAGLegalize(SelectionDAG &DAG); 89 90 /// Run - While there is still lowering to do, perform a pass over the DAG. 91 /// Most regularization can be done in a single pass, but targets that require 92 /// large values to be split into registers multiple times (e.g. i64 -> 4x 93 /// i16) require iteration for these values (the first iteration will demote 94 /// to i32, the second will demote to i16). 95 void Run() { 96 do { 97 NeedsAnotherIteration = false; 98 LegalizeDAG(); 99 } while (NeedsAnotherIteration); 100 } 101 102 /// getTypeAction - Return how we should legalize values of this type, either 103 /// it is already legal or we need to expand it into multiple registers of 104 /// smaller integer type, or we need to promote it to a larger type. 105 LegalizeAction getTypeAction(MVT::ValueType VT) const { 106 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 107 } 108 109 /// isTypeLegal - Return true if this type is legal on this target. 110 /// 111 bool isTypeLegal(MVT::ValueType VT) const { 112 return getTypeAction(VT) == Legal; 113 } 114 115private: 116 void LegalizeDAG(); 117 118 SDOperand LegalizeOp(SDOperand O); 119 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 120 SDOperand PromoteOp(SDOperand O); 121 122 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 123 SDOperand &Hi); 124 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 125 SDOperand Source); 126 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 127 SDOperand &Lo, SDOperand &Hi); 128 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 129 SDOperand &Lo, SDOperand &Hi); 130 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 131 SDOperand &Lo, SDOperand &Hi); 132 133 SDOperand getIntPtrConstant(uint64_t Val) { 134 return DAG.getConstant(Val, TLI.getPointerTy()); 135 } 136}; 137} 138 139 140SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 141 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 142 ValueTypeActions(TLI.getValueTypeActions()) { 143 assert(MVT::LAST_VALUETYPE <= 16 && 144 "Too many value types for ValueTypeActions to hold!"); 145} 146 147void SelectionDAGLegalize::LegalizeDAG() { 148 SDOperand OldRoot = DAG.getRoot(); 149 SDOperand NewRoot = LegalizeOp(OldRoot); 150 DAG.setRoot(NewRoot); 151 152 ExpandedNodes.clear(); 153 LegalizedNodes.clear(); 154 PromotedNodes.clear(); 155 156 // Remove dead nodes now. 157 DAG.RemoveDeadNodes(OldRoot.Val); 158} 159 160SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 161 assert(getTypeAction(Op.getValueType()) == Legal && 162 "Caller should expand or promote operands that are not legal!"); 163 164 // If this operation defines any values that cannot be represented in a 165 // register on this target, make sure to expand or promote them. 166 if (Op.Val->getNumValues() > 1) { 167 for (unsigned i = 0, e = Op.Val->getNumValues(); i != e; ++i) 168 switch (getTypeAction(Op.Val->getValueType(i))) { 169 case Legal: break; // Nothing to do. 170 case Expand: { 171 SDOperand T1, T2; 172 ExpandOp(Op.getValue(i), T1, T2); 173 assert(LegalizedNodes.count(Op) && 174 "Expansion didn't add legal operands!"); 175 return LegalizedNodes[Op]; 176 } 177 case Promote: 178 PromoteOp(Op.getValue(i)); 179 assert(LegalizedNodes.count(Op) && 180 "Expansion didn't add legal operands!"); 181 return LegalizedNodes[Op]; 182 } 183 } 184 185 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 186 if (I != LegalizedNodes.end()) return I->second; 187 188 SDOperand Tmp1, Tmp2, Tmp3; 189 190 SDOperand Result = Op; 191 SDNode *Node = Op.Val; 192 193 switch (Node->getOpcode()) { 194 default: 195 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 196 assert(0 && "Do not know how to legalize this operator!"); 197 abort(); 198 case ISD::EntryToken: 199 case ISD::FrameIndex: 200 case ISD::GlobalAddress: 201 case ISD::ExternalSymbol: 202 case ISD::ConstantPool: // Nothing to do. 203 assert(getTypeAction(Node->getValueType(0)) == Legal && 204 "This must be legal!"); 205 break; 206 case ISD::CopyFromReg: 207 Tmp1 = LegalizeOp(Node->getOperand(0)); 208 if (Tmp1 != Node->getOperand(0)) 209 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), 210 Node->getValueType(0), Tmp1); 211 else 212 Result = Op.getValue(0); 213 214 // Since CopyFromReg produces two values, make sure to remember that we 215 // legalized both of them. 216 AddLegalizedOperand(Op.getValue(0), Result); 217 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 218 return Result.getValue(Op.ResNo); 219 case ISD::ImplicitDef: 220 Tmp1 = LegalizeOp(Node->getOperand(0)); 221 if (Tmp1 != Node->getOperand(0)) 222 Result = DAG.getImplicitDef(Tmp1, cast<RegSDNode>(Node)->getReg()); 223 break; 224 case ISD::UNDEF: { 225 MVT::ValueType VT = Op.getValueType(); 226 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 227 default: assert(0 && "This action is not supported yet!"); 228 case TargetLowering::Expand: 229 case TargetLowering::Promote: 230 if (MVT::isInteger(VT)) 231 Result = DAG.getConstant(0, VT); 232 else if (MVT::isFloatingPoint(VT)) 233 Result = DAG.getConstantFP(0, VT); 234 else 235 assert(0 && "Unknown value type!"); 236 break; 237 case TargetLowering::Legal: 238 break; 239 } 240 break; 241 } 242 case ISD::Constant: 243 // We know we don't need to expand constants here, constants only have one 244 // value and we check that it is fine above. 245 246 // FIXME: Maybe we should handle things like targets that don't support full 247 // 32-bit immediates? 248 break; 249 case ISD::ConstantFP: { 250 // Spill FP immediates to the constant pool if the target cannot directly 251 // codegen them. Targets often have some immediate values that can be 252 // efficiently generated into an FP register without a load. We explicitly 253 // leave these constants as ConstantFP nodes for the target to deal with. 254 255 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 256 257 // Check to see if this FP immediate is already legal. 258 bool isLegal = false; 259 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 260 E = TLI.legal_fpimm_end(); I != E; ++I) 261 if (CFP->isExactlyValue(*I)) { 262 isLegal = true; 263 break; 264 } 265 266 if (!isLegal) { 267 // Otherwise we need to spill the constant to memory. 268 MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool(); 269 270 bool Extend = false; 271 272 // If a FP immediate is precise when represented as a float, we put it 273 // into the constant pool as a float, even if it's is statically typed 274 // as a double. 275 MVT::ValueType VT = CFP->getValueType(0); 276 bool isDouble = VT == MVT::f64; 277 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 278 Type::FloatTy, CFP->getValue()); 279 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 280 // Only do this if the target has a native EXTLOAD instruction from 281 // f32. 282 TLI.getOperationAction(ISD::EXTLOAD, 283 MVT::f32) == TargetLowering::Legal) { 284 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 285 VT = MVT::f32; 286 Extend = true; 287 } 288 289 SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(LLVMC), 290 TLI.getPointerTy()); 291 if (Extend) { 292 Result = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), CPIdx, 293 DAG.getSrcValue(NULL), MVT::f32); 294 } else { 295 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 296 DAG.getSrcValue(NULL)); 297 } 298 } 299 break; 300 } 301 case ISD::TokenFactor: { 302 std::vector<SDOperand> Ops; 303 bool Changed = false; 304 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 305 SDOperand Op = Node->getOperand(i); 306 // Fold single-use TokenFactor nodes into this token factor as we go. 307 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 308 Changed = true; 309 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 310 Ops.push_back(LegalizeOp(Op.getOperand(j))); 311 } else { 312 Ops.push_back(LegalizeOp(Op)); // Legalize the operands 313 Changed |= Ops[i] != Op; 314 } 315 } 316 if (Changed) 317 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 318 break; 319 } 320 321 case ISD::ADJCALLSTACKDOWN: 322 case ISD::ADJCALLSTACKUP: 323 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 324 // There is no need to legalize the size argument (Operand #1) 325 if (Tmp1 != Node->getOperand(0)) 326 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 327 Node->getOperand(1)); 328 break; 329 case ISD::DYNAMIC_STACKALLOC: 330 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 331 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 332 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 333 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 334 Tmp3 != Node->getOperand(2)) 335 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, Node->getValueType(0), 336 Tmp1, Tmp2, Tmp3); 337 else 338 Result = Op.getValue(0); 339 340 // Since this op produces two values, make sure to remember that we 341 // legalized both of them. 342 AddLegalizedOperand(SDOperand(Node, 0), Result); 343 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 344 return Result.getValue(Op.ResNo); 345 346 case ISD::CALL: { 347 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 348 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 349 350 bool Changed = false; 351 std::vector<SDOperand> Ops; 352 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 353 Ops.push_back(LegalizeOp(Node->getOperand(i))); 354 Changed |= Ops.back() != Node->getOperand(i); 355 } 356 357 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 358 std::vector<MVT::ValueType> RetTyVTs; 359 RetTyVTs.reserve(Node->getNumValues()); 360 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 361 RetTyVTs.push_back(Node->getValueType(i)); 362 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops), 0); 363 } else { 364 Result = Result.getValue(0); 365 } 366 // Since calls produce multiple values, make sure to remember that we 367 // legalized all of them. 368 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 369 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 370 return Result.getValue(Op.ResNo); 371 } 372 case ISD::BR: 373 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 374 if (Tmp1 != Node->getOperand(0)) 375 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 376 break; 377 378 case ISD::BRCOND: 379 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 380 381 switch (getTypeAction(Node->getOperand(1).getValueType())) { 382 case Expand: assert(0 && "It's impossible to expand bools"); 383 case Legal: 384 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 385 break; 386 case Promote: 387 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 388 break; 389 } 390 // Basic block destination (Op#2) is always legal. 391 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 392 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 393 Node->getOperand(2)); 394 break; 395 case ISD::BRCONDTWOWAY: 396 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 397 switch (getTypeAction(Node->getOperand(1).getValueType())) { 398 case Expand: assert(0 && "It's impossible to expand bools"); 399 case Legal: 400 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 401 break; 402 case Promote: 403 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 404 break; 405 } 406 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 407 // pair. 408 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 409 case TargetLowering::Promote: 410 default: assert(0 && "This action is not supported yet!"); 411 case TargetLowering::Legal: 412 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 413 std::vector<SDOperand> Ops; 414 Ops.push_back(Tmp1); 415 Ops.push_back(Tmp2); 416 Ops.push_back(Node->getOperand(2)); 417 Ops.push_back(Node->getOperand(3)); 418 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 419 } 420 break; 421 case TargetLowering::Expand: 422 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 423 Node->getOperand(2)); 424 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 425 break; 426 } 427 break; 428 429 case ISD::LOAD: 430 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 431 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 432 433 if (Tmp1 != Node->getOperand(0) || 434 Tmp2 != Node->getOperand(1)) 435 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, 436 Node->getOperand(2)); 437 else 438 Result = SDOperand(Node, 0); 439 440 // Since loads produce two values, make sure to remember that we legalized 441 // both of them. 442 AddLegalizedOperand(SDOperand(Node, 0), Result); 443 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 444 return Result.getValue(Op.ResNo); 445 446 case ISD::EXTLOAD: 447 case ISD::SEXTLOAD: 448 case ISD::ZEXTLOAD: { 449 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 450 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 451 452 MVT::ValueType SrcVT = cast<MVTSDNode>(Node)->getExtraValueType(); 453 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 454 default: assert(0 && "This action is not supported yet!"); 455 case TargetLowering::Promote: 456 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 457 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), 458 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 459 // Since loads produce two values, make sure to remember that we legalized 460 // both of them. 461 AddLegalizedOperand(SDOperand(Node, 0), Result); 462 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 463 return Result.getValue(Op.ResNo); 464 465 case TargetLowering::Legal: 466 if (Tmp1 != Node->getOperand(0) || 467 Tmp2 != Node->getOperand(1)) 468 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), 469 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 470 else 471 Result = SDOperand(Node, 0); 472 473 // Since loads produce two values, make sure to remember that we legalized 474 // both of them. 475 AddLegalizedOperand(SDOperand(Node, 0), Result); 476 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 477 return Result.getValue(Op.ResNo); 478 case TargetLowering::Expand: 479 assert(Node->getOpcode() != ISD::EXTLOAD && 480 "EXTLOAD should always be supported!"); 481 // Turn the unsupported load into an EXTLOAD followed by an explicit 482 // zero/sign extend inreg. 483 Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0), 484 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 485 SDOperand ValRes; 486 if (Node->getOpcode() == ISD::SEXTLOAD) 487 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 488 Result, SrcVT); 489 else 490 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 491 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 492 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 493 if (Op.ResNo) 494 return Result.getValue(1); 495 return ValRes; 496 } 497 assert(0 && "Unreachable"); 498 } 499 case ISD::EXTRACT_ELEMENT: 500 // Get both the low and high parts. 501 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 502 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 503 Result = Tmp2; // 1 -> Hi 504 else 505 Result = Tmp1; // 0 -> Lo 506 break; 507 508 case ISD::CopyToReg: 509 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 510 511 switch (getTypeAction(Node->getOperand(1).getValueType())) { 512 case Legal: 513 // Legalize the incoming value (must be legal). 514 Tmp2 = LegalizeOp(Node->getOperand(1)); 515 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 516 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg()); 517 break; 518 case Promote: 519 Tmp2 = PromoteOp(Node->getOperand(1)); 520 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg()); 521 break; 522 case Expand: 523 SDOperand Lo, Hi; 524 ExpandOp(Node->getOperand(1), Lo, Hi); 525 unsigned Reg = cast<RegSDNode>(Node)->getReg(); 526 Lo = DAG.getCopyToReg(Tmp1, Lo, Reg); 527 Hi = DAG.getCopyToReg(Tmp1, Hi, Reg+1); 528 // Note that the copytoreg nodes are independent of each other. 529 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 530 assert(isTypeLegal(Result.getValueType()) && 531 "Cannot expand multiple times yet (i64 -> i16)"); 532 break; 533 } 534 break; 535 536 case ISD::RET: 537 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 538 switch (Node->getNumOperands()) { 539 case 2: // ret val 540 switch (getTypeAction(Node->getOperand(1).getValueType())) { 541 case Legal: 542 Tmp2 = LegalizeOp(Node->getOperand(1)); 543 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 544 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 545 break; 546 case Expand: { 547 SDOperand Lo, Hi; 548 ExpandOp(Node->getOperand(1), Lo, Hi); 549 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 550 break; 551 } 552 case Promote: 553 Tmp2 = PromoteOp(Node->getOperand(1)); 554 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 555 break; 556 } 557 break; 558 case 1: // ret void 559 if (Tmp1 != Node->getOperand(0)) 560 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 561 break; 562 default: { // ret <values> 563 std::vector<SDOperand> NewValues; 564 NewValues.push_back(Tmp1); 565 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 566 switch (getTypeAction(Node->getOperand(i).getValueType())) { 567 case Legal: 568 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 569 break; 570 case Expand: { 571 SDOperand Lo, Hi; 572 ExpandOp(Node->getOperand(i), Lo, Hi); 573 NewValues.push_back(Lo); 574 NewValues.push_back(Hi); 575 break; 576 } 577 case Promote: 578 assert(0 && "Can't promote multiple return value yet!"); 579 } 580 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 581 break; 582 } 583 } 584 break; 585 case ISD::STORE: 586 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 587 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 588 589 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 590 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 591 if (CFP->getValueType(0) == MVT::f32) { 592 union { 593 unsigned I; 594 float F; 595 } V; 596 V.F = CFP->getValue(); 597 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 598 DAG.getConstant(V.I, MVT::i32), Tmp2, 599 Node->getOperand(3)); 600 } else { 601 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 602 union { 603 uint64_t I; 604 double F; 605 } V; 606 V.F = CFP->getValue(); 607 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 608 DAG.getConstant(V.I, MVT::i64), Tmp2, 609 Node->getOperand(3)); 610 } 611 Node = Result.Val; 612 } 613 614 switch (getTypeAction(Node->getOperand(1).getValueType())) { 615 case Legal: { 616 SDOperand Val = LegalizeOp(Node->getOperand(1)); 617 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 618 Tmp2 != Node->getOperand(2)) 619 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 620 Node->getOperand(3)); 621 break; 622 } 623 case Promote: 624 // Truncate the value and store the result. 625 Tmp3 = PromoteOp(Node->getOperand(1)); 626 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 627 Node->getOperand(3), 628 Node->getOperand(1).getValueType()); 629 break; 630 631 case Expand: 632 SDOperand Lo, Hi; 633 ExpandOp(Node->getOperand(1), Lo, Hi); 634 635 if (!TLI.isLittleEndian()) 636 std::swap(Lo, Hi); 637 638 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 639 Node->getOperand(3)); 640 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 641 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 642 getIntPtrConstant(IncrementSize)); 643 assert(isTypeLegal(Tmp2.getValueType()) && 644 "Pointers must be legal!"); 645 //Again, claiming both parts of the store came form the same Instr 646 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 647 Node->getOperand(3)); 648 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 649 break; 650 } 651 break; 652 case ISD::PCMARKER: 653 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 654 if (Tmp1 != Node->getOperand(0)) 655 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 656 break; 657 case ISD::TRUNCSTORE: 658 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 659 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 660 661 switch (getTypeAction(Node->getOperand(1).getValueType())) { 662 case Legal: 663 Tmp2 = LegalizeOp(Node->getOperand(1)); 664 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 665 Tmp3 != Node->getOperand(2)) 666 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 667 Node->getOperand(3), 668 cast<MVTSDNode>(Node)->getExtraValueType()); 669 break; 670 case Promote: 671 case Expand: 672 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 673 } 674 break; 675 case ISD::SELECT: 676 switch (getTypeAction(Node->getOperand(0).getValueType())) { 677 case Expand: assert(0 && "It's impossible to expand bools"); 678 case Legal: 679 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 680 break; 681 case Promote: 682 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 683 break; 684 } 685 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 686 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 687 688 switch (TLI.getOperationAction(Node->getOpcode(), Tmp2.getValueType())) { 689 default: assert(0 && "This action is not supported yet!"); 690 case TargetLowering::Legal: 691 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 692 Tmp3 != Node->getOperand(2)) 693 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 694 Tmp1, Tmp2, Tmp3); 695 break; 696 case TargetLowering::Promote: { 697 MVT::ValueType NVT = 698 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 699 unsigned ExtOp, TruncOp; 700 if (MVT::isInteger(Tmp2.getValueType())) { 701 ExtOp = ISD::ZERO_EXTEND; 702 TruncOp = ISD::TRUNCATE; 703 } else { 704 ExtOp = ISD::FP_EXTEND; 705 TruncOp = ISD::FP_ROUND; 706 } 707 // Promote each of the values to the new type. 708 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 709 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 710 // Perform the larger operation, then round down. 711 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 712 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 713 break; 714 } 715 } 716 break; 717 case ISD::SETCC: 718 switch (getTypeAction(Node->getOperand(0).getValueType())) { 719 case Legal: 720 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 721 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 722 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 723 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 724 Node->getValueType(0), Tmp1, Tmp2); 725 break; 726 case Promote: 727 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 728 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 729 730 // If this is an FP compare, the operands have already been extended. 731 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 732 MVT::ValueType VT = Node->getOperand(0).getValueType(); 733 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 734 735 // Otherwise, we have to insert explicit sign or zero extends. Note 736 // that we could insert sign extends for ALL conditions, but zero extend 737 // is cheaper on many machines (an AND instead of two shifts), so prefer 738 // it. 739 switch (cast<SetCCSDNode>(Node)->getCondition()) { 740 default: assert(0 && "Unknown integer comparison!"); 741 case ISD::SETEQ: 742 case ISD::SETNE: 743 case ISD::SETUGE: 744 case ISD::SETUGT: 745 case ISD::SETULE: 746 case ISD::SETULT: 747 // ALL of these operations will work if we either sign or zero extend 748 // the operands (including the unsigned comparisons!). Zero extend is 749 // usually a simpler/cheaper operation, so prefer it. 750 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 751 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 752 break; 753 case ISD::SETGE: 754 case ISD::SETGT: 755 case ISD::SETLT: 756 case ISD::SETLE: 757 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 758 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT); 759 break; 760 } 761 762 } 763 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 764 Node->getValueType(0), Tmp1, Tmp2); 765 break; 766 case Expand: 767 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 768 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 769 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 770 switch (cast<SetCCSDNode>(Node)->getCondition()) { 771 case ISD::SETEQ: 772 case ISD::SETNE: 773 if (RHSLo == RHSHi) 774 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 775 if (RHSCST->isAllOnesValue()) { 776 // Comparison to -1. 777 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 778 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 779 Node->getValueType(0), Tmp1, RHSLo); 780 break; 781 } 782 783 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 784 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 785 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 786 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 787 Node->getValueType(0), Tmp1, 788 DAG.getConstant(0, Tmp1.getValueType())); 789 break; 790 default: 791 // If this is a comparison of the sign bit, just look at the top part. 792 // X > -1, x < 0 793 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 794 if ((cast<SetCCSDNode>(Node)->getCondition() == ISD::SETLT && 795 CST->getValue() == 0) || // X < 0 796 (cast<SetCCSDNode>(Node)->getCondition() == ISD::SETGT && 797 (CST->isAllOnesValue()))) // X > -1 798 return DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 799 Node->getValueType(0), LHSHi, RHSHi); 800 801 // FIXME: This generated code sucks. 802 ISD::CondCode LowCC; 803 switch (cast<SetCCSDNode>(Node)->getCondition()) { 804 default: assert(0 && "Unknown integer setcc!"); 805 case ISD::SETLT: 806 case ISD::SETULT: LowCC = ISD::SETULT; break; 807 case ISD::SETGT: 808 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 809 case ISD::SETLE: 810 case ISD::SETULE: LowCC = ISD::SETULE; break; 811 case ISD::SETGE: 812 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 813 } 814 815 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 816 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 817 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 818 819 // NOTE: on targets without efficient SELECT of bools, we can always use 820 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 821 Tmp1 = DAG.getSetCC(LowCC, Node->getValueType(0), LHSLo, RHSLo); 822 Tmp2 = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 823 Node->getValueType(0), LHSHi, RHSHi); 824 Result = DAG.getSetCC(ISD::SETEQ, Node->getValueType(0), LHSHi, RHSHi); 825 Result = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 826 Result, Tmp1, Tmp2); 827 break; 828 } 829 } 830 break; 831 832 case ISD::MEMSET: 833 case ISD::MEMCPY: 834 case ISD::MEMMOVE: { 835 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 836 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 837 838 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 839 switch (getTypeAction(Node->getOperand(2).getValueType())) { 840 case Expand: assert(0 && "Cannot expand a byte!"); 841 case Legal: 842 Tmp3 = LegalizeOp(Node->getOperand(2)); 843 break; 844 case Promote: 845 Tmp3 = PromoteOp(Node->getOperand(2)); 846 break; 847 } 848 } else { 849 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 850 } 851 852 SDOperand Tmp4; 853 switch (getTypeAction(Node->getOperand(3).getValueType())) { 854 case Expand: assert(0 && "Cannot expand this yet!"); 855 case Legal: 856 Tmp4 = LegalizeOp(Node->getOperand(3)); 857 break; 858 case Promote: 859 Tmp4 = PromoteOp(Node->getOperand(3)); 860 break; 861 } 862 863 SDOperand Tmp5; 864 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 865 case Expand: assert(0 && "Cannot expand this yet!"); 866 case Legal: 867 Tmp5 = LegalizeOp(Node->getOperand(4)); 868 break; 869 case Promote: 870 Tmp5 = PromoteOp(Node->getOperand(4)); 871 break; 872 } 873 874 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 875 default: assert(0 && "This action not implemented for this operation!"); 876 case TargetLowering::Legal: 877 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 878 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 879 Tmp5 != Node->getOperand(4)) { 880 std::vector<SDOperand> Ops; 881 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 882 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 883 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 884 } 885 break; 886 case TargetLowering::Expand: { 887 // Otherwise, the target does not support this operation. Lower the 888 // operation to an explicit libcall as appropriate. 889 MVT::ValueType IntPtr = TLI.getPointerTy(); 890 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 891 std::vector<std::pair<SDOperand, const Type*> > Args; 892 893 const char *FnName = 0; 894 if (Node->getOpcode() == ISD::MEMSET) { 895 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 896 // Extend the ubyte argument to be an int value for the call. 897 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 898 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 899 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 900 901 FnName = "memset"; 902 } else if (Node->getOpcode() == ISD::MEMCPY || 903 Node->getOpcode() == ISD::MEMMOVE) { 904 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 905 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 906 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 907 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 908 } else { 909 assert(0 && "Unknown op!"); 910 } 911 std::pair<SDOperand,SDOperand> CallResult = 912 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, 913 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 914 Result = LegalizeOp(CallResult.second); 915 break; 916 } 917 case TargetLowering::Custom: 918 std::vector<SDOperand> Ops; 919 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 920 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 921 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 922 Result = TLI.LowerOperation(Result); 923 Result = LegalizeOp(Result); 924 break; 925 } 926 break; 927 } 928 929 case ISD::READPORT: 930 Tmp1 = LegalizeOp(Node->getOperand(0)); 931 Tmp2 = LegalizeOp(Node->getOperand(1)); 932 933 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 934 Result = DAG.getNode(ISD::READPORT, Node->getValueType(0), Tmp1, Tmp2); 935 else 936 Result = SDOperand(Node, 0); 937 // Since these produce two values, make sure to remember that we legalized 938 // both of them. 939 AddLegalizedOperand(SDOperand(Node, 0), Result); 940 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 941 return Result.getValue(Op.ResNo); 942 case ISD::WRITEPORT: 943 Tmp1 = LegalizeOp(Node->getOperand(0)); 944 Tmp2 = LegalizeOp(Node->getOperand(1)); 945 Tmp3 = LegalizeOp(Node->getOperand(2)); 946 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 947 Tmp3 != Node->getOperand(2)) 948 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 949 break; 950 951 case ISD::READIO: 952 Tmp1 = LegalizeOp(Node->getOperand(0)); 953 Tmp2 = LegalizeOp(Node->getOperand(1)); 954 955 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 956 case TargetLowering::Custom: 957 default: assert(0 && "This action not implemented for this operation!"); 958 case TargetLowering::Legal: 959 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 960 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), 961 Tmp1, Tmp2); 962 else 963 Result = SDOperand(Node, 0); 964 break; 965 case TargetLowering::Expand: 966 // Replace this with a load from memory. 967 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 968 Node->getOperand(1), DAG.getSrcValue(NULL)); 969 Result = LegalizeOp(Result); 970 break; 971 } 972 973 // Since these produce two values, make sure to remember that we legalized 974 // both of them. 975 AddLegalizedOperand(SDOperand(Node, 0), Result); 976 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 977 return Result.getValue(Op.ResNo); 978 979 case ISD::WRITEIO: 980 Tmp1 = LegalizeOp(Node->getOperand(0)); 981 Tmp2 = LegalizeOp(Node->getOperand(1)); 982 Tmp3 = LegalizeOp(Node->getOperand(2)); 983 984 switch (TLI.getOperationAction(Node->getOpcode(), 985 Node->getOperand(1).getValueType())) { 986 case TargetLowering::Custom: 987 default: assert(0 && "This action not implemented for this operation!"); 988 case TargetLowering::Legal: 989 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 990 Tmp3 != Node->getOperand(2)) 991 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 992 break; 993 case TargetLowering::Expand: 994 // Replace this with a store to memory. 995 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 996 Node->getOperand(1), Node->getOperand(2), 997 DAG.getSrcValue(NULL)); 998 Result = LegalizeOp(Result); 999 break; 1000 } 1001 break; 1002 1003 case ISD::ADD_PARTS: 1004 case ISD::SUB_PARTS: 1005 case ISD::SHL_PARTS: 1006 case ISD::SRA_PARTS: 1007 case ISD::SRL_PARTS: { 1008 std::vector<SDOperand> Ops; 1009 bool Changed = false; 1010 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1011 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1012 Changed |= Ops.back() != Node->getOperand(i); 1013 } 1014 if (Changed) 1015 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 1016 1017 // Since these produce multiple values, make sure to remember that we 1018 // legalized all of them. 1019 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1020 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1021 return Result.getValue(Op.ResNo); 1022 } 1023 1024 // Binary operators 1025 case ISD::ADD: 1026 case ISD::SUB: 1027 case ISD::MUL: 1028 case ISD::MULHS: 1029 case ISD::MULHU: 1030 case ISD::UDIV: 1031 case ISD::SDIV: 1032 case ISD::AND: 1033 case ISD::OR: 1034 case ISD::XOR: 1035 case ISD::SHL: 1036 case ISD::SRL: 1037 case ISD::SRA: 1038 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1039 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1040 if (Tmp1 != Node->getOperand(0) || 1041 Tmp2 != Node->getOperand(1)) 1042 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 1043 break; 1044 1045 case ISD::UREM: 1046 case ISD::SREM: 1047 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1048 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1049 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1050 case TargetLowering::Legal: 1051 if (Tmp1 != Node->getOperand(0) || 1052 Tmp2 != Node->getOperand(1)) 1053 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1054 Tmp2); 1055 break; 1056 case TargetLowering::Promote: 1057 case TargetLowering::Custom: 1058 assert(0 && "Cannot promote/custom handle this yet!"); 1059 case TargetLowering::Expand: { 1060 MVT::ValueType VT = Node->getValueType(0); 1061 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 1062 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 1063 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 1064 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 1065 } 1066 break; 1067 } 1068 break; 1069 1070 case ISD::CTPOP: 1071 case ISD::CTTZ: 1072 case ISD::CTLZ: 1073 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1074 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1075 case TargetLowering::Legal: 1076 if (Tmp1 != Node->getOperand(0)) 1077 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1078 break; 1079 case TargetLowering::Promote: { 1080 MVT::ValueType OVT = Tmp1.getValueType(); 1081 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1082 1083 // Zero extend the argument. 1084 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1085 // Perform the larger operation, then subtract if needed. 1086 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1087 switch(Node->getOpcode()) 1088 { 1089 case ISD::CTPOP: 1090 Result = Tmp1; 1091 break; 1092 case ISD::CTTZ: 1093 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 1094 Tmp2 = DAG.getSetCC(ISD::SETEQ, MVT::i1, Tmp1, 1095 DAG.getConstant(getSizeInBits(NVT), NVT)); 1096 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 1097 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 1098 break; 1099 case ISD::CTLZ: 1100 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 1101 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 1102 DAG.getConstant(getSizeInBits(NVT) - 1103 getSizeInBits(OVT), NVT)); 1104 break; 1105 } 1106 break; 1107 } 1108 case TargetLowering::Custom: 1109 assert(0 && "Cannot custom handle this yet!"); 1110 case TargetLowering::Expand: 1111 switch(Node->getOpcode()) 1112 { 1113 case ISD::CTPOP: { 1114 static const uint64_t mask[6][9] = { 1115 {0, 0x55, 0x5555, 0, 0x55555555, 0, 0, 0, 0x5555555555555555ULL}, 1116 {0, 0x33, 0x3333, 0, 0x33333333, 0, 0, 0, 0x3333333333333333ULL}, 1117 {0, 0x0F, 0x0F0F, 0, 0x0F0F0F0F, 0, 0, 0, 0x0F0F0F0F0F0F0F0FULL}, 1118 {0, 0, 0x00FF, 0, 0x00FF00FF, 0, 0, 0, 0x00FF00FF00FF00FFULL}, 1119 {0, 0, 0, 0, 0x0000FFFF, 0, 0, 0, 0x0000FFFF0000FFFFULL}, 1120 {0, 0, 0, 0, 0, 0, 0, 0, 0x00000000FFFFFFFFULL}}; 1121 MVT::ValueType VT = Tmp1.getValueType(); 1122 int len = getSizeInBits(VT); 1123 for (int i = 0; (1 << i) <= (len / 2); ++i) { 1124 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 1125 Tmp2 = DAG.getConstant(mask[i][len/8], VT); 1126 Tmp3 = DAG.getConstant(1 << i, VT); 1127 Tmp1 = DAG.getNode(ISD::ADD, VT, 1128 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 1129 DAG.getNode(ISD::AND, VT, 1130 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 1131 Tmp2)); 1132 } 1133 Result = Tmp1; 1134 break; 1135 } 1136// case ISD::CTTZ: 1137// break; 1138// case ISD::CTLZ: 1139// break; 1140 default: 1141 assert(0 && "Cannot expand this yet!"); 1142 break; 1143 } 1144 break; 1145 } 1146 break; 1147 1148 // Unary operators 1149 case ISD::FABS: 1150 case ISD::FNEG: 1151 case ISD::FSQRT: 1152 case ISD::FSIN: 1153 case ISD::FCOS: 1154 Tmp1 = LegalizeOp(Node->getOperand(0)); 1155 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1156 case TargetLowering::Legal: 1157 if (Tmp1 != Node->getOperand(0)) 1158 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1159 break; 1160 case TargetLowering::Promote: 1161 case TargetLowering::Custom: 1162 assert(0 && "Cannot promote/custom handle this yet!"); 1163 case TargetLowering::Expand: 1164 switch(Node->getOpcode()) { 1165 case ISD::FNEG: { 1166 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 1167 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 1168 Result = LegalizeOp(DAG.getNode(ISD::SUB, Node->getValueType(0), 1169 Tmp2, Tmp1)); 1170 break; 1171 } 1172 case ISD::FABS: { 1173 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 1174 MVT::ValueType VT = Node->getValueType(0); 1175 Tmp2 = DAG.getConstantFP(0.0, VT); 1176 Tmp2 = DAG.getSetCC(ISD::SETUGT, TLI.getSetCCResultTy(), Tmp1, Tmp2); 1177 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 1178 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 1179 Result = LegalizeOp(Result); 1180 break; 1181 } 1182 case ISD::FSQRT: 1183 case ISD::FSIN: 1184 case ISD::FCOS: { 1185 MVT::ValueType VT = Node->getValueType(0); 1186 Type *T = VT == MVT::f32 ? Type::FloatTy : Type::DoubleTy; 1187 const char *FnName = 0; 1188 switch(Node->getOpcode()) { 1189 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 1190 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 1191 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 1192 default: assert(0 && "Unreachable!"); 1193 } 1194 std::vector<std::pair<SDOperand, const Type*> > Args; 1195 Args.push_back(std::make_pair(Tmp1, T)); 1196 std::pair<SDOperand,SDOperand> CallResult = 1197 TLI.LowerCallTo(DAG.getEntryNode(), T, false, 1198 DAG.getExternalSymbol(FnName, VT), Args, DAG); 1199 Result = LegalizeOp(CallResult.first); 1200 break; 1201 } 1202 default: 1203 assert(0 && "Unreachable!"); 1204 } 1205 break; 1206 } 1207 break; 1208 1209 // Conversion operators. The source and destination have different types. 1210 case ISD::ZERO_EXTEND: 1211 case ISD::SIGN_EXTEND: 1212 case ISD::TRUNCATE: 1213 case ISD::FP_EXTEND: 1214 case ISD::FP_ROUND: 1215 case ISD::FP_TO_SINT: 1216 case ISD::FP_TO_UINT: 1217 case ISD::SINT_TO_FP: 1218 case ISD::UINT_TO_FP: 1219 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1220 case Legal: 1221 Tmp1 = LegalizeOp(Node->getOperand(0)); 1222 if (Tmp1 != Node->getOperand(0)) 1223 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1224 break; 1225 case Expand: 1226 if (Node->getOpcode() == ISD::SINT_TO_FP || 1227 Node->getOpcode() == ISD::UINT_TO_FP) { 1228 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 1229 Node->getValueType(0), Node->getOperand(0)); 1230 Result = LegalizeOp(Result); 1231 break; 1232 } else if (Node->getOpcode() == ISD::TRUNCATE) { 1233 // In the expand case, we must be dealing with a truncate, because 1234 // otherwise the result would be larger than the source. 1235 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1236 1237 // Since the result is legal, we should just be able to truncate the low 1238 // part of the source. 1239 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 1240 break; 1241 } 1242 assert(0 && "Shouldn't need to expand other operators here!"); 1243 1244 case Promote: 1245 switch (Node->getOpcode()) { 1246 case ISD::ZERO_EXTEND: 1247 Result = PromoteOp(Node->getOperand(0)); 1248 // NOTE: Any extend would work here... 1249 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result); 1250 Result = DAG.getZeroExtendInReg(Result, 1251 Node->getOperand(0).getValueType()); 1252 break; 1253 case ISD::SIGN_EXTEND: 1254 Result = PromoteOp(Node->getOperand(0)); 1255 // NOTE: Any extend would work here... 1256 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result); 1257 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1258 Result, Node->getOperand(0).getValueType()); 1259 break; 1260 case ISD::TRUNCATE: 1261 Result = PromoteOp(Node->getOperand(0)); 1262 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 1263 break; 1264 case ISD::FP_EXTEND: 1265 Result = PromoteOp(Node->getOperand(0)); 1266 if (Result.getValueType() != Op.getValueType()) 1267 // Dynamically dead while we have only 2 FP types. 1268 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 1269 break; 1270 case ISD::FP_ROUND: 1271 case ISD::FP_TO_SINT: 1272 case ISD::FP_TO_UINT: 1273 Result = PromoteOp(Node->getOperand(0)); 1274 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 1275 break; 1276 case ISD::SINT_TO_FP: 1277 Result = PromoteOp(Node->getOperand(0)); 1278 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1279 Result, Node->getOperand(0).getValueType()); 1280 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 1281 break; 1282 case ISD::UINT_TO_FP: 1283 Result = PromoteOp(Node->getOperand(0)); 1284 Result = DAG.getZeroExtendInReg(Result, 1285 Node->getOperand(0).getValueType()); 1286 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 1287 break; 1288 } 1289 } 1290 break; 1291 case ISD::FP_ROUND_INREG: 1292 case ISD::SIGN_EXTEND_INREG: { 1293 Tmp1 = LegalizeOp(Node->getOperand(0)); 1294 MVT::ValueType ExtraVT = cast<MVTSDNode>(Node)->getExtraValueType(); 1295 1296 // If this operation is not supported, convert it to a shl/shr or load/store 1297 // pair. 1298 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 1299 default: assert(0 && "This action not supported for this op yet!"); 1300 case TargetLowering::Legal: 1301 if (Tmp1 != Node->getOperand(0)) 1302 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1303 ExtraVT); 1304 break; 1305 case TargetLowering::Expand: 1306 // If this is an integer extend and shifts are supported, do that. 1307 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 1308 // NOTE: we could fall back on load/store here too for targets without 1309 // SAR. However, it is doubtful that any exist. 1310 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 1311 MVT::getSizeInBits(ExtraVT); 1312 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 1313 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 1314 Node->getOperand(0), ShiftCst); 1315 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 1316 Result, ShiftCst); 1317 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 1318 // The only way we can lower this is to turn it into a STORETRUNC, 1319 // EXTLOAD pair, targetting a temporary location (a stack slot). 1320 1321 // NOTE: there is a choice here between constantly creating new stack 1322 // slots and always reusing the same one. We currently always create 1323 // new ones, as reuse may inhibit scheduling. 1324 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 1325 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 1326 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 1327 MachineFunction &MF = DAG.getMachineFunction(); 1328 int SSFI = 1329 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 1330 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 1331 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 1332 Node->getOperand(0), StackSlot, 1333 DAG.getSrcValue(NULL), ExtraVT); 1334 Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0), 1335 Result, StackSlot, DAG.getSrcValue(NULL), ExtraVT); 1336 } else { 1337 assert(0 && "Unknown op"); 1338 } 1339 Result = LegalizeOp(Result); 1340 break; 1341 } 1342 break; 1343 } 1344 } 1345 1346 if (!Op.Val->hasOneUse()) 1347 AddLegalizedOperand(Op, Result); 1348 1349 return Result; 1350} 1351 1352/// PromoteOp - Given an operation that produces a value in an invalid type, 1353/// promote it to compute the value into a larger type. The produced value will 1354/// have the correct bits for the low portion of the register, but no guarantee 1355/// is made about the top bits: it may be zero, sign-extended, or garbage. 1356SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 1357 MVT::ValueType VT = Op.getValueType(); 1358 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1359 assert(getTypeAction(VT) == Promote && 1360 "Caller should expand or legalize operands that are not promotable!"); 1361 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 1362 "Cannot promote to smaller type!"); 1363 1364 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 1365 if (I != PromotedNodes.end()) return I->second; 1366 1367 SDOperand Tmp1, Tmp2, Tmp3; 1368 1369 SDOperand Result; 1370 SDNode *Node = Op.Val; 1371 1372 // Promotion needs an optimization step to clean up after it, and is not 1373 // careful to avoid operations the target does not support. Make sure that 1374 // all generated operations are legalized in the next iteration. 1375 NeedsAnotherIteration = true; 1376 1377 switch (Node->getOpcode()) { 1378 default: 1379 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 1380 assert(0 && "Do not know how to promote this operator!"); 1381 abort(); 1382 case ISD::UNDEF: 1383 Result = DAG.getNode(ISD::UNDEF, NVT); 1384 break; 1385 case ISD::Constant: 1386 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 1387 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 1388 break; 1389 case ISD::ConstantFP: 1390 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 1391 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 1392 break; 1393 case ISD::CopyFromReg: 1394 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), NVT, 1395 Node->getOperand(0)); 1396 // Remember that we legalized the chain. 1397 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1398 break; 1399 1400 case ISD::SETCC: 1401 assert(getTypeAction(TLI.getSetCCResultTy()) == Legal && 1402 "SetCC type is not legal??"); 1403 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(), 1404 TLI.getSetCCResultTy(), Node->getOperand(0), 1405 Node->getOperand(1)); 1406 Result = LegalizeOp(Result); 1407 break; 1408 1409 case ISD::TRUNCATE: 1410 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1411 case Legal: 1412 Result = LegalizeOp(Node->getOperand(0)); 1413 assert(Result.getValueType() >= NVT && 1414 "This truncation doesn't make sense!"); 1415 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 1416 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 1417 break; 1418 case Promote: 1419 // The truncation is not required, because we don't guarantee anything 1420 // about high bits anyway. 1421 Result = PromoteOp(Node->getOperand(0)); 1422 break; 1423 case Expand: 1424 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1425 // Truncate the low part of the expanded value to the result type 1426 Result = DAG.getNode(ISD::TRUNCATE, VT, Tmp1); 1427 } 1428 break; 1429 case ISD::SIGN_EXTEND: 1430 case ISD::ZERO_EXTEND: 1431 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1432 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 1433 case Legal: 1434 // Input is legal? Just do extend all the way to the larger type. 1435 Result = LegalizeOp(Node->getOperand(0)); 1436 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 1437 break; 1438 case Promote: 1439 // Promote the reg if it's smaller. 1440 Result = PromoteOp(Node->getOperand(0)); 1441 // The high bits are not guaranteed to be anything. Insert an extend. 1442 if (Node->getOpcode() == ISD::SIGN_EXTEND) 1443 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 1444 Node->getOperand(0).getValueType()); 1445 else 1446 Result = DAG.getZeroExtendInReg(Result, 1447 Node->getOperand(0).getValueType()); 1448 break; 1449 } 1450 break; 1451 1452 case ISD::FP_EXTEND: 1453 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 1454 case ISD::FP_ROUND: 1455 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1456 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 1457 case Promote: assert(0 && "Unreachable with 2 FP types!"); 1458 case Legal: 1459 // Input is legal? Do an FP_ROUND_INREG. 1460 Result = LegalizeOp(Node->getOperand(0)); 1461 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1462 break; 1463 } 1464 break; 1465 1466 case ISD::SINT_TO_FP: 1467 case ISD::UINT_TO_FP: 1468 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1469 case Legal: 1470 Result = LegalizeOp(Node->getOperand(0)); 1471 // No extra round required here. 1472 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 1473 break; 1474 1475 case Promote: 1476 Result = PromoteOp(Node->getOperand(0)); 1477 if (Node->getOpcode() == ISD::SINT_TO_FP) 1478 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1479 Result, Node->getOperand(0).getValueType()); 1480 else 1481 Result = DAG.getZeroExtendInReg(Result, 1482 Node->getOperand(0).getValueType()); 1483 // No extra round required here. 1484 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 1485 break; 1486 case Expand: 1487 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 1488 Node->getOperand(0)); 1489 Result = LegalizeOp(Result); 1490 1491 // Round if we cannot tolerate excess precision. 1492 if (NoExcessFPPrecision) 1493 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1494 break; 1495 } 1496 break; 1497 1498 case ISD::FP_TO_SINT: 1499 case ISD::FP_TO_UINT: 1500 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1501 case Legal: 1502 Tmp1 = LegalizeOp(Node->getOperand(0)); 1503 break; 1504 case Promote: 1505 // The input result is prerounded, so we don't have to do anything 1506 // special. 1507 Tmp1 = PromoteOp(Node->getOperand(0)); 1508 break; 1509 case Expand: 1510 assert(0 && "not implemented"); 1511 } 1512 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 1513 break; 1514 1515 case ISD::FABS: 1516 case ISD::FNEG: 1517 Tmp1 = PromoteOp(Node->getOperand(0)); 1518 assert(Tmp1.getValueType() == NVT); 1519 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 1520 // NOTE: we do not have to do any extra rounding here for 1521 // NoExcessFPPrecision, because we know the input will have the appropriate 1522 // precision, and these operations don't modify precision at all. 1523 break; 1524 1525 case ISD::FSQRT: 1526 case ISD::FSIN: 1527 case ISD::FCOS: 1528 Tmp1 = PromoteOp(Node->getOperand(0)); 1529 assert(Tmp1.getValueType() == NVT); 1530 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 1531 if(NoExcessFPPrecision) 1532 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1533 break; 1534 1535 case ISD::AND: 1536 case ISD::OR: 1537 case ISD::XOR: 1538 case ISD::ADD: 1539 case ISD::SUB: 1540 case ISD::MUL: 1541 // The input may have strange things in the top bits of the registers, but 1542 // these operations don't care. They may have wierd bits going out, but 1543 // that too is okay if they are integer operations. 1544 Tmp1 = PromoteOp(Node->getOperand(0)); 1545 Tmp2 = PromoteOp(Node->getOperand(1)); 1546 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 1547 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1548 1549 // However, if this is a floating point operation, they will give excess 1550 // precision that we may not be able to tolerate. If we DO allow excess 1551 // precision, just leave it, otherwise excise it. 1552 // FIXME: Why would we need to round FP ops more than integer ones? 1553 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 1554 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 1555 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1556 break; 1557 1558 case ISD::SDIV: 1559 case ISD::SREM: 1560 // These operators require that their input be sign extended. 1561 Tmp1 = PromoteOp(Node->getOperand(0)); 1562 Tmp2 = PromoteOp(Node->getOperand(1)); 1563 if (MVT::isInteger(NVT)) { 1564 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 1565 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT); 1566 } 1567 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1568 1569 // Perform FP_ROUND: this is probably overly pessimistic. 1570 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 1571 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT); 1572 break; 1573 1574 case ISD::UDIV: 1575 case ISD::UREM: 1576 // These operators require that their input be zero extended. 1577 Tmp1 = PromoteOp(Node->getOperand(0)); 1578 Tmp2 = PromoteOp(Node->getOperand(1)); 1579 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 1580 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1581 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1582 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 1583 break; 1584 1585 case ISD::SHL: 1586 Tmp1 = PromoteOp(Node->getOperand(0)); 1587 Tmp2 = LegalizeOp(Node->getOperand(1)); 1588 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 1589 break; 1590 case ISD::SRA: 1591 // The input value must be properly sign extended. 1592 Tmp1 = PromoteOp(Node->getOperand(0)); 1593 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT); 1594 Tmp2 = LegalizeOp(Node->getOperand(1)); 1595 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 1596 break; 1597 case ISD::SRL: 1598 // The input value must be properly zero extended. 1599 Tmp1 = PromoteOp(Node->getOperand(0)); 1600 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1601 Tmp2 = LegalizeOp(Node->getOperand(1)); 1602 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 1603 break; 1604 case ISD::LOAD: 1605 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1606 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1607 // FIXME: When the DAG combiner exists, change this to use EXTLOAD! 1608 if (MVT::isInteger(NVT)) 1609 Result = DAG.getNode(ISD::ZEXTLOAD, NVT, Tmp1, Tmp2, Node->getOperand(2), 1610 VT); 1611 else 1612 Result = DAG.getNode(ISD::EXTLOAD, NVT, Tmp1, Tmp2, Node->getOperand(2), 1613 VT); 1614 1615 // Remember that we legalized the chain. 1616 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1617 break; 1618 case ISD::SELECT: 1619 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1620 case Expand: assert(0 && "It's impossible to expand bools"); 1621 case Legal: 1622 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 1623 break; 1624 case Promote: 1625 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1626 break; 1627 } 1628 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 1629 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 1630 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 1631 break; 1632 case ISD::CALL: { 1633 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1634 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 1635 1636 std::vector<SDOperand> Ops; 1637 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 1638 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1639 1640 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 1641 "Can only promote single result calls"); 1642 std::vector<MVT::ValueType> RetTyVTs; 1643 RetTyVTs.reserve(2); 1644 RetTyVTs.push_back(NVT); 1645 RetTyVTs.push_back(MVT::Other); 1646 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops); 1647 Result = SDOperand(NC, 0); 1648 1649 // Insert the new chain mapping. 1650 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1651 break; 1652 } 1653 case ISD::CTPOP: 1654 case ISD::CTTZ: 1655 case ISD::CTLZ: 1656 Tmp1 = Node->getOperand(0); 1657 //Zero extend the argument 1658 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1659 // Perform the larger operation, then subtract if needed. 1660 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 1661 switch(Node->getOpcode()) 1662 { 1663 case ISD::CTPOP: 1664 Result = Tmp1; 1665 break; 1666 case ISD::CTTZ: 1667 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 1668 Tmp2 = DAG.getSetCC(ISD::SETEQ, MVT::i1, Tmp1, 1669 DAG.getConstant(getSizeInBits(NVT), NVT)); 1670 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 1671 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 1672 break; 1673 case ISD::CTLZ: 1674 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 1675 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 1676 DAG.getConstant(getSizeInBits(NVT) - 1677 getSizeInBits(VT), NVT)); 1678 break; 1679 } 1680 break; 1681 } 1682 1683 assert(Result.Val && "Didn't set a result!"); 1684 AddPromotedOperand(Op, Result); 1685 return Result; 1686} 1687 1688/// ExpandAddSub - Find a clever way to expand this add operation into 1689/// subcomponents. 1690void SelectionDAGLegalize:: 1691ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 1692 SDOperand &Lo, SDOperand &Hi) { 1693 // Expand the subcomponents. 1694 SDOperand LHSL, LHSH, RHSL, RHSH; 1695 ExpandOp(LHS, LHSL, LHSH); 1696 ExpandOp(RHS, RHSL, RHSH); 1697 1698 // FIXME: this should be moved to the dag combiner someday. 1699 if (NodeOp == ISD::ADD_PARTS || NodeOp == ISD::SUB_PARTS) 1700 if (LHSL.getValueType() == MVT::i32) { 1701 SDOperand LowEl; 1702 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHSL)) 1703 if (C->getValue() == 0) 1704 LowEl = RHSL; 1705 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHSL)) 1706 if (C->getValue() == 0) 1707 LowEl = LHSL; 1708 if (LowEl.Val) { 1709 // Turn this into an add/sub of the high part only. 1710 SDOperand HiEl = 1711 DAG.getNode(NodeOp == ISD::ADD_PARTS ? ISD::ADD : ISD::SUB, 1712 LowEl.getValueType(), LHSH, RHSH); 1713 Lo = LowEl; 1714 Hi = HiEl; 1715 return; 1716 } 1717 } 1718 1719 std::vector<SDOperand> Ops; 1720 Ops.push_back(LHSL); 1721 Ops.push_back(LHSH); 1722 Ops.push_back(RHSL); 1723 Ops.push_back(RHSH); 1724 Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops); 1725 Hi = Lo.getValue(1); 1726} 1727 1728void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 1729 SDOperand Op, SDOperand Amt, 1730 SDOperand &Lo, SDOperand &Hi) { 1731 // Expand the subcomponents. 1732 SDOperand LHSL, LHSH; 1733 ExpandOp(Op, LHSL, LHSH); 1734 1735 std::vector<SDOperand> Ops; 1736 Ops.push_back(LHSL); 1737 Ops.push_back(LHSH); 1738 Ops.push_back(Amt); 1739 Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops); 1740 Hi = Lo.getValue(1); 1741} 1742 1743 1744/// ExpandShift - Try to find a clever way to expand this shift operation out to 1745/// smaller elements. If we can't find a way that is more efficient than a 1746/// libcall on this target, return false. Otherwise, return true with the 1747/// low-parts expanded into Lo and Hi. 1748bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 1749 SDOperand &Lo, SDOperand &Hi) { 1750 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 1751 "This is not a shift!"); 1752 1753 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 1754 SDOperand ShAmt = LegalizeOp(Amt); 1755 MVT::ValueType ShTy = ShAmt.getValueType(); 1756 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 1757 unsigned NVTBits = MVT::getSizeInBits(NVT); 1758 1759 // Handle the case when Amt is an immediate. Other cases are currently broken 1760 // and are disabled. 1761 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 1762 unsigned Cst = CN->getValue(); 1763 // Expand the incoming operand to be shifted, so that we have its parts 1764 SDOperand InL, InH; 1765 ExpandOp(Op, InL, InH); 1766 switch(Opc) { 1767 case ISD::SHL: 1768 if (Cst > VTBits) { 1769 Lo = DAG.getConstant(0, NVT); 1770 Hi = DAG.getConstant(0, NVT); 1771 } else if (Cst > NVTBits) { 1772 Lo = DAG.getConstant(0, NVT); 1773 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 1774 } else if (Cst == NVTBits) { 1775 Lo = DAG.getConstant(0, NVT); 1776 Hi = InL; 1777 } else { 1778 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 1779 Hi = DAG.getNode(ISD::OR, NVT, 1780 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 1781 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 1782 } 1783 return true; 1784 case ISD::SRL: 1785 if (Cst > VTBits) { 1786 Lo = DAG.getConstant(0, NVT); 1787 Hi = DAG.getConstant(0, NVT); 1788 } else if (Cst > NVTBits) { 1789 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 1790 Hi = DAG.getConstant(0, NVT); 1791 } else if (Cst == NVTBits) { 1792 Lo = InH; 1793 Hi = DAG.getConstant(0, NVT); 1794 } else { 1795 Lo = DAG.getNode(ISD::OR, NVT, 1796 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 1797 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 1798 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 1799 } 1800 return true; 1801 case ISD::SRA: 1802 if (Cst > VTBits) { 1803 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 1804 DAG.getConstant(NVTBits-1, ShTy)); 1805 } else if (Cst > NVTBits) { 1806 Lo = DAG.getNode(ISD::SRA, NVT, InH, 1807 DAG.getConstant(Cst-NVTBits, ShTy)); 1808 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1809 DAG.getConstant(NVTBits-1, ShTy)); 1810 } else if (Cst == NVTBits) { 1811 Lo = InH; 1812 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1813 DAG.getConstant(NVTBits-1, ShTy)); 1814 } else { 1815 Lo = DAG.getNode(ISD::OR, NVT, 1816 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 1817 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 1818 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 1819 } 1820 return true; 1821 } 1822 } 1823 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 1824 // so disable it for now. Currently targets are handling this via SHL_PARTS 1825 // and friends. 1826 return false; 1827 1828 // If we have an efficient select operation (or if the selects will all fold 1829 // away), lower to some complex code, otherwise just emit the libcall. 1830 if (TLI.getOperationAction(ISD::SELECT, NVT) != TargetLowering::Legal && 1831 !isa<ConstantSDNode>(Amt)) 1832 return false; 1833 1834 SDOperand InL, InH; 1835 ExpandOp(Op, InL, InH); 1836 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 1837 DAG.getConstant(NVTBits, ShTy), ShAmt); 1838 1839 // Compare the unmasked shift amount against 32. 1840 SDOperand Cond = DAG.getSetCC(ISD::SETGE, TLI.getSetCCResultTy(), ShAmt, 1841 DAG.getConstant(NVTBits, ShTy)); 1842 1843 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 1844 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 1845 DAG.getConstant(NVTBits-1, ShTy)); 1846 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 1847 DAG.getConstant(NVTBits-1, ShTy)); 1848 } 1849 1850 if (Opc == ISD::SHL) { 1851 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 1852 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 1853 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 1854 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 1855 1856 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 1857 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 1858 } else { 1859 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 1860 DAG.getSetCC(ISD::SETEQ, 1861 TLI.getSetCCResultTy(), NAmt, 1862 DAG.getConstant(32, ShTy)), 1863 DAG.getConstant(0, NVT), 1864 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 1865 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 1866 HiLoPart, 1867 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 1868 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 1869 1870 SDOperand HiPart; 1871 if (Opc == ISD::SRA) 1872 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 1873 DAG.getConstant(NVTBits-1, ShTy)); 1874 else 1875 HiPart = DAG.getConstant(0, NVT); 1876 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 1877 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 1878 } 1879 return true; 1880} 1881 1882/// FindLatestAdjCallStackDown - Scan up the dag to find the latest (highest 1883/// NodeDepth) node that is an AdjCallStackDown operation and occurs later than 1884/// Found. 1885static void FindLatestAdjCallStackDown(SDNode *Node, SDNode *&Found) { 1886 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 1887 1888 // If we found an ADJCALLSTACKDOWN, we already know this node occurs later 1889 // than the Found node. Just remember this node and return. 1890 if (Node->getOpcode() == ISD::ADJCALLSTACKDOWN) { 1891 Found = Node; 1892 return; 1893 } 1894 1895 // Otherwise, scan the operands of Node to see if any of them is a call. 1896 assert(Node->getNumOperands() != 0 && 1897 "All leaves should have depth equal to the entry node!"); 1898 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 1899 FindLatestAdjCallStackDown(Node->getOperand(i).Val, Found); 1900 1901 // Tail recurse for the last iteration. 1902 FindLatestAdjCallStackDown(Node->getOperand(Node->getNumOperands()-1).Val, 1903 Found); 1904} 1905 1906 1907/// FindEarliestAdjCallStackUp - Scan down the dag to find the earliest (lowest 1908/// NodeDepth) node that is an AdjCallStackUp operation and occurs more recent 1909/// than Found. 1910static void FindEarliestAdjCallStackUp(SDNode *Node, SDNode *&Found) { 1911 if (Found && Node->getNodeDepth() >= Found->getNodeDepth()) return; 1912 1913 // If we found an ADJCALLSTACKUP, we already know this node occurs earlier 1914 // than the Found node. Just remember this node and return. 1915 if (Node->getOpcode() == ISD::ADJCALLSTACKUP) { 1916 Found = Node; 1917 return; 1918 } 1919 1920 // Otherwise, scan the operands of Node to see if any of them is a call. 1921 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 1922 if (UI == E) return; 1923 for (--E; UI != E; ++UI) 1924 FindEarliestAdjCallStackUp(*UI, Found); 1925 1926 // Tail recurse for the last iteration. 1927 FindEarliestAdjCallStackUp(*UI, Found); 1928} 1929 1930/// FindAdjCallStackUp - Given a chained node that is part of a call sequence, 1931/// find the ADJCALLSTACKUP node that terminates the call sequence. 1932static SDNode *FindAdjCallStackUp(SDNode *Node) { 1933 if (Node->getOpcode() == ISD::ADJCALLSTACKUP) 1934 return Node; 1935 if (Node->use_empty()) 1936 return 0; // No adjcallstackup 1937 1938 if (Node->hasOneUse()) // Simple case, only has one user to check. 1939 return FindAdjCallStackUp(*Node->use_begin()); 1940 1941 SDOperand TheChain(Node, Node->getNumValues()-1); 1942 assert(TheChain.getValueType() == MVT::Other && "Is not a token chain!"); 1943 1944 for (SDNode::use_iterator UI = Node->use_begin(), 1945 E = Node->use_end(); ; ++UI) { 1946 assert(UI != E && "Didn't find a user of the tokchain, no ADJCALLSTACKUP!"); 1947 1948 // Make sure to only follow users of our token chain. 1949 SDNode *User = *UI; 1950 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 1951 if (User->getOperand(i) == TheChain) 1952 return FindAdjCallStackUp(User); 1953 } 1954 assert(0 && "Unreachable"); 1955 abort(); 1956} 1957 1958/// FindInputOutputChains - If we are replacing an operation with a call we need 1959/// to find the call that occurs before and the call that occurs after it to 1960/// properly serialize the calls in the block. 1961static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 1962 SDOperand Entry) { 1963 SDNode *LatestAdjCallStackDown = Entry.Val; 1964 SDNode *LatestAdjCallStackUp = 0; 1965 FindLatestAdjCallStackDown(OpNode, LatestAdjCallStackDown); 1966 //std::cerr << "Found node: "; LatestAdjCallStackDown->dump(); std::cerr <<"\n"; 1967 1968 // It is possible that no ISD::ADJCALLSTACKDOWN was found because there is no 1969 // previous call in the function. LatestCallStackDown may in that case be 1970 // the entry node itself. Do not attempt to find a matching ADJCALLSTACKUP 1971 // unless LatestCallStackDown is an ADJCALLSTACKDOWN. 1972 if (LatestAdjCallStackDown->getOpcode() == ISD::ADJCALLSTACKDOWN) 1973 LatestAdjCallStackUp = FindAdjCallStackUp(LatestAdjCallStackDown); 1974 else 1975 LatestAdjCallStackUp = Entry.Val; 1976 assert(LatestAdjCallStackUp && "NULL return from FindAdjCallStackUp"); 1977 1978 SDNode *EarliestAdjCallStackUp = 0; 1979 FindEarliestAdjCallStackUp(OpNode, EarliestAdjCallStackUp); 1980 1981 if (EarliestAdjCallStackUp) { 1982 //std::cerr << "Found node: "; 1983 //EarliestAdjCallStackUp->dump(); std::cerr <<"\n"; 1984 } 1985 1986 return SDOperand(LatestAdjCallStackUp, 0); 1987} 1988 1989 1990 1991// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1992// does not fit into a register, return the lo part and set the hi part to the 1993// by-reg argument. If it does fit into a single register, return the result 1994// and leave the Hi part unset. 1995SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 1996 SDOperand &Hi) { 1997 SDNode *OutChain; 1998 SDOperand InChain = FindInputOutputChains(Node, OutChain, 1999 DAG.getEntryNode()); 2000 if (InChain.Val == 0) 2001 InChain = DAG.getEntryNode(); 2002 2003 TargetLowering::ArgListTy Args; 2004 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2005 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 2006 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 2007 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 2008 } 2009 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 2010 2011 // We don't care about token chains for libcalls. We just use the entry 2012 // node as our input and ignore the output chain. This allows us to place 2013 // calls wherever we need them to satisfy data dependences. 2014 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 2015 SDOperand Result = TLI.LowerCallTo(InChain, RetTy, false, Callee, 2016 Args, DAG).first; 2017 switch (getTypeAction(Result.getValueType())) { 2018 default: assert(0 && "Unknown thing"); 2019 case Legal: 2020 return Result; 2021 case Promote: 2022 assert(0 && "Cannot promote this yet!"); 2023 case Expand: 2024 SDOperand Lo; 2025 ExpandOp(Result, Lo, Hi); 2026 return Lo; 2027 } 2028} 2029 2030 2031/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 2032/// destination type is legal. 2033SDOperand SelectionDAGLegalize:: 2034ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 2035 assert(getTypeAction(DestTy) == Legal && "Destination type is not legal!"); 2036 assert(getTypeAction(Source.getValueType()) == Expand && 2037 "This is not an expansion!"); 2038 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 2039 2040 SDNode *OutChain; 2041 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 2042 DAG.getEntryNode()); 2043 2044 const char *FnName = 0; 2045 if (isSigned) { 2046 if (DestTy == MVT::f32) 2047 FnName = "__floatdisf"; 2048 else { 2049 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 2050 FnName = "__floatdidf"; 2051 } 2052 } else { 2053 // If this is unsigned, and not supported, first perform the conversion to 2054 // signed, then adjust the result if the sign bit is set. 2055 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source); 2056 2057 assert(Source.getValueType() == MVT::i64 && 2058 "This only works for 64-bit -> FP"); 2059 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 2060 // incoming integer is set. To handle this, we dynamically test to see if 2061 // it is set, and, if so, add a fudge factor. 2062 SDOperand Lo, Hi; 2063 ExpandOp(Source, Lo, Hi); 2064 2065 SDOperand SignSet = DAG.getSetCC(ISD::SETLT, TLI.getSetCCResultTy(), Hi, 2066 DAG.getConstant(0, Hi.getValueType())); 2067 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 2068 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 2069 SignSet, Four, Zero); 2070 // FIXME: This is almost certainly broken for big-endian systems. Should 2071 // this just put the fudge factor in the low bits of the uint64 constant or? 2072 static Constant *FudgeFactor = 2073 ConstantUInt::get(Type::ULongTy, 0x5f800000ULL << 32); 2074 2075 MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool(); 2076 SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(FudgeFactor), 2077 TLI.getPointerTy()); 2078 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 2079 SDOperand FudgeInReg; 2080 if (DestTy == MVT::f32) 2081 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 2082 DAG.getSrcValue(NULL)); 2083 else { 2084 assert(DestTy == MVT::f64 && "Unexpected conversion"); 2085 FudgeInReg = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 2086 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 2087 } 2088 return DAG.getNode(ISD::ADD, DestTy, SignedConv, FudgeInReg); 2089 } 2090 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 2091 2092 TargetLowering::ArgListTy Args; 2093 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 2094 Args.push_back(std::make_pair(Source, ArgTy)); 2095 2096 // We don't care about token chains for libcalls. We just use the entry 2097 // node as our input and ignore the output chain. This allows us to place 2098 // calls wherever we need them to satisfy data dependences. 2099 const Type *RetTy = MVT::getTypeForValueType(DestTy); 2100 return TLI.LowerCallTo(InChain, RetTy, false, Callee, Args, DAG).first; 2101} 2102 2103 2104 2105/// ExpandOp - Expand the specified SDOperand into its two component pieces 2106/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 2107/// LegalizeNodes map is filled in for any results that are not expanded, the 2108/// ExpandedNodes map is filled in for any results that are expanded, and the 2109/// Lo/Hi values are returned. 2110void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 2111 MVT::ValueType VT = Op.getValueType(); 2112 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2113 SDNode *Node = Op.Val; 2114 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 2115 assert(MVT::isInteger(VT) && "Cannot expand FP values!"); 2116 assert(MVT::isInteger(NVT) && NVT < VT && 2117 "Cannot expand to FP value or to larger int value!"); 2118 2119 // If there is more than one use of this, see if we already expanded it. 2120 // There is no use remembering values that only have a single use, as the map 2121 // entries will never be reused. 2122 if (!Node->hasOneUse()) { 2123 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 2124 = ExpandedNodes.find(Op); 2125 if (I != ExpandedNodes.end()) { 2126 Lo = I->second.first; 2127 Hi = I->second.second; 2128 return; 2129 } 2130 } 2131 2132 // Expanding to multiple registers needs to perform an optimization step, and 2133 // is not careful to avoid operations the target does not support. Make sure 2134 // that all generated operations are legalized in the next iteration. 2135 NeedsAnotherIteration = true; 2136 2137 switch (Node->getOpcode()) { 2138 default: 2139 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2140 assert(0 && "Do not know how to expand this operator!"); 2141 abort(); 2142 case ISD::UNDEF: 2143 Lo = DAG.getNode(ISD::UNDEF, NVT); 2144 Hi = DAG.getNode(ISD::UNDEF, NVT); 2145 break; 2146 case ISD::Constant: { 2147 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 2148 Lo = DAG.getConstant(Cst, NVT); 2149 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 2150 break; 2151 } 2152 2153 case ISD::CopyFromReg: { 2154 unsigned Reg = cast<RegSDNode>(Node)->getReg(); 2155 // Aggregate register values are always in consequtive pairs. 2156 Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0)); 2157 Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1)); 2158 2159 // Remember that we legalized the chain. 2160 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 2161 2162 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 2163 break; 2164 } 2165 2166 case ISD::BUILD_PAIR: 2167 // Legalize both operands. FIXME: in the future we should handle the case 2168 // where the two elements are not legal. 2169 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 2170 Lo = LegalizeOp(Node->getOperand(0)); 2171 Hi = LegalizeOp(Node->getOperand(1)); 2172 break; 2173 2174 case ISD::CTPOP: 2175 ExpandOp(Node->getOperand(0), Lo, Hi); 2176 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 2177 DAG.getNode(ISD::CTPOP, NVT, Lo), 2178 DAG.getNode(ISD::CTPOP, NVT, Hi)); 2179 Hi = DAG.getConstant(0, NVT); 2180 break; 2181 2182 case ISD::CTTZ: 2183 case ISD::CTLZ: 2184 assert(0 && "ct intrinsics cannot be expanded!"); 2185 2186 case ISD::LOAD: { 2187 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2188 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2189 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 2190 2191 // Increment the pointer to the other half. 2192 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 2193 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2194 getIntPtrConstant(IncrementSize)); 2195 //Is this safe? declaring that the two parts of the split load 2196 //are from the same instruction? 2197 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 2198 2199 // Build a factor node to remember that this load is independent of the 2200 // other one. 2201 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2202 Hi.getValue(1)); 2203 2204 // Remember that we legalized the chain. 2205 AddLegalizedOperand(Op.getValue(1), TF); 2206 if (!TLI.isLittleEndian()) 2207 std::swap(Lo, Hi); 2208 break; 2209 } 2210 case ISD::CALL: { 2211 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2212 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 2213 2214 bool Changed = false; 2215 std::vector<SDOperand> Ops; 2216 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 2217 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2218 Changed |= Ops.back() != Node->getOperand(i); 2219 } 2220 2221 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 2222 "Can only expand a call once so far, not i64 -> i16!"); 2223 2224 std::vector<MVT::ValueType> RetTyVTs; 2225 RetTyVTs.reserve(3); 2226 RetTyVTs.push_back(NVT); 2227 RetTyVTs.push_back(NVT); 2228 RetTyVTs.push_back(MVT::Other); 2229 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops); 2230 Lo = SDOperand(NC, 0); 2231 Hi = SDOperand(NC, 1); 2232 2233 // Insert the new chain mapping. 2234 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 2235 break; 2236 } 2237 case ISD::AND: 2238 case ISD::OR: 2239 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 2240 SDOperand LL, LH, RL, RH; 2241 ExpandOp(Node->getOperand(0), LL, LH); 2242 ExpandOp(Node->getOperand(1), RL, RH); 2243 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 2244 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 2245 break; 2246 } 2247 case ISD::SELECT: { 2248 SDOperand C, LL, LH, RL, RH; 2249 2250 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2251 case Expand: assert(0 && "It's impossible to expand bools"); 2252 case Legal: 2253 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2254 break; 2255 case Promote: 2256 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 2257 break; 2258 } 2259 ExpandOp(Node->getOperand(1), LL, LH); 2260 ExpandOp(Node->getOperand(2), RL, RH); 2261 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 2262 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 2263 break; 2264 } 2265 case ISD::SIGN_EXTEND: { 2266 SDOperand In; 2267 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2268 case Expand: assert(0 && "expand-expand not implemented yet!"); 2269 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 2270 case Promote: 2271 In = PromoteOp(Node->getOperand(0)); 2272 // Emit the appropriate sign_extend_inreg to get the value we want. 2273 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 2274 Node->getOperand(0).getValueType()); 2275 break; 2276 } 2277 2278 // The low part is just a sign extension of the input (which degenerates to 2279 // a copy). 2280 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 2281 2282 // The high part is obtained by SRA'ing all but one of the bits of the lo 2283 // part. 2284 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 2285 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 2286 TLI.getShiftAmountTy())); 2287 break; 2288 } 2289 case ISD::ZERO_EXTEND: { 2290 SDOperand In; 2291 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2292 case Expand: assert(0 && "expand-expand not implemented yet!"); 2293 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 2294 case Promote: 2295 In = PromoteOp(Node->getOperand(0)); 2296 // Emit the appropriate zero_extend_inreg to get the value we want. 2297 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 2298 break; 2299 } 2300 2301 // The low part is just a zero extension of the input (which degenerates to 2302 // a copy). 2303 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 2304 2305 // The high part is just a zero. 2306 Hi = DAG.getConstant(0, NVT); 2307 break; 2308 } 2309 // These operators cannot be expanded directly, emit them as calls to 2310 // library functions. 2311 case ISD::FP_TO_SINT: 2312 if (Node->getOperand(0).getValueType() == MVT::f32) 2313 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 2314 else 2315 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 2316 break; 2317 case ISD::FP_TO_UINT: 2318 if (Node->getOperand(0).getValueType() == MVT::f32) 2319 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 2320 else 2321 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 2322 break; 2323 2324 case ISD::SHL: 2325 // If we can emit an efficient shift operation, do so now. 2326 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 2327 break; 2328 2329 // If this target supports SHL_PARTS, use it. 2330 if (TLI.getOperationAction(ISD::SHL_PARTS, NVT) == TargetLowering::Legal) { 2331 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 2332 Lo, Hi); 2333 break; 2334 } 2335 2336 // Otherwise, emit a libcall. 2337 Lo = ExpandLibCall("__ashldi3", Node, Hi); 2338 break; 2339 2340 case ISD::SRA: 2341 // If we can emit an efficient shift operation, do so now. 2342 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 2343 break; 2344 2345 // If this target supports SRA_PARTS, use it. 2346 if (TLI.getOperationAction(ISD::SRA_PARTS, NVT) == TargetLowering::Legal) { 2347 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 2348 Lo, Hi); 2349 break; 2350 } 2351 2352 // Otherwise, emit a libcall. 2353 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 2354 break; 2355 case ISD::SRL: 2356 // If we can emit an efficient shift operation, do so now. 2357 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 2358 break; 2359 2360 // If this target supports SRL_PARTS, use it. 2361 if (TLI.getOperationAction(ISD::SRL_PARTS, NVT) == TargetLowering::Legal) { 2362 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 2363 Lo, Hi); 2364 break; 2365 } 2366 2367 // Otherwise, emit a libcall. 2368 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 2369 break; 2370 2371 case ISD::ADD: 2372 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 2373 Lo, Hi); 2374 break; 2375 case ISD::SUB: 2376 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 2377 Lo, Hi); 2378 break; 2379 case ISD::MUL: { 2380 if (TLI.getOperationAction(ISD::MULHU, NVT) == TargetLowering::Legal) { 2381 SDOperand LL, LH, RL, RH; 2382 ExpandOp(Node->getOperand(0), LL, LH); 2383 ExpandOp(Node->getOperand(1), RL, RH); 2384 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 2385 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 2386 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 2387 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 2388 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 2389 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 2390 } else { 2391 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 2392 } 2393 break; 2394 } 2395 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 2396 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 2397 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 2398 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 2399 } 2400 2401 // Remember in a map if the values will be reused later. 2402 if (!Node->hasOneUse()) { 2403 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 2404 std::make_pair(Lo, Hi))).second; 2405 assert(isNew && "Value already expanded?!?"); 2406 } 2407} 2408 2409 2410// SelectionDAG::Legalize - This is the entry point for the file. 2411// 2412void SelectionDAG::Legalize() { 2413 /// run - This is the main entry point to this class. 2414 /// 2415 SelectionDAGLegalize(*this).Run(); 2416} 2417 2418