LegalizeDAG.cpp revision 9d5f45607793052bf5b4436d1b43013fab9999ac
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/Target/TargetFrameInfo.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetMachine.h" 22#include "llvm/Target/TargetOptions.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/DerivedTypes.h" 26#include "llvm/Support/MathExtras.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Compiler.h" 29#include "llvm/ADT/DenseMap.h" 30#include "llvm/ADT/SmallVector.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include <map> 33using namespace llvm; 34 35#ifndef NDEBUG 36static cl::opt<bool> 37ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 38 cl::desc("Pop up a window to show dags before legalize")); 39#else 40static const bool ViewLegalizeDAGs = 0; 41#endif 42 43//===----------------------------------------------------------------------===// 44/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 45/// hacks on it until the target machine can handle it. This involves 46/// eliminating value sizes the machine cannot handle (promoting small sizes to 47/// large sizes or splitting up large values into small values) as well as 48/// eliminating operations the machine cannot handle. 49/// 50/// This code also does a small amount of optimization and recognition of idioms 51/// as part of its processing. For example, if a target does not support a 52/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 53/// will attempt merge setcc and brc instructions into brcc's. 54/// 55namespace { 56class VISIBILITY_HIDDEN SelectionDAGLegalize { 57 TargetLowering &TLI; 58 SelectionDAG &DAG; 59 60 // Libcall insertion helpers. 61 62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 63 /// legalized. We use this to ensure that calls are properly serialized 64 /// against each other, including inserted libcalls. 65 SDOperand LastCALLSEQ_END; 66 67 /// IsLegalizingCall - This member is used *only* for purposes of providing 68 /// helpful assertions that a libcall isn't created while another call is 69 /// being legalized (which could lead to non-serialized call sequences). 70 bool IsLegalizingCall; 71 72 enum LegalizeAction { 73 Legal, // The target natively supports this operation. 74 Promote, // This operation should be executed in a larger type. 75 Expand // Try to expand this to other ops, otherwise use a libcall. 76 }; 77 78 /// ValueTypeActions - This is a bitvector that contains two bits for each 79 /// value type, where the two bits correspond to the LegalizeAction enum. 80 /// This can be queried with "getTypeAction(VT)". 81 TargetLowering::ValueTypeActionImpl ValueTypeActions; 82 83 /// LegalizedNodes - For nodes that are of legal width, and that have more 84 /// than one use, this map indicates what regularized operand to use. This 85 /// allows us to avoid legalizing the same thing more than once. 86 DenseMap<SDOperand, SDOperand> LegalizedNodes; 87 88 /// PromotedNodes - For nodes that are below legal width, and that have more 89 /// than one use, this map indicates what promoted value to use. This allows 90 /// us to avoid promoting the same thing more than once. 91 DenseMap<SDOperand, SDOperand> PromotedNodes; 92 93 /// ExpandedNodes - For nodes that need to be expanded this map indicates 94 /// which which operands are the expanded version of the input. This allows 95 /// us to avoid expanding the same node more than once. 96 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 97 98 /// SplitNodes - For vector nodes that need to be split, this map indicates 99 /// which which operands are the split version of the input. This allows us 100 /// to avoid splitting the same node more than once. 101 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 102 103 /// ScalarizedNodes - For nodes that need to be converted from vector types to 104 /// scalar types, this contains the mapping of ones we have already 105 /// processed to the result. 106 std::map<SDOperand, SDOperand> ScalarizedNodes; 107 108 void AddLegalizedOperand(SDOperand From, SDOperand To) { 109 LegalizedNodes.insert(std::make_pair(From, To)); 110 // If someone requests legalization of the new node, return itself. 111 if (From != To) 112 LegalizedNodes.insert(std::make_pair(To, To)); 113 } 114 void AddPromotedOperand(SDOperand From, SDOperand To) { 115 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 116 assert(isNew && "Got into the map somehow?"); 117 // If someone requests legalization of the new node, return itself. 118 LegalizedNodes.insert(std::make_pair(To, To)); 119 } 120 121public: 122 123 SelectionDAGLegalize(SelectionDAG &DAG); 124 125 /// getTypeAction - Return how we should legalize values of this type, either 126 /// it is already legal or we need to expand it into multiple registers of 127 /// smaller integer type, or we need to promote it to a larger type. 128 LegalizeAction getTypeAction(MVT::ValueType VT) const { 129 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 130 } 131 132 /// isTypeLegal - Return true if this type is legal on this target. 133 /// 134 bool isTypeLegal(MVT::ValueType VT) const { 135 return getTypeAction(VT) == Legal; 136 } 137 138 void LegalizeDAG(); 139 140private: 141 /// HandleOp - Legalize, Promote, or Expand the specified operand as 142 /// appropriate for its type. 143 void HandleOp(SDOperand Op); 144 145 /// LegalizeOp - We know that the specified value has a legal type. 146 /// Recursively ensure that the operands have legal types, then return the 147 /// result. 148 SDOperand LegalizeOp(SDOperand O); 149 150 /// PromoteOp - Given an operation that produces a value in an invalid type, 151 /// promote it to compute the value into a larger type. The produced value 152 /// will have the correct bits for the low portion of the register, but no 153 /// guarantee is made about the top bits: it may be zero, sign-extended, or 154 /// garbage. 155 SDOperand PromoteOp(SDOperand O); 156 157 /// ExpandOp - Expand the specified SDOperand into its two component pieces 158 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 159 /// the LegalizeNodes map is filled in for any results that are not expanded, 160 /// the ExpandedNodes map is filled in for any results that are expanded, and 161 /// the Lo/Hi values are returned. This applies to integer types and Vector 162 /// types. 163 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 164 165 /// SplitVectorOp - Given an operand of vector type, break it down into 166 /// two smaller values. 167 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 168 169 /// ScalarizeVectorOp - Given an operand of single-element vector type 170 /// (e.g. v1f32), convert it into the equivalent operation that returns a 171 /// scalar (e.g. f32) value. 172 SDOperand ScalarizeVectorOp(SDOperand O); 173 174 /// isShuffleLegal - Return true if a vector shuffle is legal with the 175 /// specified mask and type. Targets can specify exactly which masks they 176 /// support and the code generator is tasked with not creating illegal masks. 177 /// 178 /// Note that this will also return true for shuffles that are promoted to a 179 /// different type. 180 /// 181 /// If this is a legal shuffle, this method returns the (possibly promoted) 182 /// build_vector Mask. If it's not a legal shuffle, it returns null. 183 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 184 185 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 186 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 187 188 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 189 190 SDOperand CreateStackTemporary(MVT::ValueType VT); 191 192 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 193 SDOperand &Hi); 194 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 195 SDOperand Source); 196 197 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 198 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 199 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 200 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 201 SDOperand LegalOp, 202 MVT::ValueType DestVT); 203 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 204 bool isSigned); 205 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 206 bool isSigned); 207 208 SDOperand ExpandBSWAP(SDOperand Op); 209 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 210 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 211 SDOperand &Lo, SDOperand &Hi); 212 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 213 SDOperand &Lo, SDOperand &Hi); 214 215 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 216 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 217 218 SDOperand getIntPtrConstant(uint64_t Val) { 219 return DAG.getConstant(Val, TLI.getPointerTy()); 220 } 221}; 222} 223 224/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 225/// specified mask and type. Targets can specify exactly which masks they 226/// support and the code generator is tasked with not creating illegal masks. 227/// 228/// Note that this will also return true for shuffles that are promoted to a 229/// different type. 230SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 231 SDOperand Mask) const { 232 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 233 default: return 0; 234 case TargetLowering::Legal: 235 case TargetLowering::Custom: 236 break; 237 case TargetLowering::Promote: { 238 // If this is promoted to a different type, convert the shuffle mask and 239 // ask if it is legal in the promoted type! 240 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 241 242 // If we changed # elements, change the shuffle mask. 243 unsigned NumEltsGrowth = 244 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 245 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 246 if (NumEltsGrowth > 1) { 247 // Renumber the elements. 248 SmallVector<SDOperand, 8> Ops; 249 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 250 SDOperand InOp = Mask.getOperand(i); 251 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 252 if (InOp.getOpcode() == ISD::UNDEF) 253 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 254 else { 255 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 256 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 257 } 258 } 259 } 260 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 261 } 262 VT = NVT; 263 break; 264 } 265 } 266 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 267} 268 269SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 270 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 271 ValueTypeActions(TLI.getValueTypeActions()) { 272 assert(MVT::LAST_VALUETYPE <= 32 && 273 "Too many value types for ValueTypeActions to hold!"); 274} 275 276/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 277/// contains all of a nodes operands before it contains the node. 278static void ComputeTopDownOrdering(SelectionDAG &DAG, 279 SmallVector<SDNode*, 64> &Order) { 280 281 DenseMap<SDNode*, unsigned> Visited; 282 std::vector<SDNode*> Worklist; 283 Worklist.reserve(128); 284 285 // Compute ordering from all of the leaves in the graphs, those (like the 286 // entry node) that have no operands. 287 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 288 E = DAG.allnodes_end(); I != E; ++I) { 289 if (I->getNumOperands() == 0) { 290 Visited[I] = 0 - 1U; 291 Worklist.push_back(I); 292 } 293 } 294 295 while (!Worklist.empty()) { 296 SDNode *N = Worklist.back(); 297 Worklist.pop_back(); 298 299 if (++Visited[N] != N->getNumOperands()) 300 continue; // Haven't visited all operands yet 301 302 Order.push_back(N); 303 304 // Now that we have N in, add anything that uses it if all of their operands 305 // are now done. 306 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 307 UI != E; ++UI) 308 Worklist.push_back(*UI); 309 } 310 311 assert(Order.size() == Visited.size() && 312 Order.size() == 313 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 314 "Error: DAG is cyclic!"); 315} 316 317 318void SelectionDAGLegalize::LegalizeDAG() { 319 LastCALLSEQ_END = DAG.getEntryNode(); 320 IsLegalizingCall = false; 321 322 // The legalize process is inherently a bottom-up recursive process (users 323 // legalize their uses before themselves). Given infinite stack space, we 324 // could just start legalizing on the root and traverse the whole graph. In 325 // practice however, this causes us to run out of stack space on large basic 326 // blocks. To avoid this problem, compute an ordering of the nodes where each 327 // node is only legalized after all of its operands are legalized. 328 SmallVector<SDNode*, 64> Order; 329 ComputeTopDownOrdering(DAG, Order); 330 331 for (unsigned i = 0, e = Order.size(); i != e; ++i) 332 HandleOp(SDOperand(Order[i], 0)); 333 334 // Finally, it's possible the root changed. Get the new root. 335 SDOperand OldRoot = DAG.getRoot(); 336 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 337 DAG.setRoot(LegalizedNodes[OldRoot]); 338 339 ExpandedNodes.clear(); 340 LegalizedNodes.clear(); 341 PromotedNodes.clear(); 342 SplitNodes.clear(); 343 ScalarizedNodes.clear(); 344 345 // Remove dead nodes now. 346 DAG.RemoveDeadNodes(); 347} 348 349 350/// FindCallEndFromCallStart - Given a chained node that is part of a call 351/// sequence, find the CALLSEQ_END node that terminates the call sequence. 352static SDNode *FindCallEndFromCallStart(SDNode *Node) { 353 if (Node->getOpcode() == ISD::CALLSEQ_END) 354 return Node; 355 if (Node->use_empty()) 356 return 0; // No CallSeqEnd 357 358 // The chain is usually at the end. 359 SDOperand TheChain(Node, Node->getNumValues()-1); 360 if (TheChain.getValueType() != MVT::Other) { 361 // Sometimes it's at the beginning. 362 TheChain = SDOperand(Node, 0); 363 if (TheChain.getValueType() != MVT::Other) { 364 // Otherwise, hunt for it. 365 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 366 if (Node->getValueType(i) == MVT::Other) { 367 TheChain = SDOperand(Node, i); 368 break; 369 } 370 371 // Otherwise, we walked into a node without a chain. 372 if (TheChain.getValueType() != MVT::Other) 373 return 0; 374 } 375 } 376 377 for (SDNode::use_iterator UI = Node->use_begin(), 378 E = Node->use_end(); UI != E; ++UI) { 379 380 // Make sure to only follow users of our token chain. 381 SDNode *User = *UI; 382 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 383 if (User->getOperand(i) == TheChain) 384 if (SDNode *Result = FindCallEndFromCallStart(User)) 385 return Result; 386 } 387 return 0; 388} 389 390/// FindCallStartFromCallEnd - Given a chained node that is part of a call 391/// sequence, find the CALLSEQ_START node that initiates the call sequence. 392static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 393 assert(Node && "Didn't find callseq_start for a call??"); 394 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 395 396 assert(Node->getOperand(0).getValueType() == MVT::Other && 397 "Node doesn't have a token chain argument!"); 398 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 399} 400 401/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 402/// see if any uses can reach Dest. If no dest operands can get to dest, 403/// legalize them, legalize ourself, and return false, otherwise, return true. 404/// 405/// Keep track of the nodes we fine that actually do lead to Dest in 406/// NodesLeadingTo. This avoids retraversing them exponential number of times. 407/// 408bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 409 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 410 if (N == Dest) return true; // N certainly leads to Dest :) 411 412 // If we've already processed this node and it does lead to Dest, there is no 413 // need to reprocess it. 414 if (NodesLeadingTo.count(N)) return true; 415 416 // If the first result of this node has been already legalized, then it cannot 417 // reach N. 418 switch (getTypeAction(N->getValueType(0))) { 419 case Legal: 420 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 421 break; 422 case Promote: 423 if (PromotedNodes.count(SDOperand(N, 0))) return false; 424 break; 425 case Expand: 426 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 427 break; 428 } 429 430 // Okay, this node has not already been legalized. Check and legalize all 431 // operands. If none lead to Dest, then we can legalize this node. 432 bool OperandsLeadToDest = false; 433 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 434 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 435 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 436 437 if (OperandsLeadToDest) { 438 NodesLeadingTo.insert(N); 439 return true; 440 } 441 442 // Okay, this node looks safe, legalize it and return false. 443 HandleOp(SDOperand(N, 0)); 444 return false; 445} 446 447/// HandleOp - Legalize, Promote, or Expand the specified operand as 448/// appropriate for its type. 449void SelectionDAGLegalize::HandleOp(SDOperand Op) { 450 MVT::ValueType VT = Op.getValueType(); 451 switch (getTypeAction(VT)) { 452 default: assert(0 && "Bad type action!"); 453 case Legal: (void)LegalizeOp(Op); break; 454 case Promote: (void)PromoteOp(Op); break; 455 case Expand: 456 if (!MVT::isVector(VT)) { 457 // If this is an illegal scalar, expand it into its two component 458 // pieces. 459 SDOperand X, Y; 460 if (Op.getOpcode() == ISD::TargetConstant) 461 break; // Allow illegal target nodes. 462 ExpandOp(Op, X, Y); 463 } else if (MVT::getVectorNumElements(VT) == 1) { 464 // If this is an illegal single element vector, convert it to a 465 // scalar operation. 466 (void)ScalarizeVectorOp(Op); 467 } else { 468 // Otherwise, this is an illegal multiple element vector. 469 // Split it in half and legalize both parts. 470 SDOperand X, Y; 471 SplitVectorOp(Op, X, Y); 472 } 473 break; 474 } 475} 476 477/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 478/// a load from the constant pool. 479static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 480 SelectionDAG &DAG, TargetLowering &TLI) { 481 bool Extend = false; 482 483 // If a FP immediate is precise when represented as a float and if the 484 // target can do an extending load from float to double, we put it into 485 // the constant pool as a float, even if it's is statically typed as a 486 // double. 487 MVT::ValueType VT = CFP->getValueType(0); 488 bool isDouble = VT == MVT::f64; 489 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 490 Type::FloatTy, CFP->getValueAPF()); 491 if (!UseCP) { 492 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(), 493 isDouble ? MVT::i64 : MVT::i32); 494 } 495 496 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) && 497 // Only do this if the target has a native EXTLOAD instruction from f32. 498 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 499 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 500 VT = MVT::f32; 501 Extend = true; 502 } 503 504 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 505 if (Extend) { 506 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 507 CPIdx, NULL, 0, MVT::f32); 508 } else { 509 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 510 } 511} 512 513 514/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 515/// operations. 516static 517SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 518 SelectionDAG &DAG, TargetLowering &TLI) { 519 MVT::ValueType VT = Node->getValueType(0); 520 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 521 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 522 "fcopysign expansion only supported for f32 and f64"); 523 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 524 525 // First get the sign bit of second operand. 526 SDOperand Mask1 = (SrcVT == MVT::f64) 527 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 528 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 529 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 530 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 531 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 532 // Shift right or sign-extend it if the two operands have different types. 533 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 534 if (SizeDiff > 0) { 535 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 536 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 537 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 538 } else if (SizeDiff < 0) 539 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 540 541 // Clear the sign bit of first operand. 542 SDOperand Mask2 = (VT == MVT::f64) 543 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 544 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 545 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 546 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 547 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 548 549 // Or the value with the sign bit. 550 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 551 return Result; 552} 553 554/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 555static 556SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 557 TargetLowering &TLI) { 558 SDOperand Chain = ST->getChain(); 559 SDOperand Ptr = ST->getBasePtr(); 560 SDOperand Val = ST->getValue(); 561 MVT::ValueType VT = Val.getValueType(); 562 int Alignment = ST->getAlignment(); 563 int SVOffset = ST->getSrcValueOffset(); 564 if (MVT::isFloatingPoint(ST->getStoredVT())) { 565 // Expand to a bitconvert of the value to the integer type of the 566 // same size, then a (misaligned) int store. 567 MVT::ValueType intVT; 568 if (VT==MVT::f64) 569 intVT = MVT::i64; 570 else if (VT==MVT::f32) 571 intVT = MVT::i32; 572 else 573 assert(0 && "Unaligned load of unsupported floating point type"); 574 575 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 576 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 577 SVOffset, ST->isVolatile(), Alignment); 578 } 579 assert(MVT::isInteger(ST->getStoredVT()) && 580 "Unaligned store of unknown type."); 581 // Get the half-size VT 582 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1; 583 int NumBits = MVT::getSizeInBits(NewStoredVT); 584 int IncrementSize = NumBits / 8; 585 586 // Divide the stored value in two parts. 587 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 588 SDOperand Lo = Val; 589 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 590 591 // Store the two parts 592 SDOperand Store1, Store2; 593 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 594 ST->getSrcValue(), SVOffset, NewStoredVT, 595 ST->isVolatile(), Alignment); 596 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 597 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 598 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 599 ST->getSrcValue(), SVOffset + IncrementSize, 600 NewStoredVT, ST->isVolatile(), Alignment); 601 602 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 603} 604 605/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 606static 607SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 608 TargetLowering &TLI) { 609 int SVOffset = LD->getSrcValueOffset(); 610 SDOperand Chain = LD->getChain(); 611 SDOperand Ptr = LD->getBasePtr(); 612 MVT::ValueType VT = LD->getValueType(0); 613 MVT::ValueType LoadedVT = LD->getLoadedVT(); 614 if (MVT::isFloatingPoint(VT)) { 615 // Expand to a (misaligned) integer load of the same size, 616 // then bitconvert to floating point. 617 MVT::ValueType intVT; 618 if (LoadedVT==MVT::f64) 619 intVT = MVT::i64; 620 else if (LoadedVT==MVT::f32) 621 intVT = MVT::i32; 622 else 623 assert(0 && "Unaligned load of unsupported floating point type"); 624 625 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 626 SVOffset, LD->isVolatile(), 627 LD->getAlignment()); 628 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 629 if (LoadedVT != VT) 630 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 631 632 SDOperand Ops[] = { Result, Chain }; 633 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 634 Ops, 2); 635 } 636 assert(MVT::isInteger(LoadedVT) && "Unaligned load of unsupported type."); 637 MVT::ValueType NewLoadedVT = LoadedVT - 1; 638 int NumBits = MVT::getSizeInBits(NewLoadedVT); 639 int Alignment = LD->getAlignment(); 640 int IncrementSize = NumBits / 8; 641 ISD::LoadExtType HiExtType = LD->getExtensionType(); 642 643 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 644 if (HiExtType == ISD::NON_EXTLOAD) 645 HiExtType = ISD::ZEXTLOAD; 646 647 // Load the value in two parts 648 SDOperand Lo, Hi; 649 if (TLI.isLittleEndian()) { 650 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 651 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 652 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 653 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 654 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 655 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 656 Alignment); 657 } else { 658 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 659 NewLoadedVT,LD->isVolatile(), Alignment); 660 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 661 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 662 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 663 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 664 Alignment); 665 } 666 667 // aggregate the two parts 668 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 669 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 670 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 671 672 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 673 Hi.getValue(1)); 674 675 SDOperand Ops[] = { Result, TF }; 676 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 677} 678 679/// LegalizeOp - We know that the specified value has a legal type, and 680/// that its operands are legal. Now ensure that the operation itself 681/// is legal, recursively ensuring that the operands' operations remain 682/// legal. 683SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 684 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 685 return Op; 686 687 assert(isTypeLegal(Op.getValueType()) && 688 "Caller should expand or promote operands that are not legal!"); 689 SDNode *Node = Op.Val; 690 691 // If this operation defines any values that cannot be represented in a 692 // register on this target, make sure to expand or promote them. 693 if (Node->getNumValues() > 1) { 694 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 695 if (getTypeAction(Node->getValueType(i)) != Legal) { 696 HandleOp(Op.getValue(i)); 697 assert(LegalizedNodes.count(Op) && 698 "Handling didn't add legal operands!"); 699 return LegalizedNodes[Op]; 700 } 701 } 702 703 // Note that LegalizeOp may be reentered even from single-use nodes, which 704 // means that we always must cache transformed nodes. 705 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 706 if (I != LegalizedNodes.end()) return I->second; 707 708 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 709 SDOperand Result = Op; 710 bool isCustom = false; 711 712 switch (Node->getOpcode()) { 713 case ISD::FrameIndex: 714 case ISD::EntryToken: 715 case ISD::Register: 716 case ISD::BasicBlock: 717 case ISD::TargetFrameIndex: 718 case ISD::TargetJumpTable: 719 case ISD::TargetConstant: 720 case ISD::TargetConstantFP: 721 case ISD::TargetConstantPool: 722 case ISD::TargetGlobalAddress: 723 case ISD::TargetGlobalTLSAddress: 724 case ISD::TargetExternalSymbol: 725 case ISD::VALUETYPE: 726 case ISD::SRCVALUE: 727 case ISD::STRING: 728 case ISD::CONDCODE: 729 // Primitives must all be legal. 730 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 731 "This must be legal!"); 732 break; 733 default: 734 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 735 // If this is a target node, legalize it by legalizing the operands then 736 // passing it through. 737 SmallVector<SDOperand, 8> Ops; 738 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 739 Ops.push_back(LegalizeOp(Node->getOperand(i))); 740 741 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 742 743 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 744 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 745 return Result.getValue(Op.ResNo); 746 } 747 // Otherwise this is an unhandled builtin node. splat. 748#ifndef NDEBUG 749 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 750#endif 751 assert(0 && "Do not know how to legalize this operator!"); 752 abort(); 753 case ISD::GLOBAL_OFFSET_TABLE: 754 case ISD::GlobalAddress: 755 case ISD::GlobalTLSAddress: 756 case ISD::ExternalSymbol: 757 case ISD::ConstantPool: 758 case ISD::JumpTable: // Nothing to do. 759 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 760 default: assert(0 && "This action is not supported yet!"); 761 case TargetLowering::Custom: 762 Tmp1 = TLI.LowerOperation(Op, DAG); 763 if (Tmp1.Val) Result = Tmp1; 764 // FALLTHROUGH if the target doesn't want to lower this op after all. 765 case TargetLowering::Legal: 766 break; 767 } 768 break; 769 case ISD::FRAMEADDR: 770 case ISD::RETURNADDR: 771 // The only option for these nodes is to custom lower them. If the target 772 // does not custom lower them, then return zero. 773 Tmp1 = TLI.LowerOperation(Op, DAG); 774 if (Tmp1.Val) 775 Result = Tmp1; 776 else 777 Result = DAG.getConstant(0, TLI.getPointerTy()); 778 break; 779 case ISD::FRAME_TO_ARGS_OFFSET: { 780 MVT::ValueType VT = Node->getValueType(0); 781 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 782 default: assert(0 && "This action is not supported yet!"); 783 case TargetLowering::Custom: 784 Result = TLI.LowerOperation(Op, DAG); 785 if (Result.Val) break; 786 // Fall Thru 787 case TargetLowering::Legal: 788 Result = DAG.getConstant(0, VT); 789 break; 790 } 791 } 792 break; 793 case ISD::EXCEPTIONADDR: { 794 Tmp1 = LegalizeOp(Node->getOperand(0)); 795 MVT::ValueType VT = Node->getValueType(0); 796 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 797 default: assert(0 && "This action is not supported yet!"); 798 case TargetLowering::Expand: { 799 unsigned Reg = TLI.getExceptionAddressRegister(); 800 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo); 801 } 802 break; 803 case TargetLowering::Custom: 804 Result = TLI.LowerOperation(Op, DAG); 805 if (Result.Val) break; 806 // Fall Thru 807 case TargetLowering::Legal: { 808 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 809 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 810 Ops, 2).getValue(Op.ResNo); 811 break; 812 } 813 } 814 } 815 break; 816 case ISD::EHSELECTION: { 817 Tmp1 = LegalizeOp(Node->getOperand(0)); 818 Tmp2 = LegalizeOp(Node->getOperand(1)); 819 MVT::ValueType VT = Node->getValueType(0); 820 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 821 default: assert(0 && "This action is not supported yet!"); 822 case TargetLowering::Expand: { 823 unsigned Reg = TLI.getExceptionSelectorRegister(); 824 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo); 825 } 826 break; 827 case TargetLowering::Custom: 828 Result = TLI.LowerOperation(Op, DAG); 829 if (Result.Val) break; 830 // Fall Thru 831 case TargetLowering::Legal: { 832 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 833 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 834 Ops, 2).getValue(Op.ResNo); 835 break; 836 } 837 } 838 } 839 break; 840 case ISD::EH_RETURN: { 841 MVT::ValueType VT = Node->getValueType(0); 842 // The only "good" option for this node is to custom lower it. 843 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 844 default: assert(0 && "This action is not supported at all!"); 845 case TargetLowering::Custom: 846 Result = TLI.LowerOperation(Op, DAG); 847 if (Result.Val) break; 848 // Fall Thru 849 case TargetLowering::Legal: 850 // Target does not know, how to lower this, lower to noop 851 Result = LegalizeOp(Node->getOperand(0)); 852 break; 853 } 854 } 855 break; 856 case ISD::AssertSext: 857 case ISD::AssertZext: 858 Tmp1 = LegalizeOp(Node->getOperand(0)); 859 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 860 break; 861 case ISD::MERGE_VALUES: 862 // Legalize eliminates MERGE_VALUES nodes. 863 Result = Node->getOperand(Op.ResNo); 864 break; 865 case ISD::CopyFromReg: 866 Tmp1 = LegalizeOp(Node->getOperand(0)); 867 Result = Op.getValue(0); 868 if (Node->getNumValues() == 2) { 869 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 870 } else { 871 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 872 if (Node->getNumOperands() == 3) { 873 Tmp2 = LegalizeOp(Node->getOperand(2)); 874 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 875 } else { 876 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 877 } 878 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 879 } 880 // Since CopyFromReg produces two values, make sure to remember that we 881 // legalized both of them. 882 AddLegalizedOperand(Op.getValue(0), Result); 883 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 884 return Result.getValue(Op.ResNo); 885 case ISD::UNDEF: { 886 MVT::ValueType VT = Op.getValueType(); 887 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 888 default: assert(0 && "This action is not supported yet!"); 889 case TargetLowering::Expand: 890 if (MVT::isInteger(VT)) 891 Result = DAG.getConstant(0, VT); 892 else if (MVT::isFloatingPoint(VT)) 893 Result = DAG.getConstantFP(0, VT); 894 else 895 assert(0 && "Unknown value type!"); 896 break; 897 case TargetLowering::Legal: 898 break; 899 } 900 break; 901 } 902 903 case ISD::INTRINSIC_W_CHAIN: 904 case ISD::INTRINSIC_WO_CHAIN: 905 case ISD::INTRINSIC_VOID: { 906 SmallVector<SDOperand, 8> Ops; 907 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 908 Ops.push_back(LegalizeOp(Node->getOperand(i))); 909 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 910 911 // Allow the target to custom lower its intrinsics if it wants to. 912 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 913 TargetLowering::Custom) { 914 Tmp3 = TLI.LowerOperation(Result, DAG); 915 if (Tmp3.Val) Result = Tmp3; 916 } 917 918 if (Result.Val->getNumValues() == 1) break; 919 920 // Must have return value and chain result. 921 assert(Result.Val->getNumValues() == 2 && 922 "Cannot return more than two values!"); 923 924 // Since loads produce two values, make sure to remember that we 925 // legalized both of them. 926 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 927 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 928 return Result.getValue(Op.ResNo); 929 } 930 931 case ISD::LOCATION: 932 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 933 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 934 935 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 936 case TargetLowering::Promote: 937 default: assert(0 && "This action is not supported yet!"); 938 case TargetLowering::Expand: { 939 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 940 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 941 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 942 943 if (MMI && (useDEBUG_LOC || useLABEL)) { 944 const std::string &FName = 945 cast<StringSDNode>(Node->getOperand(3))->getValue(); 946 const std::string &DirName = 947 cast<StringSDNode>(Node->getOperand(4))->getValue(); 948 unsigned SrcFile = MMI->RecordSource(DirName, FName); 949 950 SmallVector<SDOperand, 8> Ops; 951 Ops.push_back(Tmp1); // chain 952 SDOperand LineOp = Node->getOperand(1); 953 SDOperand ColOp = Node->getOperand(2); 954 955 if (useDEBUG_LOC) { 956 Ops.push_back(LineOp); // line # 957 Ops.push_back(ColOp); // col # 958 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 959 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 960 } else { 961 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 962 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 963 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile); 964 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 965 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size()); 966 } 967 } else { 968 Result = Tmp1; // chain 969 } 970 break; 971 } 972 case TargetLowering::Legal: 973 if (Tmp1 != Node->getOperand(0) || 974 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 975 SmallVector<SDOperand, 8> Ops; 976 Ops.push_back(Tmp1); 977 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 978 Ops.push_back(Node->getOperand(1)); // line # must be legal. 979 Ops.push_back(Node->getOperand(2)); // col # must be legal. 980 } else { 981 // Otherwise promote them. 982 Ops.push_back(PromoteOp(Node->getOperand(1))); 983 Ops.push_back(PromoteOp(Node->getOperand(2))); 984 } 985 Ops.push_back(Node->getOperand(3)); // filename must be legal. 986 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 987 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 988 } 989 break; 990 } 991 break; 992 993 case ISD::DEBUG_LOC: 994 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 995 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 996 default: assert(0 && "This action is not supported yet!"); 997 case TargetLowering::Legal: 998 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 999 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1000 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1001 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1002 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1003 break; 1004 } 1005 break; 1006 1007 case ISD::LABEL: 1008 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!"); 1009 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1010 default: assert(0 && "This action is not supported yet!"); 1011 case TargetLowering::Legal: 1012 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1013 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1014 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1015 break; 1016 case TargetLowering::Expand: 1017 Result = LegalizeOp(Node->getOperand(0)); 1018 break; 1019 } 1020 break; 1021 1022 case ISD::Constant: { 1023 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1024 unsigned opAction = 1025 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1026 1027 // We know we don't need to expand constants here, constants only have one 1028 // value and we check that it is fine above. 1029 1030 if (opAction == TargetLowering::Custom) { 1031 Tmp1 = TLI.LowerOperation(Result, DAG); 1032 if (Tmp1.Val) 1033 Result = Tmp1; 1034 } 1035 break; 1036 } 1037 case ISD::ConstantFP: { 1038 // Spill FP immediates to the constant pool if the target cannot directly 1039 // codegen them. Targets often have some immediate values that can be 1040 // efficiently generated into an FP register without a load. We explicitly 1041 // leave these constants as ConstantFP nodes for the target to deal with. 1042 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1043 1044 // Check to see if this FP immediate is already legal. 1045 bool isLegal = false; 1046 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1047 E = TLI.legal_fpimm_end(); I != E; ++I) 1048 if (CFP->isExactlyValue(*I)) { 1049 isLegal = true; 1050 break; 1051 } 1052 1053 // If this is a legal constant, turn it into a TargetConstantFP node. 1054 if (isLegal) { 1055 Result = DAG.getTargetConstantFP(CFP->getValueAPF(), 1056 CFP->getValueType(0)); 1057 break; 1058 } 1059 1060 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1061 default: assert(0 && "This action is not supported yet!"); 1062 case TargetLowering::Custom: 1063 Tmp3 = TLI.LowerOperation(Result, DAG); 1064 if (Tmp3.Val) { 1065 Result = Tmp3; 1066 break; 1067 } 1068 // FALLTHROUGH 1069 case TargetLowering::Expand: 1070 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1071 } 1072 break; 1073 } 1074 case ISD::TokenFactor: 1075 if (Node->getNumOperands() == 2) { 1076 Tmp1 = LegalizeOp(Node->getOperand(0)); 1077 Tmp2 = LegalizeOp(Node->getOperand(1)); 1078 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1079 } else if (Node->getNumOperands() == 3) { 1080 Tmp1 = LegalizeOp(Node->getOperand(0)); 1081 Tmp2 = LegalizeOp(Node->getOperand(1)); 1082 Tmp3 = LegalizeOp(Node->getOperand(2)); 1083 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1084 } else { 1085 SmallVector<SDOperand, 8> Ops; 1086 // Legalize the operands. 1087 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1088 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1089 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1090 } 1091 break; 1092 1093 case ISD::FORMAL_ARGUMENTS: 1094 case ISD::CALL: 1095 // The only option for this is to custom lower it. 1096 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1097 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1098 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() && 1099 "Lowering call/formal_arguments produced unexpected # results!"); 1100 1101 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1102 // remember that we legalized all of them, so it doesn't get relegalized. 1103 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1104 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1105 if (Op.ResNo == i) 1106 Tmp2 = Tmp1; 1107 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1108 } 1109 return Tmp2; 1110 case ISD::EXTRACT_SUBREG: { 1111 Tmp1 = LegalizeOp(Node->getOperand(0)); 1112 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1113 assert(idx && "Operand must be a constant"); 1114 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1116 } 1117 break; 1118 case ISD::INSERT_SUBREG: { 1119 Tmp1 = LegalizeOp(Node->getOperand(0)); 1120 Tmp2 = LegalizeOp(Node->getOperand(1)); 1121 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1122 assert(idx && "Operand must be a constant"); 1123 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1124 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1125 } 1126 break; 1127 case ISD::BUILD_VECTOR: 1128 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1129 default: assert(0 && "This action is not supported yet!"); 1130 case TargetLowering::Custom: 1131 Tmp3 = TLI.LowerOperation(Result, DAG); 1132 if (Tmp3.Val) { 1133 Result = Tmp3; 1134 break; 1135 } 1136 // FALLTHROUGH 1137 case TargetLowering::Expand: 1138 Result = ExpandBUILD_VECTOR(Result.Val); 1139 break; 1140 } 1141 break; 1142 case ISD::INSERT_VECTOR_ELT: 1143 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1144 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 1145 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1146 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1147 1148 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1149 Node->getValueType(0))) { 1150 default: assert(0 && "This action is not supported yet!"); 1151 case TargetLowering::Legal: 1152 break; 1153 case TargetLowering::Custom: 1154 Tmp3 = TLI.LowerOperation(Result, DAG); 1155 if (Tmp3.Val) { 1156 Result = Tmp3; 1157 break; 1158 } 1159 // FALLTHROUGH 1160 case TargetLowering::Expand: { 1161 // If the insert index is a constant, codegen this as a scalar_to_vector, 1162 // then a shuffle that inserts it into the right position in the vector. 1163 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1164 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1165 Tmp1.getValueType(), Tmp2); 1166 1167 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1168 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1169 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1170 1171 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 1172 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 1173 // the RHS. 1174 SmallVector<SDOperand, 8> ShufOps; 1175 for (unsigned i = 0; i != NumElts; ++i) { 1176 if (i != InsertPos->getValue()) 1177 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1178 else 1179 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1180 } 1181 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1182 &ShufOps[0], ShufOps.size()); 1183 1184 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1185 Tmp1, ScVec, ShufMask); 1186 Result = LegalizeOp(Result); 1187 break; 1188 } 1189 1190 // If the target doesn't support this, we have to spill the input vector 1191 // to a temporary stack slot, update the element, then reload it. This is 1192 // badness. We could also load the value into a vector register (either 1193 // with a "move to register" or "extload into register" instruction, then 1194 // permute it into place, if the idx is a constant and if the idx is 1195 // supported by the target. 1196 MVT::ValueType VT = Tmp1.getValueType(); 1197 MVT::ValueType EltVT = Tmp2.getValueType(); 1198 MVT::ValueType IdxVT = Tmp3.getValueType(); 1199 MVT::ValueType PtrVT = TLI.getPointerTy(); 1200 SDOperand StackPtr = CreateStackTemporary(VT); 1201 // Store the vector. 1202 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); 1203 1204 // Truncate or zero extend offset to target pointer type. 1205 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1206 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1207 // Add the offset to the index. 1208 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1209 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1210 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1211 // Store the scalar value. 1212 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); 1213 // Load the updated vector. 1214 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 1215 break; 1216 } 1217 } 1218 break; 1219 case ISD::SCALAR_TO_VECTOR: 1220 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1221 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1222 break; 1223 } 1224 1225 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1226 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1227 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1228 Node->getValueType(0))) { 1229 default: assert(0 && "This action is not supported yet!"); 1230 case TargetLowering::Legal: 1231 break; 1232 case TargetLowering::Custom: 1233 Tmp3 = TLI.LowerOperation(Result, DAG); 1234 if (Tmp3.Val) { 1235 Result = Tmp3; 1236 break; 1237 } 1238 // FALLTHROUGH 1239 case TargetLowering::Expand: 1240 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1241 break; 1242 } 1243 break; 1244 case ISD::VECTOR_SHUFFLE: 1245 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1246 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1247 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1248 1249 // Allow targets to custom lower the SHUFFLEs they support. 1250 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1251 default: assert(0 && "Unknown operation action!"); 1252 case TargetLowering::Legal: 1253 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1254 "vector shuffle should not be created if not legal!"); 1255 break; 1256 case TargetLowering::Custom: 1257 Tmp3 = TLI.LowerOperation(Result, DAG); 1258 if (Tmp3.Val) { 1259 Result = Tmp3; 1260 break; 1261 } 1262 // FALLTHROUGH 1263 case TargetLowering::Expand: { 1264 MVT::ValueType VT = Node->getValueType(0); 1265 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1266 MVT::ValueType PtrVT = TLI.getPointerTy(); 1267 SDOperand Mask = Node->getOperand(2); 1268 unsigned NumElems = Mask.getNumOperands(); 1269 SmallVector<SDOperand,8> Ops; 1270 for (unsigned i = 0; i != NumElems; ++i) { 1271 SDOperand Arg = Mask.getOperand(i); 1272 if (Arg.getOpcode() == ISD::UNDEF) { 1273 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1274 } else { 1275 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1276 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1277 if (Idx < NumElems) 1278 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1279 DAG.getConstant(Idx, PtrVT))); 1280 else 1281 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1282 DAG.getConstant(Idx - NumElems, PtrVT))); 1283 } 1284 } 1285 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1286 break; 1287 } 1288 case TargetLowering::Promote: { 1289 // Change base type to a different vector type. 1290 MVT::ValueType OVT = Node->getValueType(0); 1291 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1292 1293 // Cast the two input vectors. 1294 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1295 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1296 1297 // Convert the shuffle mask to the right # elements. 1298 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1299 assert(Tmp3.Val && "Shuffle not legal?"); 1300 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1301 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1302 break; 1303 } 1304 } 1305 break; 1306 1307 case ISD::EXTRACT_VECTOR_ELT: 1308 Tmp1 = Node->getOperand(0); 1309 Tmp2 = LegalizeOp(Node->getOperand(1)); 1310 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1311 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1312 break; 1313 1314 case ISD::EXTRACT_SUBVECTOR: 1315 Tmp1 = Node->getOperand(0); 1316 Tmp2 = LegalizeOp(Node->getOperand(1)); 1317 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1318 Result = ExpandEXTRACT_SUBVECTOR(Result); 1319 break; 1320 1321 case ISD::CALLSEQ_START: { 1322 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1323 1324 // Recursively Legalize all of the inputs of the call end that do not lead 1325 // to this call start. This ensures that any libcalls that need be inserted 1326 // are inserted *before* the CALLSEQ_START. 1327 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1328 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1329 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1330 NodesLeadingTo); 1331 } 1332 1333 // Now that we legalized all of the inputs (which may have inserted 1334 // libcalls) create the new CALLSEQ_START node. 1335 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1336 1337 // Merge in the last call, to ensure that this call start after the last 1338 // call ended. 1339 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1340 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1341 Tmp1 = LegalizeOp(Tmp1); 1342 } 1343 1344 // Do not try to legalize the target-specific arguments (#1+). 1345 if (Tmp1 != Node->getOperand(0)) { 1346 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1347 Ops[0] = Tmp1; 1348 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1349 } 1350 1351 // Remember that the CALLSEQ_START is legalized. 1352 AddLegalizedOperand(Op.getValue(0), Result); 1353 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1354 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1355 1356 // Now that the callseq_start and all of the non-call nodes above this call 1357 // sequence have been legalized, legalize the call itself. During this 1358 // process, no libcalls can/will be inserted, guaranteeing that no calls 1359 // can overlap. 1360 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1361 SDOperand InCallSEQ = LastCALLSEQ_END; 1362 // Note that we are selecting this call! 1363 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1364 IsLegalizingCall = true; 1365 1366 // Legalize the call, starting from the CALLSEQ_END. 1367 LegalizeOp(LastCALLSEQ_END); 1368 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1369 return Result; 1370 } 1371 case ISD::CALLSEQ_END: 1372 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1373 // will cause this node to be legalized as well as handling libcalls right. 1374 if (LastCALLSEQ_END.Val != Node) { 1375 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1376 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1377 assert(I != LegalizedNodes.end() && 1378 "Legalizing the call start should have legalized this node!"); 1379 return I->second; 1380 } 1381 1382 // Otherwise, the call start has been legalized and everything is going 1383 // according to plan. Just legalize ourselves normally here. 1384 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1385 // Do not try to legalize the target-specific arguments (#1+), except for 1386 // an optional flag input. 1387 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1388 if (Tmp1 != Node->getOperand(0)) { 1389 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1390 Ops[0] = Tmp1; 1391 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1392 } 1393 } else { 1394 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1395 if (Tmp1 != Node->getOperand(0) || 1396 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1397 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1398 Ops[0] = Tmp1; 1399 Ops.back() = Tmp2; 1400 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1401 } 1402 } 1403 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1404 // This finishes up call legalization. 1405 IsLegalizingCall = false; 1406 1407 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1408 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1409 if (Node->getNumValues() == 2) 1410 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1411 return Result.getValue(Op.ResNo); 1412 case ISD::DYNAMIC_STACKALLOC: { 1413 MVT::ValueType VT = Node->getValueType(0); 1414 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1415 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1416 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1417 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1418 1419 Tmp1 = Result.getValue(0); 1420 Tmp2 = Result.getValue(1); 1421 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1422 default: assert(0 && "This action is not supported yet!"); 1423 case TargetLowering::Expand: { 1424 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1425 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1426 " not tell us which reg is the stack pointer!"); 1427 SDOperand Chain = Tmp1.getOperand(0); 1428 SDOperand Size = Tmp2.getOperand(1); 1429 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1430 Chain = SP.getValue(1); 1431 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1432 unsigned StackAlign = 1433 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1434 if (Align > StackAlign) 1435 SP = DAG.getNode(ISD::AND, VT, SP, 1436 DAG.getConstant(-(uint64_t)Align, VT)); 1437 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1438 Tmp2 = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1439 Tmp1 = LegalizeOp(Tmp1); 1440 Tmp2 = LegalizeOp(Tmp2); 1441 break; 1442 } 1443 case TargetLowering::Custom: 1444 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1445 if (Tmp3.Val) { 1446 Tmp1 = LegalizeOp(Tmp3); 1447 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1448 } 1449 break; 1450 case TargetLowering::Legal: 1451 break; 1452 } 1453 // Since this op produce two values, make sure to remember that we 1454 // legalized both of them. 1455 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1456 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1457 return Op.ResNo ? Tmp2 : Tmp1; 1458 } 1459 case ISD::INLINEASM: { 1460 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1461 bool Changed = false; 1462 // Legalize all of the operands of the inline asm, in case they are nodes 1463 // that need to be expanded or something. Note we skip the asm string and 1464 // all of the TargetConstant flags. 1465 SDOperand Op = LegalizeOp(Ops[0]); 1466 Changed = Op != Ops[0]; 1467 Ops[0] = Op; 1468 1469 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1470 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1471 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1472 for (++i; NumVals; ++i, --NumVals) { 1473 SDOperand Op = LegalizeOp(Ops[i]); 1474 if (Op != Ops[i]) { 1475 Changed = true; 1476 Ops[i] = Op; 1477 } 1478 } 1479 } 1480 1481 if (HasInFlag) { 1482 Op = LegalizeOp(Ops.back()); 1483 Changed |= Op != Ops.back(); 1484 Ops.back() = Op; 1485 } 1486 1487 if (Changed) 1488 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1489 1490 // INLINE asm returns a chain and flag, make sure to add both to the map. 1491 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1492 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1493 return Result.getValue(Op.ResNo); 1494 } 1495 case ISD::BR: 1496 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1497 // Ensure that libcalls are emitted before a branch. 1498 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1499 Tmp1 = LegalizeOp(Tmp1); 1500 LastCALLSEQ_END = DAG.getEntryNode(); 1501 1502 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1503 break; 1504 case ISD::BRIND: 1505 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1506 // Ensure that libcalls are emitted before a branch. 1507 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1508 Tmp1 = LegalizeOp(Tmp1); 1509 LastCALLSEQ_END = DAG.getEntryNode(); 1510 1511 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1512 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1513 case Legal: 1514 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1515 break; 1516 } 1517 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1518 break; 1519 case ISD::BR_JT: 1520 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1521 // Ensure that libcalls are emitted before a branch. 1522 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1523 Tmp1 = LegalizeOp(Tmp1); 1524 LastCALLSEQ_END = DAG.getEntryNode(); 1525 1526 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1527 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1528 1529 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1530 default: assert(0 && "This action is not supported yet!"); 1531 case TargetLowering::Legal: break; 1532 case TargetLowering::Custom: 1533 Tmp1 = TLI.LowerOperation(Result, DAG); 1534 if (Tmp1.Val) Result = Tmp1; 1535 break; 1536 case TargetLowering::Expand: { 1537 SDOperand Chain = Result.getOperand(0); 1538 SDOperand Table = Result.getOperand(1); 1539 SDOperand Index = Result.getOperand(2); 1540 1541 MVT::ValueType PTy = TLI.getPointerTy(); 1542 MachineFunction &MF = DAG.getMachineFunction(); 1543 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1544 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1545 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1546 1547 SDOperand LD; 1548 switch (EntrySize) { 1549 default: assert(0 && "Size of jump table not supported yet."); break; 1550 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; 1551 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; 1552 } 1553 1554 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1555 // For PIC, the sequence is: 1556 // BRIND(load(Jumptable + index) + RelocBase) 1557 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha 1558 SDOperand Reloc; 1559 if (TLI.usesGlobalOffsetTable()) 1560 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy); 1561 else 1562 Reloc = Table; 1563 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD; 1564 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc); 1565 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1566 } else { 1567 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD); 1568 } 1569 } 1570 } 1571 break; 1572 case ISD::BRCOND: 1573 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1574 // Ensure that libcalls are emitted before a return. 1575 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1576 Tmp1 = LegalizeOp(Tmp1); 1577 LastCALLSEQ_END = DAG.getEntryNode(); 1578 1579 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1580 case Expand: assert(0 && "It's impossible to expand bools"); 1581 case Legal: 1582 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1583 break; 1584 case Promote: 1585 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1586 1587 // The top bits of the promoted condition are not necessarily zero, ensure 1588 // that the value is properly zero extended. 1589 if (!DAG.MaskedValueIsZero(Tmp2, 1590 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1591 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1592 break; 1593 } 1594 1595 // Basic block destination (Op#2) is always legal. 1596 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1597 1598 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1599 default: assert(0 && "This action is not supported yet!"); 1600 case TargetLowering::Legal: break; 1601 case TargetLowering::Custom: 1602 Tmp1 = TLI.LowerOperation(Result, DAG); 1603 if (Tmp1.Val) Result = Tmp1; 1604 break; 1605 case TargetLowering::Expand: 1606 // Expand brcond's setcc into its constituent parts and create a BR_CC 1607 // Node. 1608 if (Tmp2.getOpcode() == ISD::SETCC) { 1609 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1610 Tmp2.getOperand(0), Tmp2.getOperand(1), 1611 Node->getOperand(2)); 1612 } else { 1613 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1614 DAG.getCondCode(ISD::SETNE), Tmp2, 1615 DAG.getConstant(0, Tmp2.getValueType()), 1616 Node->getOperand(2)); 1617 } 1618 break; 1619 } 1620 break; 1621 case ISD::BR_CC: 1622 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1623 // Ensure that libcalls are emitted before a branch. 1624 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1625 Tmp1 = LegalizeOp(Tmp1); 1626 Tmp2 = Node->getOperand(2); // LHS 1627 Tmp3 = Node->getOperand(3); // RHS 1628 Tmp4 = Node->getOperand(1); // CC 1629 1630 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1631 LastCALLSEQ_END = DAG.getEntryNode(); 1632 1633 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1634 // the LHS is a legal SETCC itself. In this case, we need to compare 1635 // the result against zero to select between true and false values. 1636 if (Tmp3.Val == 0) { 1637 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1638 Tmp4 = DAG.getCondCode(ISD::SETNE); 1639 } 1640 1641 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1642 Node->getOperand(4)); 1643 1644 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1645 default: assert(0 && "Unexpected action for BR_CC!"); 1646 case TargetLowering::Legal: break; 1647 case TargetLowering::Custom: 1648 Tmp4 = TLI.LowerOperation(Result, DAG); 1649 if (Tmp4.Val) Result = Tmp4; 1650 break; 1651 } 1652 break; 1653 case ISD::LOAD: { 1654 LoadSDNode *LD = cast<LoadSDNode>(Node); 1655 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1656 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1657 1658 ISD::LoadExtType ExtType = LD->getExtensionType(); 1659 if (ExtType == ISD::NON_EXTLOAD) { 1660 MVT::ValueType VT = Node->getValueType(0); 1661 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1662 Tmp3 = Result.getValue(0); 1663 Tmp4 = Result.getValue(1); 1664 1665 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1666 default: assert(0 && "This action is not supported yet!"); 1667 case TargetLowering::Legal: 1668 // If this is an unaligned load and the target doesn't support it, 1669 // expand it. 1670 if (!TLI.allowsUnalignedMemoryAccesses()) { 1671 unsigned ABIAlignment = TLI.getTargetData()-> 1672 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1673 if (LD->getAlignment() < ABIAlignment){ 1674 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1675 TLI); 1676 Tmp3 = Result.getOperand(0); 1677 Tmp4 = Result.getOperand(1); 1678 Tmp3 = LegalizeOp(Tmp3); 1679 Tmp4 = LegalizeOp(Tmp4); 1680 } 1681 } 1682 break; 1683 case TargetLowering::Custom: 1684 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1685 if (Tmp1.Val) { 1686 Tmp3 = LegalizeOp(Tmp1); 1687 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1688 } 1689 break; 1690 case TargetLowering::Promote: { 1691 // Only promote a load of vector type to another. 1692 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1693 // Change base type to a different vector type. 1694 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1695 1696 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1697 LD->getSrcValueOffset(), 1698 LD->isVolatile(), LD->getAlignment()); 1699 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1700 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1701 break; 1702 } 1703 } 1704 // Since loads produce two values, make sure to remember that we 1705 // legalized both of them. 1706 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1707 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1708 return Op.ResNo ? Tmp4 : Tmp3; 1709 } else { 1710 MVT::ValueType SrcVT = LD->getLoadedVT(); 1711 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1712 default: assert(0 && "This action is not supported yet!"); 1713 case TargetLowering::Promote: 1714 assert(SrcVT == MVT::i1 && 1715 "Can only promote extending LOAD from i1 -> i8!"); 1716 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1717 LD->getSrcValue(), LD->getSrcValueOffset(), 1718 MVT::i8, LD->isVolatile(), LD->getAlignment()); 1719 Tmp1 = Result.getValue(0); 1720 Tmp2 = Result.getValue(1); 1721 break; 1722 case TargetLowering::Custom: 1723 isCustom = true; 1724 // FALLTHROUGH 1725 case TargetLowering::Legal: 1726 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1727 Tmp1 = Result.getValue(0); 1728 Tmp2 = Result.getValue(1); 1729 1730 if (isCustom) { 1731 Tmp3 = TLI.LowerOperation(Result, DAG); 1732 if (Tmp3.Val) { 1733 Tmp1 = LegalizeOp(Tmp3); 1734 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1735 } 1736 } else { 1737 // If this is an unaligned load and the target doesn't support it, 1738 // expand it. 1739 if (!TLI.allowsUnalignedMemoryAccesses()) { 1740 unsigned ABIAlignment = TLI.getTargetData()-> 1741 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1742 if (LD->getAlignment() < ABIAlignment){ 1743 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1744 TLI); 1745 Tmp1 = Result.getOperand(0); 1746 Tmp2 = Result.getOperand(1); 1747 Tmp1 = LegalizeOp(Tmp1); 1748 Tmp2 = LegalizeOp(Tmp2); 1749 } 1750 } 1751 } 1752 break; 1753 case TargetLowering::Expand: 1754 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1755 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1756 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1757 LD->getSrcValueOffset(), 1758 LD->isVolatile(), LD->getAlignment()); 1759 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1760 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1761 Tmp2 = LegalizeOp(Load.getValue(1)); 1762 break; 1763 } 1764 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1765 // Turn the unsupported load into an EXTLOAD followed by an explicit 1766 // zero/sign extend inreg. 1767 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1768 Tmp1, Tmp2, LD->getSrcValue(), 1769 LD->getSrcValueOffset(), SrcVT, 1770 LD->isVolatile(), LD->getAlignment()); 1771 SDOperand ValRes; 1772 if (ExtType == ISD::SEXTLOAD) 1773 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1774 Result, DAG.getValueType(SrcVT)); 1775 else 1776 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1777 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1778 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1779 break; 1780 } 1781 // Since loads produce two values, make sure to remember that we legalized 1782 // both of them. 1783 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1784 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1785 return Op.ResNo ? Tmp2 : Tmp1; 1786 } 1787 } 1788 case ISD::EXTRACT_ELEMENT: { 1789 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1790 switch (getTypeAction(OpTy)) { 1791 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1792 case Legal: 1793 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1794 // 1 -> Hi 1795 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1796 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1797 TLI.getShiftAmountTy())); 1798 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1799 } else { 1800 // 0 -> Lo 1801 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1802 Node->getOperand(0)); 1803 } 1804 break; 1805 case Expand: 1806 // Get both the low and high parts. 1807 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1808 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1809 Result = Tmp2; // 1 -> Hi 1810 else 1811 Result = Tmp1; // 0 -> Lo 1812 break; 1813 } 1814 break; 1815 } 1816 1817 case ISD::CopyToReg: 1818 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1819 1820 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1821 "Register type must be legal!"); 1822 // Legalize the incoming value (must be a legal type). 1823 Tmp2 = LegalizeOp(Node->getOperand(2)); 1824 if (Node->getNumValues() == 1) { 1825 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1826 } else { 1827 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1828 if (Node->getNumOperands() == 4) { 1829 Tmp3 = LegalizeOp(Node->getOperand(3)); 1830 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1831 Tmp3); 1832 } else { 1833 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1834 } 1835 1836 // Since this produces two values, make sure to remember that we legalized 1837 // both of them. 1838 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1839 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1840 return Result; 1841 } 1842 break; 1843 1844 case ISD::RET: 1845 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1846 1847 // Ensure that libcalls are emitted before a return. 1848 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1849 Tmp1 = LegalizeOp(Tmp1); 1850 LastCALLSEQ_END = DAG.getEntryNode(); 1851 1852 switch (Node->getNumOperands()) { 1853 case 3: // ret val 1854 Tmp2 = Node->getOperand(1); 1855 Tmp3 = Node->getOperand(2); // Signness 1856 switch (getTypeAction(Tmp2.getValueType())) { 1857 case Legal: 1858 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1859 break; 1860 case Expand: 1861 if (!MVT::isVector(Tmp2.getValueType())) { 1862 SDOperand Lo, Hi; 1863 ExpandOp(Tmp2, Lo, Hi); 1864 1865 // Big endian systems want the hi reg first. 1866 if (!TLI.isLittleEndian()) 1867 std::swap(Lo, Hi); 1868 1869 if (Hi.Val) 1870 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1871 else 1872 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 1873 Result = LegalizeOp(Result); 1874 } else { 1875 SDNode *InVal = Tmp2.Val; 1876 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 1877 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 1878 1879 // Figure out if there is a simple type corresponding to this Vector 1880 // type. If so, convert to the vector type. 1881 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1882 if (TLI.isTypeLegal(TVT)) { 1883 // Turn this into a return of the vector type. 1884 Tmp2 = LegalizeOp(Tmp2); 1885 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1886 } else if (NumElems == 1) { 1887 // Turn this into a return of the scalar type. 1888 Tmp2 = ScalarizeVectorOp(Tmp2); 1889 Tmp2 = LegalizeOp(Tmp2); 1890 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1891 1892 // FIXME: Returns of gcc generic vectors smaller than a legal type 1893 // should be returned in integer registers! 1894 1895 // The scalarized value type may not be legal, e.g. it might require 1896 // promotion or expansion. Relegalize the return. 1897 Result = LegalizeOp(Result); 1898 } else { 1899 // FIXME: Returns of gcc generic vectors larger than a legal vector 1900 // type should be returned by reference! 1901 SDOperand Lo, Hi; 1902 SplitVectorOp(Tmp2, Lo, Hi); 1903 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1904 Result = LegalizeOp(Result); 1905 } 1906 } 1907 break; 1908 case Promote: 1909 Tmp2 = PromoteOp(Node->getOperand(1)); 1910 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1911 Result = LegalizeOp(Result); 1912 break; 1913 } 1914 break; 1915 case 1: // ret void 1916 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1917 break; 1918 default: { // ret <values> 1919 SmallVector<SDOperand, 8> NewValues; 1920 NewValues.push_back(Tmp1); 1921 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 1922 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1923 case Legal: 1924 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1925 NewValues.push_back(Node->getOperand(i+1)); 1926 break; 1927 case Expand: { 1928 SDOperand Lo, Hi; 1929 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && 1930 "FIXME: TODO: implement returning non-legal vector types!"); 1931 ExpandOp(Node->getOperand(i), Lo, Hi); 1932 NewValues.push_back(Lo); 1933 NewValues.push_back(Node->getOperand(i+1)); 1934 if (Hi.Val) { 1935 NewValues.push_back(Hi); 1936 NewValues.push_back(Node->getOperand(i+1)); 1937 } 1938 break; 1939 } 1940 case Promote: 1941 assert(0 && "Can't promote multiple return value yet!"); 1942 } 1943 1944 if (NewValues.size() == Node->getNumOperands()) 1945 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 1946 else 1947 Result = DAG.getNode(ISD::RET, MVT::Other, 1948 &NewValues[0], NewValues.size()); 1949 break; 1950 } 1951 } 1952 1953 if (Result.getOpcode() == ISD::RET) { 1954 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 1955 default: assert(0 && "This action is not supported yet!"); 1956 case TargetLowering::Legal: break; 1957 case TargetLowering::Custom: 1958 Tmp1 = TLI.LowerOperation(Result, DAG); 1959 if (Tmp1.Val) Result = Tmp1; 1960 break; 1961 } 1962 } 1963 break; 1964 case ISD::STORE: { 1965 StoreSDNode *ST = cast<StoreSDNode>(Node); 1966 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1967 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1968 int SVOffset = ST->getSrcValueOffset(); 1969 unsigned Alignment = ST->getAlignment(); 1970 bool isVolatile = ST->isVolatile(); 1971 1972 if (!ST->isTruncatingStore()) { 1973 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1974 // FIXME: We shouldn't do this for TargetConstantFP's. 1975 // FIXME: move this to the DAG Combiner! Note that we can't regress due 1976 // to phase ordering between legalized code and the dag combiner. This 1977 // probably means that we need to integrate dag combiner and legalizer 1978 // together. 1979 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 1980 if (CFP->getValueType(0) == MVT::f32) { 1981 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF(). 1982 convertToAPInt().getZExtValue(), 1983 MVT::i32); 1984 } else { 1985 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1986 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 1987 getZExtValue(), MVT::i64); 1988 } 1989 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1990 SVOffset, isVolatile, Alignment); 1991 break; 1992 } 1993 1994 switch (getTypeAction(ST->getStoredVT())) { 1995 case Legal: { 1996 Tmp3 = LegalizeOp(ST->getValue()); 1997 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1998 ST->getOffset()); 1999 2000 MVT::ValueType VT = Tmp3.getValueType(); 2001 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2002 default: assert(0 && "This action is not supported yet!"); 2003 case TargetLowering::Legal: 2004 // If this is an unaligned store and the target doesn't support it, 2005 // expand it. 2006 if (!TLI.allowsUnalignedMemoryAccesses()) { 2007 unsigned ABIAlignment = TLI.getTargetData()-> 2008 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2009 if (ST->getAlignment() < ABIAlignment) 2010 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2011 TLI); 2012 } 2013 break; 2014 case TargetLowering::Custom: 2015 Tmp1 = TLI.LowerOperation(Result, DAG); 2016 if (Tmp1.Val) Result = Tmp1; 2017 break; 2018 case TargetLowering::Promote: 2019 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 2020 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2021 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2022 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2023 ST->getSrcValue(), SVOffset, isVolatile, 2024 Alignment); 2025 break; 2026 } 2027 break; 2028 } 2029 case Promote: 2030 // Truncate the value and store the result. 2031 Tmp3 = PromoteOp(ST->getValue()); 2032 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2033 SVOffset, ST->getStoredVT(), 2034 isVolatile, Alignment); 2035 break; 2036 2037 case Expand: 2038 unsigned IncrementSize = 0; 2039 SDOperand Lo, Hi; 2040 2041 // If this is a vector type, then we have to calculate the increment as 2042 // the product of the element size in bytes, and the number of elements 2043 // in the high half of the vector. 2044 if (MVT::isVector(ST->getValue().getValueType())) { 2045 SDNode *InVal = ST->getValue().Val; 2046 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 2047 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 2048 2049 // Figure out if there is a simple type corresponding to this Vector 2050 // type. If so, convert to the vector type. 2051 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2052 if (TLI.isTypeLegal(TVT)) { 2053 // Turn this into a normal store of the vector type. 2054 Tmp3 = LegalizeOp(Node->getOperand(1)); 2055 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2056 SVOffset, isVolatile, Alignment); 2057 Result = LegalizeOp(Result); 2058 break; 2059 } else if (NumElems == 1) { 2060 // Turn this into a normal store of the scalar type. 2061 Tmp3 = ScalarizeVectorOp(Node->getOperand(1)); 2062 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2063 SVOffset, isVolatile, Alignment); 2064 // The scalarized value type may not be legal, e.g. it might require 2065 // promotion or expansion. Relegalize the scalar store. 2066 Result = LegalizeOp(Result); 2067 break; 2068 } else { 2069 SplitVectorOp(Node->getOperand(1), Lo, Hi); 2070 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 2071 } 2072 } else { 2073 ExpandOp(Node->getOperand(1), Lo, Hi); 2074 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 2075 2076 if (!TLI.isLittleEndian()) 2077 std::swap(Lo, Hi); 2078 } 2079 2080 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2081 SVOffset, isVolatile, Alignment); 2082 2083 if (Hi.Val == NULL) { 2084 // Must be int <-> float one-to-one expansion. 2085 Result = Lo; 2086 break; 2087 } 2088 2089 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2090 getIntPtrConstant(IncrementSize)); 2091 assert(isTypeLegal(Tmp2.getValueType()) && 2092 "Pointers must be legal!"); 2093 SVOffset += IncrementSize; 2094 if (Alignment > IncrementSize) 2095 Alignment = IncrementSize; 2096 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2097 SVOffset, isVolatile, Alignment); 2098 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2099 break; 2100 } 2101 } else { 2102 // Truncating store 2103 assert(isTypeLegal(ST->getValue().getValueType()) && 2104 "Cannot handle illegal TRUNCSTORE yet!"); 2105 Tmp3 = LegalizeOp(ST->getValue()); 2106 2107 // The only promote case we handle is TRUNCSTORE:i1 X into 2108 // -> TRUNCSTORE:i8 (and X, 1) 2109 if (ST->getStoredVT() == MVT::i1 && 2110 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) { 2111 // Promote the bool to a mask then store. 2112 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3, 2113 DAG.getConstant(1, Tmp3.getValueType())); 2114 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2115 SVOffset, MVT::i8, 2116 isVolatile, Alignment); 2117 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2118 Tmp2 != ST->getBasePtr()) { 2119 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2120 ST->getOffset()); 2121 } 2122 2123 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT(); 2124 switch (TLI.getStoreXAction(StVT)) { 2125 default: assert(0 && "This action is not supported yet!"); 2126 case TargetLowering::Legal: 2127 // If this is an unaligned store and the target doesn't support it, 2128 // expand it. 2129 if (!TLI.allowsUnalignedMemoryAccesses()) { 2130 unsigned ABIAlignment = TLI.getTargetData()-> 2131 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2132 if (ST->getAlignment() < ABIAlignment) 2133 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2134 TLI); 2135 } 2136 break; 2137 case TargetLowering::Custom: 2138 Tmp1 = TLI.LowerOperation(Result, DAG); 2139 if (Tmp1.Val) Result = Tmp1; 2140 break; 2141 } 2142 } 2143 break; 2144 } 2145 case ISD::PCMARKER: 2146 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2147 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2148 break; 2149 case ISD::STACKSAVE: 2150 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2151 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2152 Tmp1 = Result.getValue(0); 2153 Tmp2 = Result.getValue(1); 2154 2155 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2156 default: assert(0 && "This action is not supported yet!"); 2157 case TargetLowering::Legal: break; 2158 case TargetLowering::Custom: 2159 Tmp3 = TLI.LowerOperation(Result, DAG); 2160 if (Tmp3.Val) { 2161 Tmp1 = LegalizeOp(Tmp3); 2162 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2163 } 2164 break; 2165 case TargetLowering::Expand: 2166 // Expand to CopyFromReg if the target set 2167 // StackPointerRegisterToSaveRestore. 2168 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2169 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2170 Node->getValueType(0)); 2171 Tmp2 = Tmp1.getValue(1); 2172 } else { 2173 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2174 Tmp2 = Node->getOperand(0); 2175 } 2176 break; 2177 } 2178 2179 // Since stacksave produce two values, make sure to remember that we 2180 // legalized both of them. 2181 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2182 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2183 return Op.ResNo ? Tmp2 : Tmp1; 2184 2185 case ISD::STACKRESTORE: 2186 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2187 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2188 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2189 2190 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2191 default: assert(0 && "This action is not supported yet!"); 2192 case TargetLowering::Legal: break; 2193 case TargetLowering::Custom: 2194 Tmp1 = TLI.LowerOperation(Result, DAG); 2195 if (Tmp1.Val) Result = Tmp1; 2196 break; 2197 case TargetLowering::Expand: 2198 // Expand to CopyToReg if the target set 2199 // StackPointerRegisterToSaveRestore. 2200 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2201 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2202 } else { 2203 Result = Tmp1; 2204 } 2205 break; 2206 } 2207 break; 2208 2209 case ISD::READCYCLECOUNTER: 2210 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2211 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2212 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2213 Node->getValueType(0))) { 2214 default: assert(0 && "This action is not supported yet!"); 2215 case TargetLowering::Legal: 2216 Tmp1 = Result.getValue(0); 2217 Tmp2 = Result.getValue(1); 2218 break; 2219 case TargetLowering::Custom: 2220 Result = TLI.LowerOperation(Result, DAG); 2221 Tmp1 = LegalizeOp(Result.getValue(0)); 2222 Tmp2 = LegalizeOp(Result.getValue(1)); 2223 break; 2224 } 2225 2226 // Since rdcc produce two values, make sure to remember that we legalized 2227 // both of them. 2228 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2229 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2230 return Result; 2231 2232 case ISD::SELECT: 2233 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2234 case Expand: assert(0 && "It's impossible to expand bools"); 2235 case Legal: 2236 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2237 break; 2238 case Promote: 2239 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2240 // Make sure the condition is either zero or one. 2241 if (!DAG.MaskedValueIsZero(Tmp1, 2242 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 2243 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2244 break; 2245 } 2246 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2247 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2248 2249 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2250 2251 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2252 default: assert(0 && "This action is not supported yet!"); 2253 case TargetLowering::Legal: break; 2254 case TargetLowering::Custom: { 2255 Tmp1 = TLI.LowerOperation(Result, DAG); 2256 if (Tmp1.Val) Result = Tmp1; 2257 break; 2258 } 2259 case TargetLowering::Expand: 2260 if (Tmp1.getOpcode() == ISD::SETCC) { 2261 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2262 Tmp2, Tmp3, 2263 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2264 } else { 2265 Result = DAG.getSelectCC(Tmp1, 2266 DAG.getConstant(0, Tmp1.getValueType()), 2267 Tmp2, Tmp3, ISD::SETNE); 2268 } 2269 break; 2270 case TargetLowering::Promote: { 2271 MVT::ValueType NVT = 2272 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2273 unsigned ExtOp, TruncOp; 2274 if (MVT::isVector(Tmp2.getValueType())) { 2275 ExtOp = ISD::BIT_CONVERT; 2276 TruncOp = ISD::BIT_CONVERT; 2277 } else if (MVT::isInteger(Tmp2.getValueType())) { 2278 ExtOp = ISD::ANY_EXTEND; 2279 TruncOp = ISD::TRUNCATE; 2280 } else { 2281 ExtOp = ISD::FP_EXTEND; 2282 TruncOp = ISD::FP_ROUND; 2283 } 2284 // Promote each of the values to the new type. 2285 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2286 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2287 // Perform the larger operation, then round down. 2288 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2289 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2290 break; 2291 } 2292 } 2293 break; 2294 case ISD::SELECT_CC: { 2295 Tmp1 = Node->getOperand(0); // LHS 2296 Tmp2 = Node->getOperand(1); // RHS 2297 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2298 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2299 SDOperand CC = Node->getOperand(4); 2300 2301 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2302 2303 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2304 // the LHS is a legal SETCC itself. In this case, we need to compare 2305 // the result against zero to select between true and false values. 2306 if (Tmp2.Val == 0) { 2307 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2308 CC = DAG.getCondCode(ISD::SETNE); 2309 } 2310 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2311 2312 // Everything is legal, see if we should expand this op or something. 2313 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2314 default: assert(0 && "This action is not supported yet!"); 2315 case TargetLowering::Legal: break; 2316 case TargetLowering::Custom: 2317 Tmp1 = TLI.LowerOperation(Result, DAG); 2318 if (Tmp1.Val) Result = Tmp1; 2319 break; 2320 } 2321 break; 2322 } 2323 case ISD::SETCC: 2324 Tmp1 = Node->getOperand(0); 2325 Tmp2 = Node->getOperand(1); 2326 Tmp3 = Node->getOperand(2); 2327 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2328 2329 // If we had to Expand the SetCC operands into a SELECT node, then it may 2330 // not always be possible to return a true LHS & RHS. In this case, just 2331 // return the value we legalized, returned in the LHS 2332 if (Tmp2.Val == 0) { 2333 Result = Tmp1; 2334 break; 2335 } 2336 2337 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2338 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2339 case TargetLowering::Custom: 2340 isCustom = true; 2341 // FALLTHROUGH. 2342 case TargetLowering::Legal: 2343 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2344 if (isCustom) { 2345 Tmp4 = TLI.LowerOperation(Result, DAG); 2346 if (Tmp4.Val) Result = Tmp4; 2347 } 2348 break; 2349 case TargetLowering::Promote: { 2350 // First step, figure out the appropriate operation to use. 2351 // Allow SETCC to not be supported for all legal data types 2352 // Mostly this targets FP 2353 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2354 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2355 2356 // Scan for the appropriate larger type to use. 2357 while (1) { 2358 NewInTy = (MVT::ValueType)(NewInTy+1); 2359 2360 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2361 "Fell off of the edge of the integer world"); 2362 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2363 "Fell off of the edge of the floating point world"); 2364 2365 // If the target supports SETCC of this type, use it. 2366 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2367 break; 2368 } 2369 if (MVT::isInteger(NewInTy)) 2370 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2371 else { 2372 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2373 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2374 } 2375 Tmp1 = LegalizeOp(Tmp1); 2376 Tmp2 = LegalizeOp(Tmp2); 2377 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2378 Result = LegalizeOp(Result); 2379 break; 2380 } 2381 case TargetLowering::Expand: 2382 // Expand a setcc node into a select_cc of the same condition, lhs, and 2383 // rhs that selects between const 1 (true) and const 0 (false). 2384 MVT::ValueType VT = Node->getValueType(0); 2385 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2386 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2387 Tmp3); 2388 break; 2389 } 2390 break; 2391 case ISD::MEMSET: 2392 case ISD::MEMCPY: 2393 case ISD::MEMMOVE: { 2394 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2395 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2396 2397 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2398 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2399 case Expand: assert(0 && "Cannot expand a byte!"); 2400 case Legal: 2401 Tmp3 = LegalizeOp(Node->getOperand(2)); 2402 break; 2403 case Promote: 2404 Tmp3 = PromoteOp(Node->getOperand(2)); 2405 break; 2406 } 2407 } else { 2408 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2409 } 2410 2411 SDOperand Tmp4; 2412 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2413 case Expand: { 2414 // Length is too big, just take the lo-part of the length. 2415 SDOperand HiPart; 2416 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2417 break; 2418 } 2419 case Legal: 2420 Tmp4 = LegalizeOp(Node->getOperand(3)); 2421 break; 2422 case Promote: 2423 Tmp4 = PromoteOp(Node->getOperand(3)); 2424 break; 2425 } 2426 2427 SDOperand Tmp5; 2428 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2429 case Expand: assert(0 && "Cannot expand this yet!"); 2430 case Legal: 2431 Tmp5 = LegalizeOp(Node->getOperand(4)); 2432 break; 2433 case Promote: 2434 Tmp5 = PromoteOp(Node->getOperand(4)); 2435 break; 2436 } 2437 2438 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2439 default: assert(0 && "This action not implemented for this operation!"); 2440 case TargetLowering::Custom: 2441 isCustom = true; 2442 // FALLTHROUGH 2443 case TargetLowering::Legal: 2444 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 2445 if (isCustom) { 2446 Tmp1 = TLI.LowerOperation(Result, DAG); 2447 if (Tmp1.Val) Result = Tmp1; 2448 } 2449 break; 2450 case TargetLowering::Expand: { 2451 // Otherwise, the target does not support this operation. Lower the 2452 // operation to an explicit libcall as appropriate. 2453 MVT::ValueType IntPtr = TLI.getPointerTy(); 2454 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2455 TargetLowering::ArgListTy Args; 2456 TargetLowering::ArgListEntry Entry; 2457 2458 const char *FnName = 0; 2459 if (Node->getOpcode() == ISD::MEMSET) { 2460 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; 2461 Args.push_back(Entry); 2462 // Extend the (previously legalized) ubyte argument to be an int value 2463 // for the call. 2464 if (Tmp3.getValueType() > MVT::i32) 2465 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2466 else 2467 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2468 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 2469 Args.push_back(Entry); 2470 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false; 2471 Args.push_back(Entry); 2472 2473 FnName = "memset"; 2474 } else if (Node->getOpcode() == ISD::MEMCPY || 2475 Node->getOpcode() == ISD::MEMMOVE) { 2476 Entry.Ty = IntPtrTy; 2477 Entry.Node = Tmp2; Args.push_back(Entry); 2478 Entry.Node = Tmp3; Args.push_back(Entry); 2479 Entry.Node = Tmp4; Args.push_back(Entry); 2480 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2481 } else { 2482 assert(0 && "Unknown op!"); 2483 } 2484 2485 std::pair<SDOperand,SDOperand> CallResult = 2486 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 2487 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2488 Result = CallResult.second; 2489 break; 2490 } 2491 } 2492 break; 2493 } 2494 2495 case ISD::SHL_PARTS: 2496 case ISD::SRA_PARTS: 2497 case ISD::SRL_PARTS: { 2498 SmallVector<SDOperand, 8> Ops; 2499 bool Changed = false; 2500 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2501 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2502 Changed |= Ops.back() != Node->getOperand(i); 2503 } 2504 if (Changed) 2505 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2506 2507 switch (TLI.getOperationAction(Node->getOpcode(), 2508 Node->getValueType(0))) { 2509 default: assert(0 && "This action is not supported yet!"); 2510 case TargetLowering::Legal: break; 2511 case TargetLowering::Custom: 2512 Tmp1 = TLI.LowerOperation(Result, DAG); 2513 if (Tmp1.Val) { 2514 SDOperand Tmp2, RetVal(0, 0); 2515 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2516 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2517 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2518 if (i == Op.ResNo) 2519 RetVal = Tmp2; 2520 } 2521 assert(RetVal.Val && "Illegal result number"); 2522 return RetVal; 2523 } 2524 break; 2525 } 2526 2527 // Since these produce multiple values, make sure to remember that we 2528 // legalized all of them. 2529 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2530 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2531 return Result.getValue(Op.ResNo); 2532 } 2533 2534 // Binary operators 2535 case ISD::ADD: 2536 case ISD::SUB: 2537 case ISD::MUL: 2538 case ISD::MULHS: 2539 case ISD::MULHU: 2540 case ISD::UDIV: 2541 case ISD::SDIV: 2542 case ISD::AND: 2543 case ISD::OR: 2544 case ISD::XOR: 2545 case ISD::SHL: 2546 case ISD::SRL: 2547 case ISD::SRA: 2548 case ISD::FADD: 2549 case ISD::FSUB: 2550 case ISD::FMUL: 2551 case ISD::FDIV: 2552 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2553 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2554 case Expand: assert(0 && "Not possible"); 2555 case Legal: 2556 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2557 break; 2558 case Promote: 2559 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2560 break; 2561 } 2562 2563 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2564 2565 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2566 default: assert(0 && "BinOp legalize operation not supported"); 2567 case TargetLowering::Legal: break; 2568 case TargetLowering::Custom: 2569 Tmp1 = TLI.LowerOperation(Result, DAG); 2570 if (Tmp1.Val) Result = Tmp1; 2571 break; 2572 case TargetLowering::Expand: { 2573 if (Node->getValueType(0) == MVT::i32) { 2574 switch (Node->getOpcode()) { 2575 default: assert(0 && "Do not know how to expand this integer BinOp!"); 2576 case ISD::UDIV: 2577 case ISD::SDIV: 2578 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV 2579 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 2580 SDOperand Dummy; 2581 bool isSigned = Node->getOpcode() == ISD::SDIV; 2582 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2583 }; 2584 break; 2585 } 2586 2587 assert(MVT::isVector(Node->getValueType(0)) && 2588 "Cannot expand this binary operator!"); 2589 // Expand the operation into a bunch of nasty scalar code. 2590 SmallVector<SDOperand, 8> Ops; 2591 MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0)); 2592 MVT::ValueType PtrVT = TLI.getPointerTy(); 2593 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0)); 2594 i != e; ++i) { 2595 SDOperand Idx = DAG.getConstant(i, PtrVT); 2596 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx); 2597 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx); 2598 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS)); 2599 } 2600 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), 2601 &Ops[0], Ops.size()); 2602 break; 2603 } 2604 case TargetLowering::Promote: { 2605 switch (Node->getOpcode()) { 2606 default: assert(0 && "Do not know how to promote this BinOp!"); 2607 case ISD::AND: 2608 case ISD::OR: 2609 case ISD::XOR: { 2610 MVT::ValueType OVT = Node->getValueType(0); 2611 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2612 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2613 // Bit convert each of the values to the new type. 2614 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2615 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2616 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2617 // Bit convert the result back the original type. 2618 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2619 break; 2620 } 2621 } 2622 } 2623 } 2624 break; 2625 2626 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2627 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2628 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2629 case Expand: assert(0 && "Not possible"); 2630 case Legal: 2631 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2632 break; 2633 case Promote: 2634 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2635 break; 2636 } 2637 2638 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2639 2640 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2641 default: assert(0 && "Operation not supported"); 2642 case TargetLowering::Custom: 2643 Tmp1 = TLI.LowerOperation(Result, DAG); 2644 if (Tmp1.Val) Result = Tmp1; 2645 break; 2646 case TargetLowering::Legal: break; 2647 case TargetLowering::Expand: { 2648 // If this target supports fabs/fneg natively and select is cheap, 2649 // do this efficiently. 2650 if (!TLI.isSelectExpensive() && 2651 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 2652 TargetLowering::Legal && 2653 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 2654 TargetLowering::Legal) { 2655 // Get the sign bit of the RHS. 2656 MVT::ValueType IVT = 2657 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2658 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2659 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2660 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2661 // Get the absolute value of the result. 2662 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2663 // Select between the nabs and abs value based on the sign bit of 2664 // the input. 2665 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2666 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2667 AbsVal), 2668 AbsVal); 2669 Result = LegalizeOp(Result); 2670 break; 2671 } 2672 2673 // Otherwise, do bitwise ops! 2674 MVT::ValueType NVT = 2675 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 2676 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 2677 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 2678 Result = LegalizeOp(Result); 2679 break; 2680 } 2681 } 2682 break; 2683 2684 case ISD::ADDC: 2685 case ISD::SUBC: 2686 Tmp1 = LegalizeOp(Node->getOperand(0)); 2687 Tmp2 = LegalizeOp(Node->getOperand(1)); 2688 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2689 // Since this produces two values, make sure to remember that we legalized 2690 // both of them. 2691 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2692 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2693 return Result; 2694 2695 case ISD::ADDE: 2696 case ISD::SUBE: 2697 Tmp1 = LegalizeOp(Node->getOperand(0)); 2698 Tmp2 = LegalizeOp(Node->getOperand(1)); 2699 Tmp3 = LegalizeOp(Node->getOperand(2)); 2700 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2701 // Since this produces two values, make sure to remember that we legalized 2702 // both of them. 2703 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2704 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2705 return Result; 2706 2707 case ISD::BUILD_PAIR: { 2708 MVT::ValueType PairTy = Node->getValueType(0); 2709 // TODO: handle the case where the Lo and Hi operands are not of legal type 2710 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2711 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2712 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2713 case TargetLowering::Promote: 2714 case TargetLowering::Custom: 2715 assert(0 && "Cannot promote/custom this yet!"); 2716 case TargetLowering::Legal: 2717 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2718 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2719 break; 2720 case TargetLowering::Expand: 2721 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2722 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2723 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2724 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2725 TLI.getShiftAmountTy())); 2726 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2727 break; 2728 } 2729 break; 2730 } 2731 2732 case ISD::UREM: 2733 case ISD::SREM: 2734 case ISD::FREM: 2735 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2736 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2737 2738 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2739 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2740 case TargetLowering::Custom: 2741 isCustom = true; 2742 // FALLTHROUGH 2743 case TargetLowering::Legal: 2744 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2745 if (isCustom) { 2746 Tmp1 = TLI.LowerOperation(Result, DAG); 2747 if (Tmp1.Val) Result = Tmp1; 2748 } 2749 break; 2750 case TargetLowering::Expand: 2751 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2752 bool isSigned = DivOpc == ISD::SDIV; 2753 if (MVT::isInteger(Node->getValueType(0))) { 2754 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) == 2755 TargetLowering::Legal) { 2756 // X % Y -> X-X/Y*Y 2757 MVT::ValueType VT = Node->getValueType(0); 2758 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 2759 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2760 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2761 } else { 2762 assert(Node->getValueType(0) == MVT::i32 && 2763 "Cannot expand this binary operator!"); 2764 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 2765 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 2766 SDOperand Dummy; 2767 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2768 } 2769 } else { 2770 // Floating point mod -> fmod libcall. 2771 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 2772 ? RTLIB::REM_F32 : RTLIB::REM_F64; 2773 SDOperand Dummy; 2774 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2775 false/*sign irrelevant*/, Dummy); 2776 } 2777 break; 2778 } 2779 break; 2780 case ISD::VAARG: { 2781 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2782 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2783 2784 MVT::ValueType VT = Node->getValueType(0); 2785 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2786 default: assert(0 && "This action is not supported yet!"); 2787 case TargetLowering::Custom: 2788 isCustom = true; 2789 // FALLTHROUGH 2790 case TargetLowering::Legal: 2791 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2792 Result = Result.getValue(0); 2793 Tmp1 = Result.getValue(1); 2794 2795 if (isCustom) { 2796 Tmp2 = TLI.LowerOperation(Result, DAG); 2797 if (Tmp2.Val) { 2798 Result = LegalizeOp(Tmp2); 2799 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2800 } 2801 } 2802 break; 2803 case TargetLowering::Expand: { 2804 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 2805 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2806 SV->getValue(), SV->getOffset()); 2807 // Increment the pointer, VAList, to the next vaarg 2808 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2809 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2810 TLI.getPointerTy())); 2811 // Store the incremented VAList to the legalized pointer 2812 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 2813 SV->getOffset()); 2814 // Load the actual argument out of the pointer VAList 2815 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 2816 Tmp1 = LegalizeOp(Result.getValue(1)); 2817 Result = LegalizeOp(Result); 2818 break; 2819 } 2820 } 2821 // Since VAARG produces two values, make sure to remember that we 2822 // legalized both of them. 2823 AddLegalizedOperand(SDOperand(Node, 0), Result); 2824 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 2825 return Op.ResNo ? Tmp1 : Result; 2826 } 2827 2828 case ISD::VACOPY: 2829 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2830 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 2831 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 2832 2833 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 2834 default: assert(0 && "This action is not supported yet!"); 2835 case TargetLowering::Custom: 2836 isCustom = true; 2837 // FALLTHROUGH 2838 case TargetLowering::Legal: 2839 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 2840 Node->getOperand(3), Node->getOperand(4)); 2841 if (isCustom) { 2842 Tmp1 = TLI.LowerOperation(Result, DAG); 2843 if (Tmp1.Val) Result = Tmp1; 2844 } 2845 break; 2846 case TargetLowering::Expand: 2847 // This defaults to loading a pointer from the input and storing it to the 2848 // output, returning the chain. 2849 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 2850 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); 2851 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 2852 SVD->getOffset()); 2853 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), 2854 SVS->getOffset()); 2855 break; 2856 } 2857 break; 2858 2859 case ISD::VAEND: 2860 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2861 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2862 2863 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 2864 default: assert(0 && "This action is not supported yet!"); 2865 case TargetLowering::Custom: 2866 isCustom = true; 2867 // FALLTHROUGH 2868 case TargetLowering::Legal: 2869 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2870 if (isCustom) { 2871 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 2872 if (Tmp1.Val) Result = Tmp1; 2873 } 2874 break; 2875 case TargetLowering::Expand: 2876 Result = Tmp1; // Default to a no-op, return the chain 2877 break; 2878 } 2879 break; 2880 2881 case ISD::VASTART: 2882 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2883 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2884 2885 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2886 2887 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 2888 default: assert(0 && "This action is not supported yet!"); 2889 case TargetLowering::Legal: break; 2890 case TargetLowering::Custom: 2891 Tmp1 = TLI.LowerOperation(Result, DAG); 2892 if (Tmp1.Val) Result = Tmp1; 2893 break; 2894 } 2895 break; 2896 2897 case ISD::ROTL: 2898 case ISD::ROTR: 2899 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2900 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2901 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2902 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2903 default: 2904 assert(0 && "ROTL/ROTR legalize operation not supported"); 2905 break; 2906 case TargetLowering::Legal: 2907 break; 2908 case TargetLowering::Custom: 2909 Tmp1 = TLI.LowerOperation(Result, DAG); 2910 if (Tmp1.Val) Result = Tmp1; 2911 break; 2912 case TargetLowering::Promote: 2913 assert(0 && "Do not know how to promote ROTL/ROTR"); 2914 break; 2915 case TargetLowering::Expand: 2916 assert(0 && "Do not know how to expand ROTL/ROTR"); 2917 break; 2918 } 2919 break; 2920 2921 case ISD::BSWAP: 2922 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2923 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2924 case TargetLowering::Custom: 2925 assert(0 && "Cannot custom legalize this yet!"); 2926 case TargetLowering::Legal: 2927 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2928 break; 2929 case TargetLowering::Promote: { 2930 MVT::ValueType OVT = Tmp1.getValueType(); 2931 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2932 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 2933 2934 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2935 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2936 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2937 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2938 break; 2939 } 2940 case TargetLowering::Expand: 2941 Result = ExpandBSWAP(Tmp1); 2942 break; 2943 } 2944 break; 2945 2946 case ISD::CTPOP: 2947 case ISD::CTTZ: 2948 case ISD::CTLZ: 2949 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2950 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2951 case TargetLowering::Custom: 2952 case TargetLowering::Legal: 2953 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2954 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 2955 TargetLowering::Custom) { 2956 Tmp1 = TLI.LowerOperation(Result, DAG); 2957 if (Tmp1.Val) { 2958 Result = Tmp1; 2959 } 2960 } 2961 break; 2962 case TargetLowering::Promote: { 2963 MVT::ValueType OVT = Tmp1.getValueType(); 2964 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2965 2966 // Zero extend the argument. 2967 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2968 // Perform the larger operation, then subtract if needed. 2969 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2970 switch (Node->getOpcode()) { 2971 case ISD::CTPOP: 2972 Result = Tmp1; 2973 break; 2974 case ISD::CTTZ: 2975 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2976 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2977 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 2978 ISD::SETEQ); 2979 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2980 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 2981 break; 2982 case ISD::CTLZ: 2983 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2984 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2985 DAG.getConstant(MVT::getSizeInBits(NVT) - 2986 MVT::getSizeInBits(OVT), NVT)); 2987 break; 2988 } 2989 break; 2990 } 2991 case TargetLowering::Expand: 2992 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 2993 break; 2994 } 2995 break; 2996 2997 // Unary operators 2998 case ISD::FABS: 2999 case ISD::FNEG: 3000 case ISD::FSQRT: 3001 case ISD::FSIN: 3002 case ISD::FCOS: 3003 Tmp1 = LegalizeOp(Node->getOperand(0)); 3004 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3005 case TargetLowering::Promote: 3006 case TargetLowering::Custom: 3007 isCustom = true; 3008 // FALLTHROUGH 3009 case TargetLowering::Legal: 3010 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3011 if (isCustom) { 3012 Tmp1 = TLI.LowerOperation(Result, DAG); 3013 if (Tmp1.Val) Result = Tmp1; 3014 } 3015 break; 3016 case TargetLowering::Expand: 3017 switch (Node->getOpcode()) { 3018 default: assert(0 && "Unreachable!"); 3019 case ISD::FNEG: 3020 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3021 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3022 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3023 break; 3024 case ISD::FABS: { 3025 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3026 MVT::ValueType VT = Node->getValueType(0); 3027 Tmp2 = DAG.getConstantFP(0.0, VT); 3028 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 3029 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3030 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3031 break; 3032 } 3033 case ISD::FSQRT: 3034 case ISD::FSIN: 3035 case ISD::FCOS: { 3036 MVT::ValueType VT = Node->getValueType(0); 3037 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3038 switch(Node->getOpcode()) { 3039 case ISD::FSQRT: 3040 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64; 3041 break; 3042 case ISD::FSIN: 3043 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 3044 break; 3045 case ISD::FCOS: 3046 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64; 3047 break; 3048 default: assert(0 && "Unreachable!"); 3049 } 3050 SDOperand Dummy; 3051 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3052 false/*sign irrelevant*/, Dummy); 3053 break; 3054 } 3055 } 3056 break; 3057 } 3058 break; 3059 case ISD::FPOWI: { 3060 // We always lower FPOWI into a libcall. No target support it yet. 3061 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 3062 ? RTLIB::POWI_F32 : RTLIB::POWI_F64; 3063 SDOperand Dummy; 3064 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3065 false/*sign irrelevant*/, Dummy); 3066 break; 3067 } 3068 case ISD::BIT_CONVERT: 3069 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3070 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3071 } else if (MVT::isVector(Op.getOperand(0).getValueType())) { 3072 // The input has to be a vector type, we have to either scalarize it, pack 3073 // it, or convert it based on whether the input vector type is legal. 3074 SDNode *InVal = Node->getOperand(0).Val; 3075 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 3076 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 3077 3078 // Figure out if there is a simple type corresponding to this Vector 3079 // type. If so, convert to the vector type. 3080 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3081 if (TLI.isTypeLegal(TVT)) { 3082 // Turn this into a bit convert of the vector input. 3083 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3084 LegalizeOp(Node->getOperand(0))); 3085 break; 3086 } else if (NumElems == 1) { 3087 // Turn this into a bit convert of the scalar input. 3088 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3089 ScalarizeVectorOp(Node->getOperand(0))); 3090 break; 3091 } else { 3092 // FIXME: UNIMP! Store then reload 3093 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3094 } 3095 } else { 3096 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3097 Node->getOperand(0).getValueType())) { 3098 default: assert(0 && "Unknown operation action!"); 3099 case TargetLowering::Expand: 3100 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3101 break; 3102 case TargetLowering::Legal: 3103 Tmp1 = LegalizeOp(Node->getOperand(0)); 3104 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3105 break; 3106 } 3107 } 3108 break; 3109 3110 // Conversion operators. The source and destination have different types. 3111 case ISD::SINT_TO_FP: 3112 case ISD::UINT_TO_FP: { 3113 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3114 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3115 case Legal: 3116 switch (TLI.getOperationAction(Node->getOpcode(), 3117 Node->getOperand(0).getValueType())) { 3118 default: assert(0 && "Unknown operation action!"); 3119 case TargetLowering::Custom: 3120 isCustom = true; 3121 // FALLTHROUGH 3122 case TargetLowering::Legal: 3123 Tmp1 = LegalizeOp(Node->getOperand(0)); 3124 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3125 if (isCustom) { 3126 Tmp1 = TLI.LowerOperation(Result, DAG); 3127 if (Tmp1.Val) Result = Tmp1; 3128 } 3129 break; 3130 case TargetLowering::Expand: 3131 Result = ExpandLegalINT_TO_FP(isSigned, 3132 LegalizeOp(Node->getOperand(0)), 3133 Node->getValueType(0)); 3134 break; 3135 case TargetLowering::Promote: 3136 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3137 Node->getValueType(0), 3138 isSigned); 3139 break; 3140 } 3141 break; 3142 case Expand: 3143 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3144 Node->getValueType(0), Node->getOperand(0)); 3145 break; 3146 case Promote: 3147 Tmp1 = PromoteOp(Node->getOperand(0)); 3148 if (isSigned) { 3149 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3150 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3151 } else { 3152 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3153 Node->getOperand(0).getValueType()); 3154 } 3155 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3156 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3157 break; 3158 } 3159 break; 3160 } 3161 case ISD::TRUNCATE: 3162 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3163 case Legal: 3164 Tmp1 = LegalizeOp(Node->getOperand(0)); 3165 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3166 break; 3167 case Expand: 3168 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3169 3170 // Since the result is legal, we should just be able to truncate the low 3171 // part of the source. 3172 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3173 break; 3174 case Promote: 3175 Result = PromoteOp(Node->getOperand(0)); 3176 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3177 break; 3178 } 3179 break; 3180 3181 case ISD::FP_TO_SINT: 3182 case ISD::FP_TO_UINT: 3183 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3184 case Legal: 3185 Tmp1 = LegalizeOp(Node->getOperand(0)); 3186 3187 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3188 default: assert(0 && "Unknown operation action!"); 3189 case TargetLowering::Custom: 3190 isCustom = true; 3191 // FALLTHROUGH 3192 case TargetLowering::Legal: 3193 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3194 if (isCustom) { 3195 Tmp1 = TLI.LowerOperation(Result, DAG); 3196 if (Tmp1.Val) Result = Tmp1; 3197 } 3198 break; 3199 case TargetLowering::Promote: 3200 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3201 Node->getOpcode() == ISD::FP_TO_SINT); 3202 break; 3203 case TargetLowering::Expand: 3204 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3205 SDOperand True, False; 3206 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3207 MVT::ValueType NVT = Node->getValueType(0); 3208 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 3209 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 3210 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 3211 Node->getOperand(0), Tmp2, ISD::SETLT); 3212 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3213 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3214 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3215 Tmp2)); 3216 False = DAG.getNode(ISD::XOR, NVT, False, 3217 DAG.getConstant(1ULL << ShiftAmt, NVT)); 3218 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3219 break; 3220 } else { 3221 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3222 } 3223 break; 3224 } 3225 break; 3226 case Expand: { 3227 // Convert f32 / f64 to i32 / i64. 3228 MVT::ValueType VT = Op.getValueType(); 3229 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3230 switch (Node->getOpcode()) { 3231 case ISD::FP_TO_SINT: 3232 if (Node->getOperand(0).getValueType() == MVT::f32) 3233 LC = (VT == MVT::i32) 3234 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3235 else 3236 LC = (VT == MVT::i32) 3237 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3238 break; 3239 case ISD::FP_TO_UINT: 3240 if (Node->getOperand(0).getValueType() == MVT::f32) 3241 LC = (VT == MVT::i32) 3242 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3243 else 3244 LC = (VT == MVT::i32) 3245 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3246 break; 3247 default: assert(0 && "Unreachable!"); 3248 } 3249 SDOperand Dummy; 3250 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3251 false/*sign irrelevant*/, Dummy); 3252 break; 3253 } 3254 case Promote: 3255 Tmp1 = PromoteOp(Node->getOperand(0)); 3256 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3257 Result = LegalizeOp(Result); 3258 break; 3259 } 3260 break; 3261 3262 case ISD::FP_EXTEND: 3263 case ISD::FP_ROUND: { 3264 MVT::ValueType newVT = Op.getValueType(); 3265 MVT::ValueType oldVT = Op.getOperand(0).getValueType(); 3266 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) { 3267 // The only way we can lower this is to turn it into a STORE, 3268 // LOAD pair, targetting a temporary location (a stack slot). 3269 3270 // NOTE: there is a choice here between constantly creating new stack 3271 // slots and always reusing the same one. We currently always create 3272 // new ones, as reuse may inhibit scheduling. 3273 MVT::ValueType slotVT = 3274 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT; 3275 const Type *Ty = MVT::getTypeForValueType(slotVT); 3276 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3277 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3278 MachineFunction &MF = DAG.getMachineFunction(); 3279 int SSFI = 3280 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3281 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3282 if (Node->getOpcode() == ISD::FP_EXTEND) { 3283 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), 3284 StackSlot, NULL, 0); 3285 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT, 3286 Result, StackSlot, NULL, 0, oldVT); 3287 } else { 3288 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3289 StackSlot, NULL, 0, newVT); 3290 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT); 3291 } 3292 break; 3293 } 3294 } 3295 // FALL THROUGH 3296 case ISD::ANY_EXTEND: 3297 case ISD::ZERO_EXTEND: 3298 case ISD::SIGN_EXTEND: 3299 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3300 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3301 case Legal: 3302 Tmp1 = LegalizeOp(Node->getOperand(0)); 3303 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3304 break; 3305 case Promote: 3306 switch (Node->getOpcode()) { 3307 case ISD::ANY_EXTEND: 3308 Tmp1 = PromoteOp(Node->getOperand(0)); 3309 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3310 break; 3311 case ISD::ZERO_EXTEND: 3312 Result = PromoteOp(Node->getOperand(0)); 3313 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3314 Result = DAG.getZeroExtendInReg(Result, 3315 Node->getOperand(0).getValueType()); 3316 break; 3317 case ISD::SIGN_EXTEND: 3318 Result = PromoteOp(Node->getOperand(0)); 3319 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3320 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3321 Result, 3322 DAG.getValueType(Node->getOperand(0).getValueType())); 3323 break; 3324 case ISD::FP_EXTEND: 3325 Result = PromoteOp(Node->getOperand(0)); 3326 if (Result.getValueType() != Op.getValueType()) 3327 // Dynamically dead while we have only 2 FP types. 3328 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 3329 break; 3330 case ISD::FP_ROUND: 3331 Result = PromoteOp(Node->getOperand(0)); 3332 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 3333 break; 3334 } 3335 } 3336 break; 3337 case ISD::FP_ROUND_INREG: 3338 case ISD::SIGN_EXTEND_INREG: { 3339 Tmp1 = LegalizeOp(Node->getOperand(0)); 3340 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3341 3342 // If this operation is not supported, convert it to a shl/shr or load/store 3343 // pair. 3344 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3345 default: assert(0 && "This action not supported for this op yet!"); 3346 case TargetLowering::Legal: 3347 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3348 break; 3349 case TargetLowering::Expand: 3350 // If this is an integer extend and shifts are supported, do that. 3351 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3352 // NOTE: we could fall back on load/store here too for targets without 3353 // SAR. However, it is doubtful that any exist. 3354 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3355 MVT::getSizeInBits(ExtraVT); 3356 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3357 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3358 Node->getOperand(0), ShiftCst); 3359 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3360 Result, ShiftCst); 3361 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3362 // The only way we can lower this is to turn it into a TRUNCSTORE, 3363 // EXTLOAD pair, targetting a temporary location (a stack slot). 3364 3365 // NOTE: there is a choice here between constantly creating new stack 3366 // slots and always reusing the same one. We currently always create 3367 // new ones, as reuse may inhibit scheduling. 3368 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 3369 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3370 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3371 MachineFunction &MF = DAG.getMachineFunction(); 3372 int SSFI = 3373 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3374 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3375 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3376 StackSlot, NULL, 0, ExtraVT); 3377 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 3378 Result, StackSlot, NULL, 0, ExtraVT); 3379 } else { 3380 assert(0 && "Unknown op"); 3381 } 3382 break; 3383 } 3384 break; 3385 } 3386 case ISD::TRAMPOLINE: { 3387 SDOperand Ops[6]; 3388 for (unsigned i = 0; i != 6; ++i) 3389 Ops[i] = LegalizeOp(Node->getOperand(i)); 3390 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3391 // The only option for this node is to custom lower it. 3392 Result = TLI.LowerOperation(Result, DAG); 3393 assert(Result.Val && "Should always custom lower!"); 3394 3395 // Since trampoline produces two values, make sure to remember that we 3396 // legalized both of them. 3397 Tmp1 = LegalizeOp(Result.getValue(1)); 3398 Result = LegalizeOp(Result); 3399 AddLegalizedOperand(SDOperand(Node, 0), Result); 3400 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3401 return Op.ResNo ? Tmp1 : Result; 3402 } 3403 } 3404 3405 assert(Result.getValueType() == Op.getValueType() && 3406 "Bad legalization!"); 3407 3408 // Make sure that the generated code is itself legal. 3409 if (Result != Op) 3410 Result = LegalizeOp(Result); 3411 3412 // Note that LegalizeOp may be reentered even from single-use nodes, which 3413 // means that we always must cache transformed nodes. 3414 AddLegalizedOperand(Op, Result); 3415 return Result; 3416} 3417 3418/// PromoteOp - Given an operation that produces a value in an invalid type, 3419/// promote it to compute the value into a larger type. The produced value will 3420/// have the correct bits for the low portion of the register, but no guarantee 3421/// is made about the top bits: it may be zero, sign-extended, or garbage. 3422SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 3423 MVT::ValueType VT = Op.getValueType(); 3424 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3425 assert(getTypeAction(VT) == Promote && 3426 "Caller should expand or legalize operands that are not promotable!"); 3427 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 3428 "Cannot promote to smaller type!"); 3429 3430 SDOperand Tmp1, Tmp2, Tmp3; 3431 SDOperand Result; 3432 SDNode *Node = Op.Val; 3433 3434 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 3435 if (I != PromotedNodes.end()) return I->second; 3436 3437 switch (Node->getOpcode()) { 3438 case ISD::CopyFromReg: 3439 assert(0 && "CopyFromReg must be legal!"); 3440 default: 3441#ifndef NDEBUG 3442 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 3443#endif 3444 assert(0 && "Do not know how to promote this operator!"); 3445 abort(); 3446 case ISD::UNDEF: 3447 Result = DAG.getNode(ISD::UNDEF, NVT); 3448 break; 3449 case ISD::Constant: 3450 if (VT != MVT::i1) 3451 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 3452 else 3453 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 3454 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 3455 break; 3456 case ISD::ConstantFP: 3457 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 3458 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 3459 break; 3460 3461 case ISD::SETCC: 3462 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 3463 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 3464 Node->getOperand(1), Node->getOperand(2)); 3465 break; 3466 3467 case ISD::TRUNCATE: 3468 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3469 case Legal: 3470 Result = LegalizeOp(Node->getOperand(0)); 3471 assert(Result.getValueType() >= NVT && 3472 "This truncation doesn't make sense!"); 3473 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 3474 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 3475 break; 3476 case Promote: 3477 // The truncation is not required, because we don't guarantee anything 3478 // about high bits anyway. 3479 Result = PromoteOp(Node->getOperand(0)); 3480 break; 3481 case Expand: 3482 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3483 // Truncate the low part of the expanded value to the result type 3484 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 3485 } 3486 break; 3487 case ISD::SIGN_EXTEND: 3488 case ISD::ZERO_EXTEND: 3489 case ISD::ANY_EXTEND: 3490 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3491 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 3492 case Legal: 3493 // Input is legal? Just do extend all the way to the larger type. 3494 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3495 break; 3496 case Promote: 3497 // Promote the reg if it's smaller. 3498 Result = PromoteOp(Node->getOperand(0)); 3499 // The high bits are not guaranteed to be anything. Insert an extend. 3500 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3501 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3502 DAG.getValueType(Node->getOperand(0).getValueType())); 3503 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3504 Result = DAG.getZeroExtendInReg(Result, 3505 Node->getOperand(0).getValueType()); 3506 break; 3507 } 3508 break; 3509 case ISD::BIT_CONVERT: 3510 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3511 Result = PromoteOp(Result); 3512 break; 3513 3514 case ISD::FP_EXTEND: 3515 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3516 case ISD::FP_ROUND: 3517 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3518 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3519 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3520 case Legal: 3521 // Input is legal? Do an FP_ROUND_INREG. 3522 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 3523 DAG.getValueType(VT)); 3524 break; 3525 } 3526 break; 3527 3528 case ISD::SINT_TO_FP: 3529 case ISD::UINT_TO_FP: 3530 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3531 case Legal: 3532 // No extra round required here. 3533 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3534 break; 3535 3536 case Promote: 3537 Result = PromoteOp(Node->getOperand(0)); 3538 if (Node->getOpcode() == ISD::SINT_TO_FP) 3539 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3540 Result, 3541 DAG.getValueType(Node->getOperand(0).getValueType())); 3542 else 3543 Result = DAG.getZeroExtendInReg(Result, 3544 Node->getOperand(0).getValueType()); 3545 // No extra round required here. 3546 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3547 break; 3548 case Expand: 3549 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3550 Node->getOperand(0)); 3551 // Round if we cannot tolerate excess precision. 3552 if (NoExcessFPPrecision) 3553 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3554 DAG.getValueType(VT)); 3555 break; 3556 } 3557 break; 3558 3559 case ISD::SIGN_EXTEND_INREG: 3560 Result = PromoteOp(Node->getOperand(0)); 3561 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3562 Node->getOperand(1)); 3563 break; 3564 case ISD::FP_TO_SINT: 3565 case ISD::FP_TO_UINT: 3566 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3567 case Legal: 3568 case Expand: 3569 Tmp1 = Node->getOperand(0); 3570 break; 3571 case Promote: 3572 // The input result is prerounded, so we don't have to do anything 3573 // special. 3574 Tmp1 = PromoteOp(Node->getOperand(0)); 3575 break; 3576 } 3577 // If we're promoting a UINT to a larger size, check to see if the new node 3578 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3579 // we can use that instead. This allows us to generate better code for 3580 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3581 // legal, such as PowerPC. 3582 if (Node->getOpcode() == ISD::FP_TO_UINT && 3583 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3584 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3585 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3586 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3587 } else { 3588 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3589 } 3590 break; 3591 3592 case ISD::FABS: 3593 case ISD::FNEG: 3594 Tmp1 = PromoteOp(Node->getOperand(0)); 3595 assert(Tmp1.getValueType() == NVT); 3596 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3597 // NOTE: we do not have to do any extra rounding here for 3598 // NoExcessFPPrecision, because we know the input will have the appropriate 3599 // precision, and these operations don't modify precision at all. 3600 break; 3601 3602 case ISD::FSQRT: 3603 case ISD::FSIN: 3604 case ISD::FCOS: 3605 Tmp1 = PromoteOp(Node->getOperand(0)); 3606 assert(Tmp1.getValueType() == NVT); 3607 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3608 if (NoExcessFPPrecision) 3609 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3610 DAG.getValueType(VT)); 3611 break; 3612 3613 case ISD::FPOWI: { 3614 // Promote f32 powi to f64 powi. Note that this could insert a libcall 3615 // directly as well, which may be better. 3616 Tmp1 = PromoteOp(Node->getOperand(0)); 3617 assert(Tmp1.getValueType() == NVT); 3618 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 3619 if (NoExcessFPPrecision) 3620 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3621 DAG.getValueType(VT)); 3622 break; 3623 } 3624 3625 case ISD::AND: 3626 case ISD::OR: 3627 case ISD::XOR: 3628 case ISD::ADD: 3629 case ISD::SUB: 3630 case ISD::MUL: 3631 // The input may have strange things in the top bits of the registers, but 3632 // these operations don't care. They may have weird bits going out, but 3633 // that too is okay if they are integer operations. 3634 Tmp1 = PromoteOp(Node->getOperand(0)); 3635 Tmp2 = PromoteOp(Node->getOperand(1)); 3636 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3637 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3638 break; 3639 case ISD::FADD: 3640 case ISD::FSUB: 3641 case ISD::FMUL: 3642 Tmp1 = PromoteOp(Node->getOperand(0)); 3643 Tmp2 = PromoteOp(Node->getOperand(1)); 3644 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3645 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3646 3647 // Floating point operations will give excess precision that we may not be 3648 // able to tolerate. If we DO allow excess precision, just leave it, 3649 // otherwise excise it. 3650 // FIXME: Why would we need to round FP ops more than integer ones? 3651 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3652 if (NoExcessFPPrecision) 3653 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3654 DAG.getValueType(VT)); 3655 break; 3656 3657 case ISD::SDIV: 3658 case ISD::SREM: 3659 // These operators require that their input be sign extended. 3660 Tmp1 = PromoteOp(Node->getOperand(0)); 3661 Tmp2 = PromoteOp(Node->getOperand(1)); 3662 if (MVT::isInteger(NVT)) { 3663 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3664 DAG.getValueType(VT)); 3665 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3666 DAG.getValueType(VT)); 3667 } 3668 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3669 3670 // Perform FP_ROUND: this is probably overly pessimistic. 3671 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3672 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3673 DAG.getValueType(VT)); 3674 break; 3675 case ISD::FDIV: 3676 case ISD::FREM: 3677 case ISD::FCOPYSIGN: 3678 // These operators require that their input be fp extended. 3679 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3680 case Legal: 3681 Tmp1 = LegalizeOp(Node->getOperand(0)); 3682 break; 3683 case Promote: 3684 Tmp1 = PromoteOp(Node->getOperand(0)); 3685 break; 3686 case Expand: 3687 assert(0 && "not implemented"); 3688 } 3689 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3690 case Legal: 3691 Tmp2 = LegalizeOp(Node->getOperand(1)); 3692 break; 3693 case Promote: 3694 Tmp2 = PromoteOp(Node->getOperand(1)); 3695 break; 3696 case Expand: 3697 assert(0 && "not implemented"); 3698 } 3699 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3700 3701 // Perform FP_ROUND: this is probably overly pessimistic. 3702 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 3703 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3704 DAG.getValueType(VT)); 3705 break; 3706 3707 case ISD::UDIV: 3708 case ISD::UREM: 3709 // These operators require that their input be zero extended. 3710 Tmp1 = PromoteOp(Node->getOperand(0)); 3711 Tmp2 = PromoteOp(Node->getOperand(1)); 3712 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3713 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3714 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3715 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3716 break; 3717 3718 case ISD::SHL: 3719 Tmp1 = PromoteOp(Node->getOperand(0)); 3720 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 3721 break; 3722 case ISD::SRA: 3723 // The input value must be properly sign extended. 3724 Tmp1 = PromoteOp(Node->getOperand(0)); 3725 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3726 DAG.getValueType(VT)); 3727 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 3728 break; 3729 case ISD::SRL: 3730 // The input value must be properly zero extended. 3731 Tmp1 = PromoteOp(Node->getOperand(0)); 3732 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3733 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 3734 break; 3735 3736 case ISD::VAARG: 3737 Tmp1 = Node->getOperand(0); // Get the chain. 3738 Tmp2 = Node->getOperand(1); // Get the pointer. 3739 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 3740 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 3741 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 3742 } else { 3743 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 3744 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3745 SV->getValue(), SV->getOffset()); 3746 // Increment the pointer, VAList, to the next vaarg 3747 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3748 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3749 TLI.getPointerTy())); 3750 // Store the incremented VAList to the legalized pointer 3751 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 3752 SV->getOffset()); 3753 // Load the actual argument out of the pointer VAList 3754 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 3755 } 3756 // Remember that we legalized the chain. 3757 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3758 break; 3759 3760 case ISD::LOAD: { 3761 LoadSDNode *LD = cast<LoadSDNode>(Node); 3762 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 3763 ? ISD::EXTLOAD : LD->getExtensionType(); 3764 Result = DAG.getExtLoad(ExtType, NVT, 3765 LD->getChain(), LD->getBasePtr(), 3766 LD->getSrcValue(), LD->getSrcValueOffset(), 3767 LD->getLoadedVT(), 3768 LD->isVolatile(), 3769 LD->getAlignment()); 3770 // Remember that we legalized the chain. 3771 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3772 break; 3773 } 3774 case ISD::SELECT: 3775 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 3776 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 3777 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 3778 break; 3779 case ISD::SELECT_CC: 3780 Tmp2 = PromoteOp(Node->getOperand(2)); // True 3781 Tmp3 = PromoteOp(Node->getOperand(3)); // False 3782 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3783 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 3784 break; 3785 case ISD::BSWAP: 3786 Tmp1 = Node->getOperand(0); 3787 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3788 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3789 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3790 DAG.getConstant(MVT::getSizeInBits(NVT) - 3791 MVT::getSizeInBits(VT), 3792 TLI.getShiftAmountTy())); 3793 break; 3794 case ISD::CTPOP: 3795 case ISD::CTTZ: 3796 case ISD::CTLZ: 3797 // Zero extend the argument 3798 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 3799 // Perform the larger operation, then subtract if needed. 3800 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3801 switch(Node->getOpcode()) { 3802 case ISD::CTPOP: 3803 Result = Tmp1; 3804 break; 3805 case ISD::CTTZ: 3806 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3807 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3808 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3809 ISD::SETEQ); 3810 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3811 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 3812 break; 3813 case ISD::CTLZ: 3814 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3815 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3816 DAG.getConstant(MVT::getSizeInBits(NVT) - 3817 MVT::getSizeInBits(VT), NVT)); 3818 break; 3819 } 3820 break; 3821 case ISD::EXTRACT_SUBVECTOR: 3822 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 3823 break; 3824 case ISD::EXTRACT_VECTOR_ELT: 3825 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 3826 break; 3827 } 3828 3829 assert(Result.Val && "Didn't set a result!"); 3830 3831 // Make sure the result is itself legal. 3832 Result = LegalizeOp(Result); 3833 3834 // Remember that we promoted this! 3835 AddPromotedOperand(Op, Result); 3836 return Result; 3837} 3838 3839/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 3840/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 3841/// based on the vector type. The return type of this matches the element type 3842/// of the vector, which may not be legal for the target. 3843SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 3844 // We know that operand #0 is the Vec vector. If the index is a constant 3845 // or if the invec is a supported hardware type, we can use it. Otherwise, 3846 // lower to a store then an indexed load. 3847 SDOperand Vec = Op.getOperand(0); 3848 SDOperand Idx = Op.getOperand(1); 3849 3850 SDNode *InVal = Vec.Val; 3851 MVT::ValueType TVT = InVal->getValueType(0); 3852 unsigned NumElems = MVT::getVectorNumElements(TVT); 3853 3854 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 3855 default: assert(0 && "This action is not supported yet!"); 3856 case TargetLowering::Custom: { 3857 Vec = LegalizeOp(Vec); 3858 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3859 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 3860 if (Tmp3.Val) 3861 return Tmp3; 3862 break; 3863 } 3864 case TargetLowering::Legal: 3865 if (isTypeLegal(TVT)) { 3866 Vec = LegalizeOp(Vec); 3867 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3868 return Op; 3869 } 3870 break; 3871 case TargetLowering::Expand: 3872 break; 3873 } 3874 3875 if (NumElems == 1) { 3876 // This must be an access of the only element. Return it. 3877 Op = ScalarizeVectorOp(Vec); 3878 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 3879 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 3880 SDOperand Lo, Hi; 3881 SplitVectorOp(Vec, Lo, Hi); 3882 if (CIdx->getValue() < NumElems/2) { 3883 Vec = Lo; 3884 } else { 3885 Vec = Hi; 3886 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, 3887 Idx.getValueType()); 3888 } 3889 3890 // It's now an extract from the appropriate high or low part. Recurse. 3891 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3892 Op = ExpandEXTRACT_VECTOR_ELT(Op); 3893 } else { 3894 // Store the value to a temporary stack slot, then LOAD the scalar 3895 // element back out. 3896 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType()); 3897 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 3898 3899 // Add the offset to the index. 3900 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 3901 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 3902 DAG.getConstant(EltSize, Idx.getValueType())); 3903 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 3904 3905 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 3906 } 3907 return Op; 3908} 3909 3910/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 3911/// we assume the operation can be split if it is not already legal. 3912SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 3913 // We know that operand #0 is the Vec vector. For now we assume the index 3914 // is a constant and that the extracted result is a supported hardware type. 3915 SDOperand Vec = Op.getOperand(0); 3916 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 3917 3918 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); 3919 3920 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 3921 // This must be an access of the desired vector length. Return it. 3922 return Vec; 3923 } 3924 3925 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 3926 SDOperand Lo, Hi; 3927 SplitVectorOp(Vec, Lo, Hi); 3928 if (CIdx->getValue() < NumElems/2) { 3929 Vec = Lo; 3930 } else { 3931 Vec = Hi; 3932 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 3933 } 3934 3935 // It's now an extract from the appropriate high or low part. Recurse. 3936 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3937 return ExpandEXTRACT_SUBVECTOR(Op); 3938} 3939 3940/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 3941/// with condition CC on the current target. This usually involves legalizing 3942/// or promoting the arguments. In the case where LHS and RHS must be expanded, 3943/// there may be no choice but to create a new SetCC node to represent the 3944/// legalized value of setcc lhs, rhs. In this case, the value is returned in 3945/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 3946void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 3947 SDOperand &RHS, 3948 SDOperand &CC) { 3949 SDOperand Tmp1, Tmp2, Result; 3950 3951 switch (getTypeAction(LHS.getValueType())) { 3952 case Legal: 3953 Tmp1 = LegalizeOp(LHS); // LHS 3954 Tmp2 = LegalizeOp(RHS); // RHS 3955 break; 3956 case Promote: 3957 Tmp1 = PromoteOp(LHS); // LHS 3958 Tmp2 = PromoteOp(RHS); // RHS 3959 3960 // If this is an FP compare, the operands have already been extended. 3961 if (MVT::isInteger(LHS.getValueType())) { 3962 MVT::ValueType VT = LHS.getValueType(); 3963 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3964 3965 // Otherwise, we have to insert explicit sign or zero extends. Note 3966 // that we could insert sign extends for ALL conditions, but zero extend 3967 // is cheaper on many machines (an AND instead of two shifts), so prefer 3968 // it. 3969 switch (cast<CondCodeSDNode>(CC)->get()) { 3970 default: assert(0 && "Unknown integer comparison!"); 3971 case ISD::SETEQ: 3972 case ISD::SETNE: 3973 case ISD::SETUGE: 3974 case ISD::SETUGT: 3975 case ISD::SETULE: 3976 case ISD::SETULT: 3977 // ALL of these operations will work if we either sign or zero extend 3978 // the operands (including the unsigned comparisons!). Zero extend is 3979 // usually a simpler/cheaper operation, so prefer it. 3980 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3981 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3982 break; 3983 case ISD::SETGE: 3984 case ISD::SETGT: 3985 case ISD::SETLT: 3986 case ISD::SETLE: 3987 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3988 DAG.getValueType(VT)); 3989 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3990 DAG.getValueType(VT)); 3991 break; 3992 } 3993 } 3994 break; 3995 case Expand: { 3996 MVT::ValueType VT = LHS.getValueType(); 3997 if (VT == MVT::f32 || VT == MVT::f64) { 3998 // Expand into one or more soft-fp libcall(s). 3999 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4000 switch (cast<CondCodeSDNode>(CC)->get()) { 4001 case ISD::SETEQ: 4002 case ISD::SETOEQ: 4003 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4004 break; 4005 case ISD::SETNE: 4006 case ISD::SETUNE: 4007 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4008 break; 4009 case ISD::SETGE: 4010 case ISD::SETOGE: 4011 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4012 break; 4013 case ISD::SETLT: 4014 case ISD::SETOLT: 4015 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4016 break; 4017 case ISD::SETLE: 4018 case ISD::SETOLE: 4019 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4020 break; 4021 case ISD::SETGT: 4022 case ISD::SETOGT: 4023 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4024 break; 4025 case ISD::SETUO: 4026 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4027 break; 4028 case ISD::SETO: 4029 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4030 break; 4031 default: 4032 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4033 switch (cast<CondCodeSDNode>(CC)->get()) { 4034 case ISD::SETONE: 4035 // SETONE = SETOLT | SETOGT 4036 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4037 // Fallthrough 4038 case ISD::SETUGT: 4039 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4040 break; 4041 case ISD::SETUGE: 4042 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4043 break; 4044 case ISD::SETULT: 4045 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4046 break; 4047 case ISD::SETULE: 4048 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4049 break; 4050 case ISD::SETUEQ: 4051 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4052 break; 4053 default: assert(0 && "Unsupported FP setcc!"); 4054 } 4055 } 4056 4057 SDOperand Dummy; 4058 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 4059 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4060 false /*sign irrelevant*/, Dummy); 4061 Tmp2 = DAG.getConstant(0, MVT::i32); 4062 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4063 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4064 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 4065 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 4066 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4067 false /*sign irrelevant*/, Dummy); 4068 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 4069 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4070 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4071 Tmp2 = SDOperand(); 4072 } 4073 LHS = Tmp1; 4074 RHS = Tmp2; 4075 return; 4076 } 4077 4078 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4079 ExpandOp(LHS, LHSLo, LHSHi); 4080 ExpandOp(RHS, RHSLo, RHSHi); 4081 switch (cast<CondCodeSDNode>(CC)->get()) { 4082 case ISD::SETEQ: 4083 case ISD::SETNE: 4084 if (RHSLo == RHSHi) 4085 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4086 if (RHSCST->isAllOnesValue()) { 4087 // Comparison to -1. 4088 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4089 Tmp2 = RHSLo; 4090 break; 4091 } 4092 4093 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4094 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4095 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4096 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4097 break; 4098 default: 4099 // If this is a comparison of the sign bit, just look at the top part. 4100 // X > -1, x < 0 4101 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4102 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4103 CST->getValue() == 0) || // X < 0 4104 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4105 CST->isAllOnesValue())) { // X > -1 4106 Tmp1 = LHSHi; 4107 Tmp2 = RHSHi; 4108 break; 4109 } 4110 4111 // FIXME: This generated code sucks. 4112 ISD::CondCode LowCC; 4113 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4114 switch (CCCode) { 4115 default: assert(0 && "Unknown integer setcc!"); 4116 case ISD::SETLT: 4117 case ISD::SETULT: LowCC = ISD::SETULT; break; 4118 case ISD::SETGT: 4119 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4120 case ISD::SETLE: 4121 case ISD::SETULE: LowCC = ISD::SETULE; break; 4122 case ISD::SETGE: 4123 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4124 } 4125 4126 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4127 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4128 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4129 4130 // NOTE: on targets without efficient SELECT of bools, we can always use 4131 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4132 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4133 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, 4134 false, DagCombineInfo); 4135 if (!Tmp1.Val) 4136 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 4137 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4138 CCCode, false, DagCombineInfo); 4139 if (!Tmp2.Val) 4140 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC); 4141 4142 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4143 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4144 if ((Tmp1C && Tmp1C->getValue() == 0) || 4145 (Tmp2C && Tmp2C->getValue() == 0 && 4146 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4147 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4148 (Tmp2C && Tmp2C->getValue() == 1 && 4149 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4150 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4151 // low part is known false, returns high part. 4152 // For LE / GE, if high part is known false, ignore the low part. 4153 // For LT / GT, if high part is known true, ignore the low part. 4154 Tmp1 = Tmp2; 4155 Tmp2 = SDOperand(); 4156 } else { 4157 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4158 ISD::SETEQ, false, DagCombineInfo); 4159 if (!Result.Val) 4160 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4161 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4162 Result, Tmp1, Tmp2)); 4163 Tmp1 = Result; 4164 Tmp2 = SDOperand(); 4165 } 4166 } 4167 } 4168 } 4169 LHS = Tmp1; 4170 RHS = Tmp2; 4171} 4172 4173/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 4174/// The resultant code need not be legal. Note that SrcOp is the input operand 4175/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 4176SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 4177 SDOperand SrcOp) { 4178 // Create the stack frame object. 4179 SDOperand FIPtr = CreateStackTemporary(DestVT); 4180 4181 // Emit a store to the stack slot. 4182 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); 4183 // Result is a load from the stack slot. 4184 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4185} 4186 4187SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4188 // Create a vector sized/aligned stack slot, store the value to element #0, 4189 // then load the whole vector back out. 4190 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); 4191 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4192 NULL, 0); 4193 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 4194} 4195 4196 4197/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4198/// support the operation, but do support the resultant vector type. 4199SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4200 4201 // If the only non-undef value is the low element, turn this into a 4202 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4203 unsigned NumElems = Node->getNumOperands(); 4204 bool isOnlyLowElement = true; 4205 SDOperand SplatValue = Node->getOperand(0); 4206 std::map<SDOperand, std::vector<unsigned> > Values; 4207 Values[SplatValue].push_back(0); 4208 bool isConstant = true; 4209 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4210 SplatValue.getOpcode() != ISD::UNDEF) 4211 isConstant = false; 4212 4213 for (unsigned i = 1; i < NumElems; ++i) { 4214 SDOperand V = Node->getOperand(i); 4215 Values[V].push_back(i); 4216 if (V.getOpcode() != ISD::UNDEF) 4217 isOnlyLowElement = false; 4218 if (SplatValue != V) 4219 SplatValue = SDOperand(0,0); 4220 4221 // If this isn't a constant element or an undef, we can't use a constant 4222 // pool load. 4223 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4224 V.getOpcode() != ISD::UNDEF) 4225 isConstant = false; 4226 } 4227 4228 if (isOnlyLowElement) { 4229 // If the low element is an undef too, then this whole things is an undef. 4230 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4231 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4232 // Otherwise, turn this into a scalar_to_vector node. 4233 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4234 Node->getOperand(0)); 4235 } 4236 4237 // If all elements are constants, create a load from the constant pool. 4238 if (isConstant) { 4239 MVT::ValueType VT = Node->getValueType(0); 4240 const Type *OpNTy = 4241 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 4242 std::vector<Constant*> CV; 4243 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4244 if (ConstantFPSDNode *V = 4245 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4246 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF())); 4247 } else if (ConstantSDNode *V = 4248 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4249 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 4250 } else { 4251 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4252 CV.push_back(UndefValue::get(OpNTy)); 4253 } 4254 } 4255 Constant *CP = ConstantVector::get(CV); 4256 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4257 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 4258 } 4259 4260 if (SplatValue.Val) { // Splat of one value? 4261 // Build the shuffle constant vector: <0, 0, 0, 0> 4262 MVT::ValueType MaskVT = 4263 MVT::getIntVectorWithNumElements(NumElems); 4264 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 4265 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4266 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4267 &ZeroVec[0], ZeroVec.size()); 4268 4269 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4270 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4271 // Get the splatted value into the low element of a vector register. 4272 SDOperand LowValVec = 4273 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4274 4275 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4276 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4277 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4278 SplatMask); 4279 } 4280 } 4281 4282 // If there are only two unique elements, we may be able to turn this into a 4283 // vector shuffle. 4284 if (Values.size() == 2) { 4285 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 4286 MVT::ValueType MaskVT = 4287 MVT::getIntVectorWithNumElements(NumElems); 4288 std::vector<SDOperand> MaskVec(NumElems); 4289 unsigned i = 0; 4290 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4291 E = Values.end(); I != E; ++I) { 4292 for (std::vector<unsigned>::iterator II = I->second.begin(), 4293 EE = I->second.end(); II != EE; ++II) 4294 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT)); 4295 i += NumElems; 4296 } 4297 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4298 &MaskVec[0], MaskVec.size()); 4299 4300 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4301 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 4302 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 4303 SmallVector<SDOperand, 8> Ops; 4304 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4305 E = Values.end(); I != E; ++I) { 4306 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4307 I->first); 4308 Ops.push_back(Op); 4309 } 4310 Ops.push_back(ShuffleMask); 4311 4312 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 4313 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 4314 &Ops[0], Ops.size()); 4315 } 4316 } 4317 4318 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 4319 // aligned object on the stack, store each element into it, then load 4320 // the result as a vector. 4321 MVT::ValueType VT = Node->getValueType(0); 4322 // Create the stack frame object. 4323 SDOperand FIPtr = CreateStackTemporary(VT); 4324 4325 // Emit a store of each element to the stack slot. 4326 SmallVector<SDOperand, 8> Stores; 4327 unsigned TypeByteSize = 4328 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 4329 // Store (in the right endianness) the elements to memory. 4330 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4331 // Ignore undef elements. 4332 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4333 4334 unsigned Offset = TypeByteSize*i; 4335 4336 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 4337 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 4338 4339 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 4340 NULL, 0)); 4341 } 4342 4343 SDOperand StoreChain; 4344 if (!Stores.empty()) // Not all undef elements? 4345 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4346 &Stores[0], Stores.size()); 4347 else 4348 StoreChain = DAG.getEntryNode(); 4349 4350 // Result is a load from the stack slot. 4351 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 4352} 4353 4354/// CreateStackTemporary - Create a stack temporary, suitable for holding the 4355/// specified value type. 4356SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) { 4357 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4358 unsigned ByteSize = MVT::getSizeInBits(VT)/8; 4359 const Type *Ty = MVT::getTypeForValueType(VT); 4360 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty); 4361 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 4362 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 4363} 4364 4365void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 4366 SDOperand Op, SDOperand Amt, 4367 SDOperand &Lo, SDOperand &Hi) { 4368 // Expand the subcomponents. 4369 SDOperand LHSL, LHSH; 4370 ExpandOp(Op, LHSL, LHSH); 4371 4372 SDOperand Ops[] = { LHSL, LHSH, Amt }; 4373 MVT::ValueType VT = LHSL.getValueType(); 4374 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 4375 Hi = Lo.getValue(1); 4376} 4377 4378 4379/// ExpandShift - Try to find a clever way to expand this shift operation out to 4380/// smaller elements. If we can't find a way that is more efficient than a 4381/// libcall on this target, return false. Otherwise, return true with the 4382/// low-parts expanded into Lo and Hi. 4383bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 4384 SDOperand &Lo, SDOperand &Hi) { 4385 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 4386 "This is not a shift!"); 4387 4388 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 4389 SDOperand ShAmt = LegalizeOp(Amt); 4390 MVT::ValueType ShTy = ShAmt.getValueType(); 4391 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 4392 unsigned NVTBits = MVT::getSizeInBits(NVT); 4393 4394 // Handle the case when Amt is an immediate. Other cases are currently broken 4395 // and are disabled. 4396 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 4397 unsigned Cst = CN->getValue(); 4398 // Expand the incoming operand to be shifted, so that we have its parts 4399 SDOperand InL, InH; 4400 ExpandOp(Op, InL, InH); 4401 switch(Opc) { 4402 case ISD::SHL: 4403 if (Cst > VTBits) { 4404 Lo = DAG.getConstant(0, NVT); 4405 Hi = DAG.getConstant(0, NVT); 4406 } else if (Cst > NVTBits) { 4407 Lo = DAG.getConstant(0, NVT); 4408 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 4409 } else if (Cst == NVTBits) { 4410 Lo = DAG.getConstant(0, NVT); 4411 Hi = InL; 4412 } else { 4413 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 4414 Hi = DAG.getNode(ISD::OR, NVT, 4415 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 4416 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 4417 } 4418 return true; 4419 case ISD::SRL: 4420 if (Cst > VTBits) { 4421 Lo = DAG.getConstant(0, NVT); 4422 Hi = DAG.getConstant(0, NVT); 4423 } else if (Cst > NVTBits) { 4424 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 4425 Hi = DAG.getConstant(0, NVT); 4426 } else if (Cst == NVTBits) { 4427 Lo = InH; 4428 Hi = DAG.getConstant(0, NVT); 4429 } else { 4430 Lo = DAG.getNode(ISD::OR, NVT, 4431 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4432 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4433 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 4434 } 4435 return true; 4436 case ISD::SRA: 4437 if (Cst > VTBits) { 4438 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 4439 DAG.getConstant(NVTBits-1, ShTy)); 4440 } else if (Cst > NVTBits) { 4441 Lo = DAG.getNode(ISD::SRA, NVT, InH, 4442 DAG.getConstant(Cst-NVTBits, ShTy)); 4443 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4444 DAG.getConstant(NVTBits-1, ShTy)); 4445 } else if (Cst == NVTBits) { 4446 Lo = InH; 4447 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4448 DAG.getConstant(NVTBits-1, ShTy)); 4449 } else { 4450 Lo = DAG.getNode(ISD::OR, NVT, 4451 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4452 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4453 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 4454 } 4455 return true; 4456 } 4457 } 4458 4459 // Okay, the shift amount isn't constant. However, if we can tell that it is 4460 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 4461 uint64_t Mask = NVTBits, KnownZero, KnownOne; 4462 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 4463 4464 // If we know that the high bit of the shift amount is one, then we can do 4465 // this as a couple of simple shifts. 4466 if (KnownOne & Mask) { 4467 // Mask out the high bit, which we know is set. 4468 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 4469 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4470 4471 // Expand the incoming operand to be shifted, so that we have its parts 4472 SDOperand InL, InH; 4473 ExpandOp(Op, InL, InH); 4474 switch(Opc) { 4475 case ISD::SHL: 4476 Lo = DAG.getConstant(0, NVT); // Low part is zero. 4477 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 4478 return true; 4479 case ISD::SRL: 4480 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 4481 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 4482 return true; 4483 case ISD::SRA: 4484 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 4485 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4486 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 4487 return true; 4488 } 4489 } 4490 4491 // If we know that the high bit of the shift amount is zero, then we can do 4492 // this as a couple of simple shifts. 4493 if (KnownZero & Mask) { 4494 // Compute 32-amt. 4495 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 4496 DAG.getConstant(NVTBits, Amt.getValueType()), 4497 Amt); 4498 4499 // Expand the incoming operand to be shifted, so that we have its parts 4500 SDOperand InL, InH; 4501 ExpandOp(Op, InL, InH); 4502 switch(Opc) { 4503 case ISD::SHL: 4504 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 4505 Hi = DAG.getNode(ISD::OR, NVT, 4506 DAG.getNode(ISD::SHL, NVT, InH, Amt), 4507 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 4508 return true; 4509 case ISD::SRL: 4510 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 4511 Lo = DAG.getNode(ISD::OR, NVT, 4512 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4513 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4514 return true; 4515 case ISD::SRA: 4516 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 4517 Lo = DAG.getNode(ISD::OR, NVT, 4518 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4519 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4520 return true; 4521 } 4522 } 4523 4524 return false; 4525} 4526 4527 4528// ExpandLibCall - Expand a node into a call to a libcall. If the result value 4529// does not fit into a register, return the lo part and set the hi part to the 4530// by-reg argument. If it does fit into a single register, return the result 4531// and leave the Hi part unset. 4532SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 4533 bool isSigned, SDOperand &Hi) { 4534 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 4535 // The input chain to this libcall is the entry node of the function. 4536 // Legalizing the call will automatically add the previous call to the 4537 // dependence. 4538 SDOperand InChain = DAG.getEntryNode(); 4539 4540 TargetLowering::ArgListTy Args; 4541 TargetLowering::ArgListEntry Entry; 4542 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4543 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 4544 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 4545 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 4546 Entry.isSExt = isSigned; 4547 Args.push_back(Entry); 4548 } 4549 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 4550 4551 // Splice the libcall in wherever FindInputOutputChains tells us to. 4552 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 4553 std::pair<SDOperand,SDOperand> CallInfo = 4554 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false, 4555 Callee, Args, DAG); 4556 4557 // Legalize the call sequence, starting with the chain. This will advance 4558 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 4559 // was added by LowerCallTo (guaranteeing proper serialization of calls). 4560 LegalizeOp(CallInfo.second); 4561 SDOperand Result; 4562 switch (getTypeAction(CallInfo.first.getValueType())) { 4563 default: assert(0 && "Unknown thing"); 4564 case Legal: 4565 Result = CallInfo.first; 4566 break; 4567 case Expand: 4568 ExpandOp(CallInfo.first, Result, Hi); 4569 break; 4570 } 4571 return Result; 4572} 4573 4574 4575/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 4576/// 4577SDOperand SelectionDAGLegalize:: 4578ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 4579 assert(getTypeAction(Source.getValueType()) == Expand && 4580 "This is not an expansion!"); 4581 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 4582 4583 if (!isSigned) { 4584 assert(Source.getValueType() == MVT::i64 && 4585 "This only works for 64-bit -> FP"); 4586 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 4587 // incoming integer is set. To handle this, we dynamically test to see if 4588 // it is set, and, if so, add a fudge factor. 4589 SDOperand Lo, Hi; 4590 ExpandOp(Source, Lo, Hi); 4591 4592 // If this is unsigned, and not supported, first perform the conversion to 4593 // signed, then adjust the result if the sign bit is set. 4594 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 4595 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 4596 4597 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 4598 DAG.getConstant(0, Hi.getValueType()), 4599 ISD::SETLT); 4600 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4601 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4602 SignSet, Four, Zero); 4603 uint64_t FF = 0x5f800000ULL; 4604 if (TLI.isLittleEndian()) FF <<= 32; 4605 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4606 4607 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4608 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4609 SDOperand FudgeInReg; 4610 if (DestTy == MVT::f32) 4611 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4612 else { 4613 assert(DestTy == MVT::f64 && "Unexpected conversion"); 4614 // FIXME: Avoid the extend by construction the right constantpool? 4615 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 4616 CPIdx, NULL, 0, MVT::f32); 4617 } 4618 MVT::ValueType SCVT = SignedConv.getValueType(); 4619 if (SCVT != DestTy) { 4620 // Destination type needs to be expanded as well. The FADD now we are 4621 // constructing will be expanded into a libcall. 4622 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 4623 assert(SCVT == MVT::i32 && DestTy == MVT::f64); 4624 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, 4625 SignedConv, SignedConv.getValue(1)); 4626 } 4627 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 4628 } 4629 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 4630 } 4631 4632 // Check to see if the target has a custom way to lower this. If so, use it. 4633 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 4634 default: assert(0 && "This action not implemented for this operation!"); 4635 case TargetLowering::Legal: 4636 case TargetLowering::Expand: 4637 break; // This case is handled below. 4638 case TargetLowering::Custom: { 4639 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 4640 Source), DAG); 4641 if (NV.Val) 4642 return LegalizeOp(NV); 4643 break; // The target decided this was legal after all 4644 } 4645 } 4646 4647 // Expand the source, then glue it back together for the call. We must expand 4648 // the source in case it is shared (this pass of legalize must traverse it). 4649 SDOperand SrcLo, SrcHi; 4650 ExpandOp(Source, SrcLo, SrcHi); 4651 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 4652 4653 RTLIB::Libcall LC; 4654 if (DestTy == MVT::f32) 4655 LC = RTLIB::SINTTOFP_I64_F32; 4656 else { 4657 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 4658 LC = RTLIB::SINTTOFP_I64_F64; 4659 } 4660 4661 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 4662 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 4663 SDOperand UnusedHiPart; 4664 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 4665 UnusedHiPart); 4666} 4667 4668/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 4669/// INT_TO_FP operation of the specified operand when the target requests that 4670/// we expand it. At this point, we know that the result and operand types are 4671/// legal for the target. 4672SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 4673 SDOperand Op0, 4674 MVT::ValueType DestVT) { 4675 if (Op0.getValueType() == MVT::i32) { 4676 // simple 32-bit [signed|unsigned] integer to float/double expansion 4677 4678 // get the stack frame index of a 8 byte buffer, pessimistically aligned 4679 MachineFunction &MF = DAG.getMachineFunction(); 4680 const Type *F64Type = MVT::getTypeForValueType(MVT::f64); 4681 unsigned StackAlign = 4682 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type); 4683 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign); 4684 // get address of 8 byte buffer 4685 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4686 // word offset constant for Hi/Lo address computation 4687 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 4688 // set up Hi and Lo (into buffer) address based on endian 4689 SDOperand Hi = StackSlot; 4690 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 4691 if (TLI.isLittleEndian()) 4692 std::swap(Hi, Lo); 4693 4694 // if signed map to unsigned space 4695 SDOperand Op0Mapped; 4696 if (isSigned) { 4697 // constant used to invert sign bit (signed to unsigned mapping) 4698 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 4699 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 4700 } else { 4701 Op0Mapped = Op0; 4702 } 4703 // store the lo of the constructed double - based on integer input 4704 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 4705 Op0Mapped, Lo, NULL, 0); 4706 // initial hi portion of constructed double 4707 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 4708 // store the hi of the constructed double - biased exponent 4709 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 4710 // load the constructed double 4711 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 4712 // FP constant to bias correct the final result 4713 SDOperand Bias = DAG.getConstantFP(isSigned ? 4714 BitsToDouble(0x4330000080000000ULL) 4715 : BitsToDouble(0x4330000000000000ULL), 4716 MVT::f64); 4717 // subtract the bias 4718 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 4719 // final result 4720 SDOperand Result; 4721 // handle final rounding 4722 if (DestVT == MVT::f64) { 4723 // do nothing 4724 Result = Sub; 4725 } else { 4726 // if f32 then cast to f32 4727 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 4728 } 4729 return Result; 4730 } 4731 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 4732 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 4733 4734 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 4735 DAG.getConstant(0, Op0.getValueType()), 4736 ISD::SETLT); 4737 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4738 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4739 SignSet, Four, Zero); 4740 4741 // If the sign bit of the integer is set, the large number will be treated 4742 // as a negative number. To counteract this, the dynamic code adds an 4743 // offset depending on the data type. 4744 uint64_t FF; 4745 switch (Op0.getValueType()) { 4746 default: assert(0 && "Unsupported integer type!"); 4747 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 4748 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 4749 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 4750 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 4751 } 4752 if (TLI.isLittleEndian()) FF <<= 32; 4753 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4754 4755 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4756 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4757 SDOperand FudgeInReg; 4758 if (DestVT == MVT::f32) 4759 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4760 else { 4761 assert(DestVT == MVT::f64 && "Unexpected conversion"); 4762 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 4763 DAG.getEntryNode(), CPIdx, 4764 NULL, 0, MVT::f32)); 4765 } 4766 4767 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 4768} 4769 4770/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 4771/// *INT_TO_FP operation of the specified operand when the target requests that 4772/// we promote it. At this point, we know that the result and operand types are 4773/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 4774/// operation that takes a larger input. 4775SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 4776 MVT::ValueType DestVT, 4777 bool isSigned) { 4778 // First step, figure out the appropriate *INT_TO_FP operation to use. 4779 MVT::ValueType NewInTy = LegalOp.getValueType(); 4780 4781 unsigned OpToUse = 0; 4782 4783 // Scan for the appropriate larger type to use. 4784 while (1) { 4785 NewInTy = (MVT::ValueType)(NewInTy+1); 4786 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 4787 4788 // If the target supports SINT_TO_FP of this type, use it. 4789 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 4790 default: break; 4791 case TargetLowering::Legal: 4792 if (!TLI.isTypeLegal(NewInTy)) 4793 break; // Can't use this datatype. 4794 // FALL THROUGH. 4795 case TargetLowering::Custom: 4796 OpToUse = ISD::SINT_TO_FP; 4797 break; 4798 } 4799 if (OpToUse) break; 4800 if (isSigned) continue; 4801 4802 // If the target supports UINT_TO_FP of this type, use it. 4803 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 4804 default: break; 4805 case TargetLowering::Legal: 4806 if (!TLI.isTypeLegal(NewInTy)) 4807 break; // Can't use this datatype. 4808 // FALL THROUGH. 4809 case TargetLowering::Custom: 4810 OpToUse = ISD::UINT_TO_FP; 4811 break; 4812 } 4813 if (OpToUse) break; 4814 4815 // Otherwise, try a larger type. 4816 } 4817 4818 // Okay, we found the operation and type to use. Zero extend our input to the 4819 // desired type then run the operation on it. 4820 return DAG.getNode(OpToUse, DestVT, 4821 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 4822 NewInTy, LegalOp)); 4823} 4824 4825/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 4826/// FP_TO_*INT operation of the specified operand when the target requests that 4827/// we promote it. At this point, we know that the result and operand types are 4828/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 4829/// operation that returns a larger result. 4830SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 4831 MVT::ValueType DestVT, 4832 bool isSigned) { 4833 // First step, figure out the appropriate FP_TO*INT operation to use. 4834 MVT::ValueType NewOutTy = DestVT; 4835 4836 unsigned OpToUse = 0; 4837 4838 // Scan for the appropriate larger type to use. 4839 while (1) { 4840 NewOutTy = (MVT::ValueType)(NewOutTy+1); 4841 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 4842 4843 // If the target supports FP_TO_SINT returning this type, use it. 4844 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 4845 default: break; 4846 case TargetLowering::Legal: 4847 if (!TLI.isTypeLegal(NewOutTy)) 4848 break; // Can't use this datatype. 4849 // FALL THROUGH. 4850 case TargetLowering::Custom: 4851 OpToUse = ISD::FP_TO_SINT; 4852 break; 4853 } 4854 if (OpToUse) break; 4855 4856 // If the target supports FP_TO_UINT of this type, use it. 4857 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 4858 default: break; 4859 case TargetLowering::Legal: 4860 if (!TLI.isTypeLegal(NewOutTy)) 4861 break; // Can't use this datatype. 4862 // FALL THROUGH. 4863 case TargetLowering::Custom: 4864 OpToUse = ISD::FP_TO_UINT; 4865 break; 4866 } 4867 if (OpToUse) break; 4868 4869 // Otherwise, try a larger type. 4870 } 4871 4872 // Okay, we found the operation and type to use. Truncate the result of the 4873 // extended FP_TO_*INT operation to the desired size. 4874 return DAG.getNode(ISD::TRUNCATE, DestVT, 4875 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 4876} 4877 4878/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 4879/// 4880SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 4881 MVT::ValueType VT = Op.getValueType(); 4882 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 4883 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 4884 switch (VT) { 4885 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 4886 case MVT::i16: 4887 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4888 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4889 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 4890 case MVT::i32: 4891 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4892 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4893 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4894 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4895 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 4896 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 4897 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4898 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4899 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4900 case MVT::i64: 4901 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 4902 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 4903 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4904 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4905 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4906 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4907 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 4908 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 4909 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 4910 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 4911 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 4912 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 4913 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 4914 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 4915 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 4916 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 4917 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4918 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4919 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 4920 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4921 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 4922 } 4923} 4924 4925/// ExpandBitCount - Expand the specified bitcount instruction into operations. 4926/// 4927SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 4928 switch (Opc) { 4929 default: assert(0 && "Cannot expand this yet!"); 4930 case ISD::CTPOP: { 4931 static const uint64_t mask[6] = { 4932 0x5555555555555555ULL, 0x3333333333333333ULL, 4933 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 4934 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 4935 }; 4936 MVT::ValueType VT = Op.getValueType(); 4937 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4938 unsigned len = MVT::getSizeInBits(VT); 4939 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4940 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 4941 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 4942 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4943 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 4944 DAG.getNode(ISD::AND, VT, 4945 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 4946 } 4947 return Op; 4948 } 4949 case ISD::CTLZ: { 4950 // for now, we do this: 4951 // x = x | (x >> 1); 4952 // x = x | (x >> 2); 4953 // ... 4954 // x = x | (x >>16); 4955 // x = x | (x >>32); // for 64-bit input 4956 // return popcount(~x); 4957 // 4958 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 4959 MVT::ValueType VT = Op.getValueType(); 4960 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4961 unsigned len = MVT::getSizeInBits(VT); 4962 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4963 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4964 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 4965 } 4966 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 4967 return DAG.getNode(ISD::CTPOP, VT, Op); 4968 } 4969 case ISD::CTTZ: { 4970 // for now, we use: { return popcount(~x & (x - 1)); } 4971 // unless the target has ctlz but not ctpop, in which case we use: 4972 // { return 32 - nlz(~x & (x-1)); } 4973 // see also http://www.hackersdelight.org/HDcode/ntz.cc 4974 MVT::ValueType VT = Op.getValueType(); 4975 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 4976 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 4977 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 4978 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 4979 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 4980 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 4981 TLI.isOperationLegal(ISD::CTLZ, VT)) 4982 return DAG.getNode(ISD::SUB, VT, 4983 DAG.getConstant(MVT::getSizeInBits(VT), VT), 4984 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 4985 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 4986 } 4987 } 4988} 4989 4990/// ExpandOp - Expand the specified SDOperand into its two component pieces 4991/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 4992/// LegalizeNodes map is filled in for any results that are not expanded, the 4993/// ExpandedNodes map is filled in for any results that are expanded, and the 4994/// Lo/Hi values are returned. 4995void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 4996 MVT::ValueType VT = Op.getValueType(); 4997 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4998 SDNode *Node = Op.Val; 4999 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5000 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 5001 MVT::isVector(VT)) && 5002 "Cannot expand to FP value or to larger int value!"); 5003 5004 // See if we already expanded it. 5005 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5006 = ExpandedNodes.find(Op); 5007 if (I != ExpandedNodes.end()) { 5008 Lo = I->second.first; 5009 Hi = I->second.second; 5010 return; 5011 } 5012 5013 switch (Node->getOpcode()) { 5014 case ISD::CopyFromReg: 5015 assert(0 && "CopyFromReg must be legal!"); 5016 default: 5017#ifndef NDEBUG 5018 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5019#endif 5020 assert(0 && "Do not know how to expand this operator!"); 5021 abort(); 5022 case ISD::UNDEF: 5023 NVT = TLI.getTypeToExpandTo(VT); 5024 Lo = DAG.getNode(ISD::UNDEF, NVT); 5025 Hi = DAG.getNode(ISD::UNDEF, NVT); 5026 break; 5027 case ISD::Constant: { 5028 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 5029 Lo = DAG.getConstant(Cst, NVT); 5030 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 5031 break; 5032 } 5033 case ISD::ConstantFP: { 5034 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5035 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5036 if (getTypeAction(Lo.getValueType()) == Expand) 5037 ExpandOp(Lo, Lo, Hi); 5038 break; 5039 } 5040 case ISD::BUILD_PAIR: 5041 // Return the operands. 5042 Lo = Node->getOperand(0); 5043 Hi = Node->getOperand(1); 5044 break; 5045 5046 case ISD::SIGN_EXTEND_INREG: 5047 ExpandOp(Node->getOperand(0), Lo, Hi); 5048 // sext_inreg the low part if needed. 5049 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5050 5051 // The high part gets the sign extension from the lo-part. This handles 5052 // things like sextinreg V:i64 from i8. 5053 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5054 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 5055 TLI.getShiftAmountTy())); 5056 break; 5057 5058 case ISD::BSWAP: { 5059 ExpandOp(Node->getOperand(0), Lo, Hi); 5060 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5061 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5062 Lo = TempLo; 5063 break; 5064 } 5065 5066 case ISD::CTPOP: 5067 ExpandOp(Node->getOperand(0), Lo, Hi); 5068 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5069 DAG.getNode(ISD::CTPOP, NVT, Lo), 5070 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5071 Hi = DAG.getConstant(0, NVT); 5072 break; 5073 5074 case ISD::CTLZ: { 5075 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5076 ExpandOp(Node->getOperand(0), Lo, Hi); 5077 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5078 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5079 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 5080 ISD::SETNE); 5081 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5082 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5083 5084 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5085 Hi = DAG.getConstant(0, NVT); 5086 break; 5087 } 5088 5089 case ISD::CTTZ: { 5090 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5091 ExpandOp(Node->getOperand(0), Lo, Hi); 5092 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5093 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5094 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 5095 ISD::SETNE); 5096 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5097 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5098 5099 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5100 Hi = DAG.getConstant(0, NVT); 5101 break; 5102 } 5103 5104 case ISD::VAARG: { 5105 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5106 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5107 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5108 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5109 5110 // Remember that we legalized the chain. 5111 Hi = LegalizeOp(Hi); 5112 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5113 if (!TLI.isLittleEndian()) 5114 std::swap(Lo, Hi); 5115 break; 5116 } 5117 5118 case ISD::LOAD: { 5119 LoadSDNode *LD = cast<LoadSDNode>(Node); 5120 SDOperand Ch = LD->getChain(); // Legalize the chain. 5121 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5122 ISD::LoadExtType ExtType = LD->getExtensionType(); 5123 int SVOffset = LD->getSrcValueOffset(); 5124 unsigned Alignment = LD->getAlignment(); 5125 bool isVolatile = LD->isVolatile(); 5126 5127 if (ExtType == ISD::NON_EXTLOAD) { 5128 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5129 isVolatile, Alignment); 5130 if (VT == MVT::f32 || VT == MVT::f64) { 5131 // f32->i32 or f64->i64 one to one expansion. 5132 // Remember that we legalized the chain. 5133 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5134 // Recursively expand the new load. 5135 if (getTypeAction(NVT) == Expand) 5136 ExpandOp(Lo, Lo, Hi); 5137 break; 5138 } 5139 5140 // Increment the pointer to the other half. 5141 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 5142 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5143 getIntPtrConstant(IncrementSize)); 5144 SVOffset += IncrementSize; 5145 if (Alignment > IncrementSize) 5146 Alignment = IncrementSize; 5147 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5148 isVolatile, Alignment); 5149 5150 // Build a factor node to remember that this load is independent of the 5151 // other one. 5152 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5153 Hi.getValue(1)); 5154 5155 // Remember that we legalized the chain. 5156 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5157 if (!TLI.isLittleEndian()) 5158 std::swap(Lo, Hi); 5159 } else { 5160 MVT::ValueType EVT = LD->getLoadedVT(); 5161 5162 if (VT == MVT::f64 && EVT == MVT::f32) { 5163 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5164 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5165 SVOffset, isVolatile, Alignment); 5166 // Remember that we legalized the chain. 5167 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 5168 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 5169 break; 5170 } 5171 5172 if (EVT == NVT) 5173 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 5174 SVOffset, isVolatile, Alignment); 5175 else 5176 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 5177 SVOffset, EVT, isVolatile, 5178 Alignment); 5179 5180 // Remember that we legalized the chain. 5181 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5182 5183 if (ExtType == ISD::SEXTLOAD) { 5184 // The high part is obtained by SRA'ing all but one of the bits of the 5185 // lo part. 5186 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5187 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5188 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5189 } else if (ExtType == ISD::ZEXTLOAD) { 5190 // The high part is just a zero. 5191 Hi = DAG.getConstant(0, NVT); 5192 } else /* if (ExtType == ISD::EXTLOAD) */ { 5193 // The high part is undefined. 5194 Hi = DAG.getNode(ISD::UNDEF, NVT); 5195 } 5196 } 5197 break; 5198 } 5199 case ISD::AND: 5200 case ISD::OR: 5201 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 5202 SDOperand LL, LH, RL, RH; 5203 ExpandOp(Node->getOperand(0), LL, LH); 5204 ExpandOp(Node->getOperand(1), RL, RH); 5205 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 5206 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 5207 break; 5208 } 5209 case ISD::SELECT: { 5210 SDOperand LL, LH, RL, RH; 5211 ExpandOp(Node->getOperand(1), LL, LH); 5212 ExpandOp(Node->getOperand(2), RL, RH); 5213 if (getTypeAction(NVT) == Expand) 5214 NVT = TLI.getTypeToExpandTo(NVT); 5215 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 5216 if (VT != MVT::f32) 5217 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 5218 break; 5219 } 5220 case ISD::SELECT_CC: { 5221 SDOperand TL, TH, FL, FH; 5222 ExpandOp(Node->getOperand(2), TL, TH); 5223 ExpandOp(Node->getOperand(3), FL, FH); 5224 if (getTypeAction(NVT) == Expand) 5225 NVT = TLI.getTypeToExpandTo(NVT); 5226 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5227 Node->getOperand(1), TL, FL, Node->getOperand(4)); 5228 if (VT != MVT::f32) 5229 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5230 Node->getOperand(1), TH, FH, Node->getOperand(4)); 5231 break; 5232 } 5233 case ISD::ANY_EXTEND: 5234 // The low part is any extension of the input (which degenerates to a copy). 5235 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 5236 // The high part is undefined. 5237 Hi = DAG.getNode(ISD::UNDEF, NVT); 5238 break; 5239 case ISD::SIGN_EXTEND: { 5240 // The low part is just a sign extension of the input (which degenerates to 5241 // a copy). 5242 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 5243 5244 // The high part is obtained by SRA'ing all but one of the bits of the lo 5245 // part. 5246 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5247 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5248 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5249 break; 5250 } 5251 case ISD::ZERO_EXTEND: 5252 // The low part is just a zero extension of the input (which degenerates to 5253 // a copy). 5254 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 5255 5256 // The high part is just a zero. 5257 Hi = DAG.getConstant(0, NVT); 5258 break; 5259 5260 case ISD::TRUNCATE: { 5261 // The input value must be larger than this value. Expand *it*. 5262 SDOperand NewLo; 5263 ExpandOp(Node->getOperand(0), NewLo, Hi); 5264 5265 // The low part is now either the right size, or it is closer. If not the 5266 // right size, make an illegal truncate so we recursively expand it. 5267 if (NewLo.getValueType() != Node->getValueType(0)) 5268 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 5269 ExpandOp(NewLo, Lo, Hi); 5270 break; 5271 } 5272 5273 case ISD::BIT_CONVERT: { 5274 SDOperand Tmp; 5275 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 5276 // If the target wants to, allow it to lower this itself. 5277 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5278 case Expand: assert(0 && "cannot expand FP!"); 5279 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 5280 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 5281 } 5282 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 5283 } 5284 5285 // f32 / f64 must be expanded to i32 / i64. 5286 if (VT == MVT::f32 || VT == MVT::f64) { 5287 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5288 if (getTypeAction(NVT) == Expand) 5289 ExpandOp(Lo, Lo, Hi); 5290 break; 5291 } 5292 5293 // If source operand will be expanded to the same type as VT, i.e. 5294 // i64 <- f64, i32 <- f32, expand the source operand instead. 5295 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 5296 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 5297 ExpandOp(Node->getOperand(0), Lo, Hi); 5298 break; 5299 } 5300 5301 // Turn this into a load/store pair by default. 5302 if (Tmp.Val == 0) 5303 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0)); 5304 5305 ExpandOp(Tmp, Lo, Hi); 5306 break; 5307 } 5308 5309 case ISD::READCYCLECOUNTER: 5310 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 5311 TargetLowering::Custom && 5312 "Must custom expand ReadCycleCounter"); 5313 Lo = TLI.LowerOperation(Op, DAG); 5314 assert(Lo.Val && "Node must be custom expanded!"); 5315 Hi = Lo.getValue(1); 5316 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 5317 LegalizeOp(Lo.getValue(2))); 5318 break; 5319 5320 // These operators cannot be expanded directly, emit them as calls to 5321 // library functions. 5322 case ISD::FP_TO_SINT: { 5323 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 5324 SDOperand Op; 5325 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5326 case Expand: assert(0 && "cannot expand FP!"); 5327 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5328 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5329 } 5330 5331 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 5332 5333 // Now that the custom expander is done, expand the result, which is still 5334 // VT. 5335 if (Op.Val) { 5336 ExpandOp(Op, Lo, Hi); 5337 break; 5338 } 5339 } 5340 5341 RTLIB::Libcall LC; 5342 if (Node->getOperand(0).getValueType() == MVT::f32) 5343 LC = RTLIB::FPTOSINT_F32_I64; 5344 else 5345 LC = RTLIB::FPTOSINT_F64_I64; 5346 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5347 false/*sign irrelevant*/, Hi); 5348 break; 5349 } 5350 5351 case ISD::FP_TO_UINT: { 5352 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 5353 SDOperand Op; 5354 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5355 case Expand: assert(0 && "cannot expand FP!"); 5356 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5357 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5358 } 5359 5360 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 5361 5362 // Now that the custom expander is done, expand the result. 5363 if (Op.Val) { 5364 ExpandOp(Op, Lo, Hi); 5365 break; 5366 } 5367 } 5368 5369 RTLIB::Libcall LC; 5370 if (Node->getOperand(0).getValueType() == MVT::f32) 5371 LC = RTLIB::FPTOUINT_F32_I64; 5372 else 5373 LC = RTLIB::FPTOUINT_F64_I64; 5374 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5375 false/*sign irrelevant*/, Hi); 5376 break; 5377 } 5378 5379 case ISD::SHL: { 5380 // If the target wants custom lowering, do so. 5381 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5382 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 5383 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 5384 Op = TLI.LowerOperation(Op, DAG); 5385 if (Op.Val) { 5386 // Now that the custom expander is done, expand the result, which is 5387 // still VT. 5388 ExpandOp(Op, Lo, Hi); 5389 break; 5390 } 5391 } 5392 5393 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 5394 // this X << 1 as X+X. 5395 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 5396 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 5397 TLI.isOperationLegal(ISD::ADDE, NVT)) { 5398 SDOperand LoOps[2], HiOps[3]; 5399 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 5400 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 5401 LoOps[1] = LoOps[0]; 5402 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5403 5404 HiOps[1] = HiOps[0]; 5405 HiOps[2] = Lo.getValue(1); 5406 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5407 break; 5408 } 5409 } 5410 5411 // If we can emit an efficient shift operation, do so now. 5412 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5413 break; 5414 5415 // If this target supports SHL_PARTS, use it. 5416 TargetLowering::LegalizeAction Action = 5417 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 5418 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5419 Action == TargetLowering::Custom) { 5420 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5421 break; 5422 } 5423 5424 // Otherwise, emit a libcall. 5425 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 5426 false/*left shift=unsigned*/, Hi); 5427 break; 5428 } 5429 5430 case ISD::SRA: { 5431 // If the target wants custom lowering, do so. 5432 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5433 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 5434 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 5435 Op = TLI.LowerOperation(Op, DAG); 5436 if (Op.Val) { 5437 // Now that the custom expander is done, expand the result, which is 5438 // still VT. 5439 ExpandOp(Op, Lo, Hi); 5440 break; 5441 } 5442 } 5443 5444 // If we can emit an efficient shift operation, do so now. 5445 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5446 break; 5447 5448 // If this target supports SRA_PARTS, use it. 5449 TargetLowering::LegalizeAction Action = 5450 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 5451 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5452 Action == TargetLowering::Custom) { 5453 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5454 break; 5455 } 5456 5457 // Otherwise, emit a libcall. 5458 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 5459 true/*ashr is signed*/, Hi); 5460 break; 5461 } 5462 5463 case ISD::SRL: { 5464 // If the target wants custom lowering, do so. 5465 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5466 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 5467 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 5468 Op = TLI.LowerOperation(Op, DAG); 5469 if (Op.Val) { 5470 // Now that the custom expander is done, expand the result, which is 5471 // still VT. 5472 ExpandOp(Op, Lo, Hi); 5473 break; 5474 } 5475 } 5476 5477 // If we can emit an efficient shift operation, do so now. 5478 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5479 break; 5480 5481 // If this target supports SRL_PARTS, use it. 5482 TargetLowering::LegalizeAction Action = 5483 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 5484 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5485 Action == TargetLowering::Custom) { 5486 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5487 break; 5488 } 5489 5490 // Otherwise, emit a libcall. 5491 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 5492 false/*lshr is unsigned*/, Hi); 5493 break; 5494 } 5495 5496 case ISD::ADD: 5497 case ISD::SUB: { 5498 // If the target wants to custom expand this, let them. 5499 if (TLI.getOperationAction(Node->getOpcode(), VT) == 5500 TargetLowering::Custom) { 5501 Op = TLI.LowerOperation(Op, DAG); 5502 if (Op.Val) { 5503 ExpandOp(Op, Lo, Hi); 5504 break; 5505 } 5506 } 5507 5508 // Expand the subcomponents. 5509 SDOperand LHSL, LHSH, RHSL, RHSH; 5510 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5511 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5512 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5513 SDOperand LoOps[2], HiOps[3]; 5514 LoOps[0] = LHSL; 5515 LoOps[1] = RHSL; 5516 HiOps[0] = LHSH; 5517 HiOps[1] = RHSH; 5518 if (Node->getOpcode() == ISD::ADD) { 5519 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5520 HiOps[2] = Lo.getValue(1); 5521 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5522 } else { 5523 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5524 HiOps[2] = Lo.getValue(1); 5525 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5526 } 5527 break; 5528 } 5529 5530 case ISD::ADDC: 5531 case ISD::SUBC: { 5532 // Expand the subcomponents. 5533 SDOperand LHSL, LHSH, RHSL, RHSH; 5534 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5535 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5536 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5537 SDOperand LoOps[2] = { LHSL, RHSL }; 5538 SDOperand HiOps[3] = { LHSH, RHSH }; 5539 5540 if (Node->getOpcode() == ISD::ADDC) { 5541 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5542 HiOps[2] = Lo.getValue(1); 5543 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5544 } else { 5545 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5546 HiOps[2] = Lo.getValue(1); 5547 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5548 } 5549 // Remember that we legalized the flag. 5550 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5551 break; 5552 } 5553 case ISD::ADDE: 5554 case ISD::SUBE: { 5555 // Expand the subcomponents. 5556 SDOperand LHSL, LHSH, RHSL, RHSH; 5557 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5558 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5559 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5560 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 5561 SDOperand HiOps[3] = { LHSH, RHSH }; 5562 5563 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 5564 HiOps[2] = Lo.getValue(1); 5565 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 5566 5567 // Remember that we legalized the flag. 5568 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5569 break; 5570 } 5571 case ISD::MUL: { 5572 // If the target wants to custom expand this, let them. 5573 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 5574 SDOperand New = TLI.LowerOperation(Op, DAG); 5575 if (New.Val) { 5576 ExpandOp(New, Lo, Hi); 5577 break; 5578 } 5579 } 5580 5581 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 5582 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 5583 if (HasMULHS || HasMULHU) { 5584 SDOperand LL, LH, RL, RH; 5585 ExpandOp(Node->getOperand(0), LL, LH); 5586 ExpandOp(Node->getOperand(1), RL, RH); 5587 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 5588 // FIXME: Move this to the dag combiner. 5589 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 5590 // extended the sign bit of the low half through the upper half, and if so 5591 // emit a MULHS instead of the alternate sequence that is valid for any 5592 // i64 x i64 multiply. 5593 if (HasMULHS && 5594 // is RH an extension of the sign bit of RL? 5595 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 5596 RH.getOperand(1).getOpcode() == ISD::Constant && 5597 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 5598 // is LH an extension of the sign bit of LL? 5599 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 5600 LH.getOperand(1).getOpcode() == ISD::Constant && 5601 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 5602 // Low part: 5603 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5604 // High part: 5605 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 5606 break; 5607 } else if (HasMULHU) { 5608 // Low part: 5609 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5610 5611 // High part: 5612 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 5613 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 5614 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 5615 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 5616 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 5617 break; 5618 } 5619 } 5620 5621 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 5622 false/*sign irrelevant*/, Hi); 5623 break; 5624 } 5625 case ISD::SDIV: 5626 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 5627 break; 5628 case ISD::UDIV: 5629 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 5630 break; 5631 case ISD::SREM: 5632 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 5633 break; 5634 case ISD::UREM: 5635 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 5636 break; 5637 5638 case ISD::FADD: 5639 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5640 ? RTLIB::ADD_F32 : RTLIB::ADD_F64), 5641 Node, false, Hi); 5642 break; 5643 case ISD::FSUB: 5644 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5645 ? RTLIB::SUB_F32 : RTLIB::SUB_F64), 5646 Node, false, Hi); 5647 break; 5648 case ISD::FMUL: 5649 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5650 ? RTLIB::MUL_F32 : RTLIB::MUL_F64), 5651 Node, false, Hi); 5652 break; 5653 case ISD::FDIV: 5654 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5655 ? RTLIB::DIV_F32 : RTLIB::DIV_F64), 5656 Node, false, Hi); 5657 break; 5658 case ISD::FP_EXTEND: 5659 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 5660 break; 5661 case ISD::FP_ROUND: 5662 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 5663 break; 5664 case ISD::FPOWI: 5665 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5666 ? RTLIB::POWI_F32 : RTLIB::POWI_F64), 5667 Node, false, Hi); 5668 break; 5669 case ISD::FSQRT: 5670 case ISD::FSIN: 5671 case ISD::FCOS: { 5672 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5673 switch(Node->getOpcode()) { 5674 case ISD::FSQRT: 5675 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64; 5676 break; 5677 case ISD::FSIN: 5678 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 5679 break; 5680 case ISD::FCOS: 5681 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64; 5682 break; 5683 default: assert(0 && "Unreachable!"); 5684 } 5685 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 5686 break; 5687 } 5688 case ISD::FABS: { 5689 SDOperand Mask = (VT == MVT::f64) 5690 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 5691 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 5692 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 5693 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5694 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 5695 if (getTypeAction(NVT) == Expand) 5696 ExpandOp(Lo, Lo, Hi); 5697 break; 5698 } 5699 case ISD::FNEG: { 5700 SDOperand Mask = (VT == MVT::f64) 5701 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 5702 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 5703 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 5704 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5705 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 5706 if (getTypeAction(NVT) == Expand) 5707 ExpandOp(Lo, Lo, Hi); 5708 break; 5709 } 5710 case ISD::FCOPYSIGN: { 5711 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 5712 if (getTypeAction(NVT) == Expand) 5713 ExpandOp(Lo, Lo, Hi); 5714 break; 5715 } 5716 case ISD::SINT_TO_FP: 5717 case ISD::UINT_TO_FP: { 5718 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 5719 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 5720 RTLIB::Libcall LC; 5721 if (Node->getOperand(0).getValueType() == MVT::i64) { 5722 if (VT == MVT::f32) 5723 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 5724 else 5725 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 5726 } else { 5727 if (VT == MVT::f32) 5728 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 5729 else 5730 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 5731 } 5732 5733 // Promote the operand if needed. 5734 if (getTypeAction(SrcVT) == Promote) { 5735 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 5736 Tmp = isSigned 5737 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 5738 DAG.getValueType(SrcVT)) 5739 : DAG.getZeroExtendInReg(Tmp, SrcVT); 5740 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 5741 } 5742 5743 const char *LibCall = TLI.getLibcallName(LC); 5744 if (LibCall) 5745 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 5746 else { 5747 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 5748 Node->getOperand(0)); 5749 if (getTypeAction(Lo.getValueType()) == Expand) 5750 ExpandOp(Lo, Lo, Hi); 5751 } 5752 break; 5753 } 5754 } 5755 5756 // Make sure the resultant values have been legalized themselves, unless this 5757 // is a type that requires multi-step expansion. 5758 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 5759 Lo = LegalizeOp(Lo); 5760 if (Hi.Val) 5761 // Don't legalize the high part if it is expanded to a single node. 5762 Hi = LegalizeOp(Hi); 5763 } 5764 5765 // Remember in a map if the values will be reused later. 5766 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 5767 assert(isNew && "Value already expanded?!?"); 5768} 5769 5770/// SplitVectorOp - Given an operand of vector type, break it down into 5771/// two smaller values, still of vector type. 5772void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 5773 SDOperand &Hi) { 5774 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); 5775 SDNode *Node = Op.Val; 5776 unsigned NumElements = MVT::getVectorNumElements(Node->getValueType(0)); 5777 assert(NumElements > 1 && "Cannot split a single element vector!"); 5778 unsigned NewNumElts = NumElements/2; 5779 MVT::ValueType NewEltVT = MVT::getVectorElementType(Node->getValueType(0)); 5780 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts); 5781 5782 // See if we already split it. 5783 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5784 = SplitNodes.find(Op); 5785 if (I != SplitNodes.end()) { 5786 Lo = I->second.first; 5787 Hi = I->second.second; 5788 return; 5789 } 5790 5791 switch (Node->getOpcode()) { 5792 default: 5793#ifndef NDEBUG 5794 Node->dump(&DAG); 5795#endif 5796 assert(0 && "Unhandled operation in SplitVectorOp!"); 5797 case ISD::BUILD_PAIR: 5798 Lo = Node->getOperand(0); 5799 Hi = Node->getOperand(1); 5800 break; 5801 case ISD::BUILD_VECTOR: { 5802 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 5803 Node->op_begin()+NewNumElts); 5804 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size()); 5805 5806 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts, 5807 Node->op_end()); 5808 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size()); 5809 break; 5810 } 5811 case ISD::CONCAT_VECTORS: { 5812 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 5813 if (NewNumSubvectors == 1) { 5814 Lo = Node->getOperand(0); 5815 Hi = Node->getOperand(1); 5816 } else { 5817 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 5818 Node->op_begin()+NewNumSubvectors); 5819 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size()); 5820 5821 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 5822 Node->op_end()); 5823 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size()); 5824 } 5825 break; 5826 } 5827 case ISD::ADD: 5828 case ISD::SUB: 5829 case ISD::MUL: 5830 case ISD::FADD: 5831 case ISD::FSUB: 5832 case ISD::FMUL: 5833 case ISD::SDIV: 5834 case ISD::UDIV: 5835 case ISD::FDIV: 5836 case ISD::AND: 5837 case ISD::OR: 5838 case ISD::XOR: { 5839 SDOperand LL, LH, RL, RH; 5840 SplitVectorOp(Node->getOperand(0), LL, LH); 5841 SplitVectorOp(Node->getOperand(1), RL, RH); 5842 5843 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL); 5844 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH); 5845 break; 5846 } 5847 case ISD::LOAD: { 5848 LoadSDNode *LD = cast<LoadSDNode>(Node); 5849 SDOperand Ch = LD->getChain(); 5850 SDOperand Ptr = LD->getBasePtr(); 5851 const Value *SV = LD->getSrcValue(); 5852 int SVOffset = LD->getSrcValueOffset(); 5853 unsigned Alignment = LD->getAlignment(); 5854 bool isVolatile = LD->isVolatile(); 5855 5856 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 5857 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8; 5858 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5859 getIntPtrConstant(IncrementSize)); 5860 SVOffset += IncrementSize; 5861 if (Alignment > IncrementSize) 5862 Alignment = IncrementSize; 5863 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 5864 5865 // Build a factor node to remember that this load is independent of the 5866 // other one. 5867 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5868 Hi.getValue(1)); 5869 5870 // Remember that we legalized the chain. 5871 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5872 break; 5873 } 5874 case ISD::BIT_CONVERT: { 5875 // We know the result is a vector. The input may be either a vector or a 5876 // scalar value. 5877 SDOperand InOp = Node->getOperand(0); 5878 if (!MVT::isVector(InOp.getValueType()) || 5879 MVT::getVectorNumElements(InOp.getValueType()) == 1) { 5880 // The input is a scalar or single-element vector. 5881 // Lower to a store/load so that it can be split. 5882 // FIXME: this could be improved probably. 5883 SDOperand Ptr = CreateStackTemporary(InOp.getValueType()); 5884 5885 SDOperand St = DAG.getStore(DAG.getEntryNode(), 5886 InOp, Ptr, NULL, 0); 5887 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0); 5888 } 5889 // Split the vector and convert each of the pieces now. 5890 SplitVectorOp(InOp, Lo, Hi); 5891 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo); 5892 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi); 5893 break; 5894 } 5895 } 5896 5897 // Remember in a map if the values will be reused later. 5898 bool isNew = 5899 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 5900 assert(isNew && "Value already split?!?"); 5901} 5902 5903 5904/// ScalarizeVectorOp - Given an operand of single-element vector type 5905/// (e.g. v1f32), convert it into the equivalent operation that returns a 5906/// scalar (e.g. f32) value. 5907SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 5908 assert(MVT::isVector(Op.getValueType()) && 5909 "Bad ScalarizeVectorOp invocation!"); 5910 SDNode *Node = Op.Val; 5911 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); 5912 assert(MVT::getVectorNumElements(Op.getValueType()) == 1); 5913 5914 // See if we already scalarized it. 5915 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 5916 if (I != ScalarizedNodes.end()) return I->second; 5917 5918 SDOperand Result; 5919 switch (Node->getOpcode()) { 5920 default: 5921#ifndef NDEBUG 5922 Node->dump(&DAG); cerr << "\n"; 5923#endif 5924 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 5925 case ISD::ADD: 5926 case ISD::FADD: 5927 case ISD::SUB: 5928 case ISD::FSUB: 5929 case ISD::MUL: 5930 case ISD::FMUL: 5931 case ISD::SDIV: 5932 case ISD::UDIV: 5933 case ISD::FDIV: 5934 case ISD::SREM: 5935 case ISD::UREM: 5936 case ISD::FREM: 5937 case ISD::AND: 5938 case ISD::OR: 5939 case ISD::XOR: 5940 Result = DAG.getNode(Node->getOpcode(), 5941 NewVT, 5942 ScalarizeVectorOp(Node->getOperand(0)), 5943 ScalarizeVectorOp(Node->getOperand(1))); 5944 break; 5945 case ISD::FNEG: 5946 case ISD::FABS: 5947 case ISD::FSQRT: 5948 case ISD::FSIN: 5949 case ISD::FCOS: 5950 Result = DAG.getNode(Node->getOpcode(), 5951 NewVT, 5952 ScalarizeVectorOp(Node->getOperand(0))); 5953 break; 5954 case ISD::LOAD: { 5955 LoadSDNode *LD = cast<LoadSDNode>(Node); 5956 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 5957 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 5958 5959 const Value *SV = LD->getSrcValue(); 5960 int SVOffset = LD->getSrcValueOffset(); 5961 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 5962 LD->isVolatile(), LD->getAlignment()); 5963 5964 // Remember that we legalized the chain. 5965 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 5966 break; 5967 } 5968 case ISD::BUILD_VECTOR: 5969 Result = Node->getOperand(0); 5970 break; 5971 case ISD::INSERT_VECTOR_ELT: 5972 // Returning the inserted scalar element. 5973 Result = Node->getOperand(1); 5974 break; 5975 case ISD::CONCAT_VECTORS: 5976 assert(Node->getOperand(0).getValueType() == NewVT && 5977 "Concat of non-legal vectors not yet supported!"); 5978 Result = Node->getOperand(0); 5979 break; 5980 case ISD::VECTOR_SHUFFLE: { 5981 // Figure out if the scalar is the LHS or RHS and return it. 5982 SDOperand EltNum = Node->getOperand(2).getOperand(0); 5983 if (cast<ConstantSDNode>(EltNum)->getValue()) 5984 Result = ScalarizeVectorOp(Node->getOperand(1)); 5985 else 5986 Result = ScalarizeVectorOp(Node->getOperand(0)); 5987 break; 5988 } 5989 case ISD::EXTRACT_SUBVECTOR: 5990 Result = Node->getOperand(0); 5991 assert(Result.getValueType() == NewVT); 5992 break; 5993 case ISD::BIT_CONVERT: 5994 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 5995 break; 5996 case ISD::SELECT: 5997 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 5998 ScalarizeVectorOp(Op.getOperand(1)), 5999 ScalarizeVectorOp(Op.getOperand(2))); 6000 break; 6001 } 6002 6003 if (TLI.isTypeLegal(NewVT)) 6004 Result = LegalizeOp(Result); 6005 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 6006 assert(isNew && "Value already scalarized?"); 6007 return Result; 6008} 6009 6010 6011// SelectionDAG::Legalize - This is the entry point for the file. 6012// 6013void SelectionDAG::Legalize() { 6014 if (ViewLegalizeDAGs) viewGraph(); 6015 6016 /// run - This is the main entry point to this class. 6017 /// 6018 SelectionDAGLegalize(*this).LegalizeDAG(); 6019} 6020 6021