LegalizeDAG.cpp revision a0d3608864af5d055696d047cb82f29dca64f670
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/Target/TargetFrameInfo.h" 20#include "llvm/Target/TargetLowering.h" 21#include "llvm/Target/TargetData.h" 22#include "llvm/Target/TargetMachine.h" 23#include "llvm/Target/TargetOptions.h" 24#include "llvm/CallingConv.h" 25#include "llvm/Constants.h" 26#include "llvm/DerivedTypes.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Compiler.h" 29#include "llvm/Support/MathExtras.h" 30#include "llvm/ADT/DenseMap.h" 31#include "llvm/ADT/SmallVector.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include <map> 34using namespace llvm; 35 36#ifndef NDEBUG 37static cl::opt<bool> 38ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 39 cl::desc("Pop up a window to show dags before legalize")); 40#else 41static const bool ViewLegalizeDAGs = 0; 42#endif 43 44//===----------------------------------------------------------------------===// 45/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 46/// hacks on it until the target machine can handle it. This involves 47/// eliminating value sizes the machine cannot handle (promoting small sizes to 48/// large sizes or splitting up large values into small values) as well as 49/// eliminating operations the machine cannot handle. 50/// 51/// This code also does a small amount of optimization and recognition of idioms 52/// as part of its processing. For example, if a target does not support a 53/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 54/// will attempt merge setcc and brc instructions into brcc's. 55/// 56namespace { 57class VISIBILITY_HIDDEN SelectionDAGLegalize { 58 TargetLowering &TLI; 59 SelectionDAG &DAG; 60 61 // Libcall insertion helpers. 62 63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 64 /// legalized. We use this to ensure that calls are properly serialized 65 /// against each other, including inserted libcalls. 66 SDOperand LastCALLSEQ_END; 67 68 /// IsLegalizingCall - This member is used *only* for purposes of providing 69 /// helpful assertions that a libcall isn't created while another call is 70 /// being legalized (which could lead to non-serialized call sequences). 71 bool IsLegalizingCall; 72 73 enum LegalizeAction { 74 Legal, // The target natively supports this operation. 75 Promote, // This operation should be executed in a larger type. 76 Expand // Try to expand this to other ops, otherwise use a libcall. 77 }; 78 79 /// ValueTypeActions - This is a bitvector that contains two bits for each 80 /// value type, where the two bits correspond to the LegalizeAction enum. 81 /// This can be queried with "getTypeAction(VT)". 82 TargetLowering::ValueTypeActionImpl ValueTypeActions; 83 84 /// LegalizedNodes - For nodes that are of legal width, and that have more 85 /// than one use, this map indicates what regularized operand to use. This 86 /// allows us to avoid legalizing the same thing more than once. 87 DenseMap<SDOperand, SDOperand> LegalizedNodes; 88 89 /// PromotedNodes - For nodes that are below legal width, and that have more 90 /// than one use, this map indicates what promoted value to use. This allows 91 /// us to avoid promoting the same thing more than once. 92 DenseMap<SDOperand, SDOperand> PromotedNodes; 93 94 /// ExpandedNodes - For nodes that need to be expanded this map indicates 95 /// which which operands are the expanded version of the input. This allows 96 /// us to avoid expanding the same node more than once. 97 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 98 99 /// SplitNodes - For vector nodes that need to be split, this map indicates 100 /// which which operands are the split version of the input. This allows us 101 /// to avoid splitting the same node more than once. 102 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 103 104 /// ScalarizedNodes - For nodes that need to be converted from vector types to 105 /// scalar types, this contains the mapping of ones we have already 106 /// processed to the result. 107 std::map<SDOperand, SDOperand> ScalarizedNodes; 108 109 void AddLegalizedOperand(SDOperand From, SDOperand To) { 110 LegalizedNodes.insert(std::make_pair(From, To)); 111 // If someone requests legalization of the new node, return itself. 112 if (From != To) 113 LegalizedNodes.insert(std::make_pair(To, To)); 114 } 115 void AddPromotedOperand(SDOperand From, SDOperand To) { 116 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 117 assert(isNew && "Got into the map somehow?"); 118 // If someone requests legalization of the new node, return itself. 119 LegalizedNodes.insert(std::make_pair(To, To)); 120 } 121 122public: 123 124 SelectionDAGLegalize(SelectionDAG &DAG); 125 126 /// getTypeAction - Return how we should legalize values of this type, either 127 /// it is already legal or we need to expand it into multiple registers of 128 /// smaller integer type, or we need to promote it to a larger type. 129 LegalizeAction getTypeAction(MVT::ValueType VT) const { 130 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 131 } 132 133 /// isTypeLegal - Return true if this type is legal on this target. 134 /// 135 bool isTypeLegal(MVT::ValueType VT) const { 136 return getTypeAction(VT) == Legal; 137 } 138 139 void LegalizeDAG(); 140 141private: 142 /// HandleOp - Legalize, Promote, or Expand the specified operand as 143 /// appropriate for its type. 144 void HandleOp(SDOperand Op); 145 146 /// LegalizeOp - We know that the specified value has a legal type. 147 /// Recursively ensure that the operands have legal types, then return the 148 /// result. 149 SDOperand LegalizeOp(SDOperand O); 150 151 /// UnrollVectorOp - We know that the given vector has a legal type, however 152 /// the operation it performs is not legal and is an operation that we have 153 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 154 /// operating on each element individually. 155 SDOperand UnrollVectorOp(SDOperand O); 156 157 /// PromoteOp - Given an operation that produces a value in an invalid type, 158 /// promote it to compute the value into a larger type. The produced value 159 /// will have the correct bits for the low portion of the register, but no 160 /// guarantee is made about the top bits: it may be zero, sign-extended, or 161 /// garbage. 162 SDOperand PromoteOp(SDOperand O); 163 164 /// ExpandOp - Expand the specified SDOperand into its two component pieces 165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 166 /// the LegalizeNodes map is filled in for any results that are not expanded, 167 /// the ExpandedNodes map is filled in for any results that are expanded, and 168 /// the Lo/Hi values are returned. This applies to integer types and Vector 169 /// types. 170 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 171 172 /// SplitVectorOp - Given an operand of vector type, break it down into 173 /// two smaller values. 174 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 175 176 /// ScalarizeVectorOp - Given an operand of single-element vector type 177 /// (e.g. v1f32), convert it into the equivalent operation that returns a 178 /// scalar (e.g. f32) value. 179 SDOperand ScalarizeVectorOp(SDOperand O); 180 181 /// isShuffleLegal - Return true if a vector shuffle is legal with the 182 /// specified mask and type. Targets can specify exactly which masks they 183 /// support and the code generator is tasked with not creating illegal masks. 184 /// 185 /// Note that this will also return true for shuffles that are promoted to a 186 /// different type. 187 /// 188 /// If this is a legal shuffle, this method returns the (possibly promoted) 189 /// build_vector Mask. If it's not a legal shuffle, it returns null. 190 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 191 192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 194 195 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 196 197 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 198 SDOperand &Hi); 199 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 200 SDOperand Source); 201 202 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT, 203 MVT::ValueType DestVT); 204 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 205 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 206 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 207 SDOperand LegalOp, 208 MVT::ValueType DestVT); 209 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 210 bool isSigned); 211 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 212 bool isSigned); 213 214 SDOperand ExpandBSWAP(SDOperand Op); 215 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 216 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 217 SDOperand &Lo, SDOperand &Hi); 218 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 219 SDOperand &Lo, SDOperand &Hi); 220 221 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 222 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 223}; 224} 225 226/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 227/// specified mask and type. Targets can specify exactly which masks they 228/// support and the code generator is tasked with not creating illegal masks. 229/// 230/// Note that this will also return true for shuffles that are promoted to a 231/// different type. 232SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 233 SDOperand Mask) const { 234 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 235 default: return 0; 236 case TargetLowering::Legal: 237 case TargetLowering::Custom: 238 break; 239 case TargetLowering::Promote: { 240 // If this is promoted to a different type, convert the shuffle mask and 241 // ask if it is legal in the promoted type! 242 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 243 244 // If we changed # elements, change the shuffle mask. 245 unsigned NumEltsGrowth = 246 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 247 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 248 if (NumEltsGrowth > 1) { 249 // Renumber the elements. 250 SmallVector<SDOperand, 8> Ops; 251 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 252 SDOperand InOp = Mask.getOperand(i); 253 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 254 if (InOp.getOpcode() == ISD::UNDEF) 255 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 256 else { 257 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 258 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 259 } 260 } 261 } 262 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 263 } 264 VT = NVT; 265 break; 266 } 267 } 268 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 269} 270 271SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 272 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 273 ValueTypeActions(TLI.getValueTypeActions()) { 274 assert(MVT::LAST_VALUETYPE <= 32 && 275 "Too many value types for ValueTypeActions to hold!"); 276} 277 278/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 279/// contains all of a nodes operands before it contains the node. 280static void ComputeTopDownOrdering(SelectionDAG &DAG, 281 SmallVector<SDNode*, 64> &Order) { 282 283 DenseMap<SDNode*, unsigned> Visited; 284 std::vector<SDNode*> Worklist; 285 Worklist.reserve(128); 286 287 // Compute ordering from all of the leaves in the graphs, those (like the 288 // entry node) that have no operands. 289 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 290 E = DAG.allnodes_end(); I != E; ++I) { 291 if (I->getNumOperands() == 0) { 292 Visited[I] = 0 - 1U; 293 Worklist.push_back(I); 294 } 295 } 296 297 while (!Worklist.empty()) { 298 SDNode *N = Worklist.back(); 299 Worklist.pop_back(); 300 301 if (++Visited[N] != N->getNumOperands()) 302 continue; // Haven't visited all operands yet 303 304 Order.push_back(N); 305 306 // Now that we have N in, add anything that uses it if all of their operands 307 // are now done. 308 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 309 UI != E; ++UI) 310 Worklist.push_back(*UI); 311 } 312 313 assert(Order.size() == Visited.size() && 314 Order.size() == 315 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 316 "Error: DAG is cyclic!"); 317} 318 319 320void SelectionDAGLegalize::LegalizeDAG() { 321 LastCALLSEQ_END = DAG.getEntryNode(); 322 IsLegalizingCall = false; 323 324 // The legalize process is inherently a bottom-up recursive process (users 325 // legalize their uses before themselves). Given infinite stack space, we 326 // could just start legalizing on the root and traverse the whole graph. In 327 // practice however, this causes us to run out of stack space on large basic 328 // blocks. To avoid this problem, compute an ordering of the nodes where each 329 // node is only legalized after all of its operands are legalized. 330 SmallVector<SDNode*, 64> Order; 331 ComputeTopDownOrdering(DAG, Order); 332 333 for (unsigned i = 0, e = Order.size(); i != e; ++i) 334 HandleOp(SDOperand(Order[i], 0)); 335 336 // Finally, it's possible the root changed. Get the new root. 337 SDOperand OldRoot = DAG.getRoot(); 338 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 339 DAG.setRoot(LegalizedNodes[OldRoot]); 340 341 ExpandedNodes.clear(); 342 LegalizedNodes.clear(); 343 PromotedNodes.clear(); 344 SplitNodes.clear(); 345 ScalarizedNodes.clear(); 346 347 // Remove dead nodes now. 348 DAG.RemoveDeadNodes(); 349} 350 351 352/// FindCallEndFromCallStart - Given a chained node that is part of a call 353/// sequence, find the CALLSEQ_END node that terminates the call sequence. 354static SDNode *FindCallEndFromCallStart(SDNode *Node) { 355 if (Node->getOpcode() == ISD::CALLSEQ_END) 356 return Node; 357 if (Node->use_empty()) 358 return 0; // No CallSeqEnd 359 360 // The chain is usually at the end. 361 SDOperand TheChain(Node, Node->getNumValues()-1); 362 if (TheChain.getValueType() != MVT::Other) { 363 // Sometimes it's at the beginning. 364 TheChain = SDOperand(Node, 0); 365 if (TheChain.getValueType() != MVT::Other) { 366 // Otherwise, hunt for it. 367 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 368 if (Node->getValueType(i) == MVT::Other) { 369 TheChain = SDOperand(Node, i); 370 break; 371 } 372 373 // Otherwise, we walked into a node without a chain. 374 if (TheChain.getValueType() != MVT::Other) 375 return 0; 376 } 377 } 378 379 for (SDNode::use_iterator UI = Node->use_begin(), 380 E = Node->use_end(); UI != E; ++UI) { 381 382 // Make sure to only follow users of our token chain. 383 SDNode *User = *UI; 384 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 385 if (User->getOperand(i) == TheChain) 386 if (SDNode *Result = FindCallEndFromCallStart(User)) 387 return Result; 388 } 389 return 0; 390} 391 392/// FindCallStartFromCallEnd - Given a chained node that is part of a call 393/// sequence, find the CALLSEQ_START node that initiates the call sequence. 394static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 395 assert(Node && "Didn't find callseq_start for a call??"); 396 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 397 398 assert(Node->getOperand(0).getValueType() == MVT::Other && 399 "Node doesn't have a token chain argument!"); 400 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 401} 402 403/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 404/// see if any uses can reach Dest. If no dest operands can get to dest, 405/// legalize them, legalize ourself, and return false, otherwise, return true. 406/// 407/// Keep track of the nodes we fine that actually do lead to Dest in 408/// NodesLeadingTo. This avoids retraversing them exponential number of times. 409/// 410bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 411 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 412 if (N == Dest) return true; // N certainly leads to Dest :) 413 414 // If we've already processed this node and it does lead to Dest, there is no 415 // need to reprocess it. 416 if (NodesLeadingTo.count(N)) return true; 417 418 // If the first result of this node has been already legalized, then it cannot 419 // reach N. 420 switch (getTypeAction(N->getValueType(0))) { 421 case Legal: 422 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 423 break; 424 case Promote: 425 if (PromotedNodes.count(SDOperand(N, 0))) return false; 426 break; 427 case Expand: 428 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 429 break; 430 } 431 432 // Okay, this node has not already been legalized. Check and legalize all 433 // operands. If none lead to Dest, then we can legalize this node. 434 bool OperandsLeadToDest = false; 435 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 436 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 437 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 438 439 if (OperandsLeadToDest) { 440 NodesLeadingTo.insert(N); 441 return true; 442 } 443 444 // Okay, this node looks safe, legalize it and return false. 445 HandleOp(SDOperand(N, 0)); 446 return false; 447} 448 449/// HandleOp - Legalize, Promote, or Expand the specified operand as 450/// appropriate for its type. 451void SelectionDAGLegalize::HandleOp(SDOperand Op) { 452 MVT::ValueType VT = Op.getValueType(); 453 switch (getTypeAction(VT)) { 454 default: assert(0 && "Bad type action!"); 455 case Legal: (void)LegalizeOp(Op); break; 456 case Promote: (void)PromoteOp(Op); break; 457 case Expand: 458 if (!MVT::isVector(VT)) { 459 // If this is an illegal scalar, expand it into its two component 460 // pieces. 461 SDOperand X, Y; 462 if (Op.getOpcode() == ISD::TargetConstant) 463 break; // Allow illegal target nodes. 464 ExpandOp(Op, X, Y); 465 } else if (MVT::getVectorNumElements(VT) == 1) { 466 // If this is an illegal single element vector, convert it to a 467 // scalar operation. 468 (void)ScalarizeVectorOp(Op); 469 } else { 470 // Otherwise, this is an illegal multiple element vector. 471 // Split it in half and legalize both parts. 472 SDOperand X, Y; 473 SplitVectorOp(Op, X, Y); 474 } 475 break; 476 } 477} 478 479/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 480/// a load from the constant pool. 481static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 482 SelectionDAG &DAG, TargetLowering &TLI) { 483 bool Extend = false; 484 485 // If a FP immediate is precise when represented as a float and if the 486 // target can do an extending load from float to double, we put it into 487 // the constant pool as a float, even if it's is statically typed as a 488 // double. 489 MVT::ValueType VT = CFP->getValueType(0); 490 bool isDouble = VT == MVT::f64; 491 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT), 492 CFP->getValueAPF()); 493 if (!UseCP) { 494 if (VT!=MVT::f64 && VT!=MVT::f32) 495 assert(0 && "Invalid type expansion"); 496 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(), 497 isDouble ? MVT::i64 : MVT::i32); 498 } 499 500 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) && 501 // Only do this if the target has a native EXTLOAD instruction from f32. 502 // Do not try to be clever about long doubles (so far) 503 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 504 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 505 VT = MVT::f32; 506 Extend = true; 507 } 508 509 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 510 if (Extend) { 511 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 512 CPIdx, NULL, 0, MVT::f32); 513 } else { 514 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 515 } 516} 517 518 519/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 520/// operations. 521static 522SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 523 SelectionDAG &DAG, TargetLowering &TLI) { 524 MVT::ValueType VT = Node->getValueType(0); 525 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 526 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 527 "fcopysign expansion only supported for f32 and f64"); 528 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 529 530 // First get the sign bit of second operand. 531 SDOperand Mask1 = (SrcVT == MVT::f64) 532 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 533 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 534 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 535 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 536 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 537 // Shift right or sign-extend it if the two operands have different types. 538 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 539 if (SizeDiff > 0) { 540 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 541 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 542 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 543 } else if (SizeDiff < 0) 544 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 545 546 // Clear the sign bit of first operand. 547 SDOperand Mask2 = (VT == MVT::f64) 548 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 549 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 550 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 551 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 552 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 553 554 // Or the value with the sign bit. 555 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 556 return Result; 557} 558 559/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 560static 561SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 562 TargetLowering &TLI) { 563 SDOperand Chain = ST->getChain(); 564 SDOperand Ptr = ST->getBasePtr(); 565 SDOperand Val = ST->getValue(); 566 MVT::ValueType VT = Val.getValueType(); 567 int Alignment = ST->getAlignment(); 568 int SVOffset = ST->getSrcValueOffset(); 569 if (MVT::isFloatingPoint(ST->getStoredVT())) { 570 // Expand to a bitconvert of the value to the integer type of the 571 // same size, then a (misaligned) int store. 572 MVT::ValueType intVT; 573 if (VT==MVT::f64) 574 intVT = MVT::i64; 575 else if (VT==MVT::f32) 576 intVT = MVT::i32; 577 else 578 assert(0 && "Unaligned load of unsupported floating point type"); 579 580 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 581 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 582 SVOffset, ST->isVolatile(), Alignment); 583 } 584 assert(MVT::isInteger(ST->getStoredVT()) && 585 "Unaligned store of unknown type."); 586 // Get the half-size VT 587 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1; 588 int NumBits = MVT::getSizeInBits(NewStoredVT); 589 int IncrementSize = NumBits / 8; 590 591 // Divide the stored value in two parts. 592 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 593 SDOperand Lo = Val; 594 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 595 596 // Store the two parts 597 SDOperand Store1, Store2; 598 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 599 ST->getSrcValue(), SVOffset, NewStoredVT, 600 ST->isVolatile(), Alignment); 601 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 602 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 603 Alignment = MinAlign(Alignment, IncrementSize); 604 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 605 ST->getSrcValue(), SVOffset + IncrementSize, 606 NewStoredVT, ST->isVolatile(), Alignment); 607 608 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 609} 610 611/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 612static 613SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 614 TargetLowering &TLI) { 615 int SVOffset = LD->getSrcValueOffset(); 616 SDOperand Chain = LD->getChain(); 617 SDOperand Ptr = LD->getBasePtr(); 618 MVT::ValueType VT = LD->getValueType(0); 619 MVT::ValueType LoadedVT = LD->getLoadedVT(); 620 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) { 621 // Expand to a (misaligned) integer load of the same size, 622 // then bitconvert to floating point. 623 MVT::ValueType intVT; 624 if (LoadedVT == MVT::f64) 625 intVT = MVT::i64; 626 else if (LoadedVT == MVT::f32) 627 intVT = MVT::i32; 628 else 629 assert(0 && "Unaligned load of unsupported floating point type"); 630 631 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 632 SVOffset, LD->isVolatile(), 633 LD->getAlignment()); 634 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 635 if (LoadedVT != VT) 636 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 637 638 SDOperand Ops[] = { Result, Chain }; 639 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 640 Ops, 2); 641 } 642 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) && 643 "Unaligned load of unsupported type."); 644 645 // Compute the new VT that is half the size of the old one. We either have an 646 // integer MVT or we have a vector MVT. 647 unsigned NumBits = MVT::getSizeInBits(LoadedVT); 648 MVT::ValueType NewLoadedVT; 649 if (!MVT::isVector(LoadedVT)) { 650 NewLoadedVT = MVT::getIntegerType(NumBits/2); 651 } else { 652 // FIXME: This is not right for <1 x anything> it is also not right for 653 // non-power-of-two vectors. 654 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT), 655 MVT::getVectorNumElements(LoadedVT)/2); 656 } 657 NumBits >>= 1; 658 659 unsigned Alignment = LD->getAlignment(); 660 unsigned IncrementSize = NumBits / 8; 661 ISD::LoadExtType HiExtType = LD->getExtensionType(); 662 663 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 664 if (HiExtType == ISD::NON_EXTLOAD) 665 HiExtType = ISD::ZEXTLOAD; 666 667 // Load the value in two parts 668 SDOperand Lo, Hi; 669 if (TLI.isLittleEndian()) { 670 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 671 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 672 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 673 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 674 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 675 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 676 MinAlign(Alignment, IncrementSize)); 677 } else { 678 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 679 NewLoadedVT,LD->isVolatile(), Alignment); 680 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 681 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 682 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 683 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 684 MinAlign(Alignment, IncrementSize)); 685 } 686 687 // aggregate the two parts 688 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 689 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 690 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 691 692 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 693 Hi.getValue(1)); 694 695 SDOperand Ops[] = { Result, TF }; 696 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 697} 698 699/// UnrollVectorOp - We know that the given vector has a legal type, however 700/// the operation it performs is not legal and is an operation that we have 701/// no way of lowering. "Unroll" the vector, splitting out the scalars and 702/// operating on each element individually. 703SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 704 MVT::ValueType VT = Op.getValueType(); 705 assert(isTypeLegal(VT) && 706 "Caller should expand or promote operands that are not legal!"); 707 assert(Op.Val->getNumValues() == 1 && 708 "Can't unroll a vector with multiple results!"); 709 unsigned NE = MVT::getVectorNumElements(VT); 710 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 711 712 SmallVector<SDOperand, 8> Scalars; 713 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 714 for (unsigned i = 0; i != NE; ++i) { 715 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 716 SDOperand Operand = Op.getOperand(j); 717 MVT::ValueType OperandVT = Operand.getValueType(); 718 if (MVT::isVector(OperandVT)) { 719 // A vector operand; extract a single element. 720 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT); 721 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 722 OperandEltVT, 723 Operand, 724 DAG.getConstant(i, MVT::i32)); 725 } else { 726 // A scalar operand; just use it as is. 727 Operands[j] = Operand; 728 } 729 } 730 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 731 &Operands[0], Operands.size())); 732 } 733 734 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 735} 736 737/// GetFPLibCall - Return the right libcall for the given floating point type. 738static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT, 739 RTLIB::Libcall Call_F32, 740 RTLIB::Libcall Call_F64, 741 RTLIB::Libcall Call_F80, 742 RTLIB::Libcall Call_PPCF128) { 743 return 744 VT == MVT::f32 ? Call_F32 : 745 VT == MVT::f64 ? Call_F64 : 746 VT == MVT::f80 ? Call_F80 : 747 VT == MVT::ppcf128 ? Call_PPCF128 : 748 RTLIB::UNKNOWN_LIBCALL; 749} 750 751/// LegalizeOp - We know that the specified value has a legal type, and 752/// that its operands are legal. Now ensure that the operation itself 753/// is legal, recursively ensuring that the operands' operations remain 754/// legal. 755SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 756 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 757 return Op; 758 759 assert(isTypeLegal(Op.getValueType()) && 760 "Caller should expand or promote operands that are not legal!"); 761 SDNode *Node = Op.Val; 762 763 // If this operation defines any values that cannot be represented in a 764 // register on this target, make sure to expand or promote them. 765 if (Node->getNumValues() > 1) { 766 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 767 if (getTypeAction(Node->getValueType(i)) != Legal) { 768 HandleOp(Op.getValue(i)); 769 assert(LegalizedNodes.count(Op) && 770 "Handling didn't add legal operands!"); 771 return LegalizedNodes[Op]; 772 } 773 } 774 775 // Note that LegalizeOp may be reentered even from single-use nodes, which 776 // means that we always must cache transformed nodes. 777 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 778 if (I != LegalizedNodes.end()) return I->second; 779 780 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 781 SDOperand Result = Op; 782 bool isCustom = false; 783 784 switch (Node->getOpcode()) { 785 case ISD::FrameIndex: 786 case ISD::EntryToken: 787 case ISD::Register: 788 case ISD::BasicBlock: 789 case ISD::TargetFrameIndex: 790 case ISD::TargetJumpTable: 791 case ISD::TargetConstant: 792 case ISD::TargetConstantFP: 793 case ISD::TargetConstantPool: 794 case ISD::TargetGlobalAddress: 795 case ISD::TargetGlobalTLSAddress: 796 case ISD::TargetExternalSymbol: 797 case ISD::VALUETYPE: 798 case ISD::SRCVALUE: 799 case ISD::STRING: 800 case ISD::CONDCODE: 801 // Primitives must all be legal. 802 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 803 "This must be legal!"); 804 break; 805 default: 806 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 807 // If this is a target node, legalize it by legalizing the operands then 808 // passing it through. 809 SmallVector<SDOperand, 8> Ops; 810 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 811 Ops.push_back(LegalizeOp(Node->getOperand(i))); 812 813 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 814 815 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 816 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 817 return Result.getValue(Op.ResNo); 818 } 819 // Otherwise this is an unhandled builtin node. splat. 820#ifndef NDEBUG 821 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 822#endif 823 assert(0 && "Do not know how to legalize this operator!"); 824 abort(); 825 case ISD::GLOBAL_OFFSET_TABLE: 826 case ISD::GlobalAddress: 827 case ISD::GlobalTLSAddress: 828 case ISD::ExternalSymbol: 829 case ISD::ConstantPool: 830 case ISD::JumpTable: // Nothing to do. 831 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 832 default: assert(0 && "This action is not supported yet!"); 833 case TargetLowering::Custom: 834 Tmp1 = TLI.LowerOperation(Op, DAG); 835 if (Tmp1.Val) Result = Tmp1; 836 // FALLTHROUGH if the target doesn't want to lower this op after all. 837 case TargetLowering::Legal: 838 break; 839 } 840 break; 841 case ISD::FRAMEADDR: 842 case ISD::RETURNADDR: 843 // The only option for these nodes is to custom lower them. If the target 844 // does not custom lower them, then return zero. 845 Tmp1 = TLI.LowerOperation(Op, DAG); 846 if (Tmp1.Val) 847 Result = Tmp1; 848 else 849 Result = DAG.getConstant(0, TLI.getPointerTy()); 850 break; 851 case ISD::FRAME_TO_ARGS_OFFSET: { 852 MVT::ValueType VT = Node->getValueType(0); 853 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 854 default: assert(0 && "This action is not supported yet!"); 855 case TargetLowering::Custom: 856 Result = TLI.LowerOperation(Op, DAG); 857 if (Result.Val) break; 858 // Fall Thru 859 case TargetLowering::Legal: 860 Result = DAG.getConstant(0, VT); 861 break; 862 } 863 } 864 break; 865 case ISD::EXCEPTIONADDR: { 866 Tmp1 = LegalizeOp(Node->getOperand(0)); 867 MVT::ValueType VT = Node->getValueType(0); 868 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 869 default: assert(0 && "This action is not supported yet!"); 870 case TargetLowering::Expand: { 871 unsigned Reg = TLI.getExceptionAddressRegister(); 872 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 873 } 874 break; 875 case TargetLowering::Custom: 876 Result = TLI.LowerOperation(Op, DAG); 877 if (Result.Val) break; 878 // Fall Thru 879 case TargetLowering::Legal: { 880 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 881 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 882 Ops, 2); 883 break; 884 } 885 } 886 } 887 if (Result.Val->getNumValues() == 1) break; 888 889 assert(Result.Val->getNumValues() == 2 && 890 "Cannot return more than two values!"); 891 892 // Since we produced two values, make sure to remember that we 893 // legalized both of them. 894 Tmp1 = LegalizeOp(Result); 895 Tmp2 = LegalizeOp(Result.getValue(1)); 896 AddLegalizedOperand(Op.getValue(0), Tmp1); 897 AddLegalizedOperand(Op.getValue(1), Tmp2); 898 return Op.ResNo ? Tmp2 : Tmp1; 899 case ISD::EHSELECTION: { 900 Tmp1 = LegalizeOp(Node->getOperand(0)); 901 Tmp2 = LegalizeOp(Node->getOperand(1)); 902 MVT::ValueType VT = Node->getValueType(0); 903 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 904 default: assert(0 && "This action is not supported yet!"); 905 case TargetLowering::Expand: { 906 unsigned Reg = TLI.getExceptionSelectorRegister(); 907 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 908 } 909 break; 910 case TargetLowering::Custom: 911 Result = TLI.LowerOperation(Op, DAG); 912 if (Result.Val) break; 913 // Fall Thru 914 case TargetLowering::Legal: { 915 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 916 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 917 Ops, 2); 918 break; 919 } 920 } 921 } 922 if (Result.Val->getNumValues() == 1) break; 923 924 assert(Result.Val->getNumValues() == 2 && 925 "Cannot return more than two values!"); 926 927 // Since we produced two values, make sure to remember that we 928 // legalized both of them. 929 Tmp1 = LegalizeOp(Result); 930 Tmp2 = LegalizeOp(Result.getValue(1)); 931 AddLegalizedOperand(Op.getValue(0), Tmp1); 932 AddLegalizedOperand(Op.getValue(1), Tmp2); 933 return Op.ResNo ? Tmp2 : Tmp1; 934 case ISD::EH_RETURN: { 935 MVT::ValueType VT = Node->getValueType(0); 936 // The only "good" option for this node is to custom lower it. 937 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 938 default: assert(0 && "This action is not supported at all!"); 939 case TargetLowering::Custom: 940 Result = TLI.LowerOperation(Op, DAG); 941 if (Result.Val) break; 942 // Fall Thru 943 case TargetLowering::Legal: 944 // Target does not know, how to lower this, lower to noop 945 Result = LegalizeOp(Node->getOperand(0)); 946 break; 947 } 948 } 949 break; 950 case ISD::AssertSext: 951 case ISD::AssertZext: 952 Tmp1 = LegalizeOp(Node->getOperand(0)); 953 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 954 break; 955 case ISD::MERGE_VALUES: 956 // Legalize eliminates MERGE_VALUES nodes. 957 Result = Node->getOperand(Op.ResNo); 958 break; 959 case ISD::CopyFromReg: 960 Tmp1 = LegalizeOp(Node->getOperand(0)); 961 Result = Op.getValue(0); 962 if (Node->getNumValues() == 2) { 963 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 964 } else { 965 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 966 if (Node->getNumOperands() == 3) { 967 Tmp2 = LegalizeOp(Node->getOperand(2)); 968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 969 } else { 970 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 971 } 972 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 973 } 974 // Since CopyFromReg produces two values, make sure to remember that we 975 // legalized both of them. 976 AddLegalizedOperand(Op.getValue(0), Result); 977 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 978 return Result.getValue(Op.ResNo); 979 case ISD::UNDEF: { 980 MVT::ValueType VT = Op.getValueType(); 981 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 982 default: assert(0 && "This action is not supported yet!"); 983 case TargetLowering::Expand: 984 if (MVT::isInteger(VT)) 985 Result = DAG.getConstant(0, VT); 986 else if (MVT::isFloatingPoint(VT)) 987 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)), 988 VT); 989 else 990 assert(0 && "Unknown value type!"); 991 break; 992 case TargetLowering::Legal: 993 break; 994 } 995 break; 996 } 997 998 case ISD::INTRINSIC_W_CHAIN: 999 case ISD::INTRINSIC_WO_CHAIN: 1000 case ISD::INTRINSIC_VOID: { 1001 SmallVector<SDOperand, 8> Ops; 1002 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1003 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1004 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1005 1006 // Allow the target to custom lower its intrinsics if it wants to. 1007 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1008 TargetLowering::Custom) { 1009 Tmp3 = TLI.LowerOperation(Result, DAG); 1010 if (Tmp3.Val) Result = Tmp3; 1011 } 1012 1013 if (Result.Val->getNumValues() == 1) break; 1014 1015 // Must have return value and chain result. 1016 assert(Result.Val->getNumValues() == 2 && 1017 "Cannot return more than two values!"); 1018 1019 // Since loads produce two values, make sure to remember that we 1020 // legalized both of them. 1021 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1022 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1023 return Result.getValue(Op.ResNo); 1024 } 1025 1026 case ISD::LOCATION: 1027 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 1028 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1029 1030 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 1031 case TargetLowering::Promote: 1032 default: assert(0 && "This action is not supported yet!"); 1033 case TargetLowering::Expand: { 1034 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1035 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1036 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 1037 1038 if (MMI && (useDEBUG_LOC || useLABEL)) { 1039 const std::string &FName = 1040 cast<StringSDNode>(Node->getOperand(3))->getValue(); 1041 const std::string &DirName = 1042 cast<StringSDNode>(Node->getOperand(4))->getValue(); 1043 unsigned SrcFile = MMI->RecordSource(DirName, FName); 1044 1045 SmallVector<SDOperand, 8> Ops; 1046 Ops.push_back(Tmp1); // chain 1047 SDOperand LineOp = Node->getOperand(1); 1048 SDOperand ColOp = Node->getOperand(2); 1049 1050 if (useDEBUG_LOC) { 1051 Ops.push_back(LineOp); // line # 1052 Ops.push_back(ColOp); // col # 1053 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1054 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1055 } else { 1056 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 1057 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 1058 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile); 1059 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 1060 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size()); 1061 } 1062 } else { 1063 Result = Tmp1; // chain 1064 } 1065 break; 1066 } 1067 case TargetLowering::Legal: 1068 if (Tmp1 != Node->getOperand(0) || 1069 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1070 SmallVector<SDOperand, 8> Ops; 1071 Ops.push_back(Tmp1); 1072 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1073 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1074 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1075 } else { 1076 // Otherwise promote them. 1077 Ops.push_back(PromoteOp(Node->getOperand(1))); 1078 Ops.push_back(PromoteOp(Node->getOperand(2))); 1079 } 1080 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1081 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1082 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1083 } 1084 break; 1085 } 1086 break; 1087 1088 case ISD::DEBUG_LOC: 1089 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1090 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1091 default: assert(0 && "This action is not supported yet!"); 1092 case TargetLowering::Legal: 1093 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1094 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1095 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1096 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1097 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1098 break; 1099 } 1100 break; 1101 1102 case ISD::LABEL: 1103 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!"); 1104 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1105 default: assert(0 && "This action is not supported yet!"); 1106 case TargetLowering::Legal: 1107 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1108 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1109 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1110 break; 1111 case TargetLowering::Expand: 1112 Result = LegalizeOp(Node->getOperand(0)); 1113 break; 1114 } 1115 break; 1116 1117 case ISD::Constant: { 1118 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1119 unsigned opAction = 1120 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1121 1122 // We know we don't need to expand constants here, constants only have one 1123 // value and we check that it is fine above. 1124 1125 if (opAction == TargetLowering::Custom) { 1126 Tmp1 = TLI.LowerOperation(Result, DAG); 1127 if (Tmp1.Val) 1128 Result = Tmp1; 1129 } 1130 break; 1131 } 1132 case ISD::ConstantFP: { 1133 // Spill FP immediates to the constant pool if the target cannot directly 1134 // codegen them. Targets often have some immediate values that can be 1135 // efficiently generated into an FP register without a load. We explicitly 1136 // leave these constants as ConstantFP nodes for the target to deal with. 1137 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1138 1139 // Check to see if this FP immediate is already legal. 1140 bool isLegal = false; 1141 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1142 E = TLI.legal_fpimm_end(); I != E; ++I) 1143 if (CFP->isExactlyValue(*I)) { 1144 isLegal = true; 1145 break; 1146 } 1147 1148 // If this is a legal constant, turn it into a TargetConstantFP node. 1149 if (isLegal) { 1150 Result = DAG.getTargetConstantFP(CFP->getValueAPF(), 1151 CFP->getValueType(0)); 1152 break; 1153 } 1154 1155 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1156 default: assert(0 && "This action is not supported yet!"); 1157 case TargetLowering::Custom: 1158 Tmp3 = TLI.LowerOperation(Result, DAG); 1159 if (Tmp3.Val) { 1160 Result = Tmp3; 1161 break; 1162 } 1163 // FALLTHROUGH 1164 case TargetLowering::Expand: 1165 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1166 } 1167 break; 1168 } 1169 case ISD::TokenFactor: 1170 if (Node->getNumOperands() == 2) { 1171 Tmp1 = LegalizeOp(Node->getOperand(0)); 1172 Tmp2 = LegalizeOp(Node->getOperand(1)); 1173 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1174 } else if (Node->getNumOperands() == 3) { 1175 Tmp1 = LegalizeOp(Node->getOperand(0)); 1176 Tmp2 = LegalizeOp(Node->getOperand(1)); 1177 Tmp3 = LegalizeOp(Node->getOperand(2)); 1178 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1179 } else { 1180 SmallVector<SDOperand, 8> Ops; 1181 // Legalize the operands. 1182 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1183 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1184 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1185 } 1186 break; 1187 1188 case ISD::FORMAL_ARGUMENTS: 1189 case ISD::CALL: 1190 // The only option for this is to custom lower it. 1191 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1192 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1193 1194 // The number of incoming and outgoing values should match; unless the final 1195 // outgoing value is a flag. 1196 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1197 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1198 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1199 MVT::Flag)) && 1200 "Lowering call/formal_arguments produced unexpected # results!"); 1201 1202 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1203 // remember that we legalized all of them, so it doesn't get relegalized. 1204 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1205 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1206 continue; 1207 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1208 if (Op.ResNo == i) 1209 Tmp2 = Tmp1; 1210 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1211 } 1212 return Tmp2; 1213 case ISD::EXTRACT_SUBREG: { 1214 Tmp1 = LegalizeOp(Node->getOperand(0)); 1215 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1216 assert(idx && "Operand must be a constant"); 1217 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1218 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1219 } 1220 break; 1221 case ISD::INSERT_SUBREG: { 1222 Tmp1 = LegalizeOp(Node->getOperand(0)); 1223 Tmp2 = LegalizeOp(Node->getOperand(1)); 1224 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1225 assert(idx && "Operand must be a constant"); 1226 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1227 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1228 } 1229 break; 1230 case ISD::BUILD_VECTOR: 1231 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1232 default: assert(0 && "This action is not supported yet!"); 1233 case TargetLowering::Custom: 1234 Tmp3 = TLI.LowerOperation(Result, DAG); 1235 if (Tmp3.Val) { 1236 Result = Tmp3; 1237 break; 1238 } 1239 // FALLTHROUGH 1240 case TargetLowering::Expand: 1241 Result = ExpandBUILD_VECTOR(Result.Val); 1242 break; 1243 } 1244 break; 1245 case ISD::INSERT_VECTOR_ELT: 1246 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1247 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 1248 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1249 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1250 1251 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1252 Node->getValueType(0))) { 1253 default: assert(0 && "This action is not supported yet!"); 1254 case TargetLowering::Legal: 1255 break; 1256 case TargetLowering::Custom: 1257 Tmp4 = TLI.LowerOperation(Result, DAG); 1258 if (Tmp4.Val) { 1259 Result = Tmp4; 1260 break; 1261 } 1262 // FALLTHROUGH 1263 case TargetLowering::Expand: { 1264 // If the insert index is a constant, codegen this as a scalar_to_vector, 1265 // then a shuffle that inserts it into the right position in the vector. 1266 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1267 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1268 Tmp1.getValueType(), Tmp2); 1269 1270 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1271 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1272 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1273 1274 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 1275 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 1276 // the RHS. 1277 SmallVector<SDOperand, 8> ShufOps; 1278 for (unsigned i = 0; i != NumElts; ++i) { 1279 if (i != InsertPos->getValue()) 1280 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1281 else 1282 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1283 } 1284 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1285 &ShufOps[0], ShufOps.size()); 1286 1287 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1288 Tmp1, ScVec, ShufMask); 1289 Result = LegalizeOp(Result); 1290 break; 1291 } 1292 1293 // If the target doesn't support this, we have to spill the input vector 1294 // to a temporary stack slot, update the element, then reload it. This is 1295 // badness. We could also load the value into a vector register (either 1296 // with a "move to register" or "extload into register" instruction, then 1297 // permute it into place, if the idx is a constant and if the idx is 1298 // supported by the target. 1299 MVT::ValueType VT = Tmp1.getValueType(); 1300 MVT::ValueType EltVT = Tmp2.getValueType(); 1301 MVT::ValueType IdxVT = Tmp3.getValueType(); 1302 MVT::ValueType PtrVT = TLI.getPointerTy(); 1303 SDOperand StackPtr = DAG.CreateStackTemporary(VT); 1304 // Store the vector. 1305 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); 1306 1307 // Truncate or zero extend offset to target pointer type. 1308 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1309 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1310 // Add the offset to the index. 1311 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1312 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1313 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1314 // Store the scalar value. 1315 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); 1316 // Load the updated vector. 1317 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 1318 break; 1319 } 1320 } 1321 break; 1322 case ISD::SCALAR_TO_VECTOR: 1323 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1324 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1325 break; 1326 } 1327 1328 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1329 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1330 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1331 Node->getValueType(0))) { 1332 default: assert(0 && "This action is not supported yet!"); 1333 case TargetLowering::Legal: 1334 break; 1335 case TargetLowering::Custom: 1336 Tmp3 = TLI.LowerOperation(Result, DAG); 1337 if (Tmp3.Val) { 1338 Result = Tmp3; 1339 break; 1340 } 1341 // FALLTHROUGH 1342 case TargetLowering::Expand: 1343 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1344 break; 1345 } 1346 break; 1347 case ISD::VECTOR_SHUFFLE: 1348 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1349 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1350 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1351 1352 // Allow targets to custom lower the SHUFFLEs they support. 1353 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1354 default: assert(0 && "Unknown operation action!"); 1355 case TargetLowering::Legal: 1356 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1357 "vector shuffle should not be created if not legal!"); 1358 break; 1359 case TargetLowering::Custom: 1360 Tmp3 = TLI.LowerOperation(Result, DAG); 1361 if (Tmp3.Val) { 1362 Result = Tmp3; 1363 break; 1364 } 1365 // FALLTHROUGH 1366 case TargetLowering::Expand: { 1367 MVT::ValueType VT = Node->getValueType(0); 1368 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1369 MVT::ValueType PtrVT = TLI.getPointerTy(); 1370 SDOperand Mask = Node->getOperand(2); 1371 unsigned NumElems = Mask.getNumOperands(); 1372 SmallVector<SDOperand,8> Ops; 1373 for (unsigned i = 0; i != NumElems; ++i) { 1374 SDOperand Arg = Mask.getOperand(i); 1375 if (Arg.getOpcode() == ISD::UNDEF) { 1376 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1377 } else { 1378 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1379 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1380 if (Idx < NumElems) 1381 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1382 DAG.getConstant(Idx, PtrVT))); 1383 else 1384 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1385 DAG.getConstant(Idx - NumElems, PtrVT))); 1386 } 1387 } 1388 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1389 break; 1390 } 1391 case TargetLowering::Promote: { 1392 // Change base type to a different vector type. 1393 MVT::ValueType OVT = Node->getValueType(0); 1394 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1395 1396 // Cast the two input vectors. 1397 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1398 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1399 1400 // Convert the shuffle mask to the right # elements. 1401 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1402 assert(Tmp3.Val && "Shuffle not legal?"); 1403 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1404 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1405 break; 1406 } 1407 } 1408 break; 1409 1410 case ISD::EXTRACT_VECTOR_ELT: 1411 Tmp1 = Node->getOperand(0); 1412 Tmp2 = LegalizeOp(Node->getOperand(1)); 1413 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1414 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1415 break; 1416 1417 case ISD::EXTRACT_SUBVECTOR: 1418 Tmp1 = Node->getOperand(0); 1419 Tmp2 = LegalizeOp(Node->getOperand(1)); 1420 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1421 Result = ExpandEXTRACT_SUBVECTOR(Result); 1422 break; 1423 1424 case ISD::CALLSEQ_START: { 1425 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1426 1427 // Recursively Legalize all of the inputs of the call end that do not lead 1428 // to this call start. This ensures that any libcalls that need be inserted 1429 // are inserted *before* the CALLSEQ_START. 1430 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1431 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1432 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1433 NodesLeadingTo); 1434 } 1435 1436 // Now that we legalized all of the inputs (which may have inserted 1437 // libcalls) create the new CALLSEQ_START node. 1438 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1439 1440 // Merge in the last call, to ensure that this call start after the last 1441 // call ended. 1442 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1443 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1444 Tmp1 = LegalizeOp(Tmp1); 1445 } 1446 1447 // Do not try to legalize the target-specific arguments (#1+). 1448 if (Tmp1 != Node->getOperand(0)) { 1449 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1450 Ops[0] = Tmp1; 1451 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1452 } 1453 1454 // Remember that the CALLSEQ_START is legalized. 1455 AddLegalizedOperand(Op.getValue(0), Result); 1456 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1457 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1458 1459 // Now that the callseq_start and all of the non-call nodes above this call 1460 // sequence have been legalized, legalize the call itself. During this 1461 // process, no libcalls can/will be inserted, guaranteeing that no calls 1462 // can overlap. 1463 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1464 SDOperand InCallSEQ = LastCALLSEQ_END; 1465 // Note that we are selecting this call! 1466 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1467 IsLegalizingCall = true; 1468 1469 // Legalize the call, starting from the CALLSEQ_END. 1470 LegalizeOp(LastCALLSEQ_END); 1471 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1472 return Result; 1473 } 1474 case ISD::CALLSEQ_END: 1475 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1476 // will cause this node to be legalized as well as handling libcalls right. 1477 if (LastCALLSEQ_END.Val != Node) { 1478 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1479 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1480 assert(I != LegalizedNodes.end() && 1481 "Legalizing the call start should have legalized this node!"); 1482 return I->second; 1483 } 1484 1485 // Otherwise, the call start has been legalized and everything is going 1486 // according to plan. Just legalize ourselves normally here. 1487 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1488 // Do not try to legalize the target-specific arguments (#1+), except for 1489 // an optional flag input. 1490 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1491 if (Tmp1 != Node->getOperand(0)) { 1492 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1493 Ops[0] = Tmp1; 1494 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1495 } 1496 } else { 1497 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1498 if (Tmp1 != Node->getOperand(0) || 1499 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1500 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1501 Ops[0] = Tmp1; 1502 Ops.back() = Tmp2; 1503 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1504 } 1505 } 1506 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1507 // This finishes up call legalization. 1508 IsLegalizingCall = false; 1509 1510 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1511 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1512 if (Node->getNumValues() == 2) 1513 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1514 return Result.getValue(Op.ResNo); 1515 case ISD::DYNAMIC_STACKALLOC: { 1516 MVT::ValueType VT = Node->getValueType(0); 1517 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1518 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1519 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1520 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1521 1522 Tmp1 = Result.getValue(0); 1523 Tmp2 = Result.getValue(1); 1524 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1525 default: assert(0 && "This action is not supported yet!"); 1526 case TargetLowering::Expand: { 1527 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1528 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1529 " not tell us which reg is the stack pointer!"); 1530 SDOperand Chain = Tmp1.getOperand(0); 1531 1532 // Chain the dynamic stack allocation so that it doesn't modify the stack 1533 // pointer when other instructions are using the stack. 1534 Chain = DAG.getCALLSEQ_START(Chain, 1535 DAG.getConstant(0, TLI.getPointerTy())); 1536 1537 SDOperand Size = Tmp2.getOperand(1); 1538 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1539 Chain = SP.getValue(1); 1540 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1541 unsigned StackAlign = 1542 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1543 if (Align > StackAlign) 1544 SP = DAG.getNode(ISD::AND, VT, SP, 1545 DAG.getConstant(-(uint64_t)Align, VT)); 1546 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1547 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1548 1549 Tmp2 = 1550 DAG.getCALLSEQ_END(Chain, 1551 DAG.getConstant(0, TLI.getPointerTy()), 1552 DAG.getConstant(0, TLI.getPointerTy()), 1553 SDOperand()); 1554 1555 Tmp1 = LegalizeOp(Tmp1); 1556 Tmp2 = LegalizeOp(Tmp2); 1557 break; 1558 } 1559 case TargetLowering::Custom: 1560 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1561 if (Tmp3.Val) { 1562 Tmp1 = LegalizeOp(Tmp3); 1563 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1564 } 1565 break; 1566 case TargetLowering::Legal: 1567 break; 1568 } 1569 // Since this op produce two values, make sure to remember that we 1570 // legalized both of them. 1571 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1572 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1573 return Op.ResNo ? Tmp2 : Tmp1; 1574 } 1575 case ISD::INLINEASM: { 1576 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1577 bool Changed = false; 1578 // Legalize all of the operands of the inline asm, in case they are nodes 1579 // that need to be expanded or something. Note we skip the asm string and 1580 // all of the TargetConstant flags. 1581 SDOperand Op = LegalizeOp(Ops[0]); 1582 Changed = Op != Ops[0]; 1583 Ops[0] = Op; 1584 1585 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1586 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1587 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1588 for (++i; NumVals; ++i, --NumVals) { 1589 SDOperand Op = LegalizeOp(Ops[i]); 1590 if (Op != Ops[i]) { 1591 Changed = true; 1592 Ops[i] = Op; 1593 } 1594 } 1595 } 1596 1597 if (HasInFlag) { 1598 Op = LegalizeOp(Ops.back()); 1599 Changed |= Op != Ops.back(); 1600 Ops.back() = Op; 1601 } 1602 1603 if (Changed) 1604 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1605 1606 // INLINE asm returns a chain and flag, make sure to add both to the map. 1607 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1608 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1609 return Result.getValue(Op.ResNo); 1610 } 1611 case ISD::BR: 1612 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1613 // Ensure that libcalls are emitted before a branch. 1614 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1615 Tmp1 = LegalizeOp(Tmp1); 1616 LastCALLSEQ_END = DAG.getEntryNode(); 1617 1618 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1619 break; 1620 case ISD::BRIND: 1621 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1622 // Ensure that libcalls are emitted before a branch. 1623 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1624 Tmp1 = LegalizeOp(Tmp1); 1625 LastCALLSEQ_END = DAG.getEntryNode(); 1626 1627 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1628 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1629 case Legal: 1630 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1631 break; 1632 } 1633 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1634 break; 1635 case ISD::BR_JT: 1636 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1637 // Ensure that libcalls are emitted before a branch. 1638 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1639 Tmp1 = LegalizeOp(Tmp1); 1640 LastCALLSEQ_END = DAG.getEntryNode(); 1641 1642 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1643 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1644 1645 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1646 default: assert(0 && "This action is not supported yet!"); 1647 case TargetLowering::Legal: break; 1648 case TargetLowering::Custom: 1649 Tmp1 = TLI.LowerOperation(Result, DAG); 1650 if (Tmp1.Val) Result = Tmp1; 1651 break; 1652 case TargetLowering::Expand: { 1653 SDOperand Chain = Result.getOperand(0); 1654 SDOperand Table = Result.getOperand(1); 1655 SDOperand Index = Result.getOperand(2); 1656 1657 MVT::ValueType PTy = TLI.getPointerTy(); 1658 MachineFunction &MF = DAG.getMachineFunction(); 1659 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1660 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1661 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1662 1663 SDOperand LD; 1664 switch (EntrySize) { 1665 default: assert(0 && "Size of jump table not supported yet."); break; 1666 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; 1667 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; 1668 } 1669 1670 Addr = LD; 1671 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1672 // For PIC, the sequence is: 1673 // BRIND(load(Jumptable + index) + RelocBase) 1674 // RelocBase can be JumpTable, GOT or some sort of global base. 1675 if (PTy != MVT::i32) 1676 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1677 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1678 TLI.getPICJumpTableRelocBase(Table, DAG)); 1679 } 1680 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1681 } 1682 } 1683 break; 1684 case ISD::BRCOND: 1685 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1686 // Ensure that libcalls are emitted before a return. 1687 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1688 Tmp1 = LegalizeOp(Tmp1); 1689 LastCALLSEQ_END = DAG.getEntryNode(); 1690 1691 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1692 case Expand: assert(0 && "It's impossible to expand bools"); 1693 case Legal: 1694 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1695 break; 1696 case Promote: 1697 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1698 1699 // The top bits of the promoted condition are not necessarily zero, ensure 1700 // that the value is properly zero extended. 1701 if (!DAG.MaskedValueIsZero(Tmp2, 1702 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1703 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1704 break; 1705 } 1706 1707 // Basic block destination (Op#2) is always legal. 1708 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1709 1710 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1711 default: assert(0 && "This action is not supported yet!"); 1712 case TargetLowering::Legal: break; 1713 case TargetLowering::Custom: 1714 Tmp1 = TLI.LowerOperation(Result, DAG); 1715 if (Tmp1.Val) Result = Tmp1; 1716 break; 1717 case TargetLowering::Expand: 1718 // Expand brcond's setcc into its constituent parts and create a BR_CC 1719 // Node. 1720 if (Tmp2.getOpcode() == ISD::SETCC) { 1721 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1722 Tmp2.getOperand(0), Tmp2.getOperand(1), 1723 Node->getOperand(2)); 1724 } else { 1725 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1726 DAG.getCondCode(ISD::SETNE), Tmp2, 1727 DAG.getConstant(0, Tmp2.getValueType()), 1728 Node->getOperand(2)); 1729 } 1730 break; 1731 } 1732 break; 1733 case ISD::BR_CC: 1734 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1735 // Ensure that libcalls are emitted before a branch. 1736 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1737 Tmp1 = LegalizeOp(Tmp1); 1738 Tmp2 = Node->getOperand(2); // LHS 1739 Tmp3 = Node->getOperand(3); // RHS 1740 Tmp4 = Node->getOperand(1); // CC 1741 1742 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1743 LastCALLSEQ_END = DAG.getEntryNode(); 1744 1745 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1746 // the LHS is a legal SETCC itself. In this case, we need to compare 1747 // the result against zero to select between true and false values. 1748 if (Tmp3.Val == 0) { 1749 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1750 Tmp4 = DAG.getCondCode(ISD::SETNE); 1751 } 1752 1753 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1754 Node->getOperand(4)); 1755 1756 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1757 default: assert(0 && "Unexpected action for BR_CC!"); 1758 case TargetLowering::Legal: break; 1759 case TargetLowering::Custom: 1760 Tmp4 = TLI.LowerOperation(Result, DAG); 1761 if (Tmp4.Val) Result = Tmp4; 1762 break; 1763 } 1764 break; 1765 case ISD::LOAD: { 1766 LoadSDNode *LD = cast<LoadSDNode>(Node); 1767 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1768 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1769 1770 ISD::LoadExtType ExtType = LD->getExtensionType(); 1771 if (ExtType == ISD::NON_EXTLOAD) { 1772 MVT::ValueType VT = Node->getValueType(0); 1773 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1774 Tmp3 = Result.getValue(0); 1775 Tmp4 = Result.getValue(1); 1776 1777 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1778 default: assert(0 && "This action is not supported yet!"); 1779 case TargetLowering::Legal: 1780 // If this is an unaligned load and the target doesn't support it, 1781 // expand it. 1782 if (!TLI.allowsUnalignedMemoryAccesses()) { 1783 unsigned ABIAlignment = TLI.getTargetData()-> 1784 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1785 if (LD->getAlignment() < ABIAlignment){ 1786 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1787 TLI); 1788 Tmp3 = Result.getOperand(0); 1789 Tmp4 = Result.getOperand(1); 1790 Tmp3 = LegalizeOp(Tmp3); 1791 Tmp4 = LegalizeOp(Tmp4); 1792 } 1793 } 1794 break; 1795 case TargetLowering::Custom: 1796 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1797 if (Tmp1.Val) { 1798 Tmp3 = LegalizeOp(Tmp1); 1799 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1800 } 1801 break; 1802 case TargetLowering::Promote: { 1803 // Only promote a load of vector type to another. 1804 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1805 // Change base type to a different vector type. 1806 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1807 1808 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1809 LD->getSrcValueOffset(), 1810 LD->isVolatile(), LD->getAlignment()); 1811 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1812 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1813 break; 1814 } 1815 } 1816 // Since loads produce two values, make sure to remember that we 1817 // legalized both of them. 1818 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1819 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1820 return Op.ResNo ? Tmp4 : Tmp3; 1821 } else { 1822 MVT::ValueType SrcVT = LD->getLoadedVT(); 1823 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1824 default: assert(0 && "This action is not supported yet!"); 1825 case TargetLowering::Promote: 1826 assert(SrcVT == MVT::i1 && 1827 "Can only promote extending LOAD from i1 -> i8!"); 1828 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1829 LD->getSrcValue(), LD->getSrcValueOffset(), 1830 MVT::i8, LD->isVolatile(), LD->getAlignment()); 1831 Tmp1 = Result.getValue(0); 1832 Tmp2 = Result.getValue(1); 1833 break; 1834 case TargetLowering::Custom: 1835 isCustom = true; 1836 // FALLTHROUGH 1837 case TargetLowering::Legal: 1838 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1839 Tmp1 = Result.getValue(0); 1840 Tmp2 = Result.getValue(1); 1841 1842 if (isCustom) { 1843 Tmp3 = TLI.LowerOperation(Result, DAG); 1844 if (Tmp3.Val) { 1845 Tmp1 = LegalizeOp(Tmp3); 1846 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1847 } 1848 } else { 1849 // If this is an unaligned load and the target doesn't support it, 1850 // expand it. 1851 if (!TLI.allowsUnalignedMemoryAccesses()) { 1852 unsigned ABIAlignment = TLI.getTargetData()-> 1853 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1854 if (LD->getAlignment() < ABIAlignment){ 1855 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1856 TLI); 1857 Tmp1 = Result.getOperand(0); 1858 Tmp2 = Result.getOperand(1); 1859 Tmp1 = LegalizeOp(Tmp1); 1860 Tmp2 = LegalizeOp(Tmp2); 1861 } 1862 } 1863 } 1864 break; 1865 case TargetLowering::Expand: 1866 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1867 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1868 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1869 LD->getSrcValueOffset(), 1870 LD->isVolatile(), LD->getAlignment()); 1871 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1872 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1873 Tmp2 = LegalizeOp(Load.getValue(1)); 1874 break; 1875 } 1876 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1877 // Turn the unsupported load into an EXTLOAD followed by an explicit 1878 // zero/sign extend inreg. 1879 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1880 Tmp1, Tmp2, LD->getSrcValue(), 1881 LD->getSrcValueOffset(), SrcVT, 1882 LD->isVolatile(), LD->getAlignment()); 1883 SDOperand ValRes; 1884 if (ExtType == ISD::SEXTLOAD) 1885 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1886 Result, DAG.getValueType(SrcVT)); 1887 else 1888 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1889 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1890 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1891 break; 1892 } 1893 // Since loads produce two values, make sure to remember that we legalized 1894 // both of them. 1895 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1896 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1897 return Op.ResNo ? Tmp2 : Tmp1; 1898 } 1899 } 1900 case ISD::EXTRACT_ELEMENT: { 1901 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1902 switch (getTypeAction(OpTy)) { 1903 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1904 case Legal: 1905 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1906 // 1 -> Hi 1907 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1908 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1909 TLI.getShiftAmountTy())); 1910 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1911 } else { 1912 // 0 -> Lo 1913 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1914 Node->getOperand(0)); 1915 } 1916 break; 1917 case Expand: 1918 // Get both the low and high parts. 1919 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1920 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1921 Result = Tmp2; // 1 -> Hi 1922 else 1923 Result = Tmp1; // 0 -> Lo 1924 break; 1925 } 1926 break; 1927 } 1928 1929 case ISD::CopyToReg: 1930 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1931 1932 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1933 "Register type must be legal!"); 1934 // Legalize the incoming value (must be a legal type). 1935 Tmp2 = LegalizeOp(Node->getOperand(2)); 1936 if (Node->getNumValues() == 1) { 1937 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1938 } else { 1939 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1940 if (Node->getNumOperands() == 4) { 1941 Tmp3 = LegalizeOp(Node->getOperand(3)); 1942 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1943 Tmp3); 1944 } else { 1945 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1946 } 1947 1948 // Since this produces two values, make sure to remember that we legalized 1949 // both of them. 1950 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1951 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1952 return Result; 1953 } 1954 break; 1955 1956 case ISD::RET: 1957 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1958 1959 // Ensure that libcalls are emitted before a return. 1960 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1961 Tmp1 = LegalizeOp(Tmp1); 1962 LastCALLSEQ_END = DAG.getEntryNode(); 1963 1964 switch (Node->getNumOperands()) { 1965 case 3: // ret val 1966 Tmp2 = Node->getOperand(1); 1967 Tmp3 = Node->getOperand(2); // Signness 1968 switch (getTypeAction(Tmp2.getValueType())) { 1969 case Legal: 1970 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1971 break; 1972 case Expand: 1973 if (!MVT::isVector(Tmp2.getValueType())) { 1974 SDOperand Lo, Hi; 1975 ExpandOp(Tmp2, Lo, Hi); 1976 1977 // Big endian systems want the hi reg first. 1978 if (!TLI.isLittleEndian()) 1979 std::swap(Lo, Hi); 1980 1981 if (Hi.Val) 1982 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1983 else 1984 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 1985 Result = LegalizeOp(Result); 1986 } else { 1987 SDNode *InVal = Tmp2.Val; 1988 int InIx = Tmp2.ResNo; 1989 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 1990 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 1991 1992 // Figure out if there is a simple type corresponding to this Vector 1993 // type. If so, convert to the vector type. 1994 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1995 if (TLI.isTypeLegal(TVT)) { 1996 // Turn this into a return of the vector type. 1997 Tmp2 = LegalizeOp(Tmp2); 1998 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1999 } else if (NumElems == 1) { 2000 // Turn this into a return of the scalar type. 2001 Tmp2 = ScalarizeVectorOp(Tmp2); 2002 Tmp2 = LegalizeOp(Tmp2); 2003 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2004 2005 // FIXME: Returns of gcc generic vectors smaller than a legal type 2006 // should be returned in integer registers! 2007 2008 // The scalarized value type may not be legal, e.g. it might require 2009 // promotion or expansion. Relegalize the return. 2010 Result = LegalizeOp(Result); 2011 } else { 2012 // FIXME: Returns of gcc generic vectors larger than a legal vector 2013 // type should be returned by reference! 2014 SDOperand Lo, Hi; 2015 SplitVectorOp(Tmp2, Lo, Hi); 2016 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2017 Result = LegalizeOp(Result); 2018 } 2019 } 2020 break; 2021 case Promote: 2022 Tmp2 = PromoteOp(Node->getOperand(1)); 2023 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2024 Result = LegalizeOp(Result); 2025 break; 2026 } 2027 break; 2028 case 1: // ret void 2029 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2030 break; 2031 default: { // ret <values> 2032 SmallVector<SDOperand, 8> NewValues; 2033 NewValues.push_back(Tmp1); 2034 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2035 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2036 case Legal: 2037 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2038 NewValues.push_back(Node->getOperand(i+1)); 2039 break; 2040 case Expand: { 2041 SDOperand Lo, Hi; 2042 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && 2043 "FIXME: TODO: implement returning non-legal vector types!"); 2044 ExpandOp(Node->getOperand(i), Lo, Hi); 2045 NewValues.push_back(Lo); 2046 NewValues.push_back(Node->getOperand(i+1)); 2047 if (Hi.Val) { 2048 NewValues.push_back(Hi); 2049 NewValues.push_back(Node->getOperand(i+1)); 2050 } 2051 break; 2052 } 2053 case Promote: 2054 assert(0 && "Can't promote multiple return value yet!"); 2055 } 2056 2057 if (NewValues.size() == Node->getNumOperands()) 2058 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2059 else 2060 Result = DAG.getNode(ISD::RET, MVT::Other, 2061 &NewValues[0], NewValues.size()); 2062 break; 2063 } 2064 } 2065 2066 if (Result.getOpcode() == ISD::RET) { 2067 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2068 default: assert(0 && "This action is not supported yet!"); 2069 case TargetLowering::Legal: break; 2070 case TargetLowering::Custom: 2071 Tmp1 = TLI.LowerOperation(Result, DAG); 2072 if (Tmp1.Val) Result = Tmp1; 2073 break; 2074 } 2075 } 2076 break; 2077 case ISD::STORE: { 2078 StoreSDNode *ST = cast<StoreSDNode>(Node); 2079 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2080 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2081 int SVOffset = ST->getSrcValueOffset(); 2082 unsigned Alignment = ST->getAlignment(); 2083 bool isVolatile = ST->isVolatile(); 2084 2085 if (!ST->isTruncatingStore()) { 2086 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2087 // FIXME: We shouldn't do this for TargetConstantFP's. 2088 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2089 // to phase ordering between legalized code and the dag combiner. This 2090 // probably means that we need to integrate dag combiner and legalizer 2091 // together. 2092 // We generally can't do this one for long doubles. 2093 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2094 if (CFP->getValueType(0) == MVT::f32 && 2095 getTypeAction(MVT::i32) == Legal) { 2096 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF(). 2097 convertToAPInt().getZExtValue(), 2098 MVT::i32); 2099 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2100 SVOffset, isVolatile, Alignment); 2101 break; 2102 } else if (CFP->getValueType(0) == MVT::f64) { 2103 // If this target supports 64-bit registers, do a single 64-bit store. 2104 if (getTypeAction(MVT::i64) == Legal) { 2105 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2106 getZExtValue(), MVT::i64); 2107 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2108 SVOffset, isVolatile, Alignment); 2109 break; 2110 } else if (getTypeAction(MVT::i32) == Legal) { 2111 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2112 // stores. If the target supports neither 32- nor 64-bits, this 2113 // xform is certainly not worth it. 2114 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue(); 2115 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32); 2116 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32); 2117 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 2118 2119 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2120 SVOffset, isVolatile, Alignment); 2121 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2122 DAG.getIntPtrConstant(4)); 2123 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2124 isVolatile, MinAlign(Alignment, 4U)); 2125 2126 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2127 break; 2128 } 2129 } 2130 } 2131 2132 switch (getTypeAction(ST->getStoredVT())) { 2133 case Legal: { 2134 Tmp3 = LegalizeOp(ST->getValue()); 2135 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2136 ST->getOffset()); 2137 2138 MVT::ValueType VT = Tmp3.getValueType(); 2139 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2140 default: assert(0 && "This action is not supported yet!"); 2141 case TargetLowering::Legal: 2142 // If this is an unaligned store and the target doesn't support it, 2143 // expand it. 2144 if (!TLI.allowsUnalignedMemoryAccesses()) { 2145 unsigned ABIAlignment = TLI.getTargetData()-> 2146 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2147 if (ST->getAlignment() < ABIAlignment) 2148 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2149 TLI); 2150 } 2151 break; 2152 case TargetLowering::Custom: 2153 Tmp1 = TLI.LowerOperation(Result, DAG); 2154 if (Tmp1.Val) Result = Tmp1; 2155 break; 2156 case TargetLowering::Promote: 2157 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 2158 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2159 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2160 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2161 ST->getSrcValue(), SVOffset, isVolatile, 2162 Alignment); 2163 break; 2164 } 2165 break; 2166 } 2167 case Promote: 2168 // Truncate the value and store the result. 2169 Tmp3 = PromoteOp(ST->getValue()); 2170 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2171 SVOffset, ST->getStoredVT(), 2172 isVolatile, Alignment); 2173 break; 2174 2175 case Expand: 2176 unsigned IncrementSize = 0; 2177 SDOperand Lo, Hi; 2178 2179 // If this is a vector type, then we have to calculate the increment as 2180 // the product of the element size in bytes, and the number of elements 2181 // in the high half of the vector. 2182 if (MVT::isVector(ST->getValue().getValueType())) { 2183 SDNode *InVal = ST->getValue().Val; 2184 int InIx = ST->getValue().ResNo; 2185 MVT::ValueType InVT = InVal->getValueType(InIx); 2186 unsigned NumElems = MVT::getVectorNumElements(InVT); 2187 MVT::ValueType EVT = MVT::getVectorElementType(InVT); 2188 2189 // Figure out if there is a simple type corresponding to this Vector 2190 // type. If so, convert to the vector type. 2191 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2192 if (TLI.isTypeLegal(TVT)) { 2193 // Turn this into a normal store of the vector type. 2194 Tmp3 = LegalizeOp(Node->getOperand(1)); 2195 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2196 SVOffset, isVolatile, Alignment); 2197 Result = LegalizeOp(Result); 2198 break; 2199 } else if (NumElems == 1) { 2200 // Turn this into a normal store of the scalar type. 2201 Tmp3 = ScalarizeVectorOp(Node->getOperand(1)); 2202 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2203 SVOffset, isVolatile, Alignment); 2204 // The scalarized value type may not be legal, e.g. it might require 2205 // promotion or expansion. Relegalize the scalar store. 2206 Result = LegalizeOp(Result); 2207 break; 2208 } else { 2209 SplitVectorOp(Node->getOperand(1), Lo, Hi); 2210 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) * 2211 MVT::getSizeInBits(EVT)/8; 2212 } 2213 } else { 2214 ExpandOp(Node->getOperand(1), Lo, Hi); 2215 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 2216 2217 if (!TLI.isLittleEndian()) 2218 std::swap(Lo, Hi); 2219 } 2220 2221 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2222 SVOffset, isVolatile, Alignment); 2223 2224 if (Hi.Val == NULL) { 2225 // Must be int <-> float one-to-one expansion. 2226 Result = Lo; 2227 break; 2228 } 2229 2230 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2231 DAG.getIntPtrConstant(IncrementSize)); 2232 assert(isTypeLegal(Tmp2.getValueType()) && 2233 "Pointers must be legal!"); 2234 SVOffset += IncrementSize; 2235 Alignment = MinAlign(Alignment, IncrementSize); 2236 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2237 SVOffset, isVolatile, Alignment); 2238 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2239 break; 2240 } 2241 } else { 2242 switch (getTypeAction(ST->getValue().getValueType())) { 2243 case Legal: 2244 Tmp3 = LegalizeOp(ST->getValue()); 2245 break; 2246 case Promote: 2247 // We can promote the value, the truncstore will still take care of it. 2248 Tmp3 = PromoteOp(ST->getValue()); 2249 break; 2250 case Expand: 2251 // Just store the low part. This may become a non-trunc store, so make 2252 // sure to use getTruncStore, not UpdateNodeOperands below. 2253 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2254 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2255 SVOffset, MVT::i8, isVolatile, Alignment); 2256 } 2257 2258 // Unconditionally promote TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2259 if (ST->getStoredVT() == MVT::i1) { 2260 // Promote the bool to a mask then store. 2261 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3, 2262 DAG.getConstant(1, Tmp3.getValueType())); 2263 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2264 SVOffset, MVT::i8, 2265 isVolatile, Alignment); 2266 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2267 Tmp2 != ST->getBasePtr()) { 2268 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2269 ST->getOffset()); 2270 } 2271 2272 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT(); 2273 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2274 default: assert(0 && "This action is not supported yet!"); 2275 case TargetLowering::Legal: 2276 // If this is an unaligned store and the target doesn't support it, 2277 // expand it. 2278 if (!TLI.allowsUnalignedMemoryAccesses()) { 2279 unsigned ABIAlignment = TLI.getTargetData()-> 2280 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2281 if (ST->getAlignment() < ABIAlignment) 2282 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2283 TLI); 2284 } 2285 break; 2286 case TargetLowering::Custom: 2287 Result = TLI.LowerOperation(Result, DAG); 2288 break; 2289 } 2290 } 2291 break; 2292 } 2293 case ISD::PCMARKER: 2294 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2295 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2296 break; 2297 case ISD::STACKSAVE: 2298 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2299 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2300 Tmp1 = Result.getValue(0); 2301 Tmp2 = Result.getValue(1); 2302 2303 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2304 default: assert(0 && "This action is not supported yet!"); 2305 case TargetLowering::Legal: break; 2306 case TargetLowering::Custom: 2307 Tmp3 = TLI.LowerOperation(Result, DAG); 2308 if (Tmp3.Val) { 2309 Tmp1 = LegalizeOp(Tmp3); 2310 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2311 } 2312 break; 2313 case TargetLowering::Expand: 2314 // Expand to CopyFromReg if the target set 2315 // StackPointerRegisterToSaveRestore. 2316 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2317 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2318 Node->getValueType(0)); 2319 Tmp2 = Tmp1.getValue(1); 2320 } else { 2321 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2322 Tmp2 = Node->getOperand(0); 2323 } 2324 break; 2325 } 2326 2327 // Since stacksave produce two values, make sure to remember that we 2328 // legalized both of them. 2329 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2330 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2331 return Op.ResNo ? Tmp2 : Tmp1; 2332 2333 case ISD::STACKRESTORE: 2334 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2335 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2336 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2337 2338 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2339 default: assert(0 && "This action is not supported yet!"); 2340 case TargetLowering::Legal: break; 2341 case TargetLowering::Custom: 2342 Tmp1 = TLI.LowerOperation(Result, DAG); 2343 if (Tmp1.Val) Result = Tmp1; 2344 break; 2345 case TargetLowering::Expand: 2346 // Expand to CopyToReg if the target set 2347 // StackPointerRegisterToSaveRestore. 2348 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2349 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2350 } else { 2351 Result = Tmp1; 2352 } 2353 break; 2354 } 2355 break; 2356 2357 case ISD::READCYCLECOUNTER: 2358 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2359 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2360 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2361 Node->getValueType(0))) { 2362 default: assert(0 && "This action is not supported yet!"); 2363 case TargetLowering::Legal: 2364 Tmp1 = Result.getValue(0); 2365 Tmp2 = Result.getValue(1); 2366 break; 2367 case TargetLowering::Custom: 2368 Result = TLI.LowerOperation(Result, DAG); 2369 Tmp1 = LegalizeOp(Result.getValue(0)); 2370 Tmp2 = LegalizeOp(Result.getValue(1)); 2371 break; 2372 } 2373 2374 // Since rdcc produce two values, make sure to remember that we legalized 2375 // both of them. 2376 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2377 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2378 return Result; 2379 2380 case ISD::SELECT: 2381 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2382 case Expand: assert(0 && "It's impossible to expand bools"); 2383 case Legal: 2384 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2385 break; 2386 case Promote: 2387 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2388 // Make sure the condition is either zero or one. 2389 if (!DAG.MaskedValueIsZero(Tmp1, 2390 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 2391 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2392 break; 2393 } 2394 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2395 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2396 2397 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2398 2399 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2400 default: assert(0 && "This action is not supported yet!"); 2401 case TargetLowering::Legal: break; 2402 case TargetLowering::Custom: { 2403 Tmp1 = TLI.LowerOperation(Result, DAG); 2404 if (Tmp1.Val) Result = Tmp1; 2405 break; 2406 } 2407 case TargetLowering::Expand: 2408 if (Tmp1.getOpcode() == ISD::SETCC) { 2409 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2410 Tmp2, Tmp3, 2411 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2412 } else { 2413 Result = DAG.getSelectCC(Tmp1, 2414 DAG.getConstant(0, Tmp1.getValueType()), 2415 Tmp2, Tmp3, ISD::SETNE); 2416 } 2417 break; 2418 case TargetLowering::Promote: { 2419 MVT::ValueType NVT = 2420 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2421 unsigned ExtOp, TruncOp; 2422 if (MVT::isVector(Tmp2.getValueType())) { 2423 ExtOp = ISD::BIT_CONVERT; 2424 TruncOp = ISD::BIT_CONVERT; 2425 } else if (MVT::isInteger(Tmp2.getValueType())) { 2426 ExtOp = ISD::ANY_EXTEND; 2427 TruncOp = ISD::TRUNCATE; 2428 } else { 2429 ExtOp = ISD::FP_EXTEND; 2430 TruncOp = ISD::FP_ROUND; 2431 } 2432 // Promote each of the values to the new type. 2433 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2434 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2435 // Perform the larger operation, then round down. 2436 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2437 if (TruncOp != ISD::FP_ROUND) 2438 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2439 else 2440 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2441 DAG.getIntPtrConstant(0)); 2442 break; 2443 } 2444 } 2445 break; 2446 case ISD::SELECT_CC: { 2447 Tmp1 = Node->getOperand(0); // LHS 2448 Tmp2 = Node->getOperand(1); // RHS 2449 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2450 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2451 SDOperand CC = Node->getOperand(4); 2452 2453 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2454 2455 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2456 // the LHS is a legal SETCC itself. In this case, we need to compare 2457 // the result against zero to select between true and false values. 2458 if (Tmp2.Val == 0) { 2459 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2460 CC = DAG.getCondCode(ISD::SETNE); 2461 } 2462 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2463 2464 // Everything is legal, see if we should expand this op or something. 2465 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2466 default: assert(0 && "This action is not supported yet!"); 2467 case TargetLowering::Legal: break; 2468 case TargetLowering::Custom: 2469 Tmp1 = TLI.LowerOperation(Result, DAG); 2470 if (Tmp1.Val) Result = Tmp1; 2471 break; 2472 } 2473 break; 2474 } 2475 case ISD::SETCC: 2476 Tmp1 = Node->getOperand(0); 2477 Tmp2 = Node->getOperand(1); 2478 Tmp3 = Node->getOperand(2); 2479 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2480 2481 // If we had to Expand the SetCC operands into a SELECT node, then it may 2482 // not always be possible to return a true LHS & RHS. In this case, just 2483 // return the value we legalized, returned in the LHS 2484 if (Tmp2.Val == 0) { 2485 Result = Tmp1; 2486 break; 2487 } 2488 2489 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2490 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2491 case TargetLowering::Custom: 2492 isCustom = true; 2493 // FALLTHROUGH. 2494 case TargetLowering::Legal: 2495 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2496 if (isCustom) { 2497 Tmp4 = TLI.LowerOperation(Result, DAG); 2498 if (Tmp4.Val) Result = Tmp4; 2499 } 2500 break; 2501 case TargetLowering::Promote: { 2502 // First step, figure out the appropriate operation to use. 2503 // Allow SETCC to not be supported for all legal data types 2504 // Mostly this targets FP 2505 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2506 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2507 2508 // Scan for the appropriate larger type to use. 2509 while (1) { 2510 NewInTy = (MVT::ValueType)(NewInTy+1); 2511 2512 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2513 "Fell off of the edge of the integer world"); 2514 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2515 "Fell off of the edge of the floating point world"); 2516 2517 // If the target supports SETCC of this type, use it. 2518 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2519 break; 2520 } 2521 if (MVT::isInteger(NewInTy)) 2522 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2523 else { 2524 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2525 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2526 } 2527 Tmp1 = LegalizeOp(Tmp1); 2528 Tmp2 = LegalizeOp(Tmp2); 2529 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2530 Result = LegalizeOp(Result); 2531 break; 2532 } 2533 case TargetLowering::Expand: 2534 // Expand a setcc node into a select_cc of the same condition, lhs, and 2535 // rhs that selects between const 1 (true) and const 0 (false). 2536 MVT::ValueType VT = Node->getValueType(0); 2537 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2538 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2539 Tmp3); 2540 break; 2541 } 2542 break; 2543 case ISD::MEMSET: 2544 case ISD::MEMCPY: 2545 case ISD::MEMMOVE: { 2546 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2547 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2548 2549 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2550 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2551 case Expand: assert(0 && "Cannot expand a byte!"); 2552 case Legal: 2553 Tmp3 = LegalizeOp(Node->getOperand(2)); 2554 break; 2555 case Promote: 2556 Tmp3 = PromoteOp(Node->getOperand(2)); 2557 break; 2558 } 2559 } else { 2560 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2561 } 2562 2563 SDOperand Tmp4; 2564 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2565 case Expand: { 2566 // Length is too big, just take the lo-part of the length. 2567 SDOperand HiPart; 2568 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2569 break; 2570 } 2571 case Legal: 2572 Tmp4 = LegalizeOp(Node->getOperand(3)); 2573 break; 2574 case Promote: 2575 Tmp4 = PromoteOp(Node->getOperand(3)); 2576 break; 2577 } 2578 2579 SDOperand Tmp5; 2580 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2581 case Expand: assert(0 && "Cannot expand this yet!"); 2582 case Legal: 2583 Tmp5 = LegalizeOp(Node->getOperand(4)); 2584 break; 2585 case Promote: 2586 Tmp5 = PromoteOp(Node->getOperand(4)); 2587 break; 2588 } 2589 2590 SDOperand Tmp6; 2591 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool 2592 case Expand: assert(0 && "Cannot expand this yet!"); 2593 case Legal: 2594 Tmp6 = LegalizeOp(Node->getOperand(5)); 2595 break; 2596 case Promote: 2597 Tmp6 = PromoteOp(Node->getOperand(5)); 2598 break; 2599 } 2600 2601 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2602 default: assert(0 && "This action not implemented for this operation!"); 2603 case TargetLowering::Custom: 2604 isCustom = true; 2605 // FALLTHROUGH 2606 case TargetLowering::Legal: { 2607 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 }; 2608 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 2609 if (isCustom) { 2610 Tmp1 = TLI.LowerOperation(Result, DAG); 2611 if (Tmp1.Val) Result = Tmp1; 2612 } 2613 break; 2614 } 2615 case TargetLowering::Expand: { 2616 // Otherwise, the target does not support this operation. Lower the 2617 // operation to an explicit libcall as appropriate. 2618 MVT::ValueType IntPtr = TLI.getPointerTy(); 2619 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2620 TargetLowering::ArgListTy Args; 2621 TargetLowering::ArgListEntry Entry; 2622 2623 const char *FnName = 0; 2624 if (Node->getOpcode() == ISD::MEMSET) { 2625 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; 2626 Args.push_back(Entry); 2627 // Extend the (previously legalized) ubyte argument to be an int value 2628 // for the call. 2629 if (Tmp3.getValueType() > MVT::i32) 2630 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2631 else 2632 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2633 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 2634 Args.push_back(Entry); 2635 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false; 2636 Args.push_back(Entry); 2637 2638 FnName = "memset"; 2639 } else if (Node->getOpcode() == ISD::MEMCPY || 2640 Node->getOpcode() == ISD::MEMMOVE) { 2641 Entry.Ty = IntPtrTy; 2642 Entry.Node = Tmp2; Args.push_back(Entry); 2643 Entry.Node = Tmp3; Args.push_back(Entry); 2644 Entry.Node = Tmp4; Args.push_back(Entry); 2645 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2646 } else { 2647 assert(0 && "Unknown op!"); 2648 } 2649 2650 std::pair<SDOperand,SDOperand> CallResult = 2651 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 2652 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2653 Result = CallResult.second; 2654 break; 2655 } 2656 } 2657 break; 2658 } 2659 2660 case ISD::SHL_PARTS: 2661 case ISD::SRA_PARTS: 2662 case ISD::SRL_PARTS: { 2663 SmallVector<SDOperand, 8> Ops; 2664 bool Changed = false; 2665 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2666 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2667 Changed |= Ops.back() != Node->getOperand(i); 2668 } 2669 if (Changed) 2670 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2671 2672 switch (TLI.getOperationAction(Node->getOpcode(), 2673 Node->getValueType(0))) { 2674 default: assert(0 && "This action is not supported yet!"); 2675 case TargetLowering::Legal: break; 2676 case TargetLowering::Custom: 2677 Tmp1 = TLI.LowerOperation(Result, DAG); 2678 if (Tmp1.Val) { 2679 SDOperand Tmp2, RetVal(0, 0); 2680 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2681 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2682 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2683 if (i == Op.ResNo) 2684 RetVal = Tmp2; 2685 } 2686 assert(RetVal.Val && "Illegal result number"); 2687 return RetVal; 2688 } 2689 break; 2690 } 2691 2692 // Since these produce multiple values, make sure to remember that we 2693 // legalized all of them. 2694 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2695 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2696 return Result.getValue(Op.ResNo); 2697 } 2698 2699 // Binary operators 2700 case ISD::ADD: 2701 case ISD::SUB: 2702 case ISD::MUL: 2703 case ISD::MULHS: 2704 case ISD::MULHU: 2705 case ISD::UDIV: 2706 case ISD::SDIV: 2707 case ISD::AND: 2708 case ISD::OR: 2709 case ISD::XOR: 2710 case ISD::SHL: 2711 case ISD::SRL: 2712 case ISD::SRA: 2713 case ISD::FADD: 2714 case ISD::FSUB: 2715 case ISD::FMUL: 2716 case ISD::FDIV: 2717 case ISD::FPOW: 2718 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2719 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2720 case Expand: assert(0 && "Not possible"); 2721 case Legal: 2722 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2723 break; 2724 case Promote: 2725 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2726 break; 2727 } 2728 2729 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2730 2731 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2732 default: assert(0 && "BinOp legalize operation not supported"); 2733 case TargetLowering::Legal: break; 2734 case TargetLowering::Custom: 2735 Tmp1 = TLI.LowerOperation(Result, DAG); 2736 if (Tmp1.Val) Result = Tmp1; 2737 break; 2738 case TargetLowering::Expand: { 2739 MVT::ValueType VT = Op.getValueType(); 2740 2741 // See if multiply or divide can be lowered using two-result operations. 2742 SDVTList VTs = DAG.getVTList(VT, VT); 2743 if (Node->getOpcode() == ISD::MUL) { 2744 // We just need the low half of the multiply; try both the signed 2745 // and unsigned forms. If the target supports both SMUL_LOHI and 2746 // UMUL_LOHI, form a preference by checking which forms of plain 2747 // MULH it supports. 2748 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2749 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2750 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2751 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2752 unsigned OpToUse = 0; 2753 if (HasSMUL_LOHI && !HasMULHS) { 2754 OpToUse = ISD::SMUL_LOHI; 2755 } else if (HasUMUL_LOHI && !HasMULHU) { 2756 OpToUse = ISD::UMUL_LOHI; 2757 } else if (HasSMUL_LOHI) { 2758 OpToUse = ISD::SMUL_LOHI; 2759 } else if (HasUMUL_LOHI) { 2760 OpToUse = ISD::UMUL_LOHI; 2761 } 2762 if (OpToUse) { 2763 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 2764 break; 2765 } 2766 } 2767 if (Node->getOpcode() == ISD::MULHS && 2768 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 2769 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2770 break; 2771 } 2772 if (Node->getOpcode() == ISD::MULHU && 2773 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 2774 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2775 break; 2776 } 2777 if (Node->getOpcode() == ISD::SDIV && 2778 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 2779 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 2780 break; 2781 } 2782 if (Node->getOpcode() == ISD::UDIV && 2783 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 2784 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 2785 break; 2786 } 2787 2788 // Check to see if we have a libcall for this operator. 2789 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2790 bool isSigned = false; 2791 switch (Node->getOpcode()) { 2792 case ISD::UDIV: 2793 case ISD::SDIV: 2794 if (VT == MVT::i32) { 2795 LC = Node->getOpcode() == ISD::UDIV 2796 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 2797 isSigned = Node->getOpcode() == ISD::SDIV; 2798 } 2799 break; 2800 case ISD::FPOW: 2801 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 2802 RTLIB::POW_PPCF128); 2803 break; 2804 default: break; 2805 } 2806 if (LC != RTLIB::UNKNOWN_LIBCALL) { 2807 SDOperand Dummy; 2808 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2809 break; 2810 } 2811 2812 assert(MVT::isVector(Node->getValueType(0)) && 2813 "Cannot expand this binary operator!"); 2814 // Expand the operation into a bunch of nasty scalar code. 2815 Result = LegalizeOp(UnrollVectorOp(Op)); 2816 break; 2817 } 2818 case TargetLowering::Promote: { 2819 switch (Node->getOpcode()) { 2820 default: assert(0 && "Do not know how to promote this BinOp!"); 2821 case ISD::AND: 2822 case ISD::OR: 2823 case ISD::XOR: { 2824 MVT::ValueType OVT = Node->getValueType(0); 2825 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2826 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2827 // Bit convert each of the values to the new type. 2828 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2829 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2830 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2831 // Bit convert the result back the original type. 2832 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2833 break; 2834 } 2835 } 2836 } 2837 } 2838 break; 2839 2840 case ISD::SMUL_LOHI: 2841 case ISD::UMUL_LOHI: 2842 case ISD::SDIVREM: 2843 case ISD::UDIVREM: 2844 // These nodes will only be produced by target-specific lowering, so 2845 // they shouldn't be here if they aren't legal. 2846 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 2847 "This must be legal!"); 2848 2849 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2850 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2851 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2852 break; 2853 2854 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2855 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2856 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2857 case Expand: assert(0 && "Not possible"); 2858 case Legal: 2859 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2860 break; 2861 case Promote: 2862 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2863 break; 2864 } 2865 2866 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2867 2868 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2869 default: assert(0 && "Operation not supported"); 2870 case TargetLowering::Custom: 2871 Tmp1 = TLI.LowerOperation(Result, DAG); 2872 if (Tmp1.Val) Result = Tmp1; 2873 break; 2874 case TargetLowering::Legal: break; 2875 case TargetLowering::Expand: { 2876 // If this target supports fabs/fneg natively and select is cheap, 2877 // do this efficiently. 2878 if (!TLI.isSelectExpensive() && 2879 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 2880 TargetLowering::Legal && 2881 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 2882 TargetLowering::Legal) { 2883 // Get the sign bit of the RHS. 2884 MVT::ValueType IVT = 2885 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2886 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2887 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2888 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2889 // Get the absolute value of the result. 2890 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2891 // Select between the nabs and abs value based on the sign bit of 2892 // the input. 2893 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2894 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2895 AbsVal), 2896 AbsVal); 2897 Result = LegalizeOp(Result); 2898 break; 2899 } 2900 2901 // Otherwise, do bitwise ops! 2902 MVT::ValueType NVT = 2903 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 2904 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 2905 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 2906 Result = LegalizeOp(Result); 2907 break; 2908 } 2909 } 2910 break; 2911 2912 case ISD::ADDC: 2913 case ISD::SUBC: 2914 Tmp1 = LegalizeOp(Node->getOperand(0)); 2915 Tmp2 = LegalizeOp(Node->getOperand(1)); 2916 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2917 // Since this produces two values, make sure to remember that we legalized 2918 // both of them. 2919 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2920 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2921 return Result; 2922 2923 case ISD::ADDE: 2924 case ISD::SUBE: 2925 Tmp1 = LegalizeOp(Node->getOperand(0)); 2926 Tmp2 = LegalizeOp(Node->getOperand(1)); 2927 Tmp3 = LegalizeOp(Node->getOperand(2)); 2928 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2929 // Since this produces two values, make sure to remember that we legalized 2930 // both of them. 2931 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2932 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2933 return Result; 2934 2935 case ISD::BUILD_PAIR: { 2936 MVT::ValueType PairTy = Node->getValueType(0); 2937 // TODO: handle the case where the Lo and Hi operands are not of legal type 2938 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2939 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2940 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2941 case TargetLowering::Promote: 2942 case TargetLowering::Custom: 2943 assert(0 && "Cannot promote/custom this yet!"); 2944 case TargetLowering::Legal: 2945 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2946 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2947 break; 2948 case TargetLowering::Expand: 2949 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2950 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2951 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2952 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2953 TLI.getShiftAmountTy())); 2954 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2955 break; 2956 } 2957 break; 2958 } 2959 2960 case ISD::UREM: 2961 case ISD::SREM: 2962 case ISD::FREM: 2963 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2964 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2965 2966 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2967 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2968 case TargetLowering::Custom: 2969 isCustom = true; 2970 // FALLTHROUGH 2971 case TargetLowering::Legal: 2972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2973 if (isCustom) { 2974 Tmp1 = TLI.LowerOperation(Result, DAG); 2975 if (Tmp1.Val) Result = Tmp1; 2976 } 2977 break; 2978 case TargetLowering::Expand: { 2979 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2980 bool isSigned = DivOpc == ISD::SDIV; 2981 MVT::ValueType VT = Node->getValueType(0); 2982 2983 // See if remainder can be lowered using two-result operations. 2984 SDVTList VTs = DAG.getVTList(VT, VT); 2985 if (Node->getOpcode() == ISD::SREM && 2986 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 2987 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 2988 break; 2989 } 2990 if (Node->getOpcode() == ISD::UREM && 2991 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 2992 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 2993 break; 2994 } 2995 2996 if (MVT::isInteger(VT)) { 2997 if (TLI.getOperationAction(DivOpc, VT) == 2998 TargetLowering::Legal) { 2999 // X % Y -> X-X/Y*Y 3000 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3001 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3002 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3003 } else if (MVT::isVector(VT)) { 3004 Result = LegalizeOp(UnrollVectorOp(Op)); 3005 } else { 3006 assert(VT == MVT::i32 && 3007 "Cannot expand this binary operator!"); 3008 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3009 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3010 SDOperand Dummy; 3011 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 3012 } 3013 } else { 3014 assert(MVT::isFloatingPoint(VT) && 3015 "remainder op must have integer or floating-point type"); 3016 if (MVT::isVector(VT)) { 3017 Result = LegalizeOp(UnrollVectorOp(Op)); 3018 } else { 3019 // Floating point mod -> fmod libcall. 3020 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3021 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3022 SDOperand Dummy; 3023 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3024 false/*sign irrelevant*/, Dummy); 3025 } 3026 } 3027 break; 3028 } 3029 } 3030 break; 3031 case ISD::VAARG: { 3032 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3033 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3034 3035 MVT::ValueType VT = Node->getValueType(0); 3036 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3037 default: assert(0 && "This action is not supported yet!"); 3038 case TargetLowering::Custom: 3039 isCustom = true; 3040 // FALLTHROUGH 3041 case TargetLowering::Legal: 3042 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3043 Result = Result.getValue(0); 3044 Tmp1 = Result.getValue(1); 3045 3046 if (isCustom) { 3047 Tmp2 = TLI.LowerOperation(Result, DAG); 3048 if (Tmp2.Val) { 3049 Result = LegalizeOp(Tmp2); 3050 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3051 } 3052 } 3053 break; 3054 case TargetLowering::Expand: { 3055 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 3056 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3057 SV->getValue(), SV->getOffset()); 3058 // Increment the pointer, VAList, to the next vaarg 3059 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3060 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3061 TLI.getPointerTy())); 3062 // Store the incremented VAList to the legalized pointer 3063 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 3064 SV->getOffset()); 3065 // Load the actual argument out of the pointer VAList 3066 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3067 Tmp1 = LegalizeOp(Result.getValue(1)); 3068 Result = LegalizeOp(Result); 3069 break; 3070 } 3071 } 3072 // Since VAARG produces two values, make sure to remember that we 3073 // legalized both of them. 3074 AddLegalizedOperand(SDOperand(Node, 0), Result); 3075 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3076 return Op.ResNo ? Tmp1 : Result; 3077 } 3078 3079 case ISD::VACOPY: 3080 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3081 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3082 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3083 3084 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3085 default: assert(0 && "This action is not supported yet!"); 3086 case TargetLowering::Custom: 3087 isCustom = true; 3088 // FALLTHROUGH 3089 case TargetLowering::Legal: 3090 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3091 Node->getOperand(3), Node->getOperand(4)); 3092 if (isCustom) { 3093 Tmp1 = TLI.LowerOperation(Result, DAG); 3094 if (Tmp1.Val) Result = Tmp1; 3095 } 3096 break; 3097 case TargetLowering::Expand: 3098 // This defaults to loading a pointer from the input and storing it to the 3099 // output, returning the chain. 3100 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 3101 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); 3102 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 3103 SVD->getOffset()); 3104 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), 3105 SVS->getOffset()); 3106 break; 3107 } 3108 break; 3109 3110 case ISD::VAEND: 3111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3112 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3113 3114 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3115 default: assert(0 && "This action is not supported yet!"); 3116 case TargetLowering::Custom: 3117 isCustom = true; 3118 // FALLTHROUGH 3119 case TargetLowering::Legal: 3120 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3121 if (isCustom) { 3122 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3123 if (Tmp1.Val) Result = Tmp1; 3124 } 3125 break; 3126 case TargetLowering::Expand: 3127 Result = Tmp1; // Default to a no-op, return the chain 3128 break; 3129 } 3130 break; 3131 3132 case ISD::VASTART: 3133 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3134 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3135 3136 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3137 3138 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3139 default: assert(0 && "This action is not supported yet!"); 3140 case TargetLowering::Legal: break; 3141 case TargetLowering::Custom: 3142 Tmp1 = TLI.LowerOperation(Result, DAG); 3143 if (Tmp1.Val) Result = Tmp1; 3144 break; 3145 } 3146 break; 3147 3148 case ISD::ROTL: 3149 case ISD::ROTR: 3150 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3151 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3152 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3153 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3154 default: 3155 assert(0 && "ROTL/ROTR legalize operation not supported"); 3156 break; 3157 case TargetLowering::Legal: 3158 break; 3159 case TargetLowering::Custom: 3160 Tmp1 = TLI.LowerOperation(Result, DAG); 3161 if (Tmp1.Val) Result = Tmp1; 3162 break; 3163 case TargetLowering::Promote: 3164 assert(0 && "Do not know how to promote ROTL/ROTR"); 3165 break; 3166 case TargetLowering::Expand: 3167 assert(0 && "Do not know how to expand ROTL/ROTR"); 3168 break; 3169 } 3170 break; 3171 3172 case ISD::BSWAP: 3173 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3174 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3175 case TargetLowering::Custom: 3176 assert(0 && "Cannot custom legalize this yet!"); 3177 case TargetLowering::Legal: 3178 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3179 break; 3180 case TargetLowering::Promote: { 3181 MVT::ValueType OVT = Tmp1.getValueType(); 3182 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3183 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 3184 3185 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3186 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3187 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3188 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3189 break; 3190 } 3191 case TargetLowering::Expand: 3192 Result = ExpandBSWAP(Tmp1); 3193 break; 3194 } 3195 break; 3196 3197 case ISD::CTPOP: 3198 case ISD::CTTZ: 3199 case ISD::CTLZ: 3200 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3201 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3202 case TargetLowering::Custom: 3203 case TargetLowering::Legal: 3204 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3205 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3206 TargetLowering::Custom) { 3207 Tmp1 = TLI.LowerOperation(Result, DAG); 3208 if (Tmp1.Val) { 3209 Result = Tmp1; 3210 } 3211 } 3212 break; 3213 case TargetLowering::Promote: { 3214 MVT::ValueType OVT = Tmp1.getValueType(); 3215 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3216 3217 // Zero extend the argument. 3218 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3219 // Perform the larger operation, then subtract if needed. 3220 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3221 switch (Node->getOpcode()) { 3222 case ISD::CTPOP: 3223 Result = Tmp1; 3224 break; 3225 case ISD::CTTZ: 3226 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3227 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3228 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3229 ISD::SETEQ); 3230 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3231 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 3232 break; 3233 case ISD::CTLZ: 3234 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3235 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3236 DAG.getConstant(MVT::getSizeInBits(NVT) - 3237 MVT::getSizeInBits(OVT), NVT)); 3238 break; 3239 } 3240 break; 3241 } 3242 case TargetLowering::Expand: 3243 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3244 break; 3245 } 3246 break; 3247 3248 // Unary operators 3249 case ISD::FABS: 3250 case ISD::FNEG: 3251 case ISD::FSQRT: 3252 case ISD::FSIN: 3253 case ISD::FCOS: 3254 Tmp1 = LegalizeOp(Node->getOperand(0)); 3255 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3256 case TargetLowering::Promote: 3257 case TargetLowering::Custom: 3258 isCustom = true; 3259 // FALLTHROUGH 3260 case TargetLowering::Legal: 3261 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3262 if (isCustom) { 3263 Tmp1 = TLI.LowerOperation(Result, DAG); 3264 if (Tmp1.Val) Result = Tmp1; 3265 } 3266 break; 3267 case TargetLowering::Expand: 3268 switch (Node->getOpcode()) { 3269 default: assert(0 && "Unreachable!"); 3270 case ISD::FNEG: 3271 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3272 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3273 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3274 break; 3275 case ISD::FABS: { 3276 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3277 MVT::ValueType VT = Node->getValueType(0); 3278 Tmp2 = DAG.getConstantFP(0.0, VT); 3279 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 3280 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3281 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3282 break; 3283 } 3284 case ISD::FSQRT: 3285 case ISD::FSIN: 3286 case ISD::FCOS: { 3287 MVT::ValueType VT = Node->getValueType(0); 3288 3289 // Expand unsupported unary vector operators by unrolling them. 3290 if (MVT::isVector(VT)) { 3291 Result = LegalizeOp(UnrollVectorOp(Op)); 3292 break; 3293 } 3294 3295 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3296 switch(Node->getOpcode()) { 3297 case ISD::FSQRT: 3298 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3299 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3300 break; 3301 case ISD::FSIN: 3302 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3303 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3304 break; 3305 case ISD::FCOS: 3306 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3307 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3308 break; 3309 default: assert(0 && "Unreachable!"); 3310 } 3311 SDOperand Dummy; 3312 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3313 false/*sign irrelevant*/, Dummy); 3314 break; 3315 } 3316 } 3317 break; 3318 } 3319 break; 3320 case ISD::FPOWI: { 3321 MVT::ValueType VT = Node->getValueType(0); 3322 3323 // Expand unsupported unary vector operators by unrolling them. 3324 if (MVT::isVector(VT)) { 3325 Result = LegalizeOp(UnrollVectorOp(Op)); 3326 break; 3327 } 3328 3329 // We always lower FPOWI into a libcall. No target support for it yet. 3330 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3331 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3332 SDOperand Dummy; 3333 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3334 false/*sign irrelevant*/, Dummy); 3335 break; 3336 } 3337 case ISD::BIT_CONVERT: 3338 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3339 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3340 Node->getValueType(0)); 3341 } else if (MVT::isVector(Op.getOperand(0).getValueType())) { 3342 // The input has to be a vector type, we have to either scalarize it, pack 3343 // it, or convert it based on whether the input vector type is legal. 3344 SDNode *InVal = Node->getOperand(0).Val; 3345 int InIx = Node->getOperand(0).ResNo; 3346 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 3347 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 3348 3349 // Figure out if there is a simple type corresponding to this Vector 3350 // type. If so, convert to the vector type. 3351 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3352 if (TLI.isTypeLegal(TVT)) { 3353 // Turn this into a bit convert of the vector input. 3354 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3355 LegalizeOp(Node->getOperand(0))); 3356 break; 3357 } else if (NumElems == 1) { 3358 // Turn this into a bit convert of the scalar input. 3359 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3360 ScalarizeVectorOp(Node->getOperand(0))); 3361 break; 3362 } else { 3363 // FIXME: UNIMP! Store then reload 3364 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3365 } 3366 } else { 3367 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3368 Node->getOperand(0).getValueType())) { 3369 default: assert(0 && "Unknown operation action!"); 3370 case TargetLowering::Expand: 3371 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3372 Node->getValueType(0)); 3373 break; 3374 case TargetLowering::Legal: 3375 Tmp1 = LegalizeOp(Node->getOperand(0)); 3376 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3377 break; 3378 } 3379 } 3380 break; 3381 3382 // Conversion operators. The source and destination have different types. 3383 case ISD::SINT_TO_FP: 3384 case ISD::UINT_TO_FP: { 3385 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3386 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3387 case Legal: 3388 switch (TLI.getOperationAction(Node->getOpcode(), 3389 Node->getOperand(0).getValueType())) { 3390 default: assert(0 && "Unknown operation action!"); 3391 case TargetLowering::Custom: 3392 isCustom = true; 3393 // FALLTHROUGH 3394 case TargetLowering::Legal: 3395 Tmp1 = LegalizeOp(Node->getOperand(0)); 3396 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3397 if (isCustom) { 3398 Tmp1 = TLI.LowerOperation(Result, DAG); 3399 if (Tmp1.Val) Result = Tmp1; 3400 } 3401 break; 3402 case TargetLowering::Expand: 3403 Result = ExpandLegalINT_TO_FP(isSigned, 3404 LegalizeOp(Node->getOperand(0)), 3405 Node->getValueType(0)); 3406 break; 3407 case TargetLowering::Promote: 3408 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3409 Node->getValueType(0), 3410 isSigned); 3411 break; 3412 } 3413 break; 3414 case Expand: 3415 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3416 Node->getValueType(0), Node->getOperand(0)); 3417 break; 3418 case Promote: 3419 Tmp1 = PromoteOp(Node->getOperand(0)); 3420 if (isSigned) { 3421 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3422 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3423 } else { 3424 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3425 Node->getOperand(0).getValueType()); 3426 } 3427 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3428 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3429 break; 3430 } 3431 break; 3432 } 3433 case ISD::TRUNCATE: 3434 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3435 case Legal: 3436 Tmp1 = LegalizeOp(Node->getOperand(0)); 3437 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3438 break; 3439 case Expand: 3440 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3441 3442 // Since the result is legal, we should just be able to truncate the low 3443 // part of the source. 3444 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3445 break; 3446 case Promote: 3447 Result = PromoteOp(Node->getOperand(0)); 3448 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3449 break; 3450 } 3451 break; 3452 3453 case ISD::FP_TO_SINT: 3454 case ISD::FP_TO_UINT: 3455 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3456 case Legal: 3457 Tmp1 = LegalizeOp(Node->getOperand(0)); 3458 3459 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3460 default: assert(0 && "Unknown operation action!"); 3461 case TargetLowering::Custom: 3462 isCustom = true; 3463 // FALLTHROUGH 3464 case TargetLowering::Legal: 3465 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3466 if (isCustom) { 3467 Tmp1 = TLI.LowerOperation(Result, DAG); 3468 if (Tmp1.Val) Result = Tmp1; 3469 } 3470 break; 3471 case TargetLowering::Promote: 3472 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3473 Node->getOpcode() == ISD::FP_TO_SINT); 3474 break; 3475 case TargetLowering::Expand: 3476 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3477 SDOperand True, False; 3478 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3479 MVT::ValueType NVT = Node->getValueType(0); 3480 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1; 3481 const uint64_t zero[] = {0, 0}; 3482 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero)); 3483 uint64_t x = 1ULL << ShiftAmt; 3484 (void)apf.convertFromZeroExtendedInteger 3485 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven); 3486 Tmp2 = DAG.getConstantFP(apf, VT); 3487 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 3488 Node->getOperand(0), Tmp2, ISD::SETLT); 3489 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3490 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3491 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3492 Tmp2)); 3493 False = DAG.getNode(ISD::XOR, NVT, False, 3494 DAG.getConstant(1ULL << ShiftAmt, NVT)); 3495 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3496 break; 3497 } else { 3498 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3499 } 3500 break; 3501 } 3502 break; 3503 case Expand: { 3504 MVT::ValueType VT = Op.getValueType(); 3505 MVT::ValueType OVT = Node->getOperand(0).getValueType(); 3506 // Convert ppcf128 to i32 3507 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3508 if (Node->getOpcode() == ISD::FP_TO_SINT) { 3509 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 3510 Node->getOperand(0), DAG.getValueType(MVT::f64)); 3511 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 3512 DAG.getIntPtrConstant(1)); 3513 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 3514 } else { 3515 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3516 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3517 Tmp2 = DAG.getConstantFP(apf, OVT); 3518 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3519 // FIXME: generated code sucks. 3520 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3521 DAG.getNode(ISD::ADD, MVT::i32, 3522 DAG.getNode(ISD::FP_TO_SINT, VT, 3523 DAG.getNode(ISD::FSUB, OVT, 3524 Node->getOperand(0), Tmp2)), 3525 DAG.getConstant(0x80000000, MVT::i32)), 3526 DAG.getNode(ISD::FP_TO_SINT, VT, 3527 Node->getOperand(0)), 3528 DAG.getCondCode(ISD::SETGE)); 3529 } 3530 break; 3531 } 3532 // Convert f32 / f64 to i32 / i64. 3533 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3534 switch (Node->getOpcode()) { 3535 case ISD::FP_TO_SINT: { 3536 if (OVT == MVT::f32) 3537 LC = (VT == MVT::i32) 3538 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3539 else if (OVT == MVT::f64) 3540 LC = (VT == MVT::i32) 3541 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3542 else if (OVT == MVT::f80) { 3543 assert(VT == MVT::i64); 3544 LC = RTLIB::FPTOSINT_F80_I64; 3545 } 3546 else if (OVT == MVT::ppcf128) { 3547 assert(VT == MVT::i64); 3548 LC = RTLIB::FPTOSINT_PPCF128_I64; 3549 } 3550 break; 3551 } 3552 case ISD::FP_TO_UINT: { 3553 if (OVT == MVT::f32) 3554 LC = (VT == MVT::i32) 3555 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3556 else if (OVT == MVT::f64) 3557 LC = (VT == MVT::i32) 3558 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3559 else if (OVT == MVT::f80) { 3560 LC = (VT == MVT::i32) 3561 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64; 3562 } 3563 else if (OVT == MVT::ppcf128) { 3564 assert(VT == MVT::i64); 3565 LC = RTLIB::FPTOUINT_PPCF128_I64; 3566 } 3567 break; 3568 } 3569 default: assert(0 && "Unreachable!"); 3570 } 3571 SDOperand Dummy; 3572 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3573 false/*sign irrelevant*/, Dummy); 3574 break; 3575 } 3576 case Promote: 3577 Tmp1 = PromoteOp(Node->getOperand(0)); 3578 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3579 Result = LegalizeOp(Result); 3580 break; 3581 } 3582 break; 3583 3584 case ISD::FP_EXTEND: { 3585 MVT::ValueType DstVT = Op.getValueType(); 3586 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3587 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3588 // The only other way we can lower this is to turn it into a STORE, 3589 // LOAD pair, targetting a temporary location (a stack slot). 3590 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 3591 break; 3592 } 3593 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3594 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3595 case Legal: 3596 Tmp1 = LegalizeOp(Node->getOperand(0)); 3597 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3598 break; 3599 case Promote: 3600 Tmp1 = PromoteOp(Node->getOperand(0)); 3601 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3602 break; 3603 } 3604 break; 3605 } 3606 case ISD::FP_ROUND: { 3607 MVT::ValueType DstVT = Op.getValueType(); 3608 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3609 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3610 if (SrcVT == MVT::ppcf128) { 3611 SDOperand Lo; 3612 ExpandOp(Node->getOperand(0), Lo, Result); 3613 // Round it the rest of the way (e.g. to f32) if needed. 3614 if (DstVT!=MVT::f64) 3615 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 3616 break; 3617 } 3618 // The only other way we can lower this is to turn it into a STORE, 3619 // LOAD pair, targetting a temporary location (a stack slot). 3620 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 3621 break; 3622 } 3623 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3624 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3625 case Legal: 3626 Tmp1 = LegalizeOp(Node->getOperand(0)); 3627 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3628 break; 3629 case Promote: 3630 Tmp1 = PromoteOp(Node->getOperand(0)); 3631 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 3632 Node->getOperand(1)); 3633 break; 3634 } 3635 break; 3636 } 3637 case ISD::ANY_EXTEND: 3638 case ISD::ZERO_EXTEND: 3639 case ISD::SIGN_EXTEND: 3640 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3641 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3642 case Legal: 3643 Tmp1 = LegalizeOp(Node->getOperand(0)); 3644 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3645 break; 3646 case Promote: 3647 switch (Node->getOpcode()) { 3648 case ISD::ANY_EXTEND: 3649 Tmp1 = PromoteOp(Node->getOperand(0)); 3650 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3651 break; 3652 case ISD::ZERO_EXTEND: 3653 Result = PromoteOp(Node->getOperand(0)); 3654 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3655 Result = DAG.getZeroExtendInReg(Result, 3656 Node->getOperand(0).getValueType()); 3657 break; 3658 case ISD::SIGN_EXTEND: 3659 Result = PromoteOp(Node->getOperand(0)); 3660 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3661 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3662 Result, 3663 DAG.getValueType(Node->getOperand(0).getValueType())); 3664 break; 3665 } 3666 } 3667 break; 3668 case ISD::FP_ROUND_INREG: 3669 case ISD::SIGN_EXTEND_INREG: { 3670 Tmp1 = LegalizeOp(Node->getOperand(0)); 3671 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3672 3673 // If this operation is not supported, convert it to a shl/shr or load/store 3674 // pair. 3675 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3676 default: assert(0 && "This action not supported for this op yet!"); 3677 case TargetLowering::Legal: 3678 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3679 break; 3680 case TargetLowering::Expand: 3681 // If this is an integer extend and shifts are supported, do that. 3682 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3683 // NOTE: we could fall back on load/store here too for targets without 3684 // SAR. However, it is doubtful that any exist. 3685 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3686 MVT::getSizeInBits(ExtraVT); 3687 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3688 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3689 Node->getOperand(0), ShiftCst); 3690 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3691 Result, ShiftCst); 3692 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3693 // The only way we can lower this is to turn it into a TRUNCSTORE, 3694 // EXTLOAD pair, targetting a temporary location (a stack slot). 3695 3696 // NOTE: there is a choice here between constantly creating new stack 3697 // slots and always reusing the same one. We currently always create 3698 // new ones, as reuse may inhibit scheduling. 3699 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 3700 Node->getValueType(0)); 3701 } else { 3702 assert(0 && "Unknown op"); 3703 } 3704 break; 3705 } 3706 break; 3707 } 3708 case ISD::TRAMPOLINE: { 3709 SDOperand Ops[6]; 3710 for (unsigned i = 0; i != 6; ++i) 3711 Ops[i] = LegalizeOp(Node->getOperand(i)); 3712 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3713 // The only option for this node is to custom lower it. 3714 Result = TLI.LowerOperation(Result, DAG); 3715 assert(Result.Val && "Should always custom lower!"); 3716 3717 // Since trampoline produces two values, make sure to remember that we 3718 // legalized both of them. 3719 Tmp1 = LegalizeOp(Result.getValue(1)); 3720 Result = LegalizeOp(Result); 3721 AddLegalizedOperand(SDOperand(Node, 0), Result); 3722 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3723 return Op.ResNo ? Tmp1 : Result; 3724 } 3725 case ISD::FLT_ROUNDS: { 3726 MVT::ValueType VT = Node->getValueType(0); 3727 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3728 default: assert(0 && "This action not supported for this op yet!"); 3729 case TargetLowering::Custom: 3730 Result = TLI.LowerOperation(Op, DAG); 3731 if (Result.Val) break; 3732 // Fall Thru 3733 case TargetLowering::Legal: 3734 // If this operation is not supported, lower it to constant 1 3735 Result = DAG.getConstant(1, VT); 3736 break; 3737 } 3738 } 3739 case ISD::TRAP: { 3740 MVT::ValueType VT = Node->getValueType(0); 3741 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3742 default: assert(0 && "This action not supported for this op yet!"); 3743 case TargetLowering::Legal: 3744 Tmp1 = LegalizeOp(Node->getOperand(0)); 3745 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3746 break; 3747 case TargetLowering::Custom: 3748 Result = TLI.LowerOperation(Op, DAG); 3749 if (Result.Val) break; 3750 // Fall Thru 3751 case TargetLowering::Expand: 3752 // If this operation is not supported, lower it to 'abort()' call 3753 Tmp1 = LegalizeOp(Node->getOperand(0)); 3754 TargetLowering::ArgListTy Args; 3755 std::pair<SDOperand,SDOperand> CallResult = 3756 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 3757 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 3758 Args, DAG); 3759 Result = CallResult.second; 3760 break; 3761 } 3762 break; 3763 } 3764 } 3765 3766 assert(Result.getValueType() == Op.getValueType() && 3767 "Bad legalization!"); 3768 3769 // Make sure that the generated code is itself legal. 3770 if (Result != Op) 3771 Result = LegalizeOp(Result); 3772 3773 // Note that LegalizeOp may be reentered even from single-use nodes, which 3774 // means that we always must cache transformed nodes. 3775 AddLegalizedOperand(Op, Result); 3776 return Result; 3777} 3778 3779/// PromoteOp - Given an operation that produces a value in an invalid type, 3780/// promote it to compute the value into a larger type. The produced value will 3781/// have the correct bits for the low portion of the register, but no guarantee 3782/// is made about the top bits: it may be zero, sign-extended, or garbage. 3783SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 3784 MVT::ValueType VT = Op.getValueType(); 3785 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3786 assert(getTypeAction(VT) == Promote && 3787 "Caller should expand or legalize operands that are not promotable!"); 3788 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 3789 "Cannot promote to smaller type!"); 3790 3791 SDOperand Tmp1, Tmp2, Tmp3; 3792 SDOperand Result; 3793 SDNode *Node = Op.Val; 3794 3795 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 3796 if (I != PromotedNodes.end()) return I->second; 3797 3798 switch (Node->getOpcode()) { 3799 case ISD::CopyFromReg: 3800 assert(0 && "CopyFromReg must be legal!"); 3801 default: 3802#ifndef NDEBUG 3803 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 3804#endif 3805 assert(0 && "Do not know how to promote this operator!"); 3806 abort(); 3807 case ISD::UNDEF: 3808 Result = DAG.getNode(ISD::UNDEF, NVT); 3809 break; 3810 case ISD::Constant: 3811 if (VT != MVT::i1) 3812 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 3813 else 3814 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 3815 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 3816 break; 3817 case ISD::ConstantFP: 3818 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 3819 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 3820 break; 3821 3822 case ISD::SETCC: 3823 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 3824 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 3825 Node->getOperand(1), Node->getOperand(2)); 3826 break; 3827 3828 case ISD::TRUNCATE: 3829 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3830 case Legal: 3831 Result = LegalizeOp(Node->getOperand(0)); 3832 assert(Result.getValueType() >= NVT && 3833 "This truncation doesn't make sense!"); 3834 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 3835 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 3836 break; 3837 case Promote: 3838 // The truncation is not required, because we don't guarantee anything 3839 // about high bits anyway. 3840 Result = PromoteOp(Node->getOperand(0)); 3841 break; 3842 case Expand: 3843 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3844 // Truncate the low part of the expanded value to the result type 3845 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 3846 } 3847 break; 3848 case ISD::SIGN_EXTEND: 3849 case ISD::ZERO_EXTEND: 3850 case ISD::ANY_EXTEND: 3851 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3852 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 3853 case Legal: 3854 // Input is legal? Just do extend all the way to the larger type. 3855 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3856 break; 3857 case Promote: 3858 // Promote the reg if it's smaller. 3859 Result = PromoteOp(Node->getOperand(0)); 3860 // The high bits are not guaranteed to be anything. Insert an extend. 3861 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3862 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3863 DAG.getValueType(Node->getOperand(0).getValueType())); 3864 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3865 Result = DAG.getZeroExtendInReg(Result, 3866 Node->getOperand(0).getValueType()); 3867 break; 3868 } 3869 break; 3870 case ISD::BIT_CONVERT: 3871 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3872 Node->getValueType(0)); 3873 Result = PromoteOp(Result); 3874 break; 3875 3876 case ISD::FP_EXTEND: 3877 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3878 case ISD::FP_ROUND: 3879 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3880 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3881 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3882 case Legal: 3883 if (Node->getConstantOperandVal(1) == 0) { 3884 // Input is legal? Do an FP_ROUND_INREG. 3885 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 3886 DAG.getValueType(VT)); 3887 } else { 3888 // Just remove the truncate, it isn't affecting the value. 3889 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 3890 Node->getOperand(1)); 3891 } 3892 break; 3893 } 3894 break; 3895 case ISD::SINT_TO_FP: 3896 case ISD::UINT_TO_FP: 3897 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3898 case Legal: 3899 // No extra round required here. 3900 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3901 break; 3902 3903 case Promote: 3904 Result = PromoteOp(Node->getOperand(0)); 3905 if (Node->getOpcode() == ISD::SINT_TO_FP) 3906 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3907 Result, 3908 DAG.getValueType(Node->getOperand(0).getValueType())); 3909 else 3910 Result = DAG.getZeroExtendInReg(Result, 3911 Node->getOperand(0).getValueType()); 3912 // No extra round required here. 3913 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3914 break; 3915 case Expand: 3916 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3917 Node->getOperand(0)); 3918 // Round if we cannot tolerate excess precision. 3919 if (NoExcessFPPrecision) 3920 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3921 DAG.getValueType(VT)); 3922 break; 3923 } 3924 break; 3925 3926 case ISD::SIGN_EXTEND_INREG: 3927 Result = PromoteOp(Node->getOperand(0)); 3928 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3929 Node->getOperand(1)); 3930 break; 3931 case ISD::FP_TO_SINT: 3932 case ISD::FP_TO_UINT: 3933 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3934 case Legal: 3935 case Expand: 3936 Tmp1 = Node->getOperand(0); 3937 break; 3938 case Promote: 3939 // The input result is prerounded, so we don't have to do anything 3940 // special. 3941 Tmp1 = PromoteOp(Node->getOperand(0)); 3942 break; 3943 } 3944 // If we're promoting a UINT to a larger size, check to see if the new node 3945 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3946 // we can use that instead. This allows us to generate better code for 3947 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3948 // legal, such as PowerPC. 3949 if (Node->getOpcode() == ISD::FP_TO_UINT && 3950 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3951 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3952 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3953 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3954 } else { 3955 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3956 } 3957 break; 3958 3959 case ISD::FABS: 3960 case ISD::FNEG: 3961 Tmp1 = PromoteOp(Node->getOperand(0)); 3962 assert(Tmp1.getValueType() == NVT); 3963 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3964 // NOTE: we do not have to do any extra rounding here for 3965 // NoExcessFPPrecision, because we know the input will have the appropriate 3966 // precision, and these operations don't modify precision at all. 3967 break; 3968 3969 case ISD::FSQRT: 3970 case ISD::FSIN: 3971 case ISD::FCOS: 3972 Tmp1 = PromoteOp(Node->getOperand(0)); 3973 assert(Tmp1.getValueType() == NVT); 3974 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3975 if (NoExcessFPPrecision) 3976 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3977 DAG.getValueType(VT)); 3978 break; 3979 3980 case ISD::FPOWI: { 3981 // Promote f32 powi to f64 powi. Note that this could insert a libcall 3982 // directly as well, which may be better. 3983 Tmp1 = PromoteOp(Node->getOperand(0)); 3984 assert(Tmp1.getValueType() == NVT); 3985 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 3986 if (NoExcessFPPrecision) 3987 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3988 DAG.getValueType(VT)); 3989 break; 3990 } 3991 3992 case ISD::AND: 3993 case ISD::OR: 3994 case ISD::XOR: 3995 case ISD::ADD: 3996 case ISD::SUB: 3997 case ISD::MUL: 3998 // The input may have strange things in the top bits of the registers, but 3999 // these operations don't care. They may have weird bits going out, but 4000 // that too is okay if they are integer operations. 4001 Tmp1 = PromoteOp(Node->getOperand(0)); 4002 Tmp2 = PromoteOp(Node->getOperand(1)); 4003 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4004 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4005 break; 4006 case ISD::FADD: 4007 case ISD::FSUB: 4008 case ISD::FMUL: 4009 Tmp1 = PromoteOp(Node->getOperand(0)); 4010 Tmp2 = PromoteOp(Node->getOperand(1)); 4011 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4012 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4013 4014 // Floating point operations will give excess precision that we may not be 4015 // able to tolerate. If we DO allow excess precision, just leave it, 4016 // otherwise excise it. 4017 // FIXME: Why would we need to round FP ops more than integer ones? 4018 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4019 if (NoExcessFPPrecision) 4020 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4021 DAG.getValueType(VT)); 4022 break; 4023 4024 case ISD::SDIV: 4025 case ISD::SREM: 4026 // These operators require that their input be sign extended. 4027 Tmp1 = PromoteOp(Node->getOperand(0)); 4028 Tmp2 = PromoteOp(Node->getOperand(1)); 4029 if (MVT::isInteger(NVT)) { 4030 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4031 DAG.getValueType(VT)); 4032 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4033 DAG.getValueType(VT)); 4034 } 4035 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4036 4037 // Perform FP_ROUND: this is probably overly pessimistic. 4038 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 4039 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4040 DAG.getValueType(VT)); 4041 break; 4042 case ISD::FDIV: 4043 case ISD::FREM: 4044 case ISD::FCOPYSIGN: 4045 // These operators require that their input be fp extended. 4046 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4047 case Expand: assert(0 && "not implemented"); 4048 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4049 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4050 } 4051 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4052 case Expand: assert(0 && "not implemented"); 4053 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4054 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4055 } 4056 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4057 4058 // Perform FP_ROUND: this is probably overly pessimistic. 4059 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4060 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4061 DAG.getValueType(VT)); 4062 break; 4063 4064 case ISD::UDIV: 4065 case ISD::UREM: 4066 // These operators require that their input be zero extended. 4067 Tmp1 = PromoteOp(Node->getOperand(0)); 4068 Tmp2 = PromoteOp(Node->getOperand(1)); 4069 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 4070 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4071 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4072 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4073 break; 4074 4075 case ISD::SHL: 4076 Tmp1 = PromoteOp(Node->getOperand(0)); 4077 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4078 break; 4079 case ISD::SRA: 4080 // The input value must be properly sign extended. 4081 Tmp1 = PromoteOp(Node->getOperand(0)); 4082 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4083 DAG.getValueType(VT)); 4084 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4085 break; 4086 case ISD::SRL: 4087 // The input value must be properly zero extended. 4088 Tmp1 = PromoteOp(Node->getOperand(0)); 4089 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4090 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4091 break; 4092 4093 case ISD::VAARG: 4094 Tmp1 = Node->getOperand(0); // Get the chain. 4095 Tmp2 = Node->getOperand(1); // Get the pointer. 4096 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4097 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4098 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 4099 } else { 4100 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 4101 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 4102 SV->getValue(), SV->getOffset()); 4103 // Increment the pointer, VAList, to the next vaarg 4104 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4105 DAG.getConstant(MVT::getSizeInBits(VT)/8, 4106 TLI.getPointerTy())); 4107 // Store the incremented VAList to the legalized pointer 4108 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 4109 SV->getOffset()); 4110 // Load the actual argument out of the pointer VAList 4111 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4112 } 4113 // Remember that we legalized the chain. 4114 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4115 break; 4116 4117 case ISD::LOAD: { 4118 LoadSDNode *LD = cast<LoadSDNode>(Node); 4119 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4120 ? ISD::EXTLOAD : LD->getExtensionType(); 4121 Result = DAG.getExtLoad(ExtType, NVT, 4122 LD->getChain(), LD->getBasePtr(), 4123 LD->getSrcValue(), LD->getSrcValueOffset(), 4124 LD->getLoadedVT(), 4125 LD->isVolatile(), 4126 LD->getAlignment()); 4127 // Remember that we legalized the chain. 4128 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4129 break; 4130 } 4131 case ISD::SELECT: 4132 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4133 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4134 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 4135 break; 4136 case ISD::SELECT_CC: 4137 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4138 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4139 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4140 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4141 break; 4142 case ISD::BSWAP: 4143 Tmp1 = Node->getOperand(0); 4144 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4145 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4146 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4147 DAG.getConstant(MVT::getSizeInBits(NVT) - 4148 MVT::getSizeInBits(VT), 4149 TLI.getShiftAmountTy())); 4150 break; 4151 case ISD::CTPOP: 4152 case ISD::CTTZ: 4153 case ISD::CTLZ: 4154 // Zero extend the argument 4155 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4156 // Perform the larger operation, then subtract if needed. 4157 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4158 switch(Node->getOpcode()) { 4159 case ISD::CTPOP: 4160 Result = Tmp1; 4161 break; 4162 case ISD::CTTZ: 4163 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4164 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 4165 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 4166 ISD::SETEQ); 4167 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4168 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 4169 break; 4170 case ISD::CTLZ: 4171 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4172 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4173 DAG.getConstant(MVT::getSizeInBits(NVT) - 4174 MVT::getSizeInBits(VT), NVT)); 4175 break; 4176 } 4177 break; 4178 case ISD::EXTRACT_SUBVECTOR: 4179 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4180 break; 4181 case ISD::EXTRACT_VECTOR_ELT: 4182 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4183 break; 4184 } 4185 4186 assert(Result.Val && "Didn't set a result!"); 4187 4188 // Make sure the result is itself legal. 4189 Result = LegalizeOp(Result); 4190 4191 // Remember that we promoted this! 4192 AddPromotedOperand(Op, Result); 4193 return Result; 4194} 4195 4196/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4197/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4198/// based on the vector type. The return type of this matches the element type 4199/// of the vector, which may not be legal for the target. 4200SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4201 // We know that operand #0 is the Vec vector. If the index is a constant 4202 // or if the invec is a supported hardware type, we can use it. Otherwise, 4203 // lower to a store then an indexed load. 4204 SDOperand Vec = Op.getOperand(0); 4205 SDOperand Idx = Op.getOperand(1); 4206 4207 MVT::ValueType TVT = Vec.getValueType(); 4208 unsigned NumElems = MVT::getVectorNumElements(TVT); 4209 4210 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4211 default: assert(0 && "This action is not supported yet!"); 4212 case TargetLowering::Custom: { 4213 Vec = LegalizeOp(Vec); 4214 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4215 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4216 if (Tmp3.Val) 4217 return Tmp3; 4218 break; 4219 } 4220 case TargetLowering::Legal: 4221 if (isTypeLegal(TVT)) { 4222 Vec = LegalizeOp(Vec); 4223 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4224 return Op; 4225 } 4226 break; 4227 case TargetLowering::Expand: 4228 break; 4229 } 4230 4231 if (NumElems == 1) { 4232 // This must be an access of the only element. Return it. 4233 Op = ScalarizeVectorOp(Vec); 4234 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4235 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4236 SDOperand Lo, Hi; 4237 SplitVectorOp(Vec, Lo, Hi); 4238 if (CIdx->getValue() < NumElems/2) { 4239 Vec = Lo; 4240 } else { 4241 Vec = Hi; 4242 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, 4243 Idx.getValueType()); 4244 } 4245 4246 // It's now an extract from the appropriate high or low part. Recurse. 4247 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4248 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4249 } else { 4250 // Store the value to a temporary stack slot, then LOAD the scalar 4251 // element back out. 4252 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4253 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4254 4255 // Add the offset to the index. 4256 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 4257 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4258 DAG.getConstant(EltSize, Idx.getValueType())); 4259 4260 if (MVT::getSizeInBits(Idx.getValueType()) > 4261 MVT::getSizeInBits(TLI.getPointerTy())) 4262 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4263 else 4264 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4265 4266 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4267 4268 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4269 } 4270 return Op; 4271} 4272 4273/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4274/// we assume the operation can be split if it is not already legal. 4275SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4276 // We know that operand #0 is the Vec vector. For now we assume the index 4277 // is a constant and that the extracted result is a supported hardware type. 4278 SDOperand Vec = Op.getOperand(0); 4279 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4280 4281 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); 4282 4283 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 4284 // This must be an access of the desired vector length. Return it. 4285 return Vec; 4286 } 4287 4288 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4289 SDOperand Lo, Hi; 4290 SplitVectorOp(Vec, Lo, Hi); 4291 if (CIdx->getValue() < NumElems/2) { 4292 Vec = Lo; 4293 } else { 4294 Vec = Hi; 4295 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4296 } 4297 4298 // It's now an extract from the appropriate high or low part. Recurse. 4299 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4300 return ExpandEXTRACT_SUBVECTOR(Op); 4301} 4302 4303/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4304/// with condition CC on the current target. This usually involves legalizing 4305/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4306/// there may be no choice but to create a new SetCC node to represent the 4307/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4308/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4309void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4310 SDOperand &RHS, 4311 SDOperand &CC) { 4312 SDOperand Tmp1, Tmp2, Tmp3, Result; 4313 4314 switch (getTypeAction(LHS.getValueType())) { 4315 case Legal: 4316 Tmp1 = LegalizeOp(LHS); // LHS 4317 Tmp2 = LegalizeOp(RHS); // RHS 4318 break; 4319 case Promote: 4320 Tmp1 = PromoteOp(LHS); // LHS 4321 Tmp2 = PromoteOp(RHS); // RHS 4322 4323 // If this is an FP compare, the operands have already been extended. 4324 if (MVT::isInteger(LHS.getValueType())) { 4325 MVT::ValueType VT = LHS.getValueType(); 4326 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4327 4328 // Otherwise, we have to insert explicit sign or zero extends. Note 4329 // that we could insert sign extends for ALL conditions, but zero extend 4330 // is cheaper on many machines (an AND instead of two shifts), so prefer 4331 // it. 4332 switch (cast<CondCodeSDNode>(CC)->get()) { 4333 default: assert(0 && "Unknown integer comparison!"); 4334 case ISD::SETEQ: 4335 case ISD::SETNE: 4336 case ISD::SETUGE: 4337 case ISD::SETUGT: 4338 case ISD::SETULE: 4339 case ISD::SETULT: 4340 // ALL of these operations will work if we either sign or zero extend 4341 // the operands (including the unsigned comparisons!). Zero extend is 4342 // usually a simpler/cheaper operation, so prefer it. 4343 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4344 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4345 break; 4346 case ISD::SETGE: 4347 case ISD::SETGT: 4348 case ISD::SETLT: 4349 case ISD::SETLE: 4350 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4351 DAG.getValueType(VT)); 4352 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4353 DAG.getValueType(VT)); 4354 break; 4355 } 4356 } 4357 break; 4358 case Expand: { 4359 MVT::ValueType VT = LHS.getValueType(); 4360 if (VT == MVT::f32 || VT == MVT::f64) { 4361 // Expand into one or more soft-fp libcall(s). 4362 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4363 switch (cast<CondCodeSDNode>(CC)->get()) { 4364 case ISD::SETEQ: 4365 case ISD::SETOEQ: 4366 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4367 break; 4368 case ISD::SETNE: 4369 case ISD::SETUNE: 4370 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4371 break; 4372 case ISD::SETGE: 4373 case ISD::SETOGE: 4374 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4375 break; 4376 case ISD::SETLT: 4377 case ISD::SETOLT: 4378 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4379 break; 4380 case ISD::SETLE: 4381 case ISD::SETOLE: 4382 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4383 break; 4384 case ISD::SETGT: 4385 case ISD::SETOGT: 4386 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4387 break; 4388 case ISD::SETUO: 4389 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4390 break; 4391 case ISD::SETO: 4392 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4393 break; 4394 default: 4395 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4396 switch (cast<CondCodeSDNode>(CC)->get()) { 4397 case ISD::SETONE: 4398 // SETONE = SETOLT | SETOGT 4399 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4400 // Fallthrough 4401 case ISD::SETUGT: 4402 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4403 break; 4404 case ISD::SETUGE: 4405 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4406 break; 4407 case ISD::SETULT: 4408 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4409 break; 4410 case ISD::SETULE: 4411 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4412 break; 4413 case ISD::SETUEQ: 4414 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4415 break; 4416 default: assert(0 && "Unsupported FP setcc!"); 4417 } 4418 } 4419 4420 SDOperand Dummy; 4421 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 4422 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4423 false /*sign irrelevant*/, Dummy); 4424 Tmp2 = DAG.getConstant(0, MVT::i32); 4425 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4426 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4427 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 4428 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 4429 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4430 false /*sign irrelevant*/, Dummy); 4431 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 4432 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4433 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4434 Tmp2 = SDOperand(); 4435 } 4436 LHS = Tmp1; 4437 RHS = Tmp2; 4438 return; 4439 } 4440 4441 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4442 ExpandOp(LHS, LHSLo, LHSHi); 4443 ExpandOp(RHS, RHSLo, RHSHi); 4444 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4445 4446 if (VT==MVT::ppcf128) { 4447 // FIXME: This generated code sucks. We want to generate 4448 // FCMP crN, hi1, hi2 4449 // BNE crN, L: 4450 // FCMP crN, lo1, lo2 4451 // The following can be improved, but not that much. 4452 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4453 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode); 4454 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4455 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE); 4456 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode); 4457 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4458 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4459 Tmp2 = SDOperand(); 4460 break; 4461 } 4462 4463 switch (CCCode) { 4464 case ISD::SETEQ: 4465 case ISD::SETNE: 4466 if (RHSLo == RHSHi) 4467 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4468 if (RHSCST->isAllOnesValue()) { 4469 // Comparison to -1. 4470 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4471 Tmp2 = RHSLo; 4472 break; 4473 } 4474 4475 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4476 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4477 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4478 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4479 break; 4480 default: 4481 // If this is a comparison of the sign bit, just look at the top part. 4482 // X > -1, x < 0 4483 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4484 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4485 CST->getValue() == 0) || // X < 0 4486 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4487 CST->isAllOnesValue())) { // X > -1 4488 Tmp1 = LHSHi; 4489 Tmp2 = RHSHi; 4490 break; 4491 } 4492 4493 // FIXME: This generated code sucks. 4494 ISD::CondCode LowCC; 4495 switch (CCCode) { 4496 default: assert(0 && "Unknown integer setcc!"); 4497 case ISD::SETLT: 4498 case ISD::SETULT: LowCC = ISD::SETULT; break; 4499 case ISD::SETGT: 4500 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4501 case ISD::SETLE: 4502 case ISD::SETULE: LowCC = ISD::SETULE; break; 4503 case ISD::SETGE: 4504 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4505 } 4506 4507 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4508 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4509 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4510 4511 // NOTE: on targets without efficient SELECT of bools, we can always use 4512 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4513 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4514 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, 4515 false, DagCombineInfo); 4516 if (!Tmp1.Val) 4517 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 4518 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4519 CCCode, false, DagCombineInfo); 4520 if (!Tmp2.Val) 4521 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC); 4522 4523 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4524 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4525 if ((Tmp1C && Tmp1C->getValue() == 0) || 4526 (Tmp2C && Tmp2C->getValue() == 0 && 4527 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4528 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4529 (Tmp2C && Tmp2C->getValue() == 1 && 4530 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4531 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4532 // low part is known false, returns high part. 4533 // For LE / GE, if high part is known false, ignore the low part. 4534 // For LT / GT, if high part is known true, ignore the low part. 4535 Tmp1 = Tmp2; 4536 Tmp2 = SDOperand(); 4537 } else { 4538 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4539 ISD::SETEQ, false, DagCombineInfo); 4540 if (!Result.Val) 4541 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4542 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4543 Result, Tmp1, Tmp2)); 4544 Tmp1 = Result; 4545 Tmp2 = SDOperand(); 4546 } 4547 } 4548 } 4549 } 4550 LHS = Tmp1; 4551 RHS = Tmp2; 4552} 4553 4554/// EmitStackConvert - Emit a store/load combination to the stack. This stores 4555/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 4556/// a load from the stack slot to DestVT, extending it if needed. 4557/// The resultant code need not be legal. 4558SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, 4559 MVT::ValueType SlotVT, 4560 MVT::ValueType DestVT) { 4561 // Create the stack frame object. 4562 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); 4563 4564 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType()); 4565 unsigned SlotSize = MVT::getSizeInBits(SlotVT); 4566 unsigned DestSize = MVT::getSizeInBits(DestVT); 4567 4568 // Emit a store to the stack slot. Use a truncstore if the input value is 4569 // later than DestVT. 4570 SDOperand Store; 4571 if (SrcSize > SlotSize) 4572 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0,SlotVT); 4573 else { 4574 assert(SrcSize == SlotSize && "Invalid store"); 4575 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); 4576 } 4577 4578 // Result is a load from the stack slot. 4579 if (SlotSize == DestSize) 4580 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4581 4582 assert(SlotSize < DestSize && "Unknown extension!"); 4583 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT); 4584} 4585 4586SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4587 // Create a vector sized/aligned stack slot, store the value to element #0, 4588 // then load the whole vector back out. 4589 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4590 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4591 NULL, 0); 4592 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 4593} 4594 4595 4596/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4597/// support the operation, but do support the resultant vector type. 4598SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4599 4600 // If the only non-undef value is the low element, turn this into a 4601 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4602 unsigned NumElems = Node->getNumOperands(); 4603 bool isOnlyLowElement = true; 4604 SDOperand SplatValue = Node->getOperand(0); 4605 std::map<SDOperand, std::vector<unsigned> > Values; 4606 Values[SplatValue].push_back(0); 4607 bool isConstant = true; 4608 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4609 SplatValue.getOpcode() != ISD::UNDEF) 4610 isConstant = false; 4611 4612 for (unsigned i = 1; i < NumElems; ++i) { 4613 SDOperand V = Node->getOperand(i); 4614 Values[V].push_back(i); 4615 if (V.getOpcode() != ISD::UNDEF) 4616 isOnlyLowElement = false; 4617 if (SplatValue != V) 4618 SplatValue = SDOperand(0,0); 4619 4620 // If this isn't a constant element or an undef, we can't use a constant 4621 // pool load. 4622 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4623 V.getOpcode() != ISD::UNDEF) 4624 isConstant = false; 4625 } 4626 4627 if (isOnlyLowElement) { 4628 // If the low element is an undef too, then this whole things is an undef. 4629 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4630 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4631 // Otherwise, turn this into a scalar_to_vector node. 4632 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4633 Node->getOperand(0)); 4634 } 4635 4636 // If all elements are constants, create a load from the constant pool. 4637 if (isConstant) { 4638 MVT::ValueType VT = Node->getValueType(0); 4639 const Type *OpNTy = 4640 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 4641 std::vector<Constant*> CV; 4642 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4643 if (ConstantFPSDNode *V = 4644 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4645 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF())); 4646 } else if (ConstantSDNode *V = 4647 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4648 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 4649 } else { 4650 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4651 CV.push_back(UndefValue::get(OpNTy)); 4652 } 4653 } 4654 Constant *CP = ConstantVector::get(CV); 4655 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4656 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 4657 } 4658 4659 if (SplatValue.Val) { // Splat of one value? 4660 // Build the shuffle constant vector: <0, 0, 0, 0> 4661 MVT::ValueType MaskVT = 4662 MVT::getIntVectorWithNumElements(NumElems); 4663 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 4664 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4665 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4666 &ZeroVec[0], ZeroVec.size()); 4667 4668 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4669 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4670 // Get the splatted value into the low element of a vector register. 4671 SDOperand LowValVec = 4672 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4673 4674 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4675 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4676 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4677 SplatMask); 4678 } 4679 } 4680 4681 // If there are only two unique elements, we may be able to turn this into a 4682 // vector shuffle. 4683 if (Values.size() == 2) { 4684 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 4685 MVT::ValueType MaskVT = 4686 MVT::getIntVectorWithNumElements(NumElems); 4687 std::vector<SDOperand> MaskVec(NumElems); 4688 unsigned i = 0; 4689 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4690 E = Values.end(); I != E; ++I) { 4691 for (std::vector<unsigned>::iterator II = I->second.begin(), 4692 EE = I->second.end(); II != EE; ++II) 4693 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT)); 4694 i += NumElems; 4695 } 4696 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4697 &MaskVec[0], MaskVec.size()); 4698 4699 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4700 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 4701 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 4702 SmallVector<SDOperand, 8> Ops; 4703 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4704 E = Values.end(); I != E; ++I) { 4705 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4706 I->first); 4707 Ops.push_back(Op); 4708 } 4709 Ops.push_back(ShuffleMask); 4710 4711 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 4712 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 4713 &Ops[0], Ops.size()); 4714 } 4715 } 4716 4717 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 4718 // aligned object on the stack, store each element into it, then load 4719 // the result as a vector. 4720 MVT::ValueType VT = Node->getValueType(0); 4721 // Create the stack frame object. 4722 SDOperand FIPtr = DAG.CreateStackTemporary(VT); 4723 4724 // Emit a store of each element to the stack slot. 4725 SmallVector<SDOperand, 8> Stores; 4726 unsigned TypeByteSize = 4727 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 4728 // Store (in the right endianness) the elements to memory. 4729 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4730 // Ignore undef elements. 4731 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4732 4733 unsigned Offset = TypeByteSize*i; 4734 4735 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 4736 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 4737 4738 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 4739 NULL, 0)); 4740 } 4741 4742 SDOperand StoreChain; 4743 if (!Stores.empty()) // Not all undef elements? 4744 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4745 &Stores[0], Stores.size()); 4746 else 4747 StoreChain = DAG.getEntryNode(); 4748 4749 // Result is a load from the stack slot. 4750 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 4751} 4752 4753void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 4754 SDOperand Op, SDOperand Amt, 4755 SDOperand &Lo, SDOperand &Hi) { 4756 // Expand the subcomponents. 4757 SDOperand LHSL, LHSH; 4758 ExpandOp(Op, LHSL, LHSH); 4759 4760 SDOperand Ops[] = { LHSL, LHSH, Amt }; 4761 MVT::ValueType VT = LHSL.getValueType(); 4762 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 4763 Hi = Lo.getValue(1); 4764} 4765 4766 4767/// ExpandShift - Try to find a clever way to expand this shift operation out to 4768/// smaller elements. If we can't find a way that is more efficient than a 4769/// libcall on this target, return false. Otherwise, return true with the 4770/// low-parts expanded into Lo and Hi. 4771bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 4772 SDOperand &Lo, SDOperand &Hi) { 4773 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 4774 "This is not a shift!"); 4775 4776 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 4777 SDOperand ShAmt = LegalizeOp(Amt); 4778 MVT::ValueType ShTy = ShAmt.getValueType(); 4779 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 4780 unsigned NVTBits = MVT::getSizeInBits(NVT); 4781 4782 // Handle the case when Amt is an immediate. 4783 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 4784 unsigned Cst = CN->getValue(); 4785 // Expand the incoming operand to be shifted, so that we have its parts 4786 SDOperand InL, InH; 4787 ExpandOp(Op, InL, InH); 4788 switch(Opc) { 4789 case ISD::SHL: 4790 if (Cst > VTBits) { 4791 Lo = DAG.getConstant(0, NVT); 4792 Hi = DAG.getConstant(0, NVT); 4793 } else if (Cst > NVTBits) { 4794 Lo = DAG.getConstant(0, NVT); 4795 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 4796 } else if (Cst == NVTBits) { 4797 Lo = DAG.getConstant(0, NVT); 4798 Hi = InL; 4799 } else { 4800 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 4801 Hi = DAG.getNode(ISD::OR, NVT, 4802 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 4803 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 4804 } 4805 return true; 4806 case ISD::SRL: 4807 if (Cst > VTBits) { 4808 Lo = DAG.getConstant(0, NVT); 4809 Hi = DAG.getConstant(0, NVT); 4810 } else if (Cst > NVTBits) { 4811 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 4812 Hi = DAG.getConstant(0, NVT); 4813 } else if (Cst == NVTBits) { 4814 Lo = InH; 4815 Hi = DAG.getConstant(0, NVT); 4816 } else { 4817 Lo = DAG.getNode(ISD::OR, NVT, 4818 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4819 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4820 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 4821 } 4822 return true; 4823 case ISD::SRA: 4824 if (Cst > VTBits) { 4825 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 4826 DAG.getConstant(NVTBits-1, ShTy)); 4827 } else if (Cst > NVTBits) { 4828 Lo = DAG.getNode(ISD::SRA, NVT, InH, 4829 DAG.getConstant(Cst-NVTBits, ShTy)); 4830 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4831 DAG.getConstant(NVTBits-1, ShTy)); 4832 } else if (Cst == NVTBits) { 4833 Lo = InH; 4834 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4835 DAG.getConstant(NVTBits-1, ShTy)); 4836 } else { 4837 Lo = DAG.getNode(ISD::OR, NVT, 4838 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4839 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4840 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 4841 } 4842 return true; 4843 } 4844 } 4845 4846 // Okay, the shift amount isn't constant. However, if we can tell that it is 4847 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 4848 uint64_t Mask = NVTBits, KnownZero, KnownOne; 4849 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 4850 4851 // If we know that the high bit of the shift amount is one, then we can do 4852 // this as a couple of simple shifts. 4853 if (KnownOne & Mask) { 4854 // Mask out the high bit, which we know is set. 4855 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 4856 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4857 4858 // Expand the incoming operand to be shifted, so that we have its parts 4859 SDOperand InL, InH; 4860 ExpandOp(Op, InL, InH); 4861 switch(Opc) { 4862 case ISD::SHL: 4863 Lo = DAG.getConstant(0, NVT); // Low part is zero. 4864 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 4865 return true; 4866 case ISD::SRL: 4867 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 4868 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 4869 return true; 4870 case ISD::SRA: 4871 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 4872 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4873 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 4874 return true; 4875 } 4876 } 4877 4878 // If we know that the high bit of the shift amount is zero, then we can do 4879 // this as a couple of simple shifts. 4880 if (KnownZero & Mask) { 4881 // Compute 32-amt. 4882 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 4883 DAG.getConstant(NVTBits, Amt.getValueType()), 4884 Amt); 4885 4886 // Expand the incoming operand to be shifted, so that we have its parts 4887 SDOperand InL, InH; 4888 ExpandOp(Op, InL, InH); 4889 switch(Opc) { 4890 case ISD::SHL: 4891 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 4892 Hi = DAG.getNode(ISD::OR, NVT, 4893 DAG.getNode(ISD::SHL, NVT, InH, Amt), 4894 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 4895 return true; 4896 case ISD::SRL: 4897 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 4898 Lo = DAG.getNode(ISD::OR, NVT, 4899 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4900 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4901 return true; 4902 case ISD::SRA: 4903 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 4904 Lo = DAG.getNode(ISD::OR, NVT, 4905 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4906 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4907 return true; 4908 } 4909 } 4910 4911 return false; 4912} 4913 4914 4915// ExpandLibCall - Expand a node into a call to a libcall. If the result value 4916// does not fit into a register, return the lo part and set the hi part to the 4917// by-reg argument. If it does fit into a single register, return the result 4918// and leave the Hi part unset. 4919SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 4920 bool isSigned, SDOperand &Hi) { 4921 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 4922 // The input chain to this libcall is the entry node of the function. 4923 // Legalizing the call will automatically add the previous call to the 4924 // dependence. 4925 SDOperand InChain = DAG.getEntryNode(); 4926 4927 TargetLowering::ArgListTy Args; 4928 TargetLowering::ArgListEntry Entry; 4929 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4930 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 4931 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 4932 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 4933 Entry.isSExt = isSigned; 4934 Args.push_back(Entry); 4935 } 4936 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 4937 4938 // Splice the libcall in wherever FindInputOutputChains tells us to. 4939 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 4940 std::pair<SDOperand,SDOperand> CallInfo = 4941 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false, 4942 Callee, Args, DAG); 4943 4944 // Legalize the call sequence, starting with the chain. This will advance 4945 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 4946 // was added by LowerCallTo (guaranteeing proper serialization of calls). 4947 LegalizeOp(CallInfo.second); 4948 SDOperand Result; 4949 switch (getTypeAction(CallInfo.first.getValueType())) { 4950 default: assert(0 && "Unknown thing"); 4951 case Legal: 4952 Result = CallInfo.first; 4953 break; 4954 case Expand: 4955 ExpandOp(CallInfo.first, Result, Hi); 4956 break; 4957 } 4958 return Result; 4959} 4960 4961 4962/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 4963/// 4964SDOperand SelectionDAGLegalize:: 4965ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 4966 assert(getTypeAction(Source.getValueType()) == Expand && 4967 "This is not an expansion!"); 4968 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 4969 4970 if (!isSigned) { 4971 assert(Source.getValueType() == MVT::i64 && 4972 "This only works for 64-bit -> FP"); 4973 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 4974 // incoming integer is set. To handle this, we dynamically test to see if 4975 // it is set, and, if so, add a fudge factor. 4976 SDOperand Lo, Hi; 4977 ExpandOp(Source, Lo, Hi); 4978 4979 // If this is unsigned, and not supported, first perform the conversion to 4980 // signed, then adjust the result if the sign bit is set. 4981 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 4982 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 4983 4984 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 4985 DAG.getConstant(0, Hi.getValueType()), 4986 ISD::SETLT); 4987 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 4988 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4989 SignSet, Four, Zero); 4990 uint64_t FF = 0x5f800000ULL; 4991 if (TLI.isLittleEndian()) FF <<= 32; 4992 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4993 4994 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4995 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4996 SDOperand FudgeInReg; 4997 if (DestTy == MVT::f32) 4998 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4999 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) 5000 // FIXME: Avoid the extend by construction the right constantpool? 5001 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5002 CPIdx, NULL, 0, MVT::f32); 5003 else 5004 assert(0 && "Unexpected conversion"); 5005 5006 MVT::ValueType SCVT = SignedConv.getValueType(); 5007 if (SCVT != DestTy) { 5008 // Destination type needs to be expanded as well. The FADD now we are 5009 // constructing will be expanded into a libcall. 5010 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 5011 assert(SCVT == MVT::i32 && DestTy == MVT::f64); 5012 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, 5013 SignedConv, SignedConv.getValue(1)); 5014 } 5015 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5016 } 5017 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5018 } 5019 5020 // Check to see if the target has a custom way to lower this. If so, use it. 5021 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 5022 default: assert(0 && "This action not implemented for this operation!"); 5023 case TargetLowering::Legal: 5024 case TargetLowering::Expand: 5025 break; // This case is handled below. 5026 case TargetLowering::Custom: { 5027 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5028 Source), DAG); 5029 if (NV.Val) 5030 return LegalizeOp(NV); 5031 break; // The target decided this was legal after all 5032 } 5033 } 5034 5035 // Expand the source, then glue it back together for the call. We must expand 5036 // the source in case it is shared (this pass of legalize must traverse it). 5037 SDOperand SrcLo, SrcHi; 5038 ExpandOp(Source, SrcLo, SrcHi); 5039 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 5040 5041 RTLIB::Libcall LC; 5042 if (DestTy == MVT::f32) 5043 LC = RTLIB::SINTTOFP_I64_F32; 5044 else { 5045 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 5046 LC = RTLIB::SINTTOFP_I64_F64; 5047 } 5048 5049 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 5050 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5051 SDOperand UnusedHiPart; 5052 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 5053 UnusedHiPart); 5054} 5055 5056/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5057/// INT_TO_FP operation of the specified operand when the target requests that 5058/// we expand it. At this point, we know that the result and operand types are 5059/// legal for the target. 5060SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5061 SDOperand Op0, 5062 MVT::ValueType DestVT) { 5063 if (Op0.getValueType() == MVT::i32) { 5064 // simple 32-bit [signed|unsigned] integer to float/double expansion 5065 5066 // Get the stack frame index of a 8 byte buffer. 5067 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64); 5068 5069 // word offset constant for Hi/Lo address computation 5070 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5071 // set up Hi and Lo (into buffer) address based on endian 5072 SDOperand Hi = StackSlot; 5073 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5074 if (TLI.isLittleEndian()) 5075 std::swap(Hi, Lo); 5076 5077 // if signed map to unsigned space 5078 SDOperand Op0Mapped; 5079 if (isSigned) { 5080 // constant used to invert sign bit (signed to unsigned mapping) 5081 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5082 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5083 } else { 5084 Op0Mapped = Op0; 5085 } 5086 // store the lo of the constructed double - based on integer input 5087 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 5088 Op0Mapped, Lo, NULL, 0); 5089 // initial hi portion of constructed double 5090 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5091 // store the hi of the constructed double - biased exponent 5092 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5093 // load the constructed double 5094 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5095 // FP constant to bias correct the final result 5096 SDOperand Bias = DAG.getConstantFP(isSigned ? 5097 BitsToDouble(0x4330000080000000ULL) 5098 : BitsToDouble(0x4330000000000000ULL), 5099 MVT::f64); 5100 // subtract the bias 5101 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5102 // final result 5103 SDOperand Result; 5104 // handle final rounding 5105 if (DestVT == MVT::f64) { 5106 // do nothing 5107 Result = Sub; 5108 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { 5109 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 5110 DAG.getIntPtrConstant(0)); 5111 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { 5112 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5113 } 5114 return Result; 5115 } 5116 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5117 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5118 5119 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 5120 DAG.getConstant(0, Op0.getValueType()), 5121 ISD::SETLT); 5122 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5123 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5124 SignSet, Four, Zero); 5125 5126 // If the sign bit of the integer is set, the large number will be treated 5127 // as a negative number. To counteract this, the dynamic code adds an 5128 // offset depending on the data type. 5129 uint64_t FF; 5130 switch (Op0.getValueType()) { 5131 default: assert(0 && "Unsupported integer type!"); 5132 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5133 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5134 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5135 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5136 } 5137 if (TLI.isLittleEndian()) FF <<= 32; 5138 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5139 5140 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5141 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5142 SDOperand FudgeInReg; 5143 if (DestVT == MVT::f32) 5144 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 5145 else { 5146 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5147 DAG.getEntryNode(), CPIdx, 5148 NULL, 0, MVT::f32)); 5149 } 5150 5151 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5152} 5153 5154/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5155/// *INT_TO_FP operation of the specified operand when the target requests that 5156/// we promote it. At this point, we know that the result and operand types are 5157/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5158/// operation that takes a larger input. 5159SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5160 MVT::ValueType DestVT, 5161 bool isSigned) { 5162 // First step, figure out the appropriate *INT_TO_FP operation to use. 5163 MVT::ValueType NewInTy = LegalOp.getValueType(); 5164 5165 unsigned OpToUse = 0; 5166 5167 // Scan for the appropriate larger type to use. 5168 while (1) { 5169 NewInTy = (MVT::ValueType)(NewInTy+1); 5170 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 5171 5172 // If the target supports SINT_TO_FP of this type, use it. 5173 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5174 default: break; 5175 case TargetLowering::Legal: 5176 if (!TLI.isTypeLegal(NewInTy)) 5177 break; // Can't use this datatype. 5178 // FALL THROUGH. 5179 case TargetLowering::Custom: 5180 OpToUse = ISD::SINT_TO_FP; 5181 break; 5182 } 5183 if (OpToUse) break; 5184 if (isSigned) continue; 5185 5186 // If the target supports UINT_TO_FP of this type, use it. 5187 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5188 default: break; 5189 case TargetLowering::Legal: 5190 if (!TLI.isTypeLegal(NewInTy)) 5191 break; // Can't use this datatype. 5192 // FALL THROUGH. 5193 case TargetLowering::Custom: 5194 OpToUse = ISD::UINT_TO_FP; 5195 break; 5196 } 5197 if (OpToUse) break; 5198 5199 // Otherwise, try a larger type. 5200 } 5201 5202 // Okay, we found the operation and type to use. Zero extend our input to the 5203 // desired type then run the operation on it. 5204 return DAG.getNode(OpToUse, DestVT, 5205 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5206 NewInTy, LegalOp)); 5207} 5208 5209/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5210/// FP_TO_*INT operation of the specified operand when the target requests that 5211/// we promote it. At this point, we know that the result and operand types are 5212/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5213/// operation that returns a larger result. 5214SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5215 MVT::ValueType DestVT, 5216 bool isSigned) { 5217 // First step, figure out the appropriate FP_TO*INT operation to use. 5218 MVT::ValueType NewOutTy = DestVT; 5219 5220 unsigned OpToUse = 0; 5221 5222 // Scan for the appropriate larger type to use. 5223 while (1) { 5224 NewOutTy = (MVT::ValueType)(NewOutTy+1); 5225 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 5226 5227 // If the target supports FP_TO_SINT returning this type, use it. 5228 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5229 default: break; 5230 case TargetLowering::Legal: 5231 if (!TLI.isTypeLegal(NewOutTy)) 5232 break; // Can't use this datatype. 5233 // FALL THROUGH. 5234 case TargetLowering::Custom: 5235 OpToUse = ISD::FP_TO_SINT; 5236 break; 5237 } 5238 if (OpToUse) break; 5239 5240 // If the target supports FP_TO_UINT of this type, use it. 5241 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5242 default: break; 5243 case TargetLowering::Legal: 5244 if (!TLI.isTypeLegal(NewOutTy)) 5245 break; // Can't use this datatype. 5246 // FALL THROUGH. 5247 case TargetLowering::Custom: 5248 OpToUse = ISD::FP_TO_UINT; 5249 break; 5250 } 5251 if (OpToUse) break; 5252 5253 // Otherwise, try a larger type. 5254 } 5255 5256 5257 // Okay, we found the operation and type to use. 5258 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5259 5260 // If the operation produces an invalid type, it must be custom lowered. Use 5261 // the target lowering hooks to expand it. Just keep the low part of the 5262 // expanded operation, we know that we're truncating anyway. 5263 if (getTypeAction(NewOutTy) == Expand) { 5264 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0); 5265 assert(Operation.Val && "Didn't return anything"); 5266 } 5267 5268 // Truncate the result of the extended FP_TO_*INT operation to the desired 5269 // size. 5270 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5271} 5272 5273/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5274/// 5275SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5276 MVT::ValueType VT = Op.getValueType(); 5277 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 5278 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5279 switch (VT) { 5280 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5281 case MVT::i16: 5282 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5283 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5284 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5285 case MVT::i32: 5286 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5287 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5288 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5289 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5290 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5291 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5292 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5293 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5294 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5295 case MVT::i64: 5296 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5297 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5298 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5299 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5300 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5301 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5302 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5303 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5304 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5305 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5306 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5307 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5308 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5309 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5310 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5311 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5312 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5313 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5314 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5315 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5316 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5317 } 5318} 5319 5320/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5321/// 5322SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5323 switch (Opc) { 5324 default: assert(0 && "Cannot expand this yet!"); 5325 case ISD::CTPOP: { 5326 static const uint64_t mask[6] = { 5327 0x5555555555555555ULL, 0x3333333333333333ULL, 5328 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5329 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5330 }; 5331 MVT::ValueType VT = Op.getValueType(); 5332 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5333 unsigned len = MVT::getSizeInBits(VT); 5334 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5335 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5336 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5337 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5338 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5339 DAG.getNode(ISD::AND, VT, 5340 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5341 } 5342 return Op; 5343 } 5344 case ISD::CTLZ: { 5345 // for now, we do this: 5346 // x = x | (x >> 1); 5347 // x = x | (x >> 2); 5348 // ... 5349 // x = x | (x >>16); 5350 // x = x | (x >>32); // for 64-bit input 5351 // return popcount(~x); 5352 // 5353 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5354 MVT::ValueType VT = Op.getValueType(); 5355 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5356 unsigned len = MVT::getSizeInBits(VT); 5357 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5358 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5359 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5360 } 5361 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5362 return DAG.getNode(ISD::CTPOP, VT, Op); 5363 } 5364 case ISD::CTTZ: { 5365 // for now, we use: { return popcount(~x & (x - 1)); } 5366 // unless the target has ctlz but not ctpop, in which case we use: 5367 // { return 32 - nlz(~x & (x-1)); } 5368 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5369 MVT::ValueType VT = Op.getValueType(); 5370 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5371 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5372 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5373 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5374 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5375 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5376 TLI.isOperationLegal(ISD::CTLZ, VT)) 5377 return DAG.getNode(ISD::SUB, VT, 5378 DAG.getConstant(MVT::getSizeInBits(VT), VT), 5379 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5380 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5381 } 5382 } 5383} 5384 5385/// ExpandOp - Expand the specified SDOperand into its two component pieces 5386/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5387/// LegalizeNodes map is filled in for any results that are not expanded, the 5388/// ExpandedNodes map is filled in for any results that are expanded, and the 5389/// Lo/Hi values are returned. 5390void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5391 MVT::ValueType VT = Op.getValueType(); 5392 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 5393 SDNode *Node = Op.Val; 5394 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5395 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 5396 MVT::isVector(VT)) && 5397 "Cannot expand to FP value or to larger int value!"); 5398 5399 // See if we already expanded it. 5400 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5401 = ExpandedNodes.find(Op); 5402 if (I != ExpandedNodes.end()) { 5403 Lo = I->second.first; 5404 Hi = I->second.second; 5405 return; 5406 } 5407 5408 switch (Node->getOpcode()) { 5409 case ISD::CopyFromReg: 5410 assert(0 && "CopyFromReg must be legal!"); 5411 case ISD::FP_ROUND_INREG: 5412 if (VT == MVT::ppcf128 && 5413 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5414 TargetLowering::Custom) { 5415 SDOperand SrcLo, SrcHi, Src; 5416 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5417 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5418 SDOperand Result = TLI.LowerOperation( 5419 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5420 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5421 Lo = Result.Val->getOperand(0); 5422 Hi = Result.Val->getOperand(1); 5423 break; 5424 } 5425 // fall through 5426 default: 5427#ifndef NDEBUG 5428 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5429#endif 5430 assert(0 && "Do not know how to expand this operator!"); 5431 abort(); 5432 case ISD::EXTRACT_VECTOR_ELT: 5433 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5434 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5435 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5436 return ExpandOp(Lo, Lo, Hi); 5437 case ISD::UNDEF: 5438 NVT = TLI.getTypeToExpandTo(VT); 5439 Lo = DAG.getNode(ISD::UNDEF, NVT); 5440 Hi = DAG.getNode(ISD::UNDEF, NVT); 5441 break; 5442 case ISD::Constant: { 5443 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 5444 Lo = DAG.getConstant(Cst, NVT); 5445 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 5446 break; 5447 } 5448 case ISD::ConstantFP: { 5449 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5450 if (CFP->getValueType(0) == MVT::ppcf128) { 5451 APInt api = CFP->getValueAPF().convertToAPInt(); 5452 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5453 MVT::f64); 5454 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5455 MVT::f64); 5456 break; 5457 } 5458 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5459 if (getTypeAction(Lo.getValueType()) == Expand) 5460 ExpandOp(Lo, Lo, Hi); 5461 break; 5462 } 5463 case ISD::BUILD_PAIR: 5464 // Return the operands. 5465 Lo = Node->getOperand(0); 5466 Hi = Node->getOperand(1); 5467 break; 5468 5469 case ISD::MERGE_VALUES: 5470 if (Node->getNumValues() == 1) { 5471 ExpandOp(Op.getOperand(0), Lo, Hi); 5472 break; 5473 } 5474 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5475 assert(Op.ResNo == 0 && Node->getNumValues() == 2 && 5476 Op.getValue(1).getValueType() == MVT::Other && 5477 "unhandled MERGE_VALUES"); 5478 ExpandOp(Op.getOperand(0), Lo, Hi); 5479 // Remember that we legalized the chain. 5480 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5481 break; 5482 5483 case ISD::SIGN_EXTEND_INREG: 5484 ExpandOp(Node->getOperand(0), Lo, Hi); 5485 // sext_inreg the low part if needed. 5486 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5487 5488 // The high part gets the sign extension from the lo-part. This handles 5489 // things like sextinreg V:i64 from i8. 5490 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5491 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 5492 TLI.getShiftAmountTy())); 5493 break; 5494 5495 case ISD::BSWAP: { 5496 ExpandOp(Node->getOperand(0), Lo, Hi); 5497 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5498 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5499 Lo = TempLo; 5500 break; 5501 } 5502 5503 case ISD::CTPOP: 5504 ExpandOp(Node->getOperand(0), Lo, Hi); 5505 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5506 DAG.getNode(ISD::CTPOP, NVT, Lo), 5507 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5508 Hi = DAG.getConstant(0, NVT); 5509 break; 5510 5511 case ISD::CTLZ: { 5512 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5513 ExpandOp(Node->getOperand(0), Lo, Hi); 5514 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5515 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5516 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 5517 ISD::SETNE); 5518 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5519 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5520 5521 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5522 Hi = DAG.getConstant(0, NVT); 5523 break; 5524 } 5525 5526 case ISD::CTTZ: { 5527 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5528 ExpandOp(Node->getOperand(0), Lo, Hi); 5529 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5530 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5531 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 5532 ISD::SETNE); 5533 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5534 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5535 5536 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5537 Hi = DAG.getConstant(0, NVT); 5538 break; 5539 } 5540 5541 case ISD::VAARG: { 5542 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5543 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5544 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5545 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5546 5547 // Remember that we legalized the chain. 5548 Hi = LegalizeOp(Hi); 5549 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5550 if (!TLI.isLittleEndian()) 5551 std::swap(Lo, Hi); 5552 break; 5553 } 5554 5555 case ISD::LOAD: { 5556 LoadSDNode *LD = cast<LoadSDNode>(Node); 5557 SDOperand Ch = LD->getChain(); // Legalize the chain. 5558 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5559 ISD::LoadExtType ExtType = LD->getExtensionType(); 5560 int SVOffset = LD->getSrcValueOffset(); 5561 unsigned Alignment = LD->getAlignment(); 5562 bool isVolatile = LD->isVolatile(); 5563 5564 if (ExtType == ISD::NON_EXTLOAD) { 5565 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5566 isVolatile, Alignment); 5567 if (VT == MVT::f32 || VT == MVT::f64) { 5568 // f32->i32 or f64->i64 one to one expansion. 5569 // Remember that we legalized the chain. 5570 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5571 // Recursively expand the new load. 5572 if (getTypeAction(NVT) == Expand) 5573 ExpandOp(Lo, Lo, Hi); 5574 break; 5575 } 5576 5577 // Increment the pointer to the other half. 5578 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 5579 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5580 DAG.getIntPtrConstant(IncrementSize)); 5581 SVOffset += IncrementSize; 5582 Alignment = MinAlign(Alignment, IncrementSize); 5583 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5584 isVolatile, Alignment); 5585 5586 // Build a factor node to remember that this load is independent of the 5587 // other one. 5588 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5589 Hi.getValue(1)); 5590 5591 // Remember that we legalized the chain. 5592 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5593 if (!TLI.isLittleEndian()) 5594 std::swap(Lo, Hi); 5595 } else { 5596 MVT::ValueType EVT = LD->getLoadedVT(); 5597 5598 if ((VT == MVT::f64 && EVT == MVT::f32) || 5599 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 5600 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5601 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5602 SVOffset, isVolatile, Alignment); 5603 // Remember that we legalized the chain. 5604 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 5605 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 5606 break; 5607 } 5608 5609 if (EVT == NVT) 5610 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 5611 SVOffset, isVolatile, Alignment); 5612 else 5613 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 5614 SVOffset, EVT, isVolatile, 5615 Alignment); 5616 5617 // Remember that we legalized the chain. 5618 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5619 5620 if (ExtType == ISD::SEXTLOAD) { 5621 // The high part is obtained by SRA'ing all but one of the bits of the 5622 // lo part. 5623 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5624 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5625 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5626 } else if (ExtType == ISD::ZEXTLOAD) { 5627 // The high part is just a zero. 5628 Hi = DAG.getConstant(0, NVT); 5629 } else /* if (ExtType == ISD::EXTLOAD) */ { 5630 // The high part is undefined. 5631 Hi = DAG.getNode(ISD::UNDEF, NVT); 5632 } 5633 } 5634 break; 5635 } 5636 case ISD::AND: 5637 case ISD::OR: 5638 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 5639 SDOperand LL, LH, RL, RH; 5640 ExpandOp(Node->getOperand(0), LL, LH); 5641 ExpandOp(Node->getOperand(1), RL, RH); 5642 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 5643 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 5644 break; 5645 } 5646 case ISD::SELECT: { 5647 SDOperand LL, LH, RL, RH; 5648 ExpandOp(Node->getOperand(1), LL, LH); 5649 ExpandOp(Node->getOperand(2), RL, RH); 5650 if (getTypeAction(NVT) == Expand) 5651 NVT = TLI.getTypeToExpandTo(NVT); 5652 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 5653 if (VT != MVT::f32) 5654 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 5655 break; 5656 } 5657 case ISD::SELECT_CC: { 5658 SDOperand TL, TH, FL, FH; 5659 ExpandOp(Node->getOperand(2), TL, TH); 5660 ExpandOp(Node->getOperand(3), FL, FH); 5661 if (getTypeAction(NVT) == Expand) 5662 NVT = TLI.getTypeToExpandTo(NVT); 5663 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5664 Node->getOperand(1), TL, FL, Node->getOperand(4)); 5665 if (VT != MVT::f32) 5666 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5667 Node->getOperand(1), TH, FH, Node->getOperand(4)); 5668 break; 5669 } 5670 case ISD::ANY_EXTEND: 5671 // The low part is any extension of the input (which degenerates to a copy). 5672 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 5673 // The high part is undefined. 5674 Hi = DAG.getNode(ISD::UNDEF, NVT); 5675 break; 5676 case ISD::SIGN_EXTEND: { 5677 // The low part is just a sign extension of the input (which degenerates to 5678 // a copy). 5679 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 5680 5681 // The high part is obtained by SRA'ing all but one of the bits of the lo 5682 // part. 5683 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5684 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5685 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5686 break; 5687 } 5688 case ISD::ZERO_EXTEND: 5689 // The low part is just a zero extension of the input (which degenerates to 5690 // a copy). 5691 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 5692 5693 // The high part is just a zero. 5694 Hi = DAG.getConstant(0, NVT); 5695 break; 5696 5697 case ISD::TRUNCATE: { 5698 // The input value must be larger than this value. Expand *it*. 5699 SDOperand NewLo; 5700 ExpandOp(Node->getOperand(0), NewLo, Hi); 5701 5702 // The low part is now either the right size, or it is closer. If not the 5703 // right size, make an illegal truncate so we recursively expand it. 5704 if (NewLo.getValueType() != Node->getValueType(0)) 5705 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 5706 ExpandOp(NewLo, Lo, Hi); 5707 break; 5708 } 5709 5710 case ISD::BIT_CONVERT: { 5711 SDOperand Tmp; 5712 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 5713 // If the target wants to, allow it to lower this itself. 5714 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5715 case Expand: assert(0 && "cannot expand FP!"); 5716 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 5717 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 5718 } 5719 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 5720 } 5721 5722 // f32 / f64 must be expanded to i32 / i64. 5723 if (VT == MVT::f32 || VT == MVT::f64) { 5724 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5725 if (getTypeAction(NVT) == Expand) 5726 ExpandOp(Lo, Lo, Hi); 5727 break; 5728 } 5729 5730 // If source operand will be expanded to the same type as VT, i.e. 5731 // i64 <- f64, i32 <- f32, expand the source operand instead. 5732 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 5733 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 5734 ExpandOp(Node->getOperand(0), Lo, Hi); 5735 break; 5736 } 5737 5738 // Turn this into a load/store pair by default. 5739 if (Tmp.Val == 0) 5740 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 5741 5742 ExpandOp(Tmp, Lo, Hi); 5743 break; 5744 } 5745 5746 case ISD::READCYCLECOUNTER: { 5747 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 5748 TargetLowering::Custom && 5749 "Must custom expand ReadCycleCounter"); 5750 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 5751 assert(Tmp.Val && "Node must be custom expanded!"); 5752 ExpandOp(Tmp.getValue(0), Lo, Hi); 5753 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 5754 LegalizeOp(Tmp.getValue(1))); 5755 break; 5756 } 5757 5758 // These operators cannot be expanded directly, emit them as calls to 5759 // library functions. 5760 case ISD::FP_TO_SINT: { 5761 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 5762 SDOperand Op; 5763 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5764 case Expand: assert(0 && "cannot expand FP!"); 5765 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5766 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5767 } 5768 5769 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 5770 5771 // Now that the custom expander is done, expand the result, which is still 5772 // VT. 5773 if (Op.Val) { 5774 ExpandOp(Op, Lo, Hi); 5775 break; 5776 } 5777 } 5778 5779 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5780 if (Node->getOperand(0).getValueType() == MVT::f32) 5781 LC = RTLIB::FPTOSINT_F32_I64; 5782 else if (Node->getOperand(0).getValueType() == MVT::f64) 5783 LC = RTLIB::FPTOSINT_F64_I64; 5784 else if (Node->getOperand(0).getValueType() == MVT::f80) 5785 LC = RTLIB::FPTOSINT_F80_I64; 5786 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 5787 LC = RTLIB::FPTOSINT_PPCF128_I64; 5788 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5789 false/*sign irrelevant*/, Hi); 5790 break; 5791 } 5792 5793 case ISD::FP_TO_UINT: { 5794 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 5795 SDOperand Op; 5796 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5797 case Expand: assert(0 && "cannot expand FP!"); 5798 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5799 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5800 } 5801 5802 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 5803 5804 // Now that the custom expander is done, expand the result. 5805 if (Op.Val) { 5806 ExpandOp(Op, Lo, Hi); 5807 break; 5808 } 5809 } 5810 5811 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5812 if (Node->getOperand(0).getValueType() == MVT::f32) 5813 LC = RTLIB::FPTOUINT_F32_I64; 5814 else if (Node->getOperand(0).getValueType() == MVT::f64) 5815 LC = RTLIB::FPTOUINT_F64_I64; 5816 else if (Node->getOperand(0).getValueType() == MVT::f80) 5817 LC = RTLIB::FPTOUINT_F80_I64; 5818 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 5819 LC = RTLIB::FPTOUINT_PPCF128_I64; 5820 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5821 false/*sign irrelevant*/, Hi); 5822 break; 5823 } 5824 5825 case ISD::SHL: { 5826 // If the target wants custom lowering, do so. 5827 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5828 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 5829 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 5830 Op = TLI.LowerOperation(Op, DAG); 5831 if (Op.Val) { 5832 // Now that the custom expander is done, expand the result, which is 5833 // still VT. 5834 ExpandOp(Op, Lo, Hi); 5835 break; 5836 } 5837 } 5838 5839 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 5840 // this X << 1 as X+X. 5841 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 5842 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 5843 TLI.isOperationLegal(ISD::ADDE, NVT)) { 5844 SDOperand LoOps[2], HiOps[3]; 5845 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 5846 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 5847 LoOps[1] = LoOps[0]; 5848 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5849 5850 HiOps[1] = HiOps[0]; 5851 HiOps[2] = Lo.getValue(1); 5852 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5853 break; 5854 } 5855 } 5856 5857 // If we can emit an efficient shift operation, do so now. 5858 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5859 break; 5860 5861 // If this target supports SHL_PARTS, use it. 5862 TargetLowering::LegalizeAction Action = 5863 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 5864 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5865 Action == TargetLowering::Custom) { 5866 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5867 break; 5868 } 5869 5870 // Otherwise, emit a libcall. 5871 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 5872 false/*left shift=unsigned*/, Hi); 5873 break; 5874 } 5875 5876 case ISD::SRA: { 5877 // If the target wants custom lowering, do so. 5878 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5879 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 5880 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 5881 Op = TLI.LowerOperation(Op, DAG); 5882 if (Op.Val) { 5883 // Now that the custom expander is done, expand the result, which is 5884 // still VT. 5885 ExpandOp(Op, Lo, Hi); 5886 break; 5887 } 5888 } 5889 5890 // If we can emit an efficient shift operation, do so now. 5891 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5892 break; 5893 5894 // If this target supports SRA_PARTS, use it. 5895 TargetLowering::LegalizeAction Action = 5896 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 5897 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5898 Action == TargetLowering::Custom) { 5899 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5900 break; 5901 } 5902 5903 // Otherwise, emit a libcall. 5904 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 5905 true/*ashr is signed*/, Hi); 5906 break; 5907 } 5908 5909 case ISD::SRL: { 5910 // If the target wants custom lowering, do so. 5911 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5912 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 5913 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 5914 Op = TLI.LowerOperation(Op, DAG); 5915 if (Op.Val) { 5916 // Now that the custom expander is done, expand the result, which is 5917 // still VT. 5918 ExpandOp(Op, Lo, Hi); 5919 break; 5920 } 5921 } 5922 5923 // If we can emit an efficient shift operation, do so now. 5924 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5925 break; 5926 5927 // If this target supports SRL_PARTS, use it. 5928 TargetLowering::LegalizeAction Action = 5929 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 5930 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5931 Action == TargetLowering::Custom) { 5932 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5933 break; 5934 } 5935 5936 // Otherwise, emit a libcall. 5937 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 5938 false/*lshr is unsigned*/, Hi); 5939 break; 5940 } 5941 5942 case ISD::ADD: 5943 case ISD::SUB: { 5944 // If the target wants to custom expand this, let them. 5945 if (TLI.getOperationAction(Node->getOpcode(), VT) == 5946 TargetLowering::Custom) { 5947 Op = TLI.LowerOperation(Op, DAG); 5948 if (Op.Val) { 5949 ExpandOp(Op, Lo, Hi); 5950 break; 5951 } 5952 } 5953 5954 // Expand the subcomponents. 5955 SDOperand LHSL, LHSH, RHSL, RHSH; 5956 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5957 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5958 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5959 SDOperand LoOps[2], HiOps[3]; 5960 LoOps[0] = LHSL; 5961 LoOps[1] = RHSL; 5962 HiOps[0] = LHSH; 5963 HiOps[1] = RHSH; 5964 if (Node->getOpcode() == ISD::ADD) { 5965 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5966 HiOps[2] = Lo.getValue(1); 5967 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5968 } else { 5969 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5970 HiOps[2] = Lo.getValue(1); 5971 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5972 } 5973 break; 5974 } 5975 5976 case ISD::ADDC: 5977 case ISD::SUBC: { 5978 // Expand the subcomponents. 5979 SDOperand LHSL, LHSH, RHSL, RHSH; 5980 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5981 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5982 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5983 SDOperand LoOps[2] = { LHSL, RHSL }; 5984 SDOperand HiOps[3] = { LHSH, RHSH }; 5985 5986 if (Node->getOpcode() == ISD::ADDC) { 5987 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5988 HiOps[2] = Lo.getValue(1); 5989 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5990 } else { 5991 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5992 HiOps[2] = Lo.getValue(1); 5993 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5994 } 5995 // Remember that we legalized the flag. 5996 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5997 break; 5998 } 5999 case ISD::ADDE: 6000 case ISD::SUBE: { 6001 // Expand the subcomponents. 6002 SDOperand LHSL, LHSH, RHSL, RHSH; 6003 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6004 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6005 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6006 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 6007 SDOperand HiOps[3] = { LHSH, RHSH }; 6008 6009 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6010 HiOps[2] = Lo.getValue(1); 6011 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6012 6013 // Remember that we legalized the flag. 6014 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6015 break; 6016 } 6017 case ISD::MUL: { 6018 // If the target wants to custom expand this, let them. 6019 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6020 SDOperand New = TLI.LowerOperation(Op, DAG); 6021 if (New.Val) { 6022 ExpandOp(New, Lo, Hi); 6023 break; 6024 } 6025 } 6026 6027 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6028 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6029 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6030 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6031 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6032 SDOperand LL, LH, RL, RH; 6033 ExpandOp(Node->getOperand(0), LL, LH); 6034 ExpandOp(Node->getOperand(1), RL, RH); 6035 unsigned BitSize = MVT::getSizeInBits(RH.getValueType()); 6036 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6037 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6038 // FIXME: generalize this to handle other bit sizes 6039 if (LHSSB == 32 && RHSSB == 32 && 6040 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) && 6041 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) { 6042 // The inputs are both zero-extended. 6043 if (HasUMUL_LOHI) { 6044 // We can emit a umul_lohi. 6045 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6046 Hi = SDOperand(Lo.Val, 1); 6047 break; 6048 } 6049 if (HasMULHU) { 6050 // We can emit a mulhu+mul. 6051 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6052 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6053 break; 6054 } 6055 } 6056 if (LHSSB > BitSize && RHSSB > BitSize) { 6057 // The input values are both sign-extended. 6058 if (HasSMUL_LOHI) { 6059 // We can emit a smul_lohi. 6060 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6061 Hi = SDOperand(Lo.Val, 1); 6062 break; 6063 } 6064 if (HasMULHS) { 6065 // We can emit a mulhs+mul. 6066 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6067 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6068 break; 6069 } 6070 } 6071 if (HasUMUL_LOHI) { 6072 // Lo,Hi = umul LHS, RHS. 6073 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6074 DAG.getVTList(NVT, NVT), LL, RL); 6075 Lo = UMulLOHI; 6076 Hi = UMulLOHI.getValue(1); 6077 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6078 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6079 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6080 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6081 break; 6082 } 6083 if (HasMULHU) { 6084 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6085 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6086 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6087 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6088 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6089 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6090 break; 6091 } 6092 } 6093 6094 // If nothing else, we can make a libcall. 6095 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 6096 false/*sign irrelevant*/, Hi); 6097 break; 6098 } 6099 case ISD::SDIV: 6100 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 6101 break; 6102 case ISD::UDIV: 6103 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 6104 break; 6105 case ISD::SREM: 6106 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 6107 break; 6108 case ISD::UREM: 6109 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 6110 break; 6111 6112 case ISD::FADD: 6113 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32, 6114 RTLIB::ADD_F64, 6115 RTLIB::ADD_F80, 6116 RTLIB::ADD_PPCF128)), 6117 Node, false, Hi); 6118 break; 6119 case ISD::FSUB: 6120 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32, 6121 RTLIB::SUB_F64, 6122 RTLIB::SUB_F80, 6123 RTLIB::SUB_PPCF128)), 6124 Node, false, Hi); 6125 break; 6126 case ISD::FMUL: 6127 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32, 6128 RTLIB::MUL_F64, 6129 RTLIB::MUL_F80, 6130 RTLIB::MUL_PPCF128)), 6131 Node, false, Hi); 6132 break; 6133 case ISD::FDIV: 6134 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32, 6135 RTLIB::DIV_F64, 6136 RTLIB::DIV_F80, 6137 RTLIB::DIV_PPCF128)), 6138 Node, false, Hi); 6139 break; 6140 case ISD::FP_EXTEND: 6141 if (VT == MVT::ppcf128) { 6142 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6143 Node->getOperand(0).getValueType()==MVT::f64); 6144 const uint64_t zero = 0; 6145 if (Node->getOperand(0).getValueType()==MVT::f32) 6146 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6147 else 6148 Hi = Node->getOperand(0); 6149 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6150 break; 6151 } 6152 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 6153 break; 6154 case ISD::FP_ROUND: 6155 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 6156 break; 6157 case ISD::FPOWI: 6158 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32, 6159 RTLIB::POWI_F64, 6160 RTLIB::POWI_F80, 6161 RTLIB::POWI_PPCF128)), 6162 Node, false, Hi); 6163 break; 6164 case ISD::FSQRT: 6165 case ISD::FSIN: 6166 case ISD::FCOS: { 6167 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6168 switch(Node->getOpcode()) { 6169 case ISD::FSQRT: 6170 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6171 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6172 break; 6173 case ISD::FSIN: 6174 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6175 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6176 break; 6177 case ISD::FCOS: 6178 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6179 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6180 break; 6181 default: assert(0 && "Unreachable!"); 6182 } 6183 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 6184 break; 6185 } 6186 case ISD::FABS: { 6187 if (VT == MVT::ppcf128) { 6188 SDOperand Tmp; 6189 ExpandOp(Node->getOperand(0), Lo, Tmp); 6190 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6191 // lo = hi==fabs(hi) ? lo : -lo; 6192 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6193 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6194 DAG.getCondCode(ISD::SETEQ)); 6195 break; 6196 } 6197 SDOperand Mask = (VT == MVT::f64) 6198 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6199 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6200 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6201 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6202 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6203 if (getTypeAction(NVT) == Expand) 6204 ExpandOp(Lo, Lo, Hi); 6205 break; 6206 } 6207 case ISD::FNEG: { 6208 if (VT == MVT::ppcf128) { 6209 ExpandOp(Node->getOperand(0), Lo, Hi); 6210 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6211 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6212 break; 6213 } 6214 SDOperand Mask = (VT == MVT::f64) 6215 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6216 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6217 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6218 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6219 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6220 if (getTypeAction(NVT) == Expand) 6221 ExpandOp(Lo, Lo, Hi); 6222 break; 6223 } 6224 case ISD::FCOPYSIGN: { 6225 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6226 if (getTypeAction(NVT) == Expand) 6227 ExpandOp(Lo, Lo, Hi); 6228 break; 6229 } 6230 case ISD::SINT_TO_FP: 6231 case ISD::UINT_TO_FP: { 6232 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6233 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 6234 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) { 6235 static uint64_t zero = 0; 6236 if (isSigned) { 6237 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6238 Node->getOperand(0))); 6239 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6240 } else { 6241 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6242 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6243 Node->getOperand(0))); 6244 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6245 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6246 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6247 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6248 DAG.getConstant(0, MVT::i32), 6249 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6250 DAG.getConstantFP( 6251 APFloat(APInt(128, 2, TwoE32)), 6252 MVT::ppcf128)), 6253 Hi, 6254 DAG.getCondCode(ISD::SETLT)), 6255 Lo, Hi); 6256 } 6257 break; 6258 } 6259 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6260 // si64->ppcf128 done by libcall, below 6261 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6262 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6263 Lo, Hi); 6264 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6265 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6266 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6267 DAG.getConstant(0, MVT::i64), 6268 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6269 DAG.getConstantFP( 6270 APFloat(APInt(128, 2, TwoE64)), 6271 MVT::ppcf128)), 6272 Hi, 6273 DAG.getCondCode(ISD::SETLT)), 6274 Lo, Hi); 6275 break; 6276 } 6277 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6278 if (Node->getOperand(0).getValueType() == MVT::i64) { 6279 if (VT == MVT::f32) 6280 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 6281 else if (VT == MVT::f64) 6282 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 6283 else if (VT == MVT::f80) { 6284 assert(isSigned); 6285 LC = RTLIB::SINTTOFP_I64_F80; 6286 } 6287 else if (VT == MVT::ppcf128) { 6288 assert(isSigned); 6289 LC = RTLIB::SINTTOFP_I64_PPCF128; 6290 } 6291 } else { 6292 if (VT == MVT::f32) 6293 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 6294 else 6295 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 6296 } 6297 6298 // Promote the operand if needed. 6299 if (getTypeAction(SrcVT) == Promote) { 6300 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6301 Tmp = isSigned 6302 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6303 DAG.getValueType(SrcVT)) 6304 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6305 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6306 } 6307 6308 const char *LibCall = TLI.getLibcallName(LC); 6309 if (LibCall) 6310 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 6311 else { 6312 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6313 Node->getOperand(0)); 6314 if (getTypeAction(Lo.getValueType()) == Expand) 6315 ExpandOp(Lo, Lo, Hi); 6316 } 6317 break; 6318 } 6319 } 6320 6321 // Make sure the resultant values have been legalized themselves, unless this 6322 // is a type that requires multi-step expansion. 6323 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6324 Lo = LegalizeOp(Lo); 6325 if (Hi.Val) 6326 // Don't legalize the high part if it is expanded to a single node. 6327 Hi = LegalizeOp(Hi); 6328 } 6329 6330 // Remember in a map if the values will be reused later. 6331 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6332 assert(isNew && "Value already expanded?!?"); 6333} 6334 6335/// SplitVectorOp - Given an operand of vector type, break it down into 6336/// two smaller values, still of vector type. 6337void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6338 SDOperand &Hi) { 6339 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); 6340 SDNode *Node = Op.Val; 6341 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType()); 6342 assert(NumElements > 1 && "Cannot split a single element vector!"); 6343 6344 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType()); 6345 6346 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6347 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6348 6349 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo); 6350 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi); 6351 6352 // See if we already split it. 6353 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6354 = SplitNodes.find(Op); 6355 if (I != SplitNodes.end()) { 6356 Lo = I->second.first; 6357 Hi = I->second.second; 6358 return; 6359 } 6360 6361 switch (Node->getOpcode()) { 6362 default: 6363#ifndef NDEBUG 6364 Node->dump(&DAG); 6365#endif 6366 assert(0 && "Unhandled operation in SplitVectorOp!"); 6367 case ISD::UNDEF: 6368 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6369 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6370 break; 6371 case ISD::BUILD_PAIR: 6372 Lo = Node->getOperand(0); 6373 Hi = Node->getOperand(1); 6374 break; 6375 case ISD::INSERT_VECTOR_ELT: { 6376 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6377 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 6378 SDOperand ScalarOp = Node->getOperand(1); 6379 if (Index < NewNumElts_Lo) 6380 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6381 DAG.getConstant(Index, TLI.getPointerTy())); 6382 else 6383 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6384 DAG.getConstant(Index - NewNumElts_Lo, 6385 TLI.getPointerTy())); 6386 break; 6387 } 6388 case ISD::VECTOR_SHUFFLE: { 6389 // Build the low part. 6390 SDOperand Mask = Node->getOperand(2); 6391 SmallVector<SDOperand, 8> Ops; 6392 MVT::ValueType PtrVT = TLI.getPointerTy(); 6393 6394 // Insert all of the elements from the input that are needed. We use 6395 // buildvector of extractelement here because the input vectors will have 6396 // to be legalized, so this makes the code simpler. 6397 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6398 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 6399 SDOperand InVec = Node->getOperand(0); 6400 if (Idx >= NumElements) { 6401 InVec = Node->getOperand(1); 6402 Idx -= NumElements; 6403 } 6404 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6405 DAG.getConstant(Idx, PtrVT))); 6406 } 6407 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6408 Ops.clear(); 6409 6410 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6411 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 6412 SDOperand InVec = Node->getOperand(0); 6413 if (Idx >= NumElements) { 6414 InVec = Node->getOperand(1); 6415 Idx -= NumElements; 6416 } 6417 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6418 DAG.getConstant(Idx, PtrVT))); 6419 } 6420 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6421 break; 6422 } 6423 case ISD::BUILD_VECTOR: { 6424 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6425 Node->op_begin()+NewNumElts_Lo); 6426 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6427 6428 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6429 Node->op_end()); 6430 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6431 break; 6432 } 6433 case ISD::CONCAT_VECTORS: { 6434 // FIXME: Handle non-power-of-two vectors? 6435 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6436 if (NewNumSubvectors == 1) { 6437 Lo = Node->getOperand(0); 6438 Hi = Node->getOperand(1); 6439 } else { 6440 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6441 Node->op_begin()+NewNumSubvectors); 6442 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6443 6444 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6445 Node->op_end()); 6446 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6447 } 6448 break; 6449 } 6450 case ISD::SELECT: { 6451 SDOperand Cond = Node->getOperand(0); 6452 6453 SDOperand LL, LH, RL, RH; 6454 SplitVectorOp(Node->getOperand(1), LL, LH); 6455 SplitVectorOp(Node->getOperand(2), RL, RH); 6456 6457 if (MVT::isVector(Cond.getValueType())) { 6458 // Handle a vector merge. 6459 SDOperand CL, CH; 6460 SplitVectorOp(Cond, CL, CH); 6461 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6462 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6463 } else { 6464 // Handle a simple select with vector operands. 6465 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6466 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6467 } 6468 break; 6469 } 6470 case ISD::ADD: 6471 case ISD::SUB: 6472 case ISD::MUL: 6473 case ISD::FADD: 6474 case ISD::FSUB: 6475 case ISD::FMUL: 6476 case ISD::SDIV: 6477 case ISD::UDIV: 6478 case ISD::FDIV: 6479 case ISD::FPOW: 6480 case ISD::AND: 6481 case ISD::OR: 6482 case ISD::XOR: 6483 case ISD::UREM: 6484 case ISD::SREM: 6485 case ISD::FREM: { 6486 SDOperand LL, LH, RL, RH; 6487 SplitVectorOp(Node->getOperand(0), LL, LH); 6488 SplitVectorOp(Node->getOperand(1), RL, RH); 6489 6490 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 6491 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 6492 break; 6493 } 6494 case ISD::FPOWI: { 6495 SDOperand L, H; 6496 SplitVectorOp(Node->getOperand(0), L, H); 6497 6498 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 6499 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 6500 break; 6501 } 6502 case ISD::CTTZ: 6503 case ISD::CTLZ: 6504 case ISD::CTPOP: 6505 case ISD::FNEG: 6506 case ISD::FABS: 6507 case ISD::FSQRT: 6508 case ISD::FSIN: 6509 case ISD::FCOS: 6510 case ISD::FP_TO_SINT: 6511 case ISD::FP_TO_UINT: 6512 case ISD::SINT_TO_FP: 6513 case ISD::UINT_TO_FP: { 6514 SDOperand L, H; 6515 SplitVectorOp(Node->getOperand(0), L, H); 6516 6517 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 6518 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 6519 break; 6520 } 6521 case ISD::LOAD: { 6522 LoadSDNode *LD = cast<LoadSDNode>(Node); 6523 SDOperand Ch = LD->getChain(); 6524 SDOperand Ptr = LD->getBasePtr(); 6525 const Value *SV = LD->getSrcValue(); 6526 int SVOffset = LD->getSrcValueOffset(); 6527 unsigned Alignment = LD->getAlignment(); 6528 bool isVolatile = LD->isVolatile(); 6529 6530 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6531 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8; 6532 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6533 DAG.getIntPtrConstant(IncrementSize)); 6534 SVOffset += IncrementSize; 6535 Alignment = MinAlign(Alignment, IncrementSize); 6536 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6537 6538 // Build a factor node to remember that this load is independent of the 6539 // other one. 6540 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6541 Hi.getValue(1)); 6542 6543 // Remember that we legalized the chain. 6544 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6545 break; 6546 } 6547 case ISD::BIT_CONVERT: { 6548 // We know the result is a vector. The input may be either a vector or a 6549 // scalar value. 6550 SDOperand InOp = Node->getOperand(0); 6551 if (!MVT::isVector(InOp.getValueType()) || 6552 MVT::getVectorNumElements(InOp.getValueType()) == 1) { 6553 // The input is a scalar or single-element vector. 6554 // Lower to a store/load so that it can be split. 6555 // FIXME: this could be improved probably. 6556 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); 6557 6558 SDOperand St = DAG.getStore(DAG.getEntryNode(), 6559 InOp, Ptr, NULL, 0); 6560 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0); 6561 } 6562 // Split the vector and convert each of the pieces now. 6563 SplitVectorOp(InOp, Lo, Hi); 6564 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 6565 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 6566 break; 6567 } 6568 } 6569 6570 // Remember in a map if the values will be reused later. 6571 bool isNew = 6572 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 6573 assert(isNew && "Value already split?!?"); 6574} 6575 6576 6577/// ScalarizeVectorOp - Given an operand of single-element vector type 6578/// (e.g. v1f32), convert it into the equivalent operation that returns a 6579/// scalar (e.g. f32) value. 6580SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 6581 assert(MVT::isVector(Op.getValueType()) && 6582 "Bad ScalarizeVectorOp invocation!"); 6583 SDNode *Node = Op.Val; 6584 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); 6585 assert(MVT::getVectorNumElements(Op.getValueType()) == 1); 6586 6587 // See if we already scalarized it. 6588 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 6589 if (I != ScalarizedNodes.end()) return I->second; 6590 6591 SDOperand Result; 6592 switch (Node->getOpcode()) { 6593 default: 6594#ifndef NDEBUG 6595 Node->dump(&DAG); cerr << "\n"; 6596#endif 6597 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 6598 case ISD::ADD: 6599 case ISD::FADD: 6600 case ISD::SUB: 6601 case ISD::FSUB: 6602 case ISD::MUL: 6603 case ISD::FMUL: 6604 case ISD::SDIV: 6605 case ISD::UDIV: 6606 case ISD::FDIV: 6607 case ISD::SREM: 6608 case ISD::UREM: 6609 case ISD::FREM: 6610 case ISD::FPOW: 6611 case ISD::AND: 6612 case ISD::OR: 6613 case ISD::XOR: 6614 Result = DAG.getNode(Node->getOpcode(), 6615 NewVT, 6616 ScalarizeVectorOp(Node->getOperand(0)), 6617 ScalarizeVectorOp(Node->getOperand(1))); 6618 break; 6619 case ISD::FNEG: 6620 case ISD::FABS: 6621 case ISD::FSQRT: 6622 case ISD::FSIN: 6623 case ISD::FCOS: 6624 Result = DAG.getNode(Node->getOpcode(), 6625 NewVT, 6626 ScalarizeVectorOp(Node->getOperand(0))); 6627 break; 6628 case ISD::FPOWI: 6629 Result = DAG.getNode(Node->getOpcode(), 6630 NewVT, 6631 ScalarizeVectorOp(Node->getOperand(0)), 6632 Node->getOperand(1)); 6633 break; 6634 case ISD::LOAD: { 6635 LoadSDNode *LD = cast<LoadSDNode>(Node); 6636 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 6637 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 6638 6639 const Value *SV = LD->getSrcValue(); 6640 int SVOffset = LD->getSrcValueOffset(); 6641 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 6642 LD->isVolatile(), LD->getAlignment()); 6643 6644 // Remember that we legalized the chain. 6645 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 6646 break; 6647 } 6648 case ISD::BUILD_VECTOR: 6649 Result = Node->getOperand(0); 6650 break; 6651 case ISD::INSERT_VECTOR_ELT: 6652 // Returning the inserted scalar element. 6653 Result = Node->getOperand(1); 6654 break; 6655 case ISD::CONCAT_VECTORS: 6656 assert(Node->getOperand(0).getValueType() == NewVT && 6657 "Concat of non-legal vectors not yet supported!"); 6658 Result = Node->getOperand(0); 6659 break; 6660 case ISD::VECTOR_SHUFFLE: { 6661 // Figure out if the scalar is the LHS or RHS and return it. 6662 SDOperand EltNum = Node->getOperand(2).getOperand(0); 6663 if (cast<ConstantSDNode>(EltNum)->getValue()) 6664 Result = ScalarizeVectorOp(Node->getOperand(1)); 6665 else 6666 Result = ScalarizeVectorOp(Node->getOperand(0)); 6667 break; 6668 } 6669 case ISD::EXTRACT_SUBVECTOR: 6670 Result = Node->getOperand(0); 6671 assert(Result.getValueType() == NewVT); 6672 break; 6673 case ISD::BIT_CONVERT: 6674 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 6675 break; 6676 case ISD::SELECT: 6677 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 6678 ScalarizeVectorOp(Op.getOperand(1)), 6679 ScalarizeVectorOp(Op.getOperand(2))); 6680 break; 6681 } 6682 6683 if (TLI.isTypeLegal(NewVT)) 6684 Result = LegalizeOp(Result); 6685 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 6686 assert(isNew && "Value already scalarized?"); 6687 return Result; 6688} 6689 6690 6691// SelectionDAG::Legalize - This is the entry point for the file. 6692// 6693void SelectionDAG::Legalize() { 6694 if (ViewLegalizeDAGs) viewGraph(); 6695 6696 /// run - This is the main entry point to this class. 6697 /// 6698 SelectionDAGLegalize(*this).LegalizeDAG(); 6699} 6700 6701