LegalizeDAG.cpp revision a1eaa3c52b75d4fe2bcd4f7c52e56c405ee91d3c
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/DwarfWriter.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/CodeGen/PseudoSourceValue.h" 22#include "llvm/Target/TargetFrameInfo.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetData.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Target/TargetSubtarget.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/DerivedTypes.h" 31#include "llvm/Function.h" 32#include "llvm/GlobalVariable.h" 33#include "llvm/LLVMContext.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/raw_ostream.h" 38#include "llvm/ADT/DenseMap.h" 39#include "llvm/ADT/SmallVector.h" 40#include "llvm/ADT/SmallPtrSet.h" 41#include <map> 42using namespace llvm; 43 44//===----------------------------------------------------------------------===// 45/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 46/// hacks on it until the target machine can handle it. This involves 47/// eliminating value sizes the machine cannot handle (promoting small sizes to 48/// large sizes or splitting up large values into small values) as well as 49/// eliminating operations the machine cannot handle. 50/// 51/// This code also does a small amount of optimization and recognition of idioms 52/// as part of its processing. For example, if a target does not support a 53/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 54/// will attempt merge setcc and brc instructions into brcc's. 55/// 56namespace { 57class SelectionDAGLegalize { 58 TargetLowering &TLI; 59 SelectionDAG &DAG; 60 CodeGenOpt::Level OptLevel; 61 62 // Libcall insertion helpers. 63 64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 65 /// legalized. We use this to ensure that calls are properly serialized 66 /// against each other, including inserted libcalls. 67 SDValue LastCALLSEQ_END; 68 69 /// IsLegalizingCall - This member is used *only* for purposes of providing 70 /// helpful assertions that a libcall isn't created while another call is 71 /// being legalized (which could lead to non-serialized call sequences). 72 bool IsLegalizingCall; 73 74 enum LegalizeAction { 75 Legal, // The target natively supports this operation. 76 Promote, // This operation should be executed in a larger type. 77 Expand // Try to expand this to other ops, otherwise use a libcall. 78 }; 79 80 /// ValueTypeActions - This is a bitvector that contains two bits for each 81 /// value type, where the two bits correspond to the LegalizeAction enum. 82 /// This can be queried with "getTypeAction(VT)". 83 TargetLowering::ValueTypeActionImpl ValueTypeActions; 84 85 /// LegalizedNodes - For nodes that are of legal width, and that have more 86 /// than one use, this map indicates what regularized operand to use. This 87 /// allows us to avoid legalizing the same thing more than once. 88 DenseMap<SDValue, SDValue> LegalizedNodes; 89 90 void AddLegalizedOperand(SDValue From, SDValue To) { 91 LegalizedNodes.insert(std::make_pair(From, To)); 92 // If someone requests legalization of the new node, return itself. 93 if (From != To) 94 LegalizedNodes.insert(std::make_pair(To, To)); 95 } 96 97public: 98 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 99 100 /// getTypeAction - Return how we should legalize values of this type, either 101 /// it is already legal or we need to expand it into multiple registers of 102 /// smaller integer type, or we need to promote it to a larger type. 103 LegalizeAction getTypeAction(EVT VT) const { 104 return 105 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT); 106 } 107 108 /// isTypeLegal - Return true if this type is legal on this target. 109 /// 110 bool isTypeLegal(EVT VT) const { 111 return getTypeAction(VT) == Legal; 112 } 113 114 void LegalizeDAG(); 115 116private: 117 /// LegalizeOp - We know that the specified value has a legal type. 118 /// Recursively ensure that the operands have legal types, then return the 119 /// result. 120 SDValue LegalizeOp(SDValue O); 121 122 SDValue OptimizeFloatStore(StoreSDNode *ST); 123 124 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 125 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 126 /// is necessary to spill the vector being inserted into to memory, perform 127 /// the insert there, and then read the result back. 128 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 129 SDValue Idx, DebugLoc dl); 130 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 131 SDValue Idx, DebugLoc dl); 132 133 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 134 /// performs the same shuffe in terms of order or result bytes, but on a type 135 /// whose vector element type is narrower than the original shuffle type. 136 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 137 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 138 SDValue N1, SDValue N2, 139 SmallVectorImpl<int> &Mask) const; 140 141 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 142 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 143 144 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 145 DebugLoc dl); 146 147 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 148 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 149 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 150 RTLIB::Libcall Call_PPCF128); 151 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, RTLIB::Libcall Call_I16, 152 RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64, 153 RTLIB::Libcall Call_I128); 154 155 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 156 SDValue ExpandBUILD_VECTOR(SDNode *Node); 157 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 158 SDValue ExpandDBG_STOPPOINT(SDNode *Node); 159 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 160 SmallVectorImpl<SDValue> &Results); 161 SDValue ExpandFCOPYSIGN(SDNode *Node); 162 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 163 DebugLoc dl); 164 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 165 DebugLoc dl); 166 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 167 DebugLoc dl); 168 169 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 170 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 171 172 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 173 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 174 175 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 176 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 177}; 178} 179 180/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 181/// performs the same shuffe in terms of order or result bytes, but on a type 182/// whose vector element type is narrower than the original shuffle type. 183/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 184SDValue 185SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 186 SDValue N1, SDValue N2, 187 SmallVectorImpl<int> &Mask) const { 188 EVT EltVT = NVT.getVectorElementType(); 189 unsigned NumMaskElts = VT.getVectorNumElements(); 190 unsigned NumDestElts = NVT.getVectorNumElements(); 191 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 192 193 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 194 195 if (NumEltsGrowth == 1) 196 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 197 198 SmallVector<int, 8> NewMask; 199 for (unsigned i = 0; i != NumMaskElts; ++i) { 200 int Idx = Mask[i]; 201 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 202 if (Idx < 0) 203 NewMask.push_back(-1); 204 else 205 NewMask.push_back(Idx * NumEltsGrowth + j); 206 } 207 } 208 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 209 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 210 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 211} 212 213SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 214 CodeGenOpt::Level ol) 215 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), 216 ValueTypeActions(TLI.getValueTypeActions()) { 217 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 218 "Too many value types for ValueTypeActions to hold!"); 219} 220 221void SelectionDAGLegalize::LegalizeDAG() { 222 LastCALLSEQ_END = DAG.getEntryNode(); 223 IsLegalizingCall = false; 224 225 // The legalize process is inherently a bottom-up recursive process (users 226 // legalize their uses before themselves). Given infinite stack space, we 227 // could just start legalizing on the root and traverse the whole graph. In 228 // practice however, this causes us to run out of stack space on large basic 229 // blocks. To avoid this problem, compute an ordering of the nodes where each 230 // node is only legalized after all of its operands are legalized. 231 DAG.AssignTopologicalOrder(); 232 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 233 E = prior(DAG.allnodes_end()); I != next(E); ++I) 234 LegalizeOp(SDValue(I, 0)); 235 236 // Finally, it's possible the root changed. Get the new root. 237 SDValue OldRoot = DAG.getRoot(); 238 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 239 DAG.setRoot(LegalizedNodes[OldRoot]); 240 241 LegalizedNodes.clear(); 242 243 // Remove dead nodes now. 244 DAG.RemoveDeadNodes(); 245} 246 247 248/// FindCallEndFromCallStart - Given a chained node that is part of a call 249/// sequence, find the CALLSEQ_END node that terminates the call sequence. 250static SDNode *FindCallEndFromCallStart(SDNode *Node) { 251 if (Node->getOpcode() == ISD::CALLSEQ_END) 252 return Node; 253 if (Node->use_empty()) 254 return 0; // No CallSeqEnd 255 256 // The chain is usually at the end. 257 SDValue TheChain(Node, Node->getNumValues()-1); 258 if (TheChain.getValueType() != MVT::Other) { 259 // Sometimes it's at the beginning. 260 TheChain = SDValue(Node, 0); 261 if (TheChain.getValueType() != MVT::Other) { 262 // Otherwise, hunt for it. 263 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 264 if (Node->getValueType(i) == MVT::Other) { 265 TheChain = SDValue(Node, i); 266 break; 267 } 268 269 // Otherwise, we walked into a node without a chain. 270 if (TheChain.getValueType() != MVT::Other) 271 return 0; 272 } 273 } 274 275 for (SDNode::use_iterator UI = Node->use_begin(), 276 E = Node->use_end(); UI != E; ++UI) { 277 278 // Make sure to only follow users of our token chain. 279 SDNode *User = *UI; 280 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 281 if (User->getOperand(i) == TheChain) 282 if (SDNode *Result = FindCallEndFromCallStart(User)) 283 return Result; 284 } 285 return 0; 286} 287 288/// FindCallStartFromCallEnd - Given a chained node that is part of a call 289/// sequence, find the CALLSEQ_START node that initiates the call sequence. 290static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 291 assert(Node && "Didn't find callseq_start for a call??"); 292 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 293 294 assert(Node->getOperand(0).getValueType() == MVT::Other && 295 "Node doesn't have a token chain argument!"); 296 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 297} 298 299/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 300/// see if any uses can reach Dest. If no dest operands can get to dest, 301/// legalize them, legalize ourself, and return false, otherwise, return true. 302/// 303/// Keep track of the nodes we fine that actually do lead to Dest in 304/// NodesLeadingTo. This avoids retraversing them exponential number of times. 305/// 306bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 307 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 308 if (N == Dest) return true; // N certainly leads to Dest :) 309 310 // If we've already processed this node and it does lead to Dest, there is no 311 // need to reprocess it. 312 if (NodesLeadingTo.count(N)) return true; 313 314 // If the first result of this node has been already legalized, then it cannot 315 // reach N. 316 if (LegalizedNodes.count(SDValue(N, 0))) return false; 317 318 // Okay, this node has not already been legalized. Check and legalize all 319 // operands. If none lead to Dest, then we can legalize this node. 320 bool OperandsLeadToDest = false; 321 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 322 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 323 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 324 325 if (OperandsLeadToDest) { 326 NodesLeadingTo.insert(N); 327 return true; 328 } 329 330 // Okay, this node looks safe, legalize it and return false. 331 LegalizeOp(SDValue(N, 0)); 332 return false; 333} 334 335/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 336/// a load from the constant pool. 337static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 338 SelectionDAG &DAG, const TargetLowering &TLI) { 339 bool Extend = false; 340 DebugLoc dl = CFP->getDebugLoc(); 341 342 // If a FP immediate is precise when represented as a float and if the 343 // target can do an extending load from float to double, we put it into 344 // the constant pool as a float, even if it's is statically typed as a 345 // double. This shrinks FP constants and canonicalizes them for targets where 346 // an FP extending load is the same cost as a normal load (such as on the x87 347 // fp stack or PPC FP unit). 348 EVT VT = CFP->getValueType(0); 349 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 350 if (!UseCP) { 351 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 352 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 353 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 354 } 355 356 EVT OrigVT = VT; 357 EVT SVT = VT; 358 while (SVT != MVT::f32) { 359 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 360 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 361 // Only do this if the target has a native EXTLOAD instruction from 362 // smaller type. 363 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 364 TLI.ShouldShrinkFPConstant(OrigVT)) { 365 const Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 366 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 367 VT = SVT; 368 Extend = true; 369 } 370 } 371 372 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 373 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 374 if (Extend) 375 return DAG.getExtLoad(ISD::EXTLOAD, dl, 376 OrigVT, DAG.getEntryNode(), 377 CPIdx, PseudoSourceValue::getConstantPool(), 378 0, VT, false, Alignment); 379 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 380 PseudoSourceValue::getConstantPool(), 0, false, Alignment); 381} 382 383/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 384static 385SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 386 const TargetLowering &TLI) { 387 SDValue Chain = ST->getChain(); 388 SDValue Ptr = ST->getBasePtr(); 389 SDValue Val = ST->getValue(); 390 EVT VT = Val.getValueType(); 391 int Alignment = ST->getAlignment(); 392 int SVOffset = ST->getSrcValueOffset(); 393 DebugLoc dl = ST->getDebugLoc(); 394 if (ST->getMemoryVT().isFloatingPoint() || 395 ST->getMemoryVT().isVector()) { 396 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 397 if (TLI.isTypeLegal(intVT)) { 398 // Expand to a bitconvert of the value to the integer type of the 399 // same size, then a (misaligned) int store. 400 // FIXME: Does not handle truncating floating point stores! 401 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 402 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 403 SVOffset, ST->isVolatile(), Alignment); 404 } else { 405 // Do a (aligned) store to a stack slot, then copy from the stack slot 406 // to the final destination using (unaligned) integer loads and stores. 407 EVT StoredVT = ST->getMemoryVT(); 408 EVT RegVT = 409 TLI.getRegisterType(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), StoredVT.getSizeInBits())); 410 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 411 unsigned RegBytes = RegVT.getSizeInBits() / 8; 412 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 413 414 // Make sure the stack slot is also aligned for the register type. 415 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 416 417 // Perform the original store, only redirected to the stack slot. 418 SDValue Store = DAG.getTruncStore(Chain, dl, 419 Val, StackPtr, NULL, 0, StoredVT); 420 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 421 SmallVector<SDValue, 8> Stores; 422 unsigned Offset = 0; 423 424 // Do all but one copies using the full register width. 425 for (unsigned i = 1; i < NumRegs; i++) { 426 // Load one integer register's worth from the stack slot. 427 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0); 428 // Store it to the final location. Remember the store. 429 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 430 ST->getSrcValue(), SVOffset + Offset, 431 ST->isVolatile(), 432 MinAlign(ST->getAlignment(), Offset))); 433 // Increment the pointers. 434 Offset += RegBytes; 435 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 436 Increment); 437 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 438 } 439 440 // The last store may be partial. Do a truncating store. On big-endian 441 // machines this requires an extending load from the stack slot to ensure 442 // that the bits are in the right place. 443 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset)); 444 445 // Load from the stack slot. 446 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 447 NULL, 0, MemVT); 448 449 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 450 ST->getSrcValue(), SVOffset + Offset, 451 MemVT, ST->isVolatile(), 452 MinAlign(ST->getAlignment(), Offset))); 453 // The order of the stores doesn't matter - say it with a TokenFactor. 454 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 455 Stores.size()); 456 } 457 } 458 assert(ST->getMemoryVT().isInteger() && 459 !ST->getMemoryVT().isVector() && 460 "Unaligned store of unknown type."); 461 // Get the half-size VT 462 EVT NewStoredVT = 463 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT().SimpleTy - 1); 464 int NumBits = NewStoredVT.getSizeInBits(); 465 int IncrementSize = NumBits / 8; 466 467 // Divide the stored value in two parts. 468 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 469 SDValue Lo = Val; 470 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 471 472 // Store the two parts 473 SDValue Store1, Store2; 474 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 475 ST->getSrcValue(), SVOffset, NewStoredVT, 476 ST->isVolatile(), Alignment); 477 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 478 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 479 Alignment = MinAlign(Alignment, IncrementSize); 480 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 481 ST->getSrcValue(), SVOffset + IncrementSize, 482 NewStoredVT, ST->isVolatile(), Alignment); 483 484 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 485} 486 487/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 488static 489SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 490 const TargetLowering &TLI) { 491 int SVOffset = LD->getSrcValueOffset(); 492 SDValue Chain = LD->getChain(); 493 SDValue Ptr = LD->getBasePtr(); 494 EVT VT = LD->getValueType(0); 495 EVT LoadedVT = LD->getMemoryVT(); 496 DebugLoc dl = LD->getDebugLoc(); 497 if (VT.isFloatingPoint() || VT.isVector()) { 498 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 499 if (TLI.isTypeLegal(intVT)) { 500 // Expand to a (misaligned) integer load of the same size, 501 // then bitconvert to floating point or vector. 502 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 503 SVOffset, LD->isVolatile(), 504 LD->getAlignment()); 505 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 506 if (VT.isFloatingPoint() && LoadedVT != VT) 507 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 508 509 SDValue Ops[] = { Result, Chain }; 510 return DAG.getMergeValues(Ops, 2, dl); 511 } else { 512 // Copy the value to a (aligned) stack slot using (unaligned) integer 513 // loads and stores, then do a (aligned) load from the stack slot. 514 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 515 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 516 unsigned RegBytes = RegVT.getSizeInBits() / 8; 517 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 518 519 // Make sure the stack slot is also aligned for the register type. 520 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 521 522 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 523 SmallVector<SDValue, 8> Stores; 524 SDValue StackPtr = StackBase; 525 unsigned Offset = 0; 526 527 // Do all but one copies using the full register width. 528 for (unsigned i = 1; i < NumRegs; i++) { 529 // Load one integer register's worth from the original location. 530 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 531 SVOffset + Offset, LD->isVolatile(), 532 MinAlign(LD->getAlignment(), Offset)); 533 // Follow the load with a store to the stack slot. Remember the store. 534 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 535 NULL, 0)); 536 // Increment the pointers. 537 Offset += RegBytes; 538 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 539 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 540 Increment); 541 } 542 543 // The last copy may be partial. Do an extending load. 544 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (LoadedBytes - Offset)); 545 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 546 LD->getSrcValue(), SVOffset + Offset, 547 MemVT, LD->isVolatile(), 548 MinAlign(LD->getAlignment(), Offset)); 549 // Follow the load with a store to the stack slot. Remember the store. 550 // On big-endian machines this requires a truncating store to ensure 551 // that the bits end up in the right place. 552 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 553 NULL, 0, MemVT)); 554 555 // The order of the stores doesn't matter - say it with a TokenFactor. 556 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 557 Stores.size()); 558 559 // Finally, perform the original load only redirected to the stack slot. 560 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 561 NULL, 0, LoadedVT); 562 563 // Callers expect a MERGE_VALUES node. 564 SDValue Ops[] = { Load, TF }; 565 return DAG.getMergeValues(Ops, 2, dl); 566 } 567 } 568 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 569 "Unaligned load of unsupported type."); 570 571 // Compute the new VT that is half the size of the old one. This is an 572 // integer MVT. 573 unsigned NumBits = LoadedVT.getSizeInBits(); 574 EVT NewLoadedVT; 575 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 576 NumBits >>= 1; 577 578 unsigned Alignment = LD->getAlignment(); 579 unsigned IncrementSize = NumBits / 8; 580 ISD::LoadExtType HiExtType = LD->getExtensionType(); 581 582 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 583 if (HiExtType == ISD::NON_EXTLOAD) 584 HiExtType = ISD::ZEXTLOAD; 585 586 // Load the value in two parts 587 SDValue Lo, Hi; 588 if (TLI.isLittleEndian()) { 589 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 590 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 591 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 592 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 593 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 594 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 595 MinAlign(Alignment, IncrementSize)); 596 } else { 597 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 598 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 599 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 600 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 601 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 602 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 603 MinAlign(Alignment, IncrementSize)); 604 } 605 606 // aggregate the two parts 607 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 608 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 609 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 610 611 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 612 Hi.getValue(1)); 613 614 SDValue Ops[] = { Result, TF }; 615 return DAG.getMergeValues(Ops, 2, dl); 616} 617 618/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 619/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 620/// is necessary to spill the vector being inserted into to memory, perform 621/// the insert there, and then read the result back. 622SDValue SelectionDAGLegalize:: 623PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 624 DebugLoc dl) { 625 SDValue Tmp1 = Vec; 626 SDValue Tmp2 = Val; 627 SDValue Tmp3 = Idx; 628 629 // If the target doesn't support this, we have to spill the input vector 630 // to a temporary stack slot, update the element, then reload it. This is 631 // badness. We could also load the value into a vector register (either 632 // with a "move to register" or "extload into register" instruction, then 633 // permute it into place, if the idx is a constant and if the idx is 634 // supported by the target. 635 EVT VT = Tmp1.getValueType(); 636 EVT EltVT = VT.getVectorElementType(); 637 EVT IdxVT = Tmp3.getValueType(); 638 EVT PtrVT = TLI.getPointerTy(); 639 SDValue StackPtr = DAG.CreateStackTemporary(VT); 640 641 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 642 643 // Store the vector. 644 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 645 PseudoSourceValue::getFixedStack(SPFI), 0); 646 647 // Truncate or zero extend offset to target pointer type. 648 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 649 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 650 // Add the offset to the index. 651 unsigned EltSize = EltVT.getSizeInBits()/8; 652 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 653 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 654 // Store the scalar value. 655 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 656 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 657 // Load the updated vector. 658 return DAG.getLoad(VT, dl, Ch, StackPtr, 659 PseudoSourceValue::getFixedStack(SPFI), 0); 660} 661 662 663SDValue SelectionDAGLegalize:: 664ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 665 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 666 // SCALAR_TO_VECTOR requires that the type of the value being inserted 667 // match the element type of the vector being created, except for 668 // integers in which case the inserted value can be over width. 669 EVT EltVT = Vec.getValueType().getVectorElementType(); 670 if (Val.getValueType() == EltVT || 671 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 672 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 673 Vec.getValueType(), Val); 674 675 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 676 // We generate a shuffle of InVec and ScVec, so the shuffle mask 677 // should be 0,1,2,3,4,5... with the appropriate element replaced with 678 // elt 0 of the RHS. 679 SmallVector<int, 8> ShufOps; 680 for (unsigned i = 0; i != NumElts; ++i) 681 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 682 683 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 684 &ShufOps[0]); 685 } 686 } 687 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 688} 689 690SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 691 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 692 // FIXME: We shouldn't do this for TargetConstantFP's. 693 // FIXME: move this to the DAG Combiner! Note that we can't regress due 694 // to phase ordering between legalized code and the dag combiner. This 695 // probably means that we need to integrate dag combiner and legalizer 696 // together. 697 // We generally can't do this one for long doubles. 698 SDValue Tmp1 = ST->getChain(); 699 SDValue Tmp2 = ST->getBasePtr(); 700 SDValue Tmp3; 701 int SVOffset = ST->getSrcValueOffset(); 702 unsigned Alignment = ST->getAlignment(); 703 bool isVolatile = ST->isVolatile(); 704 DebugLoc dl = ST->getDebugLoc(); 705 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 706 if (CFP->getValueType(0) == MVT::f32 && 707 getTypeAction(MVT::i32) == Legal) { 708 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 709 bitcastToAPInt().zextOrTrunc(32), 710 MVT::i32); 711 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 712 SVOffset, isVolatile, Alignment); 713 } else if (CFP->getValueType(0) == MVT::f64) { 714 // If this target supports 64-bit registers, do a single 64-bit store. 715 if (getTypeAction(MVT::i64) == Legal) { 716 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 717 zextOrTrunc(64), MVT::i64); 718 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 719 SVOffset, isVolatile, Alignment); 720 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 721 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 722 // stores. If the target supports neither 32- nor 64-bits, this 723 // xform is certainly not worth it. 724 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 725 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 726 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 727 if (TLI.isBigEndian()) std::swap(Lo, Hi); 728 729 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 730 SVOffset, isVolatile, Alignment); 731 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 732 DAG.getIntPtrConstant(4)); 733 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 734 isVolatile, MinAlign(Alignment, 4U)); 735 736 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 737 } 738 } 739 } 740 return SDValue(); 741} 742 743/// LegalizeOp - We know that the specified value has a legal type, and 744/// that its operands are legal. Now ensure that the operation itself 745/// is legal, recursively ensuring that the operands' operations remain 746/// legal. 747SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 748 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 749 return Op; 750 751 SDNode *Node = Op.getNode(); 752 DebugLoc dl = Node->getDebugLoc(); 753 754 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 755 assert(getTypeAction(Node->getValueType(i)) == Legal && 756 "Unexpected illegal type!"); 757 758 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 759 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 760 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 761 "Unexpected illegal type!"); 762 763 // Note that LegalizeOp may be reentered even from single-use nodes, which 764 // means that we always must cache transformed nodes. 765 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 766 if (I != LegalizedNodes.end()) return I->second; 767 768 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 769 SDValue Result = Op; 770 bool isCustom = false; 771 772 // Figure out the correct action; the way to query this varies by opcode 773 TargetLowering::LegalizeAction Action; 774 bool SimpleFinishLegalizing = true; 775 switch (Node->getOpcode()) { 776 case ISD::INTRINSIC_W_CHAIN: 777 case ISD::INTRINSIC_WO_CHAIN: 778 case ISD::INTRINSIC_VOID: 779 case ISD::VAARG: 780 case ISD::STACKSAVE: 781 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 782 break; 783 case ISD::SINT_TO_FP: 784 case ISD::UINT_TO_FP: 785 case ISD::EXTRACT_VECTOR_ELT: 786 Action = TLI.getOperationAction(Node->getOpcode(), 787 Node->getOperand(0).getValueType()); 788 break; 789 case ISD::FP_ROUND_INREG: 790 case ISD::SIGN_EXTEND_INREG: { 791 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 792 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 793 break; 794 } 795 case ISD::SELECT_CC: 796 case ISD::SETCC: 797 case ISD::BR_CC: { 798 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 799 Node->getOpcode() == ISD::SETCC ? 2 : 1; 800 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 801 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 802 ISD::CondCode CCCode = 803 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 804 Action = TLI.getCondCodeAction(CCCode, OpVT); 805 if (Action == TargetLowering::Legal) { 806 if (Node->getOpcode() == ISD::SELECT_CC) 807 Action = TLI.getOperationAction(Node->getOpcode(), 808 Node->getValueType(0)); 809 else 810 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 811 } 812 break; 813 } 814 case ISD::LOAD: 815 case ISD::STORE: 816 // FIXME: Model these properly. LOAD and STORE are complicated, and 817 // STORE expects the unlegalized operand in some cases. 818 SimpleFinishLegalizing = false; 819 break; 820 case ISD::CALLSEQ_START: 821 case ISD::CALLSEQ_END: 822 // FIXME: This shouldn't be necessary. These nodes have special properties 823 // dealing with the recursive nature of legalization. Removing this 824 // special case should be done as part of making LegalizeDAG non-recursive. 825 SimpleFinishLegalizing = false; 826 break; 827 case ISD::EXTRACT_ELEMENT: 828 case ISD::FLT_ROUNDS_: 829 case ISD::SADDO: 830 case ISD::SSUBO: 831 case ISD::UADDO: 832 case ISD::USUBO: 833 case ISD::SMULO: 834 case ISD::UMULO: 835 case ISD::FPOWI: 836 case ISD::MERGE_VALUES: 837 case ISD::EH_RETURN: 838 case ISD::FRAME_TO_ARGS_OFFSET: 839 // These operations lie about being legal: when they claim to be legal, 840 // they should actually be expanded. 841 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 842 if (Action == TargetLowering::Legal) 843 Action = TargetLowering::Expand; 844 break; 845 case ISD::TRAMPOLINE: 846 case ISD::FRAMEADDR: 847 case ISD::RETURNADDR: 848 // These operations lie about being legal: when they claim to be legal, 849 // they should actually be custom-lowered. 850 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 851 if (Action == TargetLowering::Legal) 852 Action = TargetLowering::Custom; 853 break; 854 case ISD::BUILD_VECTOR: 855 // A weird case: legalization for BUILD_VECTOR never legalizes the 856 // operands! 857 // FIXME: This really sucks... changing it isn't semantically incorrect, 858 // but it massively pessimizes the code for floating-point BUILD_VECTORs 859 // because ConstantFP operands get legalized into constant pool loads 860 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 861 // though, because BUILD_VECTORS usually get lowered into other nodes 862 // which get legalized properly. 863 SimpleFinishLegalizing = false; 864 break; 865 default: 866 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 867 Action = TargetLowering::Legal; 868 } else { 869 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 870 } 871 break; 872 } 873 874 if (SimpleFinishLegalizing) { 875 SmallVector<SDValue, 8> Ops, ResultVals; 876 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 877 Ops.push_back(LegalizeOp(Node->getOperand(i))); 878 switch (Node->getOpcode()) { 879 default: break; 880 case ISD::BR: 881 case ISD::BRIND: 882 case ISD::BR_JT: 883 case ISD::BR_CC: 884 case ISD::BRCOND: 885 // Branches tweak the chain to include LastCALLSEQ_END 886 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 887 LastCALLSEQ_END); 888 Ops[0] = LegalizeOp(Ops[0]); 889 LastCALLSEQ_END = DAG.getEntryNode(); 890 break; 891 case ISD::SHL: 892 case ISD::SRL: 893 case ISD::SRA: 894 case ISD::ROTL: 895 case ISD::ROTR: 896 // Legalizing shifts/rotates requires adjusting the shift amount 897 // to the appropriate width. 898 if (!Ops[1].getValueType().isVector()) 899 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 900 break; 901 case ISD::SRL_PARTS: 902 case ISD::SRA_PARTS: 903 case ISD::SHL_PARTS: 904 // Legalizing shifts/rotates requires adjusting the shift amount 905 // to the appropriate width. 906 if (!Ops[2].getValueType().isVector()) 907 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2])); 908 break; 909 } 910 911 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(), 912 Ops.size()); 913 switch (Action) { 914 case TargetLowering::Legal: 915 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 916 ResultVals.push_back(Result.getValue(i)); 917 break; 918 case TargetLowering::Custom: 919 // FIXME: The handling for custom lowering with multiple results is 920 // a complete mess. 921 Tmp1 = TLI.LowerOperation(Result, DAG); 922 if (Tmp1.getNode()) { 923 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 924 if (e == 1) 925 ResultVals.push_back(Tmp1); 926 else 927 ResultVals.push_back(Tmp1.getValue(i)); 928 } 929 break; 930 } 931 932 // FALL THROUGH 933 case TargetLowering::Expand: 934 ExpandNode(Result.getNode(), ResultVals); 935 break; 936 case TargetLowering::Promote: 937 PromoteNode(Result.getNode(), ResultVals); 938 break; 939 } 940 if (!ResultVals.empty()) { 941 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 942 if (ResultVals[i] != SDValue(Node, i)) 943 ResultVals[i] = LegalizeOp(ResultVals[i]); 944 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 945 } 946 return ResultVals[Op.getResNo()]; 947 } 948 } 949 950 switch (Node->getOpcode()) { 951 default: 952#ifndef NDEBUG 953 errs() << "NODE: "; 954 Node->dump(&DAG); 955 errs() << "\n"; 956#endif 957 llvm_unreachable("Do not know how to legalize this operator!"); 958 959 case ISD::BUILD_VECTOR: 960 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 961 default: llvm_unreachable("This action is not supported yet!"); 962 case TargetLowering::Custom: 963 Tmp3 = TLI.LowerOperation(Result, DAG); 964 if (Tmp3.getNode()) { 965 Result = Tmp3; 966 break; 967 } 968 // FALLTHROUGH 969 case TargetLowering::Expand: 970 Result = ExpandBUILD_VECTOR(Result.getNode()); 971 break; 972 } 973 break; 974 case ISD::CALLSEQ_START: { 975 SDNode *CallEnd = FindCallEndFromCallStart(Node); 976 977 // Recursively Legalize all of the inputs of the call end that do not lead 978 // to this call start. This ensures that any libcalls that need be inserted 979 // are inserted *before* the CALLSEQ_START. 980 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 981 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 982 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 983 NodesLeadingTo); 984 } 985 986 // Now that we legalized all of the inputs (which may have inserted 987 // libcalls) create the new CALLSEQ_START node. 988 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 989 990 // Merge in the last call, to ensure that this call start after the last 991 // call ended. 992 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 993 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 994 Tmp1, LastCALLSEQ_END); 995 Tmp1 = LegalizeOp(Tmp1); 996 } 997 998 // Do not try to legalize the target-specific arguments (#1+). 999 if (Tmp1 != Node->getOperand(0)) { 1000 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1001 Ops[0] = Tmp1; 1002 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1003 } 1004 1005 // Remember that the CALLSEQ_START is legalized. 1006 AddLegalizedOperand(Op.getValue(0), Result); 1007 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1008 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1009 1010 // Now that the callseq_start and all of the non-call nodes above this call 1011 // sequence have been legalized, legalize the call itself. During this 1012 // process, no libcalls can/will be inserted, guaranteeing that no calls 1013 // can overlap. 1014 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1015 // Note that we are selecting this call! 1016 LastCALLSEQ_END = SDValue(CallEnd, 0); 1017 IsLegalizingCall = true; 1018 1019 // Legalize the call, starting from the CALLSEQ_END. 1020 LegalizeOp(LastCALLSEQ_END); 1021 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1022 return Result; 1023 } 1024 case ISD::CALLSEQ_END: 1025 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1026 // will cause this node to be legalized as well as handling libcalls right. 1027 if (LastCALLSEQ_END.getNode() != Node) { 1028 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1029 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1030 assert(I != LegalizedNodes.end() && 1031 "Legalizing the call start should have legalized this node!"); 1032 return I->second; 1033 } 1034 1035 // Otherwise, the call start has been legalized and everything is going 1036 // according to plan. Just legalize ourselves normally here. 1037 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1038 // Do not try to legalize the target-specific arguments (#1+), except for 1039 // an optional flag input. 1040 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1041 if (Tmp1 != Node->getOperand(0)) { 1042 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1043 Ops[0] = Tmp1; 1044 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1045 } 1046 } else { 1047 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1048 if (Tmp1 != Node->getOperand(0) || 1049 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1050 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1051 Ops[0] = Tmp1; 1052 Ops.back() = Tmp2; 1053 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1054 } 1055 } 1056 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1057 // This finishes up call legalization. 1058 IsLegalizingCall = false; 1059 1060 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1061 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1062 if (Node->getNumValues() == 2) 1063 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1064 return Result.getValue(Op.getResNo()); 1065 case ISD::LOAD: { 1066 LoadSDNode *LD = cast<LoadSDNode>(Node); 1067 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1068 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1069 1070 ISD::LoadExtType ExtType = LD->getExtensionType(); 1071 if (ExtType == ISD::NON_EXTLOAD) { 1072 EVT VT = Node->getValueType(0); 1073 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1074 Tmp3 = Result.getValue(0); 1075 Tmp4 = Result.getValue(1); 1076 1077 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1078 default: llvm_unreachable("This action is not supported yet!"); 1079 case TargetLowering::Legal: 1080 // If this is an unaligned load and the target doesn't support it, 1081 // expand it. 1082 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1083 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1084 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1085 if (LD->getAlignment() < ABIAlignment){ 1086 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1087 DAG, TLI); 1088 Tmp3 = Result.getOperand(0); 1089 Tmp4 = Result.getOperand(1); 1090 Tmp3 = LegalizeOp(Tmp3); 1091 Tmp4 = LegalizeOp(Tmp4); 1092 } 1093 } 1094 break; 1095 case TargetLowering::Custom: 1096 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1097 if (Tmp1.getNode()) { 1098 Tmp3 = LegalizeOp(Tmp1); 1099 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1100 } 1101 break; 1102 case TargetLowering::Promote: { 1103 // Only promote a load of vector type to another. 1104 assert(VT.isVector() && "Cannot promote this load!"); 1105 // Change base type to a different vector type. 1106 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1107 1108 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1109 LD->getSrcValueOffset(), 1110 LD->isVolatile(), LD->getAlignment()); 1111 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1112 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1113 break; 1114 } 1115 } 1116 // Since loads produce two values, make sure to remember that we 1117 // legalized both of them. 1118 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1119 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1120 return Op.getResNo() ? Tmp4 : Tmp3; 1121 } else { 1122 EVT SrcVT = LD->getMemoryVT(); 1123 unsigned SrcWidth = SrcVT.getSizeInBits(); 1124 int SVOffset = LD->getSrcValueOffset(); 1125 unsigned Alignment = LD->getAlignment(); 1126 bool isVolatile = LD->isVolatile(); 1127 1128 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1129 // Some targets pretend to have an i1 loading operation, and actually 1130 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1131 // bits are guaranteed to be zero; it helps the optimizers understand 1132 // that these bits are zero. It is also useful for EXTLOAD, since it 1133 // tells the optimizers that those bits are undefined. It would be 1134 // nice to have an effective generic way of getting these benefits... 1135 // Until such a way is found, don't insist on promoting i1 here. 1136 (SrcVT != MVT::i1 || 1137 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1138 // Promote to a byte-sized load if not loading an integral number of 1139 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1140 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1141 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 1142 SDValue Ch; 1143 1144 // The extra bits are guaranteed to be zero, since we stored them that 1145 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1146 1147 ISD::LoadExtType NewExtType = 1148 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1149 1150 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 1151 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1152 NVT, isVolatile, Alignment); 1153 1154 Ch = Result.getValue(1); // The chain. 1155 1156 if (ExtType == ISD::SEXTLOAD) 1157 // Having the top bits zero doesn't help when sign extending. 1158 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1159 Result.getValueType(), 1160 Result, DAG.getValueType(SrcVT)); 1161 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1162 // All the top bits are guaranteed to be zero - inform the optimizers. 1163 Result = DAG.getNode(ISD::AssertZext, dl, 1164 Result.getValueType(), Result, 1165 DAG.getValueType(SrcVT)); 1166 1167 Tmp1 = LegalizeOp(Result); 1168 Tmp2 = LegalizeOp(Ch); 1169 } else if (SrcWidth & (SrcWidth - 1)) { 1170 // If not loading a power-of-2 number of bits, expand as two loads. 1171 assert(SrcVT.isExtended() && !SrcVT.isVector() && 1172 "Unsupported extload!"); 1173 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1174 assert(RoundWidth < SrcWidth); 1175 unsigned ExtraWidth = SrcWidth - RoundWidth; 1176 assert(ExtraWidth < RoundWidth); 1177 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1178 "Load size not an integral number of bytes!"); 1179 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1180 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1181 SDValue Lo, Hi, Ch; 1182 unsigned IncrementSize; 1183 1184 if (TLI.isLittleEndian()) { 1185 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1186 // Load the bottom RoundWidth bits. 1187 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1188 Node->getValueType(0), Tmp1, Tmp2, 1189 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1190 Alignment); 1191 1192 // Load the remaining ExtraWidth bits. 1193 IncrementSize = RoundWidth / 8; 1194 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1195 DAG.getIntPtrConstant(IncrementSize)); 1196 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1197 LD->getSrcValue(), SVOffset + IncrementSize, 1198 ExtraVT, isVolatile, 1199 MinAlign(Alignment, IncrementSize)); 1200 1201 // Build a factor node to remember that this load is independent of the 1202 // other one. 1203 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1204 Hi.getValue(1)); 1205 1206 // Move the top bits to the right place. 1207 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1208 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1209 1210 // Join the hi and lo parts. 1211 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1212 } else { 1213 // Big endian - avoid unaligned loads. 1214 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1215 // Load the top RoundWidth bits. 1216 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1217 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1218 Alignment); 1219 1220 // Load the remaining ExtraWidth bits. 1221 IncrementSize = RoundWidth / 8; 1222 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1223 DAG.getIntPtrConstant(IncrementSize)); 1224 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1225 Node->getValueType(0), Tmp1, Tmp2, 1226 LD->getSrcValue(), SVOffset + IncrementSize, 1227 ExtraVT, isVolatile, 1228 MinAlign(Alignment, IncrementSize)); 1229 1230 // Build a factor node to remember that this load is independent of the 1231 // other one. 1232 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1233 Hi.getValue(1)); 1234 1235 // Move the top bits to the right place. 1236 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1237 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1238 1239 // Join the hi and lo parts. 1240 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1241 } 1242 1243 Tmp1 = LegalizeOp(Result); 1244 Tmp2 = LegalizeOp(Ch); 1245 } else { 1246 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1247 default: llvm_unreachable("This action is not supported yet!"); 1248 case TargetLowering::Custom: 1249 isCustom = true; 1250 // FALLTHROUGH 1251 case TargetLowering::Legal: 1252 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1253 Tmp1 = Result.getValue(0); 1254 Tmp2 = Result.getValue(1); 1255 1256 if (isCustom) { 1257 Tmp3 = TLI.LowerOperation(Result, DAG); 1258 if (Tmp3.getNode()) { 1259 Tmp1 = LegalizeOp(Tmp3); 1260 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1261 } 1262 } else { 1263 // If this is an unaligned load and the target doesn't support it, 1264 // expand it. 1265 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1266 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1267 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1268 if (LD->getAlignment() < ABIAlignment){ 1269 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1270 DAG, TLI); 1271 Tmp1 = Result.getOperand(0); 1272 Tmp2 = Result.getOperand(1); 1273 Tmp1 = LegalizeOp(Tmp1); 1274 Tmp2 = LegalizeOp(Tmp2); 1275 } 1276 } 1277 } 1278 break; 1279 case TargetLowering::Expand: 1280 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1281 // f128 = EXTLOAD {f32,f64} too 1282 if ((SrcVT == MVT::f32 && (Node->getValueType(0) == MVT::f64 || 1283 Node->getValueType(0) == MVT::f128)) || 1284 (SrcVT == MVT::f64 && Node->getValueType(0) == MVT::f128)) { 1285 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1286 LD->getSrcValueOffset(), 1287 LD->isVolatile(), LD->getAlignment()); 1288 Result = DAG.getNode(ISD::FP_EXTEND, dl, 1289 Node->getValueType(0), Load); 1290 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1291 Tmp2 = LegalizeOp(Load.getValue(1)); 1292 break; 1293 } 1294 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1295 // Turn the unsupported load into an EXTLOAD followed by an explicit 1296 // zero/sign extend inreg. 1297 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1298 Tmp1, Tmp2, LD->getSrcValue(), 1299 LD->getSrcValueOffset(), SrcVT, 1300 LD->isVolatile(), LD->getAlignment()); 1301 SDValue ValRes; 1302 if (ExtType == ISD::SEXTLOAD) 1303 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1304 Result.getValueType(), 1305 Result, DAG.getValueType(SrcVT)); 1306 else 1307 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1308 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1309 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1310 break; 1311 } 1312 } 1313 1314 // Since loads produce two values, make sure to remember that we legalized 1315 // both of them. 1316 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1317 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1318 return Op.getResNo() ? Tmp2 : Tmp1; 1319 } 1320 } 1321 case ISD::STORE: { 1322 StoreSDNode *ST = cast<StoreSDNode>(Node); 1323 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1324 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1325 int SVOffset = ST->getSrcValueOffset(); 1326 unsigned Alignment = ST->getAlignment(); 1327 bool isVolatile = ST->isVolatile(); 1328 1329 if (!ST->isTruncatingStore()) { 1330 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1331 Result = SDValue(OptStore, 0); 1332 break; 1333 } 1334 1335 { 1336 Tmp3 = LegalizeOp(ST->getValue()); 1337 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1338 ST->getOffset()); 1339 1340 EVT VT = Tmp3.getValueType(); 1341 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1342 default: llvm_unreachable("This action is not supported yet!"); 1343 case TargetLowering::Legal: 1344 // If this is an unaligned store and the target doesn't support it, 1345 // expand it. 1346 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1347 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1348 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1349 if (ST->getAlignment() < ABIAlignment) 1350 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1351 DAG, TLI); 1352 } 1353 break; 1354 case TargetLowering::Custom: 1355 Tmp1 = TLI.LowerOperation(Result, DAG); 1356 if (Tmp1.getNode()) Result = Tmp1; 1357 break; 1358 case TargetLowering::Promote: 1359 assert(VT.isVector() && "Unknown legal promote case!"); 1360 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1361 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1362 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1363 ST->getSrcValue(), SVOffset, isVolatile, 1364 Alignment); 1365 break; 1366 } 1367 break; 1368 } 1369 } else { 1370 Tmp3 = LegalizeOp(ST->getValue()); 1371 1372 EVT StVT = ST->getMemoryVT(); 1373 unsigned StWidth = StVT.getSizeInBits(); 1374 1375 if (StWidth != StVT.getStoreSizeInBits()) { 1376 // Promote to a byte-sized store with upper bits zero if not 1377 // storing an integral number of bytes. For example, promote 1378 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1379 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StVT.getStoreSizeInBits()); 1380 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1381 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1382 SVOffset, NVT, isVolatile, Alignment); 1383 } else if (StWidth & (StWidth - 1)) { 1384 // If not storing a power-of-2 number of bits, expand as two stores. 1385 assert(StVT.isExtended() && !StVT.isVector() && 1386 "Unsupported truncstore!"); 1387 unsigned RoundWidth = 1 << Log2_32(StWidth); 1388 assert(RoundWidth < StWidth); 1389 unsigned ExtraWidth = StWidth - RoundWidth; 1390 assert(ExtraWidth < RoundWidth); 1391 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1392 "Store size not an integral number of bytes!"); 1393 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1394 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1395 SDValue Lo, Hi; 1396 unsigned IncrementSize; 1397 1398 if (TLI.isLittleEndian()) { 1399 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1400 // Store the bottom RoundWidth bits. 1401 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1402 SVOffset, RoundVT, 1403 isVolatile, Alignment); 1404 1405 // Store the remaining ExtraWidth bits. 1406 IncrementSize = RoundWidth / 8; 1407 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1408 DAG.getIntPtrConstant(IncrementSize)); 1409 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1410 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1411 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1412 SVOffset + IncrementSize, ExtraVT, isVolatile, 1413 MinAlign(Alignment, IncrementSize)); 1414 } else { 1415 // Big endian - avoid unaligned stores. 1416 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1417 // Store the top RoundWidth bits. 1418 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1419 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1420 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1421 SVOffset, RoundVT, isVolatile, Alignment); 1422 1423 // Store the remaining ExtraWidth bits. 1424 IncrementSize = RoundWidth / 8; 1425 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1426 DAG.getIntPtrConstant(IncrementSize)); 1427 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1428 SVOffset + IncrementSize, ExtraVT, isVolatile, 1429 MinAlign(Alignment, IncrementSize)); 1430 } 1431 1432 // The order of the stores doesn't matter. 1433 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1434 } else { 1435 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1436 Tmp2 != ST->getBasePtr()) 1437 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1438 ST->getOffset()); 1439 1440 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1441 default: llvm_unreachable("This action is not supported yet!"); 1442 case TargetLowering::Legal: 1443 // If this is an unaligned store and the target doesn't support it, 1444 // expand it. 1445 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1446 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1447 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1448 if (ST->getAlignment() < ABIAlignment) 1449 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1450 DAG, TLI); 1451 } 1452 break; 1453 case TargetLowering::Custom: 1454 Result = TLI.LowerOperation(Result, DAG); 1455 break; 1456 case Expand: 1457 // TRUNCSTORE:i16 i32 -> STORE i16 1458 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1459 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1460 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1461 SVOffset, isVolatile, Alignment); 1462 break; 1463 } 1464 } 1465 } 1466 break; 1467 } 1468 } 1469 assert(Result.getValueType() == Op.getValueType() && 1470 "Bad legalization!"); 1471 1472 // Make sure that the generated code is itself legal. 1473 if (Result != Op) 1474 Result = LegalizeOp(Result); 1475 1476 // Note that LegalizeOp may be reentered even from single-use nodes, which 1477 // means that we always must cache transformed nodes. 1478 AddLegalizedOperand(Op, Result); 1479 return Result; 1480} 1481 1482SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1483 SDValue Vec = Op.getOperand(0); 1484 SDValue Idx = Op.getOperand(1); 1485 DebugLoc dl = Op.getDebugLoc(); 1486 // Store the value to a temporary stack slot, then LOAD the returned part. 1487 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1488 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0); 1489 1490 // Add the offset to the index. 1491 unsigned EltSize = 1492 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1493 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1494 DAG.getConstant(EltSize, Idx.getValueType())); 1495 1496 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1497 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1498 else 1499 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1500 1501 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1502 1503 if (Op.getValueType().isVector()) 1504 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0); 1505 else 1506 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1507 NULL, 0, Vec.getValueType().getVectorElementType()); 1508} 1509 1510SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1511 // We can't handle this case efficiently. Allocate a sufficiently 1512 // aligned object on the stack, store each element into it, then load 1513 // the result as a vector. 1514 // Create the stack frame object. 1515 EVT VT = Node->getValueType(0); 1516 EVT OpVT = Node->getOperand(0).getValueType(); 1517 DebugLoc dl = Node->getDebugLoc(); 1518 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1519 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1520 const Value *SV = PseudoSourceValue::getFixedStack(FI); 1521 1522 // Emit a store of each element to the stack slot. 1523 SmallVector<SDValue, 8> Stores; 1524 unsigned TypeByteSize = OpVT.getSizeInBits() / 8; 1525 // Store (in the right endianness) the elements to memory. 1526 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1527 // Ignore undef elements. 1528 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1529 1530 unsigned Offset = TypeByteSize*i; 1531 1532 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1533 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1534 1535 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i), 1536 Idx, SV, Offset)); 1537 } 1538 1539 SDValue StoreChain; 1540 if (!Stores.empty()) // Not all undef elements? 1541 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1542 &Stores[0], Stores.size()); 1543 else 1544 StoreChain = DAG.getEntryNode(); 1545 1546 // Result is a load from the stack slot. 1547 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0); 1548} 1549 1550SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1551 DebugLoc dl = Node->getDebugLoc(); 1552 SDValue Tmp1 = Node->getOperand(0); 1553 SDValue Tmp2 = Node->getOperand(1); 1554 assert((Tmp2.getValueType() == MVT::f32 || 1555 Tmp2.getValueType() == MVT::f64) && 1556 "Ugly special-cased code!"); 1557 // Get the sign bit of the RHS. 1558 SDValue SignBit; 1559 EVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32; 1560 if (isTypeLegal(IVT)) { 1561 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1562 } else { 1563 assert(isTypeLegal(TLI.getPointerTy()) && 1564 (TLI.getPointerTy() == MVT::i32 || 1565 TLI.getPointerTy() == MVT::i64) && 1566 "Legal type for load?!"); 1567 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType()); 1568 SDValue StorePtr = StackPtr, LoadPtr = StackPtr; 1569 SDValue Ch = 1570 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0); 1571 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian()) 1572 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), 1573 LoadPtr, DAG.getIntPtrConstant(4)); 1574 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(), 1575 Ch, LoadPtr, NULL, 0, MVT::i32); 1576 } 1577 SignBit = 1578 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1579 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1580 ISD::SETLT); 1581 // Get the absolute value of the result. 1582 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1583 // Select between the nabs and abs value based on the sign bit of 1584 // the input. 1585 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1586 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1587 AbsVal); 1588} 1589 1590SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) { 1591 DebugLoc dl = Node->getDebugLoc(); 1592 DwarfWriter *DW = DAG.getDwarfWriter(); 1593 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, 1594 MVT::Other); 1595 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); 1596 1597 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1598 MDNode *CU_Node = DSP->getCompileUnit(); 1599 if (DW && (useDEBUG_LOC || useLABEL)) { 1600 1601 unsigned Line = DSP->getLine(); 1602 unsigned Col = DSP->getColumn(); 1603 1604 if (OptLevel == CodeGenOpt::None) { 1605 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it 1606 // won't hurt anything. 1607 if (useDEBUG_LOC) { 1608 return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0), 1609 DAG.getConstant(Line, MVT::i32), 1610 DAG.getConstant(Col, MVT::i32), 1611 DAG.getSrcValue(CU_Node)); 1612 } else { 1613 unsigned ID = DW->RecordSourceLine(Line, Col, CU_Node); 1614 return DAG.getLabel(ISD::DBG_LABEL, dl, Node->getOperand(0), ID); 1615 } 1616 } 1617 } 1618 return Node->getOperand(0); 1619} 1620 1621void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1622 SmallVectorImpl<SDValue> &Results) { 1623 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1624 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1625 " not tell us which reg is the stack pointer!"); 1626 DebugLoc dl = Node->getDebugLoc(); 1627 EVT VT = Node->getValueType(0); 1628 SDValue Tmp1 = SDValue(Node, 0); 1629 SDValue Tmp2 = SDValue(Node, 1); 1630 SDValue Tmp3 = Node->getOperand(2); 1631 SDValue Chain = Tmp1.getOperand(0); 1632 1633 // Chain the dynamic stack allocation so that it doesn't modify the stack 1634 // pointer when other instructions are using the stack. 1635 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1636 1637 SDValue Size = Tmp2.getOperand(1); 1638 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1639 Chain = SP.getValue(1); 1640 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1641 unsigned StackAlign = 1642 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1643 if (Align > StackAlign) 1644 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1645 DAG.getConstant(-(uint64_t)Align, VT)); 1646 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1647 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1648 1649 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1650 DAG.getIntPtrConstant(0, true), SDValue()); 1651 1652 Results.push_back(Tmp1); 1653 Results.push_back(Tmp2); 1654} 1655 1656/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1657/// condition code CC on the current target. This routine expands SETCC with 1658/// illegal condition code into AND / OR of multiple SETCC values. 1659void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1660 SDValue &LHS, SDValue &RHS, 1661 SDValue &CC, 1662 DebugLoc dl) { 1663 EVT OpVT = LHS.getValueType(); 1664 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1665 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1666 default: llvm_unreachable("Unknown condition code action!"); 1667 case TargetLowering::Legal: 1668 // Nothing to do. 1669 break; 1670 case TargetLowering::Expand: { 1671 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1672 unsigned Opc = 0; 1673 switch (CCCode) { 1674 default: llvm_unreachable("Don't know how to expand this condition!"); 1675 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1676 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1677 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1678 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1679 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1680 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1681 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1682 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1683 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1684 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1685 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1686 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1687 // FIXME: Implement more expansions. 1688 } 1689 1690 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1691 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1692 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1693 RHS = SDValue(); 1694 CC = SDValue(); 1695 break; 1696 } 1697 } 1698} 1699 1700/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1701/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1702/// a load from the stack slot to DestVT, extending it if needed. 1703/// The resultant code need not be legal. 1704SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1705 EVT SlotVT, 1706 EVT DestVT, 1707 DebugLoc dl) { 1708 // Create the stack frame object. 1709 unsigned SrcAlign = 1710 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1711 getTypeForEVT(*DAG.getContext())); 1712 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1713 1714 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1715 int SPFI = StackPtrFI->getIndex(); 1716 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1717 1718 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1719 unsigned SlotSize = SlotVT.getSizeInBits(); 1720 unsigned DestSize = DestVT.getSizeInBits(); 1721 unsigned DestAlign = 1722 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT(*DAG.getContext())); 1723 1724 // Emit a store to the stack slot. Use a truncstore if the input value is 1725 // later than DestVT. 1726 SDValue Store; 1727 1728 if (SrcSize > SlotSize) 1729 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1730 SV, 0, SlotVT, false, SrcAlign); 1731 else { 1732 assert(SrcSize == SlotSize && "Invalid store"); 1733 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1734 SV, 0, false, SrcAlign); 1735 } 1736 1737 // Result is a load from the stack slot. 1738 if (SlotSize == DestSize) 1739 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign); 1740 1741 assert(SlotSize < DestSize && "Unknown extension!"); 1742 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, 1743 false, DestAlign); 1744} 1745 1746SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1747 DebugLoc dl = Node->getDebugLoc(); 1748 // Create a vector sized/aligned stack slot, store the value to element #0, 1749 // then load the whole vector back out. 1750 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1751 1752 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1753 int SPFI = StackPtrFI->getIndex(); 1754 1755 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1756 StackPtr, 1757 PseudoSourceValue::getFixedStack(SPFI), 0, 1758 Node->getValueType(0).getVectorElementType()); 1759 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1760 PseudoSourceValue::getFixedStack(SPFI), 0); 1761} 1762 1763 1764/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1765/// support the operation, but do support the resultant vector type. 1766SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1767 unsigned NumElems = Node->getNumOperands(); 1768 SDValue Value1, Value2; 1769 DebugLoc dl = Node->getDebugLoc(); 1770 EVT VT = Node->getValueType(0); 1771 EVT OpVT = Node->getOperand(0).getValueType(); 1772 EVT EltVT = VT.getVectorElementType(); 1773 1774 // If the only non-undef value is the low element, turn this into a 1775 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1776 bool isOnlyLowElement = true; 1777 bool MoreThanTwoValues = false; 1778 bool isConstant = true; 1779 for (unsigned i = 0; i < NumElems; ++i) { 1780 SDValue V = Node->getOperand(i); 1781 if (V.getOpcode() == ISD::UNDEF) 1782 continue; 1783 if (i > 0) 1784 isOnlyLowElement = false; 1785 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1786 isConstant = false; 1787 1788 if (!Value1.getNode()) { 1789 Value1 = V; 1790 } else if (!Value2.getNode()) { 1791 if (V != Value1) 1792 Value2 = V; 1793 } else if (V != Value1 && V != Value2) { 1794 MoreThanTwoValues = true; 1795 } 1796 } 1797 1798 if (!Value1.getNode()) 1799 return DAG.getUNDEF(VT); 1800 1801 if (isOnlyLowElement) 1802 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1803 1804 // If all elements are constants, create a load from the constant pool. 1805 if (isConstant) { 1806 std::vector<Constant*> CV; 1807 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1808 if (ConstantFPSDNode *V = 1809 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1810 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1811 } else if (ConstantSDNode *V = 1812 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1813 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1814 } else { 1815 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1816 const Type *OpNTy = OpVT.getTypeForEVT(*DAG.getContext()); 1817 CV.push_back(UndefValue::get(OpNTy)); 1818 } 1819 } 1820 Constant *CP = ConstantVector::get(CV); 1821 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1822 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1823 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1824 PseudoSourceValue::getConstantPool(), 0, 1825 false, Alignment); 1826 } 1827 1828 if (!MoreThanTwoValues) { 1829 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1830 for (unsigned i = 0; i < NumElems; ++i) { 1831 SDValue V = Node->getOperand(i); 1832 if (V.getOpcode() == ISD::UNDEF) 1833 continue; 1834 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1835 } 1836 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1837 // Get the splatted value into the low element of a vector register. 1838 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1839 SDValue Vec2; 1840 if (Value2.getNode()) 1841 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1842 else 1843 Vec2 = DAG.getUNDEF(VT); 1844 1845 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1846 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1847 } 1848 } 1849 1850 // Otherwise, we can't handle this case efficiently. 1851 return ExpandVectorBuildThroughStack(Node); 1852} 1853 1854// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1855// does not fit into a register, return the lo part and set the hi part to the 1856// by-reg argument. If it does fit into a single register, return the result 1857// and leave the Hi part unset. 1858SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1859 bool isSigned) { 1860 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1861 // The input chain to this libcall is the entry node of the function. 1862 // Legalizing the call will automatically add the previous call to the 1863 // dependence. 1864 SDValue InChain = DAG.getEntryNode(); 1865 1866 TargetLowering::ArgListTy Args; 1867 TargetLowering::ArgListEntry Entry; 1868 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1869 EVT ArgVT = Node->getOperand(i).getValueType(); 1870 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1871 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1872 Entry.isSExt = isSigned; 1873 Entry.isZExt = !isSigned; 1874 Args.push_back(Entry); 1875 } 1876 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1877 TLI.getPointerTy()); 1878 1879 // Splice the libcall in wherever FindInputOutputChains tells us to. 1880 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1881 std::pair<SDValue, SDValue> CallInfo = 1882 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1883 0, TLI.getLibcallCallingConv(LC), false, 1884 /*isReturnValueUsed=*/true, 1885 Callee, Args, DAG, 1886 Node->getDebugLoc()); 1887 1888 // Legalize the call sequence, starting with the chain. This will advance 1889 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1890 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1891 LegalizeOp(CallInfo.second); 1892 return CallInfo.first; 1893} 1894 1895SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1896 RTLIB::Libcall Call_F32, 1897 RTLIB::Libcall Call_F64, 1898 RTLIB::Libcall Call_F80, 1899 RTLIB::Libcall Call_PPCF128) { 1900 RTLIB::Libcall LC; 1901 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1902 default: llvm_unreachable("Unexpected request for libcall!"); 1903 case MVT::f32: LC = Call_F32; break; 1904 case MVT::f64: LC = Call_F64; break; 1905 case MVT::f80: LC = Call_F80; break; 1906 case MVT::ppcf128: LC = Call_PPCF128; break; 1907 } 1908 return ExpandLibCall(LC, Node, false); 1909} 1910 1911SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 1912 RTLIB::Libcall Call_I16, 1913 RTLIB::Libcall Call_I32, 1914 RTLIB::Libcall Call_I64, 1915 RTLIB::Libcall Call_I128) { 1916 RTLIB::Libcall LC; 1917 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1918 default: llvm_unreachable("Unexpected request for libcall!"); 1919 case MVT::i16: LC = Call_I16; break; 1920 case MVT::i32: LC = Call_I32; break; 1921 case MVT::i64: LC = Call_I64; break; 1922 case MVT::i128: LC = Call_I128; break; 1923 } 1924 return ExpandLibCall(LC, Node, isSigned); 1925} 1926 1927/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 1928/// INT_TO_FP operation of the specified operand when the target requests that 1929/// we expand it. At this point, we know that the result and operand types are 1930/// legal for the target. 1931SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 1932 SDValue Op0, 1933 EVT DestVT, 1934 DebugLoc dl) { 1935 if (Op0.getValueType() == MVT::i32) { 1936 // simple 32-bit [signed|unsigned] integer to float/double expansion 1937 1938 // Get the stack frame index of a 8 byte buffer. 1939 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 1940 1941 // word offset constant for Hi/Lo address computation 1942 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 1943 // set up Hi and Lo (into buffer) address based on endian 1944 SDValue Hi = StackSlot; 1945 SDValue Lo = DAG.getNode(ISD::ADD, dl, 1946 TLI.getPointerTy(), StackSlot, WordOff); 1947 if (TLI.isLittleEndian()) 1948 std::swap(Hi, Lo); 1949 1950 // if signed map to unsigned space 1951 SDValue Op0Mapped; 1952 if (isSigned) { 1953 // constant used to invert sign bit (signed to unsigned mapping) 1954 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 1955 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 1956 } else { 1957 Op0Mapped = Op0; 1958 } 1959 // store the lo of the constructed double - based on integer input 1960 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 1961 Op0Mapped, Lo, NULL, 0); 1962 // initial hi portion of constructed double 1963 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 1964 // store the hi of the constructed double - biased exponent 1965 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0); 1966 // load the constructed double 1967 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0); 1968 // FP constant to bias correct the final result 1969 SDValue Bias = DAG.getConstantFP(isSigned ? 1970 BitsToDouble(0x4330000080000000ULL) : 1971 BitsToDouble(0x4330000000000000ULL), 1972 MVT::f64); 1973 // subtract the bias 1974 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 1975 // final result 1976 SDValue Result; 1977 // handle final rounding 1978 if (DestVT == MVT::f64) { 1979 // do nothing 1980 Result = Sub; 1981 } else if (DestVT.bitsLT(MVT::f64)) { 1982 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 1983 DAG.getIntPtrConstant(0)); 1984 } else if (DestVT.bitsGT(MVT::f64)) { 1985 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 1986 } 1987 return Result; 1988 } 1989 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 1990 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 1991 1992 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 1993 Op0, DAG.getConstant(0, Op0.getValueType()), 1994 ISD::SETLT); 1995 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 1996 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 1997 SignSet, Four, Zero); 1998 1999 // If the sign bit of the integer is set, the large number will be treated 2000 // as a negative number. To counteract this, the dynamic code adds an 2001 // offset depending on the data type. 2002 uint64_t FF; 2003 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2004 default: llvm_unreachable("Unsupported integer type!"); 2005 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2006 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2007 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2008 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2009 } 2010 if (TLI.isLittleEndian()) FF <<= 32; 2011 Constant *FudgeFactor = ConstantInt::get( 2012 Type::getInt64Ty(*DAG.getContext()), FF); 2013 2014 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2015 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2016 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2017 Alignment = std::min(Alignment, 4u); 2018 SDValue FudgeInReg; 2019 if (DestVT == MVT::f32) 2020 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2021 PseudoSourceValue::getConstantPool(), 0, 2022 false, Alignment); 2023 else { 2024 FudgeInReg = 2025 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2026 DAG.getEntryNode(), CPIdx, 2027 PseudoSourceValue::getConstantPool(), 0, 2028 MVT::f32, false, Alignment)); 2029 } 2030 2031 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2032} 2033 2034/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2035/// *INT_TO_FP operation of the specified operand when the target requests that 2036/// we promote it. At this point, we know that the result and operand types are 2037/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2038/// operation that takes a larger input. 2039SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2040 EVT DestVT, 2041 bool isSigned, 2042 DebugLoc dl) { 2043 // First step, figure out the appropriate *INT_TO_FP operation to use. 2044 EVT NewInTy = LegalOp.getValueType(); 2045 2046 unsigned OpToUse = 0; 2047 2048 // Scan for the appropriate larger type to use. 2049 while (1) { 2050 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2051 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2052 2053 // If the target supports SINT_TO_FP of this type, use it. 2054 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2055 OpToUse = ISD::SINT_TO_FP; 2056 break; 2057 } 2058 if (isSigned) continue; 2059 2060 // If the target supports UINT_TO_FP of this type, use it. 2061 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2062 OpToUse = ISD::UINT_TO_FP; 2063 break; 2064 } 2065 2066 // Otherwise, try a larger type. 2067 } 2068 2069 // Okay, we found the operation and type to use. Zero extend our input to the 2070 // desired type then run the operation on it. 2071 return DAG.getNode(OpToUse, dl, DestVT, 2072 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2073 dl, NewInTy, LegalOp)); 2074} 2075 2076/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2077/// FP_TO_*INT operation of the specified operand when the target requests that 2078/// we promote it. At this point, we know that the result and operand types are 2079/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2080/// operation that returns a larger result. 2081SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2082 EVT DestVT, 2083 bool isSigned, 2084 DebugLoc dl) { 2085 // First step, figure out the appropriate FP_TO*INT operation to use. 2086 EVT NewOutTy = DestVT; 2087 2088 unsigned OpToUse = 0; 2089 2090 // Scan for the appropriate larger type to use. 2091 while (1) { 2092 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2093 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2094 2095 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2096 OpToUse = ISD::FP_TO_SINT; 2097 break; 2098 } 2099 2100 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2101 OpToUse = ISD::FP_TO_UINT; 2102 break; 2103 } 2104 2105 // Otherwise, try a larger type. 2106 } 2107 2108 2109 // Okay, we found the operation and type to use. 2110 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2111 2112 // Truncate the result of the extended FP_TO_*INT operation to the desired 2113 // size. 2114 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2115} 2116 2117/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2118/// 2119SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2120 EVT VT = Op.getValueType(); 2121 EVT SHVT = TLI.getShiftAmountTy(); 2122 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2123 switch (VT.getSimpleVT().SimpleTy) { 2124 default: llvm_unreachable("Unhandled Expand type in BSWAP!"); 2125 case MVT::i16: 2126 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2127 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2128 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2129 case MVT::i32: 2130 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2131 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2132 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2133 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2134 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2135 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2136 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2137 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2138 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2139 case MVT::i64: 2140 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2141 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2142 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2143 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2144 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2145 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2146 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2147 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2148 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2149 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2150 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2151 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2152 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2153 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2154 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2155 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2156 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2157 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2158 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2159 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2160 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2161 } 2162} 2163 2164/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2165/// 2166SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2167 DebugLoc dl) { 2168 switch (Opc) { 2169 default: llvm_unreachable("Cannot expand this yet!"); 2170 case ISD::CTPOP: { 2171 static const uint64_t mask[6] = { 2172 0x5555555555555555ULL, 0x3333333333333333ULL, 2173 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2174 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2175 }; 2176 EVT VT = Op.getValueType(); 2177 EVT ShVT = TLI.getShiftAmountTy(); 2178 unsigned len = VT.getSizeInBits(); 2179 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2180 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2181 unsigned EltSize = VT.isVector() ? 2182 VT.getVectorElementType().getSizeInBits() : len; 2183 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2184 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2185 Op = DAG.getNode(ISD::ADD, dl, VT, 2186 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2187 DAG.getNode(ISD::AND, dl, VT, 2188 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2189 Tmp2)); 2190 } 2191 return Op; 2192 } 2193 case ISD::CTLZ: { 2194 // for now, we do this: 2195 // x = x | (x >> 1); 2196 // x = x | (x >> 2); 2197 // ... 2198 // x = x | (x >>16); 2199 // x = x | (x >>32); // for 64-bit input 2200 // return popcount(~x); 2201 // 2202 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2203 EVT VT = Op.getValueType(); 2204 EVT ShVT = TLI.getShiftAmountTy(); 2205 unsigned len = VT.getSizeInBits(); 2206 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2207 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2208 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2209 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2210 } 2211 Op = DAG.getNOT(dl, Op, VT); 2212 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2213 } 2214 case ISD::CTTZ: { 2215 // for now, we use: { return popcount(~x & (x - 1)); } 2216 // unless the target has ctlz but not ctpop, in which case we use: 2217 // { return 32 - nlz(~x & (x-1)); } 2218 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2219 EVT VT = Op.getValueType(); 2220 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2221 DAG.getNOT(dl, Op, VT), 2222 DAG.getNode(ISD::SUB, dl, VT, Op, 2223 DAG.getConstant(1, VT))); 2224 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2225 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2226 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2227 return DAG.getNode(ISD::SUB, dl, VT, 2228 DAG.getConstant(VT.getSizeInBits(), VT), 2229 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2230 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2231 } 2232 } 2233} 2234 2235void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2236 SmallVectorImpl<SDValue> &Results) { 2237 DebugLoc dl = Node->getDebugLoc(); 2238 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2239 switch (Node->getOpcode()) { 2240 case ISD::CTPOP: 2241 case ISD::CTLZ: 2242 case ISD::CTTZ: 2243 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2244 Results.push_back(Tmp1); 2245 break; 2246 case ISD::BSWAP: 2247 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2248 break; 2249 case ISD::FRAMEADDR: 2250 case ISD::RETURNADDR: 2251 case ISD::FRAME_TO_ARGS_OFFSET: 2252 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2253 break; 2254 case ISD::FLT_ROUNDS_: 2255 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2256 break; 2257 case ISD::EH_RETURN: 2258 case ISD::DBG_LABEL: 2259 case ISD::EH_LABEL: 2260 case ISD::PREFETCH: 2261 case ISD::MEMBARRIER: 2262 case ISD::VAEND: 2263 Results.push_back(Node->getOperand(0)); 2264 break; 2265 case ISD::DBG_STOPPOINT: 2266 Results.push_back(ExpandDBG_STOPPOINT(Node)); 2267 break; 2268 case ISD::DYNAMIC_STACKALLOC: 2269 ExpandDYNAMIC_STACKALLOC(Node, Results); 2270 break; 2271 case ISD::MERGE_VALUES: 2272 for (unsigned i = 0; i < Node->getNumValues(); i++) 2273 Results.push_back(Node->getOperand(i)); 2274 break; 2275 case ISD::UNDEF: { 2276 EVT VT = Node->getValueType(0); 2277 if (VT.isInteger()) 2278 Results.push_back(DAG.getConstant(0, VT)); 2279 else if (VT.isFloatingPoint()) 2280 Results.push_back(DAG.getConstantFP(0, VT)); 2281 else 2282 llvm_unreachable("Unknown value type!"); 2283 break; 2284 } 2285 case ISD::TRAP: { 2286 // If this operation is not supported, lower it to 'abort()' call 2287 TargetLowering::ArgListTy Args; 2288 std::pair<SDValue, SDValue> CallResult = 2289 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2290 false, false, false, false, 0, CallingConv::C, false, 2291 /*isReturnValueUsed=*/true, 2292 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2293 Args, DAG, dl); 2294 Results.push_back(CallResult.second); 2295 break; 2296 } 2297 case ISD::FP_ROUND: 2298 case ISD::BIT_CONVERT: 2299 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2300 Node->getValueType(0), dl); 2301 Results.push_back(Tmp1); 2302 break; 2303 case ISD::FP_EXTEND: 2304 Tmp1 = EmitStackConvert(Node->getOperand(0), 2305 Node->getOperand(0).getValueType(), 2306 Node->getValueType(0), dl); 2307 Results.push_back(Tmp1); 2308 break; 2309 case ISD::SIGN_EXTEND_INREG: { 2310 // NOTE: we could fall back on load/store here too for targets without 2311 // SAR. However, it is doubtful that any exist. 2312 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2313 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 2314 ExtraVT.getSizeInBits(); 2315 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2316 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2317 Node->getOperand(0), ShiftCst); 2318 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2319 Results.push_back(Tmp1); 2320 break; 2321 } 2322 case ISD::FP_ROUND_INREG: { 2323 // The only way we can lower this is to turn it into a TRUNCSTORE, 2324 // EXTLOAD pair, targetting a temporary location (a stack slot). 2325 2326 // NOTE: there is a choice here between constantly creating new stack 2327 // slots and always reusing the same one. We currently always create 2328 // new ones, as reuse may inhibit scheduling. 2329 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2330 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2331 Node->getValueType(0), dl); 2332 Results.push_back(Tmp1); 2333 break; 2334 } 2335 case ISD::SINT_TO_FP: 2336 case ISD::UINT_TO_FP: 2337 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2338 Node->getOperand(0), Node->getValueType(0), dl); 2339 Results.push_back(Tmp1); 2340 break; 2341 case ISD::FP_TO_UINT: { 2342 SDValue True, False; 2343 EVT VT = Node->getOperand(0).getValueType(); 2344 EVT NVT = Node->getValueType(0); 2345 const uint64_t zero[] = {0, 0}; 2346 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2347 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2348 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2349 Tmp1 = DAG.getConstantFP(apf, VT); 2350 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2351 Node->getOperand(0), 2352 Tmp1, ISD::SETLT); 2353 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2354 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2355 DAG.getNode(ISD::FSUB, dl, VT, 2356 Node->getOperand(0), Tmp1)); 2357 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2358 DAG.getConstant(x, NVT)); 2359 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2360 Results.push_back(Tmp1); 2361 break; 2362 } 2363 case ISD::VAARG: { 2364 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2365 EVT VT = Node->getValueType(0); 2366 Tmp1 = Node->getOperand(0); 2367 Tmp2 = Node->getOperand(1); 2368 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0); 2369 // Increment the pointer, VAList, to the next vaarg 2370 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2371 DAG.getConstant(TLI.getTargetData()-> 2372 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2373 TLI.getPointerTy())); 2374 // Store the incremented VAList to the legalized pointer 2375 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0); 2376 // Load the actual argument out of the pointer VAList 2377 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0)); 2378 Results.push_back(Results[0].getValue(1)); 2379 break; 2380 } 2381 case ISD::VACOPY: { 2382 // This defaults to loading a pointer from the input and storing it to the 2383 // output, returning the chain. 2384 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2385 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2386 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2387 Node->getOperand(2), VS, 0); 2388 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0); 2389 Results.push_back(Tmp1); 2390 break; 2391 } 2392 case ISD::EXTRACT_VECTOR_ELT: 2393 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2394 // This must be an access of the only element. Return it. 2395 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2396 Node->getOperand(0)); 2397 else 2398 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2399 Results.push_back(Tmp1); 2400 break; 2401 case ISD::EXTRACT_SUBVECTOR: 2402 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2403 break; 2404 case ISD::CONCAT_VECTORS: { 2405 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2406 break; 2407 } 2408 case ISD::SCALAR_TO_VECTOR: 2409 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2410 break; 2411 case ISD::INSERT_VECTOR_ELT: 2412 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2413 Node->getOperand(1), 2414 Node->getOperand(2), dl)); 2415 break; 2416 case ISD::VECTOR_SHUFFLE: { 2417 SmallVector<int, 8> Mask; 2418 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2419 2420 EVT VT = Node->getValueType(0); 2421 EVT EltVT = VT.getVectorElementType(); 2422 unsigned NumElems = VT.getVectorNumElements(); 2423 SmallVector<SDValue, 8> Ops; 2424 for (unsigned i = 0; i != NumElems; ++i) { 2425 if (Mask[i] < 0) { 2426 Ops.push_back(DAG.getUNDEF(EltVT)); 2427 continue; 2428 } 2429 unsigned Idx = Mask[i]; 2430 if (Idx < NumElems) 2431 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2432 Node->getOperand(0), 2433 DAG.getIntPtrConstant(Idx))); 2434 else 2435 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2436 Node->getOperand(1), 2437 DAG.getIntPtrConstant(Idx - NumElems))); 2438 } 2439 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2440 Results.push_back(Tmp1); 2441 break; 2442 } 2443 case ISD::EXTRACT_ELEMENT: { 2444 EVT OpTy = Node->getOperand(0).getValueType(); 2445 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2446 // 1 -> Hi 2447 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2448 DAG.getConstant(OpTy.getSizeInBits()/2, 2449 TLI.getShiftAmountTy())); 2450 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2451 } else { 2452 // 0 -> Lo 2453 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2454 Node->getOperand(0)); 2455 } 2456 Results.push_back(Tmp1); 2457 break; 2458 } 2459 case ISD::STACKSAVE: 2460 // Expand to CopyFromReg if the target set 2461 // StackPointerRegisterToSaveRestore. 2462 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2463 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2464 Node->getValueType(0))); 2465 Results.push_back(Results[0].getValue(1)); 2466 } else { 2467 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2468 Results.push_back(Node->getOperand(0)); 2469 } 2470 break; 2471 case ISD::STACKRESTORE: 2472 // Expand to CopyToReg if the target set 2473 // StackPointerRegisterToSaveRestore. 2474 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2475 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2476 Node->getOperand(1))); 2477 } else { 2478 Results.push_back(Node->getOperand(0)); 2479 } 2480 break; 2481 case ISD::FCOPYSIGN: 2482 Results.push_back(ExpandFCOPYSIGN(Node)); 2483 break; 2484 case ISD::FNEG: 2485 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2486 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2487 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2488 Node->getOperand(0)); 2489 Results.push_back(Tmp1); 2490 break; 2491 case ISD::FABS: { 2492 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2493 EVT VT = Node->getValueType(0); 2494 Tmp1 = Node->getOperand(0); 2495 Tmp2 = DAG.getConstantFP(0.0, VT); 2496 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2497 Tmp1, Tmp2, ISD::SETUGT); 2498 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2499 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2500 Results.push_back(Tmp1); 2501 break; 2502 } 2503 case ISD::FSQRT: 2504 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2505 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2506 break; 2507 case ISD::FSIN: 2508 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2509 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2510 break; 2511 case ISD::FCOS: 2512 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2513 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2514 break; 2515 case ISD::FLOG: 2516 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2517 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2518 break; 2519 case ISD::FLOG2: 2520 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2521 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2522 break; 2523 case ISD::FLOG10: 2524 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2525 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2526 break; 2527 case ISD::FEXP: 2528 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2529 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2530 break; 2531 case ISD::FEXP2: 2532 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2533 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2534 break; 2535 case ISD::FTRUNC: 2536 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2537 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2538 break; 2539 case ISD::FFLOOR: 2540 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2541 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2542 break; 2543 case ISD::FCEIL: 2544 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2545 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2546 break; 2547 case ISD::FRINT: 2548 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2549 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2550 break; 2551 case ISD::FNEARBYINT: 2552 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2553 RTLIB::NEARBYINT_F64, 2554 RTLIB::NEARBYINT_F80, 2555 RTLIB::NEARBYINT_PPCF128)); 2556 break; 2557 case ISD::FPOWI: 2558 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2559 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2560 break; 2561 case ISD::FPOW: 2562 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2563 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2564 break; 2565 case ISD::FDIV: 2566 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2567 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2568 break; 2569 case ISD::FREM: 2570 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2571 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2572 break; 2573 case ISD::ConstantFP: { 2574 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2575 // Check to see if this FP immediate is already legal. 2576 // If this is a legal constant, turn it into a TargetConstantFP node. 2577 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 2578 Results.push_back(SDValue(Node, 0)); 2579 else 2580 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2581 break; 2582 } 2583 case ISD::EHSELECTION: { 2584 unsigned Reg = TLI.getExceptionSelectorRegister(); 2585 assert(Reg && "Can't expand to unknown register!"); 2586 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2587 Node->getValueType(0))); 2588 Results.push_back(Results[0].getValue(1)); 2589 break; 2590 } 2591 case ISD::EXCEPTIONADDR: { 2592 unsigned Reg = TLI.getExceptionAddressRegister(); 2593 assert(Reg && "Can't expand to unknown register!"); 2594 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2595 Node->getValueType(0))); 2596 Results.push_back(Results[0].getValue(1)); 2597 break; 2598 } 2599 case ISD::SUB: { 2600 EVT VT = Node->getValueType(0); 2601 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2602 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2603 "Don't know how to expand this subtraction!"); 2604 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2605 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2606 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2607 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2608 break; 2609 } 2610 case ISD::UREM: 2611 case ISD::SREM: { 2612 EVT VT = Node->getValueType(0); 2613 SDVTList VTs = DAG.getVTList(VT, VT); 2614 bool isSigned = Node->getOpcode() == ISD::SREM; 2615 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2616 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2617 Tmp2 = Node->getOperand(0); 2618 Tmp3 = Node->getOperand(1); 2619 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2620 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2621 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2622 // X % Y -> X-X/Y*Y 2623 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2624 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2625 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2626 } else if (isSigned) { 2627 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SREM_I16, RTLIB::SREM_I32, 2628 RTLIB::SREM_I64, RTLIB::SREM_I128); 2629 } else { 2630 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UREM_I16, RTLIB::UREM_I32, 2631 RTLIB::UREM_I64, RTLIB::UREM_I128); 2632 } 2633 Results.push_back(Tmp1); 2634 break; 2635 } 2636 case ISD::UDIV: 2637 case ISD::SDIV: { 2638 bool isSigned = Node->getOpcode() == ISD::SDIV; 2639 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2640 EVT VT = Node->getValueType(0); 2641 SDVTList VTs = DAG.getVTList(VT, VT); 2642 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2643 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2644 Node->getOperand(1)); 2645 else if (isSigned) 2646 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2647 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2648 else 2649 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2650 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2651 Results.push_back(Tmp1); 2652 break; 2653 } 2654 case ISD::MULHU: 2655 case ISD::MULHS: { 2656 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2657 ISD::SMUL_LOHI; 2658 EVT VT = Node->getValueType(0); 2659 SDVTList VTs = DAG.getVTList(VT, VT); 2660 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2661 "If this wasn't legal, it shouldn't have been created!"); 2662 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 2663 Node->getOperand(1)); 2664 Results.push_back(Tmp1.getValue(1)); 2665 break; 2666 } 2667 case ISD::MUL: { 2668 EVT VT = Node->getValueType(0); 2669 SDVTList VTs = DAG.getVTList(VT, VT); 2670 // See if multiply or divide can be lowered using two-result operations. 2671 // We just need the low half of the multiply; try both the signed 2672 // and unsigned forms. If the target supports both SMUL_LOHI and 2673 // UMUL_LOHI, form a preference by checking which forms of plain 2674 // MULH it supports. 2675 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 2676 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 2677 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 2678 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 2679 unsigned OpToUse = 0; 2680 if (HasSMUL_LOHI && !HasMULHS) { 2681 OpToUse = ISD::SMUL_LOHI; 2682 } else if (HasUMUL_LOHI && !HasMULHU) { 2683 OpToUse = ISD::UMUL_LOHI; 2684 } else if (HasSMUL_LOHI) { 2685 OpToUse = ISD::SMUL_LOHI; 2686 } else if (HasUMUL_LOHI) { 2687 OpToUse = ISD::UMUL_LOHI; 2688 } 2689 if (OpToUse) { 2690 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 2691 Node->getOperand(1))); 2692 break; 2693 } 2694 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::MUL_I16, RTLIB::MUL_I32, 2695 RTLIB::MUL_I64, RTLIB::MUL_I128); 2696 Results.push_back(Tmp1); 2697 break; 2698 } 2699 case ISD::SADDO: 2700 case ISD::SSUBO: { 2701 SDValue LHS = Node->getOperand(0); 2702 SDValue RHS = Node->getOperand(1); 2703 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 2704 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2705 LHS, RHS); 2706 Results.push_back(Sum); 2707 EVT OType = Node->getValueType(1); 2708 2709 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 2710 2711 // LHSSign -> LHS >= 0 2712 // RHSSign -> RHS >= 0 2713 // SumSign -> Sum >= 0 2714 // 2715 // Add: 2716 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 2717 // Sub: 2718 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 2719 // 2720 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 2721 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 2722 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 2723 Node->getOpcode() == ISD::SADDO ? 2724 ISD::SETEQ : ISD::SETNE); 2725 2726 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 2727 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 2728 2729 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 2730 Results.push_back(Cmp); 2731 break; 2732 } 2733 case ISD::UADDO: 2734 case ISD::USUBO: { 2735 SDValue LHS = Node->getOperand(0); 2736 SDValue RHS = Node->getOperand(1); 2737 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 2738 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2739 LHS, RHS); 2740 Results.push_back(Sum); 2741 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 2742 Node->getOpcode () == ISD::UADDO ? 2743 ISD::SETULT : ISD::SETUGT)); 2744 break; 2745 } 2746 case ISD::UMULO: 2747 case ISD::SMULO: { 2748 EVT VT = Node->getValueType(0); 2749 SDValue LHS = Node->getOperand(0); 2750 SDValue RHS = Node->getOperand(1); 2751 SDValue BottomHalf; 2752 SDValue TopHalf; 2753 static unsigned Ops[2][3] = 2754 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 2755 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 2756 bool isSigned = Node->getOpcode() == ISD::SMULO; 2757 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 2758 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 2759 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 2760 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 2761 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 2762 RHS); 2763 TopHalf = BottomHalf.getValue(1); 2764 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2))) { 2765 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 2766 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 2767 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 2768 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 2769 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2770 DAG.getIntPtrConstant(0)); 2771 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2772 DAG.getIntPtrConstant(1)); 2773 } else { 2774 // FIXME: We should be able to fall back to a libcall with an illegal 2775 // type in some cases cases. 2776 // Also, we can fall back to a division in some cases, but that's a big 2777 // performance hit in the general case. 2778 llvm_unreachable("Don't know how to expand this operation yet!"); 2779 } 2780 if (isSigned) { 2781 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); 2782 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 2783 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 2784 ISD::SETNE); 2785 } else { 2786 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 2787 DAG.getConstant(0, VT), ISD::SETNE); 2788 } 2789 Results.push_back(BottomHalf); 2790 Results.push_back(TopHalf); 2791 break; 2792 } 2793 case ISD::BUILD_PAIR: { 2794 EVT PairTy = Node->getValueType(0); 2795 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 2796 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 2797 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 2798 DAG.getConstant(PairTy.getSizeInBits()/2, 2799 TLI.getShiftAmountTy())); 2800 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 2801 break; 2802 } 2803 case ISD::SELECT: 2804 Tmp1 = Node->getOperand(0); 2805 Tmp2 = Node->getOperand(1); 2806 Tmp3 = Node->getOperand(2); 2807 if (Tmp1.getOpcode() == ISD::SETCC) { 2808 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 2809 Tmp2, Tmp3, 2810 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2811 } else { 2812 Tmp1 = DAG.getSelectCC(dl, Tmp1, 2813 DAG.getConstant(0, Tmp1.getValueType()), 2814 Tmp2, Tmp3, ISD::SETNE); 2815 } 2816 Results.push_back(Tmp1); 2817 break; 2818 case ISD::BR_JT: { 2819 SDValue Chain = Node->getOperand(0); 2820 SDValue Table = Node->getOperand(1); 2821 SDValue Index = Node->getOperand(2); 2822 2823 EVT PTy = TLI.getPointerTy(); 2824 MachineFunction &MF = DAG.getMachineFunction(); 2825 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 2826 Index= DAG.getNode(ISD::MUL, dl, PTy, 2827 Index, DAG.getConstant(EntrySize, PTy)); 2828 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2829 2830 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 2831 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 2832 PseudoSourceValue::getJumpTable(), 0, MemVT); 2833 Addr = LD; 2834 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2835 // For PIC, the sequence is: 2836 // BRIND(load(Jumptable + index) + RelocBase) 2837 // RelocBase can be JumpTable, GOT or some sort of global base. 2838 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 2839 TLI.getPICJumpTableRelocBase(Table, DAG)); 2840 } 2841 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 2842 Results.push_back(Tmp1); 2843 break; 2844 } 2845 case ISD::BRCOND: 2846 // Expand brcond's setcc into its constituent parts and create a BR_CC 2847 // Node. 2848 Tmp1 = Node->getOperand(0); 2849 Tmp2 = Node->getOperand(1); 2850 if (Tmp2.getOpcode() == ISD::SETCC) { 2851 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 2852 Tmp1, Tmp2.getOperand(2), 2853 Tmp2.getOperand(0), Tmp2.getOperand(1), 2854 Node->getOperand(2)); 2855 } else { 2856 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 2857 DAG.getCondCode(ISD::SETNE), Tmp2, 2858 DAG.getConstant(0, Tmp2.getValueType()), 2859 Node->getOperand(2)); 2860 } 2861 Results.push_back(Tmp1); 2862 break; 2863 case ISD::SETCC: { 2864 Tmp1 = Node->getOperand(0); 2865 Tmp2 = Node->getOperand(1); 2866 Tmp3 = Node->getOperand(2); 2867 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 2868 2869 // If we expanded the SETCC into an AND/OR, return the new node 2870 if (Tmp2.getNode() == 0) { 2871 Results.push_back(Tmp1); 2872 break; 2873 } 2874 2875 // Otherwise, SETCC for the given comparison type must be completely 2876 // illegal; expand it into a SELECT_CC. 2877 EVT VT = Node->getValueType(0); 2878 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 2879 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 2880 Results.push_back(Tmp1); 2881 break; 2882 } 2883 case ISD::SELECT_CC: { 2884 Tmp1 = Node->getOperand(0); // LHS 2885 Tmp2 = Node->getOperand(1); // RHS 2886 Tmp3 = Node->getOperand(2); // True 2887 Tmp4 = Node->getOperand(3); // False 2888 SDValue CC = Node->getOperand(4); 2889 2890 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 2891 Tmp1, Tmp2, CC, dl); 2892 2893 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 2894 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2895 CC = DAG.getCondCode(ISD::SETNE); 2896 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 2897 Tmp3, Tmp4, CC); 2898 Results.push_back(Tmp1); 2899 break; 2900 } 2901 case ISD::BR_CC: { 2902 Tmp1 = Node->getOperand(0); // Chain 2903 Tmp2 = Node->getOperand(2); // LHS 2904 Tmp3 = Node->getOperand(3); // RHS 2905 Tmp4 = Node->getOperand(1); // CC 2906 2907 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 2908 Tmp2, Tmp3, Tmp4, dl); 2909 LastCALLSEQ_END = DAG.getEntryNode(); 2910 2911 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 2912 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 2913 Tmp4 = DAG.getCondCode(ISD::SETNE); 2914 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 2915 Tmp3, Node->getOperand(4)); 2916 Results.push_back(Tmp1); 2917 break; 2918 } 2919 case ISD::GLOBAL_OFFSET_TABLE: 2920 case ISD::GlobalAddress: 2921 case ISD::GlobalTLSAddress: 2922 case ISD::ExternalSymbol: 2923 case ISD::ConstantPool: 2924 case ISD::JumpTable: 2925 case ISD::INTRINSIC_W_CHAIN: 2926 case ISD::INTRINSIC_WO_CHAIN: 2927 case ISD::INTRINSIC_VOID: 2928 // FIXME: Custom lowering for these operations shouldn't return null! 2929 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2930 Results.push_back(SDValue(Node, i)); 2931 break; 2932 } 2933} 2934void SelectionDAGLegalize::PromoteNode(SDNode *Node, 2935 SmallVectorImpl<SDValue> &Results) { 2936 EVT OVT = Node->getValueType(0); 2937 if (Node->getOpcode() == ISD::UINT_TO_FP || 2938 Node->getOpcode() == ISD::SINT_TO_FP || 2939 Node->getOpcode() == ISD::SETCC) { 2940 OVT = Node->getOperand(0).getValueType(); 2941 } 2942 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2943 DebugLoc dl = Node->getDebugLoc(); 2944 SDValue Tmp1, Tmp2, Tmp3; 2945 switch (Node->getOpcode()) { 2946 case ISD::CTTZ: 2947 case ISD::CTLZ: 2948 case ISD::CTPOP: 2949 // Zero extend the argument. 2950 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 2951 // Perform the larger operation. 2952 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 2953 if (Node->getOpcode() == ISD::CTTZ) { 2954 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2955 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 2956 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 2957 ISD::SETEQ); 2958 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 2959 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 2960 } else if (Node->getOpcode() == ISD::CTLZ) { 2961 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2962 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 2963 DAG.getConstant(NVT.getSizeInBits() - 2964 OVT.getSizeInBits(), NVT)); 2965 } 2966 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 2967 break; 2968 case ISD::BSWAP: { 2969 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 2970 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); 2971 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 2972 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 2973 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2974 Results.push_back(Tmp1); 2975 break; 2976 } 2977 case ISD::FP_TO_UINT: 2978 case ISD::FP_TO_SINT: 2979 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 2980 Node->getOpcode() == ISD::FP_TO_SINT, dl); 2981 Results.push_back(Tmp1); 2982 break; 2983 case ISD::UINT_TO_FP: 2984 case ISD::SINT_TO_FP: 2985 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 2986 Node->getOpcode() == ISD::SINT_TO_FP, dl); 2987 Results.push_back(Tmp1); 2988 break; 2989 case ISD::AND: 2990 case ISD::OR: 2991 case ISD::XOR: { 2992 unsigned ExtOp, TruncOp; 2993 if (OVT.isVector()) { 2994 ExtOp = ISD::BIT_CONVERT; 2995 TruncOp = ISD::BIT_CONVERT; 2996 } else if (OVT.isInteger()) { 2997 ExtOp = ISD::ANY_EXTEND; 2998 TruncOp = ISD::TRUNCATE; 2999 } else { 3000 llvm_report_error("Cannot promote logic operation"); 3001 } 3002 // Promote each of the values to the new type. 3003 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3004 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3005 // Perform the larger operation, then convert back 3006 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3007 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3008 break; 3009 } 3010 case ISD::SELECT: { 3011 unsigned ExtOp, TruncOp; 3012 if (Node->getValueType(0).isVector()) { 3013 ExtOp = ISD::BIT_CONVERT; 3014 TruncOp = ISD::BIT_CONVERT; 3015 } else if (Node->getValueType(0).isInteger()) { 3016 ExtOp = ISD::ANY_EXTEND; 3017 TruncOp = ISD::TRUNCATE; 3018 } else { 3019 ExtOp = ISD::FP_EXTEND; 3020 TruncOp = ISD::FP_ROUND; 3021 } 3022 Tmp1 = Node->getOperand(0); 3023 // Promote each of the values to the new type. 3024 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3025 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3026 // Perform the larger operation, then round down. 3027 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3028 if (TruncOp != ISD::FP_ROUND) 3029 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3030 else 3031 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3032 DAG.getIntPtrConstant(0)); 3033 Results.push_back(Tmp1); 3034 break; 3035 } 3036 case ISD::VECTOR_SHUFFLE: { 3037 SmallVector<int, 8> Mask; 3038 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3039 3040 // Cast the two input vectors. 3041 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3042 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3043 3044 // Convert the shuffle mask to the right # elements. 3045 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3046 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3047 Results.push_back(Tmp1); 3048 break; 3049 } 3050 case ISD::SETCC: { 3051 unsigned ExtOp = ISD::FP_EXTEND; 3052 if (NVT.isInteger()) { 3053 ISD::CondCode CCCode = 3054 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3055 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3056 } 3057 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3058 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3059 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3060 Tmp1, Tmp2, Node->getOperand(2))); 3061 break; 3062 } 3063 } 3064} 3065 3066// SelectionDAG::Legalize - This is the entry point for the file. 3067// 3068void SelectionDAG::Legalize(bool TypesNeedLegalizing, 3069 CodeGenOpt::Level OptLevel) { 3070 /// run - This is the main entry point to this class. 3071 /// 3072 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3073} 3074 3075