LegalizeDAG.cpp revision a68d204843fc8b9606e7760fcddd20b99e8e340d
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned long long ValueTypeActions; 56 57 /// NeedsAnotherIteration - This is set when we expand a large integer 58 /// operation into smaller integer operations, but the smaller operations are 59 /// not set. This occurs only rarely in practice, for targets that don't have 60 /// 32-bit or larger integer registers. 61 bool NeedsAnotherIteration; 62 63 /// LegalizedNodes - For nodes that are of legal width, and that have more 64 /// than one use, this map indicates what regularized operand to use. This 65 /// allows us to avoid legalizing the same thing more than once. 66 std::map<SDOperand, SDOperand> LegalizedNodes; 67 68 /// PromotedNodes - For nodes that are below legal width, and that have more 69 /// than one use, this map indicates what promoted value to use. This allows 70 /// us to avoid promoting the same thing more than once. 71 std::map<SDOperand, SDOperand> PromotedNodes; 72 73 /// ExpandedNodes - For nodes that need to be expanded, and which have more 74 /// than one use, this map indicates which which operands are the expanded 75 /// version of the input. This allows us to avoid expanding the same node 76 /// more than once. 77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 78 79 void AddLegalizedOperand(SDOperand From, SDOperand To) { 80 LegalizedNodes.insert(std::make_pair(From, To)); 81 // If someone requests legalization of the new node, return itself. 82 if (From != To) 83 LegalizedNodes.insert(std::make_pair(To, To)); 84 } 85 void AddPromotedOperand(SDOperand From, SDOperand To) { 86 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 87 assert(isNew && "Got into the map somehow?"); 88 // If someone requests legalization of the new node, return itself. 89 LegalizedNodes.insert(std::make_pair(To, To)); 90 } 91 92public: 93 94 SelectionDAGLegalize(SelectionDAG &DAG); 95 96 /// Run - While there is still lowering to do, perform a pass over the DAG. 97 /// Most regularization can be done in a single pass, but targets that require 98 /// large values to be split into registers multiple times (e.g. i64 -> 4x 99 /// i16) require iteration for these values (the first iteration will demote 100 /// to i32, the second will demote to i16). 101 void Run() { 102 do { 103 NeedsAnotherIteration = false; 104 LegalizeDAG(); 105 } while (NeedsAnotherIteration); 106 } 107 108 /// getTypeAction - Return how we should legalize values of this type, either 109 /// it is already legal or we need to expand it into multiple registers of 110 /// smaller integer type, or we need to promote it to a larger type. 111 LegalizeAction getTypeAction(MVT::ValueType VT) const { 112 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 113 } 114 115 /// isTypeLegal - Return true if this type is legal on this target. 116 /// 117 bool isTypeLegal(MVT::ValueType VT) const { 118 return getTypeAction(VT) == Legal; 119 } 120 121private: 122 void LegalizeDAG(); 123 124 SDOperand LegalizeOp(SDOperand O); 125 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 126 SDOperand PromoteOp(SDOperand O); 127 128 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 129 SDOperand &Hi); 130 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 131 SDOperand Source); 132 133 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 134 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 135 SDOperand LegalOp, 136 MVT::ValueType DestVT); 137 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 138 bool isSigned); 139 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 140 bool isSigned); 141 142 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 143 SDOperand &Lo, SDOperand &Hi); 144 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 145 SDOperand &Lo, SDOperand &Hi); 146 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 147 SDOperand &Lo, SDOperand &Hi); 148 149 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 150 151 SDOperand getIntPtrConstant(uint64_t Val) { 152 return DAG.getConstant(Val, TLI.getPointerTy()); 153 } 154}; 155} 156 157static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 158 switch (VecOp) { 159 default: assert(0 && "Don't know how to scalarize this opcode!"); 160 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 161 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 162 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 163 } 164} 165 166SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 167 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 168 ValueTypeActions(TLI.getValueTypeActions()) { 169 assert(MVT::LAST_VALUETYPE <= 32 && 170 "Too many value types for ValueTypeActions to hold!"); 171} 172 173/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 174/// INT_TO_FP operation of the specified operand when the target requests that 175/// we expand it. At this point, we know that the result and operand types are 176/// legal for the target. 177SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 178 SDOperand Op0, 179 MVT::ValueType DestVT) { 180 if (Op0.getValueType() == MVT::i32) { 181 // simple 32-bit [signed|unsigned] integer to float/double expansion 182 183 // get the stack frame index of a 8 byte buffer 184 MachineFunction &MF = DAG.getMachineFunction(); 185 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 186 // get address of 8 byte buffer 187 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 188 // word offset constant for Hi/Lo address computation 189 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 190 // set up Hi and Lo (into buffer) address based on endian 191 SDOperand Hi, Lo; 192 if (TLI.isLittleEndian()) { 193 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 194 Lo = StackSlot; 195 } else { 196 Hi = StackSlot; 197 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 198 } 199 // if signed map to unsigned space 200 SDOperand Op0Mapped; 201 if (isSigned) { 202 // constant used to invert sign bit (signed to unsigned mapping) 203 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 204 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 205 } else { 206 Op0Mapped = Op0; 207 } 208 // store the lo of the constructed double - based on integer input 209 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 210 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 211 // initial hi portion of constructed double 212 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 213 // store the hi of the constructed double - biased exponent 214 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 215 InitialHi, Hi, DAG.getSrcValue(NULL)); 216 // load the constructed double 217 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 218 DAG.getSrcValue(NULL)); 219 // FP constant to bias correct the final result 220 SDOperand Bias = DAG.getConstantFP(isSigned ? 221 BitsToDouble(0x4330000080000000ULL) 222 : BitsToDouble(0x4330000000000000ULL), 223 MVT::f64); 224 // subtract the bias 225 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 226 // final result 227 SDOperand Result; 228 // handle final rounding 229 if (DestVT == MVT::f64) { 230 // do nothing 231 Result = Sub; 232 } else { 233 // if f32 then cast to f32 234 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 235 } 236 return LegalizeOp(Result); 237 } 238 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 239 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 240 241 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 242 DAG.getConstant(0, Op0.getValueType()), 243 ISD::SETLT); 244 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 245 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 246 SignSet, Four, Zero); 247 248 // If the sign bit of the integer is set, the large number will be treated 249 // as a negative number. To counteract this, the dynamic code adds an 250 // offset depending on the data type. 251 uint64_t FF; 252 switch (Op0.getValueType()) { 253 default: assert(0 && "Unsupported integer type!"); 254 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 255 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 256 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 257 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 258 } 259 if (TLI.isLittleEndian()) FF <<= 32; 260 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 261 262 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 263 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 264 SDOperand FudgeInReg; 265 if (DestVT == MVT::f32) 266 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 267 DAG.getSrcValue(NULL)); 268 else { 269 assert(DestVT == MVT::f64 && "Unexpected conversion"); 270 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 271 DAG.getEntryNode(), CPIdx, 272 DAG.getSrcValue(NULL), MVT::f32)); 273 } 274 275 return LegalizeOp(DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg)); 276} 277 278/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 279/// *INT_TO_FP operation of the specified operand when the target requests that 280/// we promote it. At this point, we know that the result and operand types are 281/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 282/// operation that takes a larger input. 283SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 284 MVT::ValueType DestVT, 285 bool isSigned) { 286 // First step, figure out the appropriate *INT_TO_FP operation to use. 287 MVT::ValueType NewInTy = LegalOp.getValueType(); 288 289 unsigned OpToUse = 0; 290 291 // Scan for the appropriate larger type to use. 292 while (1) { 293 NewInTy = (MVT::ValueType)(NewInTy+1); 294 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 295 296 // If the target supports SINT_TO_FP of this type, use it. 297 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 298 default: break; 299 case TargetLowering::Legal: 300 if (!TLI.isTypeLegal(NewInTy)) 301 break; // Can't use this datatype. 302 // FALL THROUGH. 303 case TargetLowering::Custom: 304 OpToUse = ISD::SINT_TO_FP; 305 break; 306 } 307 if (OpToUse) break; 308 if (isSigned) continue; 309 310 // If the target supports UINT_TO_FP of this type, use it. 311 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 312 default: break; 313 case TargetLowering::Legal: 314 if (!TLI.isTypeLegal(NewInTy)) 315 break; // Can't use this datatype. 316 // FALL THROUGH. 317 case TargetLowering::Custom: 318 OpToUse = ISD::UINT_TO_FP; 319 break; 320 } 321 if (OpToUse) break; 322 323 // Otherwise, try a larger type. 324 } 325 326 // Okay, we found the operation and type to use. Zero extend our input to the 327 // desired type then run the operation on it. 328 SDOperand N = DAG.getNode(OpToUse, DestVT, 329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 330 NewInTy, LegalOp)); 331 // Make sure to legalize any nodes we create here. 332 return LegalizeOp(N); 333} 334 335/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 336/// FP_TO_*INT operation of the specified operand when the target requests that 337/// we promote it. At this point, we know that the result and operand types are 338/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 339/// operation that returns a larger result. 340SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 341 MVT::ValueType DestVT, 342 bool isSigned) { 343 // First step, figure out the appropriate FP_TO*INT operation to use. 344 MVT::ValueType NewOutTy = DestVT; 345 346 unsigned OpToUse = 0; 347 348 // Scan for the appropriate larger type to use. 349 while (1) { 350 NewOutTy = (MVT::ValueType)(NewOutTy+1); 351 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 352 353 // If the target supports FP_TO_SINT returning this type, use it. 354 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 355 default: break; 356 case TargetLowering::Legal: 357 if (!TLI.isTypeLegal(NewOutTy)) 358 break; // Can't use this datatype. 359 // FALL THROUGH. 360 case TargetLowering::Custom: 361 OpToUse = ISD::FP_TO_SINT; 362 break; 363 } 364 if (OpToUse) break; 365 366 // If the target supports FP_TO_UINT of this type, use it. 367 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 368 default: break; 369 case TargetLowering::Legal: 370 if (!TLI.isTypeLegal(NewOutTy)) 371 break; // Can't use this datatype. 372 // FALL THROUGH. 373 case TargetLowering::Custom: 374 OpToUse = ISD::FP_TO_UINT; 375 break; 376 } 377 if (OpToUse) break; 378 379 // Otherwise, try a larger type. 380 } 381 382 // Okay, we found the operation and type to use. Truncate the result of the 383 // extended FP_TO_*INT operation to the desired size. 384 SDOperand N = DAG.getNode(ISD::TRUNCATE, DestVT, 385 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 386 // Make sure to legalize any nodes we create here in the next pass. 387 return LegalizeOp(N); 388} 389 390/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 391/// not been visited yet and if all of its operands have already been visited. 392static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 393 std::map<SDNode*, unsigned> &Visited) { 394 if (++Visited[N] != N->getNumOperands()) 395 return; // Haven't visited all operands yet 396 397 Order.push_back(N); 398 399 if (N->hasOneUse()) { // Tail recurse in common case. 400 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 401 return; 402 } 403 404 // Now that we have N in, add anything that uses it if all of their operands 405 // are now done. 406 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 407 ComputeTopDownOrdering(*UI, Order, Visited); 408} 409 410 411void SelectionDAGLegalize::LegalizeDAG() { 412 // The legalize process is inherently a bottom-up recursive process (users 413 // legalize their uses before themselves). Given infinite stack space, we 414 // could just start legalizing on the root and traverse the whole graph. In 415 // practice however, this causes us to run out of stack space on large basic 416 // blocks. To avoid this problem, compute an ordering of the nodes where each 417 // node is only legalized after all of its operands are legalized. 418 std::map<SDNode*, unsigned> Visited; 419 std::vector<SDNode*> Order; 420 421 // Compute ordering from all of the leaves in the graphs, those (like the 422 // entry node) that have no operands. 423 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 424 E = DAG.allnodes_end(); I != E; ++I) { 425 if (I->getNumOperands() == 0) { 426 Visited[I] = 0 - 1U; 427 ComputeTopDownOrdering(I, Order, Visited); 428 } 429 } 430 431 assert(Order.size() == Visited.size() && 432 Order.size() == 433 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 434 "Error: DAG is cyclic!"); 435 Visited.clear(); 436 437 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 438 SDNode *N = Order[i]; 439 switch (getTypeAction(N->getValueType(0))) { 440 default: assert(0 && "Bad type action!"); 441 case Legal: 442 LegalizeOp(SDOperand(N, 0)); 443 break; 444 case Promote: 445 PromoteOp(SDOperand(N, 0)); 446 break; 447 case Expand: { 448 SDOperand X, Y; 449 ExpandOp(SDOperand(N, 0), X, Y); 450 break; 451 } 452 } 453 } 454 455 // Finally, it's possible the root changed. Get the new root. 456 SDOperand OldRoot = DAG.getRoot(); 457 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 458 DAG.setRoot(LegalizedNodes[OldRoot]); 459 460 ExpandedNodes.clear(); 461 LegalizedNodes.clear(); 462 PromotedNodes.clear(); 463 464 // Remove dead nodes now. 465 DAG.RemoveDeadNodes(OldRoot.Val); 466} 467 468SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 469 assert(isTypeLegal(Op.getValueType()) && 470 "Caller should expand or promote operands that are not legal!"); 471 SDNode *Node = Op.Val; 472 473 // If this operation defines any values that cannot be represented in a 474 // register on this target, make sure to expand or promote them. 475 if (Node->getNumValues() > 1) { 476 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 477 switch (getTypeAction(Node->getValueType(i))) { 478 case Legal: break; // Nothing to do. 479 case Expand: { 480 SDOperand T1, T2; 481 ExpandOp(Op.getValue(i), T1, T2); 482 assert(LegalizedNodes.count(Op) && 483 "Expansion didn't add legal operands!"); 484 return LegalizedNodes[Op]; 485 } 486 case Promote: 487 PromoteOp(Op.getValue(i)); 488 assert(LegalizedNodes.count(Op) && 489 "Expansion didn't add legal operands!"); 490 return LegalizedNodes[Op]; 491 } 492 } 493 494 // Note that LegalizeOp may be reentered even from single-use nodes, which 495 // means that we always must cache transformed nodes. 496 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 497 if (I != LegalizedNodes.end()) return I->second; 498 499 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 500 501 SDOperand Result = Op; 502 503 switch (Node->getOpcode()) { 504 default: 505 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 506 // If this is a target node, legalize it by legalizing the operands then 507 // passing it through. 508 std::vector<SDOperand> Ops; 509 bool Changed = false; 510 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 511 Ops.push_back(LegalizeOp(Node->getOperand(i))); 512 Changed = Changed || Node->getOperand(i) != Ops.back(); 513 } 514 if (Changed) 515 if (Node->getNumValues() == 1) 516 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 517 else { 518 std::vector<MVT::ValueType> VTs(Node->value_begin(), 519 Node->value_end()); 520 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 521 } 522 523 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 524 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 525 return Result.getValue(Op.ResNo); 526 } 527 // Otherwise this is an unhandled builtin node. splat. 528 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 529 assert(0 && "Do not know how to legalize this operator!"); 530 abort(); 531 case ISD::EntryToken: 532 case ISD::FrameIndex: 533 case ISD::TargetFrameIndex: 534 case ISD::Register: 535 case ISD::TargetConstant: 536 case ISD::TargetConstantPool: 537 case ISD::GlobalAddress: 538 case ISD::TargetGlobalAddress: 539 case ISD::ExternalSymbol: 540 case ISD::TargetExternalSymbol: 541 case ISD::ConstantPool: // Nothing to do. 542 case ISD::BasicBlock: 543 case ISD::CONDCODE: 544 case ISD::VALUETYPE: 545 case ISD::SRCVALUE: 546 case ISD::STRING: 547 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 548 default: assert(0 && "This action is not supported yet!"); 549 case TargetLowering::Custom: { 550 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 551 if (Tmp.Val) { 552 Result = LegalizeOp(Tmp); 553 break; 554 } 555 } // FALLTHROUGH if the target doesn't want to lower this op after all. 556 case TargetLowering::Legal: 557 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!"); 558 break; 559 } 560 break; 561 case ISD::AssertSext: 562 case ISD::AssertZext: 563 Tmp1 = LegalizeOp(Node->getOperand(0)); 564 if (Tmp1 != Node->getOperand(0)) 565 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 566 Node->getOperand(1)); 567 break; 568 case ISD::MERGE_VALUES: 569 return LegalizeOp(Node->getOperand(Op.ResNo)); 570 case ISD::CopyFromReg: 571 Tmp1 = LegalizeOp(Node->getOperand(0)); 572 Result = Op.getValue(0); 573 if (Node->getNumValues() == 2) { 574 if (Tmp1 != Node->getOperand(0)) 575 Result = DAG.getCopyFromReg(Tmp1, 576 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 577 Node->getValueType(0)); 578 } else { 579 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 580 if (Node->getNumOperands() == 3) 581 Tmp2 = LegalizeOp(Node->getOperand(2)); 582 if (Tmp1 != Node->getOperand(0) || 583 (Node->getNumOperands() == 3 && Tmp2 != Node->getOperand(2))) 584 Result = DAG.getCopyFromReg(Tmp1, 585 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 586 Node->getValueType(0), Tmp2); 587 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 588 } 589 // Since CopyFromReg produces two values, make sure to remember that we 590 // legalized both of them. 591 AddLegalizedOperand(Op.getValue(0), Result); 592 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 593 return Result.getValue(Op.ResNo); 594 case ISD::UNDEF: { 595 MVT::ValueType VT = Op.getValueType(); 596 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 597 default: assert(0 && "This action is not supported yet!"); 598 case TargetLowering::Expand: 599 case TargetLowering::Promote: 600 if (MVT::isInteger(VT)) 601 Result = DAG.getConstant(0, VT); 602 else if (MVT::isFloatingPoint(VT)) 603 Result = DAG.getConstantFP(0, VT); 604 else 605 assert(0 && "Unknown value type!"); 606 break; 607 case TargetLowering::Legal: 608 break; 609 } 610 break; 611 } 612 613 case ISD::LOCATION: 614 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 615 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 616 617 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 618 case TargetLowering::Promote: 619 default: assert(0 && "This action is not supported yet!"); 620 case TargetLowering::Expand: { 621 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 622 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 623 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other); 624 625 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) { 626 const std::string &FName = 627 cast<StringSDNode>(Node->getOperand(3))->getValue(); 628 const std::string &DirName = 629 cast<StringSDNode>(Node->getOperand(4))->getValue(); 630 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName); 631 632 std::vector<SDOperand> Ops; 633 Ops.push_back(Tmp1); // chain 634 SDOperand LineOp = Node->getOperand(1); 635 SDOperand ColOp = Node->getOperand(2); 636 637 if (useDEBUG_LOC) { 638 Ops.push_back(LineOp); // line # 639 Ops.push_back(ColOp); // col # 640 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 641 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops); 642 } else { 643 unsigned Line = dyn_cast<ConstantSDNode>(LineOp)->getValue(); 644 unsigned Col = dyn_cast<ConstantSDNode>(ColOp)->getValue(); 645 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile); 646 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 647 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops); 648 } 649 } else { 650 Result = Tmp1; // chain 651 } 652 Result = LegalizeOp(Result); // Relegalize new nodes. 653 break; 654 } 655 case TargetLowering::Legal: 656 if (Tmp1 != Node->getOperand(0) || 657 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 658 std::vector<SDOperand> Ops; 659 Ops.push_back(Tmp1); 660 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 661 Ops.push_back(Node->getOperand(1)); // line # must be legal. 662 Ops.push_back(Node->getOperand(2)); // col # must be legal. 663 } else { 664 // Otherwise promote them. 665 Ops.push_back(PromoteOp(Node->getOperand(1))); 666 Ops.push_back(PromoteOp(Node->getOperand(2))); 667 } 668 Ops.push_back(Node->getOperand(3)); // filename must be legal. 669 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 670 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops); 671 } 672 break; 673 } 674 break; 675 676 case ISD::DEBUG_LOC: 677 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 678 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 679 case TargetLowering::Promote: 680 case TargetLowering::Expand: 681 default: assert(0 && "This action is not supported yet!"); 682 case TargetLowering::Legal: 683 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 684 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 685 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 686 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 687 688 if (Tmp1 != Node->getOperand(0) || 689 Tmp2 != Node->getOperand(1) || 690 Tmp3 != Node->getOperand(2) || 691 Tmp4 != Node->getOperand(3)) { 692 Result = DAG.getNode(ISD::DEBUG_LOC,MVT::Other, Tmp1, Tmp2, Tmp3, Tmp4); 693 } 694 break; 695 } 696 break; 697 698 case ISD::DEBUG_LABEL: 699 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!"); 700 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) { 701 case TargetLowering::Promote: 702 case TargetLowering::Expand: 703 default: assert(0 && "This action is not supported yet!"); 704 case TargetLowering::Legal: 705 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 706 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 707 708 if (Tmp1 != Node->getOperand(0) || 709 Tmp2 != Node->getOperand(1)) { 710 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Tmp1, Tmp2); 711 } 712 break; 713 } 714 break; 715 716 case ISD::Constant: 717 // We know we don't need to expand constants here, constants only have one 718 // value and we check that it is fine above. 719 720 // FIXME: Maybe we should handle things like targets that don't support full 721 // 32-bit immediates? 722 break; 723 case ISD::ConstantFP: { 724 // Spill FP immediates to the constant pool if the target cannot directly 725 // codegen them. Targets often have some immediate values that can be 726 // efficiently generated into an FP register without a load. We explicitly 727 // leave these constants as ConstantFP nodes for the target to deal with. 728 729 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 730 731 // Check to see if this FP immediate is already legal. 732 bool isLegal = false; 733 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 734 E = TLI.legal_fpimm_end(); I != E; ++I) 735 if (CFP->isExactlyValue(*I)) { 736 isLegal = true; 737 break; 738 } 739 740 if (!isLegal) { 741 // Otherwise we need to spill the constant to memory. 742 bool Extend = false; 743 744 // If a FP immediate is precise when represented as a float, we put it 745 // into the constant pool as a float, even if it's is statically typed 746 // as a double. 747 MVT::ValueType VT = CFP->getValueType(0); 748 bool isDouble = VT == MVT::f64; 749 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 750 Type::FloatTy, CFP->getValue()); 751 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 752 // Only do this if the target has a native EXTLOAD instruction from 753 // f32. 754 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 755 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 756 VT = MVT::f32; 757 Extend = true; 758 } 759 760 SDOperand CPIdx = 761 LegalizeOp(DAG.getConstantPool(LLVMC, TLI.getPointerTy())); 762 if (Extend) { 763 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 764 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 765 } else { 766 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 767 DAG.getSrcValue(NULL)); 768 } 769 } 770 break; 771 } 772 case ISD::ConstantVec: { 773 // We assume that vector constants are not legal, and will be immediately 774 // spilled to the constant pool. 775 // 776 // FIXME: revisit this when we have some kind of mechanism by which targets 777 // can decided legality of vector constants, of which there may be very 778 // many. 779 // 780 // Create a ConstantPacked, and put it in the constant pool. 781 std::vector<Constant*> CV; 782 MVT::ValueType VT = Node->getValueType(0); 783 for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) { 784 SDOperand OpN = Node->getOperand(I); 785 const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType()); 786 if (MVT::isFloatingPoint(VT)) 787 CV.push_back(ConstantFP::get(OpNTy, 788 cast<ConstantFPSDNode>(OpN)->getValue())); 789 else 790 CV.push_back(ConstantUInt::get(OpNTy, 791 cast<ConstantSDNode>(OpN)->getValue())); 792 } 793 Constant *CP = ConstantPacked::get(CV); 794 SDOperand CPIdx = LegalizeOp(DAG.getConstantPool(CP, TLI.getPointerTy())); 795 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL)); 796 break; 797 } 798 case ISD::TokenFactor: 799 if (Node->getNumOperands() == 2) { 800 bool Changed = false; 801 SDOperand Op0 = LegalizeOp(Node->getOperand(0)); 802 SDOperand Op1 = LegalizeOp(Node->getOperand(1)); 803 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1)) 804 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1); 805 } else { 806 std::vector<SDOperand> Ops; 807 bool Changed = false; 808 // Legalize the operands. 809 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 810 SDOperand Op = Node->getOperand(i); 811 Ops.push_back(LegalizeOp(Op)); 812 Changed |= Ops[i] != Op; 813 } 814 if (Changed) 815 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 816 } 817 break; 818 819 case ISD::CALLSEQ_START: 820 case ISD::CALLSEQ_END: 821 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 822 // Do not try to legalize the target-specific arguments (#1+) 823 Tmp2 = Node->getOperand(0); 824 if (Tmp1 != Tmp2) 825 Node->setAdjCallChain(Tmp1); 826 827 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These 828 // nodes are treated specially and are mutated in place. This makes the dag 829 // legalization process more efficient and also makes libcall insertion 830 // easier. 831 break; 832 case ISD::DYNAMIC_STACKALLOC: { 833 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 834 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 835 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 836 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 837 Tmp3 != Node->getOperand(2)) { 838 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 839 std::vector<SDOperand> Ops; 840 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 841 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 842 } else 843 Result = Op.getValue(0); 844 845 Tmp1 = Result; 846 Tmp2 = Result.getValue(1); 847 switch (TLI.getOperationAction(Node->getOpcode(), 848 Node->getValueType(0))) { 849 default: assert(0 && "This action is not supported yet!"); 850 case TargetLowering::Expand: { 851 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 852 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 853 " not tell us which reg is the stack pointer!"); 854 SDOperand Chain = Tmp1.getOperand(0); 855 SDOperand Size = Tmp2.getOperand(1); 856 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0)); 857 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value 858 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain 859 break; 860 } 861 case TargetLowering::Custom: 862 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 863 if (Tmp3.Val) { 864 Tmp1 = LegalizeOp(Tmp3); 865 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 866 } 867 break; 868 case TargetLowering::Legal: 869 break; 870 } 871 // Since this op produce two values, make sure to remember that we 872 // legalized both of them. 873 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 874 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 875 return Op.ResNo ? Tmp2 : Tmp1; 876 } 877 case ISD::TAILCALL: 878 case ISD::CALL: { 879 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 880 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 881 882 bool Changed = false; 883 std::vector<SDOperand> Ops; 884 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 885 Ops.push_back(LegalizeOp(Node->getOperand(i))); 886 Changed |= Ops.back() != Node->getOperand(i); 887 } 888 889 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 890 std::vector<MVT::ValueType> RetTyVTs; 891 RetTyVTs.reserve(Node->getNumValues()); 892 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 893 RetTyVTs.push_back(Node->getValueType(i)); 894 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 895 Node->getOpcode() == ISD::TAILCALL), 0); 896 } else { 897 Result = Result.getValue(0); 898 } 899 // Since calls produce multiple values, make sure to remember that we 900 // legalized all of them. 901 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 902 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 903 return Result.getValue(Op.ResNo); 904 } 905 case ISD::BR: 906 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 907 if (Tmp1 != Node->getOperand(0)) 908 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 909 break; 910 911 case ISD::BRCOND: 912 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 913 914 switch (getTypeAction(Node->getOperand(1).getValueType())) { 915 case Expand: assert(0 && "It's impossible to expand bools"); 916 case Legal: 917 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 918 break; 919 case Promote: 920 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 921 break; 922 } 923 924 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 925 default: assert(0 && "This action is not supported yet!"); 926 case TargetLowering::Expand: 927 // Expand brcond's setcc into its constituent parts and create a BR_CC 928 // Node. 929 if (Tmp2.getOpcode() == ISD::SETCC) { 930 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 931 Tmp2.getOperand(0), Tmp2.getOperand(1), 932 Node->getOperand(2)); 933 } else { 934 // Make sure the condition is either zero or one. It may have been 935 // promoted from something else. 936 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 937 938 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 939 DAG.getCondCode(ISD::SETNE), Tmp2, 940 DAG.getConstant(0, Tmp2.getValueType()), 941 Node->getOperand(2)); 942 } 943 Result = LegalizeOp(Result); // Relegalize new nodes. 944 break; 945 case TargetLowering::Custom: { 946 SDOperand Tmp = 947 TLI.LowerOperation(DAG.getNode(ISD::BRCOND, Node->getValueType(0), 948 Tmp1, Tmp2, Node->getOperand(2)), DAG); 949 if (Tmp.Val) { 950 Result = LegalizeOp(Tmp); 951 break; 952 } 953 // FALLTHROUGH if the target thinks it is legal. 954 } 955 case TargetLowering::Legal: 956 // Basic block destination (Op#2) is always legal. 957 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 958 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 959 Node->getOperand(2)); 960 break; 961 } 962 break; 963 case ISD::BR_CC: 964 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 965 if (!isTypeLegal(Node->getOperand(2).getValueType())) { 966 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 967 Node->getOperand(2), // LHS 968 Node->getOperand(3), // RHS 969 Node->getOperand(1))); 970 // If we get a SETCC back from legalizing the SETCC node we just 971 // created, then use its LHS, RHS, and CC directly in creating a new 972 // node. Otherwise, select between the true and false value based on 973 // comparing the result of the legalized with zero. 974 if (Tmp2.getOpcode() == ISD::SETCC) { 975 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 976 Tmp2.getOperand(0), Tmp2.getOperand(1), 977 Node->getOperand(4)); 978 } else { 979 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 980 DAG.getCondCode(ISD::SETNE), 981 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 982 Node->getOperand(4)); 983 } 984 break; 985 } 986 987 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 988 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 989 990 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 991 default: assert(0 && "Unexpected action for BR_CC!"); 992 case TargetLowering::Custom: { 993 Tmp4 = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 994 Tmp2, Tmp3, Node->getOperand(4)); 995 Tmp4 = TLI.LowerOperation(Tmp4, DAG); 996 if (Tmp4.Val) { 997 Result = LegalizeOp(Tmp4); 998 break; 999 } 1000 } // FALLTHROUGH if the target doesn't want to lower this op after all. 1001 case TargetLowering::Legal: 1002 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 1003 Tmp3 != Node->getOperand(3)) { 1004 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 1005 Tmp2, Tmp3, Node->getOperand(4)); 1006 } 1007 break; 1008 } 1009 break; 1010 case ISD::BRCONDTWOWAY: 1011 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1012 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1013 case Expand: assert(0 && "It's impossible to expand bools"); 1014 case Legal: 1015 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1016 break; 1017 case Promote: 1018 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1019 break; 1020 } 1021 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 1022 // pair. 1023 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 1024 case TargetLowering::Promote: 1025 default: assert(0 && "This action is not supported yet!"); 1026 case TargetLowering::Legal: 1027 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1028 std::vector<SDOperand> Ops; 1029 Ops.push_back(Tmp1); 1030 Ops.push_back(Tmp2); 1031 Ops.push_back(Node->getOperand(2)); 1032 Ops.push_back(Node->getOperand(3)); 1033 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 1034 } 1035 break; 1036 case TargetLowering::Expand: 1037 // If BRTWOWAY_CC is legal for this target, then simply expand this node 1038 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 1039 // BRCOND/BR pair. 1040 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 1041 if (Tmp2.getOpcode() == ISD::SETCC) { 1042 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 1043 Tmp2.getOperand(0), Tmp2.getOperand(1), 1044 Node->getOperand(2), Node->getOperand(3)); 1045 } else { 1046 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 1047 DAG.getConstant(0, Tmp2.getValueType()), 1048 Node->getOperand(2), Node->getOperand(3)); 1049 } 1050 } else { 1051 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 1052 Node->getOperand(2)); 1053 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 1054 } 1055 Result = LegalizeOp(Result); // Relegalize new nodes. 1056 break; 1057 } 1058 break; 1059 case ISD::BRTWOWAY_CC: 1060 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1061 if (isTypeLegal(Node->getOperand(2).getValueType())) { 1062 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 1063 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 1064 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 1065 Tmp3 != Node->getOperand(3)) { 1066 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3, 1067 Node->getOperand(4), Node->getOperand(5)); 1068 } 1069 break; 1070 } else { 1071 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1072 Node->getOperand(2), // LHS 1073 Node->getOperand(3), // RHS 1074 Node->getOperand(1))); 1075 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 1076 // pair. 1077 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 1078 default: assert(0 && "This action is not supported yet!"); 1079 case TargetLowering::Legal: 1080 // If we get a SETCC back from legalizing the SETCC node we just 1081 // created, then use its LHS, RHS, and CC directly in creating a new 1082 // node. Otherwise, select between the true and false value based on 1083 // comparing the result of the legalized with zero. 1084 if (Tmp2.getOpcode() == ISD::SETCC) { 1085 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 1086 Tmp2.getOperand(0), Tmp2.getOperand(1), 1087 Node->getOperand(4), Node->getOperand(5)); 1088 } else { 1089 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 1090 DAG.getConstant(0, Tmp2.getValueType()), 1091 Node->getOperand(4), Node->getOperand(5)); 1092 } 1093 break; 1094 case TargetLowering::Expand: 1095 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 1096 Node->getOperand(4)); 1097 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 1098 break; 1099 } 1100 Result = LegalizeOp(Result); // Relegalize new nodes. 1101 } 1102 break; 1103 case ISD::LOAD: { 1104 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1105 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1106 1107 MVT::ValueType VT = Node->getValueType(0); 1108 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1109 default: assert(0 && "This action is not supported yet!"); 1110 case TargetLowering::Custom: { 1111 SDOperand Op = DAG.getLoad(Node->getValueType(0), 1112 Tmp1, Tmp2, Node->getOperand(2)); 1113 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 1114 if (Tmp.Val) { 1115 Result = LegalizeOp(Tmp); 1116 // Since loads produce two values, make sure to remember that we legalized 1117 // both of them. 1118 AddLegalizedOperand(SDOperand(Node, 0), Result); 1119 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1120 return Result.getValue(Op.ResNo); 1121 } 1122 // FALLTHROUGH if the target thinks it is legal. 1123 } 1124 case TargetLowering::Legal: 1125 if (Tmp1 != Node->getOperand(0) || 1126 Tmp2 != Node->getOperand(1)) 1127 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, 1128 Node->getOperand(2)); 1129 else 1130 Result = SDOperand(Node, 0); 1131 1132 // Since loads produce two values, make sure to remember that we legalized 1133 // both of them. 1134 AddLegalizedOperand(SDOperand(Node, 0), Result); 1135 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1136 return Result.getValue(Op.ResNo); 1137 } 1138 assert(0 && "Unreachable"); 1139 } 1140 case ISD::EXTLOAD: 1141 case ISD::SEXTLOAD: 1142 case ISD::ZEXTLOAD: { 1143 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1144 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1145 1146 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 1147 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 1148 default: assert(0 && "This action is not supported yet!"); 1149 case TargetLowering::Promote: 1150 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 1151 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1152 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 1153 // Since loads produce two values, make sure to remember that we legalized 1154 // both of them. 1155 AddLegalizedOperand(SDOperand(Node, 0), Result); 1156 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1157 return Result.getValue(Op.ResNo); 1158 1159 case TargetLowering::Custom: { 1160 SDOperand Op = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1161 Tmp1, Tmp2, Node->getOperand(2), 1162 SrcVT); 1163 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 1164 if (Tmp.Val) { 1165 Result = LegalizeOp(Tmp); 1166 // Since loads produce two values, make sure to remember that we legalized 1167 // both of them. 1168 AddLegalizedOperand(SDOperand(Node, 0), Result); 1169 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1170 return Result.getValue(Op.ResNo); 1171 } 1172 // FALLTHROUGH if the target thinks it is legal. 1173 } 1174 case TargetLowering::Legal: 1175 if (Tmp1 != Node->getOperand(0) || 1176 Tmp2 != Node->getOperand(1)) 1177 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1178 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1179 else 1180 Result = SDOperand(Node, 0); 1181 1182 // Since loads produce two values, make sure to remember that we legalized 1183 // both of them. 1184 AddLegalizedOperand(SDOperand(Node, 0), Result); 1185 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1186 return Result.getValue(Op.ResNo); 1187 case TargetLowering::Expand: 1188 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1189 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1190 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 1191 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1192 Result = LegalizeOp(Result); // Relegalize new nodes. 1193 Load = LegalizeOp(Load); 1194 AddLegalizedOperand(SDOperand(Node, 0), Result); 1195 AddLegalizedOperand(SDOperand(Node, 1), Load.getValue(1)); 1196 if (Op.ResNo) 1197 return Load.getValue(1); 1198 return Result; 1199 } 1200 assert(Node->getOpcode() != ISD::EXTLOAD && 1201 "EXTLOAD should always be supported!"); 1202 // Turn the unsupported load into an EXTLOAD followed by an explicit 1203 // zero/sign extend inreg. 1204 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1205 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1206 SDOperand ValRes; 1207 if (Node->getOpcode() == ISD::SEXTLOAD) 1208 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1209 Result, DAG.getValueType(SrcVT)); 1210 else 1211 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1212 Result = LegalizeOp(Result); // Relegalize new nodes. 1213 ValRes = LegalizeOp(ValRes); // Relegalize new nodes. 1214 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 1215 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1216 if (Op.ResNo) 1217 return Result.getValue(1); 1218 return ValRes; 1219 } 1220 assert(0 && "Unreachable"); 1221 } 1222 case ISD::EXTRACT_ELEMENT: { 1223 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1224 switch (getTypeAction(OpTy)) { 1225 default: 1226 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1227 break; 1228 case Legal: 1229 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1230 // 1 -> Hi 1231 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1232 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1233 TLI.getShiftAmountTy())); 1234 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1235 } else { 1236 // 0 -> Lo 1237 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1238 Node->getOperand(0)); 1239 } 1240 Result = LegalizeOp(Result); 1241 break; 1242 case Expand: 1243 // Get both the low and high parts. 1244 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1245 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1246 Result = Tmp2; // 1 -> Hi 1247 else 1248 Result = Tmp1; // 0 -> Lo 1249 break; 1250 } 1251 break; 1252 } 1253 1254 case ISD::CopyToReg: 1255 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1256 1257 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1258 "Register type must be legal!"); 1259 // Legalize the incoming value (must be a legal type). 1260 Tmp2 = LegalizeOp(Node->getOperand(2)); 1261 if (Node->getNumValues() == 1) { 1262 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2)) 1263 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1, 1264 Node->getOperand(1), Tmp2); 1265 } else { 1266 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1267 if (Node->getNumOperands() == 4) 1268 Tmp3 = LegalizeOp(Node->getOperand(3)); 1269 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 1270 (Node->getNumOperands() == 4 && Tmp3 != Node->getOperand(3))) { 1271 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 1272 Result = DAG.getCopyToReg(Tmp1, Reg, Tmp2, Tmp3); 1273 } 1274 1275 // Since this produces two values, make sure to remember that we legalized 1276 // both of them. 1277 AddLegalizedOperand(SDOperand(Node, 0), Result); 1278 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1279 return Result.getValue(Op.ResNo); 1280 } 1281 break; 1282 1283 case ISD::RET: 1284 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1285 switch (Node->getNumOperands()) { 1286 case 2: // ret val 1287 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1288 case Legal: 1289 Tmp2 = LegalizeOp(Node->getOperand(1)); 1290 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1291 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1292 break; 1293 case Expand: { 1294 SDOperand Lo, Hi; 1295 ExpandOp(Node->getOperand(1), Lo, Hi); 1296 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1297 break; 1298 } 1299 case Promote: 1300 Tmp2 = PromoteOp(Node->getOperand(1)); 1301 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1302 break; 1303 } 1304 break; 1305 case 1: // ret void 1306 if (Tmp1 != Node->getOperand(0)) 1307 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 1308 break; 1309 default: { // ret <values> 1310 std::vector<SDOperand> NewValues; 1311 NewValues.push_back(Tmp1); 1312 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1313 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1314 case Legal: 1315 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1316 break; 1317 case Expand: { 1318 SDOperand Lo, Hi; 1319 ExpandOp(Node->getOperand(i), Lo, Hi); 1320 NewValues.push_back(Lo); 1321 NewValues.push_back(Hi); 1322 break; 1323 } 1324 case Promote: 1325 assert(0 && "Can't promote multiple return value yet!"); 1326 } 1327 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1328 break; 1329 } 1330 } 1331 1332 switch (TLI.getOperationAction(Node->getOpcode(), 1333 Node->getValueType(0))) { 1334 default: assert(0 && "This action is not supported yet!"); 1335 case TargetLowering::Custom: { 1336 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1337 if (Tmp.Val) { 1338 Result = LegalizeOp(Tmp); 1339 break; 1340 } 1341 // FALLTHROUGH if the target thinks it is legal. 1342 } 1343 case TargetLowering::Legal: 1344 // Nothing to do. 1345 break; 1346 } 1347 break; 1348 case ISD::STORE: { 1349 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1350 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1351 1352 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1353 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1354 if (CFP->getValueType(0) == MVT::f32) { 1355 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1356 DAG.getConstant(FloatToBits(CFP->getValue()), 1357 MVT::i32), 1358 Tmp2, 1359 Node->getOperand(3)); 1360 } else { 1361 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1362 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1363 DAG.getConstant(DoubleToBits(CFP->getValue()), 1364 MVT::i64), 1365 Tmp2, 1366 Node->getOperand(3)); 1367 } 1368 Node = Result.Val; 1369 } 1370 1371 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1372 case Legal: { 1373 SDOperand Val = LegalizeOp(Node->getOperand(1)); 1374 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 1375 Tmp2 != Node->getOperand(2)) 1376 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 1377 Node->getOperand(3)); 1378 1379 MVT::ValueType VT = Result.Val->getOperand(1).getValueType(); 1380 switch (TLI.getOperationAction(Result.Val->getOpcode(), VT)) { 1381 default: assert(0 && "This action is not supported yet!"); 1382 case TargetLowering::Custom: { 1383 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1384 if (Tmp.Val) { 1385 Result = LegalizeOp(Tmp); 1386 break; 1387 } 1388 // FALLTHROUGH if the target thinks it is legal. 1389 } 1390 case TargetLowering::Legal: 1391 // Nothing to do. 1392 break; 1393 } 1394 break; 1395 } 1396 case Promote: 1397 // Truncate the value and store the result. 1398 Tmp3 = PromoteOp(Node->getOperand(1)); 1399 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1400 Node->getOperand(3), 1401 DAG.getValueType(Node->getOperand(1).getValueType())); 1402 break; 1403 1404 case Expand: 1405 SDOperand Lo, Hi; 1406 unsigned IncrementSize; 1407 ExpandOp(Node->getOperand(1), Lo, Hi); 1408 1409 if (!TLI.isLittleEndian()) 1410 std::swap(Lo, Hi); 1411 1412 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1413 Node->getOperand(3)); 1414 // If this is a vector type, then we have to calculate the increment as 1415 // the product of the element size in bytes, and the number of elements 1416 // in the high half of the vector. 1417 if (MVT::Vector == Hi.getValueType()) { 1418 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue(); 1419 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT(); 1420 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8; 1421 } else { 1422 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1423 } 1424 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1425 getIntPtrConstant(IncrementSize)); 1426 assert(isTypeLegal(Tmp2.getValueType()) && 1427 "Pointers must be legal!"); 1428 //Again, claiming both parts of the store came form the same Instr 1429 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1430 Node->getOperand(3)); 1431 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1432 break; 1433 } 1434 break; 1435 } 1436 case ISD::PCMARKER: 1437 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1438 if (Tmp1 != Node->getOperand(0)) 1439 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 1440 break; 1441 case ISD::STACKSAVE: 1442 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1443 if (Tmp1 != Node->getOperand(0)) { 1444 std::vector<MVT::ValueType> VTs; 1445 VTs.push_back(Node->getValueType(0)); 1446 VTs.push_back(MVT::Other); 1447 std::vector<SDOperand> Ops; 1448 Ops.push_back(Tmp1); 1449 Result = DAG.getNode(ISD::STACKSAVE, VTs, Ops); 1450 } 1451 1452 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 1453 default: assert(0 && "This action is not supported yet!"); 1454 case TargetLowering::Custom: { 1455 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1456 if (Tmp.Val) { 1457 Result = LegalizeOp(Tmp); 1458 break; 1459 } 1460 // FALLTHROUGH if the target thinks it is legal. 1461 } 1462 case TargetLowering::Legal: 1463 // Since stacksave produce two values, make sure to remember that we 1464 // legalized both of them. 1465 AddLegalizedOperand(SDOperand(Node, 0), Result); 1466 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1467 return Result.getValue(Op.ResNo); 1468 case TargetLowering::Expand: 1469 // Expand to CopyFromReg if the target set 1470 // StackPointerRegisterToSaveRestore. 1471 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1472 Tmp1 = DAG.getCopyFromReg(Tmp1, SP, 1473 Node->getValueType(0)); 1474 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1475 AddLegalizedOperand(SDOperand(Node, 1), Tmp1.getValue(1)); 1476 return Tmp1.getValue(Op.ResNo); 1477 } else { 1478 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 1479 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1480 AddLegalizedOperand(SDOperand(Node, 1), Node->getOperand(0)); 1481 return Op.ResNo ? Node->getOperand(0) : Tmp1; 1482 } 1483 } 1484 1485 case ISD::STACKRESTORE: 1486 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1487 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1488 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1489 Result = DAG.getNode(ISD::STACKRESTORE, MVT::Other, Tmp1, Tmp2); 1490 1491 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 1492 default: assert(0 && "This action is not supported yet!"); 1493 case TargetLowering::Custom: { 1494 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1495 if (Tmp.Val) { 1496 Result = LegalizeOp(Tmp); 1497 break; 1498 } 1499 // FALLTHROUGH if the target thinks it is legal. 1500 } 1501 case TargetLowering::Legal: 1502 break; 1503 case TargetLowering::Expand: 1504 // Expand to CopyToReg if the target set 1505 // StackPointerRegisterToSaveRestore. 1506 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1507 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 1508 } else { 1509 Result = Tmp1; 1510 } 1511 break; 1512 } 1513 break; 1514 1515 case ISD::READCYCLECOUNTER: 1516 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1517 if (Tmp1 != Node->getOperand(0)) { 1518 std::vector<MVT::ValueType> rtypes; 1519 std::vector<SDOperand> rvals; 1520 rtypes.push_back(MVT::i64); 1521 rtypes.push_back(MVT::Other); 1522 rvals.push_back(Tmp1); 1523 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals); 1524 } 1525 1526 // Since rdcc produce two values, make sure to remember that we legalized 1527 // both of them. 1528 AddLegalizedOperand(SDOperand(Node, 0), Result); 1529 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1530 return Result.getValue(Op.ResNo); 1531 1532 case ISD::TRUNCSTORE: { 1533 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1534 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1535 1536 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1537 case Promote: 1538 case Expand: 1539 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 1540 case Legal: 1541 Tmp2 = LegalizeOp(Node->getOperand(1)); 1542 1543 // The only promote case we handle is TRUNCSTORE:i1 X into 1544 // -> TRUNCSTORE:i8 (and X, 1) 1545 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1546 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1547 TargetLowering::Promote) { 1548 // Promote the bool to a mask then store. 1549 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1550 DAG.getConstant(1, Tmp2.getValueType())); 1551 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1552 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1553 1554 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1555 Tmp3 != Node->getOperand(2)) { 1556 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1557 Node->getOperand(3), Node->getOperand(4)); 1558 } 1559 1560 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT(); 1561 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) { 1562 default: assert(0 && "This action is not supported yet!"); 1563 case TargetLowering::Custom: { 1564 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1565 if (Tmp.Val) { 1566 Result = LegalizeOp(Tmp); 1567 break; 1568 } 1569 // FALLTHROUGH if the target thinks it is legal. 1570 } 1571 case TargetLowering::Legal: 1572 // Nothing to do. 1573 break; 1574 } 1575 break; 1576 } 1577 break; 1578 } 1579 case ISD::SELECT: 1580 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1581 case Expand: assert(0 && "It's impossible to expand bools"); 1582 case Legal: 1583 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1584 break; 1585 case Promote: 1586 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1587 break; 1588 } 1589 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1590 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1591 1592 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1593 default: assert(0 && "This action is not supported yet!"); 1594 case TargetLowering::Expand: 1595 if (Tmp1.getOpcode() == ISD::SETCC) { 1596 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1597 Tmp2, Tmp3, 1598 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1599 } else { 1600 // Make sure the condition is either zero or one. It may have been 1601 // promoted from something else. 1602 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1603 Result = DAG.getSelectCC(Tmp1, 1604 DAG.getConstant(0, Tmp1.getValueType()), 1605 Tmp2, Tmp3, ISD::SETNE); 1606 } 1607 Result = LegalizeOp(Result); // Relegalize new nodes. 1608 break; 1609 case TargetLowering::Custom: { 1610 SDOperand Tmp = 1611 TLI.LowerOperation(DAG.getNode(ISD::SELECT, Node->getValueType(0), 1612 Tmp1, Tmp2, Tmp3), DAG); 1613 if (Tmp.Val) { 1614 Result = LegalizeOp(Tmp); 1615 break; 1616 } 1617 // FALLTHROUGH if the target thinks it is legal. 1618 } 1619 case TargetLowering::Legal: 1620 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1621 Tmp3 != Node->getOperand(2)) 1622 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 1623 Tmp1, Tmp2, Tmp3); 1624 break; 1625 case TargetLowering::Promote: { 1626 MVT::ValueType NVT = 1627 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1628 unsigned ExtOp, TruncOp; 1629 if (MVT::isInteger(Tmp2.getValueType())) { 1630 ExtOp = ISD::ANY_EXTEND; 1631 TruncOp = ISD::TRUNCATE; 1632 } else { 1633 ExtOp = ISD::FP_EXTEND; 1634 TruncOp = ISD::FP_ROUND; 1635 } 1636 // Promote each of the values to the new type. 1637 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1638 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1639 // Perform the larger operation, then round down. 1640 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1641 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1642 Result = LegalizeOp(Result); 1643 break; 1644 } 1645 } 1646 break; 1647 case ISD::SELECT_CC: 1648 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1649 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1650 1651 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1652 // Everything is legal, see if we should expand this op or something. 1653 switch (TLI.getOperationAction(ISD::SELECT_CC, 1654 Node->getOperand(0).getValueType())) { 1655 default: assert(0 && "This action is not supported yet!"); 1656 case TargetLowering::Custom: { 1657 SDOperand Tmp = 1658 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), 1659 Node->getOperand(0), 1660 Node->getOperand(1), Tmp3, Tmp4, 1661 Node->getOperand(4)), DAG); 1662 if (Tmp.Val) { 1663 Result = LegalizeOp(Tmp); 1664 break; 1665 } 1666 } // FALLTHROUGH if the target can't lower this operation after all. 1667 case TargetLowering::Legal: 1668 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1669 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1670 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1671 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { 1672 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1,Tmp2, 1673 Tmp3, Tmp4, Node->getOperand(4)); 1674 } 1675 break; 1676 } 1677 break; 1678 } else { 1679 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1680 Node->getOperand(0), // LHS 1681 Node->getOperand(1), // RHS 1682 Node->getOperand(4))); 1683 // If we get a SETCC back from legalizing the SETCC node we just 1684 // created, then use its LHS, RHS, and CC directly in creating a new 1685 // node. Otherwise, select between the true and false value based on 1686 // comparing the result of the legalized with zero. 1687 if (Tmp1.getOpcode() == ISD::SETCC) { 1688 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1689 Tmp1.getOperand(0), Tmp1.getOperand(1), 1690 Tmp3, Tmp4, Tmp1.getOperand(2)); 1691 } else { 1692 Result = DAG.getSelectCC(Tmp1, 1693 DAG.getConstant(0, Tmp1.getValueType()), 1694 Tmp3, Tmp4, ISD::SETNE); 1695 } 1696 } 1697 break; 1698 case ISD::SETCC: 1699 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1700 case Legal: 1701 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1702 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1703 break; 1704 case Promote: 1705 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1706 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1707 1708 // If this is an FP compare, the operands have already been extended. 1709 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1710 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1711 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1712 1713 // Otherwise, we have to insert explicit sign or zero extends. Note 1714 // that we could insert sign extends for ALL conditions, but zero extend 1715 // is cheaper on many machines (an AND instead of two shifts), so prefer 1716 // it. 1717 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1718 default: assert(0 && "Unknown integer comparison!"); 1719 case ISD::SETEQ: 1720 case ISD::SETNE: 1721 case ISD::SETUGE: 1722 case ISD::SETUGT: 1723 case ISD::SETULE: 1724 case ISD::SETULT: 1725 // ALL of these operations will work if we either sign or zero extend 1726 // the operands (including the unsigned comparisons!). Zero extend is 1727 // usually a simpler/cheaper operation, so prefer it. 1728 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1729 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1730 break; 1731 case ISD::SETGE: 1732 case ISD::SETGT: 1733 case ISD::SETLT: 1734 case ISD::SETLE: 1735 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1736 DAG.getValueType(VT)); 1737 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1738 DAG.getValueType(VT)); 1739 break; 1740 } 1741 } 1742 break; 1743 case Expand: 1744 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1745 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1746 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1747 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1748 case ISD::SETEQ: 1749 case ISD::SETNE: 1750 if (RHSLo == RHSHi) 1751 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1752 if (RHSCST->isAllOnesValue()) { 1753 // Comparison to -1. 1754 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1755 Tmp2 = RHSLo; 1756 break; 1757 } 1758 1759 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1760 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1761 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1762 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1763 break; 1764 default: 1765 // If this is a comparison of the sign bit, just look at the top part. 1766 // X > -1, x < 0 1767 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1768 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1769 CST->getValue() == 0) || // X < 0 1770 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1771 (CST->isAllOnesValue()))) { // X > -1 1772 Tmp1 = LHSHi; 1773 Tmp2 = RHSHi; 1774 break; 1775 } 1776 1777 // FIXME: This generated code sucks. 1778 ISD::CondCode LowCC; 1779 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1780 default: assert(0 && "Unknown integer setcc!"); 1781 case ISD::SETLT: 1782 case ISD::SETULT: LowCC = ISD::SETULT; break; 1783 case ISD::SETGT: 1784 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1785 case ISD::SETLE: 1786 case ISD::SETULE: LowCC = ISD::SETULE; break; 1787 case ISD::SETGE: 1788 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1789 } 1790 1791 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1792 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1793 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1794 1795 // NOTE: on targets without efficient SELECT of bools, we can always use 1796 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1797 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1798 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1799 Node->getOperand(2)); 1800 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1801 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1802 Result, Tmp1, Tmp2)); 1803 AddLegalizedOperand(SDOperand(Node, 0), Result); 1804 return Result; 1805 } 1806 } 1807 1808 switch(TLI.getOperationAction(ISD::SETCC, 1809 Node->getOperand(0).getValueType())) { 1810 default: 1811 assert(0 && "Cannot handle this action for SETCC yet!"); 1812 break; 1813 case TargetLowering::Promote: { 1814 // First step, figure out the appropriate operation to use. 1815 // Allow SETCC to not be supported for all legal data types 1816 // Mostly this targets FP 1817 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1818 MVT::ValueType OldVT = NewInTy; 1819 1820 // Scan for the appropriate larger type to use. 1821 while (1) { 1822 NewInTy = (MVT::ValueType)(NewInTy+1); 1823 1824 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1825 "Fell off of the edge of the integer world"); 1826 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1827 "Fell off of the edge of the floating point world"); 1828 1829 // If the target supports SETCC of this type, use it. 1830 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 1831 break; 1832 } 1833 if (MVT::isInteger(NewInTy)) 1834 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1835 else { 1836 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1837 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1838 } 1839 1840 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1841 Node->getOperand(2)); 1842 Result = LegalizeOp(Result); 1843 break; 1844 } 1845 case TargetLowering::Custom: { 1846 SDOperand Tmp = 1847 TLI.LowerOperation(DAG.getNode(ISD::SETCC, Node->getValueType(0), 1848 Tmp1, Tmp2, Node->getOperand(2)), DAG); 1849 if (Tmp.Val) { 1850 Result = LegalizeOp(Tmp); 1851 break; 1852 } 1853 // FALLTHROUGH if the target thinks it is legal. 1854 } 1855 case TargetLowering::Legal: 1856 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1857 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1858 Node->getOperand(2)); 1859 break; 1860 case TargetLowering::Expand: 1861 // Expand a setcc node into a select_cc of the same condition, lhs, and 1862 // rhs that selects between const 1 (true) and const 0 (false). 1863 MVT::ValueType VT = Node->getValueType(0); 1864 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1865 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1866 Node->getOperand(2)); 1867 Result = LegalizeOp(Result); 1868 break; 1869 } 1870 break; 1871 1872 case ISD::MEMSET: 1873 case ISD::MEMCPY: 1874 case ISD::MEMMOVE: { 1875 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1876 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1877 1878 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1879 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1880 case Expand: assert(0 && "Cannot expand a byte!"); 1881 case Legal: 1882 Tmp3 = LegalizeOp(Node->getOperand(2)); 1883 break; 1884 case Promote: 1885 Tmp3 = PromoteOp(Node->getOperand(2)); 1886 break; 1887 } 1888 } else { 1889 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1890 } 1891 1892 SDOperand Tmp4; 1893 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1894 case Expand: { 1895 // Length is too big, just take the lo-part of the length. 1896 SDOperand HiPart; 1897 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1898 break; 1899 } 1900 case Legal: 1901 Tmp4 = LegalizeOp(Node->getOperand(3)); 1902 break; 1903 case Promote: 1904 Tmp4 = PromoteOp(Node->getOperand(3)); 1905 break; 1906 } 1907 1908 SDOperand Tmp5; 1909 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1910 case Expand: assert(0 && "Cannot expand this yet!"); 1911 case Legal: 1912 Tmp5 = LegalizeOp(Node->getOperand(4)); 1913 break; 1914 case Promote: 1915 Tmp5 = PromoteOp(Node->getOperand(4)); 1916 break; 1917 } 1918 1919 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1920 default: assert(0 && "This action not implemented for this operation!"); 1921 case TargetLowering::Custom: { 1922 SDOperand Tmp = 1923 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 1924 Tmp2, Tmp3, Tmp4, Tmp5), DAG); 1925 if (Tmp.Val) { 1926 Result = LegalizeOp(Tmp); 1927 break; 1928 } 1929 // FALLTHROUGH if the target thinks it is legal. 1930 } 1931 case TargetLowering::Legal: 1932 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1933 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 1934 Tmp5 != Node->getOperand(4)) { 1935 std::vector<SDOperand> Ops; 1936 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 1937 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 1938 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 1939 } 1940 break; 1941 case TargetLowering::Expand: { 1942 // Otherwise, the target does not support this operation. Lower the 1943 // operation to an explicit libcall as appropriate. 1944 MVT::ValueType IntPtr = TLI.getPointerTy(); 1945 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1946 std::vector<std::pair<SDOperand, const Type*> > Args; 1947 1948 const char *FnName = 0; 1949 if (Node->getOpcode() == ISD::MEMSET) { 1950 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1951 // Extend the ubyte argument to be an int value for the call. 1952 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1953 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1954 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1955 1956 FnName = "memset"; 1957 } else if (Node->getOpcode() == ISD::MEMCPY || 1958 Node->getOpcode() == ISD::MEMMOVE) { 1959 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1960 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1961 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1962 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1963 } else { 1964 assert(0 && "Unknown op!"); 1965 } 1966 1967 std::pair<SDOperand,SDOperand> CallResult = 1968 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1969 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1970 Result = LegalizeOp(CallResult.second); 1971 break; 1972 } 1973 } 1974 break; 1975 } 1976 1977 case ISD::READPORT: 1978 Tmp1 = LegalizeOp(Node->getOperand(0)); 1979 Tmp2 = LegalizeOp(Node->getOperand(1)); 1980 1981 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1982 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1983 std::vector<SDOperand> Ops; 1984 Ops.push_back(Tmp1); 1985 Ops.push_back(Tmp2); 1986 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1987 } else 1988 Result = SDOperand(Node, 0); 1989 // Since these produce two values, make sure to remember that we legalized 1990 // both of them. 1991 AddLegalizedOperand(SDOperand(Node, 0), Result); 1992 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1993 return Result.getValue(Op.ResNo); 1994 case ISD::WRITEPORT: 1995 Tmp1 = LegalizeOp(Node->getOperand(0)); 1996 Tmp2 = LegalizeOp(Node->getOperand(1)); 1997 Tmp3 = LegalizeOp(Node->getOperand(2)); 1998 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1999 Tmp3 != Node->getOperand(2)) 2000 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 2001 break; 2002 2003 case ISD::READIO: 2004 Tmp1 = LegalizeOp(Node->getOperand(0)); 2005 Tmp2 = LegalizeOp(Node->getOperand(1)); 2006 2007 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2008 case TargetLowering::Custom: 2009 default: assert(0 && "This action not implemented for this operation!"); 2010 case TargetLowering::Legal: 2011 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 2012 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 2013 std::vector<SDOperand> Ops; 2014 Ops.push_back(Tmp1); 2015 Ops.push_back(Tmp2); 2016 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 2017 } else 2018 Result = SDOperand(Node, 0); 2019 break; 2020 case TargetLowering::Expand: 2021 // Replace this with a load from memory. 2022 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 2023 Node->getOperand(1), DAG.getSrcValue(NULL)); 2024 Result = LegalizeOp(Result); 2025 break; 2026 } 2027 2028 // Since these produce two values, make sure to remember that we legalized 2029 // both of them. 2030 AddLegalizedOperand(SDOperand(Node, 0), Result); 2031 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2032 return Result.getValue(Op.ResNo); 2033 2034 case ISD::WRITEIO: 2035 Tmp1 = LegalizeOp(Node->getOperand(0)); 2036 Tmp2 = LegalizeOp(Node->getOperand(1)); 2037 Tmp3 = LegalizeOp(Node->getOperand(2)); 2038 2039 switch (TLI.getOperationAction(Node->getOpcode(), 2040 Node->getOperand(1).getValueType())) { 2041 case TargetLowering::Custom: 2042 default: assert(0 && "This action not implemented for this operation!"); 2043 case TargetLowering::Legal: 2044 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 2045 Tmp3 != Node->getOperand(2)) 2046 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 2047 break; 2048 case TargetLowering::Expand: 2049 // Replace this with a store to memory. 2050 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 2051 Node->getOperand(1), Node->getOperand(2), 2052 DAG.getSrcValue(NULL)); 2053 Result = LegalizeOp(Result); 2054 break; 2055 } 2056 break; 2057 2058 case ISD::ADD_PARTS: 2059 case ISD::SUB_PARTS: 2060 case ISD::SHL_PARTS: 2061 case ISD::SRA_PARTS: 2062 case ISD::SRL_PARTS: { 2063 std::vector<SDOperand> Ops; 2064 bool Changed = false; 2065 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2066 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2067 Changed |= Ops.back() != Node->getOperand(i); 2068 } 2069 if (Changed) { 2070 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 2071 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 2072 } 2073 2074 switch (TLI.getOperationAction(Node->getOpcode(), 2075 Node->getValueType(0))) { 2076 default: assert(0 && "This action is not supported yet!"); 2077 case TargetLowering::Custom: { 2078 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 2079 if (Tmp.Val) { 2080 SDOperand Tmp2, RetVal(0,0); 2081 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2082 Tmp2 = LegalizeOp(Tmp.getValue(i)); 2083 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2084 if (i == Op.ResNo) 2085 RetVal = Tmp2; 2086 } 2087 assert(RetVal.Val && "Illegal result number"); 2088 return RetVal; 2089 } 2090 // FALLTHROUGH if the target thinks it is legal. 2091 } 2092 case TargetLowering::Legal: 2093 // Nothing to do. 2094 break; 2095 } 2096 2097 // Since these produce multiple values, make sure to remember that we 2098 // legalized all of them. 2099 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2100 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2101 return Result.getValue(Op.ResNo); 2102 } 2103 2104 // Binary operators 2105 case ISD::ADD: 2106 case ISD::SUB: 2107 case ISD::MUL: 2108 case ISD::MULHS: 2109 case ISD::MULHU: 2110 case ISD::UDIV: 2111 case ISD::SDIV: 2112 case ISD::AND: 2113 case ISD::OR: 2114 case ISD::XOR: 2115 case ISD::SHL: 2116 case ISD::SRL: 2117 case ISD::SRA: 2118 case ISD::FADD: 2119 case ISD::FSUB: 2120 case ISD::FMUL: 2121 case ISD::FDIV: 2122 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2123 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2124 case Expand: assert(0 && "Not possible"); 2125 case Legal: 2126 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2127 break; 2128 case Promote: 2129 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2130 break; 2131 } 2132 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2133 case TargetLowering::Custom: { 2134 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2); 2135 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 2136 if (Tmp.Val) { 2137 Tmp = LegalizeOp(Tmp); // Relegalize input. 2138 AddLegalizedOperand(Op, Tmp); 2139 return Tmp; 2140 } //else it was considered legal and we fall through 2141 } 2142 case TargetLowering::Legal: 2143 if (Tmp1 != Node->getOperand(0) || 2144 Tmp2 != Node->getOperand(1)) 2145 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 2146 break; 2147 default: 2148 assert(0 && "Operation not supported"); 2149 } 2150 break; 2151 2152 case ISD::BUILD_PAIR: { 2153 MVT::ValueType PairTy = Node->getValueType(0); 2154 // TODO: handle the case where the Lo and Hi operands are not of legal type 2155 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2156 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2157 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2158 case TargetLowering::Legal: 2159 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2160 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2161 break; 2162 case TargetLowering::Promote: 2163 case TargetLowering::Custom: 2164 assert(0 && "Cannot promote/custom this yet!"); 2165 case TargetLowering::Expand: 2166 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2167 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2168 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2169 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2170 TLI.getShiftAmountTy())); 2171 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2)); 2172 break; 2173 } 2174 break; 2175 } 2176 2177 case ISD::UREM: 2178 case ISD::SREM: 2179 case ISD::FREM: 2180 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2181 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2182 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2183 case TargetLowering::Custom: { 2184 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 2185 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 2186 if (Tmp.Val) { 2187 Tmp = LegalizeOp(Tmp); // Relegalize input. 2188 AddLegalizedOperand(Op, Tmp); 2189 return Tmp; 2190 } //else it was considered legal and we fall through 2191 } 2192 case TargetLowering::Legal: 2193 if (Tmp1 != Node->getOperand(0) || 2194 Tmp2 != Node->getOperand(1)) 2195 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2196 Tmp2); 2197 break; 2198 case TargetLowering::Promote: 2199 assert(0 && "Cannot promote handle this yet!"); 2200 case TargetLowering::Expand: 2201 if (MVT::isInteger(Node->getValueType(0))) { 2202 MVT::ValueType VT = Node->getValueType(0); 2203 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2204 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 2205 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2206 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2207 } else { 2208 // Floating point mod -> fmod libcall. 2209 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 2210 SDOperand Dummy; 2211 Result = ExpandLibCall(FnName, Node, Dummy); 2212 } 2213 break; 2214 } 2215 break; 2216 2217 case ISD::ROTL: 2218 case ISD::ROTR: 2219 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2220 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2221 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2222 case TargetLowering::Custom: 2223 case TargetLowering::Promote: 2224 case TargetLowering::Expand: 2225 assert(0 && "Cannot handle this yet!"); 2226 case TargetLowering::Legal: 2227 if (Tmp1 != Node->getOperand(0) || 2228 Tmp2 != Node->getOperand(1)) 2229 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2230 Tmp2); 2231 break; 2232 } 2233 break; 2234 2235 case ISD::BSWAP: 2236 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2237 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2238 case TargetLowering::Legal: 2239 if (Tmp1 != Node->getOperand(0)) 2240 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2241 break; 2242 case TargetLowering::Promote: { 2243 MVT::ValueType OVT = Tmp1.getValueType(); 2244 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2245 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT); 2246 2247 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2248 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2249 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2250 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2251 Result = LegalizeOp(Result); 2252 break; 2253 } 2254 case TargetLowering::Custom: 2255 assert(0 && "Cannot custom legalize this yet!"); 2256 case TargetLowering::Expand: { 2257 MVT::ValueType VT = Tmp1.getValueType(); 2258 switch (VT) { 2259 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 2260 case MVT::i16: 2261 Tmp2 = DAG.getNode(ISD::SHL, VT, Tmp1, 2262 DAG.getConstant(8, TLI.getShiftAmountTy())); 2263 Tmp1 = DAG.getNode(ISD::SRL, VT, Tmp1, 2264 DAG.getConstant(8, TLI.getShiftAmountTy())); 2265 Result = DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 2266 break; 2267 case MVT::i32: 2268 Tmp4 = DAG.getNode(ISD::SHL, VT, Tmp1, 2269 DAG.getConstant(24, TLI.getShiftAmountTy())); 2270 Tmp3 = DAG.getNode(ISD::SHL, VT, Tmp1, 2271 DAG.getConstant(8, TLI.getShiftAmountTy())); 2272 Tmp2 = DAG.getNode(ISD::SRL, VT, Tmp1, 2273 DAG.getConstant(8, TLI.getShiftAmountTy())); 2274 Tmp1 = DAG.getNode(ISD::SRL, VT, Tmp1, 2275 DAG.getConstant(24, TLI.getShiftAmountTy())); 2276 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2277 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2278 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 2279 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 2280 Result = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 2281 break; 2282 case MVT::i64: { 2283 SDOperand Tmp5, Tmp6, Tmp7, Tmp8; 2284 Tmp8 = DAG.getNode(ISD::SHL, VT, Tmp1, 2285 DAG.getConstant(56, TLI.getShiftAmountTy())); 2286 Tmp7 = DAG.getNode(ISD::SHL, VT, Tmp1, 2287 DAG.getConstant(40, TLI.getShiftAmountTy())); 2288 Tmp6 = DAG.getNode(ISD::SHL, VT, Tmp1, 2289 DAG.getConstant(24, TLI.getShiftAmountTy())); 2290 Tmp5 = DAG.getNode(ISD::SHL, VT, Tmp1, 2291 DAG.getConstant(8, TLI.getShiftAmountTy())); 2292 Tmp4 = DAG.getNode(ISD::SRL, VT, Tmp1, 2293 DAG.getConstant(8, TLI.getShiftAmountTy())); 2294 Tmp3 = DAG.getNode(ISD::SRL, VT, Tmp1, 2295 DAG.getConstant(24, TLI.getShiftAmountTy())); 2296 Tmp2 = DAG.getNode(ISD::SRL, VT, Tmp1, 2297 DAG.getConstant(40, TLI.getShiftAmountTy())); 2298 Tmp1 = DAG.getNode(ISD::SRL, VT, Tmp1, 2299 DAG.getConstant(56, TLI.getShiftAmountTy())); 2300 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, 2301 DAG.getConstant(0x00FF000000000000ULL, VT)); 2302 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp7, 2303 DAG.getConstant(0x0000FF0000000000ULL, VT)); 2304 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp7, 2305 DAG.getConstant(0x000000FF00000000ULL, VT)); 2306 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp7, 2307 DAG.getConstant(0x00000000FF000000ULL, VT)); 2308 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp7, 2309 DAG.getConstant(0x0000000000FF0000ULL, VT)); 2310 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp7, 2311 DAG.getConstant(0x000000000000FF00ULL, VT)); 2312 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 2313 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 2314 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 2315 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 2316 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 2317 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 2318 Result = DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 2319 break; 2320 } 2321 } 2322 Result = LegalizeOp(Result); 2323 break; 2324 } 2325 } 2326 break; 2327 2328 case ISD::CTPOP: 2329 case ISD::CTTZ: 2330 case ISD::CTLZ: 2331 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2332 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2333 case TargetLowering::Legal: 2334 if (Tmp1 != Node->getOperand(0)) 2335 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2336 break; 2337 case TargetLowering::Promote: { 2338 MVT::ValueType OVT = Tmp1.getValueType(); 2339 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2340 2341 // Zero extend the argument. 2342 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2343 // Perform the larger operation, then subtract if needed. 2344 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2345 switch(Node->getOpcode()) 2346 { 2347 case ISD::CTPOP: 2348 Result = Tmp1; 2349 break; 2350 case ISD::CTTZ: 2351 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2352 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2353 DAG.getConstant(getSizeInBits(NVT), NVT), 2354 ISD::SETEQ); 2355 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2356 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 2357 break; 2358 case ISD::CTLZ: 2359 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2360 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2361 DAG.getConstant(getSizeInBits(NVT) - 2362 getSizeInBits(OVT), NVT)); 2363 break; 2364 } 2365 Result = LegalizeOp(Result); 2366 break; 2367 } 2368 case TargetLowering::Custom: 2369 assert(0 && "Cannot custom handle this yet!"); 2370 case TargetLowering::Expand: 2371 switch(Node->getOpcode()) 2372 { 2373 case ISD::CTPOP: { 2374 static const uint64_t mask[6] = { 2375 0x5555555555555555ULL, 0x3333333333333333ULL, 2376 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2377 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2378 }; 2379 MVT::ValueType VT = Tmp1.getValueType(); 2380 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 2381 unsigned len = getSizeInBits(VT); 2382 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2383 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2384 Tmp2 = DAG.getConstant(mask[i], VT); 2385 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2386 Tmp1 = DAG.getNode(ISD::ADD, VT, 2387 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 2388 DAG.getNode(ISD::AND, VT, 2389 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 2390 Tmp2)); 2391 } 2392 Result = LegalizeOp(Tmp1); 2393 break; 2394 } 2395 case ISD::CTLZ: { 2396 /* for now, we do this: 2397 x = x | (x >> 1); 2398 x = x | (x >> 2); 2399 ... 2400 x = x | (x >>16); 2401 x = x | (x >>32); // for 64-bit input 2402 return popcount(~x); 2403 2404 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ 2405 MVT::ValueType VT = Tmp1.getValueType(); 2406 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 2407 unsigned len = getSizeInBits(VT); 2408 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2409 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2410 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, 2411 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); 2412 } 2413 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); 2414 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 2415 break; 2416 } 2417 case ISD::CTTZ: { 2418 // for now, we use: { return popcount(~x & (x - 1)); } 2419 // unless the target has ctlz but not ctpop, in which case we use: 2420 // { return 32 - nlz(~x & (x-1)); } 2421 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2422 MVT::ValueType VT = Tmp1.getValueType(); 2423 Tmp2 = DAG.getConstant(~0ULL, VT); 2424 Tmp3 = DAG.getNode(ISD::AND, VT, 2425 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), 2426 DAG.getNode(ISD::SUB, VT, Tmp1, 2427 DAG.getConstant(1, VT))); 2428 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead 2429 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 2430 TLI.isOperationLegal(ISD::CTLZ, VT)) { 2431 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, 2432 DAG.getConstant(getSizeInBits(VT), VT), 2433 DAG.getNode(ISD::CTLZ, VT, Tmp3))); 2434 } else { 2435 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 2436 } 2437 break; 2438 } 2439 default: 2440 assert(0 && "Cannot expand this yet!"); 2441 break; 2442 } 2443 break; 2444 } 2445 break; 2446 2447 // Unary operators 2448 case ISD::FABS: 2449 case ISD::FNEG: 2450 case ISD::FSQRT: 2451 case ISD::FSIN: 2452 case ISD::FCOS: 2453 Tmp1 = LegalizeOp(Node->getOperand(0)); 2454 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2455 case TargetLowering::Legal: 2456 if (Tmp1 != Node->getOperand(0)) 2457 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2458 break; 2459 case TargetLowering::Promote: 2460 case TargetLowering::Custom: 2461 assert(0 && "Cannot promote/custom handle this yet!"); 2462 case TargetLowering::Expand: 2463 switch(Node->getOpcode()) { 2464 case ISD::FNEG: { 2465 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2466 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2467 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0), 2468 Tmp2, Tmp1)); 2469 break; 2470 } 2471 case ISD::FABS: { 2472 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2473 MVT::ValueType VT = Node->getValueType(0); 2474 Tmp2 = DAG.getConstantFP(0.0, VT); 2475 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2476 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2477 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2478 Result = LegalizeOp(Result); 2479 break; 2480 } 2481 case ISD::FSQRT: 2482 case ISD::FSIN: 2483 case ISD::FCOS: { 2484 MVT::ValueType VT = Node->getValueType(0); 2485 const char *FnName = 0; 2486 switch(Node->getOpcode()) { 2487 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 2488 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 2489 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 2490 default: assert(0 && "Unreachable!"); 2491 } 2492 SDOperand Dummy; 2493 Result = ExpandLibCall(FnName, Node, Dummy); 2494 break; 2495 } 2496 default: 2497 assert(0 && "Unreachable!"); 2498 } 2499 break; 2500 } 2501 break; 2502 2503 case ISD::BIT_CONVERT: 2504 if (!isTypeLegal(Node->getOperand(0).getValueType())) 2505 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2506 else { 2507 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2508 Node->getOperand(0).getValueType())) { 2509 default: assert(0 && "Unknown operation action!"); 2510 case TargetLowering::Expand: 2511 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2512 break; 2513 case TargetLowering::Legal: 2514 Tmp1 = LegalizeOp(Node->getOperand(0)); 2515 if (Tmp1 != Node->getOperand(0)) 2516 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Tmp1); 2517 break; 2518 } 2519 } 2520 break; 2521 // Conversion operators. The source and destination have different types. 2522 case ISD::SINT_TO_FP: 2523 case ISD::UINT_TO_FP: { 2524 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2525 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2526 case Legal: 2527 switch (TLI.getOperationAction(Node->getOpcode(), 2528 Node->getOperand(0).getValueType())) { 2529 default: assert(0 && "Unknown operation action!"); 2530 case TargetLowering::Expand: 2531 Result = ExpandLegalINT_TO_FP(isSigned, 2532 LegalizeOp(Node->getOperand(0)), 2533 Node->getValueType(0)); 2534 AddLegalizedOperand(Op, Result); 2535 return Result; 2536 case TargetLowering::Promote: 2537 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2538 Node->getValueType(0), 2539 isSigned); 2540 AddLegalizedOperand(Op, Result); 2541 return Result; 2542 case TargetLowering::Legal: 2543 break; 2544 case TargetLowering::Custom: { 2545 Tmp1 = LegalizeOp(Node->getOperand(0)); 2546 SDOperand Tmp = 2547 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2548 Tmp = TLI.LowerOperation(Tmp, DAG); 2549 if (Tmp.Val) { 2550 Tmp = LegalizeOp(Tmp); // Relegalize input. 2551 AddLegalizedOperand(Op, Tmp); 2552 return Tmp; 2553 } else { 2554 assert(0 && "Target Must Lower this"); 2555 } 2556 } 2557 } 2558 2559 Tmp1 = LegalizeOp(Node->getOperand(0)); 2560 if (Tmp1 != Node->getOperand(0)) 2561 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2562 break; 2563 case Expand: 2564 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2565 Node->getValueType(0), Node->getOperand(0)); 2566 break; 2567 case Promote: 2568 if (isSigned) { 2569 Result = PromoteOp(Node->getOperand(0)); 2570 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2571 Result, DAG.getValueType(Node->getOperand(0).getValueType())); 2572 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 2573 } else { 2574 Result = PromoteOp(Node->getOperand(0)); 2575 Result = DAG.getZeroExtendInReg(Result, 2576 Node->getOperand(0).getValueType()); 2577 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 2578 } 2579 break; 2580 } 2581 break; 2582 } 2583 case ISD::TRUNCATE: 2584 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2585 case Legal: 2586 Tmp1 = LegalizeOp(Node->getOperand(0)); 2587 if (Tmp1 != Node->getOperand(0)) 2588 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2589 break; 2590 case Expand: 2591 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2592 2593 // Since the result is legal, we should just be able to truncate the low 2594 // part of the source. 2595 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2596 break; 2597 case Promote: 2598 Result = PromoteOp(Node->getOperand(0)); 2599 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2600 break; 2601 } 2602 break; 2603 2604 case ISD::FP_TO_SINT: 2605 case ISD::FP_TO_UINT: 2606 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2607 case Legal: 2608 Tmp1 = LegalizeOp(Node->getOperand(0)); 2609 2610 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2611 default: assert(0 && "Unknown operation action!"); 2612 case TargetLowering::Expand: 2613 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2614 SDOperand True, False; 2615 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2616 MVT::ValueType NVT = Node->getValueType(0); 2617 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2618 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2619 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2620 Node->getOperand(0), Tmp2, ISD::SETLT); 2621 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2622 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2623 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2624 Tmp2)); 2625 False = DAG.getNode(ISD::XOR, NVT, False, 2626 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2627 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False)); 2628 AddLegalizedOperand(SDOperand(Node, 0), Result); 2629 return Result; 2630 } else { 2631 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2632 } 2633 break; 2634 case TargetLowering::Promote: 2635 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2636 Node->getOpcode() == ISD::FP_TO_SINT); 2637 AddLegalizedOperand(Op, Result); 2638 return Result; 2639 case TargetLowering::Custom: { 2640 SDOperand Tmp = 2641 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2642 Tmp = TLI.LowerOperation(Tmp, DAG); 2643 if (Tmp.Val) { 2644 Tmp = LegalizeOp(Tmp); 2645 AddLegalizedOperand(Op, Tmp); 2646 return Tmp; 2647 } else { 2648 // The target thinks this is legal afterall. 2649 break; 2650 } 2651 } 2652 case TargetLowering::Legal: 2653 break; 2654 } 2655 2656 if (Tmp1 != Node->getOperand(0)) 2657 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2658 break; 2659 case Expand: 2660 assert(0 && "Shouldn't need to expand other operators here!"); 2661 case Promote: 2662 Result = PromoteOp(Node->getOperand(0)); 2663 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2664 break; 2665 } 2666 break; 2667 2668 case ISD::ANY_EXTEND: 2669 case ISD::ZERO_EXTEND: 2670 case ISD::SIGN_EXTEND: 2671 case ISD::FP_EXTEND: 2672 case ISD::FP_ROUND: 2673 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2674 case Legal: 2675 Tmp1 = LegalizeOp(Node->getOperand(0)); 2676 if (Tmp1 != Node->getOperand(0)) 2677 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2678 break; 2679 case Expand: 2680 assert(0 && "Shouldn't need to expand other operators here!"); 2681 2682 case Promote: 2683 switch (Node->getOpcode()) { 2684 case ISD::ANY_EXTEND: 2685 Result = PromoteOp(Node->getOperand(0)); 2686 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2687 break; 2688 case ISD::ZERO_EXTEND: 2689 Result = PromoteOp(Node->getOperand(0)); 2690 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2691 Result = DAG.getZeroExtendInReg(Result, 2692 Node->getOperand(0).getValueType()); 2693 break; 2694 case ISD::SIGN_EXTEND: 2695 Result = PromoteOp(Node->getOperand(0)); 2696 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2697 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2698 Result, 2699 DAG.getValueType(Node->getOperand(0).getValueType())); 2700 break; 2701 case ISD::FP_EXTEND: 2702 Result = PromoteOp(Node->getOperand(0)); 2703 if (Result.getValueType() != Op.getValueType()) 2704 // Dynamically dead while we have only 2 FP types. 2705 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2706 break; 2707 case ISD::FP_ROUND: 2708 Result = PromoteOp(Node->getOperand(0)); 2709 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2710 break; 2711 } 2712 } 2713 break; 2714 case ISD::FP_ROUND_INREG: 2715 case ISD::SIGN_EXTEND_INREG: { 2716 Tmp1 = LegalizeOp(Node->getOperand(0)); 2717 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2718 2719 // If this operation is not supported, convert it to a shl/shr or load/store 2720 // pair. 2721 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2722 default: assert(0 && "This action not supported for this op yet!"); 2723 case TargetLowering::Legal: 2724 if (Tmp1 != Node->getOperand(0)) 2725 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2726 DAG.getValueType(ExtraVT)); 2727 break; 2728 case TargetLowering::Expand: 2729 // If this is an integer extend and shifts are supported, do that. 2730 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2731 // NOTE: we could fall back on load/store here too for targets without 2732 // SAR. However, it is doubtful that any exist. 2733 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2734 MVT::getSizeInBits(ExtraVT); 2735 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2736 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2737 Node->getOperand(0), ShiftCst); 2738 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2739 Result, ShiftCst); 2740 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2741 // The only way we can lower this is to turn it into a STORETRUNC, 2742 // EXTLOAD pair, targetting a temporary location (a stack slot). 2743 2744 // NOTE: there is a choice here between constantly creating new stack 2745 // slots and always reusing the same one. We currently always create 2746 // new ones, as reuse may inhibit scheduling. 2747 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2748 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2749 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2750 MachineFunction &MF = DAG.getMachineFunction(); 2751 int SSFI = 2752 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2753 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2754 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2755 Node->getOperand(0), StackSlot, 2756 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2757 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2758 Result, StackSlot, DAG.getSrcValue(NULL), 2759 ExtraVT); 2760 } else { 2761 assert(0 && "Unknown op"); 2762 } 2763 Result = LegalizeOp(Result); 2764 break; 2765 } 2766 break; 2767 } 2768 } 2769 2770 // Note that LegalizeOp may be reentered even from single-use nodes, which 2771 // means that we always must cache transformed nodes. 2772 AddLegalizedOperand(Op, Result); 2773 return Result; 2774} 2775 2776/// PromoteOp - Given an operation that produces a value in an invalid type, 2777/// promote it to compute the value into a larger type. The produced value will 2778/// have the correct bits for the low portion of the register, but no guarantee 2779/// is made about the top bits: it may be zero, sign-extended, or garbage. 2780SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2781 MVT::ValueType VT = Op.getValueType(); 2782 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2783 assert(getTypeAction(VT) == Promote && 2784 "Caller should expand or legalize operands that are not promotable!"); 2785 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2786 "Cannot promote to smaller type!"); 2787 2788 SDOperand Tmp1, Tmp2, Tmp3; 2789 2790 SDOperand Result; 2791 SDNode *Node = Op.Val; 2792 2793 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2794 if (I != PromotedNodes.end()) return I->second; 2795 2796 // Promotion needs an optimization step to clean up after it, and is not 2797 // careful to avoid operations the target does not support. Make sure that 2798 // all generated operations are legalized in the next iteration. 2799 NeedsAnotherIteration = true; 2800 2801 switch (Node->getOpcode()) { 2802 case ISD::CopyFromReg: 2803 assert(0 && "CopyFromReg must be legal!"); 2804 default: 2805 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2806 assert(0 && "Do not know how to promote this operator!"); 2807 abort(); 2808 case ISD::UNDEF: 2809 Result = DAG.getNode(ISD::UNDEF, NVT); 2810 break; 2811 case ISD::Constant: 2812 if (VT != MVT::i1) 2813 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2814 else 2815 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2816 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2817 break; 2818 case ISD::ConstantFP: 2819 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2820 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2821 break; 2822 2823 case ISD::SETCC: 2824 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2825 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2826 Node->getOperand(1), Node->getOperand(2)); 2827 Result = LegalizeOp(Result); 2828 break; 2829 2830 case ISD::TRUNCATE: 2831 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2832 case Legal: 2833 Result = LegalizeOp(Node->getOperand(0)); 2834 assert(Result.getValueType() >= NVT && 2835 "This truncation doesn't make sense!"); 2836 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2837 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2838 break; 2839 case Promote: 2840 // The truncation is not required, because we don't guarantee anything 2841 // about high bits anyway. 2842 Result = PromoteOp(Node->getOperand(0)); 2843 break; 2844 case Expand: 2845 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2846 // Truncate the low part of the expanded value to the result type 2847 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2848 } 2849 break; 2850 case ISD::SIGN_EXTEND: 2851 case ISD::ZERO_EXTEND: 2852 case ISD::ANY_EXTEND: 2853 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2854 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2855 case Legal: 2856 // Input is legal? Just do extend all the way to the larger type. 2857 Result = LegalizeOp(Node->getOperand(0)); 2858 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2859 break; 2860 case Promote: 2861 // Promote the reg if it's smaller. 2862 Result = PromoteOp(Node->getOperand(0)); 2863 // The high bits are not guaranteed to be anything. Insert an extend. 2864 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2865 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2866 DAG.getValueType(Node->getOperand(0).getValueType())); 2867 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2868 Result = DAG.getZeroExtendInReg(Result, 2869 Node->getOperand(0).getValueType()); 2870 break; 2871 } 2872 break; 2873 case ISD::BIT_CONVERT: 2874 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2875 Result = PromoteOp(Result); 2876 break; 2877 2878 case ISD::FP_EXTEND: 2879 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2880 case ISD::FP_ROUND: 2881 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2882 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2883 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2884 case Legal: 2885 // Input is legal? Do an FP_ROUND_INREG. 2886 Result = LegalizeOp(Node->getOperand(0)); 2887 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2888 DAG.getValueType(VT)); 2889 break; 2890 } 2891 break; 2892 2893 case ISD::SINT_TO_FP: 2894 case ISD::UINT_TO_FP: 2895 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2896 case Legal: 2897 Result = LegalizeOp(Node->getOperand(0)); 2898 // No extra round required here. 2899 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2900 break; 2901 2902 case Promote: 2903 Result = PromoteOp(Node->getOperand(0)); 2904 if (Node->getOpcode() == ISD::SINT_TO_FP) 2905 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2906 Result, 2907 DAG.getValueType(Node->getOperand(0).getValueType())); 2908 else 2909 Result = DAG.getZeroExtendInReg(Result, 2910 Node->getOperand(0).getValueType()); 2911 // No extra round required here. 2912 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2913 break; 2914 case Expand: 2915 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2916 Node->getOperand(0)); 2917 // Round if we cannot tolerate excess precision. 2918 if (NoExcessFPPrecision) 2919 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2920 DAG.getValueType(VT)); 2921 break; 2922 } 2923 break; 2924 2925 case ISD::SIGN_EXTEND_INREG: 2926 Result = PromoteOp(Node->getOperand(0)); 2927 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2928 Node->getOperand(1)); 2929 break; 2930 case ISD::FP_TO_SINT: 2931 case ISD::FP_TO_UINT: 2932 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2933 case Legal: 2934 Tmp1 = LegalizeOp(Node->getOperand(0)); 2935 break; 2936 case Promote: 2937 // The input result is prerounded, so we don't have to do anything 2938 // special. 2939 Tmp1 = PromoteOp(Node->getOperand(0)); 2940 break; 2941 case Expand: 2942 assert(0 && "not implemented"); 2943 } 2944 // If we're promoting a UINT to a larger size, check to see if the new node 2945 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2946 // we can use that instead. This allows us to generate better code for 2947 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2948 // legal, such as PowerPC. 2949 if (Node->getOpcode() == ISD::FP_TO_UINT && 2950 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2951 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2952 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2953 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2954 } else { 2955 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2956 } 2957 break; 2958 2959 case ISD::FABS: 2960 case ISD::FNEG: 2961 Tmp1 = PromoteOp(Node->getOperand(0)); 2962 assert(Tmp1.getValueType() == NVT); 2963 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2964 // NOTE: we do not have to do any extra rounding here for 2965 // NoExcessFPPrecision, because we know the input will have the appropriate 2966 // precision, and these operations don't modify precision at all. 2967 break; 2968 2969 case ISD::FSQRT: 2970 case ISD::FSIN: 2971 case ISD::FCOS: 2972 Tmp1 = PromoteOp(Node->getOperand(0)); 2973 assert(Tmp1.getValueType() == NVT); 2974 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2975 if(NoExcessFPPrecision) 2976 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2977 DAG.getValueType(VT)); 2978 break; 2979 2980 case ISD::AND: 2981 case ISD::OR: 2982 case ISD::XOR: 2983 case ISD::ADD: 2984 case ISD::SUB: 2985 case ISD::MUL: 2986 // The input may have strange things in the top bits of the registers, but 2987 // these operations don't care. They may have weird bits going out, but 2988 // that too is okay if they are integer operations. 2989 Tmp1 = PromoteOp(Node->getOperand(0)); 2990 Tmp2 = PromoteOp(Node->getOperand(1)); 2991 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2992 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2993 break; 2994 case ISD::FADD: 2995 case ISD::FSUB: 2996 case ISD::FMUL: 2997 // The input may have strange things in the top bits of the registers, but 2998 // these operations don't care. 2999 Tmp1 = PromoteOp(Node->getOperand(0)); 3000 Tmp2 = PromoteOp(Node->getOperand(1)); 3001 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3002 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3003 3004 // Floating point operations will give excess precision that we may not be 3005 // able to tolerate. If we DO allow excess precision, just leave it, 3006 // otherwise excise it. 3007 // FIXME: Why would we need to round FP ops more than integer ones? 3008 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3009 if (NoExcessFPPrecision) 3010 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3011 DAG.getValueType(VT)); 3012 break; 3013 3014 case ISD::SDIV: 3015 case ISD::SREM: 3016 // These operators require that their input be sign extended. 3017 Tmp1 = PromoteOp(Node->getOperand(0)); 3018 Tmp2 = PromoteOp(Node->getOperand(1)); 3019 if (MVT::isInteger(NVT)) { 3020 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3021 DAG.getValueType(VT)); 3022 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3023 DAG.getValueType(VT)); 3024 } 3025 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3026 3027 // Perform FP_ROUND: this is probably overly pessimistic. 3028 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3029 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3030 DAG.getValueType(VT)); 3031 break; 3032 case ISD::FDIV: 3033 case ISD::FREM: 3034 // These operators require that their input be fp extended. 3035 Tmp1 = PromoteOp(Node->getOperand(0)); 3036 Tmp2 = PromoteOp(Node->getOperand(1)); 3037 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3038 3039 // Perform FP_ROUND: this is probably overly pessimistic. 3040 if (NoExcessFPPrecision) 3041 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3042 DAG.getValueType(VT)); 3043 break; 3044 3045 case ISD::UDIV: 3046 case ISD::UREM: 3047 // These operators require that their input be zero extended. 3048 Tmp1 = PromoteOp(Node->getOperand(0)); 3049 Tmp2 = PromoteOp(Node->getOperand(1)); 3050 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3051 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3052 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3053 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3054 break; 3055 3056 case ISD::SHL: 3057 Tmp1 = PromoteOp(Node->getOperand(0)); 3058 Tmp2 = LegalizeOp(Node->getOperand(1)); 3059 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 3060 break; 3061 case ISD::SRA: 3062 // The input value must be properly sign extended. 3063 Tmp1 = PromoteOp(Node->getOperand(0)); 3064 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3065 DAG.getValueType(VT)); 3066 Tmp2 = LegalizeOp(Node->getOperand(1)); 3067 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 3068 break; 3069 case ISD::SRL: 3070 // The input value must be properly zero extended. 3071 Tmp1 = PromoteOp(Node->getOperand(0)); 3072 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3073 Tmp2 = LegalizeOp(Node->getOperand(1)); 3074 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 3075 break; 3076 3077 case ISD::LOAD: 3078 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3079 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3080 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2, 3081 Node->getOperand(2), VT); 3082 // Remember that we legalized the chain. 3083 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 3084 break; 3085 case ISD::SEXTLOAD: 3086 case ISD::ZEXTLOAD: 3087 case ISD::EXTLOAD: 3088 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3089 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3090 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2, 3091 Node->getOperand(2), 3092 cast<VTSDNode>(Node->getOperand(3))->getVT()); 3093 // Remember that we legalized the chain. 3094 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 3095 break; 3096 case ISD::SELECT: 3097 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3098 case Expand: assert(0 && "It's impossible to expand bools"); 3099 case Legal: 3100 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 3101 break; 3102 case Promote: 3103 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 3104 break; 3105 } 3106 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 3107 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 3108 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 3109 break; 3110 case ISD::SELECT_CC: 3111 Tmp2 = PromoteOp(Node->getOperand(2)); // True 3112 Tmp3 = PromoteOp(Node->getOperand(3)); // False 3113 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3114 Node->getOperand(1), Tmp2, Tmp3, 3115 Node->getOperand(4)); 3116 break; 3117 case ISD::TAILCALL: 3118 case ISD::CALL: { 3119 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3120 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 3121 3122 std::vector<SDOperand> Ops; 3123 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 3124 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3125 3126 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 3127 "Can only promote single result calls"); 3128 std::vector<MVT::ValueType> RetTyVTs; 3129 RetTyVTs.reserve(2); 3130 RetTyVTs.push_back(NVT); 3131 RetTyVTs.push_back(MVT::Other); 3132 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 3133 Node->getOpcode() == ISD::TAILCALL); 3134 Result = SDOperand(NC, 0); 3135 3136 // Insert the new chain mapping. 3137 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 3138 break; 3139 } 3140 case ISD::BSWAP: 3141 Tmp1 = Node->getOperand(0); 3142 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3143 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3144 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3145 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), 3146 TLI.getShiftAmountTy())); 3147 break; 3148 case ISD::CTPOP: 3149 case ISD::CTTZ: 3150 case ISD::CTLZ: 3151 Tmp1 = Node->getOperand(0); 3152 //Zero extend the argument 3153 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3154 // Perform the larger operation, then subtract if needed. 3155 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3156 switch(Node->getOpcode()) 3157 { 3158 case ISD::CTPOP: 3159 Result = Tmp1; 3160 break; 3161 case ISD::CTTZ: 3162 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3163 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3164 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 3165 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3166 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 3167 break; 3168 case ISD::CTLZ: 3169 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3170 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3171 DAG.getConstant(getSizeInBits(NVT) - 3172 getSizeInBits(VT), NVT)); 3173 break; 3174 } 3175 break; 3176 } 3177 3178 assert(Result.Val && "Didn't set a result!"); 3179 AddPromotedOperand(Op, Result); 3180 return Result; 3181} 3182 3183/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 3184/// The resultant code need not be legal. Note that SrcOp is the input operand 3185/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 3186SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 3187 SDOperand SrcOp) { 3188 // Create the stack frame object. 3189 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 3190 unsigned ByteSize = MVT::getSizeInBits(DestVT)/8; 3191 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize); 3192 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 3193 3194 // Emit a store to the stack slot. 3195 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3196 SrcOp, FIPtr, DAG.getSrcValue(NULL)); 3197 // Result is a load from the stack slot. 3198 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0)); 3199} 3200 3201/// ExpandAddSub - Find a clever way to expand this add operation into 3202/// subcomponents. 3203void SelectionDAGLegalize:: 3204ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 3205 SDOperand &Lo, SDOperand &Hi) { 3206 // Expand the subcomponents. 3207 SDOperand LHSL, LHSH, RHSL, RHSH; 3208 ExpandOp(LHS, LHSL, LHSH); 3209 ExpandOp(RHS, RHSL, RHSH); 3210 3211 std::vector<SDOperand> Ops; 3212 Ops.push_back(LHSL); 3213 Ops.push_back(LHSH); 3214 Ops.push_back(RHSL); 3215 Ops.push_back(RHSH); 3216 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 3217 Lo = DAG.getNode(NodeOp, VTs, Ops); 3218 Hi = Lo.getValue(1); 3219} 3220 3221void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 3222 SDOperand Op, SDOperand Amt, 3223 SDOperand &Lo, SDOperand &Hi) { 3224 // Expand the subcomponents. 3225 SDOperand LHSL, LHSH; 3226 ExpandOp(Op, LHSL, LHSH); 3227 3228 std::vector<SDOperand> Ops; 3229 Ops.push_back(LHSL); 3230 Ops.push_back(LHSH); 3231 Ops.push_back(Amt); 3232 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 3233 Lo = DAG.getNode(NodeOp, VTs, Ops); 3234 Hi = Lo.getValue(1); 3235} 3236 3237 3238/// ExpandShift - Try to find a clever way to expand this shift operation out to 3239/// smaller elements. If we can't find a way that is more efficient than a 3240/// libcall on this target, return false. Otherwise, return true with the 3241/// low-parts expanded into Lo and Hi. 3242bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 3243 SDOperand &Lo, SDOperand &Hi) { 3244 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 3245 "This is not a shift!"); 3246 3247 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 3248 SDOperand ShAmt = LegalizeOp(Amt); 3249 MVT::ValueType ShTy = ShAmt.getValueType(); 3250 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 3251 unsigned NVTBits = MVT::getSizeInBits(NVT); 3252 3253 // Handle the case when Amt is an immediate. Other cases are currently broken 3254 // and are disabled. 3255 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 3256 unsigned Cst = CN->getValue(); 3257 // Expand the incoming operand to be shifted, so that we have its parts 3258 SDOperand InL, InH; 3259 ExpandOp(Op, InL, InH); 3260 switch(Opc) { 3261 case ISD::SHL: 3262 if (Cst > VTBits) { 3263 Lo = DAG.getConstant(0, NVT); 3264 Hi = DAG.getConstant(0, NVT); 3265 } else if (Cst > NVTBits) { 3266 Lo = DAG.getConstant(0, NVT); 3267 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 3268 } else if (Cst == NVTBits) { 3269 Lo = DAG.getConstant(0, NVT); 3270 Hi = InL; 3271 } else { 3272 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 3273 Hi = DAG.getNode(ISD::OR, NVT, 3274 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 3275 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 3276 } 3277 return true; 3278 case ISD::SRL: 3279 if (Cst > VTBits) { 3280 Lo = DAG.getConstant(0, NVT); 3281 Hi = DAG.getConstant(0, NVT); 3282 } else if (Cst > NVTBits) { 3283 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 3284 Hi = DAG.getConstant(0, NVT); 3285 } else if (Cst == NVTBits) { 3286 Lo = InH; 3287 Hi = DAG.getConstant(0, NVT); 3288 } else { 3289 Lo = DAG.getNode(ISD::OR, NVT, 3290 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3291 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3292 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 3293 } 3294 return true; 3295 case ISD::SRA: 3296 if (Cst > VTBits) { 3297 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 3298 DAG.getConstant(NVTBits-1, ShTy)); 3299 } else if (Cst > NVTBits) { 3300 Lo = DAG.getNode(ISD::SRA, NVT, InH, 3301 DAG.getConstant(Cst-NVTBits, ShTy)); 3302 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3303 DAG.getConstant(NVTBits-1, ShTy)); 3304 } else if (Cst == NVTBits) { 3305 Lo = InH; 3306 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3307 DAG.getConstant(NVTBits-1, ShTy)); 3308 } else { 3309 Lo = DAG.getNode(ISD::OR, NVT, 3310 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3311 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3312 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 3313 } 3314 return true; 3315 } 3316 } 3317 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 3318 // so disable it for now. Currently targets are handling this via SHL_PARTS 3319 // and friends. 3320 return false; 3321 3322 // If we have an efficient select operation (or if the selects will all fold 3323 // away), lower to some complex code, otherwise just emit the libcall. 3324 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt)) 3325 return false; 3326 3327 SDOperand InL, InH; 3328 ExpandOp(Op, InL, InH); 3329 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 3330 DAG.getConstant(NVTBits, ShTy), ShAmt); 3331 3332 // Compare the unmasked shift amount against 32. 3333 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt, 3334 DAG.getConstant(NVTBits, ShTy), ISD::SETGE); 3335 3336 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 3337 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 3338 DAG.getConstant(NVTBits-1, ShTy)); 3339 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 3340 DAG.getConstant(NVTBits-1, ShTy)); 3341 } 3342 3343 if (Opc == ISD::SHL) { 3344 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 3345 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 3346 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 3347 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 3348 3349 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 3350 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 3351 } else { 3352 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 3353 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt, 3354 DAG.getConstant(32, ShTy), 3355 ISD::SETEQ), 3356 DAG.getConstant(0, NVT), 3357 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 3358 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 3359 HiLoPart, 3360 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 3361 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 3362 3363 SDOperand HiPart; 3364 if (Opc == ISD::SRA) 3365 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 3366 DAG.getConstant(NVTBits-1, ShTy)); 3367 else 3368 HiPart = DAG.getConstant(0, NVT); 3369 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 3370 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 3371 } 3372 return true; 3373} 3374 3375/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 3376/// NodeDepth) node that is an CallSeqStart operation and occurs later than 3377/// Found. 3378static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found, 3379 std::set<SDNode*> &Visited) { 3380 if (Node->getNodeDepth() <= Found->getNodeDepth() || 3381 !Visited.insert(Node).second) return; 3382 3383 // If we found an CALLSEQ_START, we already know this node occurs later 3384 // than the Found node. Just remember this node and return. 3385 if (Node->getOpcode() == ISD::CALLSEQ_START) { 3386 Found = Node; 3387 return; 3388 } 3389 3390 // Otherwise, scan the operands of Node to see if any of them is a call. 3391 assert(Node->getNumOperands() != 0 && 3392 "All leaves should have depth equal to the entry node!"); 3393 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 3394 FindLatestCallSeqStart(Node->getOperand(i).Val, Found, Visited); 3395 3396 // Tail recurse for the last iteration. 3397 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 3398 Found, Visited); 3399} 3400 3401 3402/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 3403/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 3404/// than Found. 3405static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 3406 std::set<SDNode*> &Visited) { 3407 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 3408 !Visited.insert(Node).second) return; 3409 3410 // If we found an CALLSEQ_END, we already know this node occurs earlier 3411 // than the Found node. Just remember this node and return. 3412 if (Node->getOpcode() == ISD::CALLSEQ_END) { 3413 Found = Node; 3414 return; 3415 } 3416 3417 // Otherwise, scan the operands of Node to see if any of them is a call. 3418 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 3419 if (UI == E) return; 3420 for (--E; UI != E; ++UI) 3421 FindEarliestCallSeqEnd(*UI, Found, Visited); 3422 3423 // Tail recurse for the last iteration. 3424 FindEarliestCallSeqEnd(*UI, Found, Visited); 3425} 3426 3427/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 3428/// find the CALLSEQ_END node that terminates the call sequence. 3429static SDNode *FindCallSeqEnd(SDNode *Node) { 3430 if (Node->getOpcode() == ISD::CALLSEQ_END) 3431 return Node; 3432 if (Node->use_empty()) 3433 return 0; // No CallSeqEnd 3434 3435 // The chain is usually at the end. 3436 SDOperand TheChain(Node, Node->getNumValues()-1); 3437 if (TheChain.getValueType() != MVT::Other) { 3438 // Sometimes it's at the beginning. 3439 TheChain = SDOperand(Node, 0); 3440 if (TheChain.getValueType() != MVT::Other) { 3441 // Otherwise, hunt for it. 3442 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 3443 if (Node->getValueType(i) == MVT::Other) { 3444 TheChain = SDOperand(Node, i); 3445 break; 3446 } 3447 3448 // Otherwise, we walked into a node without a chain. 3449 if (TheChain.getValueType() != MVT::Other) 3450 return 0; 3451 } 3452 } 3453 3454 for (SDNode::use_iterator UI = Node->use_begin(), 3455 E = Node->use_end(); UI != E; ++UI) { 3456 3457 // Make sure to only follow users of our token chain. 3458 SDNode *User = *UI; 3459 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 3460 if (User->getOperand(i) == TheChain) 3461 if (SDNode *Result = FindCallSeqEnd(User)) 3462 return Result; 3463 } 3464 return 0; 3465} 3466 3467/// FindCallSeqStart - Given a chained node that is part of a call sequence, 3468/// find the CALLSEQ_START node that initiates the call sequence. 3469static SDNode *FindCallSeqStart(SDNode *Node) { 3470 assert(Node && "Didn't find callseq_start for a call??"); 3471 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 3472 3473 assert(Node->getOperand(0).getValueType() == MVT::Other && 3474 "Node doesn't have a token chain argument!"); 3475 return FindCallSeqStart(Node->getOperand(0).Val); 3476} 3477 3478 3479/// FindInputOutputChains - If we are replacing an operation with a call we need 3480/// to find the call that occurs before and the call that occurs after it to 3481/// properly serialize the calls in the block. The returned operand is the 3482/// input chain value for the new call (e.g. the entry node or the previous 3483/// call), and OutChain is set to be the chain node to update to point to the 3484/// end of the call chain. 3485static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 3486 SDOperand Entry) { 3487 SDNode *LatestCallSeqStart = Entry.Val; 3488 SDNode *LatestCallSeqEnd = 0; 3489 std::set<SDNode*> Visited; 3490 FindLatestCallSeqStart(OpNode, LatestCallSeqStart, Visited); 3491 Visited.clear(); 3492 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 3493 3494 // It is possible that no ISD::CALLSEQ_START was found because there is no 3495 // previous call in the function. LatestCallStackDown may in that case be 3496 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 3497 // unless LatestCallStackDown is an CALLSEQ_START. 3498 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 3499 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 3500 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 3501 } else { 3502 LatestCallSeqEnd = Entry.Val; 3503 } 3504 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 3505 3506 // Finally, find the first call that this must come before, first we find the 3507 // CallSeqEnd that ends the call. 3508 OutChain = 0; 3509 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 3510 Visited.clear(); 3511 3512 // If we found one, translate from the adj up to the callseq_start. 3513 if (OutChain) 3514 OutChain = FindCallSeqStart(OutChain); 3515 3516 return SDOperand(LatestCallSeqEnd, 0); 3517} 3518 3519/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 3520void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 3521 SDNode *OutChain) { 3522 // Nothing to splice it into? 3523 if (OutChain == 0) return; 3524 3525 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 3526 //OutChain->dump(); 3527 3528 // Form a token factor node merging the old inval and the new inval. 3529 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 3530 OutChain->getOperand(0)); 3531 // Change the node to refer to the new token. 3532 OutChain->setAdjCallChain(InToken); 3533} 3534 3535 3536// ExpandLibCall - Expand a node into a call to a libcall. If the result value 3537// does not fit into a register, return the lo part and set the hi part to the 3538// by-reg argument. If it does fit into a single register, return the result 3539// and leave the Hi part unset. 3540SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 3541 SDOperand &Hi) { 3542 SDNode *OutChain; 3543 SDOperand InChain = FindInputOutputChains(Node, OutChain, 3544 DAG.getEntryNode()); 3545 if (InChain.Val == 0) 3546 InChain = DAG.getEntryNode(); 3547 3548 TargetLowering::ArgListTy Args; 3549 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3550 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 3551 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 3552 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 3553 } 3554 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 3555 3556 // Splice the libcall in wherever FindInputOutputChains tells us to. 3557 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 3558 std::pair<SDOperand,SDOperand> CallInfo = 3559 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 3560 Callee, Args, DAG); 3561 3562 SDOperand Result; 3563 switch (getTypeAction(CallInfo.first.getValueType())) { 3564 default: assert(0 && "Unknown thing"); 3565 case Legal: 3566 Result = CallInfo.first; 3567 break; 3568 case Promote: 3569 assert(0 && "Cannot promote this yet!"); 3570 case Expand: 3571 ExpandOp(CallInfo.first, Result, Hi); 3572 CallInfo.second = LegalizeOp(CallInfo.second); 3573 break; 3574 } 3575 3576 SpliceCallInto(CallInfo.second, OutChain); 3577 NeedsAnotherIteration = true; 3578 return Result; 3579} 3580 3581 3582/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 3583/// destination type is legal. 3584SDOperand SelectionDAGLegalize:: 3585ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 3586 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 3587 assert(getTypeAction(Source.getValueType()) == Expand && 3588 "This is not an expansion!"); 3589 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 3590 3591 if (!isSigned) { 3592 assert(Source.getValueType() == MVT::i64 && 3593 "This only works for 64-bit -> FP"); 3594 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 3595 // incoming integer is set. To handle this, we dynamically test to see if 3596 // it is set, and, if so, add a fudge factor. 3597 SDOperand Lo, Hi; 3598 ExpandOp(Source, Lo, Hi); 3599 3600 // If this is unsigned, and not supported, first perform the conversion to 3601 // signed, then adjust the result if the sign bit is set. 3602 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 3603 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 3604 3605 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 3606 DAG.getConstant(0, Hi.getValueType()), 3607 ISD::SETLT); 3608 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3609 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3610 SignSet, Four, Zero); 3611 uint64_t FF = 0x5f800000ULL; 3612 if (TLI.isLittleEndian()) FF <<= 32; 3613 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3614 3615 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3616 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3617 SDOperand FudgeInReg; 3618 if (DestTy == MVT::f32) 3619 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3620 DAG.getSrcValue(NULL)); 3621 else { 3622 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3623 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3624 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 3625 } 3626 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3627 } 3628 3629 // Check to see if the target has a custom way to lower this. If so, use it. 3630 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3631 default: assert(0 && "This action not implemented for this operation!"); 3632 case TargetLowering::Legal: 3633 case TargetLowering::Expand: 3634 break; // This case is handled below. 3635 case TargetLowering::Custom: { 3636 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3637 Source), DAG); 3638 if (NV.Val) 3639 return LegalizeOp(NV); 3640 break; // The target decided this was legal after all 3641 } 3642 } 3643 3644 // Expand the source, then glue it back together for the call. We must expand 3645 // the source in case it is shared (this pass of legalize must traverse it). 3646 SDOperand SrcLo, SrcHi; 3647 ExpandOp(Source, SrcLo, SrcHi); 3648 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3649 3650 SDNode *OutChain = 0; 3651 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 3652 DAG.getEntryNode()); 3653 const char *FnName = 0; 3654 if (DestTy == MVT::f32) 3655 FnName = "__floatdisf"; 3656 else { 3657 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3658 FnName = "__floatdidf"; 3659 } 3660 3661 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 3662 3663 TargetLowering::ArgListTy Args; 3664 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 3665 3666 Args.push_back(std::make_pair(Source, ArgTy)); 3667 3668 // We don't care about token chains for libcalls. We just use the entry 3669 // node as our input and ignore the output chain. This allows us to place 3670 // calls wherever we need them to satisfy data dependences. 3671 const Type *RetTy = MVT::getTypeForValueType(DestTy); 3672 3673 std::pair<SDOperand,SDOperand> CallResult = 3674 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 3675 Callee, Args, DAG); 3676 3677 SpliceCallInto(CallResult.second, OutChain); 3678 return CallResult.first; 3679} 3680 3681 3682 3683/// ExpandOp - Expand the specified SDOperand into its two component pieces 3684/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 3685/// LegalizeNodes map is filled in for any results that are not expanded, the 3686/// ExpandedNodes map is filled in for any results that are expanded, and the 3687/// Lo/Hi values are returned. 3688void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 3689 MVT::ValueType VT = Op.getValueType(); 3690 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3691 SDNode *Node = Op.Val; 3692 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 3693 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 3694 "Cannot expand FP values!"); 3695 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 3696 "Cannot expand to FP value or to larger int value!"); 3697 3698 // See if we already expanded it. 3699 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 3700 = ExpandedNodes.find(Op); 3701 if (I != ExpandedNodes.end()) { 3702 Lo = I->second.first; 3703 Hi = I->second.second; 3704 return; 3705 } 3706 3707 // Expanding to multiple registers needs to perform an optimization step, and 3708 // is not careful to avoid operations the target does not support. Make sure 3709 // that all generated operations are legalized in the next iteration. 3710 NeedsAnotherIteration = true; 3711 3712 switch (Node->getOpcode()) { 3713 case ISD::CopyFromReg: 3714 assert(0 && "CopyFromReg must be legal!"); 3715 default: 3716 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 3717 assert(0 && "Do not know how to expand this operator!"); 3718 abort(); 3719 case ISD::UNDEF: 3720 Lo = DAG.getNode(ISD::UNDEF, NVT); 3721 Hi = DAG.getNode(ISD::UNDEF, NVT); 3722 break; 3723 case ISD::Constant: { 3724 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 3725 Lo = DAG.getConstant(Cst, NVT); 3726 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3727 break; 3728 } 3729 case ISD::ConstantVec: { 3730 unsigned NumElements = Node->getNumOperands(); 3731 // If we only have two elements left in the constant vector, just break it 3732 // apart into the two scalar constants it contains. Otherwise, bisect the 3733 // ConstantVec, and return each half as a new ConstantVec. 3734 // FIXME: this is hard coded as big endian, it may have to change to support 3735 // SSE and Alpha MVI 3736 if (NumElements == 2) { 3737 Hi = Node->getOperand(0); 3738 Lo = Node->getOperand(1); 3739 } else { 3740 NumElements /= 2; 3741 std::vector<SDOperand> LoOps, HiOps; 3742 for (unsigned I = 0, E = NumElements; I < E; ++I) { 3743 HiOps.push_back(Node->getOperand(I)); 3744 LoOps.push_back(Node->getOperand(I+NumElements)); 3745 } 3746 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps); 3747 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps); 3748 } 3749 break; 3750 } 3751 3752 case ISD::BUILD_PAIR: 3753 // Legalize both operands. FIXME: in the future we should handle the case 3754 // where the two elements are not legal. 3755 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 3756 Lo = LegalizeOp(Node->getOperand(0)); 3757 Hi = LegalizeOp(Node->getOperand(1)); 3758 break; 3759 3760 case ISD::SIGN_EXTEND_INREG: 3761 ExpandOp(Node->getOperand(0), Lo, Hi); 3762 // Sign extend the lo-part. 3763 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 3764 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 3765 TLI.getShiftAmountTy())); 3766 // sext_inreg the low part if needed. 3767 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 3768 break; 3769 3770 case ISD::BSWAP: { 3771 ExpandOp(Node->getOperand(0), Lo, Hi); 3772 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 3773 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 3774 Lo = TempLo; 3775 break; 3776 } 3777 3778 case ISD::CTPOP: 3779 ExpandOp(Node->getOperand(0), Lo, Hi); 3780 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3781 DAG.getNode(ISD::CTPOP, NVT, Lo), 3782 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3783 Hi = DAG.getConstant(0, NVT); 3784 break; 3785 3786 case ISD::CTLZ: { 3787 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3788 ExpandOp(Node->getOperand(0), Lo, Hi); 3789 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3790 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3791 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3792 ISD::SETNE); 3793 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3794 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3795 3796 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3797 Hi = DAG.getConstant(0, NVT); 3798 break; 3799 } 3800 3801 case ISD::CTTZ: { 3802 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3803 ExpandOp(Node->getOperand(0), Lo, Hi); 3804 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3805 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3806 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3807 ISD::SETNE); 3808 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3809 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3810 3811 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3812 Hi = DAG.getConstant(0, NVT); 3813 break; 3814 } 3815 3816 case ISD::LOAD: { 3817 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3818 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3819 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3820 3821 // Increment the pointer to the other half. 3822 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3823 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3824 getIntPtrConstant(IncrementSize)); 3825 //Is this safe? declaring that the two parts of the split load 3826 //are from the same instruction? 3827 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3828 3829 // Build a factor node to remember that this load is independent of the 3830 // other one. 3831 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3832 Hi.getValue(1)); 3833 3834 // Remember that we legalized the chain. 3835 AddLegalizedOperand(Op.getValue(1), TF); 3836 if (!TLI.isLittleEndian()) 3837 std::swap(Lo, Hi); 3838 break; 3839 } 3840 case ISD::VLOAD: { 3841 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3842 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3843 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3844 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3845 3846 // If we only have two elements, turn into a pair of scalar loads. 3847 // FIXME: handle case where a vector of two elements is fine, such as 3848 // 2 x double on SSE2. 3849 if (NumElements == 2) { 3850 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3851 // Increment the pointer to the other half. 3852 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8; 3853 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3854 getIntPtrConstant(IncrementSize)); 3855 //Is this safe? declaring that the two parts of the split load 3856 //are from the same instruction? 3857 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3858 } else { 3859 NumElements /= 2; // Split the vector in half 3860 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3861 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8; 3862 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3863 getIntPtrConstant(IncrementSize)); 3864 //Is this safe? declaring that the two parts of the split load 3865 //are from the same instruction? 3866 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3867 } 3868 3869 // Build a factor node to remember that this load is independent of the 3870 // other one. 3871 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3872 Hi.getValue(1)); 3873 3874 // Remember that we legalized the chain. 3875 AddLegalizedOperand(Op.getValue(1), TF); 3876 if (!TLI.isLittleEndian()) 3877 std::swap(Lo, Hi); 3878 break; 3879 } 3880 case ISD::VADD: 3881 case ISD::VSUB: 3882 case ISD::VMUL: { 3883 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3884 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3885 SDOperand LL, LH, RL, RH; 3886 3887 ExpandOp(Node->getOperand(0), LL, LH); 3888 ExpandOp(Node->getOperand(1), RL, RH); 3889 3890 // If we only have two elements, turn into a pair of scalar loads. 3891 // FIXME: handle case where a vector of two elements is fine, such as 3892 // 2 x double on SSE2. 3893 if (NumElements == 2) { 3894 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT); 3895 Lo = DAG.getNode(Opc, EVT, LL, RL); 3896 Hi = DAG.getNode(Opc, EVT, LH, RH); 3897 } else { 3898 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2), 3899 LL.getOperand(3)); 3900 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2), 3901 LH.getOperand(3)); 3902 } 3903 break; 3904 } 3905 case ISD::TAILCALL: 3906 case ISD::CALL: { 3907 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3908 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 3909 3910 bool Changed = false; 3911 std::vector<SDOperand> Ops; 3912 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 3913 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3914 Changed |= Ops.back() != Node->getOperand(i); 3915 } 3916 3917 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 3918 "Can only expand a call once so far, not i64 -> i16!"); 3919 3920 std::vector<MVT::ValueType> RetTyVTs; 3921 RetTyVTs.reserve(3); 3922 RetTyVTs.push_back(NVT); 3923 RetTyVTs.push_back(NVT); 3924 RetTyVTs.push_back(MVT::Other); 3925 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops, 3926 Node->getOpcode() == ISD::TAILCALL); 3927 Lo = SDOperand(NC, 0); 3928 Hi = SDOperand(NC, 1); 3929 3930 // Insert the new chain mapping. 3931 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 3932 break; 3933 } 3934 case ISD::AND: 3935 case ISD::OR: 3936 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 3937 SDOperand LL, LH, RL, RH; 3938 ExpandOp(Node->getOperand(0), LL, LH); 3939 ExpandOp(Node->getOperand(1), RL, RH); 3940 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 3941 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 3942 break; 3943 } 3944 case ISD::SELECT: { 3945 SDOperand C, LL, LH, RL, RH; 3946 3947 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3948 case Expand: assert(0 && "It's impossible to expand bools"); 3949 case Legal: 3950 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 3951 break; 3952 case Promote: 3953 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 3954 break; 3955 } 3956 ExpandOp(Node->getOperand(1), LL, LH); 3957 ExpandOp(Node->getOperand(2), RL, RH); 3958 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 3959 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 3960 break; 3961 } 3962 case ISD::SELECT_CC: { 3963 SDOperand TL, TH, FL, FH; 3964 ExpandOp(Node->getOperand(2), TL, TH); 3965 ExpandOp(Node->getOperand(3), FL, FH); 3966 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3967 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3968 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3969 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3970 Lo = LegalizeOp(Lo); 3971 Hi = LegalizeOp(Hi); 3972 break; 3973 } 3974 case ISD::SEXTLOAD: { 3975 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3976 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3977 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3978 3979 if (EVT == NVT) 3980 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3981 else 3982 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3983 EVT); 3984 3985 // Remember that we legalized the chain. 3986 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3987 3988 // The high part is obtained by SRA'ing all but one of the bits of the lo 3989 // part. 3990 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3991 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3992 TLI.getShiftAmountTy())); 3993 Lo = LegalizeOp(Lo); 3994 Hi = LegalizeOp(Hi); 3995 break; 3996 } 3997 case ISD::ZEXTLOAD: { 3998 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3999 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 4000 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4001 4002 if (EVT == NVT) 4003 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 4004 else 4005 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 4006 EVT); 4007 4008 // Remember that we legalized the chain. 4009 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 4010 4011 // The high part is just a zero. 4012 Hi = LegalizeOp(DAG.getConstant(0, NVT)); 4013 Lo = LegalizeOp(Lo); 4014 break; 4015 } 4016 case ISD::EXTLOAD: { 4017 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 4018 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 4019 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4020 4021 if (EVT == NVT) 4022 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 4023 else 4024 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 4025 EVT); 4026 4027 // Remember that we legalized the chain. 4028 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 4029 4030 // The high part is undefined. 4031 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT)); 4032 Lo = LegalizeOp(Lo); 4033 break; 4034 } 4035 case ISD::ANY_EXTEND: { 4036 SDOperand In; 4037 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4038 case Expand: assert(0 && "expand-expand not implemented yet!"); 4039 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 4040 case Promote: 4041 In = PromoteOp(Node->getOperand(0)); 4042 break; 4043 } 4044 4045 // The low part is any extension of the input (which degenerates to a copy). 4046 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In); 4047 // The high part is undefined. 4048 Hi = DAG.getNode(ISD::UNDEF, NVT); 4049 break; 4050 } 4051 case ISD::SIGN_EXTEND: { 4052 SDOperand In; 4053 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4054 case Expand: assert(0 && "expand-expand not implemented yet!"); 4055 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 4056 case Promote: 4057 In = PromoteOp(Node->getOperand(0)); 4058 // Emit the appropriate sign_extend_inreg to get the value we want. 4059 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 4060 DAG.getValueType(Node->getOperand(0).getValueType())); 4061 break; 4062 } 4063 4064 // The low part is just a sign extension of the input (which degenerates to 4065 // a copy). 4066 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 4067 4068 // The high part is obtained by SRA'ing all but one of the bits of the lo 4069 // part. 4070 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4071 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 4072 TLI.getShiftAmountTy())); 4073 break; 4074 } 4075 case ISD::ZERO_EXTEND: { 4076 SDOperand In; 4077 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4078 case Expand: assert(0 && "expand-expand not implemented yet!"); 4079 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 4080 case Promote: 4081 In = PromoteOp(Node->getOperand(0)); 4082 // Emit the appropriate zero_extend_inreg to get the value we want. 4083 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 4084 break; 4085 } 4086 4087 // The low part is just a zero extension of the input (which degenerates to 4088 // a copy). 4089 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 4090 4091 // The high part is just a zero. 4092 Hi = DAG.getConstant(0, NVT); 4093 break; 4094 } 4095 4096 case ISD::BIT_CONVERT: { 4097 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0), 4098 Node->getOperand(0)); 4099 ExpandOp(Tmp, Lo, Hi); 4100 break; 4101 } 4102 4103 case ISD::READCYCLECOUNTER: { 4104 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 4105 TargetLowering::Custom && 4106 "Must custom expand ReadCycleCounter"); 4107 SDOperand T = TLI.LowerOperation(Op, DAG); 4108 assert(T.Val && "Node must be custom expanded!"); 4109 Lo = LegalizeOp(T.getValue(0)); 4110 Hi = LegalizeOp(T.getValue(1)); 4111 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 4112 LegalizeOp(T.getValue(2))); 4113 break; 4114 } 4115 4116 // These operators cannot be expanded directly, emit them as calls to 4117 // library functions. 4118 case ISD::FP_TO_SINT: 4119 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 4120 SDOperand Op; 4121 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4122 case Expand: assert(0 && "cannot expand FP!"); 4123 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 4124 case Promote: Op = PromoteOp(Node->getOperand(0)); break; 4125 } 4126 4127 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 4128 4129 // Now that the custom expander is done, expand the result, which is still 4130 // VT. 4131 if (Op.Val) { 4132 ExpandOp(Op, Lo, Hi); 4133 break; 4134 } 4135 } 4136 4137 if (Node->getOperand(0).getValueType() == MVT::f32) 4138 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 4139 else 4140 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 4141 break; 4142 4143 case ISD::FP_TO_UINT: 4144 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 4145 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, 4146 LegalizeOp(Node->getOperand(0))); 4147 // Now that the custom expander is done, expand the result, which is still 4148 // VT. 4149 Op = TLI.LowerOperation(Op, DAG); 4150 if (Op.Val) { 4151 ExpandOp(Op, Lo, Hi); 4152 break; 4153 } 4154 } 4155 4156 if (Node->getOperand(0).getValueType() == MVT::f32) 4157 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 4158 else 4159 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 4160 break; 4161 4162 case ISD::SHL: { 4163 // If the target wants custom lowering, do so. 4164 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 4165 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), 4166 LegalizeOp(Node->getOperand(1))); 4167 Op = TLI.LowerOperation(Op, DAG); 4168 if (Op.Val) { 4169 // Now that the custom expander is done, expand the result, which is 4170 // still VT. 4171 ExpandOp(Op, Lo, Hi); 4172 break; 4173 } 4174 } 4175 4176 // If we can emit an efficient shift operation, do so now. 4177 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 4178 break; 4179 4180 // If this target supports SHL_PARTS, use it. 4181 TargetLowering::LegalizeAction Action = 4182 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 4183 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4184 Action == TargetLowering::Custom) { 4185 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 4186 Lo, Hi); 4187 break; 4188 } 4189 4190 // Otherwise, emit a libcall. 4191 Lo = ExpandLibCall("__ashldi3", Node, Hi); 4192 break; 4193 } 4194 4195 case ISD::SRA: { 4196 // If the target wants custom lowering, do so. 4197 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 4198 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), 4199 LegalizeOp(Node->getOperand(1))); 4200 Op = TLI.LowerOperation(Op, DAG); 4201 if (Op.Val) { 4202 // Now that the custom expander is done, expand the result, which is 4203 // still VT. 4204 ExpandOp(Op, Lo, Hi); 4205 break; 4206 } 4207 } 4208 4209 // If we can emit an efficient shift operation, do so now. 4210 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 4211 break; 4212 4213 // If this target supports SRA_PARTS, use it. 4214 TargetLowering::LegalizeAction Action = 4215 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 4216 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4217 Action == TargetLowering::Custom) { 4218 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 4219 Lo, Hi); 4220 break; 4221 } 4222 4223 // Otherwise, emit a libcall. 4224 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 4225 break; 4226 } 4227 4228 case ISD::SRL: { 4229 // If the target wants custom lowering, do so. 4230 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 4231 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), 4232 LegalizeOp(Node->getOperand(1))); 4233 Op = TLI.LowerOperation(Op, DAG); 4234 if (Op.Val) { 4235 // Now that the custom expander is done, expand the result, which is 4236 // still VT. 4237 ExpandOp(Op, Lo, Hi); 4238 break; 4239 } 4240 } 4241 4242 // If we can emit an efficient shift operation, do so now. 4243 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 4244 break; 4245 4246 // If this target supports SRL_PARTS, use it. 4247 TargetLowering::LegalizeAction Action = 4248 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 4249 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4250 Action == TargetLowering::Custom) { 4251 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 4252 Lo, Hi); 4253 break; 4254 } 4255 4256 // Otherwise, emit a libcall. 4257 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 4258 break; 4259 } 4260 4261 case ISD::ADD: 4262 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 4263 Lo, Hi); 4264 break; 4265 case ISD::SUB: 4266 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 4267 Lo, Hi); 4268 break; 4269 case ISD::MUL: { 4270 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 4271 SDOperand LL, LH, RL, RH; 4272 ExpandOp(Node->getOperand(0), LL, LH); 4273 ExpandOp(Node->getOperand(1), RL, RH); 4274 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 4275 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 4276 // extended the sign bit of the low half through the upper half, and if so 4277 // emit a MULHS instead of the alternate sequence that is valid for any 4278 // i64 x i64 multiply. 4279 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 4280 // is RH an extension of the sign bit of RL? 4281 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 4282 RH.getOperand(1).getOpcode() == ISD::Constant && 4283 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 4284 // is LH an extension of the sign bit of LL? 4285 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 4286 LH.getOperand(1).getOpcode() == ISD::Constant && 4287 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 4288 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 4289 } else { 4290 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 4291 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 4292 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 4293 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 4294 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 4295 } 4296 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 4297 } else { 4298 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 4299 } 4300 break; 4301 } 4302 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 4303 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 4304 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 4305 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 4306 } 4307 4308 // Make sure the resultant values have been legalized themselves, unless this 4309 // is a type that requires multi-step expansion. 4310 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 4311 Lo = LegalizeOp(Lo); 4312 Hi = LegalizeOp(Hi); 4313 } 4314 4315 // Remember in a map if the values will be reused later. 4316 bool isNew = 4317 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 4318 assert(isNew && "Value already expanded?!?"); 4319} 4320 4321 4322// SelectionDAG::Legalize - This is the entry point for the file. 4323// 4324void SelectionDAG::Legalize() { 4325 /// run - This is the main entry point to this class. 4326 /// 4327 SelectionDAGLegalize(*this).Run(); 4328} 4329 4330