LegalizeDAG.cpp revision a845706dc1cebfe75913832e07ef114519a879d6
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/Analysis/DebugInfo.h" 20#include "llvm/CodeGen/PseudoSourceValue.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetOptions.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Function.h" 30#include "llvm/GlobalVariable.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/ADT/DenseMap.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/SmallPtrSet.h" 40using namespace llvm; 41 42//===----------------------------------------------------------------------===// 43/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 44/// hacks on it until the target machine can handle it. This involves 45/// eliminating value sizes the machine cannot handle (promoting small sizes to 46/// large sizes or splitting up large values into small values) as well as 47/// eliminating operations the machine cannot handle. 48/// 49/// This code also does a small amount of optimization and recognition of idioms 50/// as part of its processing. For example, if a target does not support a 51/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 52/// will attempt merge setcc and brc instructions into brcc's. 53/// 54namespace { 55class SelectionDAGLegalize { 56 const TargetMachine &TM; 57 const TargetLowering &TLI; 58 SelectionDAG &DAG; 59 CodeGenOpt::Level OptLevel; 60 61 // Libcall insertion helpers. 62 63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 64 /// legalized. We use this to ensure that calls are properly serialized 65 /// against each other, including inserted libcalls. 66 SDValue LastCALLSEQ_END; 67 68 /// IsLegalizingCall - This member is used *only* for purposes of providing 69 /// helpful assertions that a libcall isn't created while another call is 70 /// being legalized (which could lead to non-serialized call sequences). 71 bool IsLegalizingCall; 72 73 enum LegalizeAction { 74 Legal, // The target natively supports this operation. 75 Promote, // This operation should be executed in a larger type. 76 Expand // Try to expand this to other ops, otherwise use a libcall. 77 }; 78 79 /// ValueTypeActions - This is a bitvector that contains two bits for each 80 /// value type, where the two bits correspond to the LegalizeAction enum. 81 /// This can be queried with "getTypeAction(VT)". 82 TargetLowering::ValueTypeActionImpl ValueTypeActions; 83 84 /// LegalizedNodes - For nodes that are of legal width, and that have more 85 /// than one use, this map indicates what regularized operand to use. This 86 /// allows us to avoid legalizing the same thing more than once. 87 DenseMap<SDValue, SDValue> LegalizedNodes; 88 89 void AddLegalizedOperand(SDValue From, SDValue To) { 90 LegalizedNodes.insert(std::make_pair(From, To)); 91 // If someone requests legalization of the new node, return itself. 92 if (From != To) 93 LegalizedNodes.insert(std::make_pair(To, To)); 94 } 95 96public: 97 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 98 99 /// getTypeAction - Return how we should legalize values of this type, either 100 /// it is already legal or we need to expand it into multiple registers of 101 /// smaller integer type, or we need to promote it to a larger type. 102 LegalizeAction getTypeAction(EVT VT) const { 103 return 104 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT); 105 } 106 107 /// isTypeLegal - Return true if this type is legal on this target. 108 /// 109 bool isTypeLegal(EVT VT) const { 110 return getTypeAction(VT) == Legal; 111 } 112 113 void LegalizeDAG(); 114 115private: 116 /// LegalizeOp - We know that the specified value has a legal type. 117 /// Recursively ensure that the operands have legal types, then return the 118 /// result. 119 SDValue LegalizeOp(SDValue O); 120 121 SDValue OptimizeFloatStore(StoreSDNode *ST); 122 123 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 124 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 125 /// is necessary to spill the vector being inserted into to memory, perform 126 /// the insert there, and then read the result back. 127 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 128 SDValue Idx, DebugLoc dl); 129 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 130 SDValue Idx, DebugLoc dl); 131 132 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 133 /// performs the same shuffe in terms of order or result bytes, but on a type 134 /// whose vector element type is narrower than the original shuffle type. 135 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 136 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 137 SDValue N1, SDValue N2, 138 SmallVectorImpl<int> &Mask) const; 139 140 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 141 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 142 143 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 144 DebugLoc dl); 145 146 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 147 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC, 148 SDNode *Node, bool isSigned); 149 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 150 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 151 RTLIB::Libcall Call_PPCF128); 152 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 153 RTLIB::Libcall Call_I8, 154 RTLIB::Libcall Call_I16, 155 RTLIB::Libcall Call_I32, 156 RTLIB::Libcall Call_I64, 157 RTLIB::Libcall Call_I128); 158 159 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 160 SDValue ExpandBUILD_VECTOR(SDNode *Node); 161 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 162 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 163 SmallVectorImpl<SDValue> &Results); 164 SDValue ExpandFCOPYSIGN(SDNode *Node); 165 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 166 DebugLoc dl); 167 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 168 DebugLoc dl); 169 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 170 DebugLoc dl); 171 172 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 173 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 174 175 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 176 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 177 178 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node); 179 180 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 181 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 182}; 183} 184 185/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 186/// performs the same shuffe in terms of order or result bytes, but on a type 187/// whose vector element type is narrower than the original shuffle type. 188/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 189SDValue 190SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 191 SDValue N1, SDValue N2, 192 SmallVectorImpl<int> &Mask) const { 193 unsigned NumMaskElts = VT.getVectorNumElements(); 194 unsigned NumDestElts = NVT.getVectorNumElements(); 195 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 196 197 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 198 199 if (NumEltsGrowth == 1) 200 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 201 202 SmallVector<int, 8> NewMask; 203 for (unsigned i = 0; i != NumMaskElts; ++i) { 204 int Idx = Mask[i]; 205 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 206 if (Idx < 0) 207 NewMask.push_back(-1); 208 else 209 NewMask.push_back(Idx * NumEltsGrowth + j); 210 } 211 } 212 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 213 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 214 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 215} 216 217SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 218 CodeGenOpt::Level ol) 219 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 220 DAG(dag), OptLevel(ol), 221 ValueTypeActions(TLI.getValueTypeActions()) { 222 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 223 "Too many value types for ValueTypeActions to hold!"); 224} 225 226void SelectionDAGLegalize::LegalizeDAG() { 227 LastCALLSEQ_END = DAG.getEntryNode(); 228 IsLegalizingCall = false; 229 230 // The legalize process is inherently a bottom-up recursive process (users 231 // legalize their uses before themselves). Given infinite stack space, we 232 // could just start legalizing on the root and traverse the whole graph. In 233 // practice however, this causes us to run out of stack space on large basic 234 // blocks. To avoid this problem, compute an ordering of the nodes where each 235 // node is only legalized after all of its operands are legalized. 236 DAG.AssignTopologicalOrder(); 237 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 238 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 239 LegalizeOp(SDValue(I, 0)); 240 241 // Finally, it's possible the root changed. Get the new root. 242 SDValue OldRoot = DAG.getRoot(); 243 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 244 DAG.setRoot(LegalizedNodes[OldRoot]); 245 246 LegalizedNodes.clear(); 247 248 // Remove dead nodes now. 249 DAG.RemoveDeadNodes(); 250} 251 252 253/// FindCallEndFromCallStart - Given a chained node that is part of a call 254/// sequence, find the CALLSEQ_END node that terminates the call sequence. 255static SDNode *FindCallEndFromCallStart(SDNode *Node) { 256 if (Node->getOpcode() == ISD::CALLSEQ_END) 257 return Node; 258 if (Node->use_empty()) 259 return 0; // No CallSeqEnd 260 261 // The chain is usually at the end. 262 SDValue TheChain(Node, Node->getNumValues()-1); 263 if (TheChain.getValueType() != MVT::Other) { 264 // Sometimes it's at the beginning. 265 TheChain = SDValue(Node, 0); 266 if (TheChain.getValueType() != MVT::Other) { 267 // Otherwise, hunt for it. 268 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 269 if (Node->getValueType(i) == MVT::Other) { 270 TheChain = SDValue(Node, i); 271 break; 272 } 273 274 // Otherwise, we walked into a node without a chain. 275 if (TheChain.getValueType() != MVT::Other) 276 return 0; 277 } 278 } 279 280 for (SDNode::use_iterator UI = Node->use_begin(), 281 E = Node->use_end(); UI != E; ++UI) { 282 283 // Make sure to only follow users of our token chain. 284 SDNode *User = *UI; 285 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 286 if (User->getOperand(i) == TheChain) 287 if (SDNode *Result = FindCallEndFromCallStart(User)) 288 return Result; 289 } 290 return 0; 291} 292 293/// FindCallStartFromCallEnd - Given a chained node that is part of a call 294/// sequence, find the CALLSEQ_START node that initiates the call sequence. 295static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 296 assert(Node && "Didn't find callseq_start for a call??"); 297 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 298 299 assert(Node->getOperand(0).getValueType() == MVT::Other && 300 "Node doesn't have a token chain argument!"); 301 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 302} 303 304/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 305/// see if any uses can reach Dest. If no dest operands can get to dest, 306/// legalize them, legalize ourself, and return false, otherwise, return true. 307/// 308/// Keep track of the nodes we fine that actually do lead to Dest in 309/// NodesLeadingTo. This avoids retraversing them exponential number of times. 310/// 311bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 312 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 313 if (N == Dest) return true; // N certainly leads to Dest :) 314 315 // If we've already processed this node and it does lead to Dest, there is no 316 // need to reprocess it. 317 if (NodesLeadingTo.count(N)) return true; 318 319 // If the first result of this node has been already legalized, then it cannot 320 // reach N. 321 if (LegalizedNodes.count(SDValue(N, 0))) return false; 322 323 // Okay, this node has not already been legalized. Check and legalize all 324 // operands. If none lead to Dest, then we can legalize this node. 325 bool OperandsLeadToDest = false; 326 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 327 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 328 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 329 330 if (OperandsLeadToDest) { 331 NodesLeadingTo.insert(N); 332 return true; 333 } 334 335 // Okay, this node looks safe, legalize it and return false. 336 LegalizeOp(SDValue(N, 0)); 337 return false; 338} 339 340/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 341/// a load from the constant pool. 342static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 343 SelectionDAG &DAG, const TargetLowering &TLI) { 344 bool Extend = false; 345 DebugLoc dl = CFP->getDebugLoc(); 346 347 // If a FP immediate is precise when represented as a float and if the 348 // target can do an extending load from float to double, we put it into 349 // the constant pool as a float, even if it's is statically typed as a 350 // double. This shrinks FP constants and canonicalizes them for targets where 351 // an FP extending load is the same cost as a normal load (such as on the x87 352 // fp stack or PPC FP unit). 353 EVT VT = CFP->getValueType(0); 354 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 355 if (!UseCP) { 356 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 357 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 358 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 359 } 360 361 EVT OrigVT = VT; 362 EVT SVT = VT; 363 while (SVT != MVT::f32) { 364 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 365 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) && 366 // Only do this if the target has a native EXTLOAD instruction from 367 // smaller type. 368 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 369 TLI.ShouldShrinkFPConstant(OrigVT)) { 370 const Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 371 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 372 VT = SVT; 373 Extend = true; 374 } 375 } 376 377 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 378 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 379 if (Extend) 380 return DAG.getExtLoad(ISD::EXTLOAD, dl, 381 OrigVT, DAG.getEntryNode(), 382 CPIdx, PseudoSourceValue::getConstantPool(), 383 0, VT, false, false, Alignment); 384 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 385 PseudoSourceValue::getConstantPool(), 0, false, false, 386 Alignment); 387} 388 389/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 390static 391SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 392 const TargetLowering &TLI) { 393 SDValue Chain = ST->getChain(); 394 SDValue Ptr = ST->getBasePtr(); 395 SDValue Val = ST->getValue(); 396 EVT VT = Val.getValueType(); 397 int Alignment = ST->getAlignment(); 398 int SVOffset = ST->getSrcValueOffset(); 399 DebugLoc dl = ST->getDebugLoc(); 400 if (ST->getMemoryVT().isFloatingPoint() || 401 ST->getMemoryVT().isVector()) { 402 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 403 if (TLI.isTypeLegal(intVT)) { 404 // Expand to a bitconvert of the value to the integer type of the 405 // same size, then a (misaligned) int store. 406 // FIXME: Does not handle truncating floating point stores! 407 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 408 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 409 SVOffset, ST->isVolatile(), ST->isNonTemporal(), 410 Alignment); 411 } else { 412 // Do a (aligned) store to a stack slot, then copy from the stack slot 413 // to the final destination using (unaligned) integer loads and stores. 414 EVT StoredVT = ST->getMemoryVT(); 415 EVT RegVT = 416 TLI.getRegisterType(*DAG.getContext(), 417 EVT::getIntegerVT(*DAG.getContext(), 418 StoredVT.getSizeInBits())); 419 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 420 unsigned RegBytes = RegVT.getSizeInBits() / 8; 421 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 422 423 // Make sure the stack slot is also aligned for the register type. 424 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 425 426 // Perform the original store, only redirected to the stack slot. 427 SDValue Store = DAG.getTruncStore(Chain, dl, 428 Val, StackPtr, NULL, 0, StoredVT, 429 false, false, 0); 430 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 431 SmallVector<SDValue, 8> Stores; 432 unsigned Offset = 0; 433 434 // Do all but one copies using the full register width. 435 for (unsigned i = 1; i < NumRegs; i++) { 436 // Load one integer register's worth from the stack slot. 437 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0, 438 false, false, 0); 439 // Store it to the final location. Remember the store. 440 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 441 ST->getSrcValue(), SVOffset + Offset, 442 ST->isVolatile(), ST->isNonTemporal(), 443 MinAlign(ST->getAlignment(), Offset))); 444 // Increment the pointers. 445 Offset += RegBytes; 446 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 447 Increment); 448 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 449 } 450 451 // The last store may be partial. Do a truncating store. On big-endian 452 // machines this requires an extending load from the stack slot to ensure 453 // that the bits are in the right place. 454 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 455 8 * (StoredBytes - Offset)); 456 457 // Load from the stack slot. 458 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 459 NULL, 0, MemVT, false, false, 0); 460 461 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 462 ST->getSrcValue(), SVOffset + Offset, 463 MemVT, ST->isVolatile(), 464 ST->isNonTemporal(), 465 MinAlign(ST->getAlignment(), Offset))); 466 // The order of the stores doesn't matter - say it with a TokenFactor. 467 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 468 Stores.size()); 469 } 470 } 471 assert(ST->getMemoryVT().isInteger() && 472 !ST->getMemoryVT().isVector() && 473 "Unaligned store of unknown type."); 474 // Get the half-size VT 475 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 476 int NumBits = NewStoredVT.getSizeInBits(); 477 int IncrementSize = NumBits / 8; 478 479 // Divide the stored value in two parts. 480 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 481 SDValue Lo = Val; 482 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 483 484 // Store the two parts 485 SDValue Store1, Store2; 486 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 487 ST->getSrcValue(), SVOffset, NewStoredVT, 488 ST->isVolatile(), ST->isNonTemporal(), Alignment); 489 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 490 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 491 Alignment = MinAlign(Alignment, IncrementSize); 492 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 493 ST->getSrcValue(), SVOffset + IncrementSize, 494 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 495 Alignment); 496 497 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 498} 499 500/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 501static 502SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 503 const TargetLowering &TLI) { 504 int SVOffset = LD->getSrcValueOffset(); 505 SDValue Chain = LD->getChain(); 506 SDValue Ptr = LD->getBasePtr(); 507 EVT VT = LD->getValueType(0); 508 EVT LoadedVT = LD->getMemoryVT(); 509 DebugLoc dl = LD->getDebugLoc(); 510 if (VT.isFloatingPoint() || VT.isVector()) { 511 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 512 if (TLI.isTypeLegal(intVT)) { 513 // Expand to a (misaligned) integer load of the same size, 514 // then bitconvert to floating point or vector. 515 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 516 SVOffset, LD->isVolatile(), 517 LD->isNonTemporal(), LD->getAlignment()); 518 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 519 if (VT.isFloatingPoint() && LoadedVT != VT) 520 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 521 522 SDValue Ops[] = { Result, Chain }; 523 return DAG.getMergeValues(Ops, 2, dl); 524 } else { 525 // Copy the value to a (aligned) stack slot using (unaligned) integer 526 // loads and stores, then do a (aligned) load from the stack slot. 527 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 528 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 529 unsigned RegBytes = RegVT.getSizeInBits() / 8; 530 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 531 532 // Make sure the stack slot is also aligned for the register type. 533 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 534 535 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 536 SmallVector<SDValue, 8> Stores; 537 SDValue StackPtr = StackBase; 538 unsigned Offset = 0; 539 540 // Do all but one copies using the full register width. 541 for (unsigned i = 1; i < NumRegs; i++) { 542 // Load one integer register's worth from the original location. 543 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 544 SVOffset + Offset, LD->isVolatile(), 545 LD->isNonTemporal(), 546 MinAlign(LD->getAlignment(), Offset)); 547 // Follow the load with a store to the stack slot. Remember the store. 548 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 549 NULL, 0, false, false, 0)); 550 // Increment the pointers. 551 Offset += RegBytes; 552 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 553 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 554 Increment); 555 } 556 557 // The last copy may be partial. Do an extending load. 558 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 559 8 * (LoadedBytes - Offset)); 560 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 561 LD->getSrcValue(), SVOffset + Offset, 562 MemVT, LD->isVolatile(), 563 LD->isNonTemporal(), 564 MinAlign(LD->getAlignment(), Offset)); 565 // Follow the load with a store to the stack slot. Remember the store. 566 // On big-endian machines this requires a truncating store to ensure 567 // that the bits end up in the right place. 568 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 569 NULL, 0, MemVT, false, false, 0)); 570 571 // The order of the stores doesn't matter - say it with a TokenFactor. 572 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 573 Stores.size()); 574 575 // Finally, perform the original load only redirected to the stack slot. 576 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 577 NULL, 0, LoadedVT, false, false, 0); 578 579 // Callers expect a MERGE_VALUES node. 580 SDValue Ops[] = { Load, TF }; 581 return DAG.getMergeValues(Ops, 2, dl); 582 } 583 } 584 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 585 "Unaligned load of unsupported type."); 586 587 // Compute the new VT that is half the size of the old one. This is an 588 // integer MVT. 589 unsigned NumBits = LoadedVT.getSizeInBits(); 590 EVT NewLoadedVT; 591 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 592 NumBits >>= 1; 593 594 unsigned Alignment = LD->getAlignment(); 595 unsigned IncrementSize = NumBits / 8; 596 ISD::LoadExtType HiExtType = LD->getExtensionType(); 597 598 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 599 if (HiExtType == ISD::NON_EXTLOAD) 600 HiExtType = ISD::ZEXTLOAD; 601 602 // Load the value in two parts 603 SDValue Lo, Hi; 604 if (TLI.isLittleEndian()) { 605 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 606 SVOffset, NewLoadedVT, LD->isVolatile(), 607 LD->isNonTemporal(), Alignment); 608 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 609 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 610 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 611 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 612 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize)); 613 } else { 614 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 615 SVOffset, NewLoadedVT, LD->isVolatile(), 616 LD->isNonTemporal(), Alignment); 617 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 618 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 619 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 620 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 621 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize)); 622 } 623 624 // aggregate the two parts 625 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 626 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 627 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 628 629 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 630 Hi.getValue(1)); 631 632 SDValue Ops[] = { Result, TF }; 633 return DAG.getMergeValues(Ops, 2, dl); 634} 635 636/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 637/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 638/// is necessary to spill the vector being inserted into to memory, perform 639/// the insert there, and then read the result back. 640SDValue SelectionDAGLegalize:: 641PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 642 DebugLoc dl) { 643 SDValue Tmp1 = Vec; 644 SDValue Tmp2 = Val; 645 SDValue Tmp3 = Idx; 646 647 // If the target doesn't support this, we have to spill the input vector 648 // to a temporary stack slot, update the element, then reload it. This is 649 // badness. We could also load the value into a vector register (either 650 // with a "move to register" or "extload into register" instruction, then 651 // permute it into place, if the idx is a constant and if the idx is 652 // supported by the target. 653 EVT VT = Tmp1.getValueType(); 654 EVT EltVT = VT.getVectorElementType(); 655 EVT IdxVT = Tmp3.getValueType(); 656 EVT PtrVT = TLI.getPointerTy(); 657 SDValue StackPtr = DAG.CreateStackTemporary(VT); 658 659 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 660 661 // Store the vector. 662 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 663 PseudoSourceValue::getFixedStack(SPFI), 0, 664 false, false, 0); 665 666 // Truncate or zero extend offset to target pointer type. 667 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 668 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 669 // Add the offset to the index. 670 unsigned EltSize = EltVT.getSizeInBits()/8; 671 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 672 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 673 // Store the scalar value. 674 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 675 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT, 676 false, false, 0); 677 // Load the updated vector. 678 return DAG.getLoad(VT, dl, Ch, StackPtr, 679 PseudoSourceValue::getFixedStack(SPFI), 0, 680 false, false, 0); 681} 682 683 684SDValue SelectionDAGLegalize:: 685ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 686 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 687 // SCALAR_TO_VECTOR requires that the type of the value being inserted 688 // match the element type of the vector being created, except for 689 // integers in which case the inserted value can be over width. 690 EVT EltVT = Vec.getValueType().getVectorElementType(); 691 if (Val.getValueType() == EltVT || 692 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 693 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 694 Vec.getValueType(), Val); 695 696 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 697 // We generate a shuffle of InVec and ScVec, so the shuffle mask 698 // should be 0,1,2,3,4,5... with the appropriate element replaced with 699 // elt 0 of the RHS. 700 SmallVector<int, 8> ShufOps; 701 for (unsigned i = 0; i != NumElts; ++i) 702 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 703 704 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 705 &ShufOps[0]); 706 } 707 } 708 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 709} 710 711SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 712 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 713 // FIXME: We shouldn't do this for TargetConstantFP's. 714 // FIXME: move this to the DAG Combiner! Note that we can't regress due 715 // to phase ordering between legalized code and the dag combiner. This 716 // probably means that we need to integrate dag combiner and legalizer 717 // together. 718 // We generally can't do this one for long doubles. 719 SDValue Tmp1 = ST->getChain(); 720 SDValue Tmp2 = ST->getBasePtr(); 721 SDValue Tmp3; 722 int SVOffset = ST->getSrcValueOffset(); 723 unsigned Alignment = ST->getAlignment(); 724 bool isVolatile = ST->isVolatile(); 725 bool isNonTemporal = ST->isNonTemporal(); 726 DebugLoc dl = ST->getDebugLoc(); 727 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 728 if (CFP->getValueType(0) == MVT::f32 && 729 getTypeAction(MVT::i32) == Legal) { 730 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 731 bitcastToAPInt().zextOrTrunc(32), 732 MVT::i32); 733 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 734 SVOffset, isVolatile, isNonTemporal, Alignment); 735 } else if (CFP->getValueType(0) == MVT::f64) { 736 // If this target supports 64-bit registers, do a single 64-bit store. 737 if (getTypeAction(MVT::i64) == Legal) { 738 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 739 zextOrTrunc(64), MVT::i64); 740 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 741 SVOffset, isVolatile, isNonTemporal, Alignment); 742 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 743 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 744 // stores. If the target supports neither 32- nor 64-bits, this 745 // xform is certainly not worth it. 746 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 747 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 748 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 749 if (TLI.isBigEndian()) std::swap(Lo, Hi); 750 751 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 752 SVOffset, isVolatile, isNonTemporal, Alignment); 753 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 754 DAG.getIntPtrConstant(4)); 755 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 756 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 757 758 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 759 } 760 } 761 } 762 return SDValue(); 763} 764 765/// LegalizeOp - We know that the specified value has a legal type, and 766/// that its operands are legal. Now ensure that the operation itself 767/// is legal, recursively ensuring that the operands' operations remain 768/// legal. 769SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 770 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 771 return Op; 772 773 SDNode *Node = Op.getNode(); 774 DebugLoc dl = Node->getDebugLoc(); 775 776 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 777 assert(getTypeAction(Node->getValueType(i)) == Legal && 778 "Unexpected illegal type!"); 779 780 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 781 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 782 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 783 "Unexpected illegal type!"); 784 785 // Note that LegalizeOp may be reentered even from single-use nodes, which 786 // means that we always must cache transformed nodes. 787 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 788 if (I != LegalizedNodes.end()) return I->second; 789 790 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 791 SDValue Result = Op; 792 bool isCustom = false; 793 794 // Figure out the correct action; the way to query this varies by opcode 795 TargetLowering::LegalizeAction Action; 796 bool SimpleFinishLegalizing = true; 797 switch (Node->getOpcode()) { 798 case ISD::INTRINSIC_W_CHAIN: 799 case ISD::INTRINSIC_WO_CHAIN: 800 case ISD::INTRINSIC_VOID: 801 case ISD::VAARG: 802 case ISD::STACKSAVE: 803 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 804 break; 805 case ISD::SINT_TO_FP: 806 case ISD::UINT_TO_FP: 807 case ISD::EXTRACT_VECTOR_ELT: 808 Action = TLI.getOperationAction(Node->getOpcode(), 809 Node->getOperand(0).getValueType()); 810 break; 811 case ISD::FP_ROUND_INREG: 812 case ISD::SIGN_EXTEND_INREG: { 813 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 814 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 815 break; 816 } 817 case ISD::SELECT_CC: 818 case ISD::SETCC: 819 case ISD::BR_CC: { 820 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 821 Node->getOpcode() == ISD::SETCC ? 2 : 1; 822 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 823 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 824 ISD::CondCode CCCode = 825 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 826 Action = TLI.getCondCodeAction(CCCode, OpVT); 827 if (Action == TargetLowering::Legal) { 828 if (Node->getOpcode() == ISD::SELECT_CC) 829 Action = TLI.getOperationAction(Node->getOpcode(), 830 Node->getValueType(0)); 831 else 832 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 833 } 834 break; 835 } 836 case ISD::LOAD: 837 case ISD::STORE: 838 // FIXME: Model these properly. LOAD and STORE are complicated, and 839 // STORE expects the unlegalized operand in some cases. 840 SimpleFinishLegalizing = false; 841 break; 842 case ISD::CALLSEQ_START: 843 case ISD::CALLSEQ_END: 844 // FIXME: This shouldn't be necessary. These nodes have special properties 845 // dealing with the recursive nature of legalization. Removing this 846 // special case should be done as part of making LegalizeDAG non-recursive. 847 SimpleFinishLegalizing = false; 848 break; 849 case ISD::EXTRACT_ELEMENT: 850 case ISD::FLT_ROUNDS_: 851 case ISD::SADDO: 852 case ISD::SSUBO: 853 case ISD::UADDO: 854 case ISD::USUBO: 855 case ISD::SMULO: 856 case ISD::UMULO: 857 case ISD::FPOWI: 858 case ISD::MERGE_VALUES: 859 case ISD::EH_RETURN: 860 case ISD::FRAME_TO_ARGS_OFFSET: 861 // These operations lie about being legal: when they claim to be legal, 862 // they should actually be expanded. 863 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 864 if (Action == TargetLowering::Legal) 865 Action = TargetLowering::Expand; 866 break; 867 case ISD::TRAMPOLINE: 868 case ISD::FRAMEADDR: 869 case ISD::RETURNADDR: 870 case ISD::EH_SJLJ_SETJMP: 871 case ISD::EH_SJLJ_LONGJMP: 872 // These operations lie about being legal: when they claim to be legal, 873 // they should actually be custom-lowered. 874 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 875 if (Action == TargetLowering::Legal) 876 Action = TargetLowering::Custom; 877 break; 878 case ISD::BUILD_VECTOR: 879 // A weird case: legalization for BUILD_VECTOR never legalizes the 880 // operands! 881 // FIXME: This really sucks... changing it isn't semantically incorrect, 882 // but it massively pessimizes the code for floating-point BUILD_VECTORs 883 // because ConstantFP operands get legalized into constant pool loads 884 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 885 // though, because BUILD_VECTORS usually get lowered into other nodes 886 // which get legalized properly. 887 SimpleFinishLegalizing = false; 888 break; 889 default: 890 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 891 Action = TargetLowering::Legal; 892 } else { 893 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 894 } 895 break; 896 } 897 898 if (SimpleFinishLegalizing) { 899 SmallVector<SDValue, 8> Ops, ResultVals; 900 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 901 Ops.push_back(LegalizeOp(Node->getOperand(i))); 902 switch (Node->getOpcode()) { 903 default: break; 904 case ISD::BR: 905 case ISD::BRIND: 906 case ISD::BR_JT: 907 case ISD::BR_CC: 908 case ISD::BRCOND: 909 // Branches tweak the chain to include LastCALLSEQ_END 910 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 911 LastCALLSEQ_END); 912 Ops[0] = LegalizeOp(Ops[0]); 913 LastCALLSEQ_END = DAG.getEntryNode(); 914 break; 915 case ISD::SHL: 916 case ISD::SRL: 917 case ISD::SRA: 918 case ISD::ROTL: 919 case ISD::ROTR: 920 // Legalizing shifts/rotates requires adjusting the shift amount 921 // to the appropriate width. 922 if (!Ops[1].getValueType().isVector()) 923 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 924 break; 925 case ISD::SRL_PARTS: 926 case ISD::SRA_PARTS: 927 case ISD::SHL_PARTS: 928 // Legalizing shifts/rotates requires adjusting the shift amount 929 // to the appropriate width. 930 if (!Ops[2].getValueType().isVector()) 931 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2])); 932 break; 933 } 934 935 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(), 936 Ops.size()), 0); 937 switch (Action) { 938 case TargetLowering::Legal: 939 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 940 ResultVals.push_back(Result.getValue(i)); 941 break; 942 case TargetLowering::Custom: 943 // FIXME: The handling for custom lowering with multiple results is 944 // a complete mess. 945 Tmp1 = TLI.LowerOperation(Result, DAG); 946 if (Tmp1.getNode()) { 947 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 948 if (e == 1) 949 ResultVals.push_back(Tmp1); 950 else 951 ResultVals.push_back(Tmp1.getValue(i)); 952 } 953 break; 954 } 955 956 // FALL THROUGH 957 case TargetLowering::Expand: 958 ExpandNode(Result.getNode(), ResultVals); 959 break; 960 case TargetLowering::Promote: 961 PromoteNode(Result.getNode(), ResultVals); 962 break; 963 } 964 if (!ResultVals.empty()) { 965 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 966 if (ResultVals[i] != SDValue(Node, i)) 967 ResultVals[i] = LegalizeOp(ResultVals[i]); 968 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 969 } 970 return ResultVals[Op.getResNo()]; 971 } 972 } 973 974 switch (Node->getOpcode()) { 975 default: 976#ifndef NDEBUG 977 dbgs() << "NODE: "; 978 Node->dump( &DAG); 979 dbgs() << "\n"; 980#endif 981 assert(0 && "Do not know how to legalize this operator!"); 982 983 case ISD::BUILD_VECTOR: 984 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 985 default: assert(0 && "This action is not supported yet!"); 986 case TargetLowering::Custom: 987 Tmp3 = TLI.LowerOperation(Result, DAG); 988 if (Tmp3.getNode()) { 989 Result = Tmp3; 990 break; 991 } 992 // FALLTHROUGH 993 case TargetLowering::Expand: 994 Result = ExpandBUILD_VECTOR(Result.getNode()); 995 break; 996 } 997 break; 998 case ISD::CALLSEQ_START: { 999 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1000 1001 // Recursively Legalize all of the inputs of the call end that do not lead 1002 // to this call start. This ensures that any libcalls that need be inserted 1003 // are inserted *before* the CALLSEQ_START. 1004 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1005 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1006 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1007 NodesLeadingTo); 1008 } 1009 1010 // Now that we legalized all of the inputs (which may have inserted 1011 // libcalls) create the new CALLSEQ_START node. 1012 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1013 1014 // Merge in the last call, to ensure that this call start after the last 1015 // call ended. 1016 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1017 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1018 Tmp1, LastCALLSEQ_END); 1019 Tmp1 = LegalizeOp(Tmp1); 1020 } 1021 1022 // Do not try to legalize the target-specific arguments (#1+). 1023 if (Tmp1 != Node->getOperand(0)) { 1024 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1025 Ops[0] = Tmp1; 1026 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0], Ops.size()), 1027 Result.getResNo()); 1028 } 1029 1030 // Remember that the CALLSEQ_START is legalized. 1031 AddLegalizedOperand(Op.getValue(0), Result); 1032 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1033 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1034 1035 // Now that the callseq_start and all of the non-call nodes above this call 1036 // sequence have been legalized, legalize the call itself. During this 1037 // process, no libcalls can/will be inserted, guaranteeing that no calls 1038 // can overlap. 1039 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1040 // Note that we are selecting this call! 1041 LastCALLSEQ_END = SDValue(CallEnd, 0); 1042 IsLegalizingCall = true; 1043 1044 // Legalize the call, starting from the CALLSEQ_END. 1045 LegalizeOp(LastCALLSEQ_END); 1046 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1047 return Result; 1048 } 1049 case ISD::CALLSEQ_END: 1050 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1051 // will cause this node to be legalized as well as handling libcalls right. 1052 if (LastCALLSEQ_END.getNode() != Node) { 1053 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1054 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1055 assert(I != LegalizedNodes.end() && 1056 "Legalizing the call start should have legalized this node!"); 1057 return I->second; 1058 } 1059 1060 // Otherwise, the call start has been legalized and everything is going 1061 // according to plan. Just legalize ourselves normally here. 1062 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1063 // Do not try to legalize the target-specific arguments (#1+), except for 1064 // an optional flag input. 1065 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1066 if (Tmp1 != Node->getOperand(0)) { 1067 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1068 Ops[0] = Tmp1; 1069 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1070 &Ops[0], Ops.size()), 1071 Result.getResNo()); 1072 } 1073 } else { 1074 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1075 if (Tmp1 != Node->getOperand(0) || 1076 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1077 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1078 Ops[0] = Tmp1; 1079 Ops.back() = Tmp2; 1080 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1081 &Ops[0], Ops.size()), 1082 Result.getResNo()); 1083 } 1084 } 1085 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1086 // This finishes up call legalization. 1087 IsLegalizingCall = false; 1088 1089 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1090 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1091 if (Node->getNumValues() == 2) 1092 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1093 return Result.getValue(Op.getResNo()); 1094 case ISD::LOAD: { 1095 LoadSDNode *LD = cast<LoadSDNode>(Node); 1096 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1097 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1098 1099 ISD::LoadExtType ExtType = LD->getExtensionType(); 1100 if (ExtType == ISD::NON_EXTLOAD) { 1101 EVT VT = Node->getValueType(0); 1102 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1103 Tmp1, Tmp2, LD->getOffset()), 1104 Result.getResNo()); 1105 Tmp3 = Result.getValue(0); 1106 Tmp4 = Result.getValue(1); 1107 1108 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1109 default: assert(0 && "This action is not supported yet!"); 1110 case TargetLowering::Legal: 1111 // If this is an unaligned load and the target doesn't support it, 1112 // expand it. 1113 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1114 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1115 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1116 if (LD->getAlignment() < ABIAlignment){ 1117 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1118 DAG, TLI); 1119 Tmp3 = Result.getOperand(0); 1120 Tmp4 = Result.getOperand(1); 1121 Tmp3 = LegalizeOp(Tmp3); 1122 Tmp4 = LegalizeOp(Tmp4); 1123 } 1124 } 1125 break; 1126 case TargetLowering::Custom: 1127 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1128 if (Tmp1.getNode()) { 1129 Tmp3 = LegalizeOp(Tmp1); 1130 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1131 } 1132 break; 1133 case TargetLowering::Promote: { 1134 // Only promote a load of vector type to another. 1135 assert(VT.isVector() && "Cannot promote this load!"); 1136 // Change base type to a different vector type. 1137 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1138 1139 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1140 LD->getSrcValueOffset(), 1141 LD->isVolatile(), LD->isNonTemporal(), 1142 LD->getAlignment()); 1143 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1144 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1145 break; 1146 } 1147 } 1148 // Since loads produce two values, make sure to remember that we 1149 // legalized both of them. 1150 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1151 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1152 return Op.getResNo() ? Tmp4 : Tmp3; 1153 } else { 1154 EVT SrcVT = LD->getMemoryVT(); 1155 unsigned SrcWidth = SrcVT.getSizeInBits(); 1156 int SVOffset = LD->getSrcValueOffset(); 1157 unsigned Alignment = LD->getAlignment(); 1158 bool isVolatile = LD->isVolatile(); 1159 bool isNonTemporal = LD->isNonTemporal(); 1160 1161 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1162 // Some targets pretend to have an i1 loading operation, and actually 1163 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1164 // bits are guaranteed to be zero; it helps the optimizers understand 1165 // that these bits are zero. It is also useful for EXTLOAD, since it 1166 // tells the optimizers that those bits are undefined. It would be 1167 // nice to have an effective generic way of getting these benefits... 1168 // Until such a way is found, don't insist on promoting i1 here. 1169 (SrcVT != MVT::i1 || 1170 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1171 // Promote to a byte-sized load if not loading an integral number of 1172 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1173 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1174 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 1175 SDValue Ch; 1176 1177 // The extra bits are guaranteed to be zero, since we stored them that 1178 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1179 1180 ISD::LoadExtType NewExtType = 1181 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1182 1183 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 1184 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1185 NVT, isVolatile, isNonTemporal, Alignment); 1186 1187 Ch = Result.getValue(1); // The chain. 1188 1189 if (ExtType == ISD::SEXTLOAD) 1190 // Having the top bits zero doesn't help when sign extending. 1191 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1192 Result.getValueType(), 1193 Result, DAG.getValueType(SrcVT)); 1194 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1195 // All the top bits are guaranteed to be zero - inform the optimizers. 1196 Result = DAG.getNode(ISD::AssertZext, dl, 1197 Result.getValueType(), Result, 1198 DAG.getValueType(SrcVT)); 1199 1200 Tmp1 = LegalizeOp(Result); 1201 Tmp2 = LegalizeOp(Ch); 1202 } else if (SrcWidth & (SrcWidth - 1)) { 1203 // If not loading a power-of-2 number of bits, expand as two loads. 1204 assert(!SrcVT.isVector() && "Unsupported extload!"); 1205 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1206 assert(RoundWidth < SrcWidth); 1207 unsigned ExtraWidth = SrcWidth - RoundWidth; 1208 assert(ExtraWidth < RoundWidth); 1209 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1210 "Load size not an integral number of bytes!"); 1211 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1212 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1213 SDValue Lo, Hi, Ch; 1214 unsigned IncrementSize; 1215 1216 if (TLI.isLittleEndian()) { 1217 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1218 // Load the bottom RoundWidth bits. 1219 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1220 Node->getValueType(0), Tmp1, Tmp2, 1221 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1222 isNonTemporal, Alignment); 1223 1224 // Load the remaining ExtraWidth bits. 1225 IncrementSize = RoundWidth / 8; 1226 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1227 DAG.getIntPtrConstant(IncrementSize)); 1228 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1229 LD->getSrcValue(), SVOffset + IncrementSize, 1230 ExtraVT, isVolatile, isNonTemporal, 1231 MinAlign(Alignment, IncrementSize)); 1232 1233 // Build a factor node to remember that this load is independent of the 1234 // other one. 1235 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1236 Hi.getValue(1)); 1237 1238 // Move the top bits to the right place. 1239 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1240 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1241 1242 // Join the hi and lo parts. 1243 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1244 } else { 1245 // Big endian - avoid unaligned loads. 1246 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1247 // Load the top RoundWidth bits. 1248 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1249 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1250 isNonTemporal, Alignment); 1251 1252 // Load the remaining ExtraWidth bits. 1253 IncrementSize = RoundWidth / 8; 1254 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1255 DAG.getIntPtrConstant(IncrementSize)); 1256 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1257 Node->getValueType(0), Tmp1, Tmp2, 1258 LD->getSrcValue(), SVOffset + IncrementSize, 1259 ExtraVT, isVolatile, isNonTemporal, 1260 MinAlign(Alignment, IncrementSize)); 1261 1262 // Build a factor node to remember that this load is independent of the 1263 // other one. 1264 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1265 Hi.getValue(1)); 1266 1267 // Move the top bits to the right place. 1268 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1269 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1270 1271 // Join the hi and lo parts. 1272 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1273 } 1274 1275 Tmp1 = LegalizeOp(Result); 1276 Tmp2 = LegalizeOp(Ch); 1277 } else { 1278 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1279 default: assert(0 && "This action is not supported yet!"); 1280 case TargetLowering::Custom: 1281 isCustom = true; 1282 // FALLTHROUGH 1283 case TargetLowering::Legal: 1284 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1285 Tmp1, Tmp2, LD->getOffset()), 1286 Result.getResNo()); 1287 Tmp1 = Result.getValue(0); 1288 Tmp2 = Result.getValue(1); 1289 1290 if (isCustom) { 1291 Tmp3 = TLI.LowerOperation(Result, DAG); 1292 if (Tmp3.getNode()) { 1293 Tmp1 = LegalizeOp(Tmp3); 1294 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1295 } 1296 } else { 1297 // If this is an unaligned load and the target doesn't support it, 1298 // expand it. 1299 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1300 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1301 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1302 if (LD->getAlignment() < ABIAlignment){ 1303 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1304 DAG, TLI); 1305 Tmp1 = Result.getOperand(0); 1306 Tmp2 = Result.getOperand(1); 1307 Tmp1 = LegalizeOp(Tmp1); 1308 Tmp2 = LegalizeOp(Tmp2); 1309 } 1310 } 1311 } 1312 break; 1313 case TargetLowering::Expand: 1314 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1315 // f128 = EXTLOAD {f32,f64} too 1316 if ((SrcVT == MVT::f32 && (Node->getValueType(0) == MVT::f64 || 1317 Node->getValueType(0) == MVT::f128)) || 1318 (SrcVT == MVT::f64 && Node->getValueType(0) == MVT::f128)) { 1319 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1320 LD->getSrcValueOffset(), 1321 LD->isVolatile(), LD->isNonTemporal(), 1322 LD->getAlignment()); 1323 Result = DAG.getNode(ISD::FP_EXTEND, dl, 1324 Node->getValueType(0), Load); 1325 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1326 Tmp2 = LegalizeOp(Load.getValue(1)); 1327 break; 1328 } 1329 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1330 // Turn the unsupported load into an EXTLOAD followed by an explicit 1331 // zero/sign extend inreg. 1332 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1333 Tmp1, Tmp2, LD->getSrcValue(), 1334 LD->getSrcValueOffset(), SrcVT, 1335 LD->isVolatile(), LD->isNonTemporal(), 1336 LD->getAlignment()); 1337 SDValue ValRes; 1338 if (ExtType == ISD::SEXTLOAD) 1339 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1340 Result.getValueType(), 1341 Result, DAG.getValueType(SrcVT)); 1342 else 1343 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1344 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1345 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1346 break; 1347 } 1348 } 1349 1350 // Since loads produce two values, make sure to remember that we legalized 1351 // both of them. 1352 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1353 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1354 return Op.getResNo() ? Tmp2 : Tmp1; 1355 } 1356 } 1357 case ISD::STORE: { 1358 StoreSDNode *ST = cast<StoreSDNode>(Node); 1359 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1360 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1361 int SVOffset = ST->getSrcValueOffset(); 1362 unsigned Alignment = ST->getAlignment(); 1363 bool isVolatile = ST->isVolatile(); 1364 bool isNonTemporal = ST->isNonTemporal(); 1365 1366 if (!ST->isTruncatingStore()) { 1367 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1368 Result = SDValue(OptStore, 0); 1369 break; 1370 } 1371 1372 { 1373 Tmp3 = LegalizeOp(ST->getValue()); 1374 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1375 Tmp1, Tmp3, Tmp2, 1376 ST->getOffset()), 1377 Result.getResNo()); 1378 1379 EVT VT = Tmp3.getValueType(); 1380 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1381 default: assert(0 && "This action is not supported yet!"); 1382 case TargetLowering::Legal: 1383 // If this is an unaligned store and the target doesn't support it, 1384 // expand it. 1385 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1386 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1387 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1388 if (ST->getAlignment() < ABIAlignment) 1389 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1390 DAG, TLI); 1391 } 1392 break; 1393 case TargetLowering::Custom: 1394 Tmp1 = TLI.LowerOperation(Result, DAG); 1395 if (Tmp1.getNode()) Result = Tmp1; 1396 break; 1397 case TargetLowering::Promote: 1398 assert(VT.isVector() && "Unknown legal promote case!"); 1399 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1400 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1401 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1402 ST->getSrcValue(), SVOffset, isVolatile, 1403 isNonTemporal, Alignment); 1404 break; 1405 } 1406 break; 1407 } 1408 } else { 1409 Tmp3 = LegalizeOp(ST->getValue()); 1410 1411 EVT StVT = ST->getMemoryVT(); 1412 unsigned StWidth = StVT.getSizeInBits(); 1413 1414 if (StWidth != StVT.getStoreSizeInBits()) { 1415 // Promote to a byte-sized store with upper bits zero if not 1416 // storing an integral number of bytes. For example, promote 1417 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1418 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), 1419 StVT.getStoreSizeInBits()); 1420 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1421 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1422 SVOffset, NVT, isVolatile, isNonTemporal, 1423 Alignment); 1424 } else if (StWidth & (StWidth - 1)) { 1425 // If not storing a power-of-2 number of bits, expand as two stores. 1426 assert(!StVT.isVector() && "Unsupported truncstore!"); 1427 unsigned RoundWidth = 1 << Log2_32(StWidth); 1428 assert(RoundWidth < StWidth); 1429 unsigned ExtraWidth = StWidth - RoundWidth; 1430 assert(ExtraWidth < RoundWidth); 1431 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1432 "Store size not an integral number of bytes!"); 1433 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1434 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1435 SDValue Lo, Hi; 1436 unsigned IncrementSize; 1437 1438 if (TLI.isLittleEndian()) { 1439 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1440 // Store the bottom RoundWidth bits. 1441 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1442 SVOffset, RoundVT, 1443 isVolatile, isNonTemporal, Alignment); 1444 1445 // Store the remaining ExtraWidth bits. 1446 IncrementSize = RoundWidth / 8; 1447 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1448 DAG.getIntPtrConstant(IncrementSize)); 1449 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1450 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1451 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1452 SVOffset + IncrementSize, ExtraVT, isVolatile, 1453 isNonTemporal, 1454 MinAlign(Alignment, IncrementSize)); 1455 } else { 1456 // Big endian - avoid unaligned stores. 1457 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1458 // Store the top RoundWidth bits. 1459 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1460 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1461 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1462 SVOffset, RoundVT, isVolatile, isNonTemporal, 1463 Alignment); 1464 1465 // Store the remaining ExtraWidth bits. 1466 IncrementSize = RoundWidth / 8; 1467 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1468 DAG.getIntPtrConstant(IncrementSize)); 1469 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1470 SVOffset + IncrementSize, ExtraVT, isVolatile, 1471 isNonTemporal, 1472 MinAlign(Alignment, IncrementSize)); 1473 } 1474 1475 // The order of the stores doesn't matter. 1476 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1477 } else { 1478 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1479 Tmp2 != ST->getBasePtr()) 1480 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1481 Tmp1, Tmp3, Tmp2, 1482 ST->getOffset()), 1483 Result.getResNo()); 1484 1485 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1486 default: assert(0 && "This action is not supported yet!"); 1487 case TargetLowering::Legal: 1488 // If this is an unaligned store and the target doesn't support it, 1489 // expand it. 1490 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1491 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1492 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1493 if (ST->getAlignment() < ABIAlignment) 1494 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1495 DAG, TLI); 1496 } 1497 break; 1498 case TargetLowering::Custom: 1499 Result = TLI.LowerOperation(Result, DAG); 1500 break; 1501 case Expand: 1502 // TRUNCSTORE:i16 i32 -> STORE i16 1503 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1504 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1505 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1506 SVOffset, isVolatile, isNonTemporal, 1507 Alignment); 1508 break; 1509 } 1510 } 1511 } 1512 break; 1513 } 1514 } 1515 assert(Result.getValueType() == Op.getValueType() && 1516 "Bad legalization!"); 1517 1518 // Make sure that the generated code is itself legal. 1519 if (Result != Op) 1520 Result = LegalizeOp(Result); 1521 1522 // Note that LegalizeOp may be reentered even from single-use nodes, which 1523 // means that we always must cache transformed nodes. 1524 AddLegalizedOperand(Op, Result); 1525 return Result; 1526} 1527 1528SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1529 SDValue Vec = Op.getOperand(0); 1530 SDValue Idx = Op.getOperand(1); 1531 DebugLoc dl = Op.getDebugLoc(); 1532 // Store the value to a temporary stack slot, then LOAD the returned part. 1533 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1534 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0, 1535 false, false, 0); 1536 1537 // Add the offset to the index. 1538 unsigned EltSize = 1539 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1540 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1541 DAG.getConstant(EltSize, Idx.getValueType())); 1542 1543 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1544 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1545 else 1546 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1547 1548 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1549 1550 if (Op.getValueType().isVector()) 1551 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0, 1552 false, false, 0); 1553 else 1554 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1555 NULL, 0, Vec.getValueType().getVectorElementType(), 1556 false, false, 0); 1557} 1558 1559SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1560 // We can't handle this case efficiently. Allocate a sufficiently 1561 // aligned object on the stack, store each element into it, then load 1562 // the result as a vector. 1563 // Create the stack frame object. 1564 EVT VT = Node->getValueType(0); 1565 EVT EltVT = VT.getVectorElementType(); 1566 DebugLoc dl = Node->getDebugLoc(); 1567 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1568 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1569 const Value *SV = PseudoSourceValue::getFixedStack(FI); 1570 1571 // Emit a store of each element to the stack slot. 1572 SmallVector<SDValue, 8> Stores; 1573 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1574 // Store (in the right endianness) the elements to memory. 1575 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1576 // Ignore undef elements. 1577 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1578 1579 unsigned Offset = TypeByteSize*i; 1580 1581 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1582 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1583 1584 // If the destination vector element type is narrower than the source 1585 // element type, only store the bits necessary. 1586 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1587 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1588 Node->getOperand(i), Idx, SV, Offset, 1589 EltVT, false, false, 0)); 1590 } else 1591 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1592 Node->getOperand(i), Idx, SV, Offset, 1593 false, false, 0)); 1594 } 1595 1596 SDValue StoreChain; 1597 if (!Stores.empty()) // Not all undef elements? 1598 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1599 &Stores[0], Stores.size()); 1600 else 1601 StoreChain = DAG.getEntryNode(); 1602 1603 // Result is a load from the stack slot. 1604 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0, false, false, 0); 1605} 1606 1607SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1608 DebugLoc dl = Node->getDebugLoc(); 1609 SDValue Tmp1 = Node->getOperand(0); 1610 SDValue Tmp2 = Node->getOperand(1); 1611 1612 // Get the sign bit of the RHS. First obtain a value that has the same 1613 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1614 SDValue SignBit; 1615 EVT FloatVT = Tmp2.getValueType(); 1616 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1617 if (isTypeLegal(IVT)) { 1618 // Convert to an integer with the same sign bit. 1619 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1620 } else { 1621 // Store the float to memory, then load the sign part out as an integer. 1622 MVT LoadTy = TLI.getPointerTy(); 1623 // First create a temporary that is aligned for both the load and store. 1624 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1625 // Then store the float to it. 1626 SDValue Ch = 1627 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL, 0, 1628 false, false, 0); 1629 if (TLI.isBigEndian()) { 1630 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1631 // Load out a legal integer with the same sign bit as the float. 1632 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, NULL, 0, false, false, 0); 1633 } else { // Little endian 1634 SDValue LoadPtr = StackPtr; 1635 // The float may be wider than the integer we are going to load. Advance 1636 // the pointer so that the loaded integer will contain the sign bit. 1637 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1638 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1639 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1640 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1641 // Load a legal integer containing the sign bit. 1642 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, NULL, 0, false, false, 0); 1643 // Move the sign bit to the top bit of the loaded integer. 1644 unsigned BitShift = LoadTy.getSizeInBits() - 1645 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1646 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1647 if (BitShift) 1648 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1649 DAG.getConstant(BitShift,TLI.getShiftAmountTy())); 1650 } 1651 } 1652 // Now get the sign bit proper, by seeing whether the value is negative. 1653 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1654 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1655 ISD::SETLT); 1656 // Get the absolute value of the result. 1657 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1658 // Select between the nabs and abs value based on the sign bit of 1659 // the input. 1660 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1661 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1662 AbsVal); 1663} 1664 1665void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1666 SmallVectorImpl<SDValue> &Results) { 1667 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1668 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1669 " not tell us which reg is the stack pointer!"); 1670 DebugLoc dl = Node->getDebugLoc(); 1671 EVT VT = Node->getValueType(0); 1672 SDValue Tmp1 = SDValue(Node, 0); 1673 SDValue Tmp2 = SDValue(Node, 1); 1674 SDValue Tmp3 = Node->getOperand(2); 1675 SDValue Chain = Tmp1.getOperand(0); 1676 1677 // Chain the dynamic stack allocation so that it doesn't modify the stack 1678 // pointer when other instructions are using the stack. 1679 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1680 1681 SDValue Size = Tmp2.getOperand(1); 1682 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1683 Chain = SP.getValue(1); 1684 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1685 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); 1686 if (Align > StackAlign) 1687 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1688 DAG.getConstant(-(uint64_t)Align, VT)); 1689 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1690 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1691 1692 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1693 DAG.getIntPtrConstant(0, true), SDValue()); 1694 1695 Results.push_back(Tmp1); 1696 Results.push_back(Tmp2); 1697} 1698 1699/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1700/// condition code CC on the current target. This routine expands SETCC with 1701/// illegal condition code into AND / OR of multiple SETCC values. 1702void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1703 SDValue &LHS, SDValue &RHS, 1704 SDValue &CC, 1705 DebugLoc dl) { 1706 EVT OpVT = LHS.getValueType(); 1707 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1708 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1709 default: assert(0 && "Unknown condition code action!"); 1710 case TargetLowering::Legal: 1711 // Nothing to do. 1712 break; 1713 case TargetLowering::Expand: { 1714 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1715 unsigned Opc = 0; 1716 switch (CCCode) { 1717 default: assert(0 && "Don't know how to expand this condition!"); 1718 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1719 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1720 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1721 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1722 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1723 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1724 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1725 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1726 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1727 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1728 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1729 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1730 // FIXME: Implement more expansions. 1731 } 1732 1733 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1734 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1735 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1736 RHS = SDValue(); 1737 CC = SDValue(); 1738 break; 1739 } 1740 } 1741} 1742 1743/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1744/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1745/// a load from the stack slot to DestVT, extending it if needed. 1746/// The resultant code need not be legal. 1747SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1748 EVT SlotVT, 1749 EVT DestVT, 1750 DebugLoc dl) { 1751 // Create the stack frame object. 1752 unsigned SrcAlign = 1753 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1754 getTypeForEVT(*DAG.getContext())); 1755 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1756 1757 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1758 int SPFI = StackPtrFI->getIndex(); 1759 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1760 1761 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1762 unsigned SlotSize = SlotVT.getSizeInBits(); 1763 unsigned DestSize = DestVT.getSizeInBits(); 1764 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); 1765 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType); 1766 1767 // Emit a store to the stack slot. Use a truncstore if the input value is 1768 // later than DestVT. 1769 SDValue Store; 1770 1771 if (SrcSize > SlotSize) 1772 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1773 SV, 0, SlotVT, false, false, SrcAlign); 1774 else { 1775 assert(SrcSize == SlotSize && "Invalid store"); 1776 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1777 SV, 0, false, false, SrcAlign); 1778 } 1779 1780 // Result is a load from the stack slot. 1781 if (SlotSize == DestSize) 1782 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, false, 1783 DestAlign); 1784 1785 assert(SlotSize < DestSize && "Unknown extension!"); 1786 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, 1787 false, false, DestAlign); 1788} 1789 1790SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1791 DebugLoc dl = Node->getDebugLoc(); 1792 // Create a vector sized/aligned stack slot, store the value to element #0, 1793 // then load the whole vector back out. 1794 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1795 1796 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1797 int SPFI = StackPtrFI->getIndex(); 1798 1799 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1800 StackPtr, 1801 PseudoSourceValue::getFixedStack(SPFI), 0, 1802 Node->getValueType(0).getVectorElementType(), 1803 false, false, 0); 1804 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1805 PseudoSourceValue::getFixedStack(SPFI), 0, 1806 false, false, 0); 1807} 1808 1809 1810/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1811/// support the operation, but do support the resultant vector type. 1812SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1813 unsigned NumElems = Node->getNumOperands(); 1814 SDValue Value1, Value2; 1815 DebugLoc dl = Node->getDebugLoc(); 1816 EVT VT = Node->getValueType(0); 1817 EVT OpVT = Node->getOperand(0).getValueType(); 1818 EVT EltVT = VT.getVectorElementType(); 1819 1820 // If the only non-undef value is the low element, turn this into a 1821 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1822 bool isOnlyLowElement = true; 1823 bool MoreThanTwoValues = false; 1824 bool isConstant = true; 1825 for (unsigned i = 0; i < NumElems; ++i) { 1826 SDValue V = Node->getOperand(i); 1827 if (V.getOpcode() == ISD::UNDEF) 1828 continue; 1829 if (i > 0) 1830 isOnlyLowElement = false; 1831 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1832 isConstant = false; 1833 1834 if (!Value1.getNode()) { 1835 Value1 = V; 1836 } else if (!Value2.getNode()) { 1837 if (V != Value1) 1838 Value2 = V; 1839 } else if (V != Value1 && V != Value2) { 1840 MoreThanTwoValues = true; 1841 } 1842 } 1843 1844 if (!Value1.getNode()) 1845 return DAG.getUNDEF(VT); 1846 1847 if (isOnlyLowElement) 1848 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1849 1850 // If all elements are constants, create a load from the constant pool. 1851 if (isConstant) { 1852 std::vector<Constant*> CV; 1853 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1854 if (ConstantFPSDNode *V = 1855 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1856 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1857 } else if (ConstantSDNode *V = 1858 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1859 if (OpVT==EltVT) 1860 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1861 else { 1862 // If OpVT and EltVT don't match, EltVT is not legal and the 1863 // element values have been promoted/truncated earlier. Undo this; 1864 // we don't want a v16i8 to become a v16i32 for example. 1865 const ConstantInt *CI = V->getConstantIntValue(); 1866 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1867 CI->getZExtValue())); 1868 } 1869 } else { 1870 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1871 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1872 CV.push_back(UndefValue::get(OpNTy)); 1873 } 1874 } 1875 Constant *CP = ConstantVector::get(CV); 1876 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1877 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1878 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1879 PseudoSourceValue::getConstantPool(), 0, 1880 false, false, Alignment); 1881 } 1882 1883 if (!MoreThanTwoValues) { 1884 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1885 for (unsigned i = 0; i < NumElems; ++i) { 1886 SDValue V = Node->getOperand(i); 1887 if (V.getOpcode() == ISD::UNDEF) 1888 continue; 1889 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1890 } 1891 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1892 // Get the splatted value into the low element of a vector register. 1893 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1894 SDValue Vec2; 1895 if (Value2.getNode()) 1896 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1897 else 1898 Vec2 = DAG.getUNDEF(VT); 1899 1900 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1901 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1902 } 1903 } 1904 1905 // Otherwise, we can't handle this case efficiently. 1906 return ExpandVectorBuildThroughStack(Node); 1907} 1908 1909// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1910// does not fit into a register, return the lo part and set the hi part to the 1911// by-reg argument. If it does fit into a single register, return the result 1912// and leave the Hi part unset. 1913SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1914 bool isSigned) { 1915 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1916 // The input chain to this libcall is the entry node of the function. 1917 // Legalizing the call will automatically add the previous call to the 1918 // dependence. 1919 SDValue InChain = DAG.getEntryNode(); 1920 1921 TargetLowering::ArgListTy Args; 1922 TargetLowering::ArgListEntry Entry; 1923 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1924 EVT ArgVT = Node->getOperand(i).getValueType(); 1925 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1926 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1927 Entry.isSExt = isSigned; 1928 Entry.isZExt = !isSigned; 1929 Args.push_back(Entry); 1930 } 1931 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1932 TLI.getPointerTy()); 1933 1934 // Splice the libcall in wherever FindInputOutputChains tells us to. 1935 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1936 std::pair<SDValue, SDValue> CallInfo = 1937 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1938 0, TLI.getLibcallCallingConv(LC), false, 1939 /*isReturnValueUsed=*/true, 1940 Callee, Args, DAG, Node->getDebugLoc()); 1941 1942 // Legalize the call sequence, starting with the chain. This will advance 1943 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1944 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1945 LegalizeOp(CallInfo.second); 1946 return CallInfo.first; 1947} 1948 1949// ExpandChainLibCall - Expand a node into a call to a libcall. Similar to 1950// ExpandLibCall except that the first operand is the in-chain. 1951std::pair<SDValue, SDValue> 1952SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC, 1953 SDNode *Node, 1954 bool isSigned) { 1955 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1956 SDValue InChain = Node->getOperand(0); 1957 1958 TargetLowering::ArgListTy Args; 1959 TargetLowering::ArgListEntry Entry; 1960 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) { 1961 EVT ArgVT = Node->getOperand(i).getValueType(); 1962 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1963 Entry.Node = Node->getOperand(i); 1964 Entry.Ty = ArgTy; 1965 Entry.isSExt = isSigned; 1966 Entry.isZExt = !isSigned; 1967 Args.push_back(Entry); 1968 } 1969 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1970 TLI.getPointerTy()); 1971 1972 // Splice the libcall in wherever FindInputOutputChains tells us to. 1973 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1974 std::pair<SDValue, SDValue> CallInfo = 1975 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1976 0, TLI.getLibcallCallingConv(LC), false, 1977 /*isReturnValueUsed=*/true, 1978 Callee, Args, DAG, Node->getDebugLoc()); 1979 1980 // Legalize the call sequence, starting with the chain. This will advance 1981 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1982 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1983 LegalizeOp(CallInfo.second); 1984 return CallInfo; 1985} 1986 1987SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1988 RTLIB::Libcall Call_F32, 1989 RTLIB::Libcall Call_F64, 1990 RTLIB::Libcall Call_F80, 1991 RTLIB::Libcall Call_PPCF128) { 1992 RTLIB::Libcall LC; 1993 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1994 default: assert(0 && "Unexpected request for libcall!"); 1995 case MVT::f32: LC = Call_F32; break; 1996 case MVT::f64: LC = Call_F64; break; 1997 case MVT::f80: LC = Call_F80; break; 1998 case MVT::ppcf128: LC = Call_PPCF128; break; 1999 } 2000 return ExpandLibCall(LC, Node, false); 2001} 2002 2003SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 2004 RTLIB::Libcall Call_I8, 2005 RTLIB::Libcall Call_I16, 2006 RTLIB::Libcall Call_I32, 2007 RTLIB::Libcall Call_I64, 2008 RTLIB::Libcall Call_I128) { 2009 RTLIB::Libcall LC; 2010 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2011 default: assert(0 && "Unexpected request for libcall!"); 2012 case MVT::i8: LC = Call_I8; break; 2013 case MVT::i16: LC = Call_I16; break; 2014 case MVT::i32: LC = Call_I32; break; 2015 case MVT::i64: LC = Call_I64; break; 2016 case MVT::i128: LC = Call_I128; break; 2017 } 2018 return ExpandLibCall(LC, Node, isSigned); 2019} 2020 2021/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 2022/// INT_TO_FP operation of the specified operand when the target requests that 2023/// we expand it. At this point, we know that the result and operand types are 2024/// legal for the target. 2025SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 2026 SDValue Op0, 2027 EVT DestVT, 2028 DebugLoc dl) { 2029 if (Op0.getValueType() == MVT::i32) { 2030 // simple 32-bit [signed|unsigned] integer to float/double expansion 2031 2032 // Get the stack frame index of a 8 byte buffer. 2033 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 2034 2035 // word offset constant for Hi/Lo address computation 2036 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 2037 // set up Hi and Lo (into buffer) address based on endian 2038 SDValue Hi = StackSlot; 2039 SDValue Lo = DAG.getNode(ISD::ADD, dl, 2040 TLI.getPointerTy(), StackSlot, WordOff); 2041 if (TLI.isLittleEndian()) 2042 std::swap(Hi, Lo); 2043 2044 // if signed map to unsigned space 2045 SDValue Op0Mapped; 2046 if (isSigned) { 2047 // constant used to invert sign bit (signed to unsigned mapping) 2048 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 2049 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 2050 } else { 2051 Op0Mapped = Op0; 2052 } 2053 // store the lo of the constructed double - based on integer input 2054 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 2055 Op0Mapped, Lo, NULL, 0, 2056 false, false, 0); 2057 // initial hi portion of constructed double 2058 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2059 // store the hi of the constructed double - biased exponent 2060 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0, 2061 false, false, 0); 2062 // load the constructed double 2063 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0, 2064 false, false, 0); 2065 // FP constant to bias correct the final result 2066 SDValue Bias = DAG.getConstantFP(isSigned ? 2067 BitsToDouble(0x4330000080000000ULL) : 2068 BitsToDouble(0x4330000000000000ULL), 2069 MVT::f64); 2070 // subtract the bias 2071 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2072 // final result 2073 SDValue Result; 2074 // handle final rounding 2075 if (DestVT == MVT::f64) { 2076 // do nothing 2077 Result = Sub; 2078 } else if (DestVT.bitsLT(MVT::f64)) { 2079 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2080 DAG.getIntPtrConstant(0)); 2081 } else if (DestVT.bitsGT(MVT::f64)) { 2082 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2083 } 2084 return Result; 2085 } 2086 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2087 // Code below here assumes !isSigned without checking again. 2088 2089 // Implementation of unsigned i64 to f64 following the algorithm in 2090 // __floatundidf in compiler_rt. This implementation has the advantage 2091 // of performing rounding correctly, both in the default rounding mode 2092 // and in all alternate rounding modes. 2093 // TODO: Generalize this for use with other types. 2094 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2095 SDValue TwoP52 = 2096 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2097 SDValue TwoP84PlusTwoP52 = 2098 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2099 SDValue TwoP84 = 2100 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2101 2102 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2103 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2104 DAG.getConstant(32, MVT::i64)); 2105 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2106 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2107 SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr); 2108 SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr); 2109 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, TwoP84PlusTwoP52); 2110 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2111 } 2112 2113 // Implementation of unsigned i64 to f32. This implementation has the 2114 // advantage of performing rounding correctly. 2115 // TODO: Generalize this for use with other types. 2116 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { 2117 EVT SHVT = TLI.getShiftAmountTy(); 2118 2119 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2120 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64)); 2121 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, 2122 DAG.getConstant(UINT64_C(0x800), MVT::i64)); 2123 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2124 DAG.getConstant(UINT64_C(0x7ff), MVT::i64)); 2125 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2126 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); 2127 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0); 2128 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2129 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64), 2130 ISD::SETUGE); 2131 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0); 2132 2133 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2134 DAG.getConstant(32, SHVT)); 2135 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); 2136 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); 2137 SDValue TwoP32 = 2138 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64); 2139 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); 2140 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); 2141 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); 2142 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); 2143 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, 2144 DAG.getIntPtrConstant(0)); 2145 2146 } 2147 2148 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2149 2150 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2151 Op0, DAG.getConstant(0, Op0.getValueType()), 2152 ISD::SETLT); 2153 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2154 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2155 SignSet, Four, Zero); 2156 2157 // If the sign bit of the integer is set, the large number will be treated 2158 // as a negative number. To counteract this, the dynamic code adds an 2159 // offset depending on the data type. 2160 uint64_t FF; 2161 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2162 default: assert(0 && "Unsupported integer type!"); 2163 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2164 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2165 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2166 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2167 } 2168 if (TLI.isLittleEndian()) FF <<= 32; 2169 Constant *FudgeFactor = ConstantInt::get( 2170 Type::getInt64Ty(*DAG.getContext()), FF); 2171 2172 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2173 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2174 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2175 Alignment = std::min(Alignment, 4u); 2176 SDValue FudgeInReg; 2177 if (DestVT == MVT::f32) 2178 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2179 PseudoSourceValue::getConstantPool(), 0, 2180 false, false, Alignment); 2181 else { 2182 FudgeInReg = 2183 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2184 DAG.getEntryNode(), CPIdx, 2185 PseudoSourceValue::getConstantPool(), 0, 2186 MVT::f32, false, false, Alignment)); 2187 } 2188 2189 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2190} 2191 2192/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2193/// *INT_TO_FP operation of the specified operand when the target requests that 2194/// we promote it. At this point, we know that the result and operand types are 2195/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2196/// operation that takes a larger input. 2197SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2198 EVT DestVT, 2199 bool isSigned, 2200 DebugLoc dl) { 2201 // First step, figure out the appropriate *INT_TO_FP operation to use. 2202 EVT NewInTy = LegalOp.getValueType(); 2203 2204 unsigned OpToUse = 0; 2205 2206 // Scan for the appropriate larger type to use. 2207 while (1) { 2208 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2209 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2210 2211 // If the target supports SINT_TO_FP of this type, use it. 2212 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2213 OpToUse = ISD::SINT_TO_FP; 2214 break; 2215 } 2216 if (isSigned) continue; 2217 2218 // If the target supports UINT_TO_FP of this type, use it. 2219 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2220 OpToUse = ISD::UINT_TO_FP; 2221 break; 2222 } 2223 2224 // Otherwise, try a larger type. 2225 } 2226 2227 // Okay, we found the operation and type to use. Zero extend our input to the 2228 // desired type then run the operation on it. 2229 return DAG.getNode(OpToUse, dl, DestVT, 2230 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2231 dl, NewInTy, LegalOp)); 2232} 2233 2234/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2235/// FP_TO_*INT operation of the specified operand when the target requests that 2236/// we promote it. At this point, we know that the result and operand types are 2237/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2238/// operation that returns a larger result. 2239SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2240 EVT DestVT, 2241 bool isSigned, 2242 DebugLoc dl) { 2243 // First step, figure out the appropriate FP_TO*INT operation to use. 2244 EVT NewOutTy = DestVT; 2245 2246 unsigned OpToUse = 0; 2247 2248 // Scan for the appropriate larger type to use. 2249 while (1) { 2250 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2251 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2252 2253 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2254 OpToUse = ISD::FP_TO_SINT; 2255 break; 2256 } 2257 2258 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2259 OpToUse = ISD::FP_TO_UINT; 2260 break; 2261 } 2262 2263 // Otherwise, try a larger type. 2264 } 2265 2266 2267 // Okay, we found the operation and type to use. 2268 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2269 2270 // Truncate the result of the extended FP_TO_*INT operation to the desired 2271 // size. 2272 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2273} 2274 2275/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2276/// 2277SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2278 EVT VT = Op.getValueType(); 2279 EVT SHVT = TLI.getShiftAmountTy(); 2280 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2281 switch (VT.getSimpleVT().SimpleTy) { 2282 default: assert(0 && "Unhandled Expand type in BSWAP!"); 2283 case MVT::i16: 2284 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2285 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2286 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2287 case MVT::i32: 2288 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2289 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2290 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2291 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2292 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2293 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2294 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2295 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2296 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2297 case MVT::i64: 2298 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2299 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2300 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2301 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2302 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2303 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2304 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2305 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2306 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2307 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2308 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2309 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2310 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2311 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2312 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2313 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2314 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2315 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2316 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2317 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2318 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2319 } 2320} 2321 2322/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2323/// 2324SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2325 DebugLoc dl) { 2326 switch (Opc) { 2327 default: assert(0 && "Cannot expand this yet!"); 2328 case ISD::CTPOP: { 2329 static const uint64_t mask[6] = { 2330 0x5555555555555555ULL, 0x3333333333333333ULL, 2331 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2332 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2333 }; 2334 EVT VT = Op.getValueType(); 2335 EVT ShVT = TLI.getShiftAmountTy(); 2336 unsigned len = VT.getSizeInBits(); 2337 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2338 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2339 unsigned EltSize = VT.isVector() ? 2340 VT.getVectorElementType().getSizeInBits() : len; 2341 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2342 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2343 Op = DAG.getNode(ISD::ADD, dl, VT, 2344 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2345 DAG.getNode(ISD::AND, dl, VT, 2346 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2347 Tmp2)); 2348 } 2349 return Op; 2350 } 2351 case ISD::CTLZ: { 2352 // for now, we do this: 2353 // x = x | (x >> 1); 2354 // x = x | (x >> 2); 2355 // ... 2356 // x = x | (x >>16); 2357 // x = x | (x >>32); // for 64-bit input 2358 // return popcount(~x); 2359 // 2360 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2361 EVT VT = Op.getValueType(); 2362 EVT ShVT = TLI.getShiftAmountTy(); 2363 unsigned len = VT.getSizeInBits(); 2364 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2365 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2366 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2367 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2368 } 2369 Op = DAG.getNOT(dl, Op, VT); 2370 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2371 } 2372 case ISD::CTTZ: { 2373 // for now, we use: { return popcount(~x & (x - 1)); } 2374 // unless the target has ctlz but not ctpop, in which case we use: 2375 // { return 32 - nlz(~x & (x-1)); } 2376 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2377 EVT VT = Op.getValueType(); 2378 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2379 DAG.getNOT(dl, Op, VT), 2380 DAG.getNode(ISD::SUB, dl, VT, Op, 2381 DAG.getConstant(1, VT))); 2382 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2383 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2384 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2385 return DAG.getNode(ISD::SUB, dl, VT, 2386 DAG.getConstant(VT.getSizeInBits(), VT), 2387 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2388 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2389 } 2390 } 2391} 2392 2393std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) { 2394 unsigned Opc = Node->getOpcode(); 2395 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 2396 RTLIB::Libcall LC; 2397 2398 switch (Opc) { 2399 default: 2400 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 2401 break; 2402 case ISD::ATOMIC_CMP_SWAP: 2403 switch (VT.SimpleTy) { 2404 default: llvm_unreachable("Unexpected value type for atomic!"); 2405 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 2406 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 2407 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 2408 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 2409 } 2410 break; 2411 case ISD::ATOMIC_LOAD_ADD: 2412 switch (VT.SimpleTy) { 2413 default: llvm_unreachable("Unexpected value type for atomic!"); 2414 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 2415 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 2416 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 2417 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 2418 } 2419 break; 2420 case ISD::ATOMIC_LOAD_SUB: 2421 switch (VT.SimpleTy) { 2422 default: llvm_unreachable("Unexpected value type for atomic!"); 2423 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 2424 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 2425 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 2426 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 2427 } 2428 break; 2429 case ISD::ATOMIC_LOAD_AND: 2430 switch (VT.SimpleTy) { 2431 default: llvm_unreachable("Unexpected value type for atomic!"); 2432 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 2433 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 2434 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 2435 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 2436 } 2437 break; 2438 case ISD::ATOMIC_LOAD_OR: 2439 switch (VT.SimpleTy) { 2440 default: llvm_unreachable("Unexpected value type for atomic!"); 2441 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 2442 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 2443 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 2444 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 2445 } 2446 break; 2447 case ISD::ATOMIC_LOAD_XOR: 2448 switch (VT.SimpleTy) { 2449 default: llvm_unreachable("Unexpected value type for atomic!"); 2450 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 2451 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 2452 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 2453 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 2454 } 2455 break; 2456 case ISD::ATOMIC_LOAD_NAND: 2457 switch (VT.SimpleTy) { 2458 default: llvm_unreachable("Unexpected value type for atomic!"); 2459 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 2460 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 2461 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 2462 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 2463 } 2464 break; 2465 } 2466 2467 return ExpandChainLibCall(LC, Node, false); 2468} 2469 2470void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2471 SmallVectorImpl<SDValue> &Results) { 2472 DebugLoc dl = Node->getDebugLoc(); 2473 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2474 switch (Node->getOpcode()) { 2475 case ISD::CTPOP: 2476 case ISD::CTLZ: 2477 case ISD::CTTZ: 2478 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2479 Results.push_back(Tmp1); 2480 break; 2481 case ISD::BSWAP: 2482 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2483 break; 2484 case ISD::FRAMEADDR: 2485 case ISD::RETURNADDR: 2486 case ISD::FRAME_TO_ARGS_OFFSET: 2487 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2488 break; 2489 case ISD::FLT_ROUNDS_: 2490 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2491 break; 2492 case ISD::EH_RETURN: 2493 case ISD::EH_LABEL: 2494 case ISD::PREFETCH: 2495 case ISD::VAEND: 2496 Results.push_back(Node->getOperand(0)); 2497 break; 2498 case ISD::MEMBARRIER: { 2499 // If the target didn't lower this, lower it to '__sync_synchronize()' call 2500 TargetLowering::ArgListTy Args; 2501 std::pair<SDValue, SDValue> CallResult = 2502 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2503 false, false, false, false, 0, CallingConv::C, false, 2504 /*isReturnValueUsed=*/true, 2505 DAG.getExternalSymbol("__sync_synchronize", 2506 TLI.getPointerTy()), 2507 Args, DAG, dl); 2508 Results.push_back(CallResult.second); 2509 break; 2510 } 2511 // By default, atomic intrinsics are marked Legal and lowered. Targets 2512 // which don't support them directly, however, may want libcalls, in which 2513 // case they mark them Expand, and we get here. 2514 // FIXME: Unimplemented for now. Add libcalls. 2515 case ISD::ATOMIC_SWAP: 2516 case ISD::ATOMIC_LOAD_ADD: 2517 case ISD::ATOMIC_LOAD_SUB: 2518 case ISD::ATOMIC_LOAD_AND: 2519 case ISD::ATOMIC_LOAD_OR: 2520 case ISD::ATOMIC_LOAD_XOR: 2521 case ISD::ATOMIC_LOAD_NAND: 2522 case ISD::ATOMIC_LOAD_MIN: 2523 case ISD::ATOMIC_LOAD_MAX: 2524 case ISD::ATOMIC_LOAD_UMIN: 2525 case ISD::ATOMIC_LOAD_UMAX: 2526 case ISD::ATOMIC_CMP_SWAP: { 2527 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node); 2528 Results.push_back(Tmp.first); 2529 Results.push_back(Tmp.second); 2530 break; 2531 } 2532 case ISD::DYNAMIC_STACKALLOC: 2533 ExpandDYNAMIC_STACKALLOC(Node, Results); 2534 break; 2535 case ISD::MERGE_VALUES: 2536 for (unsigned i = 0; i < Node->getNumValues(); i++) 2537 Results.push_back(Node->getOperand(i)); 2538 break; 2539 case ISD::UNDEF: { 2540 EVT VT = Node->getValueType(0); 2541 if (VT.isInteger()) 2542 Results.push_back(DAG.getConstant(0, VT)); 2543 else { 2544 assert(VT.isFloatingPoint() && "Unknown value type!"); 2545 Results.push_back(DAG.getConstantFP(0, VT)); 2546 } 2547 break; 2548 } 2549 case ISD::TRAP: { 2550 // If this operation is not supported, lower it to 'abort()' call 2551 TargetLowering::ArgListTy Args; 2552 std::pair<SDValue, SDValue> CallResult = 2553 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2554 false, false, false, false, 0, CallingConv::C, false, 2555 /*isReturnValueUsed=*/true, 2556 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2557 Args, DAG, dl); 2558 Results.push_back(CallResult.second); 2559 break; 2560 } 2561 case ISD::FP_ROUND: 2562 case ISD::BIT_CONVERT: 2563 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2564 Node->getValueType(0), dl); 2565 Results.push_back(Tmp1); 2566 break; 2567 case ISD::FP_EXTEND: 2568 Tmp1 = EmitStackConvert(Node->getOperand(0), 2569 Node->getOperand(0).getValueType(), 2570 Node->getValueType(0), dl); 2571 Results.push_back(Tmp1); 2572 break; 2573 case ISD::SIGN_EXTEND_INREG: { 2574 // NOTE: we could fall back on load/store here too for targets without 2575 // SAR. However, it is doubtful that any exist. 2576 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2577 EVT VT = Node->getValueType(0); 2578 EVT ShiftAmountTy = TLI.getShiftAmountTy(); 2579 if (VT.isVector()) 2580 ShiftAmountTy = VT; 2581 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2582 ExtraVT.getScalarType().getSizeInBits(); 2583 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2584 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2585 Node->getOperand(0), ShiftCst); 2586 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2587 Results.push_back(Tmp1); 2588 break; 2589 } 2590 case ISD::FP_ROUND_INREG: { 2591 // The only way we can lower this is to turn it into a TRUNCSTORE, 2592 // EXTLOAD pair, targetting a temporary location (a stack slot). 2593 2594 // NOTE: there is a choice here between constantly creating new stack 2595 // slots and always reusing the same one. We currently always create 2596 // new ones, as reuse may inhibit scheduling. 2597 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2598 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2599 Node->getValueType(0), dl); 2600 Results.push_back(Tmp1); 2601 break; 2602 } 2603 case ISD::SINT_TO_FP: 2604 case ISD::UINT_TO_FP: 2605 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2606 Node->getOperand(0), Node->getValueType(0), dl); 2607 Results.push_back(Tmp1); 2608 break; 2609 case ISD::FP_TO_UINT: { 2610 SDValue True, False; 2611 EVT VT = Node->getOperand(0).getValueType(); 2612 EVT NVT = Node->getValueType(0); 2613 const uint64_t zero[] = {0, 0}; 2614 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2615 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2616 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2617 Tmp1 = DAG.getConstantFP(apf, VT); 2618 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2619 Node->getOperand(0), 2620 Tmp1, ISD::SETLT); 2621 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2622 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2623 DAG.getNode(ISD::FSUB, dl, VT, 2624 Node->getOperand(0), Tmp1)); 2625 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2626 DAG.getConstant(x, NVT)); 2627 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2628 Results.push_back(Tmp1); 2629 break; 2630 } 2631 case ISD::VAARG: { 2632 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2633 EVT VT = Node->getValueType(0); 2634 Tmp1 = Node->getOperand(0); 2635 Tmp2 = Node->getOperand(1); 2636 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0, 2637 false, false, 0); 2638 // Increment the pointer, VAList, to the next vaarg 2639 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2640 DAG.getConstant(TLI.getTargetData()-> 2641 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2642 TLI.getPointerTy())); 2643 // Store the incremented VAList to the legalized pointer 2644 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0, 2645 false, false, 0); 2646 // Load the actual argument out of the pointer VAList 2647 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0, 2648 false, false, 0)); 2649 Results.push_back(Results[0].getValue(1)); 2650 break; 2651 } 2652 case ISD::VACOPY: { 2653 // This defaults to loading a pointer from the input and storing it to the 2654 // output, returning the chain. 2655 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2656 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2657 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2658 Node->getOperand(2), VS, 0, false, false, 0); 2659 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0, 2660 false, false, 0); 2661 Results.push_back(Tmp1); 2662 break; 2663 } 2664 case ISD::EXTRACT_VECTOR_ELT: 2665 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2666 // This must be an access of the only element. Return it. 2667 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2668 Node->getOperand(0)); 2669 else 2670 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2671 Results.push_back(Tmp1); 2672 break; 2673 case ISD::EXTRACT_SUBVECTOR: 2674 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2675 break; 2676 case ISD::CONCAT_VECTORS: { 2677 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2678 break; 2679 } 2680 case ISD::SCALAR_TO_VECTOR: 2681 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2682 break; 2683 case ISD::INSERT_VECTOR_ELT: 2684 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2685 Node->getOperand(1), 2686 Node->getOperand(2), dl)); 2687 break; 2688 case ISD::VECTOR_SHUFFLE: { 2689 SmallVector<int, 8> Mask; 2690 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2691 2692 EVT VT = Node->getValueType(0); 2693 EVT EltVT = VT.getVectorElementType(); 2694 if (getTypeAction(EltVT) == Promote) 2695 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT); 2696 unsigned NumElems = VT.getVectorNumElements(); 2697 SmallVector<SDValue, 8> Ops; 2698 for (unsigned i = 0; i != NumElems; ++i) { 2699 if (Mask[i] < 0) { 2700 Ops.push_back(DAG.getUNDEF(EltVT)); 2701 continue; 2702 } 2703 unsigned Idx = Mask[i]; 2704 if (Idx < NumElems) 2705 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2706 Node->getOperand(0), 2707 DAG.getIntPtrConstant(Idx))); 2708 else 2709 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2710 Node->getOperand(1), 2711 DAG.getIntPtrConstant(Idx - NumElems))); 2712 } 2713 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2714 Results.push_back(Tmp1); 2715 break; 2716 } 2717 case ISD::EXTRACT_ELEMENT: { 2718 EVT OpTy = Node->getOperand(0).getValueType(); 2719 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2720 // 1 -> Hi 2721 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2722 DAG.getConstant(OpTy.getSizeInBits()/2, 2723 TLI.getShiftAmountTy())); 2724 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2725 } else { 2726 // 0 -> Lo 2727 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2728 Node->getOperand(0)); 2729 } 2730 Results.push_back(Tmp1); 2731 break; 2732 } 2733 case ISD::STACKSAVE: 2734 // Expand to CopyFromReg if the target set 2735 // StackPointerRegisterToSaveRestore. 2736 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2737 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2738 Node->getValueType(0))); 2739 Results.push_back(Results[0].getValue(1)); 2740 } else { 2741 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2742 Results.push_back(Node->getOperand(0)); 2743 } 2744 break; 2745 case ISD::STACKRESTORE: 2746 // Expand to CopyToReg if the target set 2747 // StackPointerRegisterToSaveRestore. 2748 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2749 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2750 Node->getOperand(1))); 2751 } else { 2752 Results.push_back(Node->getOperand(0)); 2753 } 2754 break; 2755 case ISD::FCOPYSIGN: 2756 Results.push_back(ExpandFCOPYSIGN(Node)); 2757 break; 2758 case ISD::FNEG: 2759 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2760 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2761 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2762 Node->getOperand(0)); 2763 Results.push_back(Tmp1); 2764 break; 2765 case ISD::FABS: { 2766 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2767 EVT VT = Node->getValueType(0); 2768 Tmp1 = Node->getOperand(0); 2769 Tmp2 = DAG.getConstantFP(0.0, VT); 2770 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2771 Tmp1, Tmp2, ISD::SETUGT); 2772 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2773 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2774 Results.push_back(Tmp1); 2775 break; 2776 } 2777 case ISD::FSQRT: 2778 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2779 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2780 break; 2781 case ISD::FSIN: 2782 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2783 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2784 break; 2785 case ISD::FCOS: 2786 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2787 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2788 break; 2789 case ISD::FLOG: 2790 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2791 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2792 break; 2793 case ISD::FLOG2: 2794 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2795 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2796 break; 2797 case ISD::FLOG10: 2798 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2799 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2800 break; 2801 case ISD::FEXP: 2802 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2803 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2804 break; 2805 case ISD::FEXP2: 2806 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2807 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2808 break; 2809 case ISD::FTRUNC: 2810 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2811 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2812 break; 2813 case ISD::FFLOOR: 2814 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2815 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2816 break; 2817 case ISD::FCEIL: 2818 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2819 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2820 break; 2821 case ISD::FRINT: 2822 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2823 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2824 break; 2825 case ISD::FNEARBYINT: 2826 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2827 RTLIB::NEARBYINT_F64, 2828 RTLIB::NEARBYINT_F80, 2829 RTLIB::NEARBYINT_PPCF128)); 2830 break; 2831 case ISD::FPOWI: 2832 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2833 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2834 break; 2835 case ISD::FPOW: 2836 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2837 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2838 break; 2839 case ISD::FDIV: 2840 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2841 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2842 break; 2843 case ISD::FREM: 2844 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2845 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2846 break; 2847 case ISD::FP16_TO_FP32: 2848 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 2849 break; 2850 case ISD::FP32_TO_FP16: 2851 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 2852 break; 2853 case ISD::ConstantFP: { 2854 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2855 // Check to see if this FP immediate is already legal. 2856 // If this is a legal constant, turn it into a TargetConstantFP node. 2857 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 2858 Results.push_back(SDValue(Node, 0)); 2859 else 2860 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2861 break; 2862 } 2863 case ISD::EHSELECTION: { 2864 unsigned Reg = TLI.getExceptionSelectorRegister(); 2865 assert(Reg && "Can't expand to unknown register!"); 2866 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2867 Node->getValueType(0))); 2868 Results.push_back(Results[0].getValue(1)); 2869 break; 2870 } 2871 case ISD::EXCEPTIONADDR: { 2872 unsigned Reg = TLI.getExceptionAddressRegister(); 2873 assert(Reg && "Can't expand to unknown register!"); 2874 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2875 Node->getValueType(0))); 2876 Results.push_back(Results[0].getValue(1)); 2877 break; 2878 } 2879 case ISD::SUB: { 2880 EVT VT = Node->getValueType(0); 2881 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2882 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2883 "Don't know how to expand this subtraction!"); 2884 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2885 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2886 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2887 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2888 break; 2889 } 2890 case ISD::UREM: 2891 case ISD::SREM: { 2892 EVT VT = Node->getValueType(0); 2893 SDVTList VTs = DAG.getVTList(VT, VT); 2894 bool isSigned = Node->getOpcode() == ISD::SREM; 2895 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2896 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2897 Tmp2 = Node->getOperand(0); 2898 Tmp3 = Node->getOperand(1); 2899 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2900 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2901 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2902 // X % Y -> X-X/Y*Y 2903 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2904 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2905 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2906 } else if (isSigned) { 2907 Tmp1 = ExpandIntLibCall(Node, true, 2908 RTLIB::SREM_I8, 2909 RTLIB::SREM_I16, RTLIB::SREM_I32, 2910 RTLIB::SREM_I64, RTLIB::SREM_I128); 2911 } else { 2912 Tmp1 = ExpandIntLibCall(Node, false, 2913 RTLIB::UREM_I8, 2914 RTLIB::UREM_I16, RTLIB::UREM_I32, 2915 RTLIB::UREM_I64, RTLIB::UREM_I128); 2916 } 2917 Results.push_back(Tmp1); 2918 break; 2919 } 2920 case ISD::UDIV: 2921 case ISD::SDIV: { 2922 bool isSigned = Node->getOpcode() == ISD::SDIV; 2923 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2924 EVT VT = Node->getValueType(0); 2925 SDVTList VTs = DAG.getVTList(VT, VT); 2926 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2927 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2928 Node->getOperand(1)); 2929 else if (isSigned) 2930 Tmp1 = ExpandIntLibCall(Node, true, 2931 RTLIB::SDIV_I8, 2932 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2933 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2934 else 2935 Tmp1 = ExpandIntLibCall(Node, false, 2936 RTLIB::UDIV_I8, 2937 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2938 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2939 Results.push_back(Tmp1); 2940 break; 2941 } 2942 case ISD::MULHU: 2943 case ISD::MULHS: { 2944 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2945 ISD::SMUL_LOHI; 2946 EVT VT = Node->getValueType(0); 2947 SDVTList VTs = DAG.getVTList(VT, VT); 2948 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2949 "If this wasn't legal, it shouldn't have been created!"); 2950 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 2951 Node->getOperand(1)); 2952 Results.push_back(Tmp1.getValue(1)); 2953 break; 2954 } 2955 case ISD::MUL: { 2956 EVT VT = Node->getValueType(0); 2957 SDVTList VTs = DAG.getVTList(VT, VT); 2958 // See if multiply or divide can be lowered using two-result operations. 2959 // We just need the low half of the multiply; try both the signed 2960 // and unsigned forms. If the target supports both SMUL_LOHI and 2961 // UMUL_LOHI, form a preference by checking which forms of plain 2962 // MULH it supports. 2963 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 2964 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 2965 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 2966 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 2967 unsigned OpToUse = 0; 2968 if (HasSMUL_LOHI && !HasMULHS) { 2969 OpToUse = ISD::SMUL_LOHI; 2970 } else if (HasUMUL_LOHI && !HasMULHU) { 2971 OpToUse = ISD::UMUL_LOHI; 2972 } else if (HasSMUL_LOHI) { 2973 OpToUse = ISD::SMUL_LOHI; 2974 } else if (HasUMUL_LOHI) { 2975 OpToUse = ISD::UMUL_LOHI; 2976 } 2977 if (OpToUse) { 2978 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 2979 Node->getOperand(1))); 2980 break; 2981 } 2982 Tmp1 = ExpandIntLibCall(Node, false, 2983 RTLIB::MUL_I8, 2984 RTLIB::MUL_I16, RTLIB::MUL_I32, 2985 RTLIB::MUL_I64, RTLIB::MUL_I128); 2986 Results.push_back(Tmp1); 2987 break; 2988 } 2989 case ISD::SADDO: 2990 case ISD::SSUBO: { 2991 SDValue LHS = Node->getOperand(0); 2992 SDValue RHS = Node->getOperand(1); 2993 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 2994 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2995 LHS, RHS); 2996 Results.push_back(Sum); 2997 EVT OType = Node->getValueType(1); 2998 2999 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 3000 3001 // LHSSign -> LHS >= 0 3002 // RHSSign -> RHS >= 0 3003 // SumSign -> Sum >= 0 3004 // 3005 // Add: 3006 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 3007 // Sub: 3008 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 3009 // 3010 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 3011 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 3012 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 3013 Node->getOpcode() == ISD::SADDO ? 3014 ISD::SETEQ : ISD::SETNE); 3015 3016 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 3017 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 3018 3019 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 3020 Results.push_back(Cmp); 3021 break; 3022 } 3023 case ISD::UADDO: 3024 case ISD::USUBO: { 3025 SDValue LHS = Node->getOperand(0); 3026 SDValue RHS = Node->getOperand(1); 3027 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 3028 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3029 LHS, RHS); 3030 Results.push_back(Sum); 3031 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 3032 Node->getOpcode () == ISD::UADDO ? 3033 ISD::SETULT : ISD::SETUGT)); 3034 break; 3035 } 3036 case ISD::UMULO: 3037 case ISD::SMULO: { 3038 EVT VT = Node->getValueType(0); 3039 SDValue LHS = Node->getOperand(0); 3040 SDValue RHS = Node->getOperand(1); 3041 SDValue BottomHalf; 3042 SDValue TopHalf; 3043 static const unsigned Ops[2][3] = 3044 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 3045 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 3046 bool isSigned = Node->getOpcode() == ISD::SMULO; 3047 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 3048 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 3049 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 3050 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 3051 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 3052 RHS); 3053 TopHalf = BottomHalf.getValue(1); 3054 } else { 3055 // FIXME: We should be able to fall back to a libcall with an illegal 3056 // type in some cases. 3057 // Also, we can fall back to a division in some cases, but that's a big 3058 // performance hit in the general case. 3059 assert(TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), 3060 VT.getSizeInBits() * 2)) && 3061 "Don't know how to expand this operation yet!"); 3062 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 3063 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 3064 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 3065 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 3066 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3067 DAG.getIntPtrConstant(0)); 3068 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3069 DAG.getIntPtrConstant(1)); 3070 } 3071 if (isSigned) { 3072 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); 3073 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 3074 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 3075 ISD::SETNE); 3076 } else { 3077 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 3078 DAG.getConstant(0, VT), ISD::SETNE); 3079 } 3080 Results.push_back(BottomHalf); 3081 Results.push_back(TopHalf); 3082 break; 3083 } 3084 case ISD::BUILD_PAIR: { 3085 EVT PairTy = Node->getValueType(0); 3086 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 3087 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 3088 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 3089 DAG.getConstant(PairTy.getSizeInBits()/2, 3090 TLI.getShiftAmountTy())); 3091 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 3092 break; 3093 } 3094 case ISD::SELECT: 3095 Tmp1 = Node->getOperand(0); 3096 Tmp2 = Node->getOperand(1); 3097 Tmp3 = Node->getOperand(2); 3098 if (Tmp1.getOpcode() == ISD::SETCC) { 3099 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 3100 Tmp2, Tmp3, 3101 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 3102 } else { 3103 Tmp1 = DAG.getSelectCC(dl, Tmp1, 3104 DAG.getConstant(0, Tmp1.getValueType()), 3105 Tmp2, Tmp3, ISD::SETNE); 3106 } 3107 Results.push_back(Tmp1); 3108 break; 3109 case ISD::BR_JT: { 3110 SDValue Chain = Node->getOperand(0); 3111 SDValue Table = Node->getOperand(1); 3112 SDValue Index = Node->getOperand(2); 3113 3114 EVT PTy = TLI.getPointerTy(); 3115 3116 const TargetData &TD = *TLI.getTargetData(); 3117 unsigned EntrySize = 3118 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 3119 3120 Index = DAG.getNode(ISD::MUL, dl, PTy, 3121 Index, DAG.getConstant(EntrySize, PTy)); 3122 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 3123 3124 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 3125 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 3126 PseudoSourceValue::getJumpTable(), 0, MemVT, 3127 false, false, 0); 3128 Addr = LD; 3129 if (TM.getRelocationModel() == Reloc::PIC_) { 3130 // For PIC, the sequence is: 3131 // BRIND(load(Jumptable + index) + RelocBase) 3132 // RelocBase can be JumpTable, GOT or some sort of global base. 3133 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 3134 TLI.getPICJumpTableRelocBase(Table, DAG)); 3135 } 3136 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 3137 Results.push_back(Tmp1); 3138 break; 3139 } 3140 case ISD::BRCOND: 3141 // Expand brcond's setcc into its constituent parts and create a BR_CC 3142 // Node. 3143 Tmp1 = Node->getOperand(0); 3144 Tmp2 = Node->getOperand(1); 3145 if (Tmp2.getOpcode() == ISD::SETCC) { 3146 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 3147 Tmp1, Tmp2.getOperand(2), 3148 Tmp2.getOperand(0), Tmp2.getOperand(1), 3149 Node->getOperand(2)); 3150 } else { 3151 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 3152 DAG.getCondCode(ISD::SETNE), Tmp2, 3153 DAG.getConstant(0, Tmp2.getValueType()), 3154 Node->getOperand(2)); 3155 } 3156 Results.push_back(Tmp1); 3157 break; 3158 case ISD::SETCC: { 3159 Tmp1 = Node->getOperand(0); 3160 Tmp2 = Node->getOperand(1); 3161 Tmp3 = Node->getOperand(2); 3162 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 3163 3164 // If we expanded the SETCC into an AND/OR, return the new node 3165 if (Tmp2.getNode() == 0) { 3166 Results.push_back(Tmp1); 3167 break; 3168 } 3169 3170 // Otherwise, SETCC for the given comparison type must be completely 3171 // illegal; expand it into a SELECT_CC. 3172 EVT VT = Node->getValueType(0); 3173 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3174 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 3175 Results.push_back(Tmp1); 3176 break; 3177 } 3178 case ISD::SELECT_CC: { 3179 Tmp1 = Node->getOperand(0); // LHS 3180 Tmp2 = Node->getOperand(1); // RHS 3181 Tmp3 = Node->getOperand(2); // True 3182 Tmp4 = Node->getOperand(3); // False 3183 SDValue CC = Node->getOperand(4); 3184 3185 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 3186 Tmp1, Tmp2, CC, dl); 3187 3188 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 3189 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3190 CC = DAG.getCondCode(ISD::SETNE); 3191 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 3192 Tmp3, Tmp4, CC); 3193 Results.push_back(Tmp1); 3194 break; 3195 } 3196 case ISD::BR_CC: { 3197 Tmp1 = Node->getOperand(0); // Chain 3198 Tmp2 = Node->getOperand(2); // LHS 3199 Tmp3 = Node->getOperand(3); // RHS 3200 Tmp4 = Node->getOperand(1); // CC 3201 3202 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 3203 Tmp2, Tmp3, Tmp4, dl); 3204 LastCALLSEQ_END = DAG.getEntryNode(); 3205 3206 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 3207 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 3208 Tmp4 = DAG.getCondCode(ISD::SETNE); 3209 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3210 Tmp3, Node->getOperand(4)); 3211 Results.push_back(Tmp1); 3212 break; 3213 } 3214 case ISD::GLOBAL_OFFSET_TABLE: 3215 case ISD::GlobalAddress: 3216 case ISD::GlobalTLSAddress: 3217 case ISD::ExternalSymbol: 3218 case ISD::ConstantPool: 3219 case ISD::JumpTable: 3220 case ISD::INTRINSIC_W_CHAIN: 3221 case ISD::INTRINSIC_WO_CHAIN: 3222 case ISD::INTRINSIC_VOID: 3223 // FIXME: Custom lowering for these operations shouldn't return null! 3224 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3225 Results.push_back(SDValue(Node, i)); 3226 break; 3227 } 3228} 3229void SelectionDAGLegalize::PromoteNode(SDNode *Node, 3230 SmallVectorImpl<SDValue> &Results) { 3231 EVT OVT = Node->getValueType(0); 3232 if (Node->getOpcode() == ISD::UINT_TO_FP || 3233 Node->getOpcode() == ISD::SINT_TO_FP || 3234 Node->getOpcode() == ISD::SETCC) { 3235 OVT = Node->getOperand(0).getValueType(); 3236 } 3237 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3238 DebugLoc dl = Node->getDebugLoc(); 3239 SDValue Tmp1, Tmp2, Tmp3; 3240 switch (Node->getOpcode()) { 3241 case ISD::CTTZ: 3242 case ISD::CTLZ: 3243 case ISD::CTPOP: 3244 // Zero extend the argument. 3245 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3246 // Perform the larger operation. 3247 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3248 if (Node->getOpcode() == ISD::CTTZ) { 3249 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3250 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3251 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3252 ISD::SETEQ); 3253 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3254 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3255 } else if (Node->getOpcode() == ISD::CTLZ) { 3256 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3257 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3258 DAG.getConstant(NVT.getSizeInBits() - 3259 OVT.getSizeInBits(), NVT)); 3260 } 3261 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3262 break; 3263 case ISD::BSWAP: { 3264 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3265 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3266 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3267 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3268 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3269 Results.push_back(Tmp1); 3270 break; 3271 } 3272 case ISD::FP_TO_UINT: 3273 case ISD::FP_TO_SINT: 3274 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3275 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3276 Results.push_back(Tmp1); 3277 break; 3278 case ISD::UINT_TO_FP: 3279 case ISD::SINT_TO_FP: 3280 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3281 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3282 Results.push_back(Tmp1); 3283 break; 3284 case ISD::AND: 3285 case ISD::OR: 3286 case ISD::XOR: { 3287 unsigned ExtOp, TruncOp; 3288 if (OVT.isVector()) { 3289 ExtOp = ISD::BIT_CONVERT; 3290 TruncOp = ISD::BIT_CONVERT; 3291 } else { 3292 assert(OVT.isInteger() && "Cannot promote logic operation"); 3293 ExtOp = ISD::ANY_EXTEND; 3294 TruncOp = ISD::TRUNCATE; 3295 } 3296 // Promote each of the values to the new type. 3297 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3298 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3299 // Perform the larger operation, then convert back 3300 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3301 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3302 break; 3303 } 3304 case ISD::SELECT: { 3305 unsigned ExtOp, TruncOp; 3306 if (Node->getValueType(0).isVector()) { 3307 ExtOp = ISD::BIT_CONVERT; 3308 TruncOp = ISD::BIT_CONVERT; 3309 } else if (Node->getValueType(0).isInteger()) { 3310 ExtOp = ISD::ANY_EXTEND; 3311 TruncOp = ISD::TRUNCATE; 3312 } else { 3313 ExtOp = ISD::FP_EXTEND; 3314 TruncOp = ISD::FP_ROUND; 3315 } 3316 Tmp1 = Node->getOperand(0); 3317 // Promote each of the values to the new type. 3318 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3319 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3320 // Perform the larger operation, then round down. 3321 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3322 if (TruncOp != ISD::FP_ROUND) 3323 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3324 else 3325 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3326 DAG.getIntPtrConstant(0)); 3327 Results.push_back(Tmp1); 3328 break; 3329 } 3330 case ISD::VECTOR_SHUFFLE: { 3331 SmallVector<int, 8> Mask; 3332 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3333 3334 // Cast the two input vectors. 3335 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3336 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3337 3338 // Convert the shuffle mask to the right # elements. 3339 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3340 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3341 Results.push_back(Tmp1); 3342 break; 3343 } 3344 case ISD::SETCC: { 3345 unsigned ExtOp = ISD::FP_EXTEND; 3346 if (NVT.isInteger()) { 3347 ISD::CondCode CCCode = 3348 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3349 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3350 } 3351 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3352 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3353 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3354 Tmp1, Tmp2, Node->getOperand(2))); 3355 break; 3356 } 3357 } 3358} 3359 3360// SelectionDAG::Legalize - This is the entry point for the file. 3361// 3362void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) { 3363 /// run - This is the main entry point to this class. 3364 /// 3365 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3366} 3367 3368