LegalizeDAG.cpp revision abf6d1784b2d4bbcb7d20ab64881f77d755059f6
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned long long ValueTypeActions; 56 57 /// NeedsAnotherIteration - This is set when we expand a large integer 58 /// operation into smaller integer operations, but the smaller operations are 59 /// not set. This occurs only rarely in practice, for targets that don't have 60 /// 32-bit or larger integer registers. 61 bool NeedsAnotherIteration; 62 63 /// LegalizedNodes - For nodes that are of legal width, and that have more 64 /// than one use, this map indicates what regularized operand to use. This 65 /// allows us to avoid legalizing the same thing more than once. 66 std::map<SDOperand, SDOperand> LegalizedNodes; 67 68 /// PromotedNodes - For nodes that are below legal width, and that have more 69 /// than one use, this map indicates what promoted value to use. This allows 70 /// us to avoid promoting the same thing more than once. 71 std::map<SDOperand, SDOperand> PromotedNodes; 72 73 /// ExpandedNodes - For nodes that need to be expanded, and which have more 74 /// than one use, this map indicates which which operands are the expanded 75 /// version of the input. This allows us to avoid expanding the same node 76 /// more than once. 77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 78 79 void AddLegalizedOperand(SDOperand From, SDOperand To) { 80 LegalizedNodes.insert(std::make_pair(From, To)); 81 // If someone requests legalization of the new node, return itself. 82 if (From != To) 83 LegalizedNodes.insert(std::make_pair(To, To)); 84 } 85 void AddPromotedOperand(SDOperand From, SDOperand To) { 86 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 87 assert(isNew && "Got into the map somehow?"); 88 // If someone requests legalization of the new node, return itself. 89 LegalizedNodes.insert(std::make_pair(To, To)); 90 } 91 92public: 93 94 SelectionDAGLegalize(SelectionDAG &DAG); 95 96 /// Run - While there is still lowering to do, perform a pass over the DAG. 97 /// Most regularization can be done in a single pass, but targets that require 98 /// large values to be split into registers multiple times (e.g. i64 -> 4x 99 /// i16) require iteration for these values (the first iteration will demote 100 /// to i32, the second will demote to i16). 101 void Run() { 102 do { 103 NeedsAnotherIteration = false; 104 LegalizeDAG(); 105 } while (NeedsAnotherIteration); 106 } 107 108 /// getTypeAction - Return how we should legalize values of this type, either 109 /// it is already legal or we need to expand it into multiple registers of 110 /// smaller integer type, or we need to promote it to a larger type. 111 LegalizeAction getTypeAction(MVT::ValueType VT) const { 112 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 113 } 114 115 /// isTypeLegal - Return true if this type is legal on this target. 116 /// 117 bool isTypeLegal(MVT::ValueType VT) const { 118 return getTypeAction(VT) == Legal; 119 } 120 121private: 122 void LegalizeDAG(); 123 124 SDOperand LegalizeOp(SDOperand O); 125 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 126 SDOperand PromoteOp(SDOperand O); 127 128 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 129 SDOperand &Hi); 130 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 131 SDOperand Source); 132 133 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 134 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 135 SDOperand LegalOp, 136 MVT::ValueType DestVT); 137 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 138 bool isSigned); 139 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 140 bool isSigned); 141 142 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 143 SDOperand &Lo, SDOperand &Hi); 144 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 145 SDOperand &Lo, SDOperand &Hi); 146 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 147 SDOperand &Lo, SDOperand &Hi); 148 149 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 150 151 SDOperand getIntPtrConstant(uint64_t Val) { 152 return DAG.getConstant(Val, TLI.getPointerTy()); 153 } 154}; 155} 156 157static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 158 switch (VecOp) { 159 default: assert(0 && "Don't know how to scalarize this opcode!"); 160 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 161 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 162 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 163 } 164} 165 166SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 167 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 168 ValueTypeActions(TLI.getValueTypeActions()) { 169 assert(MVT::LAST_VALUETYPE <= 32 && 170 "Too many value types for ValueTypeActions to hold!"); 171} 172 173/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 174/// INT_TO_FP operation of the specified operand when the target requests that 175/// we expand it. At this point, we know that the result and operand types are 176/// legal for the target. 177SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 178 SDOperand Op0, 179 MVT::ValueType DestVT) { 180 if (Op0.getValueType() == MVT::i32) { 181 // simple 32-bit [signed|unsigned] integer to float/double expansion 182 183 // get the stack frame index of a 8 byte buffer 184 MachineFunction &MF = DAG.getMachineFunction(); 185 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 186 // get address of 8 byte buffer 187 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 188 // word offset constant for Hi/Lo address computation 189 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 190 // set up Hi and Lo (into buffer) address based on endian 191 SDOperand Hi, Lo; 192 if (TLI.isLittleEndian()) { 193 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 194 Lo = StackSlot; 195 } else { 196 Hi = StackSlot; 197 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 198 } 199 // if signed map to unsigned space 200 SDOperand Op0Mapped; 201 if (isSigned) { 202 // constant used to invert sign bit (signed to unsigned mapping) 203 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 204 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 205 } else { 206 Op0Mapped = Op0; 207 } 208 // store the lo of the constructed double - based on integer input 209 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 210 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 211 // initial hi portion of constructed double 212 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 213 // store the hi of the constructed double - biased exponent 214 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 215 InitialHi, Hi, DAG.getSrcValue(NULL)); 216 // load the constructed double 217 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 218 DAG.getSrcValue(NULL)); 219 // FP constant to bias correct the final result 220 SDOperand Bias = DAG.getConstantFP(isSigned ? 221 BitsToDouble(0x4330000080000000ULL) 222 : BitsToDouble(0x4330000000000000ULL), 223 MVT::f64); 224 // subtract the bias 225 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 226 // final result 227 SDOperand Result; 228 // handle final rounding 229 if (DestVT == MVT::f64) { 230 // do nothing 231 Result = Sub; 232 } else { 233 // if f32 then cast to f32 234 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 235 } 236 return LegalizeOp(Result); 237 } 238 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 239 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 240 241 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 242 DAG.getConstant(0, Op0.getValueType()), 243 ISD::SETLT); 244 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 245 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 246 SignSet, Four, Zero); 247 248 // If the sign bit of the integer is set, the large number will be treated 249 // as a negative number. To counteract this, the dynamic code adds an 250 // offset depending on the data type. 251 uint64_t FF; 252 switch (Op0.getValueType()) { 253 default: assert(0 && "Unsupported integer type!"); 254 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 255 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 256 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 257 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 258 } 259 if (TLI.isLittleEndian()) FF <<= 32; 260 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 261 262 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 263 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 264 SDOperand FudgeInReg; 265 if (DestVT == MVT::f32) 266 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 267 DAG.getSrcValue(NULL)); 268 else { 269 assert(DestVT == MVT::f64 && "Unexpected conversion"); 270 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 271 DAG.getEntryNode(), CPIdx, 272 DAG.getSrcValue(NULL), MVT::f32)); 273 } 274 275 return LegalizeOp(DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg)); 276} 277 278/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 279/// *INT_TO_FP operation of the specified operand when the target requests that 280/// we promote it. At this point, we know that the result and operand types are 281/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 282/// operation that takes a larger input. 283SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 284 MVT::ValueType DestVT, 285 bool isSigned) { 286 // First step, figure out the appropriate *INT_TO_FP operation to use. 287 MVT::ValueType NewInTy = LegalOp.getValueType(); 288 289 unsigned OpToUse = 0; 290 291 // Scan for the appropriate larger type to use. 292 while (1) { 293 NewInTy = (MVT::ValueType)(NewInTy+1); 294 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 295 296 // If the target supports SINT_TO_FP of this type, use it. 297 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 298 default: break; 299 case TargetLowering::Legal: 300 if (!TLI.isTypeLegal(NewInTy)) 301 break; // Can't use this datatype. 302 // FALL THROUGH. 303 case TargetLowering::Custom: 304 OpToUse = ISD::SINT_TO_FP; 305 break; 306 } 307 if (OpToUse) break; 308 if (isSigned) continue; 309 310 // If the target supports UINT_TO_FP of this type, use it. 311 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 312 default: break; 313 case TargetLowering::Legal: 314 if (!TLI.isTypeLegal(NewInTy)) 315 break; // Can't use this datatype. 316 // FALL THROUGH. 317 case TargetLowering::Custom: 318 OpToUse = ISD::UINT_TO_FP; 319 break; 320 } 321 if (OpToUse) break; 322 323 // Otherwise, try a larger type. 324 } 325 326 // Okay, we found the operation and type to use. Zero extend our input to the 327 // desired type then run the operation on it. 328 SDOperand N = DAG.getNode(OpToUse, DestVT, 329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 330 NewInTy, LegalOp)); 331 // Make sure to legalize any nodes we create here. 332 return LegalizeOp(N); 333} 334 335/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 336/// FP_TO_*INT operation of the specified operand when the target requests that 337/// we promote it. At this point, we know that the result and operand types are 338/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 339/// operation that returns a larger result. 340SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 341 MVT::ValueType DestVT, 342 bool isSigned) { 343 // First step, figure out the appropriate FP_TO*INT operation to use. 344 MVT::ValueType NewOutTy = DestVT; 345 346 unsigned OpToUse = 0; 347 348 // Scan for the appropriate larger type to use. 349 while (1) { 350 NewOutTy = (MVT::ValueType)(NewOutTy+1); 351 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 352 353 // If the target supports FP_TO_SINT returning this type, use it. 354 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 355 default: break; 356 case TargetLowering::Legal: 357 if (!TLI.isTypeLegal(NewOutTy)) 358 break; // Can't use this datatype. 359 // FALL THROUGH. 360 case TargetLowering::Custom: 361 OpToUse = ISD::FP_TO_SINT; 362 break; 363 } 364 if (OpToUse) break; 365 366 // If the target supports FP_TO_UINT of this type, use it. 367 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 368 default: break; 369 case TargetLowering::Legal: 370 if (!TLI.isTypeLegal(NewOutTy)) 371 break; // Can't use this datatype. 372 // FALL THROUGH. 373 case TargetLowering::Custom: 374 OpToUse = ISD::FP_TO_UINT; 375 break; 376 } 377 if (OpToUse) break; 378 379 // Otherwise, try a larger type. 380 } 381 382 // Okay, we found the operation and type to use. Truncate the result of the 383 // extended FP_TO_*INT operation to the desired size. 384 SDOperand N = DAG.getNode(ISD::TRUNCATE, DestVT, 385 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 386 // Make sure to legalize any nodes we create here in the next pass. 387 return LegalizeOp(N); 388} 389 390/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 391/// not been visited yet and if all of its operands have already been visited. 392static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 393 std::map<SDNode*, unsigned> &Visited) { 394 if (++Visited[N] != N->getNumOperands()) 395 return; // Haven't visited all operands yet 396 397 Order.push_back(N); 398 399 if (N->hasOneUse()) { // Tail recurse in common case. 400 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 401 return; 402 } 403 404 // Now that we have N in, add anything that uses it if all of their operands 405 // are now done. 406 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 407 ComputeTopDownOrdering(*UI, Order, Visited); 408} 409 410 411void SelectionDAGLegalize::LegalizeDAG() { 412 // The legalize process is inherently a bottom-up recursive process (users 413 // legalize their uses before themselves). Given infinite stack space, we 414 // could just start legalizing on the root and traverse the whole graph. In 415 // practice however, this causes us to run out of stack space on large basic 416 // blocks. To avoid this problem, compute an ordering of the nodes where each 417 // node is only legalized after all of its operands are legalized. 418 std::map<SDNode*, unsigned> Visited; 419 std::vector<SDNode*> Order; 420 421 // Compute ordering from all of the leaves in the graphs, those (like the 422 // entry node) that have no operands. 423 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 424 E = DAG.allnodes_end(); I != E; ++I) { 425 if (I->getNumOperands() == 0) { 426 Visited[I] = 0 - 1U; 427 ComputeTopDownOrdering(I, Order, Visited); 428 } 429 } 430 431 assert(Order.size() == Visited.size() && 432 Order.size() == 433 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 434 "Error: DAG is cyclic!"); 435 Visited.clear(); 436 437 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 438 SDNode *N = Order[i]; 439 switch (getTypeAction(N->getValueType(0))) { 440 default: assert(0 && "Bad type action!"); 441 case Legal: 442 LegalizeOp(SDOperand(N, 0)); 443 break; 444 case Promote: 445 PromoteOp(SDOperand(N, 0)); 446 break; 447 case Expand: { 448 SDOperand X, Y; 449 ExpandOp(SDOperand(N, 0), X, Y); 450 break; 451 } 452 } 453 } 454 455 // Finally, it's possible the root changed. Get the new root. 456 SDOperand OldRoot = DAG.getRoot(); 457 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 458 DAG.setRoot(LegalizedNodes[OldRoot]); 459 460 ExpandedNodes.clear(); 461 LegalizedNodes.clear(); 462 PromotedNodes.clear(); 463 464 // Remove dead nodes now. 465 DAG.RemoveDeadNodes(OldRoot.Val); 466} 467 468SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 469 assert(isTypeLegal(Op.getValueType()) && 470 "Caller should expand or promote operands that are not legal!"); 471 SDNode *Node = Op.Val; 472 473 // If this operation defines any values that cannot be represented in a 474 // register on this target, make sure to expand or promote them. 475 if (Node->getNumValues() > 1) { 476 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 477 switch (getTypeAction(Node->getValueType(i))) { 478 case Legal: break; // Nothing to do. 479 case Expand: { 480 SDOperand T1, T2; 481 ExpandOp(Op.getValue(i), T1, T2); 482 assert(LegalizedNodes.count(Op) && 483 "Expansion didn't add legal operands!"); 484 return LegalizedNodes[Op]; 485 } 486 case Promote: 487 PromoteOp(Op.getValue(i)); 488 assert(LegalizedNodes.count(Op) && 489 "Expansion didn't add legal operands!"); 490 return LegalizedNodes[Op]; 491 } 492 } 493 494 // Note that LegalizeOp may be reentered even from single-use nodes, which 495 // means that we always must cache transformed nodes. 496 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 497 if (I != LegalizedNodes.end()) return I->second; 498 499 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 500 501 SDOperand Result = Op; 502 503 switch (Node->getOpcode()) { 504 default: 505 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 506 // If this is a target node, legalize it by legalizing the operands then 507 // passing it through. 508 std::vector<SDOperand> Ops; 509 bool Changed = false; 510 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 511 Ops.push_back(LegalizeOp(Node->getOperand(i))); 512 Changed = Changed || Node->getOperand(i) != Ops.back(); 513 } 514 if (Changed) 515 if (Node->getNumValues() == 1) 516 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 517 else { 518 std::vector<MVT::ValueType> VTs(Node->value_begin(), 519 Node->value_end()); 520 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 521 } 522 523 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 524 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 525 return Result.getValue(Op.ResNo); 526 } 527 // Otherwise this is an unhandled builtin node. splat. 528 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 529 assert(0 && "Do not know how to legalize this operator!"); 530 abort(); 531 case ISD::EntryToken: 532 case ISD::FrameIndex: 533 case ISD::TargetFrameIndex: 534 case ISD::Register: 535 case ISD::TargetConstant: 536 case ISD::TargetConstantPool: 537 case ISD::GlobalAddress: 538 case ISD::TargetGlobalAddress: 539 case ISD::ExternalSymbol: 540 case ISD::TargetExternalSymbol: 541 case ISD::ConstantPool: // Nothing to do. 542 case ISD::BasicBlock: 543 case ISD::CONDCODE: 544 case ISD::VALUETYPE: 545 case ISD::SRCVALUE: 546 case ISD::STRING: 547 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 548 default: assert(0 && "This action is not supported yet!"); 549 case TargetLowering::Custom: { 550 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 551 if (Tmp.Val) { 552 Result = LegalizeOp(Tmp); 553 break; 554 } 555 } // FALLTHROUGH if the target doesn't want to lower this op after all. 556 case TargetLowering::Legal: 557 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!"); 558 break; 559 } 560 break; 561 case ISD::AssertSext: 562 case ISD::AssertZext: 563 Tmp1 = LegalizeOp(Node->getOperand(0)); 564 if (Tmp1 != Node->getOperand(0)) 565 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 566 Node->getOperand(1)); 567 break; 568 case ISD::MERGE_VALUES: 569 return LegalizeOp(Node->getOperand(Op.ResNo)); 570 case ISD::CopyFromReg: 571 Tmp1 = LegalizeOp(Node->getOperand(0)); 572 Result = Op.getValue(0); 573 if (Node->getNumValues() == 2) { 574 if (Tmp1 != Node->getOperand(0)) 575 Result = DAG.getCopyFromReg(Tmp1, 576 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 577 Node->getValueType(0)); 578 } else { 579 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 580 if (Node->getNumOperands() == 3) 581 Tmp2 = LegalizeOp(Node->getOperand(2)); 582 if (Tmp1 != Node->getOperand(0) || 583 (Node->getNumOperands() == 3 && Tmp2 != Node->getOperand(2))) 584 Result = DAG.getCopyFromReg(Tmp1, 585 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 586 Node->getValueType(0), Tmp2); 587 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 588 } 589 // Since CopyFromReg produces two values, make sure to remember that we 590 // legalized both of them. 591 AddLegalizedOperand(Op.getValue(0), Result); 592 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 593 return Result.getValue(Op.ResNo); 594 case ISD::UNDEF: { 595 MVT::ValueType VT = Op.getValueType(); 596 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 597 default: assert(0 && "This action is not supported yet!"); 598 case TargetLowering::Expand: 599 case TargetLowering::Promote: 600 if (MVT::isInteger(VT)) 601 Result = DAG.getConstant(0, VT); 602 else if (MVT::isFloatingPoint(VT)) 603 Result = DAG.getConstantFP(0, VT); 604 else 605 assert(0 && "Unknown value type!"); 606 break; 607 case TargetLowering::Legal: 608 break; 609 } 610 break; 611 } 612 613 case ISD::LOCATION: 614 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 615 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 616 617 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 618 case TargetLowering::Promote: 619 default: assert(0 && "This action is not supported yet!"); 620 case TargetLowering::Expand: { 621 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 622 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 623 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other); 624 625 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) { 626 const std::string &FName = 627 cast<StringSDNode>(Node->getOperand(3))->getValue(); 628 const std::string &DirName = 629 cast<StringSDNode>(Node->getOperand(4))->getValue(); 630 unsigned SrcFile = DebugInfo->getUniqueSourceID(FName, DirName); 631 632 std::vector<SDOperand> Ops; 633 Ops.push_back(Tmp1); // chain 634 SDOperand LineOp = Node->getOperand(1); 635 SDOperand ColOp = Node->getOperand(2); 636 637 if (useDEBUG_LOC) { 638 Ops.push_back(LineOp); // line # 639 Ops.push_back(ColOp); // col # 640 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 641 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops); 642 } else { 643 unsigned Line = dyn_cast<ConstantSDNode>(LineOp)->getValue(); 644 unsigned Col = dyn_cast<ConstantSDNode>(ColOp)->getValue(); 645 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile); 646 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 647 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops); 648 } 649 } else { 650 Result = Tmp1; // chain 651 } 652 Result = LegalizeOp(Result); // Relegalize new nodes. 653 break; 654 } 655 case TargetLowering::Legal: 656 if (Tmp1 != Node->getOperand(0) || 657 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 658 std::vector<SDOperand> Ops; 659 Ops.push_back(Tmp1); 660 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 661 Ops.push_back(Node->getOperand(1)); // line # must be legal. 662 Ops.push_back(Node->getOperand(2)); // col # must be legal. 663 } else { 664 // Otherwise promote them. 665 Ops.push_back(PromoteOp(Node->getOperand(1))); 666 Ops.push_back(PromoteOp(Node->getOperand(2))); 667 } 668 Ops.push_back(Node->getOperand(3)); // filename must be legal. 669 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 670 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops); 671 } 672 break; 673 } 674 break; 675 676 case ISD::DEBUG_LOC: 677 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 678 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 679 case TargetLowering::Promote: 680 case TargetLowering::Expand: 681 default: assert(0 && "This action is not supported yet!"); 682 case TargetLowering::Legal: 683 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 684 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 685 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 686 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 687 688 if (Tmp1 != Node->getOperand(0) || 689 Tmp2 != Node->getOperand(1) || 690 Tmp3 != Node->getOperand(2) || 691 Tmp4 != Node->getOperand(3)) { 692 Result = DAG.getNode(ISD::DEBUG_LOC,MVT::Other, Tmp1, Tmp2, Tmp3, Tmp4); 693 } 694 break; 695 } 696 break; 697 698 case ISD::DEBUG_LABEL: 699 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!"); 700 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) { 701 case TargetLowering::Promote: 702 case TargetLowering::Expand: 703 default: assert(0 && "This action is not supported yet!"); 704 case TargetLowering::Legal: 705 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 706 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 707 708 if (Tmp1 != Node->getOperand(0) || 709 Tmp2 != Node->getOperand(1)) { 710 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Tmp1, Tmp2); 711 } 712 break; 713 } 714 break; 715 716 case ISD::Constant: 717 // We know we don't need to expand constants here, constants only have one 718 // value and we check that it is fine above. 719 720 // FIXME: Maybe we should handle things like targets that don't support full 721 // 32-bit immediates? 722 break; 723 case ISD::ConstantFP: { 724 // Spill FP immediates to the constant pool if the target cannot directly 725 // codegen them. Targets often have some immediate values that can be 726 // efficiently generated into an FP register without a load. We explicitly 727 // leave these constants as ConstantFP nodes for the target to deal with. 728 729 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 730 731 // Check to see if this FP immediate is already legal. 732 bool isLegal = false; 733 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 734 E = TLI.legal_fpimm_end(); I != E; ++I) 735 if (CFP->isExactlyValue(*I)) { 736 isLegal = true; 737 break; 738 } 739 740 if (!isLegal) { 741 // Otherwise we need to spill the constant to memory. 742 bool Extend = false; 743 744 // If a FP immediate is precise when represented as a float, we put it 745 // into the constant pool as a float, even if it's is statically typed 746 // as a double. 747 MVT::ValueType VT = CFP->getValueType(0); 748 bool isDouble = VT == MVT::f64; 749 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 750 Type::FloatTy, CFP->getValue()); 751 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 752 // Only do this if the target has a native EXTLOAD instruction from 753 // f32. 754 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 755 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 756 VT = MVT::f32; 757 Extend = true; 758 } 759 760 SDOperand CPIdx = 761 LegalizeOp(DAG.getConstantPool(LLVMC, TLI.getPointerTy())); 762 if (Extend) { 763 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 764 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 765 } else { 766 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 767 DAG.getSrcValue(NULL)); 768 } 769 } 770 break; 771 } 772 case ISD::ConstantVec: { 773 // We assume that vector constants are not legal, and will be immediately 774 // spilled to the constant pool. 775 // 776 // FIXME: revisit this when we have some kind of mechanism by which targets 777 // can decided legality of vector constants, of which there may be very 778 // many. 779 // 780 // Create a ConstantPacked, and put it in the constant pool. 781 std::vector<Constant*> CV; 782 MVT::ValueType VT = Node->getValueType(0); 783 for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) { 784 SDOperand OpN = Node->getOperand(I); 785 const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType()); 786 if (MVT::isFloatingPoint(VT)) 787 CV.push_back(ConstantFP::get(OpNTy, 788 cast<ConstantFPSDNode>(OpN)->getValue())); 789 else 790 CV.push_back(ConstantUInt::get(OpNTy, 791 cast<ConstantSDNode>(OpN)->getValue())); 792 } 793 Constant *CP = ConstantPacked::get(CV); 794 SDOperand CPIdx = LegalizeOp(DAG.getConstantPool(CP, TLI.getPointerTy())); 795 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL)); 796 break; 797 } 798 case ISD::TokenFactor: 799 if (Node->getNumOperands() == 2) { 800 bool Changed = false; 801 SDOperand Op0 = LegalizeOp(Node->getOperand(0)); 802 SDOperand Op1 = LegalizeOp(Node->getOperand(1)); 803 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1)) 804 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1); 805 } else { 806 std::vector<SDOperand> Ops; 807 bool Changed = false; 808 // Legalize the operands. 809 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 810 SDOperand Op = Node->getOperand(i); 811 Ops.push_back(LegalizeOp(Op)); 812 Changed |= Ops[i] != Op; 813 } 814 if (Changed) 815 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 816 } 817 break; 818 819 case ISD::CALLSEQ_START: 820 case ISD::CALLSEQ_END: 821 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 822 // Do not try to legalize the target-specific arguments (#1+) 823 Tmp2 = Node->getOperand(0); 824 if (Tmp1 != Tmp2) 825 Node->setAdjCallChain(Tmp1); 826 827 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These 828 // nodes are treated specially and are mutated in place. This makes the dag 829 // legalization process more efficient and also makes libcall insertion 830 // easier. 831 break; 832 case ISD::DYNAMIC_STACKALLOC: 833 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 834 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 835 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 836 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 837 Tmp3 != Node->getOperand(2)) { 838 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 839 std::vector<SDOperand> Ops; 840 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 841 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 842 } else 843 Result = Op.getValue(0); 844 845 // Since this op produces two values, make sure to remember that we 846 // legalized both of them. 847 AddLegalizedOperand(SDOperand(Node, 0), Result); 848 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 849 return Result.getValue(Op.ResNo); 850 851 case ISD::TAILCALL: 852 case ISD::CALL: { 853 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 854 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 855 856 bool Changed = false; 857 std::vector<SDOperand> Ops; 858 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 859 Ops.push_back(LegalizeOp(Node->getOperand(i))); 860 Changed |= Ops.back() != Node->getOperand(i); 861 } 862 863 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 864 std::vector<MVT::ValueType> RetTyVTs; 865 RetTyVTs.reserve(Node->getNumValues()); 866 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 867 RetTyVTs.push_back(Node->getValueType(i)); 868 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 869 Node->getOpcode() == ISD::TAILCALL), 0); 870 } else { 871 Result = Result.getValue(0); 872 } 873 // Since calls produce multiple values, make sure to remember that we 874 // legalized all of them. 875 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 876 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 877 return Result.getValue(Op.ResNo); 878 } 879 case ISD::BR: 880 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 881 if (Tmp1 != Node->getOperand(0)) 882 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 883 break; 884 885 case ISD::BRCOND: 886 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 887 888 switch (getTypeAction(Node->getOperand(1).getValueType())) { 889 case Expand: assert(0 && "It's impossible to expand bools"); 890 case Legal: 891 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 892 break; 893 case Promote: 894 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 895 break; 896 } 897 898 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 899 default: assert(0 && "This action is not supported yet!"); 900 case TargetLowering::Expand: 901 // Expand brcond's setcc into its constituent parts and create a BR_CC 902 // Node. 903 if (Tmp2.getOpcode() == ISD::SETCC) { 904 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 905 Tmp2.getOperand(0), Tmp2.getOperand(1), 906 Node->getOperand(2)); 907 } else { 908 // Make sure the condition is either zero or one. It may have been 909 // promoted from something else. 910 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 911 912 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 913 DAG.getCondCode(ISD::SETNE), Tmp2, 914 DAG.getConstant(0, Tmp2.getValueType()), 915 Node->getOperand(2)); 916 } 917 Result = LegalizeOp(Result); // Relegalize new nodes. 918 break; 919 case TargetLowering::Custom: { 920 SDOperand Tmp = 921 TLI.LowerOperation(DAG.getNode(ISD::BRCOND, Node->getValueType(0), 922 Tmp1, Tmp2, Node->getOperand(2)), DAG); 923 if (Tmp.Val) { 924 Result = LegalizeOp(Tmp); 925 break; 926 } 927 // FALLTHROUGH if the target thinks it is legal. 928 } 929 case TargetLowering::Legal: 930 // Basic block destination (Op#2) is always legal. 931 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 932 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 933 Node->getOperand(2)); 934 break; 935 } 936 break; 937 case ISD::BR_CC: 938 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 939 if (!isTypeLegal(Node->getOperand(2).getValueType())) { 940 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 941 Node->getOperand(2), // LHS 942 Node->getOperand(3), // RHS 943 Node->getOperand(1))); 944 // If we get a SETCC back from legalizing the SETCC node we just 945 // created, then use its LHS, RHS, and CC directly in creating a new 946 // node. Otherwise, select between the true and false value based on 947 // comparing the result of the legalized with zero. 948 if (Tmp2.getOpcode() == ISD::SETCC) { 949 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 950 Tmp2.getOperand(0), Tmp2.getOperand(1), 951 Node->getOperand(4)); 952 } else { 953 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 954 DAG.getCondCode(ISD::SETNE), 955 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 956 Node->getOperand(4)); 957 } 958 break; 959 } 960 961 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 962 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 963 964 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 965 default: assert(0 && "Unexpected action for BR_CC!"); 966 case TargetLowering::Custom: { 967 Tmp4 = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 968 Tmp2, Tmp3, Node->getOperand(4)); 969 Tmp4 = TLI.LowerOperation(Tmp4, DAG); 970 if (Tmp4.Val) { 971 Result = LegalizeOp(Tmp4); 972 break; 973 } 974 } // FALLTHROUGH if the target doesn't want to lower this op after all. 975 case TargetLowering::Legal: 976 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 977 Tmp3 != Node->getOperand(3)) { 978 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 979 Tmp2, Tmp3, Node->getOperand(4)); 980 } 981 break; 982 } 983 break; 984 case ISD::BRCONDTWOWAY: 985 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 986 switch (getTypeAction(Node->getOperand(1).getValueType())) { 987 case Expand: assert(0 && "It's impossible to expand bools"); 988 case Legal: 989 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 990 break; 991 case Promote: 992 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 993 break; 994 } 995 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 996 // pair. 997 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 998 case TargetLowering::Promote: 999 default: assert(0 && "This action is not supported yet!"); 1000 case TargetLowering::Legal: 1001 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1002 std::vector<SDOperand> Ops; 1003 Ops.push_back(Tmp1); 1004 Ops.push_back(Tmp2); 1005 Ops.push_back(Node->getOperand(2)); 1006 Ops.push_back(Node->getOperand(3)); 1007 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 1008 } 1009 break; 1010 case TargetLowering::Expand: 1011 // If BRTWOWAY_CC is legal for this target, then simply expand this node 1012 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 1013 // BRCOND/BR pair. 1014 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 1015 if (Tmp2.getOpcode() == ISD::SETCC) { 1016 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 1017 Tmp2.getOperand(0), Tmp2.getOperand(1), 1018 Node->getOperand(2), Node->getOperand(3)); 1019 } else { 1020 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 1021 DAG.getConstant(0, Tmp2.getValueType()), 1022 Node->getOperand(2), Node->getOperand(3)); 1023 } 1024 } else { 1025 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 1026 Node->getOperand(2)); 1027 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 1028 } 1029 Result = LegalizeOp(Result); // Relegalize new nodes. 1030 break; 1031 } 1032 break; 1033 case ISD::BRTWOWAY_CC: 1034 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1035 if (isTypeLegal(Node->getOperand(2).getValueType())) { 1036 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 1037 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 1038 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 1039 Tmp3 != Node->getOperand(3)) { 1040 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3, 1041 Node->getOperand(4), Node->getOperand(5)); 1042 } 1043 break; 1044 } else { 1045 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1046 Node->getOperand(2), // LHS 1047 Node->getOperand(3), // RHS 1048 Node->getOperand(1))); 1049 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 1050 // pair. 1051 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 1052 default: assert(0 && "This action is not supported yet!"); 1053 case TargetLowering::Legal: 1054 // If we get a SETCC back from legalizing the SETCC node we just 1055 // created, then use its LHS, RHS, and CC directly in creating a new 1056 // node. Otherwise, select between the true and false value based on 1057 // comparing the result of the legalized with zero. 1058 if (Tmp2.getOpcode() == ISD::SETCC) { 1059 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 1060 Tmp2.getOperand(0), Tmp2.getOperand(1), 1061 Node->getOperand(4), Node->getOperand(5)); 1062 } else { 1063 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 1064 DAG.getConstant(0, Tmp2.getValueType()), 1065 Node->getOperand(4), Node->getOperand(5)); 1066 } 1067 break; 1068 case TargetLowering::Expand: 1069 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 1070 Node->getOperand(4)); 1071 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 1072 break; 1073 } 1074 Result = LegalizeOp(Result); // Relegalize new nodes. 1075 } 1076 break; 1077 case ISD::LOAD: { 1078 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1079 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1080 1081 MVT::ValueType VT = Node->getValueType(0); 1082 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1083 default: assert(0 && "This action is not supported yet!"); 1084 case TargetLowering::Custom: { 1085 SDOperand Op = DAG.getLoad(Node->getValueType(0), 1086 Tmp1, Tmp2, Node->getOperand(2)); 1087 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 1088 if (Tmp.Val) { 1089 Result = LegalizeOp(Tmp); 1090 // Since loads produce two values, make sure to remember that we legalized 1091 // both of them. 1092 AddLegalizedOperand(SDOperand(Node, 0), Result); 1093 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1094 return Result.getValue(Op.ResNo); 1095 } 1096 // FALLTHROUGH if the target thinks it is legal. 1097 } 1098 case TargetLowering::Legal: 1099 if (Tmp1 != Node->getOperand(0) || 1100 Tmp2 != Node->getOperand(1)) 1101 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, 1102 Node->getOperand(2)); 1103 else 1104 Result = SDOperand(Node, 0); 1105 1106 // Since loads produce two values, make sure to remember that we legalized 1107 // both of them. 1108 AddLegalizedOperand(SDOperand(Node, 0), Result); 1109 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1110 return Result.getValue(Op.ResNo); 1111 } 1112 assert(0 && "Unreachable"); 1113 } 1114 case ISD::EXTLOAD: 1115 case ISD::SEXTLOAD: 1116 case ISD::ZEXTLOAD: { 1117 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1118 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1119 1120 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 1121 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 1122 default: assert(0 && "This action is not supported yet!"); 1123 case TargetLowering::Promote: 1124 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 1125 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1126 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 1127 // Since loads produce two values, make sure to remember that we legalized 1128 // both of them. 1129 AddLegalizedOperand(SDOperand(Node, 0), Result); 1130 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1131 return Result.getValue(Op.ResNo); 1132 1133 case TargetLowering::Custom: { 1134 SDOperand Op = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1135 Tmp1, Tmp2, Node->getOperand(2), 1136 SrcVT); 1137 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 1138 if (Tmp.Val) { 1139 Result = LegalizeOp(Tmp); 1140 // Since loads produce two values, make sure to remember that we legalized 1141 // both of them. 1142 AddLegalizedOperand(SDOperand(Node, 0), Result); 1143 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1144 return Result.getValue(Op.ResNo); 1145 } 1146 // FALLTHROUGH if the target thinks it is legal. 1147 } 1148 case TargetLowering::Legal: 1149 if (Tmp1 != Node->getOperand(0) || 1150 Tmp2 != Node->getOperand(1)) 1151 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1152 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1153 else 1154 Result = SDOperand(Node, 0); 1155 1156 // Since loads produce two values, make sure to remember that we legalized 1157 // both of them. 1158 AddLegalizedOperand(SDOperand(Node, 0), Result); 1159 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1160 return Result.getValue(Op.ResNo); 1161 case TargetLowering::Expand: 1162 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1163 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1164 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 1165 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1166 Result = LegalizeOp(Result); // Relegalize new nodes. 1167 Load = LegalizeOp(Load); 1168 AddLegalizedOperand(SDOperand(Node, 0), Result); 1169 AddLegalizedOperand(SDOperand(Node, 1), Load.getValue(1)); 1170 if (Op.ResNo) 1171 return Load.getValue(1); 1172 return Result; 1173 } 1174 assert(Node->getOpcode() != ISD::EXTLOAD && 1175 "EXTLOAD should always be supported!"); 1176 // Turn the unsupported load into an EXTLOAD followed by an explicit 1177 // zero/sign extend inreg. 1178 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1179 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1180 SDOperand ValRes; 1181 if (Node->getOpcode() == ISD::SEXTLOAD) 1182 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1183 Result, DAG.getValueType(SrcVT)); 1184 else 1185 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1186 Result = LegalizeOp(Result); // Relegalize new nodes. 1187 ValRes = LegalizeOp(ValRes); // Relegalize new nodes. 1188 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 1189 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1190 if (Op.ResNo) 1191 return Result.getValue(1); 1192 return ValRes; 1193 } 1194 assert(0 && "Unreachable"); 1195 } 1196 case ISD::EXTRACT_ELEMENT: { 1197 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1198 switch (getTypeAction(OpTy)) { 1199 default: 1200 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1201 break; 1202 case Legal: 1203 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1204 // 1 -> Hi 1205 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1206 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1207 TLI.getShiftAmountTy())); 1208 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1209 } else { 1210 // 0 -> Lo 1211 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1212 Node->getOperand(0)); 1213 } 1214 Result = LegalizeOp(Result); 1215 break; 1216 case Expand: 1217 // Get both the low and high parts. 1218 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1219 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1220 Result = Tmp2; // 1 -> Hi 1221 else 1222 Result = Tmp1; // 0 -> Lo 1223 break; 1224 } 1225 break; 1226 } 1227 1228 case ISD::CopyToReg: 1229 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1230 1231 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1232 "Register type must be legal!"); 1233 // Legalize the incoming value (must be a legal type). 1234 Tmp2 = LegalizeOp(Node->getOperand(2)); 1235 if (Node->getNumValues() == 1) { 1236 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2)) 1237 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1, 1238 Node->getOperand(1), Tmp2); 1239 } else { 1240 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1241 if (Node->getNumOperands() == 4) 1242 Tmp3 = LegalizeOp(Node->getOperand(3)); 1243 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 1244 (Node->getNumOperands() == 4 && Tmp3 != Node->getOperand(3))) { 1245 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 1246 Result = DAG.getCopyToReg(Tmp1, Reg, Tmp2, Tmp3); 1247 } 1248 1249 // Since this produces two values, make sure to remember that we legalized 1250 // both of them. 1251 AddLegalizedOperand(SDOperand(Node, 0), Result); 1252 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1253 return Result.getValue(Op.ResNo); 1254 } 1255 break; 1256 1257 case ISD::RET: 1258 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1259 switch (Node->getNumOperands()) { 1260 case 2: // ret val 1261 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1262 case Legal: 1263 Tmp2 = LegalizeOp(Node->getOperand(1)); 1264 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1265 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1266 break; 1267 case Expand: { 1268 SDOperand Lo, Hi; 1269 ExpandOp(Node->getOperand(1), Lo, Hi); 1270 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1271 break; 1272 } 1273 case Promote: 1274 Tmp2 = PromoteOp(Node->getOperand(1)); 1275 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1276 break; 1277 } 1278 break; 1279 case 1: // ret void 1280 if (Tmp1 != Node->getOperand(0)) 1281 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 1282 break; 1283 default: { // ret <values> 1284 std::vector<SDOperand> NewValues; 1285 NewValues.push_back(Tmp1); 1286 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1287 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1288 case Legal: 1289 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1290 break; 1291 case Expand: { 1292 SDOperand Lo, Hi; 1293 ExpandOp(Node->getOperand(i), Lo, Hi); 1294 NewValues.push_back(Lo); 1295 NewValues.push_back(Hi); 1296 break; 1297 } 1298 case Promote: 1299 assert(0 && "Can't promote multiple return value yet!"); 1300 } 1301 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1302 break; 1303 } 1304 } 1305 break; 1306 case ISD::STORE: { 1307 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1308 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1309 1310 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1311 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1312 if (CFP->getValueType(0) == MVT::f32) { 1313 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1314 DAG.getConstant(FloatToBits(CFP->getValue()), 1315 MVT::i32), 1316 Tmp2, 1317 Node->getOperand(3)); 1318 } else { 1319 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1320 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1321 DAG.getConstant(DoubleToBits(CFP->getValue()), 1322 MVT::i64), 1323 Tmp2, 1324 Node->getOperand(3)); 1325 } 1326 Node = Result.Val; 1327 } 1328 1329 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1330 case Legal: { 1331 SDOperand Val = LegalizeOp(Node->getOperand(1)); 1332 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 1333 Tmp2 != Node->getOperand(2)) 1334 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 1335 Node->getOperand(3)); 1336 1337 MVT::ValueType VT = Result.Val->getOperand(1).getValueType(); 1338 switch (TLI.getOperationAction(Result.Val->getOpcode(), VT)) { 1339 default: assert(0 && "This action is not supported yet!"); 1340 case TargetLowering::Custom: { 1341 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1342 if (Tmp.Val) { 1343 Result = LegalizeOp(Tmp); 1344 break; 1345 } 1346 // FALLTHROUGH if the target thinks it is legal. 1347 } 1348 case TargetLowering::Legal: 1349 // Nothing to do. 1350 break; 1351 } 1352 break; 1353 } 1354 case Promote: 1355 // Truncate the value and store the result. 1356 Tmp3 = PromoteOp(Node->getOperand(1)); 1357 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1358 Node->getOperand(3), 1359 DAG.getValueType(Node->getOperand(1).getValueType())); 1360 break; 1361 1362 case Expand: 1363 SDOperand Lo, Hi; 1364 unsigned IncrementSize; 1365 ExpandOp(Node->getOperand(1), Lo, Hi); 1366 1367 if (!TLI.isLittleEndian()) 1368 std::swap(Lo, Hi); 1369 1370 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1371 Node->getOperand(3)); 1372 // If this is a vector type, then we have to calculate the increment as 1373 // the product of the element size in bytes, and the number of elements 1374 // in the high half of the vector. 1375 if (MVT::Vector == Hi.getValueType()) { 1376 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue(); 1377 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT(); 1378 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8; 1379 } else { 1380 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1381 } 1382 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1383 getIntPtrConstant(IncrementSize)); 1384 assert(isTypeLegal(Tmp2.getValueType()) && 1385 "Pointers must be legal!"); 1386 //Again, claiming both parts of the store came form the same Instr 1387 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1388 Node->getOperand(3)); 1389 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1390 break; 1391 } 1392 break; 1393 } 1394 case ISD::PCMARKER: 1395 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1396 if (Tmp1 != Node->getOperand(0)) 1397 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 1398 break; 1399 case ISD::READCYCLECOUNTER: 1400 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1401 if (Tmp1 != Node->getOperand(0)) { 1402 std::vector<MVT::ValueType> rtypes; 1403 std::vector<SDOperand> rvals; 1404 rtypes.push_back(MVT::i64); 1405 rtypes.push_back(MVT::Other); 1406 rvals.push_back(Tmp1); 1407 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals); 1408 } 1409 1410 // Since rdcc produce two values, make sure to remember that we legalized 1411 // both of them. 1412 AddLegalizedOperand(SDOperand(Node, 0), Result); 1413 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1414 return Result.getValue(Op.ResNo); 1415 1416 case ISD::TRUNCSTORE: { 1417 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1418 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1419 1420 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1421 case Promote: 1422 case Expand: 1423 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 1424 case Legal: 1425 Tmp2 = LegalizeOp(Node->getOperand(1)); 1426 1427 // The only promote case we handle is TRUNCSTORE:i1 X into 1428 // -> TRUNCSTORE:i8 (and X, 1) 1429 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1430 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1431 TargetLowering::Promote) { 1432 // Promote the bool to a mask then store. 1433 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1434 DAG.getConstant(1, Tmp2.getValueType())); 1435 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1436 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1437 1438 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1439 Tmp3 != Node->getOperand(2)) { 1440 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1441 Node->getOperand(3), Node->getOperand(4)); 1442 } 1443 1444 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT(); 1445 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) { 1446 default: assert(0 && "This action is not supported yet!"); 1447 case TargetLowering::Custom: { 1448 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1449 if (Tmp.Val) { 1450 Result = LegalizeOp(Tmp); 1451 break; 1452 } 1453 // FALLTHROUGH if the target thinks it is legal. 1454 } 1455 case TargetLowering::Legal: 1456 // Nothing to do. 1457 break; 1458 } 1459 break; 1460 } 1461 break; 1462 } 1463 case ISD::SELECT: 1464 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1465 case Expand: assert(0 && "It's impossible to expand bools"); 1466 case Legal: 1467 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1468 break; 1469 case Promote: 1470 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1471 break; 1472 } 1473 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1474 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1475 1476 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1477 default: assert(0 && "This action is not supported yet!"); 1478 case TargetLowering::Expand: 1479 if (Tmp1.getOpcode() == ISD::SETCC) { 1480 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1481 Tmp2, Tmp3, 1482 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1483 } else { 1484 // Make sure the condition is either zero or one. It may have been 1485 // promoted from something else. 1486 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1487 Result = DAG.getSelectCC(Tmp1, 1488 DAG.getConstant(0, Tmp1.getValueType()), 1489 Tmp2, Tmp3, ISD::SETNE); 1490 } 1491 Result = LegalizeOp(Result); // Relegalize new nodes. 1492 break; 1493 case TargetLowering::Custom: { 1494 SDOperand Tmp = 1495 TLI.LowerOperation(DAG.getNode(ISD::SELECT, Node->getValueType(0), 1496 Tmp1, Tmp2, Tmp3), DAG); 1497 if (Tmp.Val) { 1498 Result = LegalizeOp(Tmp); 1499 break; 1500 } 1501 // FALLTHROUGH if the target thinks it is legal. 1502 } 1503 case TargetLowering::Legal: 1504 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1505 Tmp3 != Node->getOperand(2)) 1506 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 1507 Tmp1, Tmp2, Tmp3); 1508 break; 1509 case TargetLowering::Promote: { 1510 MVT::ValueType NVT = 1511 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1512 unsigned ExtOp, TruncOp; 1513 if (MVT::isInteger(Tmp2.getValueType())) { 1514 ExtOp = ISD::ANY_EXTEND; 1515 TruncOp = ISD::TRUNCATE; 1516 } else { 1517 ExtOp = ISD::FP_EXTEND; 1518 TruncOp = ISD::FP_ROUND; 1519 } 1520 // Promote each of the values to the new type. 1521 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1522 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1523 // Perform the larger operation, then round down. 1524 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1525 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1526 break; 1527 } 1528 } 1529 break; 1530 case ISD::SELECT_CC: 1531 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1532 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1533 1534 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1535 // Everything is legal, see if we should expand this op or something. 1536 switch (TLI.getOperationAction(ISD::SELECT_CC, 1537 Node->getOperand(0).getValueType())) { 1538 default: assert(0 && "This action is not supported yet!"); 1539 case TargetLowering::Custom: { 1540 SDOperand Tmp = 1541 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), 1542 Node->getOperand(0), 1543 Node->getOperand(1), Tmp3, Tmp4, 1544 Node->getOperand(4)), DAG); 1545 if (Tmp.Val) { 1546 Result = LegalizeOp(Tmp); 1547 break; 1548 } 1549 } // FALLTHROUGH if the target can't lower this operation after all. 1550 case TargetLowering::Legal: 1551 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1552 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1553 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1554 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { 1555 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1,Tmp2, 1556 Tmp3, Tmp4, Node->getOperand(4)); 1557 } 1558 break; 1559 } 1560 break; 1561 } else { 1562 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1563 Node->getOperand(0), // LHS 1564 Node->getOperand(1), // RHS 1565 Node->getOperand(4))); 1566 // If we get a SETCC back from legalizing the SETCC node we just 1567 // created, then use its LHS, RHS, and CC directly in creating a new 1568 // node. Otherwise, select between the true and false value based on 1569 // comparing the result of the legalized with zero. 1570 if (Tmp1.getOpcode() == ISD::SETCC) { 1571 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1572 Tmp1.getOperand(0), Tmp1.getOperand(1), 1573 Tmp3, Tmp4, Tmp1.getOperand(2)); 1574 } else { 1575 Result = DAG.getSelectCC(Tmp1, 1576 DAG.getConstant(0, Tmp1.getValueType()), 1577 Tmp3, Tmp4, ISD::SETNE); 1578 } 1579 } 1580 break; 1581 case ISD::SETCC: 1582 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1583 case Legal: 1584 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1585 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1586 break; 1587 case Promote: 1588 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1589 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1590 1591 // If this is an FP compare, the operands have already been extended. 1592 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1593 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1594 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1595 1596 // Otherwise, we have to insert explicit sign or zero extends. Note 1597 // that we could insert sign extends for ALL conditions, but zero extend 1598 // is cheaper on many machines (an AND instead of two shifts), so prefer 1599 // it. 1600 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1601 default: assert(0 && "Unknown integer comparison!"); 1602 case ISD::SETEQ: 1603 case ISD::SETNE: 1604 case ISD::SETUGE: 1605 case ISD::SETUGT: 1606 case ISD::SETULE: 1607 case ISD::SETULT: 1608 // ALL of these operations will work if we either sign or zero extend 1609 // the operands (including the unsigned comparisons!). Zero extend is 1610 // usually a simpler/cheaper operation, so prefer it. 1611 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1612 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1613 break; 1614 case ISD::SETGE: 1615 case ISD::SETGT: 1616 case ISD::SETLT: 1617 case ISD::SETLE: 1618 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1619 DAG.getValueType(VT)); 1620 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1621 DAG.getValueType(VT)); 1622 break; 1623 } 1624 } 1625 break; 1626 case Expand: 1627 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1628 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1629 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1630 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1631 case ISD::SETEQ: 1632 case ISD::SETNE: 1633 if (RHSLo == RHSHi) 1634 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1635 if (RHSCST->isAllOnesValue()) { 1636 // Comparison to -1. 1637 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1638 Tmp2 = RHSLo; 1639 break; 1640 } 1641 1642 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1643 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1644 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1645 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1646 break; 1647 default: 1648 // If this is a comparison of the sign bit, just look at the top part. 1649 // X > -1, x < 0 1650 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1651 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1652 CST->getValue() == 0) || // X < 0 1653 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1654 (CST->isAllOnesValue()))) { // X > -1 1655 Tmp1 = LHSHi; 1656 Tmp2 = RHSHi; 1657 break; 1658 } 1659 1660 // FIXME: This generated code sucks. 1661 ISD::CondCode LowCC; 1662 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1663 default: assert(0 && "Unknown integer setcc!"); 1664 case ISD::SETLT: 1665 case ISD::SETULT: LowCC = ISD::SETULT; break; 1666 case ISD::SETGT: 1667 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1668 case ISD::SETLE: 1669 case ISD::SETULE: LowCC = ISD::SETULE; break; 1670 case ISD::SETGE: 1671 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1672 } 1673 1674 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1675 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1676 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1677 1678 // NOTE: on targets without efficient SELECT of bools, we can always use 1679 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1680 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1681 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1682 Node->getOperand(2)); 1683 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1684 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1685 Result, Tmp1, Tmp2)); 1686 AddLegalizedOperand(SDOperand(Node, 0), Result); 1687 return Result; 1688 } 1689 } 1690 1691 switch(TLI.getOperationAction(ISD::SETCC, 1692 Node->getOperand(0).getValueType())) { 1693 default: 1694 assert(0 && "Cannot handle this action for SETCC yet!"); 1695 break; 1696 case TargetLowering::Promote: { 1697 // First step, figure out the appropriate operation to use. 1698 // Allow SETCC to not be supported for all legal data types 1699 // Mostly this targets FP 1700 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1701 MVT::ValueType OldVT = NewInTy; 1702 1703 // Scan for the appropriate larger type to use. 1704 while (1) { 1705 NewInTy = (MVT::ValueType)(NewInTy+1); 1706 1707 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1708 "Fell off of the edge of the integer world"); 1709 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1710 "Fell off of the edge of the floating point world"); 1711 1712 // If the target supports SETCC of this type, use it. 1713 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 1714 break; 1715 } 1716 if (MVT::isInteger(NewInTy)) 1717 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1718 else { 1719 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1720 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1721 } 1722 1723 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1724 Node->getOperand(2)); 1725 break; 1726 } 1727 case TargetLowering::Custom: { 1728 SDOperand Tmp = 1729 TLI.LowerOperation(DAG.getNode(ISD::SETCC, Node->getValueType(0), 1730 Tmp1, Tmp2, Node->getOperand(2)), DAG); 1731 if (Tmp.Val) { 1732 Result = LegalizeOp(Tmp); 1733 break; 1734 } 1735 // FALLTHROUGH if the target thinks it is legal. 1736 } 1737 case TargetLowering::Legal: 1738 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1739 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1740 Node->getOperand(2)); 1741 break; 1742 case TargetLowering::Expand: 1743 // Expand a setcc node into a select_cc of the same condition, lhs, and 1744 // rhs that selects between const 1 (true) and const 0 (false). 1745 MVT::ValueType VT = Node->getValueType(0); 1746 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1747 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1748 Node->getOperand(2)); 1749 Result = LegalizeOp(Result); 1750 break; 1751 } 1752 break; 1753 1754 case ISD::MEMSET: 1755 case ISD::MEMCPY: 1756 case ISD::MEMMOVE: { 1757 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1758 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1759 1760 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1761 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1762 case Expand: assert(0 && "Cannot expand a byte!"); 1763 case Legal: 1764 Tmp3 = LegalizeOp(Node->getOperand(2)); 1765 break; 1766 case Promote: 1767 Tmp3 = PromoteOp(Node->getOperand(2)); 1768 break; 1769 } 1770 } else { 1771 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1772 } 1773 1774 SDOperand Tmp4; 1775 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1776 case Expand: { 1777 // Length is too big, just take the lo-part of the length. 1778 SDOperand HiPart; 1779 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1780 break; 1781 } 1782 case Legal: 1783 Tmp4 = LegalizeOp(Node->getOperand(3)); 1784 break; 1785 case Promote: 1786 Tmp4 = PromoteOp(Node->getOperand(3)); 1787 break; 1788 } 1789 1790 SDOperand Tmp5; 1791 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1792 case Expand: assert(0 && "Cannot expand this yet!"); 1793 case Legal: 1794 Tmp5 = LegalizeOp(Node->getOperand(4)); 1795 break; 1796 case Promote: 1797 Tmp5 = PromoteOp(Node->getOperand(4)); 1798 break; 1799 } 1800 1801 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1802 default: assert(0 && "This action not implemented for this operation!"); 1803 case TargetLowering::Custom: { 1804 SDOperand Tmp = 1805 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 1806 Tmp2, Tmp3, Tmp4, Tmp5), DAG); 1807 if (Tmp.Val) { 1808 Result = LegalizeOp(Tmp); 1809 break; 1810 } 1811 // FALLTHROUGH if the target thinks it is legal. 1812 } 1813 case TargetLowering::Legal: 1814 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1815 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 1816 Tmp5 != Node->getOperand(4)) { 1817 std::vector<SDOperand> Ops; 1818 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 1819 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 1820 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 1821 } 1822 break; 1823 case TargetLowering::Expand: { 1824 // Otherwise, the target does not support this operation. Lower the 1825 // operation to an explicit libcall as appropriate. 1826 MVT::ValueType IntPtr = TLI.getPointerTy(); 1827 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1828 std::vector<std::pair<SDOperand, const Type*> > Args; 1829 1830 const char *FnName = 0; 1831 if (Node->getOpcode() == ISD::MEMSET) { 1832 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1833 // Extend the ubyte argument to be an int value for the call. 1834 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1835 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1836 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1837 1838 FnName = "memset"; 1839 } else if (Node->getOpcode() == ISD::MEMCPY || 1840 Node->getOpcode() == ISD::MEMMOVE) { 1841 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1842 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1843 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1844 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1845 } else { 1846 assert(0 && "Unknown op!"); 1847 } 1848 1849 std::pair<SDOperand,SDOperand> CallResult = 1850 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1851 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1852 Result = LegalizeOp(CallResult.second); 1853 break; 1854 } 1855 } 1856 break; 1857 } 1858 1859 case ISD::READPORT: 1860 Tmp1 = LegalizeOp(Node->getOperand(0)); 1861 Tmp2 = LegalizeOp(Node->getOperand(1)); 1862 1863 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1864 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1865 std::vector<SDOperand> Ops; 1866 Ops.push_back(Tmp1); 1867 Ops.push_back(Tmp2); 1868 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1869 } else 1870 Result = SDOperand(Node, 0); 1871 // Since these produce two values, make sure to remember that we legalized 1872 // both of them. 1873 AddLegalizedOperand(SDOperand(Node, 0), Result); 1874 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1875 return Result.getValue(Op.ResNo); 1876 case ISD::WRITEPORT: 1877 Tmp1 = LegalizeOp(Node->getOperand(0)); 1878 Tmp2 = LegalizeOp(Node->getOperand(1)); 1879 Tmp3 = LegalizeOp(Node->getOperand(2)); 1880 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1881 Tmp3 != Node->getOperand(2)) 1882 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1883 break; 1884 1885 case ISD::READIO: 1886 Tmp1 = LegalizeOp(Node->getOperand(0)); 1887 Tmp2 = LegalizeOp(Node->getOperand(1)); 1888 1889 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1890 case TargetLowering::Custom: 1891 default: assert(0 && "This action not implemented for this operation!"); 1892 case TargetLowering::Legal: 1893 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1894 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1895 std::vector<SDOperand> Ops; 1896 Ops.push_back(Tmp1); 1897 Ops.push_back(Tmp2); 1898 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1899 } else 1900 Result = SDOperand(Node, 0); 1901 break; 1902 case TargetLowering::Expand: 1903 // Replace this with a load from memory. 1904 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 1905 Node->getOperand(1), DAG.getSrcValue(NULL)); 1906 Result = LegalizeOp(Result); 1907 break; 1908 } 1909 1910 // Since these produce two values, make sure to remember that we legalized 1911 // both of them. 1912 AddLegalizedOperand(SDOperand(Node, 0), Result); 1913 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1914 return Result.getValue(Op.ResNo); 1915 1916 case ISD::WRITEIO: 1917 Tmp1 = LegalizeOp(Node->getOperand(0)); 1918 Tmp2 = LegalizeOp(Node->getOperand(1)); 1919 Tmp3 = LegalizeOp(Node->getOperand(2)); 1920 1921 switch (TLI.getOperationAction(Node->getOpcode(), 1922 Node->getOperand(1).getValueType())) { 1923 case TargetLowering::Custom: 1924 default: assert(0 && "This action not implemented for this operation!"); 1925 case TargetLowering::Legal: 1926 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1927 Tmp3 != Node->getOperand(2)) 1928 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1929 break; 1930 case TargetLowering::Expand: 1931 // Replace this with a store to memory. 1932 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 1933 Node->getOperand(1), Node->getOperand(2), 1934 DAG.getSrcValue(NULL)); 1935 Result = LegalizeOp(Result); 1936 break; 1937 } 1938 break; 1939 1940 case ISD::ADD_PARTS: 1941 case ISD::SUB_PARTS: 1942 case ISD::SHL_PARTS: 1943 case ISD::SRA_PARTS: 1944 case ISD::SRL_PARTS: { 1945 std::vector<SDOperand> Ops; 1946 bool Changed = false; 1947 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1948 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1949 Changed |= Ops.back() != Node->getOperand(i); 1950 } 1951 if (Changed) { 1952 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1953 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 1954 } 1955 1956 // Since these produce multiple values, make sure to remember that we 1957 // legalized all of them. 1958 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1959 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1960 return Result.getValue(Op.ResNo); 1961 } 1962 1963 // Binary operators 1964 case ISD::ADD: 1965 case ISD::SUB: 1966 case ISD::MUL: 1967 case ISD::MULHS: 1968 case ISD::MULHU: 1969 case ISD::UDIV: 1970 case ISD::SDIV: 1971 case ISD::AND: 1972 case ISD::OR: 1973 case ISD::XOR: 1974 case ISD::SHL: 1975 case ISD::SRL: 1976 case ISD::SRA: 1977 case ISD::FADD: 1978 case ISD::FSUB: 1979 case ISD::FMUL: 1980 case ISD::FDIV: 1981 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1982 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1983 case Expand: assert(0 && "Not possible"); 1984 case Legal: 1985 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1986 break; 1987 case Promote: 1988 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 1989 break; 1990 } 1991 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1992 case TargetLowering::Custom: { 1993 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2); 1994 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1995 if (Tmp.Val) { 1996 Tmp = LegalizeOp(Tmp); // Relegalize input. 1997 AddLegalizedOperand(Op, Tmp); 1998 return Tmp; 1999 } //else it was considered legal and we fall through 2000 } 2001 case TargetLowering::Legal: 2002 if (Tmp1 != Node->getOperand(0) || 2003 Tmp2 != Node->getOperand(1)) 2004 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 2005 break; 2006 default: 2007 assert(0 && "Operation not supported"); 2008 } 2009 break; 2010 2011 case ISD::BUILD_PAIR: { 2012 MVT::ValueType PairTy = Node->getValueType(0); 2013 // TODO: handle the case where the Lo and Hi operands are not of legal type 2014 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2015 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2016 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2017 case TargetLowering::Legal: 2018 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2019 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2020 break; 2021 case TargetLowering::Promote: 2022 case TargetLowering::Custom: 2023 assert(0 && "Cannot promote/custom this yet!"); 2024 case TargetLowering::Expand: 2025 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2026 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2027 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2028 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2029 TLI.getShiftAmountTy())); 2030 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2)); 2031 break; 2032 } 2033 break; 2034 } 2035 2036 case ISD::UREM: 2037 case ISD::SREM: 2038 case ISD::FREM: 2039 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2040 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2041 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2042 case TargetLowering::Custom: { 2043 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2); 2044 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 2045 if (Tmp.Val) { 2046 Tmp = LegalizeOp(Tmp); // Relegalize input. 2047 AddLegalizedOperand(Op, Tmp); 2048 return Tmp; 2049 } //else it was considered legal and we fall through 2050 } 2051 case TargetLowering::Legal: 2052 if (Tmp1 != Node->getOperand(0) || 2053 Tmp2 != Node->getOperand(1)) 2054 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2055 Tmp2); 2056 break; 2057 case TargetLowering::Promote: 2058 assert(0 && "Cannot promote handle this yet!"); 2059 case TargetLowering::Expand: 2060 if (MVT::isInteger(Node->getValueType(0))) { 2061 MVT::ValueType VT = Node->getValueType(0); 2062 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2063 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 2064 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2065 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2066 } else { 2067 // Floating point mod -> fmod libcall. 2068 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 2069 SDOperand Dummy; 2070 Result = ExpandLibCall(FnName, Node, Dummy); 2071 } 2072 break; 2073 } 2074 break; 2075 2076 case ISD::CTPOP: 2077 case ISD::CTTZ: 2078 case ISD::CTLZ: 2079 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2080 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2081 case TargetLowering::Legal: 2082 if (Tmp1 != Node->getOperand(0)) 2083 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2084 break; 2085 case TargetLowering::Promote: { 2086 MVT::ValueType OVT = Tmp1.getValueType(); 2087 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2088 2089 // Zero extend the argument. 2090 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2091 // Perform the larger operation, then subtract if needed. 2092 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2093 switch(Node->getOpcode()) 2094 { 2095 case ISD::CTPOP: 2096 Result = Tmp1; 2097 break; 2098 case ISD::CTTZ: 2099 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2100 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2101 DAG.getConstant(getSizeInBits(NVT), NVT), 2102 ISD::SETEQ); 2103 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2104 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 2105 break; 2106 case ISD::CTLZ: 2107 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2108 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2109 DAG.getConstant(getSizeInBits(NVT) - 2110 getSizeInBits(OVT), NVT)); 2111 break; 2112 } 2113 break; 2114 } 2115 case TargetLowering::Custom: 2116 assert(0 && "Cannot custom handle this yet!"); 2117 case TargetLowering::Expand: 2118 switch(Node->getOpcode()) 2119 { 2120 case ISD::CTPOP: { 2121 static const uint64_t mask[6] = { 2122 0x5555555555555555ULL, 0x3333333333333333ULL, 2123 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2124 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2125 }; 2126 MVT::ValueType VT = Tmp1.getValueType(); 2127 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 2128 unsigned len = getSizeInBits(VT); 2129 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2130 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2131 Tmp2 = DAG.getConstant(mask[i], VT); 2132 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2133 Tmp1 = DAG.getNode(ISD::ADD, VT, 2134 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 2135 DAG.getNode(ISD::AND, VT, 2136 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 2137 Tmp2)); 2138 } 2139 Result = Tmp1; 2140 break; 2141 } 2142 case ISD::CTLZ: { 2143 /* for now, we do this: 2144 x = x | (x >> 1); 2145 x = x | (x >> 2); 2146 ... 2147 x = x | (x >>16); 2148 x = x | (x >>32); // for 64-bit input 2149 return popcount(~x); 2150 2151 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ 2152 MVT::ValueType VT = Tmp1.getValueType(); 2153 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 2154 unsigned len = getSizeInBits(VT); 2155 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2156 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2157 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, 2158 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); 2159 } 2160 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); 2161 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 2162 break; 2163 } 2164 case ISD::CTTZ: { 2165 // for now, we use: { return popcount(~x & (x - 1)); } 2166 // unless the target has ctlz but not ctpop, in which case we use: 2167 // { return 32 - nlz(~x & (x-1)); } 2168 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2169 MVT::ValueType VT = Tmp1.getValueType(); 2170 Tmp2 = DAG.getConstant(~0ULL, VT); 2171 Tmp3 = DAG.getNode(ISD::AND, VT, 2172 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), 2173 DAG.getNode(ISD::SUB, VT, Tmp1, 2174 DAG.getConstant(1, VT))); 2175 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead 2176 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 2177 TLI.isOperationLegal(ISD::CTLZ, VT)) { 2178 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, 2179 DAG.getConstant(getSizeInBits(VT), VT), 2180 DAG.getNode(ISD::CTLZ, VT, Tmp3))); 2181 } else { 2182 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 2183 } 2184 break; 2185 } 2186 default: 2187 assert(0 && "Cannot expand this yet!"); 2188 break; 2189 } 2190 break; 2191 } 2192 break; 2193 2194 // Unary operators 2195 case ISD::FABS: 2196 case ISD::FNEG: 2197 case ISD::FSQRT: 2198 case ISD::FSIN: 2199 case ISD::FCOS: 2200 Tmp1 = LegalizeOp(Node->getOperand(0)); 2201 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2202 case TargetLowering::Legal: 2203 if (Tmp1 != Node->getOperand(0)) 2204 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2205 break; 2206 case TargetLowering::Promote: 2207 case TargetLowering::Custom: 2208 assert(0 && "Cannot promote/custom handle this yet!"); 2209 case TargetLowering::Expand: 2210 switch(Node->getOpcode()) { 2211 case ISD::FNEG: { 2212 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2213 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2214 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0), 2215 Tmp2, Tmp1)); 2216 break; 2217 } 2218 case ISD::FABS: { 2219 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2220 MVT::ValueType VT = Node->getValueType(0); 2221 Tmp2 = DAG.getConstantFP(0.0, VT); 2222 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2223 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2224 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2225 Result = LegalizeOp(Result); 2226 break; 2227 } 2228 case ISD::FSQRT: 2229 case ISD::FSIN: 2230 case ISD::FCOS: { 2231 MVT::ValueType VT = Node->getValueType(0); 2232 const char *FnName = 0; 2233 switch(Node->getOpcode()) { 2234 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 2235 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 2236 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 2237 default: assert(0 && "Unreachable!"); 2238 } 2239 SDOperand Dummy; 2240 Result = ExpandLibCall(FnName, Node, Dummy); 2241 break; 2242 } 2243 default: 2244 assert(0 && "Unreachable!"); 2245 } 2246 break; 2247 } 2248 break; 2249 2250 case ISD::BIT_CONVERT: 2251 if (!isTypeLegal(Node->getOperand(0).getValueType())) 2252 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2253 else { 2254 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2255 Node->getOperand(0).getValueType())) { 2256 default: assert(0 && "Unknown operation action!"); 2257 case TargetLowering::Expand: 2258 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2259 break; 2260 case TargetLowering::Legal: 2261 Tmp1 = LegalizeOp(Node->getOperand(0)); 2262 if (Tmp1 != Node->getOperand(0)) 2263 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Tmp1); 2264 break; 2265 } 2266 } 2267 break; 2268 // Conversion operators. The source and destination have different types. 2269 case ISD::SINT_TO_FP: 2270 case ISD::UINT_TO_FP: { 2271 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2272 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2273 case Legal: 2274 switch (TLI.getOperationAction(Node->getOpcode(), 2275 Node->getOperand(0).getValueType())) { 2276 default: assert(0 && "Unknown operation action!"); 2277 case TargetLowering::Expand: 2278 Result = ExpandLegalINT_TO_FP(isSigned, 2279 LegalizeOp(Node->getOperand(0)), 2280 Node->getValueType(0)); 2281 AddLegalizedOperand(Op, Result); 2282 return Result; 2283 case TargetLowering::Promote: 2284 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2285 Node->getValueType(0), 2286 isSigned); 2287 AddLegalizedOperand(Op, Result); 2288 return Result; 2289 case TargetLowering::Legal: 2290 break; 2291 case TargetLowering::Custom: { 2292 Tmp1 = LegalizeOp(Node->getOperand(0)); 2293 SDOperand Tmp = 2294 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2295 Tmp = TLI.LowerOperation(Tmp, DAG); 2296 if (Tmp.Val) { 2297 Tmp = LegalizeOp(Tmp); // Relegalize input. 2298 AddLegalizedOperand(Op, Tmp); 2299 return Tmp; 2300 } else { 2301 assert(0 && "Target Must Lower this"); 2302 } 2303 } 2304 } 2305 2306 Tmp1 = LegalizeOp(Node->getOperand(0)); 2307 if (Tmp1 != Node->getOperand(0)) 2308 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2309 break; 2310 case Expand: 2311 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2312 Node->getValueType(0), Node->getOperand(0)); 2313 break; 2314 case Promote: 2315 if (isSigned) { 2316 Result = PromoteOp(Node->getOperand(0)); 2317 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2318 Result, DAG.getValueType(Node->getOperand(0).getValueType())); 2319 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 2320 } else { 2321 Result = PromoteOp(Node->getOperand(0)); 2322 Result = DAG.getZeroExtendInReg(Result, 2323 Node->getOperand(0).getValueType()); 2324 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 2325 } 2326 break; 2327 } 2328 break; 2329 } 2330 case ISD::TRUNCATE: 2331 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2332 case Legal: 2333 Tmp1 = LegalizeOp(Node->getOperand(0)); 2334 if (Tmp1 != Node->getOperand(0)) 2335 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2336 break; 2337 case Expand: 2338 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2339 2340 // Since the result is legal, we should just be able to truncate the low 2341 // part of the source. 2342 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2343 break; 2344 case Promote: 2345 Result = PromoteOp(Node->getOperand(0)); 2346 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2347 break; 2348 } 2349 break; 2350 2351 case ISD::FP_TO_SINT: 2352 case ISD::FP_TO_UINT: 2353 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2354 case Legal: 2355 Tmp1 = LegalizeOp(Node->getOperand(0)); 2356 2357 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2358 default: assert(0 && "Unknown operation action!"); 2359 case TargetLowering::Expand: 2360 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2361 SDOperand True, False; 2362 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2363 MVT::ValueType NVT = Node->getValueType(0); 2364 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2365 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2366 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2367 Node->getOperand(0), Tmp2, ISD::SETLT); 2368 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2369 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2370 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2371 Tmp2)); 2372 False = DAG.getNode(ISD::XOR, NVT, False, 2373 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2374 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False)); 2375 AddLegalizedOperand(SDOperand(Node, 0), Result); 2376 return Result; 2377 } else { 2378 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2379 } 2380 break; 2381 case TargetLowering::Promote: 2382 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2383 Node->getOpcode() == ISD::FP_TO_SINT); 2384 AddLegalizedOperand(Op, Result); 2385 return Result; 2386 case TargetLowering::Custom: { 2387 SDOperand Tmp = 2388 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2389 Tmp = TLI.LowerOperation(Tmp, DAG); 2390 if (Tmp.Val) { 2391 Tmp = LegalizeOp(Tmp); 2392 AddLegalizedOperand(Op, Tmp); 2393 return Tmp; 2394 } else { 2395 // The target thinks this is legal afterall. 2396 break; 2397 } 2398 } 2399 case TargetLowering::Legal: 2400 break; 2401 } 2402 2403 if (Tmp1 != Node->getOperand(0)) 2404 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2405 break; 2406 case Expand: 2407 assert(0 && "Shouldn't need to expand other operators here!"); 2408 case Promote: 2409 Result = PromoteOp(Node->getOperand(0)); 2410 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2411 break; 2412 } 2413 break; 2414 2415 case ISD::ANY_EXTEND: 2416 case ISD::ZERO_EXTEND: 2417 case ISD::SIGN_EXTEND: 2418 case ISD::FP_EXTEND: 2419 case ISD::FP_ROUND: 2420 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2421 case Legal: 2422 Tmp1 = LegalizeOp(Node->getOperand(0)); 2423 if (Tmp1 != Node->getOperand(0)) 2424 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2425 break; 2426 case Expand: 2427 assert(0 && "Shouldn't need to expand other operators here!"); 2428 2429 case Promote: 2430 switch (Node->getOpcode()) { 2431 case ISD::ANY_EXTEND: 2432 Result = PromoteOp(Node->getOperand(0)); 2433 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2434 break; 2435 case ISD::ZERO_EXTEND: 2436 Result = PromoteOp(Node->getOperand(0)); 2437 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2438 Result = DAG.getZeroExtendInReg(Result, 2439 Node->getOperand(0).getValueType()); 2440 break; 2441 case ISD::SIGN_EXTEND: 2442 Result = PromoteOp(Node->getOperand(0)); 2443 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2444 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2445 Result, 2446 DAG.getValueType(Node->getOperand(0).getValueType())); 2447 break; 2448 case ISD::FP_EXTEND: 2449 Result = PromoteOp(Node->getOperand(0)); 2450 if (Result.getValueType() != Op.getValueType()) 2451 // Dynamically dead while we have only 2 FP types. 2452 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2453 break; 2454 case ISD::FP_ROUND: 2455 Result = PromoteOp(Node->getOperand(0)); 2456 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2457 break; 2458 } 2459 } 2460 break; 2461 case ISD::FP_ROUND_INREG: 2462 case ISD::SIGN_EXTEND_INREG: { 2463 Tmp1 = LegalizeOp(Node->getOperand(0)); 2464 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2465 2466 // If this operation is not supported, convert it to a shl/shr or load/store 2467 // pair. 2468 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2469 default: assert(0 && "This action not supported for this op yet!"); 2470 case TargetLowering::Legal: 2471 if (Tmp1 != Node->getOperand(0)) 2472 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2473 DAG.getValueType(ExtraVT)); 2474 break; 2475 case TargetLowering::Expand: 2476 // If this is an integer extend and shifts are supported, do that. 2477 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2478 // NOTE: we could fall back on load/store here too for targets without 2479 // SAR. However, it is doubtful that any exist. 2480 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2481 MVT::getSizeInBits(ExtraVT); 2482 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2483 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2484 Node->getOperand(0), ShiftCst); 2485 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2486 Result, ShiftCst); 2487 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2488 // The only way we can lower this is to turn it into a STORETRUNC, 2489 // EXTLOAD pair, targetting a temporary location (a stack slot). 2490 2491 // NOTE: there is a choice here between constantly creating new stack 2492 // slots and always reusing the same one. We currently always create 2493 // new ones, as reuse may inhibit scheduling. 2494 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2495 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2496 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2497 MachineFunction &MF = DAG.getMachineFunction(); 2498 int SSFI = 2499 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2500 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2501 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2502 Node->getOperand(0), StackSlot, 2503 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2504 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2505 Result, StackSlot, DAG.getSrcValue(NULL), 2506 ExtraVT); 2507 } else { 2508 assert(0 && "Unknown op"); 2509 } 2510 Result = LegalizeOp(Result); 2511 break; 2512 } 2513 break; 2514 } 2515 } 2516 2517 // Note that LegalizeOp may be reentered even from single-use nodes, which 2518 // means that we always must cache transformed nodes. 2519 AddLegalizedOperand(Op, Result); 2520 return Result; 2521} 2522 2523/// PromoteOp - Given an operation that produces a value in an invalid type, 2524/// promote it to compute the value into a larger type. The produced value will 2525/// have the correct bits for the low portion of the register, but no guarantee 2526/// is made about the top bits: it may be zero, sign-extended, or garbage. 2527SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2528 MVT::ValueType VT = Op.getValueType(); 2529 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2530 assert(getTypeAction(VT) == Promote && 2531 "Caller should expand or legalize operands that are not promotable!"); 2532 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2533 "Cannot promote to smaller type!"); 2534 2535 SDOperand Tmp1, Tmp2, Tmp3; 2536 2537 SDOperand Result; 2538 SDNode *Node = Op.Val; 2539 2540 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2541 if (I != PromotedNodes.end()) return I->second; 2542 2543 // Promotion needs an optimization step to clean up after it, and is not 2544 // careful to avoid operations the target does not support. Make sure that 2545 // all generated operations are legalized in the next iteration. 2546 NeedsAnotherIteration = true; 2547 2548 switch (Node->getOpcode()) { 2549 case ISD::CopyFromReg: 2550 assert(0 && "CopyFromReg must be legal!"); 2551 default: 2552 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2553 assert(0 && "Do not know how to promote this operator!"); 2554 abort(); 2555 case ISD::UNDEF: 2556 Result = DAG.getNode(ISD::UNDEF, NVT); 2557 break; 2558 case ISD::Constant: 2559 if (VT != MVT::i1) 2560 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2561 else 2562 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2563 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2564 break; 2565 case ISD::ConstantFP: 2566 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2567 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2568 break; 2569 2570 case ISD::SETCC: 2571 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2572 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2573 Node->getOperand(1), Node->getOperand(2)); 2574 Result = LegalizeOp(Result); 2575 break; 2576 2577 case ISD::TRUNCATE: 2578 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2579 case Legal: 2580 Result = LegalizeOp(Node->getOperand(0)); 2581 assert(Result.getValueType() >= NVT && 2582 "This truncation doesn't make sense!"); 2583 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2584 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2585 break; 2586 case Promote: 2587 // The truncation is not required, because we don't guarantee anything 2588 // about high bits anyway. 2589 Result = PromoteOp(Node->getOperand(0)); 2590 break; 2591 case Expand: 2592 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2593 // Truncate the low part of the expanded value to the result type 2594 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2595 } 2596 break; 2597 case ISD::SIGN_EXTEND: 2598 case ISD::ZERO_EXTEND: 2599 case ISD::ANY_EXTEND: 2600 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2601 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2602 case Legal: 2603 // Input is legal? Just do extend all the way to the larger type. 2604 Result = LegalizeOp(Node->getOperand(0)); 2605 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2606 break; 2607 case Promote: 2608 // Promote the reg if it's smaller. 2609 Result = PromoteOp(Node->getOperand(0)); 2610 // The high bits are not guaranteed to be anything. Insert an extend. 2611 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2612 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2613 DAG.getValueType(Node->getOperand(0).getValueType())); 2614 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2615 Result = DAG.getZeroExtendInReg(Result, 2616 Node->getOperand(0).getValueType()); 2617 break; 2618 } 2619 break; 2620 case ISD::BIT_CONVERT: 2621 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2622 Result = PromoteOp(Result); 2623 break; 2624 2625 case ISD::FP_EXTEND: 2626 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2627 case ISD::FP_ROUND: 2628 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2629 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2630 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2631 case Legal: 2632 // Input is legal? Do an FP_ROUND_INREG. 2633 Result = LegalizeOp(Node->getOperand(0)); 2634 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2635 DAG.getValueType(VT)); 2636 break; 2637 } 2638 break; 2639 2640 case ISD::SINT_TO_FP: 2641 case ISD::UINT_TO_FP: 2642 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2643 case Legal: 2644 Result = LegalizeOp(Node->getOperand(0)); 2645 // No extra round required here. 2646 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2647 break; 2648 2649 case Promote: 2650 Result = PromoteOp(Node->getOperand(0)); 2651 if (Node->getOpcode() == ISD::SINT_TO_FP) 2652 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2653 Result, 2654 DAG.getValueType(Node->getOperand(0).getValueType())); 2655 else 2656 Result = DAG.getZeroExtendInReg(Result, 2657 Node->getOperand(0).getValueType()); 2658 // No extra round required here. 2659 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2660 break; 2661 case Expand: 2662 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2663 Node->getOperand(0)); 2664 // Round if we cannot tolerate excess precision. 2665 if (NoExcessFPPrecision) 2666 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2667 DAG.getValueType(VT)); 2668 break; 2669 } 2670 break; 2671 2672 case ISD::SIGN_EXTEND_INREG: 2673 Result = PromoteOp(Node->getOperand(0)); 2674 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2675 Node->getOperand(1)); 2676 break; 2677 case ISD::FP_TO_SINT: 2678 case ISD::FP_TO_UINT: 2679 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2680 case Legal: 2681 Tmp1 = LegalizeOp(Node->getOperand(0)); 2682 break; 2683 case Promote: 2684 // The input result is prerounded, so we don't have to do anything 2685 // special. 2686 Tmp1 = PromoteOp(Node->getOperand(0)); 2687 break; 2688 case Expand: 2689 assert(0 && "not implemented"); 2690 } 2691 // If we're promoting a UINT to a larger size, check to see if the new node 2692 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2693 // we can use that instead. This allows us to generate better code for 2694 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2695 // legal, such as PowerPC. 2696 if (Node->getOpcode() == ISD::FP_TO_UINT && 2697 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2698 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2699 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2700 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2701 } else { 2702 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2703 } 2704 break; 2705 2706 case ISD::FABS: 2707 case ISD::FNEG: 2708 Tmp1 = PromoteOp(Node->getOperand(0)); 2709 assert(Tmp1.getValueType() == NVT); 2710 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2711 // NOTE: we do not have to do any extra rounding here for 2712 // NoExcessFPPrecision, because we know the input will have the appropriate 2713 // precision, and these operations don't modify precision at all. 2714 break; 2715 2716 case ISD::FSQRT: 2717 case ISD::FSIN: 2718 case ISD::FCOS: 2719 Tmp1 = PromoteOp(Node->getOperand(0)); 2720 assert(Tmp1.getValueType() == NVT); 2721 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2722 if(NoExcessFPPrecision) 2723 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2724 DAG.getValueType(VT)); 2725 break; 2726 2727 case ISD::AND: 2728 case ISD::OR: 2729 case ISD::XOR: 2730 case ISD::ADD: 2731 case ISD::SUB: 2732 case ISD::MUL: 2733 // The input may have strange things in the top bits of the registers, but 2734 // these operations don't care. They may have weird bits going out, but 2735 // that too is okay if they are integer operations. 2736 Tmp1 = PromoteOp(Node->getOperand(0)); 2737 Tmp2 = PromoteOp(Node->getOperand(1)); 2738 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2739 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2740 break; 2741 case ISD::FADD: 2742 case ISD::FSUB: 2743 case ISD::FMUL: 2744 // The input may have strange things in the top bits of the registers, but 2745 // these operations don't care. 2746 Tmp1 = PromoteOp(Node->getOperand(0)); 2747 Tmp2 = PromoteOp(Node->getOperand(1)); 2748 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2749 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2750 2751 // Floating point operations will give excess precision that we may not be 2752 // able to tolerate. If we DO allow excess precision, just leave it, 2753 // otherwise excise it. 2754 // FIXME: Why would we need to round FP ops more than integer ones? 2755 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2756 if (NoExcessFPPrecision) 2757 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2758 DAG.getValueType(VT)); 2759 break; 2760 2761 case ISD::SDIV: 2762 case ISD::SREM: 2763 // These operators require that their input be sign extended. 2764 Tmp1 = PromoteOp(Node->getOperand(0)); 2765 Tmp2 = PromoteOp(Node->getOperand(1)); 2766 if (MVT::isInteger(NVT)) { 2767 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2768 DAG.getValueType(VT)); 2769 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2770 DAG.getValueType(VT)); 2771 } 2772 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2773 2774 // Perform FP_ROUND: this is probably overly pessimistic. 2775 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2776 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2777 DAG.getValueType(VT)); 2778 break; 2779 case ISD::FDIV: 2780 case ISD::FREM: 2781 // These operators require that their input be fp extended. 2782 Tmp1 = PromoteOp(Node->getOperand(0)); 2783 Tmp2 = PromoteOp(Node->getOperand(1)); 2784 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2785 2786 // Perform FP_ROUND: this is probably overly pessimistic. 2787 if (NoExcessFPPrecision) 2788 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2789 DAG.getValueType(VT)); 2790 break; 2791 2792 case ISD::UDIV: 2793 case ISD::UREM: 2794 // These operators require that their input be zero extended. 2795 Tmp1 = PromoteOp(Node->getOperand(0)); 2796 Tmp2 = PromoteOp(Node->getOperand(1)); 2797 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2798 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2799 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2800 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2801 break; 2802 2803 case ISD::SHL: 2804 Tmp1 = PromoteOp(Node->getOperand(0)); 2805 Tmp2 = LegalizeOp(Node->getOperand(1)); 2806 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 2807 break; 2808 case ISD::SRA: 2809 // The input value must be properly sign extended. 2810 Tmp1 = PromoteOp(Node->getOperand(0)); 2811 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2812 DAG.getValueType(VT)); 2813 Tmp2 = LegalizeOp(Node->getOperand(1)); 2814 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 2815 break; 2816 case ISD::SRL: 2817 // The input value must be properly zero extended. 2818 Tmp1 = PromoteOp(Node->getOperand(0)); 2819 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2820 Tmp2 = LegalizeOp(Node->getOperand(1)); 2821 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 2822 break; 2823 case ISD::LOAD: 2824 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2825 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2826 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2, 2827 Node->getOperand(2), VT); 2828 // Remember that we legalized the chain. 2829 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2830 break; 2831 case ISD::SEXTLOAD: 2832 case ISD::ZEXTLOAD: 2833 case ISD::EXTLOAD: 2834 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2835 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2836 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2, 2837 Node->getOperand(2), 2838 cast<VTSDNode>(Node->getOperand(3))->getVT()); 2839 // Remember that we legalized the chain. 2840 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2841 break; 2842 case ISD::SELECT: 2843 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2844 case Expand: assert(0 && "It's impossible to expand bools"); 2845 case Legal: 2846 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 2847 break; 2848 case Promote: 2849 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2850 break; 2851 } 2852 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 2853 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 2854 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 2855 break; 2856 case ISD::SELECT_CC: 2857 Tmp2 = PromoteOp(Node->getOperand(2)); // True 2858 Tmp3 = PromoteOp(Node->getOperand(3)); // False 2859 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 2860 Node->getOperand(1), Tmp2, Tmp3, 2861 Node->getOperand(4)); 2862 break; 2863 case ISD::TAILCALL: 2864 case ISD::CALL: { 2865 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2866 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 2867 2868 std::vector<SDOperand> Ops; 2869 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 2870 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2871 2872 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 2873 "Can only promote single result calls"); 2874 std::vector<MVT::ValueType> RetTyVTs; 2875 RetTyVTs.reserve(2); 2876 RetTyVTs.push_back(NVT); 2877 RetTyVTs.push_back(MVT::Other); 2878 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 2879 Node->getOpcode() == ISD::TAILCALL); 2880 Result = SDOperand(NC, 0); 2881 2882 // Insert the new chain mapping. 2883 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2884 break; 2885 } 2886 case ISD::CTPOP: 2887 case ISD::CTTZ: 2888 case ISD::CTLZ: 2889 Tmp1 = Node->getOperand(0); 2890 //Zero extend the argument 2891 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2892 // Perform the larger operation, then subtract if needed. 2893 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2894 switch(Node->getOpcode()) 2895 { 2896 case ISD::CTPOP: 2897 Result = Tmp1; 2898 break; 2899 case ISD::CTTZ: 2900 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2901 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2902 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 2903 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2904 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 2905 break; 2906 case ISD::CTLZ: 2907 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2908 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2909 DAG.getConstant(getSizeInBits(NVT) - 2910 getSizeInBits(VT), NVT)); 2911 break; 2912 } 2913 break; 2914 } 2915 2916 assert(Result.Val && "Didn't set a result!"); 2917 AddPromotedOperand(Op, Result); 2918 return Result; 2919} 2920 2921/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 2922/// The resultant code need not be legal. Note that SrcOp is the input operand 2923/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 2924SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 2925 SDOperand SrcOp) { 2926 // Create the stack frame object. 2927 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2928 unsigned ByteSize = MVT::getSizeInBits(DestVT)/8; 2929 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize); 2930 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 2931 2932 // Emit a store to the stack slot. 2933 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 2934 SrcOp, FIPtr, DAG.getSrcValue(NULL)); 2935 // Result is a load from the stack slot. 2936 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0)); 2937} 2938 2939/// ExpandAddSub - Find a clever way to expand this add operation into 2940/// subcomponents. 2941void SelectionDAGLegalize:: 2942ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 2943 SDOperand &Lo, SDOperand &Hi) { 2944 // Expand the subcomponents. 2945 SDOperand LHSL, LHSH, RHSL, RHSH; 2946 ExpandOp(LHS, LHSL, LHSH); 2947 ExpandOp(RHS, RHSL, RHSH); 2948 2949 std::vector<SDOperand> Ops; 2950 Ops.push_back(LHSL); 2951 Ops.push_back(LHSH); 2952 Ops.push_back(RHSL); 2953 Ops.push_back(RHSH); 2954 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2955 Lo = DAG.getNode(NodeOp, VTs, Ops); 2956 Hi = Lo.getValue(1); 2957} 2958 2959void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 2960 SDOperand Op, SDOperand Amt, 2961 SDOperand &Lo, SDOperand &Hi) { 2962 // Expand the subcomponents. 2963 SDOperand LHSL, LHSH; 2964 ExpandOp(Op, LHSL, LHSH); 2965 2966 std::vector<SDOperand> Ops; 2967 Ops.push_back(LHSL); 2968 Ops.push_back(LHSH); 2969 Ops.push_back(Amt); 2970 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2971 Lo = DAG.getNode(NodeOp, VTs, Ops); 2972 Hi = Lo.getValue(1); 2973} 2974 2975 2976/// ExpandShift - Try to find a clever way to expand this shift operation out to 2977/// smaller elements. If we can't find a way that is more efficient than a 2978/// libcall on this target, return false. Otherwise, return true with the 2979/// low-parts expanded into Lo and Hi. 2980bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 2981 SDOperand &Lo, SDOperand &Hi) { 2982 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 2983 "This is not a shift!"); 2984 2985 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 2986 SDOperand ShAmt = LegalizeOp(Amt); 2987 MVT::ValueType ShTy = ShAmt.getValueType(); 2988 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 2989 unsigned NVTBits = MVT::getSizeInBits(NVT); 2990 2991 // Handle the case when Amt is an immediate. Other cases are currently broken 2992 // and are disabled. 2993 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 2994 unsigned Cst = CN->getValue(); 2995 // Expand the incoming operand to be shifted, so that we have its parts 2996 SDOperand InL, InH; 2997 ExpandOp(Op, InL, InH); 2998 switch(Opc) { 2999 case ISD::SHL: 3000 if (Cst > VTBits) { 3001 Lo = DAG.getConstant(0, NVT); 3002 Hi = DAG.getConstant(0, NVT); 3003 } else if (Cst > NVTBits) { 3004 Lo = DAG.getConstant(0, NVT); 3005 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 3006 } else if (Cst == NVTBits) { 3007 Lo = DAG.getConstant(0, NVT); 3008 Hi = InL; 3009 } else { 3010 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 3011 Hi = DAG.getNode(ISD::OR, NVT, 3012 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 3013 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 3014 } 3015 return true; 3016 case ISD::SRL: 3017 if (Cst > VTBits) { 3018 Lo = DAG.getConstant(0, NVT); 3019 Hi = DAG.getConstant(0, NVT); 3020 } else if (Cst > NVTBits) { 3021 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 3022 Hi = DAG.getConstant(0, NVT); 3023 } else if (Cst == NVTBits) { 3024 Lo = InH; 3025 Hi = DAG.getConstant(0, NVT); 3026 } else { 3027 Lo = DAG.getNode(ISD::OR, NVT, 3028 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3029 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3030 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 3031 } 3032 return true; 3033 case ISD::SRA: 3034 if (Cst > VTBits) { 3035 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 3036 DAG.getConstant(NVTBits-1, ShTy)); 3037 } else if (Cst > NVTBits) { 3038 Lo = DAG.getNode(ISD::SRA, NVT, InH, 3039 DAG.getConstant(Cst-NVTBits, ShTy)); 3040 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3041 DAG.getConstant(NVTBits-1, ShTy)); 3042 } else if (Cst == NVTBits) { 3043 Lo = InH; 3044 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3045 DAG.getConstant(NVTBits-1, ShTy)); 3046 } else { 3047 Lo = DAG.getNode(ISD::OR, NVT, 3048 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3049 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3050 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 3051 } 3052 return true; 3053 } 3054 } 3055 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 3056 // so disable it for now. Currently targets are handling this via SHL_PARTS 3057 // and friends. 3058 return false; 3059 3060 // If we have an efficient select operation (or if the selects will all fold 3061 // away), lower to some complex code, otherwise just emit the libcall. 3062 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt)) 3063 return false; 3064 3065 SDOperand InL, InH; 3066 ExpandOp(Op, InL, InH); 3067 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 3068 DAG.getConstant(NVTBits, ShTy), ShAmt); 3069 3070 // Compare the unmasked shift amount against 32. 3071 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt, 3072 DAG.getConstant(NVTBits, ShTy), ISD::SETGE); 3073 3074 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 3075 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 3076 DAG.getConstant(NVTBits-1, ShTy)); 3077 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 3078 DAG.getConstant(NVTBits-1, ShTy)); 3079 } 3080 3081 if (Opc == ISD::SHL) { 3082 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 3083 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 3084 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 3085 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 3086 3087 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 3088 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 3089 } else { 3090 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 3091 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt, 3092 DAG.getConstant(32, ShTy), 3093 ISD::SETEQ), 3094 DAG.getConstant(0, NVT), 3095 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 3096 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 3097 HiLoPart, 3098 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 3099 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 3100 3101 SDOperand HiPart; 3102 if (Opc == ISD::SRA) 3103 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 3104 DAG.getConstant(NVTBits-1, ShTy)); 3105 else 3106 HiPart = DAG.getConstant(0, NVT); 3107 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 3108 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 3109 } 3110 return true; 3111} 3112 3113/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 3114/// NodeDepth) node that is an CallSeqStart operation and occurs later than 3115/// Found. 3116static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) { 3117 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 3118 3119 // If we found an CALLSEQ_START, we already know this node occurs later 3120 // than the Found node. Just remember this node and return. 3121 if (Node->getOpcode() == ISD::CALLSEQ_START) { 3122 Found = Node; 3123 return; 3124 } 3125 3126 // Otherwise, scan the operands of Node to see if any of them is a call. 3127 assert(Node->getNumOperands() != 0 && 3128 "All leaves should have depth equal to the entry node!"); 3129 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 3130 FindLatestCallSeqStart(Node->getOperand(i).Val, Found); 3131 3132 // Tail recurse for the last iteration. 3133 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 3134 Found); 3135} 3136 3137 3138/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 3139/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 3140/// than Found. 3141static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 3142 std::set<SDNode*> &Visited) { 3143 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 3144 !Visited.insert(Node).second) return; 3145 3146 // If we found an CALLSEQ_END, we already know this node occurs earlier 3147 // than the Found node. Just remember this node and return. 3148 if (Node->getOpcode() == ISD::CALLSEQ_END) { 3149 Found = Node; 3150 return; 3151 } 3152 3153 // Otherwise, scan the operands of Node to see if any of them is a call. 3154 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 3155 if (UI == E) return; 3156 for (--E; UI != E; ++UI) 3157 FindEarliestCallSeqEnd(*UI, Found, Visited); 3158 3159 // Tail recurse for the last iteration. 3160 FindEarliestCallSeqEnd(*UI, Found, Visited); 3161} 3162 3163/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 3164/// find the CALLSEQ_END node that terminates the call sequence. 3165static SDNode *FindCallSeqEnd(SDNode *Node) { 3166 if (Node->getOpcode() == ISD::CALLSEQ_END) 3167 return Node; 3168 if (Node->use_empty()) 3169 return 0; // No CallSeqEnd 3170 3171 SDOperand TheChain(Node, Node->getNumValues()-1); 3172 if (TheChain.getValueType() != MVT::Other) 3173 TheChain = SDOperand(Node, 0); 3174 if (TheChain.getValueType() != MVT::Other) 3175 return 0; 3176 3177 for (SDNode::use_iterator UI = Node->use_begin(), 3178 E = Node->use_end(); UI != E; ++UI) { 3179 3180 // Make sure to only follow users of our token chain. 3181 SDNode *User = *UI; 3182 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 3183 if (User->getOperand(i) == TheChain) 3184 if (SDNode *Result = FindCallSeqEnd(User)) 3185 return Result; 3186 } 3187 return 0; 3188} 3189 3190/// FindCallSeqStart - Given a chained node that is part of a call sequence, 3191/// find the CALLSEQ_START node that initiates the call sequence. 3192static SDNode *FindCallSeqStart(SDNode *Node) { 3193 assert(Node && "Didn't find callseq_start for a call??"); 3194 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 3195 3196 assert(Node->getOperand(0).getValueType() == MVT::Other && 3197 "Node doesn't have a token chain argument!"); 3198 return FindCallSeqStart(Node->getOperand(0).Val); 3199} 3200 3201 3202/// FindInputOutputChains - If we are replacing an operation with a call we need 3203/// to find the call that occurs before and the call that occurs after it to 3204/// properly serialize the calls in the block. The returned operand is the 3205/// input chain value for the new call (e.g. the entry node or the previous 3206/// call), and OutChain is set to be the chain node to update to point to the 3207/// end of the call chain. 3208static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 3209 SDOperand Entry) { 3210 SDNode *LatestCallSeqStart = Entry.Val; 3211 SDNode *LatestCallSeqEnd = 0; 3212 FindLatestCallSeqStart(OpNode, LatestCallSeqStart); 3213 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 3214 3215 // It is possible that no ISD::CALLSEQ_START was found because there is no 3216 // previous call in the function. LatestCallStackDown may in that case be 3217 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 3218 // unless LatestCallStackDown is an CALLSEQ_START. 3219 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 3220 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 3221 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 3222 } else { 3223 LatestCallSeqEnd = Entry.Val; 3224 } 3225 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 3226 3227 // Finally, find the first call that this must come before, first we find the 3228 // CallSeqEnd that ends the call. 3229 OutChain = 0; 3230 std::set<SDNode*> Visited; 3231 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 3232 3233 // If we found one, translate from the adj up to the callseq_start. 3234 if (OutChain) 3235 OutChain = FindCallSeqStart(OutChain); 3236 3237 return SDOperand(LatestCallSeqEnd, 0); 3238} 3239 3240/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 3241void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 3242 SDNode *OutChain) { 3243 // Nothing to splice it into? 3244 if (OutChain == 0) return; 3245 3246 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 3247 //OutChain->dump(); 3248 3249 // Form a token factor node merging the old inval and the new inval. 3250 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 3251 OutChain->getOperand(0)); 3252 // Change the node to refer to the new token. 3253 OutChain->setAdjCallChain(InToken); 3254} 3255 3256 3257// ExpandLibCall - Expand a node into a call to a libcall. If the result value 3258// does not fit into a register, return the lo part and set the hi part to the 3259// by-reg argument. If it does fit into a single register, return the result 3260// and leave the Hi part unset. 3261SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 3262 SDOperand &Hi) { 3263 SDNode *OutChain; 3264 SDOperand InChain = FindInputOutputChains(Node, OutChain, 3265 DAG.getEntryNode()); 3266 if (InChain.Val == 0) 3267 InChain = DAG.getEntryNode(); 3268 3269 TargetLowering::ArgListTy Args; 3270 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3271 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 3272 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 3273 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 3274 } 3275 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 3276 3277 // Splice the libcall in wherever FindInputOutputChains tells us to. 3278 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 3279 std::pair<SDOperand,SDOperand> CallInfo = 3280 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 3281 Callee, Args, DAG); 3282 3283 SDOperand Result; 3284 switch (getTypeAction(CallInfo.first.getValueType())) { 3285 default: assert(0 && "Unknown thing"); 3286 case Legal: 3287 Result = CallInfo.first; 3288 break; 3289 case Promote: 3290 assert(0 && "Cannot promote this yet!"); 3291 case Expand: 3292 ExpandOp(CallInfo.first, Result, Hi); 3293 CallInfo.second = LegalizeOp(CallInfo.second); 3294 break; 3295 } 3296 3297 SpliceCallInto(CallInfo.second, OutChain); 3298 NeedsAnotherIteration = true; 3299 return Result; 3300} 3301 3302 3303/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 3304/// destination type is legal. 3305SDOperand SelectionDAGLegalize:: 3306ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 3307 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 3308 assert(getTypeAction(Source.getValueType()) == Expand && 3309 "This is not an expansion!"); 3310 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 3311 3312 if (!isSigned) { 3313 assert(Source.getValueType() == MVT::i64 && 3314 "This only works for 64-bit -> FP"); 3315 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 3316 // incoming integer is set. To handle this, we dynamically test to see if 3317 // it is set, and, if so, add a fudge factor. 3318 SDOperand Lo, Hi; 3319 ExpandOp(Source, Lo, Hi); 3320 3321 // If this is unsigned, and not supported, first perform the conversion to 3322 // signed, then adjust the result if the sign bit is set. 3323 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 3324 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 3325 3326 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 3327 DAG.getConstant(0, Hi.getValueType()), 3328 ISD::SETLT); 3329 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3330 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3331 SignSet, Four, Zero); 3332 uint64_t FF = 0x5f800000ULL; 3333 if (TLI.isLittleEndian()) FF <<= 32; 3334 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3335 3336 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3337 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3338 SDOperand FudgeInReg; 3339 if (DestTy == MVT::f32) 3340 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3341 DAG.getSrcValue(NULL)); 3342 else { 3343 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3344 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3345 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 3346 } 3347 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3348 } 3349 3350 // Check to see if the target has a custom way to lower this. If so, use it. 3351 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3352 default: assert(0 && "This action not implemented for this operation!"); 3353 case TargetLowering::Legal: 3354 case TargetLowering::Expand: 3355 break; // This case is handled below. 3356 case TargetLowering::Custom: { 3357 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3358 Source), DAG); 3359 if (NV.Val) 3360 return LegalizeOp(NV); 3361 break; // The target decided this was legal after all 3362 } 3363 } 3364 3365 // Expand the source, then glue it back together for the call. We must expand 3366 // the source in case it is shared (this pass of legalize must traverse it). 3367 SDOperand SrcLo, SrcHi; 3368 ExpandOp(Source, SrcLo, SrcHi); 3369 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3370 3371 SDNode *OutChain = 0; 3372 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 3373 DAG.getEntryNode()); 3374 const char *FnName = 0; 3375 if (DestTy == MVT::f32) 3376 FnName = "__floatdisf"; 3377 else { 3378 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3379 FnName = "__floatdidf"; 3380 } 3381 3382 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 3383 3384 TargetLowering::ArgListTy Args; 3385 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 3386 3387 Args.push_back(std::make_pair(Source, ArgTy)); 3388 3389 // We don't care about token chains for libcalls. We just use the entry 3390 // node as our input and ignore the output chain. This allows us to place 3391 // calls wherever we need them to satisfy data dependences. 3392 const Type *RetTy = MVT::getTypeForValueType(DestTy); 3393 3394 std::pair<SDOperand,SDOperand> CallResult = 3395 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 3396 Callee, Args, DAG); 3397 3398 SpliceCallInto(CallResult.second, OutChain); 3399 return CallResult.first; 3400} 3401 3402 3403 3404/// ExpandOp - Expand the specified SDOperand into its two component pieces 3405/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 3406/// LegalizeNodes map is filled in for any results that are not expanded, the 3407/// ExpandedNodes map is filled in for any results that are expanded, and the 3408/// Lo/Hi values are returned. 3409void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 3410 MVT::ValueType VT = Op.getValueType(); 3411 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3412 SDNode *Node = Op.Val; 3413 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 3414 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 3415 "Cannot expand FP values!"); 3416 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 3417 "Cannot expand to FP value or to larger int value!"); 3418 3419 // See if we already expanded it. 3420 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 3421 = ExpandedNodes.find(Op); 3422 if (I != ExpandedNodes.end()) { 3423 Lo = I->second.first; 3424 Hi = I->second.second; 3425 return; 3426 } 3427 3428 // Expanding to multiple registers needs to perform an optimization step, and 3429 // is not careful to avoid operations the target does not support. Make sure 3430 // that all generated operations are legalized in the next iteration. 3431 NeedsAnotherIteration = true; 3432 3433 switch (Node->getOpcode()) { 3434 case ISD::CopyFromReg: 3435 assert(0 && "CopyFromReg must be legal!"); 3436 default: 3437 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 3438 assert(0 && "Do not know how to expand this operator!"); 3439 abort(); 3440 case ISD::UNDEF: 3441 Lo = DAG.getNode(ISD::UNDEF, NVT); 3442 Hi = DAG.getNode(ISD::UNDEF, NVT); 3443 break; 3444 case ISD::Constant: { 3445 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 3446 Lo = DAG.getConstant(Cst, NVT); 3447 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3448 break; 3449 } 3450 case ISD::ConstantVec: { 3451 unsigned NumElements = Node->getNumOperands(); 3452 // If we only have two elements left in the constant vector, just break it 3453 // apart into the two scalar constants it contains. Otherwise, bisect the 3454 // ConstantVec, and return each half as a new ConstantVec. 3455 // FIXME: this is hard coded as big endian, it may have to change to support 3456 // SSE and Alpha MVI 3457 if (NumElements == 2) { 3458 Hi = Node->getOperand(0); 3459 Lo = Node->getOperand(1); 3460 } else { 3461 NumElements /= 2; 3462 std::vector<SDOperand> LoOps, HiOps; 3463 for (unsigned I = 0, E = NumElements; I < E; ++I) { 3464 HiOps.push_back(Node->getOperand(I)); 3465 LoOps.push_back(Node->getOperand(I+NumElements)); 3466 } 3467 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps); 3468 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps); 3469 } 3470 break; 3471 } 3472 3473 case ISD::BUILD_PAIR: 3474 // Legalize both operands. FIXME: in the future we should handle the case 3475 // where the two elements are not legal. 3476 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 3477 Lo = LegalizeOp(Node->getOperand(0)); 3478 Hi = LegalizeOp(Node->getOperand(1)); 3479 break; 3480 3481 case ISD::SIGN_EXTEND_INREG: 3482 ExpandOp(Node->getOperand(0), Lo, Hi); 3483 // Sign extend the lo-part. 3484 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 3485 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 3486 TLI.getShiftAmountTy())); 3487 // sext_inreg the low part if needed. 3488 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 3489 break; 3490 3491 case ISD::CTPOP: 3492 ExpandOp(Node->getOperand(0), Lo, Hi); 3493 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3494 DAG.getNode(ISD::CTPOP, NVT, Lo), 3495 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3496 Hi = DAG.getConstant(0, NVT); 3497 break; 3498 3499 case ISD::CTLZ: { 3500 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3501 ExpandOp(Node->getOperand(0), Lo, Hi); 3502 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3503 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3504 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3505 ISD::SETNE); 3506 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3507 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3508 3509 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3510 Hi = DAG.getConstant(0, NVT); 3511 break; 3512 } 3513 3514 case ISD::CTTZ: { 3515 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3516 ExpandOp(Node->getOperand(0), Lo, Hi); 3517 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3518 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3519 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3520 ISD::SETNE); 3521 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3522 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3523 3524 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3525 Hi = DAG.getConstant(0, NVT); 3526 break; 3527 } 3528 3529 case ISD::LOAD: { 3530 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3531 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3532 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3533 3534 // Increment the pointer to the other half. 3535 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3536 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3537 getIntPtrConstant(IncrementSize)); 3538 //Is this safe? declaring that the two parts of the split load 3539 //are from the same instruction? 3540 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3541 3542 // Build a factor node to remember that this load is independent of the 3543 // other one. 3544 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3545 Hi.getValue(1)); 3546 3547 // Remember that we legalized the chain. 3548 AddLegalizedOperand(Op.getValue(1), TF); 3549 if (!TLI.isLittleEndian()) 3550 std::swap(Lo, Hi); 3551 break; 3552 } 3553 case ISD::VLOAD: { 3554 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3555 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3556 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3557 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3558 3559 // If we only have two elements, turn into a pair of scalar loads. 3560 // FIXME: handle case where a vector of two elements is fine, such as 3561 // 2 x double on SSE2. 3562 if (NumElements == 2) { 3563 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3564 // Increment the pointer to the other half. 3565 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8; 3566 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3567 getIntPtrConstant(IncrementSize)); 3568 //Is this safe? declaring that the two parts of the split load 3569 //are from the same instruction? 3570 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3571 } else { 3572 NumElements /= 2; // Split the vector in half 3573 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3574 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8; 3575 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3576 getIntPtrConstant(IncrementSize)); 3577 //Is this safe? declaring that the two parts of the split load 3578 //are from the same instruction? 3579 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3580 } 3581 3582 // Build a factor node to remember that this load is independent of the 3583 // other one. 3584 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3585 Hi.getValue(1)); 3586 3587 // Remember that we legalized the chain. 3588 AddLegalizedOperand(Op.getValue(1), TF); 3589 if (!TLI.isLittleEndian()) 3590 std::swap(Lo, Hi); 3591 break; 3592 } 3593 case ISD::VADD: 3594 case ISD::VSUB: 3595 case ISD::VMUL: { 3596 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3597 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3598 SDOperand LL, LH, RL, RH; 3599 3600 ExpandOp(Node->getOperand(0), LL, LH); 3601 ExpandOp(Node->getOperand(1), RL, RH); 3602 3603 // If we only have two elements, turn into a pair of scalar loads. 3604 // FIXME: handle case where a vector of two elements is fine, such as 3605 // 2 x double on SSE2. 3606 if (NumElements == 2) { 3607 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT); 3608 Lo = DAG.getNode(Opc, EVT, LL, RL); 3609 Hi = DAG.getNode(Opc, EVT, LH, RH); 3610 } else { 3611 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2), 3612 LL.getOperand(3)); 3613 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2), 3614 LH.getOperand(3)); 3615 } 3616 break; 3617 } 3618 case ISD::TAILCALL: 3619 case ISD::CALL: { 3620 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3621 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 3622 3623 bool Changed = false; 3624 std::vector<SDOperand> Ops; 3625 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 3626 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3627 Changed |= Ops.back() != Node->getOperand(i); 3628 } 3629 3630 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 3631 "Can only expand a call once so far, not i64 -> i16!"); 3632 3633 std::vector<MVT::ValueType> RetTyVTs; 3634 RetTyVTs.reserve(3); 3635 RetTyVTs.push_back(NVT); 3636 RetTyVTs.push_back(NVT); 3637 RetTyVTs.push_back(MVT::Other); 3638 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops, 3639 Node->getOpcode() == ISD::TAILCALL); 3640 Lo = SDOperand(NC, 0); 3641 Hi = SDOperand(NC, 1); 3642 3643 // Insert the new chain mapping. 3644 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 3645 break; 3646 } 3647 case ISD::AND: 3648 case ISD::OR: 3649 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 3650 SDOperand LL, LH, RL, RH; 3651 ExpandOp(Node->getOperand(0), LL, LH); 3652 ExpandOp(Node->getOperand(1), RL, RH); 3653 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 3654 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 3655 break; 3656 } 3657 case ISD::SELECT: { 3658 SDOperand C, LL, LH, RL, RH; 3659 3660 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3661 case Expand: assert(0 && "It's impossible to expand bools"); 3662 case Legal: 3663 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 3664 break; 3665 case Promote: 3666 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 3667 break; 3668 } 3669 ExpandOp(Node->getOperand(1), LL, LH); 3670 ExpandOp(Node->getOperand(2), RL, RH); 3671 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 3672 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 3673 break; 3674 } 3675 case ISD::SELECT_CC: { 3676 SDOperand TL, TH, FL, FH; 3677 ExpandOp(Node->getOperand(2), TL, TH); 3678 ExpandOp(Node->getOperand(3), FL, FH); 3679 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3680 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3681 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3682 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3683 Lo = LegalizeOp(Lo); 3684 Hi = LegalizeOp(Hi); 3685 break; 3686 } 3687 case ISD::SEXTLOAD: { 3688 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3689 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3690 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3691 3692 if (EVT == NVT) 3693 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3694 else 3695 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3696 EVT); 3697 3698 // Remember that we legalized the chain. 3699 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3700 3701 // The high part is obtained by SRA'ing all but one of the bits of the lo 3702 // part. 3703 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3704 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3705 TLI.getShiftAmountTy())); 3706 Lo = LegalizeOp(Lo); 3707 Hi = LegalizeOp(Hi); 3708 break; 3709 } 3710 case ISD::ZEXTLOAD: { 3711 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3712 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3713 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3714 3715 if (EVT == NVT) 3716 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3717 else 3718 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3719 EVT); 3720 3721 // Remember that we legalized the chain. 3722 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3723 3724 // The high part is just a zero. 3725 Hi = LegalizeOp(DAG.getConstant(0, NVT)); 3726 Lo = LegalizeOp(Lo); 3727 break; 3728 } 3729 case ISD::EXTLOAD: { 3730 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3731 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3732 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3733 3734 if (EVT == NVT) 3735 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3736 else 3737 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3738 EVT); 3739 3740 // Remember that we legalized the chain. 3741 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3742 3743 // The high part is undefined. 3744 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT)); 3745 Lo = LegalizeOp(Lo); 3746 break; 3747 } 3748 case ISD::ANY_EXTEND: { 3749 SDOperand In; 3750 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3751 case Expand: assert(0 && "expand-expand not implemented yet!"); 3752 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3753 case Promote: 3754 In = PromoteOp(Node->getOperand(0)); 3755 break; 3756 } 3757 3758 // The low part is any extension of the input (which degenerates to a copy). 3759 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In); 3760 // The high part is undefined. 3761 Hi = DAG.getNode(ISD::UNDEF, NVT); 3762 break; 3763 } 3764 case ISD::SIGN_EXTEND: { 3765 SDOperand In; 3766 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3767 case Expand: assert(0 && "expand-expand not implemented yet!"); 3768 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3769 case Promote: 3770 In = PromoteOp(Node->getOperand(0)); 3771 // Emit the appropriate sign_extend_inreg to get the value we want. 3772 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 3773 DAG.getValueType(Node->getOperand(0).getValueType())); 3774 break; 3775 } 3776 3777 // The low part is just a sign extension of the input (which degenerates to 3778 // a copy). 3779 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 3780 3781 // The high part is obtained by SRA'ing all but one of the bits of the lo 3782 // part. 3783 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3784 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3785 TLI.getShiftAmountTy())); 3786 break; 3787 } 3788 case ISD::ZERO_EXTEND: { 3789 SDOperand In; 3790 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3791 case Expand: assert(0 && "expand-expand not implemented yet!"); 3792 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3793 case Promote: 3794 In = PromoteOp(Node->getOperand(0)); 3795 // Emit the appropriate zero_extend_inreg to get the value we want. 3796 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 3797 break; 3798 } 3799 3800 // The low part is just a zero extension of the input (which degenerates to 3801 // a copy). 3802 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 3803 3804 // The high part is just a zero. 3805 Hi = DAG.getConstant(0, NVT); 3806 break; 3807 } 3808 3809 case ISD::BIT_CONVERT: { 3810 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0), 3811 Node->getOperand(0)); 3812 ExpandOp(Tmp, Lo, Hi); 3813 break; 3814 } 3815 3816 case ISD::READCYCLECOUNTER: { 3817 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 3818 TargetLowering::Custom && 3819 "Must custom expand ReadCycleCounter"); 3820 SDOperand T = TLI.LowerOperation(Op, DAG); 3821 assert(T.Val && "Node must be custom expanded!"); 3822 Lo = LegalizeOp(T.getValue(0)); 3823 Hi = LegalizeOp(T.getValue(1)); 3824 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 3825 LegalizeOp(T.getValue(2))); 3826 break; 3827 } 3828 3829 // These operators cannot be expanded directly, emit them as calls to 3830 // library functions. 3831 case ISD::FP_TO_SINT: 3832 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 3833 SDOperand Op; 3834 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3835 case Expand: assert(0 && "cannot expand FP!"); 3836 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3837 case Promote: Op = PromoteOp(Node->getOperand(0)); break; 3838 } 3839 3840 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 3841 3842 // Now that the custom expander is done, expand the result, which is still 3843 // VT. 3844 if (Op.Val) { 3845 ExpandOp(Op, Lo, Hi); 3846 break; 3847 } 3848 } 3849 3850 if (Node->getOperand(0).getValueType() == MVT::f32) 3851 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 3852 else 3853 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 3854 break; 3855 3856 case ISD::FP_TO_UINT: 3857 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 3858 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, 3859 LegalizeOp(Node->getOperand(0))); 3860 // Now that the custom expander is done, expand the result, which is still 3861 // VT. 3862 Op = TLI.LowerOperation(Op, DAG); 3863 if (Op.Val) { 3864 ExpandOp(Op, Lo, Hi); 3865 break; 3866 } 3867 } 3868 3869 if (Node->getOperand(0).getValueType() == MVT::f32) 3870 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 3871 else 3872 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 3873 break; 3874 3875 case ISD::SHL: 3876 // If the target wants custom lowering, do so. 3877 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 3878 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), 3879 LegalizeOp(Node->getOperand(1))); 3880 Op = TLI.LowerOperation(Op, DAG); 3881 if (Op.Val) { 3882 // Now that the custom expander is done, expand the result, which is 3883 // still VT. 3884 ExpandOp(Op, Lo, Hi); 3885 break; 3886 } 3887 } 3888 3889 // If we can emit an efficient shift operation, do so now. 3890 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3891 break; 3892 3893 // If this target supports SHL_PARTS, use it. 3894 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) { 3895 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 3896 Lo, Hi); 3897 break; 3898 } 3899 3900 // Otherwise, emit a libcall. 3901 Lo = ExpandLibCall("__ashldi3", Node, Hi); 3902 break; 3903 3904 case ISD::SRA: 3905 // If the target wants custom lowering, do so. 3906 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 3907 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), 3908 LegalizeOp(Node->getOperand(1))); 3909 Op = TLI.LowerOperation(Op, DAG); 3910 if (Op.Val) { 3911 // Now that the custom expander is done, expand the result, which is 3912 // still VT. 3913 ExpandOp(Op, Lo, Hi); 3914 break; 3915 } 3916 } 3917 3918 // If we can emit an efficient shift operation, do so now. 3919 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3920 break; 3921 3922 // If this target supports SRA_PARTS, use it. 3923 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) { 3924 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 3925 Lo, Hi); 3926 break; 3927 } 3928 3929 // Otherwise, emit a libcall. 3930 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 3931 break; 3932 case ISD::SRL: 3933 // If the target wants custom lowering, do so. 3934 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 3935 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), 3936 LegalizeOp(Node->getOperand(1))); 3937 Op = TLI.LowerOperation(Op, DAG); 3938 if (Op.Val) { 3939 // Now that the custom expander is done, expand the result, which is 3940 // still VT. 3941 ExpandOp(Op, Lo, Hi); 3942 break; 3943 } 3944 } 3945 3946 // If we can emit an efficient shift operation, do so now. 3947 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3948 break; 3949 3950 // If this target supports SRL_PARTS, use it. 3951 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) { 3952 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 3953 Lo, Hi); 3954 break; 3955 } 3956 3957 // Otherwise, emit a libcall. 3958 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 3959 break; 3960 3961 case ISD::ADD: 3962 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 3963 Lo, Hi); 3964 break; 3965 case ISD::SUB: 3966 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 3967 Lo, Hi); 3968 break; 3969 case ISD::MUL: { 3970 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 3971 SDOperand LL, LH, RL, RH; 3972 ExpandOp(Node->getOperand(0), LL, LH); 3973 ExpandOp(Node->getOperand(1), RL, RH); 3974 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 3975 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 3976 // extended the sign bit of the low half through the upper half, and if so 3977 // emit a MULHS instead of the alternate sequence that is valid for any 3978 // i64 x i64 multiply. 3979 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 3980 // is RH an extension of the sign bit of RL? 3981 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 3982 RH.getOperand(1).getOpcode() == ISD::Constant && 3983 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 3984 // is LH an extension of the sign bit of LL? 3985 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 3986 LH.getOperand(1).getOpcode() == ISD::Constant && 3987 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 3988 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 3989 } else { 3990 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 3991 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 3992 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 3993 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 3994 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 3995 } 3996 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 3997 } else { 3998 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 3999 } 4000 break; 4001 } 4002 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 4003 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 4004 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 4005 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 4006 } 4007 4008 // Remember in a map if the values will be reused later. 4009 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 4010 std::make_pair(Lo, Hi))).second; 4011 assert(isNew && "Value already expanded?!?"); 4012 4013 // Make sure the resultant values have been legalized themselves, unless this 4014 // is a type that requires multi-step expansion. 4015 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 4016 Lo = LegalizeOp(Lo); 4017 Hi = LegalizeOp(Hi); 4018 } 4019} 4020 4021 4022// SelectionDAG::Legalize - This is the entry point for the file. 4023// 4024void SelectionDAG::Legalize() { 4025 /// run - This is the main entry point to this class. 4026 /// 4027 SelectionDAGLegalize(*this).Run(); 4028} 4029 4030