LegalizeDAG.cpp revision acc398c195a697795bff3245943d104eb19192b9
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned long long ValueTypeActions; 56 57 /// NeedsAnotherIteration - This is set when we expand a large integer 58 /// operation into smaller integer operations, but the smaller operations are 59 /// not set. This occurs only rarely in practice, for targets that don't have 60 /// 32-bit or larger integer registers. 61 bool NeedsAnotherIteration; 62 63 /// LegalizedNodes - For nodes that are of legal width, and that have more 64 /// than one use, this map indicates what regularized operand to use. This 65 /// allows us to avoid legalizing the same thing more than once. 66 std::map<SDOperand, SDOperand> LegalizedNodes; 67 68 /// PromotedNodes - For nodes that are below legal width, and that have more 69 /// than one use, this map indicates what promoted value to use. This allows 70 /// us to avoid promoting the same thing more than once. 71 std::map<SDOperand, SDOperand> PromotedNodes; 72 73 /// ExpandedNodes - For nodes that need to be expanded, and which have more 74 /// than one use, this map indicates which which operands are the expanded 75 /// version of the input. This allows us to avoid expanding the same node 76 /// more than once. 77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 78 79 void AddLegalizedOperand(SDOperand From, SDOperand To) { 80 LegalizedNodes.insert(std::make_pair(From, To)); 81 // If someone requests legalization of the new node, return itself. 82 if (From != To) 83 LegalizedNodes.insert(std::make_pair(To, To)); 84 } 85 void AddPromotedOperand(SDOperand From, SDOperand To) { 86 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 87 assert(isNew && "Got into the map somehow?"); 88 // If someone requests legalization of the new node, return itself. 89 LegalizedNodes.insert(std::make_pair(To, To)); 90 } 91 92public: 93 94 SelectionDAGLegalize(SelectionDAG &DAG); 95 96 /// Run - While there is still lowering to do, perform a pass over the DAG. 97 /// Most regularization can be done in a single pass, but targets that require 98 /// large values to be split into registers multiple times (e.g. i64 -> 4x 99 /// i16) require iteration for these values (the first iteration will demote 100 /// to i32, the second will demote to i16). 101 void Run() { 102 do { 103 NeedsAnotherIteration = false; 104 LegalizeDAG(); 105 } while (NeedsAnotherIteration); 106 } 107 108 /// getTypeAction - Return how we should legalize values of this type, either 109 /// it is already legal or we need to expand it into multiple registers of 110 /// smaller integer type, or we need to promote it to a larger type. 111 LegalizeAction getTypeAction(MVT::ValueType VT) const { 112 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 113 } 114 115 /// isTypeLegal - Return true if this type is legal on this target. 116 /// 117 bool isTypeLegal(MVT::ValueType VT) const { 118 return getTypeAction(VT) == Legal; 119 } 120 121private: 122 void LegalizeDAG(); 123 124 SDOperand LegalizeOp(SDOperand O); 125 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 126 SDOperand PromoteOp(SDOperand O); 127 128 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 129 SDOperand &Hi); 130 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 131 SDOperand Source); 132 133 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 134 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 135 SDOperand LegalOp, 136 MVT::ValueType DestVT); 137 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 138 bool isSigned); 139 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 140 bool isSigned); 141 142 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 143 SDOperand &Lo, SDOperand &Hi); 144 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 145 SDOperand &Lo, SDOperand &Hi); 146 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 147 SDOperand &Lo, SDOperand &Hi); 148 149 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 150 151 SDOperand getIntPtrConstant(uint64_t Val) { 152 return DAG.getConstant(Val, TLI.getPointerTy()); 153 } 154}; 155} 156 157static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 158 switch (VecOp) { 159 default: assert(0 && "Don't know how to scalarize this opcode!"); 160 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 161 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 162 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 163 } 164} 165 166SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 167 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 168 ValueTypeActions(TLI.getValueTypeActions()) { 169 assert(MVT::LAST_VALUETYPE <= 32 && 170 "Too many value types for ValueTypeActions to hold!"); 171} 172 173/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 174/// INT_TO_FP operation of the specified operand when the target requests that 175/// we expand it. At this point, we know that the result and operand types are 176/// legal for the target. 177SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 178 SDOperand Op0, 179 MVT::ValueType DestVT) { 180 if (Op0.getValueType() == MVT::i32) { 181 // simple 32-bit [signed|unsigned] integer to float/double expansion 182 183 // get the stack frame index of a 8 byte buffer 184 MachineFunction &MF = DAG.getMachineFunction(); 185 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 186 // get address of 8 byte buffer 187 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 188 // word offset constant for Hi/Lo address computation 189 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 190 // set up Hi and Lo (into buffer) address based on endian 191 SDOperand Hi, Lo; 192 if (TLI.isLittleEndian()) { 193 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 194 Lo = StackSlot; 195 } else { 196 Hi = StackSlot; 197 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 198 } 199 // if signed map to unsigned space 200 SDOperand Op0Mapped; 201 if (isSigned) { 202 // constant used to invert sign bit (signed to unsigned mapping) 203 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 204 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 205 } else { 206 Op0Mapped = Op0; 207 } 208 // store the lo of the constructed double - based on integer input 209 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 210 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 211 // initial hi portion of constructed double 212 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 213 // store the hi of the constructed double - biased exponent 214 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 215 InitialHi, Hi, DAG.getSrcValue(NULL)); 216 // load the constructed double 217 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 218 DAG.getSrcValue(NULL)); 219 // FP constant to bias correct the final result 220 SDOperand Bias = DAG.getConstantFP(isSigned ? 221 BitsToDouble(0x4330000080000000ULL) 222 : BitsToDouble(0x4330000000000000ULL), 223 MVT::f64); 224 // subtract the bias 225 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 226 // final result 227 SDOperand Result; 228 // handle final rounding 229 if (DestVT == MVT::f64) { 230 // do nothing 231 Result = Sub; 232 } else { 233 // if f32 then cast to f32 234 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 235 } 236 return LegalizeOp(Result); 237 } 238 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 239 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 240 241 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 242 DAG.getConstant(0, Op0.getValueType()), 243 ISD::SETLT); 244 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 245 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 246 SignSet, Four, Zero); 247 248 // If the sign bit of the integer is set, the large number will be treated 249 // as a negative number. To counteract this, the dynamic code adds an 250 // offset depending on the data type. 251 uint64_t FF; 252 switch (Op0.getValueType()) { 253 default: assert(0 && "Unsupported integer type!"); 254 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 255 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 256 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 257 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 258 } 259 if (TLI.isLittleEndian()) FF <<= 32; 260 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 261 262 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 263 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 264 SDOperand FudgeInReg; 265 if (DestVT == MVT::f32) 266 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 267 DAG.getSrcValue(NULL)); 268 else { 269 assert(DestVT == MVT::f64 && "Unexpected conversion"); 270 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 271 DAG.getEntryNode(), CPIdx, 272 DAG.getSrcValue(NULL), MVT::f32)); 273 } 274 275 return LegalizeOp(DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg)); 276} 277 278/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 279/// *INT_TO_FP operation of the specified operand when the target requests that 280/// we promote it. At this point, we know that the result and operand types are 281/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 282/// operation that takes a larger input. 283SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 284 MVT::ValueType DestVT, 285 bool isSigned) { 286 // First step, figure out the appropriate *INT_TO_FP operation to use. 287 MVT::ValueType NewInTy = LegalOp.getValueType(); 288 289 unsigned OpToUse = 0; 290 291 // Scan for the appropriate larger type to use. 292 while (1) { 293 NewInTy = (MVT::ValueType)(NewInTy+1); 294 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 295 296 // If the target supports SINT_TO_FP of this type, use it. 297 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 298 default: break; 299 case TargetLowering::Legal: 300 if (!TLI.isTypeLegal(NewInTy)) 301 break; // Can't use this datatype. 302 // FALL THROUGH. 303 case TargetLowering::Custom: 304 OpToUse = ISD::SINT_TO_FP; 305 break; 306 } 307 if (OpToUse) break; 308 if (isSigned) continue; 309 310 // If the target supports UINT_TO_FP of this type, use it. 311 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 312 default: break; 313 case TargetLowering::Legal: 314 if (!TLI.isTypeLegal(NewInTy)) 315 break; // Can't use this datatype. 316 // FALL THROUGH. 317 case TargetLowering::Custom: 318 OpToUse = ISD::UINT_TO_FP; 319 break; 320 } 321 if (OpToUse) break; 322 323 // Otherwise, try a larger type. 324 } 325 326 // Okay, we found the operation and type to use. Zero extend our input to the 327 // desired type then run the operation on it. 328 SDOperand N = DAG.getNode(OpToUse, DestVT, 329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 330 NewInTy, LegalOp)); 331 // Make sure to legalize any nodes we create here. 332 return LegalizeOp(N); 333} 334 335/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 336/// FP_TO_*INT operation of the specified operand when the target requests that 337/// we promote it. At this point, we know that the result and operand types are 338/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 339/// operation that returns a larger result. 340SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 341 MVT::ValueType DestVT, 342 bool isSigned) { 343 // First step, figure out the appropriate FP_TO*INT operation to use. 344 MVT::ValueType NewOutTy = DestVT; 345 346 unsigned OpToUse = 0; 347 348 // Scan for the appropriate larger type to use. 349 while (1) { 350 NewOutTy = (MVT::ValueType)(NewOutTy+1); 351 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 352 353 // If the target supports FP_TO_SINT returning this type, use it. 354 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 355 default: break; 356 case TargetLowering::Legal: 357 if (!TLI.isTypeLegal(NewOutTy)) 358 break; // Can't use this datatype. 359 // FALL THROUGH. 360 case TargetLowering::Custom: 361 OpToUse = ISD::FP_TO_SINT; 362 break; 363 } 364 if (OpToUse) break; 365 366 // If the target supports FP_TO_UINT of this type, use it. 367 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 368 default: break; 369 case TargetLowering::Legal: 370 if (!TLI.isTypeLegal(NewOutTy)) 371 break; // Can't use this datatype. 372 // FALL THROUGH. 373 case TargetLowering::Custom: 374 OpToUse = ISD::FP_TO_UINT; 375 break; 376 } 377 if (OpToUse) break; 378 379 // Otherwise, try a larger type. 380 } 381 382 // Okay, we found the operation and type to use. Truncate the result of the 383 // extended FP_TO_*INT operation to the desired size. 384 SDOperand N = DAG.getNode(ISD::TRUNCATE, DestVT, 385 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 386 // Make sure to legalize any nodes we create here in the next pass. 387 return LegalizeOp(N); 388} 389 390/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 391/// not been visited yet and if all of its operands have already been visited. 392static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 393 std::map<SDNode*, unsigned> &Visited) { 394 if (++Visited[N] != N->getNumOperands()) 395 return; // Haven't visited all operands yet 396 397 Order.push_back(N); 398 399 if (N->hasOneUse()) { // Tail recurse in common case. 400 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 401 return; 402 } 403 404 // Now that we have N in, add anything that uses it if all of their operands 405 // are now done. 406 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 407 ComputeTopDownOrdering(*UI, Order, Visited); 408} 409 410 411void SelectionDAGLegalize::LegalizeDAG() { 412 // The legalize process is inherently a bottom-up recursive process (users 413 // legalize their uses before themselves). Given infinite stack space, we 414 // could just start legalizing on the root and traverse the whole graph. In 415 // practice however, this causes us to run out of stack space on large basic 416 // blocks. To avoid this problem, compute an ordering of the nodes where each 417 // node is only legalized after all of its operands are legalized. 418 std::map<SDNode*, unsigned> Visited; 419 std::vector<SDNode*> Order; 420 421 // Compute ordering from all of the leaves in the graphs, those (like the 422 // entry node) that have no operands. 423 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 424 E = DAG.allnodes_end(); I != E; ++I) { 425 if (I->getNumOperands() == 0) { 426 Visited[I] = 0 - 1U; 427 ComputeTopDownOrdering(I, Order, Visited); 428 } 429 } 430 431 assert(Order.size() == Visited.size() && 432 Order.size() == 433 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 434 "Error: DAG is cyclic!"); 435 Visited.clear(); 436 437 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 438 SDNode *N = Order[i]; 439 switch (getTypeAction(N->getValueType(0))) { 440 default: assert(0 && "Bad type action!"); 441 case Legal: 442 LegalizeOp(SDOperand(N, 0)); 443 break; 444 case Promote: 445 PromoteOp(SDOperand(N, 0)); 446 break; 447 case Expand: { 448 SDOperand X, Y; 449 ExpandOp(SDOperand(N, 0), X, Y); 450 break; 451 } 452 } 453 } 454 455 // Finally, it's possible the root changed. Get the new root. 456 SDOperand OldRoot = DAG.getRoot(); 457 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 458 DAG.setRoot(LegalizedNodes[OldRoot]); 459 460 ExpandedNodes.clear(); 461 LegalizedNodes.clear(); 462 PromotedNodes.clear(); 463 464 // Remove dead nodes now. 465 DAG.RemoveDeadNodes(OldRoot.Val); 466} 467 468SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 469 assert(isTypeLegal(Op.getValueType()) && 470 "Caller should expand or promote operands that are not legal!"); 471 SDNode *Node = Op.Val; 472 473 // If this operation defines any values that cannot be represented in a 474 // register on this target, make sure to expand or promote them. 475 if (Node->getNumValues() > 1) { 476 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 477 switch (getTypeAction(Node->getValueType(i))) { 478 case Legal: break; // Nothing to do. 479 case Expand: { 480 SDOperand T1, T2; 481 ExpandOp(Op.getValue(i), T1, T2); 482 assert(LegalizedNodes.count(Op) && 483 "Expansion didn't add legal operands!"); 484 return LegalizedNodes[Op]; 485 } 486 case Promote: 487 PromoteOp(Op.getValue(i)); 488 assert(LegalizedNodes.count(Op) && 489 "Expansion didn't add legal operands!"); 490 return LegalizedNodes[Op]; 491 } 492 } 493 494 // Note that LegalizeOp may be reentered even from single-use nodes, which 495 // means that we always must cache transformed nodes. 496 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 497 if (I != LegalizedNodes.end()) return I->second; 498 499 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 500 501 SDOperand Result = Op; 502 503 switch (Node->getOpcode()) { 504 default: 505 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 506 // If this is a target node, legalize it by legalizing the operands then 507 // passing it through. 508 std::vector<SDOperand> Ops; 509 bool Changed = false; 510 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 511 Ops.push_back(LegalizeOp(Node->getOperand(i))); 512 Changed = Changed || Node->getOperand(i) != Ops.back(); 513 } 514 if (Changed) 515 if (Node->getNumValues() == 1) 516 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 517 else { 518 std::vector<MVT::ValueType> VTs(Node->value_begin(), 519 Node->value_end()); 520 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 521 } 522 523 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 524 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 525 return Result.getValue(Op.ResNo); 526 } 527 // Otherwise this is an unhandled builtin node. splat. 528 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 529 assert(0 && "Do not know how to legalize this operator!"); 530 abort(); 531 case ISD::EntryToken: 532 case ISD::FrameIndex: 533 case ISD::TargetFrameIndex: 534 case ISD::Register: 535 case ISD::TargetConstant: 536 case ISD::TargetConstantPool: 537 case ISD::GlobalAddress: 538 case ISD::TargetGlobalAddress: 539 case ISD::ExternalSymbol: 540 case ISD::TargetExternalSymbol: 541 case ISD::ConstantPool: // Nothing to do. 542 case ISD::BasicBlock: 543 case ISD::CONDCODE: 544 case ISD::VALUETYPE: 545 case ISD::SRCVALUE: 546 case ISD::STRING: 547 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 548 default: assert(0 && "This action is not supported yet!"); 549 case TargetLowering::Custom: { 550 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 551 if (Tmp.Val) { 552 Result = LegalizeOp(Tmp); 553 break; 554 } 555 } // FALLTHROUGH if the target doesn't want to lower this op after all. 556 case TargetLowering::Legal: 557 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!"); 558 break; 559 } 560 break; 561 case ISD::AssertSext: 562 case ISD::AssertZext: 563 Tmp1 = LegalizeOp(Node->getOperand(0)); 564 if (Tmp1 != Node->getOperand(0)) 565 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 566 Node->getOperand(1)); 567 break; 568 case ISD::MERGE_VALUES: 569 return LegalizeOp(Node->getOperand(Op.ResNo)); 570 case ISD::CopyFromReg: 571 Tmp1 = LegalizeOp(Node->getOperand(0)); 572 Result = Op.getValue(0); 573 if (Node->getNumValues() == 2) { 574 if (Tmp1 != Node->getOperand(0)) 575 Result = DAG.getCopyFromReg(Tmp1, 576 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 577 Node->getValueType(0)); 578 } else { 579 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 580 if (Node->getNumOperands() == 3) 581 Tmp2 = LegalizeOp(Node->getOperand(2)); 582 if (Tmp1 != Node->getOperand(0) || 583 (Node->getNumOperands() == 3 && Tmp2 != Node->getOperand(2))) 584 Result = DAG.getCopyFromReg(Tmp1, 585 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 586 Node->getValueType(0), Tmp2); 587 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 588 } 589 // Since CopyFromReg produces two values, make sure to remember that we 590 // legalized both of them. 591 AddLegalizedOperand(Op.getValue(0), Result); 592 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 593 return Result.getValue(Op.ResNo); 594 case ISD::UNDEF: { 595 MVT::ValueType VT = Op.getValueType(); 596 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 597 default: assert(0 && "This action is not supported yet!"); 598 case TargetLowering::Expand: 599 case TargetLowering::Promote: 600 if (MVT::isInteger(VT)) 601 Result = DAG.getConstant(0, VT); 602 else if (MVT::isFloatingPoint(VT)) 603 Result = DAG.getConstantFP(0, VT); 604 else 605 assert(0 && "Unknown value type!"); 606 break; 607 case TargetLowering::Legal: 608 break; 609 } 610 break; 611 } 612 613 case ISD::LOCATION: 614 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 615 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 616 617 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 618 case TargetLowering::Promote: 619 default: assert(0 && "This action is not supported yet!"); 620 case TargetLowering::Expand: { 621 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 622 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 623 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other); 624 625 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) { 626 const std::string &FName = 627 cast<StringSDNode>(Node->getOperand(3))->getValue(); 628 const std::string &DirName = 629 cast<StringSDNode>(Node->getOperand(4))->getValue(); 630 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName); 631 632 std::vector<SDOperand> Ops; 633 Ops.push_back(Tmp1); // chain 634 SDOperand LineOp = Node->getOperand(1); 635 SDOperand ColOp = Node->getOperand(2); 636 637 if (useDEBUG_LOC) { 638 Ops.push_back(LineOp); // line # 639 Ops.push_back(ColOp); // col # 640 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 641 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops); 642 } else { 643 unsigned Line = dyn_cast<ConstantSDNode>(LineOp)->getValue(); 644 unsigned Col = dyn_cast<ConstantSDNode>(ColOp)->getValue(); 645 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile); 646 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 647 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops); 648 } 649 } else { 650 Result = Tmp1; // chain 651 } 652 Result = LegalizeOp(Result); // Relegalize new nodes. 653 break; 654 } 655 case TargetLowering::Legal: 656 if (Tmp1 != Node->getOperand(0) || 657 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 658 std::vector<SDOperand> Ops; 659 Ops.push_back(Tmp1); 660 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 661 Ops.push_back(Node->getOperand(1)); // line # must be legal. 662 Ops.push_back(Node->getOperand(2)); // col # must be legal. 663 } else { 664 // Otherwise promote them. 665 Ops.push_back(PromoteOp(Node->getOperand(1))); 666 Ops.push_back(PromoteOp(Node->getOperand(2))); 667 } 668 Ops.push_back(Node->getOperand(3)); // filename must be legal. 669 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 670 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops); 671 } 672 break; 673 } 674 break; 675 676 case ISD::DEBUG_LOC: 677 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 678 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 679 case TargetLowering::Promote: 680 case TargetLowering::Expand: 681 default: assert(0 && "This action is not supported yet!"); 682 case TargetLowering::Legal: 683 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 684 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 685 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 686 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 687 688 if (Tmp1 != Node->getOperand(0) || 689 Tmp2 != Node->getOperand(1) || 690 Tmp3 != Node->getOperand(2) || 691 Tmp4 != Node->getOperand(3)) { 692 Result = DAG.getNode(ISD::DEBUG_LOC,MVT::Other, Tmp1, Tmp2, Tmp3, Tmp4); 693 } 694 break; 695 } 696 break; 697 698 case ISD::DEBUG_LABEL: 699 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!"); 700 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) { 701 case TargetLowering::Promote: 702 case TargetLowering::Expand: 703 default: assert(0 && "This action is not supported yet!"); 704 case TargetLowering::Legal: 705 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 706 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 707 708 if (Tmp1 != Node->getOperand(0) || 709 Tmp2 != Node->getOperand(1)) { 710 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Tmp1, Tmp2); 711 } 712 break; 713 } 714 break; 715 716 case ISD::Constant: 717 // We know we don't need to expand constants here, constants only have one 718 // value and we check that it is fine above. 719 720 // FIXME: Maybe we should handle things like targets that don't support full 721 // 32-bit immediates? 722 break; 723 case ISD::ConstantFP: { 724 // Spill FP immediates to the constant pool if the target cannot directly 725 // codegen them. Targets often have some immediate values that can be 726 // efficiently generated into an FP register without a load. We explicitly 727 // leave these constants as ConstantFP nodes for the target to deal with. 728 729 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 730 731 // Check to see if this FP immediate is already legal. 732 bool isLegal = false; 733 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 734 E = TLI.legal_fpimm_end(); I != E; ++I) 735 if (CFP->isExactlyValue(*I)) { 736 isLegal = true; 737 break; 738 } 739 740 if (!isLegal) { 741 // Otherwise we need to spill the constant to memory. 742 bool Extend = false; 743 744 // If a FP immediate is precise when represented as a float, we put it 745 // into the constant pool as a float, even if it's is statically typed 746 // as a double. 747 MVT::ValueType VT = CFP->getValueType(0); 748 bool isDouble = VT == MVT::f64; 749 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 750 Type::FloatTy, CFP->getValue()); 751 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 752 // Only do this if the target has a native EXTLOAD instruction from 753 // f32. 754 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 755 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 756 VT = MVT::f32; 757 Extend = true; 758 } 759 760 SDOperand CPIdx = 761 LegalizeOp(DAG.getConstantPool(LLVMC, TLI.getPointerTy())); 762 if (Extend) { 763 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 764 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 765 } else { 766 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 767 DAG.getSrcValue(NULL)); 768 } 769 } 770 break; 771 } 772 case ISD::ConstantVec: { 773 // We assume that vector constants are not legal, and will be immediately 774 // spilled to the constant pool. 775 // 776 // FIXME: revisit this when we have some kind of mechanism by which targets 777 // can decided legality of vector constants, of which there may be very 778 // many. 779 // 780 // Create a ConstantPacked, and put it in the constant pool. 781 std::vector<Constant*> CV; 782 MVT::ValueType VT = Node->getValueType(0); 783 for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) { 784 SDOperand OpN = Node->getOperand(I); 785 const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType()); 786 if (MVT::isFloatingPoint(VT)) 787 CV.push_back(ConstantFP::get(OpNTy, 788 cast<ConstantFPSDNode>(OpN)->getValue())); 789 else 790 CV.push_back(ConstantUInt::get(OpNTy, 791 cast<ConstantSDNode>(OpN)->getValue())); 792 } 793 Constant *CP = ConstantPacked::get(CV); 794 SDOperand CPIdx = LegalizeOp(DAG.getConstantPool(CP, TLI.getPointerTy())); 795 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL)); 796 break; 797 } 798 case ISD::TokenFactor: 799 if (Node->getNumOperands() == 2) { 800 bool Changed = false; 801 SDOperand Op0 = LegalizeOp(Node->getOperand(0)); 802 SDOperand Op1 = LegalizeOp(Node->getOperand(1)); 803 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1)) 804 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1); 805 } else { 806 std::vector<SDOperand> Ops; 807 bool Changed = false; 808 // Legalize the operands. 809 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 810 SDOperand Op = Node->getOperand(i); 811 Ops.push_back(LegalizeOp(Op)); 812 Changed |= Ops[i] != Op; 813 } 814 if (Changed) 815 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 816 } 817 break; 818 819 case ISD::CALLSEQ_START: 820 case ISD::CALLSEQ_END: 821 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 822 // Do not try to legalize the target-specific arguments (#1+) 823 Tmp2 = Node->getOperand(0); 824 if (Tmp1 != Tmp2) 825 Node->setAdjCallChain(Tmp1); 826 827 // If this has a flag input, do legalize it. 828 if (Node->getOperand(Node->getNumOperands()-1).getValueType() == MVT::Flag){ 829 Tmp1 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 830 if (Tmp1 != Node->getOperand(Node->getNumOperands()-1)) 831 Node->setAdjCallFlag(Tmp1); 832 } 833 834 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These 835 // nodes are treated specially and are mutated in place. This makes the dag 836 // legalization process more efficient and also makes libcall insertion 837 // easier. 838 break; 839 case ISD::DYNAMIC_STACKALLOC: { 840 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 841 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 842 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 843 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 844 Tmp3 != Node->getOperand(2)) { 845 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 846 std::vector<SDOperand> Ops; 847 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 848 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 849 } else 850 Result = Op.getValue(0); 851 852 Tmp1 = Result; 853 Tmp2 = Result.getValue(1); 854 switch (TLI.getOperationAction(Node->getOpcode(), 855 Node->getValueType(0))) { 856 default: assert(0 && "This action is not supported yet!"); 857 case TargetLowering::Expand: { 858 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 859 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 860 " not tell us which reg is the stack pointer!"); 861 SDOperand Chain = Tmp1.getOperand(0); 862 SDOperand Size = Tmp2.getOperand(1); 863 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0)); 864 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value 865 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain 866 break; 867 } 868 case TargetLowering::Custom: 869 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 870 if (Tmp3.Val) { 871 Tmp1 = LegalizeOp(Tmp3); 872 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 873 } 874 break; 875 case TargetLowering::Legal: 876 break; 877 } 878 // Since this op produce two values, make sure to remember that we 879 // legalized both of them. 880 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 881 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 882 return Op.ResNo ? Tmp2 : Tmp1; 883 } 884 case ISD::TAILCALL: 885 case ISD::CALL: { 886 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 887 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 888 889 bool Changed = false; 890 std::vector<SDOperand> Ops; 891 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 892 Ops.push_back(LegalizeOp(Node->getOperand(i))); 893 Changed |= Ops.back() != Node->getOperand(i); 894 } 895 896 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 897 std::vector<MVT::ValueType> RetTyVTs; 898 RetTyVTs.reserve(Node->getNumValues()); 899 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 900 RetTyVTs.push_back(Node->getValueType(i)); 901 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 902 Node->getOpcode() == ISD::TAILCALL), 0); 903 } else { 904 Result = Result.getValue(0); 905 } 906 // Since calls produce multiple values, make sure to remember that we 907 // legalized all of them. 908 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 909 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 910 return Result.getValue(Op.ResNo); 911 } 912 case ISD::BR: 913 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 914 if (Tmp1 != Node->getOperand(0)) 915 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 916 break; 917 918 case ISD::BRCOND: 919 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 920 921 switch (getTypeAction(Node->getOperand(1).getValueType())) { 922 case Expand: assert(0 && "It's impossible to expand bools"); 923 case Legal: 924 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 925 break; 926 case Promote: 927 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 928 break; 929 } 930 931 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 932 default: assert(0 && "This action is not supported yet!"); 933 case TargetLowering::Expand: 934 // Expand brcond's setcc into its constituent parts and create a BR_CC 935 // Node. 936 if (Tmp2.getOpcode() == ISD::SETCC) { 937 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 938 Tmp2.getOperand(0), Tmp2.getOperand(1), 939 Node->getOperand(2)); 940 } else { 941 // Make sure the condition is either zero or one. It may have been 942 // promoted from something else. 943 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 944 945 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 946 DAG.getCondCode(ISD::SETNE), Tmp2, 947 DAG.getConstant(0, Tmp2.getValueType()), 948 Node->getOperand(2)); 949 } 950 Result = LegalizeOp(Result); // Relegalize new nodes. 951 break; 952 case TargetLowering::Custom: { 953 SDOperand Tmp = 954 TLI.LowerOperation(DAG.getNode(ISD::BRCOND, Node->getValueType(0), 955 Tmp1, Tmp2, Node->getOperand(2)), DAG); 956 if (Tmp.Val) { 957 Result = LegalizeOp(Tmp); 958 break; 959 } 960 // FALLTHROUGH if the target thinks it is legal. 961 } 962 case TargetLowering::Legal: 963 // Basic block destination (Op#2) is always legal. 964 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 965 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 966 Node->getOperand(2)); 967 break; 968 } 969 break; 970 case ISD::BR_CC: 971 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 972 if (!isTypeLegal(Node->getOperand(2).getValueType())) { 973 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 974 Node->getOperand(2), // LHS 975 Node->getOperand(3), // RHS 976 Node->getOperand(1))); 977 // If we get a SETCC back from legalizing the SETCC node we just 978 // created, then use its LHS, RHS, and CC directly in creating a new 979 // node. Otherwise, select between the true and false value based on 980 // comparing the result of the legalized with zero. 981 if (Tmp2.getOpcode() == ISD::SETCC) { 982 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 983 Tmp2.getOperand(0), Tmp2.getOperand(1), 984 Node->getOperand(4)); 985 } else { 986 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 987 DAG.getCondCode(ISD::SETNE), 988 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 989 Node->getOperand(4)); 990 } 991 break; 992 } 993 994 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 995 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 996 997 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 998 default: assert(0 && "Unexpected action for BR_CC!"); 999 case TargetLowering::Custom: { 1000 Tmp4 = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 1001 Tmp2, Tmp3, Node->getOperand(4)); 1002 Tmp4 = TLI.LowerOperation(Tmp4, DAG); 1003 if (Tmp4.Val) { 1004 Result = LegalizeOp(Tmp4); 1005 break; 1006 } 1007 } // FALLTHROUGH if the target doesn't want to lower this op after all. 1008 case TargetLowering::Legal: 1009 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 1010 Tmp3 != Node->getOperand(3)) { 1011 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 1012 Tmp2, Tmp3, Node->getOperand(4)); 1013 } 1014 break; 1015 } 1016 break; 1017 case ISD::BRCONDTWOWAY: 1018 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1019 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1020 case Expand: assert(0 && "It's impossible to expand bools"); 1021 case Legal: 1022 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1023 break; 1024 case Promote: 1025 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1026 break; 1027 } 1028 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 1029 // pair. 1030 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 1031 case TargetLowering::Promote: 1032 default: assert(0 && "This action is not supported yet!"); 1033 case TargetLowering::Legal: 1034 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1035 std::vector<SDOperand> Ops; 1036 Ops.push_back(Tmp1); 1037 Ops.push_back(Tmp2); 1038 Ops.push_back(Node->getOperand(2)); 1039 Ops.push_back(Node->getOperand(3)); 1040 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 1041 } 1042 break; 1043 case TargetLowering::Expand: 1044 // If BRTWOWAY_CC is legal for this target, then simply expand this node 1045 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 1046 // BRCOND/BR pair. 1047 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 1048 if (Tmp2.getOpcode() == ISD::SETCC) { 1049 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 1050 Tmp2.getOperand(0), Tmp2.getOperand(1), 1051 Node->getOperand(2), Node->getOperand(3)); 1052 } else { 1053 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 1054 DAG.getConstant(0, Tmp2.getValueType()), 1055 Node->getOperand(2), Node->getOperand(3)); 1056 } 1057 } else { 1058 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 1059 Node->getOperand(2)); 1060 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 1061 } 1062 Result = LegalizeOp(Result); // Relegalize new nodes. 1063 break; 1064 } 1065 break; 1066 case ISD::BRTWOWAY_CC: 1067 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1068 if (isTypeLegal(Node->getOperand(2).getValueType())) { 1069 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 1070 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 1071 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 1072 Tmp3 != Node->getOperand(3)) { 1073 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3, 1074 Node->getOperand(4), Node->getOperand(5)); 1075 } 1076 break; 1077 } else { 1078 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1079 Node->getOperand(2), // LHS 1080 Node->getOperand(3), // RHS 1081 Node->getOperand(1))); 1082 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 1083 // pair. 1084 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 1085 default: assert(0 && "This action is not supported yet!"); 1086 case TargetLowering::Legal: 1087 // If we get a SETCC back from legalizing the SETCC node we just 1088 // created, then use its LHS, RHS, and CC directly in creating a new 1089 // node. Otherwise, select between the true and false value based on 1090 // comparing the result of the legalized with zero. 1091 if (Tmp2.getOpcode() == ISD::SETCC) { 1092 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 1093 Tmp2.getOperand(0), Tmp2.getOperand(1), 1094 Node->getOperand(4), Node->getOperand(5)); 1095 } else { 1096 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 1097 DAG.getConstant(0, Tmp2.getValueType()), 1098 Node->getOperand(4), Node->getOperand(5)); 1099 } 1100 break; 1101 case TargetLowering::Expand: 1102 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 1103 Node->getOperand(4)); 1104 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 1105 break; 1106 } 1107 Result = LegalizeOp(Result); // Relegalize new nodes. 1108 } 1109 break; 1110 case ISD::LOAD: { 1111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1112 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1113 1114 MVT::ValueType VT = Node->getValueType(0); 1115 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1116 default: assert(0 && "This action is not supported yet!"); 1117 case TargetLowering::Custom: { 1118 SDOperand Op = DAG.getLoad(VT, Tmp1, Tmp2, Node->getOperand(2)); 1119 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 1120 if (Tmp.Val) { 1121 Result = LegalizeOp(Tmp); 1122 // Since loads produce two values, make sure to remember that we 1123 // legalized both of them. 1124 AddLegalizedOperand(SDOperand(Node, 0), Result); 1125 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1126 return Result.getValue(Op.ResNo); 1127 } 1128 // FALLTHROUGH if the target thinks it is legal. 1129 } 1130 case TargetLowering::Legal: 1131 if (Tmp1 != Node->getOperand(0) || 1132 Tmp2 != Node->getOperand(1)) 1133 Result = DAG.getLoad(VT, Tmp1, Tmp2, Node->getOperand(2)); 1134 else 1135 Result = SDOperand(Node, 0); 1136 1137 // Since loads produce two values, make sure to remember that we legalized 1138 // both of them. 1139 AddLegalizedOperand(SDOperand(Node, 0), Result); 1140 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1141 return Result.getValue(Op.ResNo); 1142 } 1143 assert(0 && "Unreachable"); 1144 } 1145 case ISD::EXTLOAD: 1146 case ISD::SEXTLOAD: 1147 case ISD::ZEXTLOAD: { 1148 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1149 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1150 1151 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 1152 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 1153 default: assert(0 && "This action is not supported yet!"); 1154 case TargetLowering::Promote: 1155 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 1156 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1157 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 1158 // Since loads produce two values, make sure to remember that we legalized 1159 // both of them. 1160 AddLegalizedOperand(SDOperand(Node, 0), Result); 1161 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1162 return Result.getValue(Op.ResNo); 1163 1164 case TargetLowering::Custom: { 1165 SDOperand Op = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1166 Tmp1, Tmp2, Node->getOperand(2), 1167 SrcVT); 1168 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 1169 if (Tmp.Val) { 1170 Result = LegalizeOp(Tmp); 1171 // Since loads produce two values, make sure to remember that we legalized 1172 // both of them. 1173 AddLegalizedOperand(SDOperand(Node, 0), Result); 1174 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1175 return Result.getValue(Op.ResNo); 1176 } 1177 // FALLTHROUGH if the target thinks it is legal. 1178 } 1179 case TargetLowering::Legal: 1180 if (Tmp1 != Node->getOperand(0) || 1181 Tmp2 != Node->getOperand(1)) 1182 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1183 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1184 else 1185 Result = SDOperand(Node, 0); 1186 1187 // Since loads produce two values, make sure to remember that we legalized 1188 // both of them. 1189 AddLegalizedOperand(SDOperand(Node, 0), Result); 1190 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1191 return Result.getValue(Op.ResNo); 1192 case TargetLowering::Expand: 1193 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1194 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1195 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 1196 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1197 Result = LegalizeOp(Result); // Relegalize new nodes. 1198 Load = LegalizeOp(Load); 1199 AddLegalizedOperand(SDOperand(Node, 0), Result); 1200 AddLegalizedOperand(SDOperand(Node, 1), Load.getValue(1)); 1201 if (Op.ResNo) 1202 return Load.getValue(1); 1203 return Result; 1204 } 1205 assert(Node->getOpcode() != ISD::EXTLOAD && 1206 "EXTLOAD should always be supported!"); 1207 // Turn the unsupported load into an EXTLOAD followed by an explicit 1208 // zero/sign extend inreg. 1209 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1210 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1211 SDOperand ValRes; 1212 if (Node->getOpcode() == ISD::SEXTLOAD) 1213 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1214 Result, DAG.getValueType(SrcVT)); 1215 else 1216 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1217 Result = LegalizeOp(Result); // Relegalize new nodes. 1218 ValRes = LegalizeOp(ValRes); // Relegalize new nodes. 1219 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 1220 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1221 if (Op.ResNo) 1222 return Result.getValue(1); 1223 return ValRes; 1224 } 1225 assert(0 && "Unreachable"); 1226 } 1227 case ISD::EXTRACT_ELEMENT: { 1228 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1229 switch (getTypeAction(OpTy)) { 1230 default: 1231 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1232 break; 1233 case Legal: 1234 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1235 // 1 -> Hi 1236 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1237 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1238 TLI.getShiftAmountTy())); 1239 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1240 } else { 1241 // 0 -> Lo 1242 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1243 Node->getOperand(0)); 1244 } 1245 Result = LegalizeOp(Result); 1246 break; 1247 case Expand: 1248 // Get both the low and high parts. 1249 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1250 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1251 Result = Tmp2; // 1 -> Hi 1252 else 1253 Result = Tmp1; // 0 -> Lo 1254 break; 1255 } 1256 break; 1257 } 1258 1259 case ISD::CopyToReg: 1260 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1261 1262 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1263 "Register type must be legal!"); 1264 // Legalize the incoming value (must be a legal type). 1265 Tmp2 = LegalizeOp(Node->getOperand(2)); 1266 if (Node->getNumValues() == 1) { 1267 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2)) 1268 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1, 1269 Node->getOperand(1), Tmp2); 1270 } else { 1271 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1272 if (Node->getNumOperands() == 4) 1273 Tmp3 = LegalizeOp(Node->getOperand(3)); 1274 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 1275 (Node->getNumOperands() == 4 && Tmp3 != Node->getOperand(3))) { 1276 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 1277 Result = DAG.getCopyToReg(Tmp1, Reg, Tmp2, Tmp3); 1278 } 1279 1280 // Since this produces two values, make sure to remember that we legalized 1281 // both of them. 1282 AddLegalizedOperand(SDOperand(Node, 0), Result); 1283 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1284 return Result.getValue(Op.ResNo); 1285 } 1286 break; 1287 1288 case ISD::RET: 1289 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1290 switch (Node->getNumOperands()) { 1291 case 2: // ret val 1292 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1293 case Legal: 1294 Tmp2 = LegalizeOp(Node->getOperand(1)); 1295 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1296 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1297 break; 1298 case Expand: { 1299 SDOperand Lo, Hi; 1300 ExpandOp(Node->getOperand(1), Lo, Hi); 1301 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1302 break; 1303 } 1304 case Promote: 1305 Tmp2 = PromoteOp(Node->getOperand(1)); 1306 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1307 break; 1308 } 1309 break; 1310 case 1: // ret void 1311 if (Tmp1 != Node->getOperand(0)) 1312 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 1313 break; 1314 default: { // ret <values> 1315 std::vector<SDOperand> NewValues; 1316 NewValues.push_back(Tmp1); 1317 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1318 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1319 case Legal: 1320 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1321 break; 1322 case Expand: { 1323 SDOperand Lo, Hi; 1324 ExpandOp(Node->getOperand(i), Lo, Hi); 1325 NewValues.push_back(Lo); 1326 NewValues.push_back(Hi); 1327 break; 1328 } 1329 case Promote: 1330 assert(0 && "Can't promote multiple return value yet!"); 1331 } 1332 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1333 break; 1334 } 1335 } 1336 1337 switch (TLI.getOperationAction(Node->getOpcode(), 1338 Node->getValueType(0))) { 1339 default: assert(0 && "This action is not supported yet!"); 1340 case TargetLowering::Custom: { 1341 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1342 if (Tmp.Val) { 1343 Result = LegalizeOp(Tmp); 1344 break; 1345 } 1346 // FALLTHROUGH if the target thinks it is legal. 1347 } 1348 case TargetLowering::Legal: 1349 // Nothing to do. 1350 break; 1351 } 1352 break; 1353 case ISD::STORE: { 1354 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1355 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1356 1357 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1358 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1359 if (CFP->getValueType(0) == MVT::f32) { 1360 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1361 DAG.getConstant(FloatToBits(CFP->getValue()), 1362 MVT::i32), 1363 Tmp2, 1364 Node->getOperand(3)); 1365 } else { 1366 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1367 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1368 DAG.getConstant(DoubleToBits(CFP->getValue()), 1369 MVT::i64), 1370 Tmp2, 1371 Node->getOperand(3)); 1372 } 1373 Result = LegalizeOp(Result); 1374 break; 1375 } 1376 1377 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1378 case Legal: { 1379 SDOperand Val = LegalizeOp(Node->getOperand(1)); 1380 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 1381 Tmp2 != Node->getOperand(2)) 1382 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 1383 Node->getOperand(3)); 1384 1385 MVT::ValueType VT = Result.Val->getOperand(1).getValueType(); 1386 switch (TLI.getOperationAction(Result.Val->getOpcode(), VT)) { 1387 default: assert(0 && "This action is not supported yet!"); 1388 case TargetLowering::Custom: { 1389 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1390 if (Tmp.Val) { 1391 Result = LegalizeOp(Tmp); 1392 break; 1393 } 1394 // FALLTHROUGH if the target thinks it is legal. 1395 } 1396 case TargetLowering::Legal: 1397 // Nothing to do. 1398 break; 1399 } 1400 break; 1401 } 1402 case Promote: 1403 // Truncate the value and store the result. 1404 Tmp3 = PromoteOp(Node->getOperand(1)); 1405 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1406 Node->getOperand(3), 1407 DAG.getValueType(Node->getOperand(1).getValueType())); 1408 break; 1409 1410 case Expand: 1411 SDOperand Lo, Hi; 1412 unsigned IncrementSize; 1413 ExpandOp(Node->getOperand(1), Lo, Hi); 1414 1415 if (!TLI.isLittleEndian()) 1416 std::swap(Lo, Hi); 1417 1418 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1419 Node->getOperand(3)); 1420 // If this is a vector type, then we have to calculate the increment as 1421 // the product of the element size in bytes, and the number of elements 1422 // in the high half of the vector. 1423 if (MVT::Vector == Hi.getValueType()) { 1424 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue(); 1425 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT(); 1426 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8; 1427 } else { 1428 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1429 } 1430 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1431 getIntPtrConstant(IncrementSize)); 1432 assert(isTypeLegal(Tmp2.getValueType()) && 1433 "Pointers must be legal!"); 1434 //Again, claiming both parts of the store came form the same Instr 1435 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1436 Node->getOperand(3)); 1437 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1438 break; 1439 } 1440 break; 1441 } 1442 case ISD::PCMARKER: 1443 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1444 if (Tmp1 != Node->getOperand(0)) 1445 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 1446 break; 1447 case ISD::STACKSAVE: 1448 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1449 if (Tmp1 != Node->getOperand(0)) { 1450 std::vector<MVT::ValueType> VTs; 1451 VTs.push_back(Node->getValueType(0)); 1452 VTs.push_back(MVT::Other); 1453 std::vector<SDOperand> Ops; 1454 Ops.push_back(Tmp1); 1455 Result = DAG.getNode(ISD::STACKSAVE, VTs, Ops); 1456 } 1457 1458 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 1459 default: assert(0 && "This action is not supported yet!"); 1460 case TargetLowering::Custom: { 1461 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1462 if (Tmp.Val) { 1463 Result = LegalizeOp(Tmp); 1464 break; 1465 } 1466 // FALLTHROUGH if the target thinks it is legal. 1467 } 1468 case TargetLowering::Legal: 1469 // Since stacksave produce two values, make sure to remember that we 1470 // legalized both of them. 1471 AddLegalizedOperand(SDOperand(Node, 0), Result); 1472 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1473 return Result.getValue(Op.ResNo); 1474 case TargetLowering::Expand: 1475 // Expand to CopyFromReg if the target set 1476 // StackPointerRegisterToSaveRestore. 1477 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1478 Tmp1 = DAG.getCopyFromReg(Tmp1, SP, 1479 Node->getValueType(0)); 1480 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1481 AddLegalizedOperand(SDOperand(Node, 1), Tmp1.getValue(1)); 1482 return Tmp1.getValue(Op.ResNo); 1483 } else { 1484 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 1485 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1486 AddLegalizedOperand(SDOperand(Node, 1), Node->getOperand(0)); 1487 return Op.ResNo ? Node->getOperand(0) : Tmp1; 1488 } 1489 } 1490 1491 case ISD::STACKRESTORE: 1492 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1493 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1494 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1495 Result = DAG.getNode(ISD::STACKRESTORE, MVT::Other, Tmp1, Tmp2); 1496 1497 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 1498 default: assert(0 && "This action is not supported yet!"); 1499 case TargetLowering::Custom: { 1500 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1501 if (Tmp.Val) { 1502 Result = LegalizeOp(Tmp); 1503 break; 1504 } 1505 // FALLTHROUGH if the target thinks it is legal. 1506 } 1507 case TargetLowering::Legal: 1508 break; 1509 case TargetLowering::Expand: 1510 // Expand to CopyToReg if the target set 1511 // StackPointerRegisterToSaveRestore. 1512 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1513 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 1514 } else { 1515 Result = Tmp1; 1516 } 1517 break; 1518 } 1519 break; 1520 1521 case ISD::READCYCLECOUNTER: 1522 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1523 if (Tmp1 != Node->getOperand(0)) { 1524 std::vector<MVT::ValueType> rtypes; 1525 std::vector<SDOperand> rvals; 1526 rtypes.push_back(MVT::i64); 1527 rtypes.push_back(MVT::Other); 1528 rvals.push_back(Tmp1); 1529 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals); 1530 } 1531 1532 // Since rdcc produce two values, make sure to remember that we legalized 1533 // both of them. 1534 AddLegalizedOperand(SDOperand(Node, 0), Result); 1535 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1536 return Result.getValue(Op.ResNo); 1537 1538 case ISD::TRUNCSTORE: { 1539 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1540 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1541 1542 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1543 case Promote: 1544 case Expand: 1545 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 1546 case Legal: 1547 Tmp2 = LegalizeOp(Node->getOperand(1)); 1548 1549 // The only promote case we handle is TRUNCSTORE:i1 X into 1550 // -> TRUNCSTORE:i8 (and X, 1) 1551 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1552 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1553 TargetLowering::Promote) { 1554 // Promote the bool to a mask then store. 1555 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1556 DAG.getConstant(1, Tmp2.getValueType())); 1557 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1558 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1559 1560 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1561 Tmp3 != Node->getOperand(2)) { 1562 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1563 Node->getOperand(3), Node->getOperand(4)); 1564 } 1565 1566 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT(); 1567 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) { 1568 default: assert(0 && "This action is not supported yet!"); 1569 case TargetLowering::Custom: { 1570 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 1571 if (Tmp.Val) { 1572 Result = LegalizeOp(Tmp); 1573 break; 1574 } 1575 // FALLTHROUGH if the target thinks it is legal. 1576 } 1577 case TargetLowering::Legal: 1578 // Nothing to do. 1579 break; 1580 } 1581 break; 1582 } 1583 break; 1584 } 1585 case ISD::SELECT: 1586 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1587 case Expand: assert(0 && "It's impossible to expand bools"); 1588 case Legal: 1589 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1590 break; 1591 case Promote: 1592 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1593 break; 1594 } 1595 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1596 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1597 1598 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1599 default: assert(0 && "This action is not supported yet!"); 1600 case TargetLowering::Expand: 1601 if (Tmp1.getOpcode() == ISD::SETCC) { 1602 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1603 Tmp2, Tmp3, 1604 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1605 } else { 1606 // Make sure the condition is either zero or one. It may have been 1607 // promoted from something else. 1608 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1609 Result = DAG.getSelectCC(Tmp1, 1610 DAG.getConstant(0, Tmp1.getValueType()), 1611 Tmp2, Tmp3, ISD::SETNE); 1612 } 1613 Result = LegalizeOp(Result); // Relegalize new nodes. 1614 break; 1615 case TargetLowering::Custom: { 1616 SDOperand Tmp = 1617 TLI.LowerOperation(DAG.getNode(ISD::SELECT, Node->getValueType(0), 1618 Tmp1, Tmp2, Tmp3), DAG); 1619 if (Tmp.Val) { 1620 Result = LegalizeOp(Tmp); 1621 break; 1622 } 1623 // FALLTHROUGH if the target thinks it is legal. 1624 } 1625 case TargetLowering::Legal: 1626 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1627 Tmp3 != Node->getOperand(2)) 1628 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 1629 Tmp1, Tmp2, Tmp3); 1630 break; 1631 case TargetLowering::Promote: { 1632 MVT::ValueType NVT = 1633 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1634 unsigned ExtOp, TruncOp; 1635 if (MVT::isInteger(Tmp2.getValueType())) { 1636 ExtOp = ISD::ANY_EXTEND; 1637 TruncOp = ISD::TRUNCATE; 1638 } else { 1639 ExtOp = ISD::FP_EXTEND; 1640 TruncOp = ISD::FP_ROUND; 1641 } 1642 // Promote each of the values to the new type. 1643 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1644 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1645 // Perform the larger operation, then round down. 1646 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1647 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1648 Result = LegalizeOp(Result); 1649 break; 1650 } 1651 } 1652 break; 1653 case ISD::SELECT_CC: 1654 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1655 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1656 1657 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1658 // Everything is legal, see if we should expand this op or something. 1659 switch (TLI.getOperationAction(ISD::SELECT_CC, 1660 Node->getOperand(0).getValueType())) { 1661 default: assert(0 && "This action is not supported yet!"); 1662 case TargetLowering::Custom: { 1663 SDOperand Tmp = 1664 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), 1665 Node->getOperand(0), 1666 Node->getOperand(1), Tmp3, Tmp4, 1667 Node->getOperand(4)), DAG); 1668 if (Tmp.Val) { 1669 Result = LegalizeOp(Tmp); 1670 break; 1671 } 1672 } // FALLTHROUGH if the target can't lower this operation after all. 1673 case TargetLowering::Legal: 1674 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1675 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1676 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1677 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { 1678 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1,Tmp2, 1679 Tmp3, Tmp4, Node->getOperand(4)); 1680 } 1681 break; 1682 } 1683 break; 1684 } else { 1685 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1686 Node->getOperand(0), // LHS 1687 Node->getOperand(1), // RHS 1688 Node->getOperand(4))); 1689 // If we get a SETCC back from legalizing the SETCC node we just 1690 // created, then use its LHS, RHS, and CC directly in creating a new 1691 // node. Otherwise, select between the true and false value based on 1692 // comparing the result of the legalized with zero. 1693 if (Tmp1.getOpcode() == ISD::SETCC) { 1694 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1695 Tmp1.getOperand(0), Tmp1.getOperand(1), 1696 Tmp3, Tmp4, Tmp1.getOperand(2)); 1697 } else { 1698 Result = DAG.getSelectCC(Tmp1, 1699 DAG.getConstant(0, Tmp1.getValueType()), 1700 Tmp3, Tmp4, ISD::SETNE); 1701 } 1702 } 1703 break; 1704 case ISD::SETCC: 1705 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1706 case Legal: 1707 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1708 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1709 break; 1710 case Promote: 1711 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1712 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1713 1714 // If this is an FP compare, the operands have already been extended. 1715 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1716 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1717 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1718 1719 // Otherwise, we have to insert explicit sign or zero extends. Note 1720 // that we could insert sign extends for ALL conditions, but zero extend 1721 // is cheaper on many machines (an AND instead of two shifts), so prefer 1722 // it. 1723 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1724 default: assert(0 && "Unknown integer comparison!"); 1725 case ISD::SETEQ: 1726 case ISD::SETNE: 1727 case ISD::SETUGE: 1728 case ISD::SETUGT: 1729 case ISD::SETULE: 1730 case ISD::SETULT: 1731 // ALL of these operations will work if we either sign or zero extend 1732 // the operands (including the unsigned comparisons!). Zero extend is 1733 // usually a simpler/cheaper operation, so prefer it. 1734 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1735 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1736 break; 1737 case ISD::SETGE: 1738 case ISD::SETGT: 1739 case ISD::SETLT: 1740 case ISD::SETLE: 1741 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1742 DAG.getValueType(VT)); 1743 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1744 DAG.getValueType(VT)); 1745 break; 1746 } 1747 } 1748 break; 1749 case Expand: 1750 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1751 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1752 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1753 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1754 case ISD::SETEQ: 1755 case ISD::SETNE: 1756 if (RHSLo == RHSHi) 1757 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1758 if (RHSCST->isAllOnesValue()) { 1759 // Comparison to -1. 1760 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1761 Tmp2 = RHSLo; 1762 break; 1763 } 1764 1765 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1766 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1767 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1768 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1769 break; 1770 default: 1771 // If this is a comparison of the sign bit, just look at the top part. 1772 // X > -1, x < 0 1773 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1774 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1775 CST->getValue() == 0) || // X < 0 1776 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1777 (CST->isAllOnesValue()))) { // X > -1 1778 Tmp1 = LHSHi; 1779 Tmp2 = RHSHi; 1780 break; 1781 } 1782 1783 // FIXME: This generated code sucks. 1784 ISD::CondCode LowCC; 1785 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1786 default: assert(0 && "Unknown integer setcc!"); 1787 case ISD::SETLT: 1788 case ISD::SETULT: LowCC = ISD::SETULT; break; 1789 case ISD::SETGT: 1790 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1791 case ISD::SETLE: 1792 case ISD::SETULE: LowCC = ISD::SETULE; break; 1793 case ISD::SETGE: 1794 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1795 } 1796 1797 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1798 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1799 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1800 1801 // NOTE: on targets without efficient SELECT of bools, we can always use 1802 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1803 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1804 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1805 Node->getOperand(2)); 1806 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1807 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1808 Result, Tmp1, Tmp2)); 1809 AddLegalizedOperand(SDOperand(Node, 0), Result); 1810 return Result; 1811 } 1812 } 1813 1814 switch(TLI.getOperationAction(ISD::SETCC, 1815 Node->getOperand(0).getValueType())) { 1816 default: 1817 assert(0 && "Cannot handle this action for SETCC yet!"); 1818 break; 1819 case TargetLowering::Promote: { 1820 // First step, figure out the appropriate operation to use. 1821 // Allow SETCC to not be supported for all legal data types 1822 // Mostly this targets FP 1823 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1824 MVT::ValueType OldVT = NewInTy; 1825 1826 // Scan for the appropriate larger type to use. 1827 while (1) { 1828 NewInTy = (MVT::ValueType)(NewInTy+1); 1829 1830 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1831 "Fell off of the edge of the integer world"); 1832 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1833 "Fell off of the edge of the floating point world"); 1834 1835 // If the target supports SETCC of this type, use it. 1836 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 1837 break; 1838 } 1839 if (MVT::isInteger(NewInTy)) 1840 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1841 else { 1842 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1843 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1844 } 1845 1846 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1847 Node->getOperand(2)); 1848 Result = LegalizeOp(Result); 1849 break; 1850 } 1851 case TargetLowering::Custom: { 1852 SDOperand Tmp = 1853 TLI.LowerOperation(DAG.getNode(ISD::SETCC, Node->getValueType(0), 1854 Tmp1, Tmp2, Node->getOperand(2)), DAG); 1855 if (Tmp.Val) { 1856 Result = LegalizeOp(Tmp); 1857 break; 1858 } 1859 // FALLTHROUGH if the target thinks it is legal. 1860 } 1861 case TargetLowering::Legal: 1862 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1863 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1864 Node->getOperand(2)); 1865 break; 1866 case TargetLowering::Expand: 1867 // Expand a setcc node into a select_cc of the same condition, lhs, and 1868 // rhs that selects between const 1 (true) and const 0 (false). 1869 MVT::ValueType VT = Node->getValueType(0); 1870 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1871 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1872 Node->getOperand(2)); 1873 Result = LegalizeOp(Result); 1874 break; 1875 } 1876 break; 1877 1878 case ISD::MEMSET: 1879 case ISD::MEMCPY: 1880 case ISD::MEMMOVE: { 1881 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1882 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1883 1884 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1885 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1886 case Expand: assert(0 && "Cannot expand a byte!"); 1887 case Legal: 1888 Tmp3 = LegalizeOp(Node->getOperand(2)); 1889 break; 1890 case Promote: 1891 Tmp3 = PromoteOp(Node->getOperand(2)); 1892 break; 1893 } 1894 } else { 1895 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1896 } 1897 1898 SDOperand Tmp4; 1899 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1900 case Expand: { 1901 // Length is too big, just take the lo-part of the length. 1902 SDOperand HiPart; 1903 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1904 break; 1905 } 1906 case Legal: 1907 Tmp4 = LegalizeOp(Node->getOperand(3)); 1908 break; 1909 case Promote: 1910 Tmp4 = PromoteOp(Node->getOperand(3)); 1911 break; 1912 } 1913 1914 SDOperand Tmp5; 1915 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1916 case Expand: assert(0 && "Cannot expand this yet!"); 1917 case Legal: 1918 Tmp5 = LegalizeOp(Node->getOperand(4)); 1919 break; 1920 case Promote: 1921 Tmp5 = PromoteOp(Node->getOperand(4)); 1922 break; 1923 } 1924 1925 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1926 default: assert(0 && "This action not implemented for this operation!"); 1927 case TargetLowering::Custom: { 1928 SDOperand Tmp = 1929 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 1930 Tmp2, Tmp3, Tmp4, Tmp5), DAG); 1931 if (Tmp.Val) { 1932 Result = LegalizeOp(Tmp); 1933 break; 1934 } 1935 // FALLTHROUGH if the target thinks it is legal. 1936 } 1937 case TargetLowering::Legal: 1938 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1939 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 1940 Tmp5 != Node->getOperand(4)) { 1941 std::vector<SDOperand> Ops; 1942 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 1943 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 1944 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 1945 } 1946 break; 1947 case TargetLowering::Expand: { 1948 // Otherwise, the target does not support this operation. Lower the 1949 // operation to an explicit libcall as appropriate. 1950 MVT::ValueType IntPtr = TLI.getPointerTy(); 1951 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1952 std::vector<std::pair<SDOperand, const Type*> > Args; 1953 1954 const char *FnName = 0; 1955 if (Node->getOpcode() == ISD::MEMSET) { 1956 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1957 // Extend the ubyte argument to be an int value for the call. 1958 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1959 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1960 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1961 1962 FnName = "memset"; 1963 } else if (Node->getOpcode() == ISD::MEMCPY || 1964 Node->getOpcode() == ISD::MEMMOVE) { 1965 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1966 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1967 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1968 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1969 } else { 1970 assert(0 && "Unknown op!"); 1971 } 1972 1973 std::pair<SDOperand,SDOperand> CallResult = 1974 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1975 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1976 Result = LegalizeOp(CallResult.second); 1977 break; 1978 } 1979 } 1980 break; 1981 } 1982 1983 case ISD::READPORT: 1984 Tmp1 = LegalizeOp(Node->getOperand(0)); 1985 Tmp2 = LegalizeOp(Node->getOperand(1)); 1986 1987 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1988 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1989 std::vector<SDOperand> Ops; 1990 Ops.push_back(Tmp1); 1991 Ops.push_back(Tmp2); 1992 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1993 } else 1994 Result = SDOperand(Node, 0); 1995 // Since these produce two values, make sure to remember that we legalized 1996 // both of them. 1997 AddLegalizedOperand(SDOperand(Node, 0), Result); 1998 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1999 return Result.getValue(Op.ResNo); 2000 case ISD::WRITEPORT: 2001 Tmp1 = LegalizeOp(Node->getOperand(0)); 2002 Tmp2 = LegalizeOp(Node->getOperand(1)); 2003 Tmp3 = LegalizeOp(Node->getOperand(2)); 2004 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 2005 Tmp3 != Node->getOperand(2)) 2006 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 2007 break; 2008 2009 case ISD::READIO: 2010 Tmp1 = LegalizeOp(Node->getOperand(0)); 2011 Tmp2 = LegalizeOp(Node->getOperand(1)); 2012 2013 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2014 case TargetLowering::Custom: 2015 default: assert(0 && "This action not implemented for this operation!"); 2016 case TargetLowering::Legal: 2017 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 2018 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 2019 std::vector<SDOperand> Ops; 2020 Ops.push_back(Tmp1); 2021 Ops.push_back(Tmp2); 2022 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 2023 } else 2024 Result = SDOperand(Node, 0); 2025 break; 2026 case TargetLowering::Expand: 2027 // Replace this with a load from memory. 2028 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 2029 Node->getOperand(1), DAG.getSrcValue(NULL)); 2030 Result = LegalizeOp(Result); 2031 break; 2032 } 2033 2034 // Since these produce two values, make sure to remember that we legalized 2035 // both of them. 2036 AddLegalizedOperand(SDOperand(Node, 0), Result); 2037 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2038 return Result.getValue(Op.ResNo); 2039 2040 case ISD::WRITEIO: 2041 Tmp1 = LegalizeOp(Node->getOperand(0)); 2042 Tmp2 = LegalizeOp(Node->getOperand(1)); 2043 Tmp3 = LegalizeOp(Node->getOperand(2)); 2044 2045 switch (TLI.getOperationAction(Node->getOpcode(), 2046 Node->getOperand(1).getValueType())) { 2047 case TargetLowering::Custom: 2048 default: assert(0 && "This action not implemented for this operation!"); 2049 case TargetLowering::Legal: 2050 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 2051 Tmp3 != Node->getOperand(2)) 2052 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 2053 break; 2054 case TargetLowering::Expand: 2055 // Replace this with a store to memory. 2056 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 2057 Node->getOperand(1), Node->getOperand(2), 2058 DAG.getSrcValue(NULL)); 2059 Result = LegalizeOp(Result); 2060 break; 2061 } 2062 break; 2063 2064 case ISD::ADD_PARTS: 2065 case ISD::SUB_PARTS: 2066 case ISD::SHL_PARTS: 2067 case ISD::SRA_PARTS: 2068 case ISD::SRL_PARTS: { 2069 std::vector<SDOperand> Ops; 2070 bool Changed = false; 2071 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2072 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2073 Changed |= Ops.back() != Node->getOperand(i); 2074 } 2075 if (Changed) { 2076 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 2077 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 2078 } 2079 2080 switch (TLI.getOperationAction(Node->getOpcode(), 2081 Node->getValueType(0))) { 2082 default: assert(0 && "This action is not supported yet!"); 2083 case TargetLowering::Custom: { 2084 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 2085 if (Tmp.Val) { 2086 SDOperand Tmp2, RetVal(0,0); 2087 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2088 Tmp2 = LegalizeOp(Tmp.getValue(i)); 2089 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2090 if (i == Op.ResNo) 2091 RetVal = Tmp2; 2092 } 2093 assert(RetVal.Val && "Illegal result number"); 2094 return RetVal; 2095 } 2096 // FALLTHROUGH if the target thinks it is legal. 2097 } 2098 case TargetLowering::Legal: 2099 // Nothing to do. 2100 break; 2101 } 2102 2103 // Since these produce multiple values, make sure to remember that we 2104 // legalized all of them. 2105 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2106 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2107 return Result.getValue(Op.ResNo); 2108 } 2109 2110 // Binary operators 2111 case ISD::ADD: 2112 case ISD::SUB: 2113 case ISD::MUL: 2114 case ISD::MULHS: 2115 case ISD::MULHU: 2116 case ISD::UDIV: 2117 case ISD::SDIV: 2118 case ISD::AND: 2119 case ISD::OR: 2120 case ISD::XOR: 2121 case ISD::SHL: 2122 case ISD::SRL: 2123 case ISD::SRA: 2124 case ISD::FADD: 2125 case ISD::FSUB: 2126 case ISD::FMUL: 2127 case ISD::FDIV: 2128 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2129 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2130 case Expand: assert(0 && "Not possible"); 2131 case Legal: 2132 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2133 break; 2134 case Promote: 2135 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2136 break; 2137 } 2138 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2139 case TargetLowering::Custom: { 2140 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2); 2141 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 2142 if (Tmp.Val) { 2143 Tmp = LegalizeOp(Tmp); // Relegalize input. 2144 AddLegalizedOperand(Op, Tmp); 2145 return Tmp; 2146 } //else it was considered legal and we fall through 2147 } 2148 case TargetLowering::Legal: 2149 if (Tmp1 != Node->getOperand(0) || 2150 Tmp2 != Node->getOperand(1)) 2151 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 2152 break; 2153 default: 2154 assert(0 && "Operation not supported"); 2155 } 2156 break; 2157 2158 case ISD::BUILD_PAIR: { 2159 MVT::ValueType PairTy = Node->getValueType(0); 2160 // TODO: handle the case where the Lo and Hi operands are not of legal type 2161 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2162 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2163 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2164 case TargetLowering::Legal: 2165 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2166 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2167 break; 2168 case TargetLowering::Promote: 2169 case TargetLowering::Custom: 2170 assert(0 && "Cannot promote/custom this yet!"); 2171 case TargetLowering::Expand: 2172 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2173 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2174 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2175 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2176 TLI.getShiftAmountTy())); 2177 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2)); 2178 break; 2179 } 2180 break; 2181 } 2182 2183 case ISD::UREM: 2184 case ISD::SREM: 2185 case ISD::FREM: 2186 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2187 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2188 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2189 case TargetLowering::Custom: { 2190 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 2191 SDOperand Tmp = TLI.LowerOperation(Result, DAG); 2192 if (Tmp.Val) { 2193 Tmp = LegalizeOp(Tmp); // Relegalize input. 2194 AddLegalizedOperand(Op, Tmp); 2195 return Tmp; 2196 } //else it was considered legal and we fall through 2197 } 2198 case TargetLowering::Legal: 2199 if (Tmp1 != Node->getOperand(0) || 2200 Tmp2 != Node->getOperand(1)) 2201 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2202 Tmp2); 2203 break; 2204 case TargetLowering::Promote: 2205 assert(0 && "Cannot promote handle this yet!"); 2206 case TargetLowering::Expand: 2207 if (MVT::isInteger(Node->getValueType(0))) { 2208 MVT::ValueType VT = Node->getValueType(0); 2209 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2210 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 2211 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2212 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2213 } else { 2214 // Floating point mod -> fmod libcall. 2215 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 2216 SDOperand Dummy; 2217 Result = ExpandLibCall(FnName, Node, Dummy); 2218 } 2219 break; 2220 } 2221 break; 2222 2223 case ISD::VAARG: { 2224 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2225 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2226 2227 MVT::ValueType VT = Node->getValueType(0); 2228 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2229 default: assert(0 && "This action is not supported yet!"); 2230 case TargetLowering::Custom: { 2231 SDOperand Op = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 2232 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 2233 if (Tmp.Val) { 2234 Result = LegalizeOp(Tmp); 2235 break; 2236 } 2237 // FALLTHROUGH if the target thinks it is legal. 2238 } 2239 case TargetLowering::Legal: 2240 if (Tmp1 != Node->getOperand(0) || 2241 Tmp2 != Node->getOperand(1)) 2242 Result = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 2243 else 2244 Result = SDOperand(Node, 0); 2245 break; 2246 case TargetLowering::Expand: { 2247 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2248 Node->getOperand(2)); 2249 // Increment the pointer, VAList, to the next vaarg 2250 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2251 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2252 TLI.getPointerTy())); 2253 // Store the incremented VAList to the legalized pointer 2254 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 2255 Node->getOperand(2)); 2256 // Load the actual argument out of the pointer VAList 2257 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0)); 2258 Result = LegalizeOp(Result); 2259 break; 2260 } 2261 } 2262 // Since VAARG produces two values, make sure to remember that we 2263 // legalized both of them. 2264 AddLegalizedOperand(SDOperand(Node, 0), Result); 2265 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2266 return Result.getValue(Op.ResNo); 2267 } 2268 2269 case ISD::VACOPY: 2270 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2271 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 2272 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 2273 2274 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 2275 default: assert(0 && "This action is not supported yet!"); 2276 case TargetLowering::Custom: { 2277 SDOperand Op = DAG.getNode(ISD::VACOPY, MVT::Other, Tmp1, Tmp2, Tmp3, 2278 Node->getOperand(3), Node->getOperand(4)); 2279 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 2280 if (Tmp.Val) { 2281 Result = LegalizeOp(Tmp); 2282 break; 2283 } 2284 // FALLTHROUGH if the target thinks it is legal. 2285 } 2286 case TargetLowering::Legal: 2287 if (Tmp1 != Node->getOperand(0) || 2288 Tmp2 != Node->getOperand(1) || 2289 Tmp3 != Node->getOperand(2)) 2290 Result = DAG.getNode(ISD::VACOPY, MVT::Other, Tmp1, Tmp2, Tmp3, 2291 Node->getOperand(3), Node->getOperand(4)); 2292 break; 2293 case TargetLowering::Expand: 2294 // This defaults to loading a pointer from the input and storing it to the 2295 // output, returning the chain. 2296 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3)); 2297 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2, 2298 Node->getOperand(4)); 2299 Result = LegalizeOp(Result); 2300 break; 2301 } 2302 break; 2303 2304 case ISD::VAEND: 2305 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2306 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2307 2308 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 2309 default: assert(0 && "This action is not supported yet!"); 2310 case TargetLowering::Custom: { 2311 SDOperand Op = DAG.getNode(ISD::VAEND, MVT::Other, Tmp1, Tmp2, 2312 Node->getOperand(2)); 2313 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 2314 if (Tmp.Val) { 2315 Result = LegalizeOp(Tmp); 2316 break; 2317 } 2318 // FALLTHROUGH if the target thinks it is legal. 2319 } 2320 case TargetLowering::Legal: 2321 if (Tmp1 != Node->getOperand(0) || 2322 Tmp2 != Node->getOperand(1)) 2323 Result = DAG.getNode(ISD::VAEND, MVT::Other, Tmp1, Tmp2, 2324 Node->getOperand(2)); 2325 break; 2326 case TargetLowering::Expand: 2327 Result = Tmp1; // Default to a no-op, return the chain 2328 break; 2329 } 2330 break; 2331 2332 case ISD::VASTART: 2333 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2334 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2335 2336 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 2337 default: assert(0 && "This action is not supported yet!"); 2338 case TargetLowering::Custom: { 2339 SDOperand Op = DAG.getNode(ISD::VASTART, MVT::Other, Tmp1, Tmp2, 2340 Node->getOperand(2)); 2341 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 2342 if (Tmp.Val) { 2343 Result = LegalizeOp(Tmp); 2344 break; 2345 } 2346 // FALLTHROUGH if the target thinks it is legal. 2347 } 2348 case TargetLowering::Legal: 2349 if (Tmp1 != Node->getOperand(0) || 2350 Tmp2 != Node->getOperand(1)) 2351 Result = DAG.getNode(ISD::VASTART, MVT::Other, Tmp1, Tmp2, 2352 Node->getOperand(2)); 2353 break; 2354 } 2355 break; 2356 2357 case ISD::ROTL: 2358 case ISD::ROTR: 2359 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2360 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2361 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2362 case TargetLowering::Custom: 2363 case TargetLowering::Promote: 2364 case TargetLowering::Expand: 2365 assert(0 && "Cannot handle this yet!"); 2366 case TargetLowering::Legal: 2367 if (Tmp1 != Node->getOperand(0) || 2368 Tmp2 != Node->getOperand(1)) 2369 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2370 Tmp2); 2371 break; 2372 } 2373 break; 2374 2375 case ISD::BSWAP: 2376 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2377 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2378 case TargetLowering::Legal: 2379 if (Tmp1 != Node->getOperand(0)) 2380 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2381 break; 2382 case TargetLowering::Promote: { 2383 MVT::ValueType OVT = Tmp1.getValueType(); 2384 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2385 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT); 2386 2387 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2388 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2389 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2390 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2391 Result = LegalizeOp(Result); 2392 break; 2393 } 2394 case TargetLowering::Custom: 2395 assert(0 && "Cannot custom legalize this yet!"); 2396 case TargetLowering::Expand: { 2397 MVT::ValueType VT = Tmp1.getValueType(); 2398 switch (VT) { 2399 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 2400 case MVT::i16: 2401 Tmp2 = DAG.getNode(ISD::SHL, VT, Tmp1, 2402 DAG.getConstant(8, TLI.getShiftAmountTy())); 2403 Tmp1 = DAG.getNode(ISD::SRL, VT, Tmp1, 2404 DAG.getConstant(8, TLI.getShiftAmountTy())); 2405 Result = DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 2406 break; 2407 case MVT::i32: 2408 Tmp4 = DAG.getNode(ISD::SHL, VT, Tmp1, 2409 DAG.getConstant(24, TLI.getShiftAmountTy())); 2410 Tmp3 = DAG.getNode(ISD::SHL, VT, Tmp1, 2411 DAG.getConstant(8, TLI.getShiftAmountTy())); 2412 Tmp2 = DAG.getNode(ISD::SRL, VT, Tmp1, 2413 DAG.getConstant(8, TLI.getShiftAmountTy())); 2414 Tmp1 = DAG.getNode(ISD::SRL, VT, Tmp1, 2415 DAG.getConstant(24, TLI.getShiftAmountTy())); 2416 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2417 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2418 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 2419 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 2420 Result = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 2421 break; 2422 case MVT::i64: { 2423 SDOperand Tmp5, Tmp6, Tmp7, Tmp8; 2424 Tmp8 = DAG.getNode(ISD::SHL, VT, Tmp1, 2425 DAG.getConstant(56, TLI.getShiftAmountTy())); 2426 Tmp7 = DAG.getNode(ISD::SHL, VT, Tmp1, 2427 DAG.getConstant(40, TLI.getShiftAmountTy())); 2428 Tmp6 = DAG.getNode(ISD::SHL, VT, Tmp1, 2429 DAG.getConstant(24, TLI.getShiftAmountTy())); 2430 Tmp5 = DAG.getNode(ISD::SHL, VT, Tmp1, 2431 DAG.getConstant(8, TLI.getShiftAmountTy())); 2432 Tmp4 = DAG.getNode(ISD::SRL, VT, Tmp1, 2433 DAG.getConstant(8, TLI.getShiftAmountTy())); 2434 Tmp3 = DAG.getNode(ISD::SRL, VT, Tmp1, 2435 DAG.getConstant(24, TLI.getShiftAmountTy())); 2436 Tmp2 = DAG.getNode(ISD::SRL, VT, Tmp1, 2437 DAG.getConstant(40, TLI.getShiftAmountTy())); 2438 Tmp1 = DAG.getNode(ISD::SRL, VT, Tmp1, 2439 DAG.getConstant(56, TLI.getShiftAmountTy())); 2440 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, 2441 DAG.getConstant(0x00FF000000000000ULL, VT)); 2442 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp7, 2443 DAG.getConstant(0x0000FF0000000000ULL, VT)); 2444 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp7, 2445 DAG.getConstant(0x000000FF00000000ULL, VT)); 2446 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp7, 2447 DAG.getConstant(0x00000000FF000000ULL, VT)); 2448 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp7, 2449 DAG.getConstant(0x0000000000FF0000ULL, VT)); 2450 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp7, 2451 DAG.getConstant(0x000000000000FF00ULL, VT)); 2452 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 2453 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 2454 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 2455 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 2456 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 2457 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 2458 Result = DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 2459 break; 2460 } 2461 } 2462 Result = LegalizeOp(Result); 2463 break; 2464 } 2465 } 2466 break; 2467 2468 case ISD::CTPOP: 2469 case ISD::CTTZ: 2470 case ISD::CTLZ: 2471 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2472 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2473 case TargetLowering::Legal: 2474 if (Tmp1 != Node->getOperand(0)) 2475 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2476 break; 2477 case TargetLowering::Promote: { 2478 MVT::ValueType OVT = Tmp1.getValueType(); 2479 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2480 2481 // Zero extend the argument. 2482 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2483 // Perform the larger operation, then subtract if needed. 2484 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2485 switch(Node->getOpcode()) 2486 { 2487 case ISD::CTPOP: 2488 Result = Tmp1; 2489 break; 2490 case ISD::CTTZ: 2491 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2492 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2493 DAG.getConstant(getSizeInBits(NVT), NVT), 2494 ISD::SETEQ); 2495 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2496 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 2497 break; 2498 case ISD::CTLZ: 2499 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2500 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2501 DAG.getConstant(getSizeInBits(NVT) - 2502 getSizeInBits(OVT), NVT)); 2503 break; 2504 } 2505 Result = LegalizeOp(Result); 2506 break; 2507 } 2508 case TargetLowering::Custom: 2509 assert(0 && "Cannot custom handle this yet!"); 2510 case TargetLowering::Expand: 2511 switch(Node->getOpcode()) 2512 { 2513 case ISD::CTPOP: { 2514 static const uint64_t mask[6] = { 2515 0x5555555555555555ULL, 0x3333333333333333ULL, 2516 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2517 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2518 }; 2519 MVT::ValueType VT = Tmp1.getValueType(); 2520 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 2521 unsigned len = getSizeInBits(VT); 2522 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2523 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2524 Tmp2 = DAG.getConstant(mask[i], VT); 2525 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2526 Tmp1 = DAG.getNode(ISD::ADD, VT, 2527 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 2528 DAG.getNode(ISD::AND, VT, 2529 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 2530 Tmp2)); 2531 } 2532 Result = LegalizeOp(Tmp1); 2533 break; 2534 } 2535 case ISD::CTLZ: { 2536 /* for now, we do this: 2537 x = x | (x >> 1); 2538 x = x | (x >> 2); 2539 ... 2540 x = x | (x >>16); 2541 x = x | (x >>32); // for 64-bit input 2542 return popcount(~x); 2543 2544 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ 2545 MVT::ValueType VT = Tmp1.getValueType(); 2546 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 2547 unsigned len = getSizeInBits(VT); 2548 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2549 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2550 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, 2551 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); 2552 } 2553 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); 2554 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 2555 break; 2556 } 2557 case ISD::CTTZ: { 2558 // for now, we use: { return popcount(~x & (x - 1)); } 2559 // unless the target has ctlz but not ctpop, in which case we use: 2560 // { return 32 - nlz(~x & (x-1)); } 2561 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2562 MVT::ValueType VT = Tmp1.getValueType(); 2563 Tmp2 = DAG.getConstant(~0ULL, VT); 2564 Tmp3 = DAG.getNode(ISD::AND, VT, 2565 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), 2566 DAG.getNode(ISD::SUB, VT, Tmp1, 2567 DAG.getConstant(1, VT))); 2568 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead 2569 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 2570 TLI.isOperationLegal(ISD::CTLZ, VT)) { 2571 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, 2572 DAG.getConstant(getSizeInBits(VT), VT), 2573 DAG.getNode(ISD::CTLZ, VT, Tmp3))); 2574 } else { 2575 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 2576 } 2577 break; 2578 } 2579 default: 2580 assert(0 && "Cannot expand this yet!"); 2581 break; 2582 } 2583 break; 2584 } 2585 break; 2586 2587 // Unary operators 2588 case ISD::FABS: 2589 case ISD::FNEG: 2590 case ISD::FSQRT: 2591 case ISD::FSIN: 2592 case ISD::FCOS: 2593 Tmp1 = LegalizeOp(Node->getOperand(0)); 2594 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2595 case TargetLowering::Legal: 2596 if (Tmp1 != Node->getOperand(0)) 2597 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2598 break; 2599 case TargetLowering::Promote: 2600 case TargetLowering::Custom: 2601 assert(0 && "Cannot promote/custom handle this yet!"); 2602 case TargetLowering::Expand: 2603 switch(Node->getOpcode()) { 2604 case ISD::FNEG: { 2605 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2606 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2607 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0), 2608 Tmp2, Tmp1)); 2609 break; 2610 } 2611 case ISD::FABS: { 2612 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2613 MVT::ValueType VT = Node->getValueType(0); 2614 Tmp2 = DAG.getConstantFP(0.0, VT); 2615 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2616 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2617 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2618 Result = LegalizeOp(Result); 2619 break; 2620 } 2621 case ISD::FSQRT: 2622 case ISD::FSIN: 2623 case ISD::FCOS: { 2624 MVT::ValueType VT = Node->getValueType(0); 2625 const char *FnName = 0; 2626 switch(Node->getOpcode()) { 2627 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 2628 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 2629 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 2630 default: assert(0 && "Unreachable!"); 2631 } 2632 SDOperand Dummy; 2633 Result = ExpandLibCall(FnName, Node, Dummy); 2634 break; 2635 } 2636 default: 2637 assert(0 && "Unreachable!"); 2638 } 2639 break; 2640 } 2641 break; 2642 2643 case ISD::BIT_CONVERT: 2644 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 2645 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2646 Result = LegalizeOp(Result); 2647 } else { 2648 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2649 Node->getOperand(0).getValueType())) { 2650 default: assert(0 && "Unknown operation action!"); 2651 case TargetLowering::Expand: 2652 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2653 Result = LegalizeOp(Result); 2654 break; 2655 case TargetLowering::Legal: 2656 Tmp1 = LegalizeOp(Node->getOperand(0)); 2657 if (Tmp1 != Node->getOperand(0)) 2658 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Tmp1); 2659 break; 2660 } 2661 } 2662 break; 2663 // Conversion operators. The source and destination have different types. 2664 case ISD::SINT_TO_FP: 2665 case ISD::UINT_TO_FP: { 2666 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2667 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2668 case Legal: 2669 switch (TLI.getOperationAction(Node->getOpcode(), 2670 Node->getOperand(0).getValueType())) { 2671 default: assert(0 && "Unknown operation action!"); 2672 case TargetLowering::Expand: 2673 Result = ExpandLegalINT_TO_FP(isSigned, 2674 LegalizeOp(Node->getOperand(0)), 2675 Node->getValueType(0)); 2676 AddLegalizedOperand(Op, Result); 2677 return Result; 2678 case TargetLowering::Promote: 2679 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2680 Node->getValueType(0), 2681 isSigned); 2682 AddLegalizedOperand(Op, Result); 2683 return Result; 2684 case TargetLowering::Legal: 2685 break; 2686 case TargetLowering::Custom: { 2687 Tmp1 = LegalizeOp(Node->getOperand(0)); 2688 SDOperand Tmp = 2689 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2690 Tmp = TLI.LowerOperation(Tmp, DAG); 2691 if (Tmp.Val) { 2692 Tmp = LegalizeOp(Tmp); // Relegalize input. 2693 AddLegalizedOperand(Op, Tmp); 2694 return Tmp; 2695 } else { 2696 assert(0 && "Target Must Lower this"); 2697 } 2698 } 2699 } 2700 2701 Tmp1 = LegalizeOp(Node->getOperand(0)); 2702 if (Tmp1 != Node->getOperand(0)) 2703 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2704 break; 2705 case Expand: 2706 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2707 Node->getValueType(0), Node->getOperand(0)); 2708 break; 2709 case Promote: 2710 if (isSigned) { 2711 Result = PromoteOp(Node->getOperand(0)); 2712 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2713 Result, DAG.getValueType(Node->getOperand(0).getValueType())); 2714 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 2715 } else { 2716 Result = PromoteOp(Node->getOperand(0)); 2717 Result = DAG.getZeroExtendInReg(Result, 2718 Node->getOperand(0).getValueType()); 2719 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 2720 } 2721 break; 2722 } 2723 break; 2724 } 2725 case ISD::TRUNCATE: 2726 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2727 case Legal: 2728 Tmp1 = LegalizeOp(Node->getOperand(0)); 2729 if (Tmp1 != Node->getOperand(0)) 2730 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2731 break; 2732 case Expand: 2733 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2734 2735 // Since the result is legal, we should just be able to truncate the low 2736 // part of the source. 2737 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2738 break; 2739 case Promote: 2740 Result = PromoteOp(Node->getOperand(0)); 2741 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2742 break; 2743 } 2744 break; 2745 2746 case ISD::FP_TO_SINT: 2747 case ISD::FP_TO_UINT: 2748 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2749 case Legal: 2750 Tmp1 = LegalizeOp(Node->getOperand(0)); 2751 2752 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2753 default: assert(0 && "Unknown operation action!"); 2754 case TargetLowering::Expand: 2755 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2756 SDOperand True, False; 2757 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2758 MVT::ValueType NVT = Node->getValueType(0); 2759 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2760 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2761 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2762 Node->getOperand(0), Tmp2, ISD::SETLT); 2763 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2764 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2765 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2766 Tmp2)); 2767 False = DAG.getNode(ISD::XOR, NVT, False, 2768 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2769 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False)); 2770 AddLegalizedOperand(SDOperand(Node, 0), Result); 2771 return Result; 2772 } else { 2773 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2774 } 2775 break; 2776 case TargetLowering::Promote: 2777 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2778 Node->getOpcode() == ISD::FP_TO_SINT); 2779 AddLegalizedOperand(Op, Result); 2780 return Result; 2781 case TargetLowering::Custom: { 2782 SDOperand Tmp = 2783 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2784 Tmp = TLI.LowerOperation(Tmp, DAG); 2785 if (Tmp.Val) { 2786 Tmp = LegalizeOp(Tmp); 2787 AddLegalizedOperand(Op, Tmp); 2788 return Tmp; 2789 } else { 2790 // The target thinks this is legal afterall. 2791 break; 2792 } 2793 } 2794 case TargetLowering::Legal: 2795 break; 2796 } 2797 2798 if (Tmp1 != Node->getOperand(0)) 2799 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2800 break; 2801 case Expand: 2802 assert(0 && "Shouldn't need to expand other operators here!"); 2803 case Promote: 2804 Result = PromoteOp(Node->getOperand(0)); 2805 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2806 break; 2807 } 2808 break; 2809 2810 case ISD::ANY_EXTEND: 2811 case ISD::ZERO_EXTEND: 2812 case ISD::SIGN_EXTEND: 2813 case ISD::FP_EXTEND: 2814 case ISD::FP_ROUND: 2815 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2816 case Legal: 2817 Tmp1 = LegalizeOp(Node->getOperand(0)); 2818 if (Tmp1 != Node->getOperand(0)) 2819 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2820 break; 2821 case Expand: 2822 assert(0 && "Shouldn't need to expand other operators here!"); 2823 2824 case Promote: 2825 switch (Node->getOpcode()) { 2826 case ISD::ANY_EXTEND: 2827 Result = PromoteOp(Node->getOperand(0)); 2828 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2829 break; 2830 case ISD::ZERO_EXTEND: 2831 Result = PromoteOp(Node->getOperand(0)); 2832 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2833 Result = DAG.getZeroExtendInReg(Result, 2834 Node->getOperand(0).getValueType()); 2835 break; 2836 case ISD::SIGN_EXTEND: 2837 Result = PromoteOp(Node->getOperand(0)); 2838 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2839 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2840 Result, 2841 DAG.getValueType(Node->getOperand(0).getValueType())); 2842 break; 2843 case ISD::FP_EXTEND: 2844 Result = PromoteOp(Node->getOperand(0)); 2845 if (Result.getValueType() != Op.getValueType()) 2846 // Dynamically dead while we have only 2 FP types. 2847 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2848 break; 2849 case ISD::FP_ROUND: 2850 Result = PromoteOp(Node->getOperand(0)); 2851 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2852 break; 2853 } 2854 } 2855 break; 2856 case ISD::FP_ROUND_INREG: 2857 case ISD::SIGN_EXTEND_INREG: { 2858 Tmp1 = LegalizeOp(Node->getOperand(0)); 2859 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2860 2861 // If this operation is not supported, convert it to a shl/shr or load/store 2862 // pair. 2863 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2864 default: assert(0 && "This action not supported for this op yet!"); 2865 case TargetLowering::Legal: 2866 if (Tmp1 != Node->getOperand(0)) 2867 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2868 DAG.getValueType(ExtraVT)); 2869 break; 2870 case TargetLowering::Expand: 2871 // If this is an integer extend and shifts are supported, do that. 2872 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2873 // NOTE: we could fall back on load/store here too for targets without 2874 // SAR. However, it is doubtful that any exist. 2875 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2876 MVT::getSizeInBits(ExtraVT); 2877 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2878 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2879 Node->getOperand(0), ShiftCst); 2880 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2881 Result, ShiftCst); 2882 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2883 // The only way we can lower this is to turn it into a STORETRUNC, 2884 // EXTLOAD pair, targetting a temporary location (a stack slot). 2885 2886 // NOTE: there is a choice here between constantly creating new stack 2887 // slots and always reusing the same one. We currently always create 2888 // new ones, as reuse may inhibit scheduling. 2889 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2890 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2891 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2892 MachineFunction &MF = DAG.getMachineFunction(); 2893 int SSFI = 2894 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2895 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2896 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2897 Node->getOperand(0), StackSlot, 2898 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2899 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2900 Result, StackSlot, DAG.getSrcValue(NULL), 2901 ExtraVT); 2902 } else { 2903 assert(0 && "Unknown op"); 2904 } 2905 Result = LegalizeOp(Result); 2906 break; 2907 } 2908 break; 2909 } 2910 } 2911 2912 // Note that LegalizeOp may be reentered even from single-use nodes, which 2913 // means that we always must cache transformed nodes. 2914 AddLegalizedOperand(Op, Result); 2915 return Result; 2916} 2917 2918/// PromoteOp - Given an operation that produces a value in an invalid type, 2919/// promote it to compute the value into a larger type. The produced value will 2920/// have the correct bits for the low portion of the register, but no guarantee 2921/// is made about the top bits: it may be zero, sign-extended, or garbage. 2922SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2923 MVT::ValueType VT = Op.getValueType(); 2924 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2925 assert(getTypeAction(VT) == Promote && 2926 "Caller should expand or legalize operands that are not promotable!"); 2927 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2928 "Cannot promote to smaller type!"); 2929 2930 SDOperand Tmp1, Tmp2, Tmp3; 2931 2932 SDOperand Result; 2933 SDNode *Node = Op.Val; 2934 2935 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2936 if (I != PromotedNodes.end()) return I->second; 2937 2938 // Promotion needs an optimization step to clean up after it, and is not 2939 // careful to avoid operations the target does not support. Make sure that 2940 // all generated operations are legalized in the next iteration. 2941 NeedsAnotherIteration = true; 2942 2943 switch (Node->getOpcode()) { 2944 case ISD::CopyFromReg: 2945 assert(0 && "CopyFromReg must be legal!"); 2946 default: 2947 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2948 assert(0 && "Do not know how to promote this operator!"); 2949 abort(); 2950 case ISD::UNDEF: 2951 Result = DAG.getNode(ISD::UNDEF, NVT); 2952 break; 2953 case ISD::Constant: 2954 if (VT != MVT::i1) 2955 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2956 else 2957 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2958 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2959 break; 2960 case ISD::ConstantFP: 2961 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2962 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2963 break; 2964 2965 case ISD::SETCC: 2966 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2967 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2968 Node->getOperand(1), Node->getOperand(2)); 2969 Result = LegalizeOp(Result); 2970 break; 2971 2972 case ISD::TRUNCATE: 2973 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2974 case Legal: 2975 Result = LegalizeOp(Node->getOperand(0)); 2976 assert(Result.getValueType() >= NVT && 2977 "This truncation doesn't make sense!"); 2978 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2979 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2980 break; 2981 case Promote: 2982 // The truncation is not required, because we don't guarantee anything 2983 // about high bits anyway. 2984 Result = PromoteOp(Node->getOperand(0)); 2985 break; 2986 case Expand: 2987 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2988 // Truncate the low part of the expanded value to the result type 2989 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2990 } 2991 break; 2992 case ISD::SIGN_EXTEND: 2993 case ISD::ZERO_EXTEND: 2994 case ISD::ANY_EXTEND: 2995 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2996 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2997 case Legal: 2998 // Input is legal? Just do extend all the way to the larger type. 2999 Result = LegalizeOp(Node->getOperand(0)); 3000 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3001 break; 3002 case Promote: 3003 // Promote the reg if it's smaller. 3004 Result = PromoteOp(Node->getOperand(0)); 3005 // The high bits are not guaranteed to be anything. Insert an extend. 3006 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3007 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3008 DAG.getValueType(Node->getOperand(0).getValueType())); 3009 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3010 Result = DAG.getZeroExtendInReg(Result, 3011 Node->getOperand(0).getValueType()); 3012 break; 3013 } 3014 break; 3015 case ISD::BIT_CONVERT: 3016 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3017 Result = PromoteOp(Result); 3018 break; 3019 3020 case ISD::FP_EXTEND: 3021 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3022 case ISD::FP_ROUND: 3023 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3024 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3025 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3026 case Legal: 3027 // Input is legal? Do an FP_ROUND_INREG. 3028 Result = LegalizeOp(Node->getOperand(0)); 3029 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3030 DAG.getValueType(VT)); 3031 break; 3032 } 3033 break; 3034 3035 case ISD::SINT_TO_FP: 3036 case ISD::UINT_TO_FP: 3037 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3038 case Legal: 3039 Result = LegalizeOp(Node->getOperand(0)); 3040 // No extra round required here. 3041 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3042 break; 3043 3044 case Promote: 3045 Result = PromoteOp(Node->getOperand(0)); 3046 if (Node->getOpcode() == ISD::SINT_TO_FP) 3047 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3048 Result, 3049 DAG.getValueType(Node->getOperand(0).getValueType())); 3050 else 3051 Result = DAG.getZeroExtendInReg(Result, 3052 Node->getOperand(0).getValueType()); 3053 // No extra round required here. 3054 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3055 break; 3056 case Expand: 3057 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3058 Node->getOperand(0)); 3059 // Round if we cannot tolerate excess precision. 3060 if (NoExcessFPPrecision) 3061 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3062 DAG.getValueType(VT)); 3063 break; 3064 } 3065 break; 3066 3067 case ISD::SIGN_EXTEND_INREG: 3068 Result = PromoteOp(Node->getOperand(0)); 3069 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3070 Node->getOperand(1)); 3071 break; 3072 case ISD::FP_TO_SINT: 3073 case ISD::FP_TO_UINT: 3074 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3075 case Legal: 3076 Tmp1 = LegalizeOp(Node->getOperand(0)); 3077 break; 3078 case Promote: 3079 // The input result is prerounded, so we don't have to do anything 3080 // special. 3081 Tmp1 = PromoteOp(Node->getOperand(0)); 3082 break; 3083 case Expand: 3084 assert(0 && "not implemented"); 3085 } 3086 // If we're promoting a UINT to a larger size, check to see if the new node 3087 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3088 // we can use that instead. This allows us to generate better code for 3089 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3090 // legal, such as PowerPC. 3091 if (Node->getOpcode() == ISD::FP_TO_UINT && 3092 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3093 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3094 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3095 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3096 } else { 3097 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3098 } 3099 break; 3100 3101 case ISD::FABS: 3102 case ISD::FNEG: 3103 Tmp1 = PromoteOp(Node->getOperand(0)); 3104 assert(Tmp1.getValueType() == NVT); 3105 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3106 // NOTE: we do not have to do any extra rounding here for 3107 // NoExcessFPPrecision, because we know the input will have the appropriate 3108 // precision, and these operations don't modify precision at all. 3109 break; 3110 3111 case ISD::FSQRT: 3112 case ISD::FSIN: 3113 case ISD::FCOS: 3114 Tmp1 = PromoteOp(Node->getOperand(0)); 3115 assert(Tmp1.getValueType() == NVT); 3116 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3117 if(NoExcessFPPrecision) 3118 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3119 DAG.getValueType(VT)); 3120 break; 3121 3122 case ISD::AND: 3123 case ISD::OR: 3124 case ISD::XOR: 3125 case ISD::ADD: 3126 case ISD::SUB: 3127 case ISD::MUL: 3128 // The input may have strange things in the top bits of the registers, but 3129 // these operations don't care. They may have weird bits going out, but 3130 // that too is okay if they are integer operations. 3131 Tmp1 = PromoteOp(Node->getOperand(0)); 3132 Tmp2 = PromoteOp(Node->getOperand(1)); 3133 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3134 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3135 break; 3136 case ISD::FADD: 3137 case ISD::FSUB: 3138 case ISD::FMUL: 3139 // The input may have strange things in the top bits of the registers, but 3140 // these operations don't care. 3141 Tmp1 = PromoteOp(Node->getOperand(0)); 3142 Tmp2 = PromoteOp(Node->getOperand(1)); 3143 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3144 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3145 3146 // Floating point operations will give excess precision that we may not be 3147 // able to tolerate. If we DO allow excess precision, just leave it, 3148 // otherwise excise it. 3149 // FIXME: Why would we need to round FP ops more than integer ones? 3150 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3151 if (NoExcessFPPrecision) 3152 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3153 DAG.getValueType(VT)); 3154 break; 3155 3156 case ISD::SDIV: 3157 case ISD::SREM: 3158 // These operators require that their input be sign extended. 3159 Tmp1 = PromoteOp(Node->getOperand(0)); 3160 Tmp2 = PromoteOp(Node->getOperand(1)); 3161 if (MVT::isInteger(NVT)) { 3162 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3163 DAG.getValueType(VT)); 3164 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3165 DAG.getValueType(VT)); 3166 } 3167 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3168 3169 // Perform FP_ROUND: this is probably overly pessimistic. 3170 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3171 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3172 DAG.getValueType(VT)); 3173 break; 3174 case ISD::FDIV: 3175 case ISD::FREM: 3176 // These operators require that their input be fp extended. 3177 Tmp1 = PromoteOp(Node->getOperand(0)); 3178 Tmp2 = PromoteOp(Node->getOperand(1)); 3179 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3180 3181 // Perform FP_ROUND: this is probably overly pessimistic. 3182 if (NoExcessFPPrecision) 3183 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3184 DAG.getValueType(VT)); 3185 break; 3186 3187 case ISD::UDIV: 3188 case ISD::UREM: 3189 // These operators require that their input be zero extended. 3190 Tmp1 = PromoteOp(Node->getOperand(0)); 3191 Tmp2 = PromoteOp(Node->getOperand(1)); 3192 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3193 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3194 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3195 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3196 break; 3197 3198 case ISD::SHL: 3199 Tmp1 = PromoteOp(Node->getOperand(0)); 3200 Tmp2 = LegalizeOp(Node->getOperand(1)); 3201 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 3202 break; 3203 case ISD::SRA: 3204 // The input value must be properly sign extended. 3205 Tmp1 = PromoteOp(Node->getOperand(0)); 3206 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3207 DAG.getValueType(VT)); 3208 Tmp2 = LegalizeOp(Node->getOperand(1)); 3209 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 3210 break; 3211 case ISD::SRL: 3212 // The input value must be properly zero extended. 3213 Tmp1 = PromoteOp(Node->getOperand(0)); 3214 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3215 Tmp2 = LegalizeOp(Node->getOperand(1)); 3216 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 3217 break; 3218 3219 case ISD::LOAD: 3220 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3221 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3222 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2, 3223 Node->getOperand(2), VT); 3224 // Remember that we legalized the chain. 3225 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 3226 break; 3227 case ISD::SEXTLOAD: 3228 case ISD::ZEXTLOAD: 3229 case ISD::EXTLOAD: 3230 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3231 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3232 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2, 3233 Node->getOperand(2), 3234 cast<VTSDNode>(Node->getOperand(3))->getVT()); 3235 // Remember that we legalized the chain. 3236 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 3237 break; 3238 case ISD::SELECT: 3239 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3240 case Expand: assert(0 && "It's impossible to expand bools"); 3241 case Legal: 3242 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 3243 break; 3244 case Promote: 3245 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 3246 break; 3247 } 3248 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 3249 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 3250 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 3251 break; 3252 case ISD::SELECT_CC: 3253 Tmp2 = PromoteOp(Node->getOperand(2)); // True 3254 Tmp3 = PromoteOp(Node->getOperand(3)); // False 3255 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3256 Node->getOperand(1), Tmp2, Tmp3, 3257 Node->getOperand(4)); 3258 break; 3259 case ISD::TAILCALL: 3260 case ISD::CALL: { 3261 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3262 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 3263 3264 std::vector<SDOperand> Ops; 3265 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 3266 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3267 3268 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 3269 "Can only promote single result calls"); 3270 std::vector<MVT::ValueType> RetTyVTs; 3271 RetTyVTs.reserve(2); 3272 RetTyVTs.push_back(NVT); 3273 RetTyVTs.push_back(MVT::Other); 3274 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 3275 Node->getOpcode() == ISD::TAILCALL); 3276 Result = SDOperand(NC, 0); 3277 3278 // Insert the new chain mapping. 3279 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 3280 break; 3281 } 3282 case ISD::BSWAP: 3283 Tmp1 = Node->getOperand(0); 3284 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3285 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3286 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3287 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), 3288 TLI.getShiftAmountTy())); 3289 break; 3290 case ISD::CTPOP: 3291 case ISD::CTTZ: 3292 case ISD::CTLZ: 3293 Tmp1 = Node->getOperand(0); 3294 //Zero extend the argument 3295 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3296 // Perform the larger operation, then subtract if needed. 3297 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3298 switch(Node->getOpcode()) 3299 { 3300 case ISD::CTPOP: 3301 Result = Tmp1; 3302 break; 3303 case ISD::CTTZ: 3304 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3305 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3306 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 3307 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3308 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 3309 break; 3310 case ISD::CTLZ: 3311 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3312 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3313 DAG.getConstant(getSizeInBits(NVT) - 3314 getSizeInBits(VT), NVT)); 3315 break; 3316 } 3317 break; 3318 } 3319 3320 assert(Result.Val && "Didn't set a result!"); 3321 AddPromotedOperand(Op, Result); 3322 return Result; 3323} 3324 3325/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 3326/// The resultant code need not be legal. Note that SrcOp is the input operand 3327/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 3328SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 3329 SDOperand SrcOp) { 3330 // Create the stack frame object. 3331 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 3332 unsigned ByteSize = MVT::getSizeInBits(DestVT)/8; 3333 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize); 3334 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 3335 3336 // Emit a store to the stack slot. 3337 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3338 SrcOp, FIPtr, DAG.getSrcValue(NULL)); 3339 // Result is a load from the stack slot. 3340 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0)); 3341} 3342 3343/// ExpandAddSub - Find a clever way to expand this add operation into 3344/// subcomponents. 3345void SelectionDAGLegalize:: 3346ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 3347 SDOperand &Lo, SDOperand &Hi) { 3348 // Expand the subcomponents. 3349 SDOperand LHSL, LHSH, RHSL, RHSH; 3350 ExpandOp(LHS, LHSL, LHSH); 3351 ExpandOp(RHS, RHSL, RHSH); 3352 3353 std::vector<SDOperand> Ops; 3354 Ops.push_back(LHSL); 3355 Ops.push_back(LHSH); 3356 Ops.push_back(RHSL); 3357 Ops.push_back(RHSH); 3358 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 3359 Lo = DAG.getNode(NodeOp, VTs, Ops); 3360 Hi = Lo.getValue(1); 3361} 3362 3363void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 3364 SDOperand Op, SDOperand Amt, 3365 SDOperand &Lo, SDOperand &Hi) { 3366 // Expand the subcomponents. 3367 SDOperand LHSL, LHSH; 3368 ExpandOp(Op, LHSL, LHSH); 3369 3370 std::vector<SDOperand> Ops; 3371 Ops.push_back(LHSL); 3372 Ops.push_back(LHSH); 3373 Ops.push_back(Amt); 3374 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 3375 Lo = DAG.getNode(NodeOp, VTs, Ops); 3376 Hi = Lo.getValue(1); 3377} 3378 3379 3380/// ExpandShift - Try to find a clever way to expand this shift operation out to 3381/// smaller elements. If we can't find a way that is more efficient than a 3382/// libcall on this target, return false. Otherwise, return true with the 3383/// low-parts expanded into Lo and Hi. 3384bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 3385 SDOperand &Lo, SDOperand &Hi) { 3386 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 3387 "This is not a shift!"); 3388 3389 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 3390 SDOperand ShAmt = LegalizeOp(Amt); 3391 MVT::ValueType ShTy = ShAmt.getValueType(); 3392 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 3393 unsigned NVTBits = MVT::getSizeInBits(NVT); 3394 3395 // Handle the case when Amt is an immediate. Other cases are currently broken 3396 // and are disabled. 3397 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 3398 unsigned Cst = CN->getValue(); 3399 // Expand the incoming operand to be shifted, so that we have its parts 3400 SDOperand InL, InH; 3401 ExpandOp(Op, InL, InH); 3402 switch(Opc) { 3403 case ISD::SHL: 3404 if (Cst > VTBits) { 3405 Lo = DAG.getConstant(0, NVT); 3406 Hi = DAG.getConstant(0, NVT); 3407 } else if (Cst > NVTBits) { 3408 Lo = DAG.getConstant(0, NVT); 3409 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 3410 } else if (Cst == NVTBits) { 3411 Lo = DAG.getConstant(0, NVT); 3412 Hi = InL; 3413 } else { 3414 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 3415 Hi = DAG.getNode(ISD::OR, NVT, 3416 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 3417 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 3418 } 3419 return true; 3420 case ISD::SRL: 3421 if (Cst > VTBits) { 3422 Lo = DAG.getConstant(0, NVT); 3423 Hi = DAG.getConstant(0, NVT); 3424 } else if (Cst > NVTBits) { 3425 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 3426 Hi = DAG.getConstant(0, NVT); 3427 } else if (Cst == NVTBits) { 3428 Lo = InH; 3429 Hi = DAG.getConstant(0, NVT); 3430 } else { 3431 Lo = DAG.getNode(ISD::OR, NVT, 3432 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3433 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3434 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 3435 } 3436 return true; 3437 case ISD::SRA: 3438 if (Cst > VTBits) { 3439 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 3440 DAG.getConstant(NVTBits-1, ShTy)); 3441 } else if (Cst > NVTBits) { 3442 Lo = DAG.getNode(ISD::SRA, NVT, InH, 3443 DAG.getConstant(Cst-NVTBits, ShTy)); 3444 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3445 DAG.getConstant(NVTBits-1, ShTy)); 3446 } else if (Cst == NVTBits) { 3447 Lo = InH; 3448 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3449 DAG.getConstant(NVTBits-1, ShTy)); 3450 } else { 3451 Lo = DAG.getNode(ISD::OR, NVT, 3452 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3453 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3454 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 3455 } 3456 return true; 3457 } 3458 } 3459 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 3460 // so disable it for now. Currently targets are handling this via SHL_PARTS 3461 // and friends. 3462 return false; 3463 3464 // If we have an efficient select operation (or if the selects will all fold 3465 // away), lower to some complex code, otherwise just emit the libcall. 3466 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt)) 3467 return false; 3468 3469 SDOperand InL, InH; 3470 ExpandOp(Op, InL, InH); 3471 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 3472 DAG.getConstant(NVTBits, ShTy), ShAmt); 3473 3474 // Compare the unmasked shift amount against 32. 3475 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt, 3476 DAG.getConstant(NVTBits, ShTy), ISD::SETGE); 3477 3478 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 3479 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 3480 DAG.getConstant(NVTBits-1, ShTy)); 3481 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 3482 DAG.getConstant(NVTBits-1, ShTy)); 3483 } 3484 3485 if (Opc == ISD::SHL) { 3486 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 3487 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 3488 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 3489 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 3490 3491 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 3492 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 3493 } else { 3494 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 3495 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt, 3496 DAG.getConstant(32, ShTy), 3497 ISD::SETEQ), 3498 DAG.getConstant(0, NVT), 3499 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 3500 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 3501 HiLoPart, 3502 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 3503 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 3504 3505 SDOperand HiPart; 3506 if (Opc == ISD::SRA) 3507 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 3508 DAG.getConstant(NVTBits-1, ShTy)); 3509 else 3510 HiPart = DAG.getConstant(0, NVT); 3511 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 3512 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 3513 } 3514 return true; 3515} 3516 3517/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 3518/// NodeDepth) node that is an CallSeqStart operation and occurs later than 3519/// Found. 3520static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found, 3521 std::set<SDNode*> &Visited) { 3522 if (Node->getNodeDepth() <= Found->getNodeDepth() || 3523 !Visited.insert(Node).second) return; 3524 3525 // If we found an CALLSEQ_START, we already know this node occurs later 3526 // than the Found node. Just remember this node and return. 3527 if (Node->getOpcode() == ISD::CALLSEQ_START) { 3528 Found = Node; 3529 return; 3530 } 3531 3532 // Otherwise, scan the operands of Node to see if any of them is a call. 3533 assert(Node->getNumOperands() != 0 && 3534 "All leaves should have depth equal to the entry node!"); 3535 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 3536 FindLatestCallSeqStart(Node->getOperand(i).Val, Found, Visited); 3537 3538 // Tail recurse for the last iteration. 3539 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 3540 Found, Visited); 3541} 3542 3543 3544/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 3545/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 3546/// than Found. 3547static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 3548 std::set<SDNode*> &Visited) { 3549 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 3550 !Visited.insert(Node).second) return; 3551 3552 // If we found an CALLSEQ_END, we already know this node occurs earlier 3553 // than the Found node. Just remember this node and return. 3554 if (Node->getOpcode() == ISD::CALLSEQ_END) { 3555 Found = Node; 3556 return; 3557 } 3558 3559 // Otherwise, scan the operands of Node to see if any of them is a call. 3560 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 3561 if (UI == E) return; 3562 for (--E; UI != E; ++UI) 3563 FindEarliestCallSeqEnd(*UI, Found, Visited); 3564 3565 // Tail recurse for the last iteration. 3566 FindEarliestCallSeqEnd(*UI, Found, Visited); 3567} 3568 3569/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 3570/// find the CALLSEQ_END node that terminates the call sequence. 3571static SDNode *FindCallSeqEnd(SDNode *Node) { 3572 if (Node->getOpcode() == ISD::CALLSEQ_END) 3573 return Node; 3574 if (Node->use_empty()) 3575 return 0; // No CallSeqEnd 3576 3577 // The chain is usually at the end. 3578 SDOperand TheChain(Node, Node->getNumValues()-1); 3579 if (TheChain.getValueType() != MVT::Other) { 3580 // Sometimes it's at the beginning. 3581 TheChain = SDOperand(Node, 0); 3582 if (TheChain.getValueType() != MVT::Other) { 3583 // Otherwise, hunt for it. 3584 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 3585 if (Node->getValueType(i) == MVT::Other) { 3586 TheChain = SDOperand(Node, i); 3587 break; 3588 } 3589 3590 // Otherwise, we walked into a node without a chain. 3591 if (TheChain.getValueType() != MVT::Other) 3592 return 0; 3593 } 3594 } 3595 3596 for (SDNode::use_iterator UI = Node->use_begin(), 3597 E = Node->use_end(); UI != E; ++UI) { 3598 3599 // Make sure to only follow users of our token chain. 3600 SDNode *User = *UI; 3601 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 3602 if (User->getOperand(i) == TheChain) 3603 if (SDNode *Result = FindCallSeqEnd(User)) 3604 return Result; 3605 } 3606 return 0; 3607} 3608 3609/// FindCallSeqStart - Given a chained node that is part of a call sequence, 3610/// find the CALLSEQ_START node that initiates the call sequence. 3611static SDNode *FindCallSeqStart(SDNode *Node) { 3612 assert(Node && "Didn't find callseq_start for a call??"); 3613 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 3614 3615 assert(Node->getOperand(0).getValueType() == MVT::Other && 3616 "Node doesn't have a token chain argument!"); 3617 return FindCallSeqStart(Node->getOperand(0).Val); 3618} 3619 3620 3621/// FindInputOutputChains - If we are replacing an operation with a call we need 3622/// to find the call that occurs before and the call that occurs after it to 3623/// properly serialize the calls in the block. The returned operand is the 3624/// input chain value for the new call (e.g. the entry node or the previous 3625/// call), and OutChain is set to be the chain node to update to point to the 3626/// end of the call chain. 3627static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 3628 SDOperand Entry) { 3629 SDNode *LatestCallSeqStart = Entry.Val; 3630 SDNode *LatestCallSeqEnd = 0; 3631 std::set<SDNode*> Visited; 3632 FindLatestCallSeqStart(OpNode, LatestCallSeqStart, Visited); 3633 Visited.clear(); 3634 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 3635 3636 // It is possible that no ISD::CALLSEQ_START was found because there is no 3637 // previous call in the function. LatestCallStackDown may in that case be 3638 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 3639 // unless LatestCallStackDown is an CALLSEQ_START. 3640 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 3641 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 3642 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 3643 } else { 3644 LatestCallSeqEnd = Entry.Val; 3645 } 3646 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 3647 3648 // Finally, find the first call that this must come before, first we find the 3649 // CallSeqEnd that ends the call. 3650 OutChain = 0; 3651 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 3652 Visited.clear(); 3653 3654 // If we found one, translate from the adj up to the callseq_start. 3655 if (OutChain) 3656 OutChain = FindCallSeqStart(OutChain); 3657 3658 return SDOperand(LatestCallSeqEnd, 0); 3659} 3660 3661/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 3662void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 3663 SDNode *OutChain) { 3664 // Nothing to splice it into? 3665 if (OutChain == 0) return; 3666 3667 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 3668 //OutChain->dump(); 3669 3670 // Form a token factor node merging the old inval and the new inval. 3671 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 3672 OutChain->getOperand(0)); 3673 // Change the node to refer to the new token. 3674 OutChain->setAdjCallChain(InToken); 3675} 3676 3677 3678// ExpandLibCall - Expand a node into a call to a libcall. If the result value 3679// does not fit into a register, return the lo part and set the hi part to the 3680// by-reg argument. If it does fit into a single register, return the result 3681// and leave the Hi part unset. 3682SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 3683 SDOperand &Hi) { 3684 SDNode *OutChain; 3685 SDOperand InChain = FindInputOutputChains(Node, OutChain, 3686 DAG.getEntryNode()); 3687 if (InChain.Val == 0) 3688 InChain = DAG.getEntryNode(); 3689 3690 TargetLowering::ArgListTy Args; 3691 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3692 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 3693 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 3694 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 3695 } 3696 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 3697 3698 // Splice the libcall in wherever FindInputOutputChains tells us to. 3699 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 3700 std::pair<SDOperand,SDOperand> CallInfo = 3701 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 3702 Callee, Args, DAG); 3703 3704 SDOperand Result; 3705 switch (getTypeAction(CallInfo.first.getValueType())) { 3706 default: assert(0 && "Unknown thing"); 3707 case Legal: 3708 Result = CallInfo.first; 3709 break; 3710 case Promote: 3711 assert(0 && "Cannot promote this yet!"); 3712 case Expand: 3713 ExpandOp(CallInfo.first, Result, Hi); 3714 CallInfo.second = LegalizeOp(CallInfo.second); 3715 break; 3716 } 3717 3718 SpliceCallInto(CallInfo.second, OutChain); 3719 NeedsAnotherIteration = true; 3720 return Result; 3721} 3722 3723 3724/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 3725/// destination type is legal. 3726SDOperand SelectionDAGLegalize:: 3727ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 3728 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 3729 assert(getTypeAction(Source.getValueType()) == Expand && 3730 "This is not an expansion!"); 3731 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 3732 3733 if (!isSigned) { 3734 assert(Source.getValueType() == MVT::i64 && 3735 "This only works for 64-bit -> FP"); 3736 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 3737 // incoming integer is set. To handle this, we dynamically test to see if 3738 // it is set, and, if so, add a fudge factor. 3739 SDOperand Lo, Hi; 3740 ExpandOp(Source, Lo, Hi); 3741 3742 // If this is unsigned, and not supported, first perform the conversion to 3743 // signed, then adjust the result if the sign bit is set. 3744 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 3745 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 3746 3747 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 3748 DAG.getConstant(0, Hi.getValueType()), 3749 ISD::SETLT); 3750 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3751 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3752 SignSet, Four, Zero); 3753 uint64_t FF = 0x5f800000ULL; 3754 if (TLI.isLittleEndian()) FF <<= 32; 3755 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3756 3757 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3758 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3759 SDOperand FudgeInReg; 3760 if (DestTy == MVT::f32) 3761 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3762 DAG.getSrcValue(NULL)); 3763 else { 3764 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3765 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3766 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 3767 } 3768 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3769 } 3770 3771 // Check to see if the target has a custom way to lower this. If so, use it. 3772 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3773 default: assert(0 && "This action not implemented for this operation!"); 3774 case TargetLowering::Legal: 3775 case TargetLowering::Expand: 3776 break; // This case is handled below. 3777 case TargetLowering::Custom: { 3778 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3779 Source), DAG); 3780 if (NV.Val) 3781 return LegalizeOp(NV); 3782 break; // The target decided this was legal after all 3783 } 3784 } 3785 3786 // Expand the source, then glue it back together for the call. We must expand 3787 // the source in case it is shared (this pass of legalize must traverse it). 3788 SDOperand SrcLo, SrcHi; 3789 ExpandOp(Source, SrcLo, SrcHi); 3790 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3791 3792 SDNode *OutChain = 0; 3793 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 3794 DAG.getEntryNode()); 3795 const char *FnName = 0; 3796 if (DestTy == MVT::f32) 3797 FnName = "__floatdisf"; 3798 else { 3799 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3800 FnName = "__floatdidf"; 3801 } 3802 3803 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 3804 3805 TargetLowering::ArgListTy Args; 3806 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 3807 3808 Args.push_back(std::make_pair(Source, ArgTy)); 3809 3810 // We don't care about token chains for libcalls. We just use the entry 3811 // node as our input and ignore the output chain. This allows us to place 3812 // calls wherever we need them to satisfy data dependences. 3813 const Type *RetTy = MVT::getTypeForValueType(DestTy); 3814 3815 std::pair<SDOperand,SDOperand> CallResult = 3816 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 3817 Callee, Args, DAG); 3818 3819 SpliceCallInto(CallResult.second, OutChain); 3820 return CallResult.first; 3821} 3822 3823 3824 3825/// ExpandOp - Expand the specified SDOperand into its two component pieces 3826/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 3827/// LegalizeNodes map is filled in for any results that are not expanded, the 3828/// ExpandedNodes map is filled in for any results that are expanded, and the 3829/// Lo/Hi values are returned. 3830void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 3831 MVT::ValueType VT = Op.getValueType(); 3832 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3833 SDNode *Node = Op.Val; 3834 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 3835 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 3836 "Cannot expand FP values!"); 3837 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 3838 "Cannot expand to FP value or to larger int value!"); 3839 3840 // See if we already expanded it. 3841 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 3842 = ExpandedNodes.find(Op); 3843 if (I != ExpandedNodes.end()) { 3844 Lo = I->second.first; 3845 Hi = I->second.second; 3846 return; 3847 } 3848 3849 // Expanding to multiple registers needs to perform an optimization step, and 3850 // is not careful to avoid operations the target does not support. Make sure 3851 // that all generated operations are legalized in the next iteration. 3852 NeedsAnotherIteration = true; 3853 3854 switch (Node->getOpcode()) { 3855 case ISD::CopyFromReg: 3856 assert(0 && "CopyFromReg must be legal!"); 3857 default: 3858 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 3859 assert(0 && "Do not know how to expand this operator!"); 3860 abort(); 3861 case ISD::UNDEF: 3862 Lo = DAG.getNode(ISD::UNDEF, NVT); 3863 Hi = DAG.getNode(ISD::UNDEF, NVT); 3864 break; 3865 case ISD::Constant: { 3866 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 3867 Lo = DAG.getConstant(Cst, NVT); 3868 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3869 break; 3870 } 3871 case ISD::ConstantVec: { 3872 unsigned NumElements = Node->getNumOperands(); 3873 // If we only have two elements left in the constant vector, just break it 3874 // apart into the two scalar constants it contains. Otherwise, bisect the 3875 // ConstantVec, and return each half as a new ConstantVec. 3876 // FIXME: this is hard coded as big endian, it may have to change to support 3877 // SSE and Alpha MVI 3878 if (NumElements == 2) { 3879 Hi = Node->getOperand(0); 3880 Lo = Node->getOperand(1); 3881 } else { 3882 NumElements /= 2; 3883 std::vector<SDOperand> LoOps, HiOps; 3884 for (unsigned I = 0, E = NumElements; I < E; ++I) { 3885 HiOps.push_back(Node->getOperand(I)); 3886 LoOps.push_back(Node->getOperand(I+NumElements)); 3887 } 3888 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps); 3889 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps); 3890 } 3891 break; 3892 } 3893 3894 case ISD::BUILD_PAIR: 3895 // Legalize both operands. FIXME: in the future we should handle the case 3896 // where the two elements are not legal. 3897 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 3898 Lo = LegalizeOp(Node->getOperand(0)); 3899 Hi = LegalizeOp(Node->getOperand(1)); 3900 break; 3901 3902 case ISD::SIGN_EXTEND_INREG: 3903 ExpandOp(Node->getOperand(0), Lo, Hi); 3904 // Sign extend the lo-part. 3905 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 3906 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 3907 TLI.getShiftAmountTy())); 3908 // sext_inreg the low part if needed. 3909 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 3910 break; 3911 3912 case ISD::BSWAP: { 3913 ExpandOp(Node->getOperand(0), Lo, Hi); 3914 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 3915 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 3916 Lo = TempLo; 3917 break; 3918 } 3919 3920 case ISD::CTPOP: 3921 ExpandOp(Node->getOperand(0), Lo, Hi); 3922 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3923 DAG.getNode(ISD::CTPOP, NVT, Lo), 3924 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3925 Hi = DAG.getConstant(0, NVT); 3926 break; 3927 3928 case ISD::CTLZ: { 3929 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3930 ExpandOp(Node->getOperand(0), Lo, Hi); 3931 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3932 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3933 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3934 ISD::SETNE); 3935 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3936 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3937 3938 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3939 Hi = DAG.getConstant(0, NVT); 3940 break; 3941 } 3942 3943 case ISD::CTTZ: { 3944 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3945 ExpandOp(Node->getOperand(0), Lo, Hi); 3946 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3947 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3948 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3949 ISD::SETNE); 3950 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3951 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3952 3953 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3954 Hi = DAG.getConstant(0, NVT); 3955 break; 3956 } 3957 3958 case ISD::VAARG: { 3959 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3960 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3961 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 3962 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 3963 3964 // Remember that we legalized the chain. 3965 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 3966 if (!TLI.isLittleEndian()) 3967 std::swap(Lo, Hi); 3968 break; 3969 } 3970 3971 case ISD::LOAD: { 3972 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3973 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3974 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3975 3976 // Increment the pointer to the other half. 3977 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3978 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3979 getIntPtrConstant(IncrementSize)); 3980 //Is this safe? declaring that the two parts of the split load 3981 //are from the same instruction? 3982 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3983 3984 // Build a factor node to remember that this load is independent of the 3985 // other one. 3986 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3987 Hi.getValue(1)); 3988 3989 // Remember that we legalized the chain. 3990 AddLegalizedOperand(Op.getValue(1), TF); 3991 if (!TLI.isLittleEndian()) 3992 std::swap(Lo, Hi); 3993 break; 3994 } 3995 case ISD::VLOAD: { 3996 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3997 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3998 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3999 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4000 4001 // If we only have two elements, turn into a pair of scalar loads. 4002 // FIXME: handle case where a vector of two elements is fine, such as 4003 // 2 x double on SSE2. 4004 if (NumElements == 2) { 4005 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 4006 // Increment the pointer to the other half. 4007 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8; 4008 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4009 getIntPtrConstant(IncrementSize)); 4010 //Is this safe? declaring that the two parts of the split load 4011 //are from the same instruction? 4012 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 4013 } else { 4014 NumElements /= 2; // Split the vector in half 4015 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 4016 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8; 4017 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4018 getIntPtrConstant(IncrementSize)); 4019 //Is this safe? declaring that the two parts of the split load 4020 //are from the same instruction? 4021 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 4022 } 4023 4024 // Build a factor node to remember that this load is independent of the 4025 // other one. 4026 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 4027 Hi.getValue(1)); 4028 4029 // Remember that we legalized the chain. 4030 AddLegalizedOperand(Op.getValue(1), TF); 4031 if (!TLI.isLittleEndian()) 4032 std::swap(Lo, Hi); 4033 break; 4034 } 4035 case ISD::VADD: 4036 case ISD::VSUB: 4037 case ISD::VMUL: { 4038 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 4039 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4040 SDOperand LL, LH, RL, RH; 4041 4042 ExpandOp(Node->getOperand(0), LL, LH); 4043 ExpandOp(Node->getOperand(1), RL, RH); 4044 4045 // If we only have two elements, turn into a pair of scalar loads. 4046 // FIXME: handle case where a vector of two elements is fine, such as 4047 // 2 x double on SSE2. 4048 if (NumElements == 2) { 4049 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT); 4050 Lo = DAG.getNode(Opc, EVT, LL, RL); 4051 Hi = DAG.getNode(Opc, EVT, LH, RH); 4052 } else { 4053 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2), 4054 LL.getOperand(3)); 4055 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2), 4056 LH.getOperand(3)); 4057 } 4058 break; 4059 } 4060 case ISD::TAILCALL: 4061 case ISD::CALL: { 4062 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 4063 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 4064 4065 bool Changed = false; 4066 std::vector<SDOperand> Ops; 4067 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 4068 Ops.push_back(LegalizeOp(Node->getOperand(i))); 4069 Changed |= Ops.back() != Node->getOperand(i); 4070 } 4071 4072 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 4073 "Can only expand a call once so far, not i64 -> i16!"); 4074 4075 std::vector<MVT::ValueType> RetTyVTs; 4076 RetTyVTs.reserve(3); 4077 RetTyVTs.push_back(NVT); 4078 RetTyVTs.push_back(NVT); 4079 RetTyVTs.push_back(MVT::Other); 4080 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops, 4081 Node->getOpcode() == ISD::TAILCALL); 4082 Lo = SDOperand(NC, 0); 4083 Hi = SDOperand(NC, 1); 4084 4085 // Insert the new chain mapping. 4086 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 4087 break; 4088 } 4089 case ISD::AND: 4090 case ISD::OR: 4091 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 4092 SDOperand LL, LH, RL, RH; 4093 ExpandOp(Node->getOperand(0), LL, LH); 4094 ExpandOp(Node->getOperand(1), RL, RH); 4095 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 4096 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 4097 break; 4098 } 4099 case ISD::SELECT: { 4100 SDOperand C, LL, LH, RL, RH; 4101 4102 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4103 case Expand: assert(0 && "It's impossible to expand bools"); 4104 case Legal: 4105 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 4106 break; 4107 case Promote: 4108 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 4109 break; 4110 } 4111 ExpandOp(Node->getOperand(1), LL, LH); 4112 ExpandOp(Node->getOperand(2), RL, RH); 4113 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 4114 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 4115 break; 4116 } 4117 case ISD::SELECT_CC: { 4118 SDOperand TL, TH, FL, FH; 4119 ExpandOp(Node->getOperand(2), TL, TH); 4120 ExpandOp(Node->getOperand(3), FL, FH); 4121 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4122 Node->getOperand(1), TL, FL, Node->getOperand(4)); 4123 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4124 Node->getOperand(1), TH, FH, Node->getOperand(4)); 4125 Lo = LegalizeOp(Lo); 4126 Hi = LegalizeOp(Hi); 4127 break; 4128 } 4129 case ISD::SEXTLOAD: { 4130 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 4131 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 4132 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4133 4134 if (EVT == NVT) 4135 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 4136 else 4137 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 4138 EVT); 4139 4140 // Remember that we legalized the chain. 4141 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 4142 4143 // The high part is obtained by SRA'ing all but one of the bits of the lo 4144 // part. 4145 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4146 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 4147 TLI.getShiftAmountTy())); 4148 Lo = LegalizeOp(Lo); 4149 Hi = LegalizeOp(Hi); 4150 break; 4151 } 4152 case ISD::ZEXTLOAD: { 4153 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 4154 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 4155 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4156 4157 if (EVT == NVT) 4158 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 4159 else 4160 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 4161 EVT); 4162 4163 // Remember that we legalized the chain. 4164 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 4165 4166 // The high part is just a zero. 4167 Hi = LegalizeOp(DAG.getConstant(0, NVT)); 4168 Lo = LegalizeOp(Lo); 4169 break; 4170 } 4171 case ISD::EXTLOAD: { 4172 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 4173 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 4174 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4175 4176 if (EVT == NVT) 4177 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 4178 else 4179 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 4180 EVT); 4181 4182 // Remember that we legalized the chain. 4183 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 4184 4185 // The high part is undefined. 4186 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT)); 4187 Lo = LegalizeOp(Lo); 4188 break; 4189 } 4190 case ISD::ANY_EXTEND: { 4191 SDOperand In; 4192 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4193 case Expand: assert(0 && "expand-expand not implemented yet!"); 4194 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 4195 case Promote: 4196 In = PromoteOp(Node->getOperand(0)); 4197 break; 4198 } 4199 4200 // The low part is any extension of the input (which degenerates to a copy). 4201 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In); 4202 // The high part is undefined. 4203 Hi = DAG.getNode(ISD::UNDEF, NVT); 4204 break; 4205 } 4206 case ISD::SIGN_EXTEND: { 4207 SDOperand In; 4208 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4209 case Expand: assert(0 && "expand-expand not implemented yet!"); 4210 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 4211 case Promote: 4212 In = PromoteOp(Node->getOperand(0)); 4213 // Emit the appropriate sign_extend_inreg to get the value we want. 4214 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 4215 DAG.getValueType(Node->getOperand(0).getValueType())); 4216 break; 4217 } 4218 4219 // The low part is just a sign extension of the input (which degenerates to 4220 // a copy). 4221 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 4222 4223 // The high part is obtained by SRA'ing all but one of the bits of the lo 4224 // part. 4225 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4226 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 4227 TLI.getShiftAmountTy())); 4228 break; 4229 } 4230 case ISD::ZERO_EXTEND: { 4231 SDOperand In; 4232 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4233 case Expand: assert(0 && "expand-expand not implemented yet!"); 4234 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 4235 case Promote: 4236 In = PromoteOp(Node->getOperand(0)); 4237 // Emit the appropriate zero_extend_inreg to get the value we want. 4238 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 4239 break; 4240 } 4241 4242 // The low part is just a zero extension of the input (which degenerates to 4243 // a copy). 4244 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 4245 4246 // The high part is just a zero. 4247 Hi = DAG.getConstant(0, NVT); 4248 break; 4249 } 4250 4251 case ISD::BIT_CONVERT: { 4252 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0), 4253 Node->getOperand(0)); 4254 ExpandOp(Tmp, Lo, Hi); 4255 break; 4256 } 4257 4258 case ISD::READCYCLECOUNTER: { 4259 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 4260 TargetLowering::Custom && 4261 "Must custom expand ReadCycleCounter"); 4262 SDOperand T = TLI.LowerOperation(Op, DAG); 4263 assert(T.Val && "Node must be custom expanded!"); 4264 Lo = LegalizeOp(T.getValue(0)); 4265 Hi = LegalizeOp(T.getValue(1)); 4266 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 4267 LegalizeOp(T.getValue(2))); 4268 break; 4269 } 4270 4271 // These operators cannot be expanded directly, emit them as calls to 4272 // library functions. 4273 case ISD::FP_TO_SINT: 4274 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 4275 SDOperand Op; 4276 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4277 case Expand: assert(0 && "cannot expand FP!"); 4278 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 4279 case Promote: Op = PromoteOp(Node->getOperand(0)); break; 4280 } 4281 4282 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 4283 4284 // Now that the custom expander is done, expand the result, which is still 4285 // VT. 4286 if (Op.Val) { 4287 ExpandOp(Op, Lo, Hi); 4288 break; 4289 } 4290 } 4291 4292 if (Node->getOperand(0).getValueType() == MVT::f32) 4293 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 4294 else 4295 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 4296 break; 4297 4298 case ISD::FP_TO_UINT: 4299 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 4300 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, 4301 LegalizeOp(Node->getOperand(0))); 4302 // Now that the custom expander is done, expand the result, which is still 4303 // VT. 4304 Op = TLI.LowerOperation(Op, DAG); 4305 if (Op.Val) { 4306 ExpandOp(Op, Lo, Hi); 4307 break; 4308 } 4309 } 4310 4311 if (Node->getOperand(0).getValueType() == MVT::f32) 4312 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 4313 else 4314 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 4315 break; 4316 4317 case ISD::SHL: { 4318 // If the target wants custom lowering, do so. 4319 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4320 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 4321 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), 4322 ShiftAmt); 4323 Op = TLI.LowerOperation(Op, DAG); 4324 if (Op.Val) { 4325 // Now that the custom expander is done, expand the result, which is 4326 // still VT. 4327 ExpandOp(Op, Lo, Hi); 4328 break; 4329 } 4330 } 4331 4332 // If we can emit an efficient shift operation, do so now. 4333 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4334 break; 4335 4336 // If this target supports SHL_PARTS, use it. 4337 TargetLowering::LegalizeAction Action = 4338 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 4339 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4340 Action == TargetLowering::Custom) { 4341 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4342 break; 4343 } 4344 4345 // Otherwise, emit a libcall. 4346 Lo = ExpandLibCall("__ashldi3", Node, Hi); 4347 break; 4348 } 4349 4350 case ISD::SRA: { 4351 // If the target wants custom lowering, do so. 4352 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4353 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 4354 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), 4355 ShiftAmt); 4356 Op = TLI.LowerOperation(Op, DAG); 4357 if (Op.Val) { 4358 // Now that the custom expander is done, expand the result, which is 4359 // still VT. 4360 ExpandOp(Op, Lo, Hi); 4361 break; 4362 } 4363 } 4364 4365 // If we can emit an efficient shift operation, do so now. 4366 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4367 break; 4368 4369 // If this target supports SRA_PARTS, use it. 4370 TargetLowering::LegalizeAction Action = 4371 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 4372 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4373 Action == TargetLowering::Custom) { 4374 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4375 break; 4376 } 4377 4378 // Otherwise, emit a libcall. 4379 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 4380 break; 4381 } 4382 4383 case ISD::SRL: { 4384 // If the target wants custom lowering, do so. 4385 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4386 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 4387 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), 4388 ShiftAmt); 4389 Op = TLI.LowerOperation(Op, DAG); 4390 if (Op.Val) { 4391 // Now that the custom expander is done, expand the result, which is 4392 // still VT. 4393 ExpandOp(Op, Lo, Hi); 4394 break; 4395 } 4396 } 4397 4398 // If we can emit an efficient shift operation, do so now. 4399 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4400 break; 4401 4402 // If this target supports SRL_PARTS, use it. 4403 TargetLowering::LegalizeAction Action = 4404 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 4405 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4406 Action == TargetLowering::Custom) { 4407 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4408 break; 4409 } 4410 4411 // Otherwise, emit a libcall. 4412 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 4413 break; 4414 } 4415 4416 case ISD::ADD: 4417 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 4418 Lo, Hi); 4419 break; 4420 case ISD::SUB: 4421 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 4422 Lo, Hi); 4423 break; 4424 case ISD::MUL: { 4425 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 4426 SDOperand LL, LH, RL, RH; 4427 ExpandOp(Node->getOperand(0), LL, LH); 4428 ExpandOp(Node->getOperand(1), RL, RH); 4429 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 4430 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 4431 // extended the sign bit of the low half through the upper half, and if so 4432 // emit a MULHS instead of the alternate sequence that is valid for any 4433 // i64 x i64 multiply. 4434 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 4435 // is RH an extension of the sign bit of RL? 4436 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 4437 RH.getOperand(1).getOpcode() == ISD::Constant && 4438 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 4439 // is LH an extension of the sign bit of LL? 4440 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 4441 LH.getOperand(1).getOpcode() == ISD::Constant && 4442 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 4443 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 4444 } else { 4445 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 4446 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 4447 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 4448 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 4449 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 4450 } 4451 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 4452 } else { 4453 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 4454 } 4455 break; 4456 } 4457 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 4458 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 4459 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 4460 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 4461 } 4462 4463 // Make sure the resultant values have been legalized themselves, unless this 4464 // is a type that requires multi-step expansion. 4465 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 4466 Lo = LegalizeOp(Lo); 4467 Hi = LegalizeOp(Hi); 4468 } 4469 4470 // Remember in a map if the values will be reused later. 4471 bool isNew = 4472 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 4473 assert(isNew && "Value already expanded?!?"); 4474} 4475 4476 4477// SelectionDAG::Legalize - This is the entry point for the file. 4478// 4479void SelectionDAG::Legalize() { 4480 /// run - This is the main entry point to this class. 4481 /// 4482 SelectionDAGLegalize(*this).Run(); 4483} 4484 4485