LegalizeDAG.cpp revision ae35575957a3ab446e2766aa05d03020ced27d14
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned long long ValueTypeActions; 56 57 /// NeedsAnotherIteration - This is set when we expand a large integer 58 /// operation into smaller integer operations, but the smaller operations are 59 /// not set. This occurs only rarely in practice, for targets that don't have 60 /// 32-bit or larger integer registers. 61 bool NeedsAnotherIteration; 62 63 /// LegalizedNodes - For nodes that are of legal width, and that have more 64 /// than one use, this map indicates what regularized operand to use. This 65 /// allows us to avoid legalizing the same thing more than once. 66 std::map<SDOperand, SDOperand> LegalizedNodes; 67 68 /// PromotedNodes - For nodes that are below legal width, and that have more 69 /// than one use, this map indicates what promoted value to use. This allows 70 /// us to avoid promoting the same thing more than once. 71 std::map<SDOperand, SDOperand> PromotedNodes; 72 73 /// ExpandedNodes - For nodes that need to be expanded, and which have more 74 /// than one use, this map indicates which which operands are the expanded 75 /// version of the input. This allows us to avoid expanding the same node 76 /// more than once. 77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 78 79 void AddLegalizedOperand(SDOperand From, SDOperand To) { 80 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second; 81 assert(isNew && "Got into the map somehow?"); 82 } 83 void AddPromotedOperand(SDOperand From, SDOperand To) { 84 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 85 assert(isNew && "Got into the map somehow?"); 86 } 87 88public: 89 90 SelectionDAGLegalize(SelectionDAG &DAG); 91 92 /// Run - While there is still lowering to do, perform a pass over the DAG. 93 /// Most regularization can be done in a single pass, but targets that require 94 /// large values to be split into registers multiple times (e.g. i64 -> 4x 95 /// i16) require iteration for these values (the first iteration will demote 96 /// to i32, the second will demote to i16). 97 void Run() { 98 do { 99 NeedsAnotherIteration = false; 100 LegalizeDAG(); 101 } while (NeedsAnotherIteration); 102 } 103 104 /// getTypeAction - Return how we should legalize values of this type, either 105 /// it is already legal or we need to expand it into multiple registers of 106 /// smaller integer type, or we need to promote it to a larger type. 107 LegalizeAction getTypeAction(MVT::ValueType VT) const { 108 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 109 } 110 111 /// isTypeLegal - Return true if this type is legal on this target. 112 /// 113 bool isTypeLegal(MVT::ValueType VT) const { 114 return getTypeAction(VT) == Legal; 115 } 116 117private: 118 void LegalizeDAG(); 119 120 SDOperand LegalizeOp(SDOperand O); 121 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 122 SDOperand PromoteOp(SDOperand O); 123 124 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 125 SDOperand &Hi); 126 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 127 SDOperand Source); 128 129 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 130 SDOperand LegalOp, 131 MVT::ValueType DestVT); 132 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 133 bool isSigned); 134 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 135 bool isSigned); 136 137 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 138 SDOperand &Lo, SDOperand &Hi); 139 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 140 SDOperand &Lo, SDOperand &Hi); 141 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 142 SDOperand &Lo, SDOperand &Hi); 143 144 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 145 146 SDOperand getIntPtrConstant(uint64_t Val) { 147 return DAG.getConstant(Val, TLI.getPointerTy()); 148 } 149}; 150} 151 152static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 153 switch (VecOp) { 154 default: assert(0 && "Don't know how to scalarize this opcode!"); 155 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 156 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 157 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 158 } 159} 160 161SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 162 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 163 ValueTypeActions(TLI.getValueTypeActions()) { 164 assert(MVT::LAST_VALUETYPE <= 32 && 165 "Too many value types for ValueTypeActions to hold!"); 166} 167 168/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 169/// INT_TO_FP operation of the specified operand when the target requests that 170/// we expand it. At this point, we know that the result and operand types are 171/// legal for the target. 172SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 173 SDOperand Op0, 174 MVT::ValueType DestVT) { 175 if (Op0.getValueType() == MVT::i32) { 176 // simple 32-bit [signed|unsigned] integer to float/double expansion 177 178 // get the stack frame index of a 8 byte buffer 179 MachineFunction &MF = DAG.getMachineFunction(); 180 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 181 // get address of 8 byte buffer 182 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 183 // word offset constant for Hi/Lo address computation 184 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 185 // set up Hi and Lo (into buffer) address based on endian 186 SDOperand Hi, Lo; 187 if (TLI.isLittleEndian()) { 188 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 189 Lo = StackSlot; 190 } else { 191 Hi = StackSlot; 192 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 193 } 194 // if signed map to unsigned space 195 SDOperand Op0Mapped; 196 if (isSigned) { 197 // constant used to invert sign bit (signed to unsigned mapping) 198 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 199 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 200 } else { 201 Op0Mapped = Op0; 202 } 203 // store the lo of the constructed double - based on integer input 204 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 205 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 206 // initial hi portion of constructed double 207 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 208 // store the hi of the constructed double - biased exponent 209 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 210 InitialHi, Hi, DAG.getSrcValue(NULL)); 211 // load the constructed double 212 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 213 DAG.getSrcValue(NULL)); 214 // FP constant to bias correct the final result 215 SDOperand Bias = DAG.getConstantFP(isSigned ? 216 BitsToDouble(0x4330000080000000ULL) 217 : BitsToDouble(0x4330000000000000ULL), 218 MVT::f64); 219 // subtract the bias 220 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 221 // final result 222 SDOperand Result; 223 // handle final rounding 224 if (DestVT == MVT::f64) { 225 // do nothing 226 Result = Sub; 227 } else { 228 // if f32 then cast to f32 229 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 230 } 231 NeedsAnotherIteration = true; 232 return Result; 233 } 234 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 235 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 236 237 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 238 DAG.getConstant(0, Op0.getValueType()), 239 ISD::SETLT); 240 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 241 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 242 SignSet, Four, Zero); 243 244 // If the sign bit of the integer is set, the large number will be treated 245 // as a negative number. To counteract this, the dynamic code adds an 246 // offset depending on the data type. 247 uint64_t FF; 248 switch (Op0.getValueType()) { 249 default: assert(0 && "Unsupported integer type!"); 250 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 251 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 252 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 253 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 254 } 255 if (TLI.isLittleEndian()) FF <<= 32; 256 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 257 258 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 259 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 260 SDOperand FudgeInReg; 261 if (DestVT == MVT::f32) 262 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 263 DAG.getSrcValue(NULL)); 264 else { 265 assert(DestVT == MVT::f64 && "Unexpected conversion"); 266 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 267 DAG.getEntryNode(), CPIdx, 268 DAG.getSrcValue(NULL), MVT::f32)); 269 } 270 271 NeedsAnotherIteration = true; 272 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 273} 274 275/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 276/// *INT_TO_FP operation of the specified operand when the target requests that 277/// we promote it. At this point, we know that the result and operand types are 278/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 279/// operation that takes a larger input. 280SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 281 MVT::ValueType DestVT, 282 bool isSigned) { 283 // First step, figure out the appropriate *INT_TO_FP operation to use. 284 MVT::ValueType NewInTy = LegalOp.getValueType(); 285 286 unsigned OpToUse = 0; 287 288 // Scan for the appropriate larger type to use. 289 while (1) { 290 NewInTy = (MVT::ValueType)(NewInTy+1); 291 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 292 293 // If the target supports SINT_TO_FP of this type, use it. 294 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 295 default: break; 296 case TargetLowering::Legal: 297 if (!TLI.isTypeLegal(NewInTy)) 298 break; // Can't use this datatype. 299 // FALL THROUGH. 300 case TargetLowering::Custom: 301 OpToUse = ISD::SINT_TO_FP; 302 break; 303 } 304 if (OpToUse) break; 305 if (isSigned) continue; 306 307 // If the target supports UINT_TO_FP of this type, use it. 308 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 309 default: break; 310 case TargetLowering::Legal: 311 if (!TLI.isTypeLegal(NewInTy)) 312 break; // Can't use this datatype. 313 // FALL THROUGH. 314 case TargetLowering::Custom: 315 OpToUse = ISD::UINT_TO_FP; 316 break; 317 } 318 if (OpToUse) break; 319 320 // Otherwise, try a larger type. 321 } 322 323 // Make sure to legalize any nodes we create here in the next pass. 324 NeedsAnotherIteration = true; 325 326 // Okay, we found the operation and type to use. Zero extend our input to the 327 // desired type then run the operation on it. 328 return DAG.getNode(OpToUse, DestVT, 329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 330 NewInTy, LegalOp)); 331} 332 333/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 334/// FP_TO_*INT operation of the specified operand when the target requests that 335/// we promote it. At this point, we know that the result and operand types are 336/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 337/// operation that returns a larger result. 338SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 339 MVT::ValueType DestVT, 340 bool isSigned) { 341 // First step, figure out the appropriate FP_TO*INT operation to use. 342 MVT::ValueType NewOutTy = DestVT; 343 344 unsigned OpToUse = 0; 345 346 // Scan for the appropriate larger type to use. 347 while (1) { 348 NewOutTy = (MVT::ValueType)(NewOutTy+1); 349 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 350 351 // If the target supports FP_TO_SINT returning this type, use it. 352 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 353 default: break; 354 case TargetLowering::Legal: 355 if (!TLI.isTypeLegal(NewOutTy)) 356 break; // Can't use this datatype. 357 // FALL THROUGH. 358 case TargetLowering::Custom: 359 OpToUse = ISD::FP_TO_SINT; 360 break; 361 } 362 if (OpToUse) break; 363 364 // If the target supports FP_TO_UINT of this type, use it. 365 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 366 default: break; 367 case TargetLowering::Legal: 368 if (!TLI.isTypeLegal(NewOutTy)) 369 break; // Can't use this datatype. 370 // FALL THROUGH. 371 case TargetLowering::Custom: 372 OpToUse = ISD::FP_TO_UINT; 373 break; 374 } 375 if (OpToUse) break; 376 377 // Otherwise, try a larger type. 378 } 379 380 // Make sure to legalize any nodes we create here in the next pass. 381 NeedsAnotherIteration = true; 382 383 // Okay, we found the operation and type to use. Truncate the result of the 384 // extended FP_TO_*INT operation to the desired size. 385 return DAG.getNode(ISD::TRUNCATE, DestVT, 386 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 387} 388 389/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 390/// not been visited yet and if all of its operands have already been visited. 391static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 392 std::map<SDNode*, unsigned> &Visited) { 393 if (++Visited[N] != N->getNumOperands()) 394 return; // Haven't visited all operands yet 395 396 Order.push_back(N); 397 398 if (N->hasOneUse()) { // Tail recurse in common case. 399 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 400 return; 401 } 402 403 // Now that we have N in, add anything that uses it if all of their operands 404 // are now done. 405 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 406 ComputeTopDownOrdering(*UI, Order, Visited); 407} 408 409 410void SelectionDAGLegalize::LegalizeDAG() { 411 // The legalize process is inherently a bottom-up recursive process (users 412 // legalize their uses before themselves). Given infinite stack space, we 413 // could just start legalizing on the root and traverse the whole graph. In 414 // practice however, this causes us to run out of stack space on large basic 415 // blocks. To avoid this problem, compute an ordering of the nodes where each 416 // node is only legalized after all of its operands are legalized. 417 std::map<SDNode*, unsigned> Visited; 418 std::vector<SDNode*> Order; 419 420 // Compute ordering from all of the leaves in the graphs, those (like the 421 // entry node) that have no operands. 422 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 423 E = DAG.allnodes_end(); I != E; ++I) { 424 if (I->getNumOperands() == 0) { 425 Visited[I] = 0 - 1U; 426 ComputeTopDownOrdering(I, Order, Visited); 427 } 428 } 429 430 assert(Order.size() == Visited.size() && 431 Order.size() == 432 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 433 "Error: DAG is cyclic!"); 434 Visited.clear(); 435 436 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 437 SDNode *N = Order[i]; 438 switch (getTypeAction(N->getValueType(0))) { 439 default: assert(0 && "Bad type action!"); 440 case Legal: 441 LegalizeOp(SDOperand(N, 0)); 442 break; 443 case Promote: 444 PromoteOp(SDOperand(N, 0)); 445 break; 446 case Expand: { 447 SDOperand X, Y; 448 ExpandOp(SDOperand(N, 0), X, Y); 449 break; 450 } 451 } 452 } 453 454 // Finally, it's possible the root changed. Get the new root. 455 SDOperand OldRoot = DAG.getRoot(); 456 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 457 DAG.setRoot(LegalizedNodes[OldRoot]); 458 459 ExpandedNodes.clear(); 460 LegalizedNodes.clear(); 461 PromotedNodes.clear(); 462 463 // Remove dead nodes now. 464 DAG.RemoveDeadNodes(OldRoot.Val); 465} 466 467SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 468 assert(isTypeLegal(Op.getValueType()) && 469 "Caller should expand or promote operands that are not legal!"); 470 SDNode *Node = Op.Val; 471 472 // If this operation defines any values that cannot be represented in a 473 // register on this target, make sure to expand or promote them. 474 if (Node->getNumValues() > 1) { 475 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 476 switch (getTypeAction(Node->getValueType(i))) { 477 case Legal: break; // Nothing to do. 478 case Expand: { 479 SDOperand T1, T2; 480 ExpandOp(Op.getValue(i), T1, T2); 481 assert(LegalizedNodes.count(Op) && 482 "Expansion didn't add legal operands!"); 483 return LegalizedNodes[Op]; 484 } 485 case Promote: 486 PromoteOp(Op.getValue(i)); 487 assert(LegalizedNodes.count(Op) && 488 "Expansion didn't add legal operands!"); 489 return LegalizedNodes[Op]; 490 } 491 } 492 493 // Note that LegalizeOp may be reentered even from single-use nodes, which 494 // means that we always must cache transformed nodes. 495 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 496 if (I != LegalizedNodes.end()) return I->second; 497 498 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 499 500 SDOperand Result = Op; 501 502 switch (Node->getOpcode()) { 503 default: 504 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 505 // If this is a target node, legalize it by legalizing the operands then 506 // passing it through. 507 std::vector<SDOperand> Ops; 508 bool Changed = false; 509 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 510 Ops.push_back(LegalizeOp(Node->getOperand(i))); 511 Changed = Changed || Node->getOperand(i) != Ops.back(); 512 } 513 if (Changed) 514 if (Node->getNumValues() == 1) 515 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 516 else { 517 std::vector<MVT::ValueType> VTs(Node->value_begin(), 518 Node->value_end()); 519 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 520 } 521 522 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 523 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 524 return Result.getValue(Op.ResNo); 525 } 526 // Otherwise this is an unhandled builtin node. splat. 527 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 528 assert(0 && "Do not know how to legalize this operator!"); 529 abort(); 530 case ISD::EntryToken: 531 case ISD::FrameIndex: 532 case ISD::TargetFrameIndex: 533 case ISD::Register: 534 case ISD::TargetConstant: 535 case ISD::GlobalAddress: 536 case ISD::TargetGlobalAddress: 537 case ISD::ExternalSymbol: 538 case ISD::ConstantPool: // Nothing to do. 539 case ISD::BasicBlock: 540 case ISD::CONDCODE: 541 case ISD::VALUETYPE: 542 case ISD::SRCVALUE: 543 case ISD::STRING: 544 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 545 default: assert(0 && "This action is not supported yet!"); 546 case TargetLowering::Custom: { 547 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 548 if (Tmp.Val) { 549 Result = LegalizeOp(Tmp); 550 break; 551 } 552 } // FALLTHROUGH if the target doesn't want to lower this op after all. 553 case TargetLowering::Legal: 554 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!"); 555 break; 556 } 557 break; 558 case ISD::AssertSext: 559 case ISD::AssertZext: 560 Tmp1 = LegalizeOp(Node->getOperand(0)); 561 if (Tmp1 != Node->getOperand(0)) 562 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 563 Node->getOperand(1)); 564 break; 565 case ISD::MERGE_VALUES: 566 return LegalizeOp(Node->getOperand(Op.ResNo)); 567 case ISD::CopyFromReg: 568 Tmp1 = LegalizeOp(Node->getOperand(0)); 569 if (Tmp1 != Node->getOperand(0)) 570 Result = DAG.getCopyFromReg(Tmp1, 571 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 572 Node->getValueType(0)); 573 else 574 Result = Op.getValue(0); 575 576 // Since CopyFromReg produces two values, make sure to remember that we 577 // legalized both of them. 578 AddLegalizedOperand(Op.getValue(0), Result); 579 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 580 return Result.getValue(Op.ResNo); 581 case ISD::ImplicitDef: 582 Tmp1 = LegalizeOp(Node->getOperand(0)); 583 if (Tmp1 != Node->getOperand(0)) 584 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other, 585 Tmp1, Node->getOperand(1)); 586 break; 587 case ISD::UNDEF: { 588 MVT::ValueType VT = Op.getValueType(); 589 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 590 default: assert(0 && "This action is not supported yet!"); 591 case TargetLowering::Expand: 592 case TargetLowering::Promote: 593 if (MVT::isInteger(VT)) 594 Result = DAG.getConstant(0, VT); 595 else if (MVT::isFloatingPoint(VT)) 596 Result = DAG.getConstantFP(0, VT); 597 else 598 assert(0 && "Unknown value type!"); 599 break; 600 case TargetLowering::Legal: 601 break; 602 } 603 break; 604 } 605 606 case ISD::LOCATION: 607 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 608 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 609 610 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 611 case TargetLowering::Promote: 612 default: assert(0 && "This action is not supported yet!"); 613 case TargetLowering::Expand: 614 // If the target doesn't support line numbers, ignore this node. 615 Result = Tmp1; 616 break; 617 case TargetLowering::Legal: 618 if (Tmp1 != Node->getOperand(0)) { 619 std::vector<SDOperand> Ops; 620 Ops.push_back(Tmp1); 621 Ops.push_back(Node->getOperand(1)); // line # must be legal. 622 Ops.push_back(Node->getOperand(2)); // col # must be legal. 623 Ops.push_back(Node->getOperand(3)); // filename must be legal. 624 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 625 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops); 626 } 627 break; 628 } 629 break; 630 631 case ISD::Constant: 632 // We know we don't need to expand constants here, constants only have one 633 // value and we check that it is fine above. 634 635 // FIXME: Maybe we should handle things like targets that don't support full 636 // 32-bit immediates? 637 break; 638 case ISD::ConstantFP: { 639 // Spill FP immediates to the constant pool if the target cannot directly 640 // codegen them. Targets often have some immediate values that can be 641 // efficiently generated into an FP register without a load. We explicitly 642 // leave these constants as ConstantFP nodes for the target to deal with. 643 644 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 645 646 // Check to see if this FP immediate is already legal. 647 bool isLegal = false; 648 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 649 E = TLI.legal_fpimm_end(); I != E; ++I) 650 if (CFP->isExactlyValue(*I)) { 651 isLegal = true; 652 break; 653 } 654 655 if (!isLegal) { 656 // Otherwise we need to spill the constant to memory. 657 bool Extend = false; 658 659 // If a FP immediate is precise when represented as a float, we put it 660 // into the constant pool as a float, even if it's is statically typed 661 // as a double. 662 MVT::ValueType VT = CFP->getValueType(0); 663 bool isDouble = VT == MVT::f64; 664 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 665 Type::FloatTy, CFP->getValue()); 666 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 667 // Only do this if the target has a native EXTLOAD instruction from 668 // f32. 669 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 670 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 671 VT = MVT::f32; 672 Extend = true; 673 } 674 675 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 676 if (Extend) { 677 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 678 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 679 } else { 680 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 681 DAG.getSrcValue(NULL)); 682 } 683 } 684 break; 685 } 686 case ISD::TokenFactor: 687 if (Node->getNumOperands() == 2) { 688 bool Changed = false; 689 SDOperand Op0 = LegalizeOp(Node->getOperand(0)); 690 SDOperand Op1 = LegalizeOp(Node->getOperand(1)); 691 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1)) 692 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1); 693 } else { 694 std::vector<SDOperand> Ops; 695 bool Changed = false; 696 // Legalize the operands. 697 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 698 SDOperand Op = Node->getOperand(i); 699 Ops.push_back(LegalizeOp(Op)); 700 Changed |= Ops[i] != Op; 701 } 702 if (Changed) 703 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 704 } 705 break; 706 707 case ISD::CALLSEQ_START: 708 case ISD::CALLSEQ_END: 709 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 710 // Do not try to legalize the target-specific arguments (#1+) 711 Tmp2 = Node->getOperand(0); 712 if (Tmp1 != Tmp2) 713 Node->setAdjCallChain(Tmp1); 714 715 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These 716 // nodes are treated specially and are mutated in place. This makes the dag 717 // legalization process more efficient and also makes libcall insertion 718 // easier. 719 break; 720 case ISD::DYNAMIC_STACKALLOC: 721 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 722 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 723 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 724 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 725 Tmp3 != Node->getOperand(2)) { 726 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 727 std::vector<SDOperand> Ops; 728 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 729 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 730 } else 731 Result = Op.getValue(0); 732 733 // Since this op produces two values, make sure to remember that we 734 // legalized both of them. 735 AddLegalizedOperand(SDOperand(Node, 0), Result); 736 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 737 return Result.getValue(Op.ResNo); 738 739 case ISD::TAILCALL: 740 case ISD::CALL: { 741 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 742 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 743 744 bool Changed = false; 745 std::vector<SDOperand> Ops; 746 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 747 Ops.push_back(LegalizeOp(Node->getOperand(i))); 748 Changed |= Ops.back() != Node->getOperand(i); 749 } 750 751 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 752 std::vector<MVT::ValueType> RetTyVTs; 753 RetTyVTs.reserve(Node->getNumValues()); 754 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 755 RetTyVTs.push_back(Node->getValueType(i)); 756 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 757 Node->getOpcode() == ISD::TAILCALL), 0); 758 } else { 759 Result = Result.getValue(0); 760 } 761 // Since calls produce multiple values, make sure to remember that we 762 // legalized all of them. 763 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 764 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 765 return Result.getValue(Op.ResNo); 766 } 767 case ISD::BR: 768 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 769 if (Tmp1 != Node->getOperand(0)) 770 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 771 break; 772 773 case ISD::BRCOND: 774 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 775 776 switch (getTypeAction(Node->getOperand(1).getValueType())) { 777 case Expand: assert(0 && "It's impossible to expand bools"); 778 case Legal: 779 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 780 break; 781 case Promote: 782 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 783 break; 784 } 785 786 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 787 default: assert(0 && "This action is not supported yet!"); 788 case TargetLowering::Expand: 789 // Expand brcond's setcc into its constituent parts and create a BR_CC 790 // Node. 791 if (Tmp2.getOpcode() == ISD::SETCC) { 792 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 793 Tmp2.getOperand(0), Tmp2.getOperand(1), 794 Node->getOperand(2)); 795 } else { 796 // Make sure the condition is either zero or one. It may have been 797 // promoted from something else. 798 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 799 800 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 801 DAG.getCondCode(ISD::SETNE), Tmp2, 802 DAG.getConstant(0, Tmp2.getValueType()), 803 Node->getOperand(2)); 804 } 805 break; 806 case TargetLowering::Legal: 807 // Basic block destination (Op#2) is always legal. 808 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 809 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 810 Node->getOperand(2)); 811 break; 812 } 813 break; 814 case ISD::BR_CC: 815 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 816 817 if (isTypeLegal(Node->getOperand(2).getValueType())) { 818 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 819 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 820 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 821 Tmp3 != Node->getOperand(3)) { 822 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 823 Tmp2, Tmp3, Node->getOperand(4)); 824 } 825 break; 826 } else { 827 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 828 Node->getOperand(2), // LHS 829 Node->getOperand(3), // RHS 830 Node->getOperand(1))); 831 // If we get a SETCC back from legalizing the SETCC node we just 832 // created, then use its LHS, RHS, and CC directly in creating a new 833 // node. Otherwise, select between the true and false value based on 834 // comparing the result of the legalized with zero. 835 if (Tmp2.getOpcode() == ISD::SETCC) { 836 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 837 Tmp2.getOperand(0), Tmp2.getOperand(1), 838 Node->getOperand(4)); 839 } else { 840 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 841 DAG.getCondCode(ISD::SETNE), 842 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 843 Node->getOperand(4)); 844 } 845 } 846 break; 847 case ISD::BRCONDTWOWAY: 848 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 849 switch (getTypeAction(Node->getOperand(1).getValueType())) { 850 case Expand: assert(0 && "It's impossible to expand bools"); 851 case Legal: 852 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 853 break; 854 case Promote: 855 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 856 break; 857 } 858 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 859 // pair. 860 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 861 case TargetLowering::Promote: 862 default: assert(0 && "This action is not supported yet!"); 863 case TargetLowering::Legal: 864 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 865 std::vector<SDOperand> Ops; 866 Ops.push_back(Tmp1); 867 Ops.push_back(Tmp2); 868 Ops.push_back(Node->getOperand(2)); 869 Ops.push_back(Node->getOperand(3)); 870 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 871 } 872 break; 873 case TargetLowering::Expand: 874 // If BRTWOWAY_CC is legal for this target, then simply expand this node 875 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 876 // BRCOND/BR pair. 877 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 878 if (Tmp2.getOpcode() == ISD::SETCC) { 879 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 880 Tmp2.getOperand(0), Tmp2.getOperand(1), 881 Node->getOperand(2), Node->getOperand(3)); 882 } else { 883 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 884 DAG.getConstant(0, Tmp2.getValueType()), 885 Node->getOperand(2), Node->getOperand(3)); 886 } 887 } else { 888 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 889 Node->getOperand(2)); 890 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 891 } 892 break; 893 } 894 break; 895 case ISD::BRTWOWAY_CC: 896 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 897 if (isTypeLegal(Node->getOperand(2).getValueType())) { 898 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 899 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 900 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 901 Tmp3 != Node->getOperand(3)) { 902 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3, 903 Node->getOperand(4), Node->getOperand(5)); 904 } 905 break; 906 } else { 907 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 908 Node->getOperand(2), // LHS 909 Node->getOperand(3), // RHS 910 Node->getOperand(1))); 911 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 912 // pair. 913 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 914 default: assert(0 && "This action is not supported yet!"); 915 case TargetLowering::Legal: 916 // If we get a SETCC back from legalizing the SETCC node we just 917 // created, then use its LHS, RHS, and CC directly in creating a new 918 // node. Otherwise, select between the true and false value based on 919 // comparing the result of the legalized with zero. 920 if (Tmp2.getOpcode() == ISD::SETCC) { 921 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 922 Tmp2.getOperand(0), Tmp2.getOperand(1), 923 Node->getOperand(4), Node->getOperand(5)); 924 } else { 925 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 926 DAG.getConstant(0, Tmp2.getValueType()), 927 Node->getOperand(4), Node->getOperand(5)); 928 } 929 break; 930 case TargetLowering::Expand: 931 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 932 Node->getOperand(4)); 933 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 934 break; 935 } 936 } 937 break; 938 case ISD::LOAD: 939 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 940 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 941 942 if (Tmp1 != Node->getOperand(0) || 943 Tmp2 != Node->getOperand(1)) 944 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, 945 Node->getOperand(2)); 946 else 947 Result = SDOperand(Node, 0); 948 949 // Since loads produce two values, make sure to remember that we legalized 950 // both of them. 951 AddLegalizedOperand(SDOperand(Node, 0), Result); 952 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 953 return Result.getValue(Op.ResNo); 954 955 case ISD::EXTLOAD: 956 case ISD::SEXTLOAD: 957 case ISD::ZEXTLOAD: { 958 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 959 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 960 961 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 962 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 963 default: assert(0 && "This action is not supported yet!"); 964 case TargetLowering::Promote: 965 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 966 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 967 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 968 // Since loads produce two values, make sure to remember that we legalized 969 // both of them. 970 AddLegalizedOperand(SDOperand(Node, 0), Result); 971 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 972 return Result.getValue(Op.ResNo); 973 974 case TargetLowering::Legal: 975 if (Tmp1 != Node->getOperand(0) || 976 Tmp2 != Node->getOperand(1)) 977 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 978 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 979 else 980 Result = SDOperand(Node, 0); 981 982 // Since loads produce two values, make sure to remember that we legalized 983 // both of them. 984 AddLegalizedOperand(SDOperand(Node, 0), Result); 985 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 986 return Result.getValue(Op.ResNo); 987 case TargetLowering::Expand: 988 //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 989 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 990 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 991 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 992 if (Op.ResNo) 993 return Load.getValue(1); 994 return Result; 995 } 996 assert(Node->getOpcode() != ISD::EXTLOAD && 997 "EXTLOAD should always be supported!"); 998 // Turn the unsupported load into an EXTLOAD followed by an explicit 999 // zero/sign extend inreg. 1000 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1001 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1002 SDOperand ValRes; 1003 if (Node->getOpcode() == ISD::SEXTLOAD) 1004 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1005 Result, DAG.getValueType(SrcVT)); 1006 else 1007 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1008 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 1009 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1010 if (Op.ResNo) 1011 return Result.getValue(1); 1012 return ValRes; 1013 } 1014 assert(0 && "Unreachable"); 1015 } 1016 case ISD::EXTRACT_ELEMENT: { 1017 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1018 switch (getTypeAction(OpTy)) { 1019 default: 1020 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1021 break; 1022 case Legal: 1023 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1024 // 1 -> Hi 1025 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1026 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1027 TLI.getShiftAmountTy())); 1028 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1029 } else { 1030 // 0 -> Lo 1031 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1032 Node->getOperand(0)); 1033 } 1034 Result = LegalizeOp(Result); 1035 break; 1036 case Expand: 1037 // Get both the low and high parts. 1038 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1039 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1040 Result = Tmp2; // 1 -> Hi 1041 else 1042 Result = Tmp1; // 0 -> Lo 1043 break; 1044 } 1045 break; 1046 } 1047 1048 case ISD::CopyToReg: 1049 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1050 1051 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1052 "Register type must be legal!"); 1053 // Legalize the incoming value (must be legal). 1054 Tmp2 = LegalizeOp(Node->getOperand(2)); 1055 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2)) 1056 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1, 1057 Node->getOperand(1), Tmp2); 1058 break; 1059 1060 case ISD::RET: 1061 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1062 switch (Node->getNumOperands()) { 1063 case 2: // ret val 1064 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1065 case Legal: 1066 Tmp2 = LegalizeOp(Node->getOperand(1)); 1067 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1068 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1069 break; 1070 case Expand: { 1071 SDOperand Lo, Hi; 1072 ExpandOp(Node->getOperand(1), Lo, Hi); 1073 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1074 break; 1075 } 1076 case Promote: 1077 Tmp2 = PromoteOp(Node->getOperand(1)); 1078 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1079 break; 1080 } 1081 break; 1082 case 1: // ret void 1083 if (Tmp1 != Node->getOperand(0)) 1084 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 1085 break; 1086 default: { // ret <values> 1087 std::vector<SDOperand> NewValues; 1088 NewValues.push_back(Tmp1); 1089 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1090 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1091 case Legal: 1092 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1093 break; 1094 case Expand: { 1095 SDOperand Lo, Hi; 1096 ExpandOp(Node->getOperand(i), Lo, Hi); 1097 NewValues.push_back(Lo); 1098 NewValues.push_back(Hi); 1099 break; 1100 } 1101 case Promote: 1102 assert(0 && "Can't promote multiple return value yet!"); 1103 } 1104 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1105 break; 1106 } 1107 } 1108 break; 1109 case ISD::STORE: 1110 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1111 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1112 1113 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1114 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1115 if (CFP->getValueType(0) == MVT::f32) { 1116 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1117 DAG.getConstant(FloatToBits(CFP->getValue()), 1118 MVT::i32), 1119 Tmp2, 1120 Node->getOperand(3)); 1121 } else { 1122 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1123 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1124 DAG.getConstant(DoubleToBits(CFP->getValue()), 1125 MVT::i64), 1126 Tmp2, 1127 Node->getOperand(3)); 1128 } 1129 Node = Result.Val; 1130 } 1131 1132 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1133 case Legal: { 1134 SDOperand Val = LegalizeOp(Node->getOperand(1)); 1135 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 1136 Tmp2 != Node->getOperand(2)) 1137 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 1138 Node->getOperand(3)); 1139 break; 1140 } 1141 case Promote: 1142 // Truncate the value and store the result. 1143 Tmp3 = PromoteOp(Node->getOperand(1)); 1144 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1145 Node->getOperand(3), 1146 DAG.getValueType(Node->getOperand(1).getValueType())); 1147 break; 1148 1149 case Expand: 1150 SDOperand Lo, Hi; 1151 unsigned IncrementSize; 1152 ExpandOp(Node->getOperand(1), Lo, Hi); 1153 1154 if (!TLI.isLittleEndian()) 1155 std::swap(Lo, Hi); 1156 1157 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1158 Node->getOperand(3)); 1159 // If this is a vector type, then we have to calculate the increment as 1160 // the product of the element size in bytes, and the number of elements 1161 // in the high half of the vector. 1162 if (MVT::Vector == Hi.getValueType()) { 1163 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue(); 1164 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT(); 1165 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8; 1166 } else { 1167 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1168 } 1169 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1170 getIntPtrConstant(IncrementSize)); 1171 assert(isTypeLegal(Tmp2.getValueType()) && 1172 "Pointers must be legal!"); 1173 //Again, claiming both parts of the store came form the same Instr 1174 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1175 Node->getOperand(3)); 1176 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1177 break; 1178 } 1179 break; 1180 case ISD::PCMARKER: 1181 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1182 if (Tmp1 != Node->getOperand(0)) 1183 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 1184 break; 1185 case ISD::READCYCLECOUNTER: 1186 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1187 if (Tmp1 != Node->getOperand(0)) 1188 Result = DAG.getNode(ISD::READCYCLECOUNTER, MVT::i64, Tmp1); 1189 break; 1190 1191 case ISD::TRUNCSTORE: 1192 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1193 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1194 1195 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1196 case Legal: 1197 Tmp2 = LegalizeOp(Node->getOperand(1)); 1198 1199 // The only promote case we handle is TRUNCSTORE:i1 X into 1200 // -> TRUNCSTORE:i8 (and X, 1) 1201 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1202 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1203 TargetLowering::Promote) { 1204 // Promote the bool to a mask then store. 1205 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1206 DAG.getConstant(1, Tmp2.getValueType())); 1207 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1208 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1209 1210 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1211 Tmp3 != Node->getOperand(2)) { 1212 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1213 Node->getOperand(3), Node->getOperand(4)); 1214 } 1215 break; 1216 case Promote: 1217 case Expand: 1218 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 1219 } 1220 break; 1221 case ISD::SELECT: 1222 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1223 case Expand: assert(0 && "It's impossible to expand bools"); 1224 case Legal: 1225 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1226 break; 1227 case Promote: 1228 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1229 break; 1230 } 1231 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1232 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1233 1234 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1235 default: assert(0 && "This action is not supported yet!"); 1236 case TargetLowering::Expand: 1237 if (Tmp1.getOpcode() == ISD::SETCC) { 1238 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1239 Tmp2, Tmp3, 1240 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1241 } else { 1242 // Make sure the condition is either zero or one. It may have been 1243 // promoted from something else. 1244 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1245 Result = DAG.getSelectCC(Tmp1, 1246 DAG.getConstant(0, Tmp1.getValueType()), 1247 Tmp2, Tmp3, ISD::SETNE); 1248 } 1249 break; 1250 case TargetLowering::Legal: 1251 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1252 Tmp3 != Node->getOperand(2)) 1253 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 1254 Tmp1, Tmp2, Tmp3); 1255 break; 1256 case TargetLowering::Promote: { 1257 MVT::ValueType NVT = 1258 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1259 unsigned ExtOp, TruncOp; 1260 if (MVT::isInteger(Tmp2.getValueType())) { 1261 ExtOp = ISD::ANY_EXTEND; 1262 TruncOp = ISD::TRUNCATE; 1263 } else { 1264 ExtOp = ISD::FP_EXTEND; 1265 TruncOp = ISD::FP_ROUND; 1266 } 1267 // Promote each of the values to the new type. 1268 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1269 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1270 // Perform the larger operation, then round down. 1271 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1272 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1273 break; 1274 } 1275 } 1276 break; 1277 case ISD::SELECT_CC: 1278 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1279 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1280 1281 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1282 // Everything is legal, see if we should expand this op or something. 1283 switch (TLI.getOperationAction(ISD::SELECT_CC, 1284 Node->getOperand(0).getValueType())) { 1285 default: assert(0 && "This action is not supported yet!"); 1286 case TargetLowering::Custom: { 1287 SDOperand Tmp = 1288 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), 1289 Node->getOperand(0), 1290 Node->getOperand(1), Tmp3, Tmp4, 1291 Node->getOperand(4)), DAG); 1292 if (Tmp.Val) { 1293 Result = LegalizeOp(Tmp); 1294 break; 1295 } 1296 } // FALLTHROUGH if the target can't lower this operation after all. 1297 case TargetLowering::Legal: 1298 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1299 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1300 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1301 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { 1302 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2, 1303 Tmp3, Tmp4, Node->getOperand(4)); 1304 } 1305 break; 1306 } 1307 break; 1308 } else { 1309 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1310 Node->getOperand(0), // LHS 1311 Node->getOperand(1), // RHS 1312 Node->getOperand(4))); 1313 // If we get a SETCC back from legalizing the SETCC node we just 1314 // created, then use its LHS, RHS, and CC directly in creating a new 1315 // node. Otherwise, select between the true and false value based on 1316 // comparing the result of the legalized with zero. 1317 if (Tmp1.getOpcode() == ISD::SETCC) { 1318 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1319 Tmp1.getOperand(0), Tmp1.getOperand(1), 1320 Tmp3, Tmp4, Tmp1.getOperand(2)); 1321 } else { 1322 Result = DAG.getSelectCC(Tmp1, 1323 DAG.getConstant(0, Tmp1.getValueType()), 1324 Tmp3, Tmp4, ISD::SETNE); 1325 } 1326 } 1327 break; 1328 case ISD::SETCC: 1329 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1330 case Legal: 1331 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1332 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1333 break; 1334 case Promote: 1335 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1336 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1337 1338 // If this is an FP compare, the operands have already been extended. 1339 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1340 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1341 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1342 1343 // Otherwise, we have to insert explicit sign or zero extends. Note 1344 // that we could insert sign extends for ALL conditions, but zero extend 1345 // is cheaper on many machines (an AND instead of two shifts), so prefer 1346 // it. 1347 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1348 default: assert(0 && "Unknown integer comparison!"); 1349 case ISD::SETEQ: 1350 case ISD::SETNE: 1351 case ISD::SETUGE: 1352 case ISD::SETUGT: 1353 case ISD::SETULE: 1354 case ISD::SETULT: 1355 // ALL of these operations will work if we either sign or zero extend 1356 // the operands (including the unsigned comparisons!). Zero extend is 1357 // usually a simpler/cheaper operation, so prefer it. 1358 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1359 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1360 break; 1361 case ISD::SETGE: 1362 case ISD::SETGT: 1363 case ISD::SETLT: 1364 case ISD::SETLE: 1365 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1366 DAG.getValueType(VT)); 1367 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1368 DAG.getValueType(VT)); 1369 break; 1370 } 1371 } 1372 break; 1373 case Expand: 1374 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1375 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1376 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1377 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1378 case ISD::SETEQ: 1379 case ISD::SETNE: 1380 if (RHSLo == RHSHi) 1381 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1382 if (RHSCST->isAllOnesValue()) { 1383 // Comparison to -1. 1384 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1385 Tmp2 = RHSLo; 1386 break; 1387 } 1388 1389 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1390 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1391 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1392 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1393 break; 1394 default: 1395 // If this is a comparison of the sign bit, just look at the top part. 1396 // X > -1, x < 0 1397 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1398 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1399 CST->getValue() == 0) || // X < 0 1400 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1401 (CST->isAllOnesValue()))) { // X > -1 1402 Tmp1 = LHSHi; 1403 Tmp2 = RHSHi; 1404 break; 1405 } 1406 1407 // FIXME: This generated code sucks. 1408 ISD::CondCode LowCC; 1409 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1410 default: assert(0 && "Unknown integer setcc!"); 1411 case ISD::SETLT: 1412 case ISD::SETULT: LowCC = ISD::SETULT; break; 1413 case ISD::SETGT: 1414 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1415 case ISD::SETLE: 1416 case ISD::SETULE: LowCC = ISD::SETULE; break; 1417 case ISD::SETGE: 1418 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1419 } 1420 1421 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1422 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1423 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1424 1425 // NOTE: on targets without efficient SELECT of bools, we can always use 1426 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1427 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1428 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1429 Node->getOperand(2)); 1430 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1431 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1432 Result, Tmp1, Tmp2)); 1433 return Result; 1434 } 1435 } 1436 1437 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) { 1438 default: 1439 assert(0 && "Cannot handle this action for SETCC yet!"); 1440 break; 1441 case TargetLowering::Promote: { 1442 // First step, figure out the appropriate operation to use. 1443 // Allow SETCC to not be supported for all legal data types 1444 // Mostly this targets FP 1445 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1446 MVT::ValueType OldVT = NewInTy; 1447 1448 // Scan for the appropriate larger type to use. 1449 while (1) { 1450 NewInTy = (MVT::ValueType)(NewInTy+1); 1451 1452 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1453 "Fell off of the edge of the integer world"); 1454 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1455 "Fell off of the edge of the floating point world"); 1456 1457 // If the target supports SETCC of this type, use it. 1458 if (TLI.getOperationAction(ISD::SETCC, NewInTy) == TargetLowering::Legal) 1459 break; 1460 } 1461 if (MVT::isInteger(NewInTy)) 1462 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1463 else { 1464 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1465 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1466 } 1467 1468 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1469 Node->getOperand(2)); 1470 break; 1471 } 1472 case TargetLowering::Legal: 1473 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1474 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1475 Node->getOperand(2)); 1476 break; 1477 case TargetLowering::Expand: 1478 // Expand a setcc node into a select_cc of the same condition, lhs, and 1479 // rhs that selects between const 1 (true) and const 0 (false). 1480 MVT::ValueType VT = Node->getValueType(0); 1481 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1482 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1483 Node->getOperand(2)); 1484 Result = LegalizeOp(Result); 1485 break; 1486 } 1487 break; 1488 1489 case ISD::MEMSET: 1490 case ISD::MEMCPY: 1491 case ISD::MEMMOVE: { 1492 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1493 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1494 1495 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1496 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1497 case Expand: assert(0 && "Cannot expand a byte!"); 1498 case Legal: 1499 Tmp3 = LegalizeOp(Node->getOperand(2)); 1500 break; 1501 case Promote: 1502 Tmp3 = PromoteOp(Node->getOperand(2)); 1503 break; 1504 } 1505 } else { 1506 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1507 } 1508 1509 SDOperand Tmp4; 1510 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1511 case Expand: { 1512 // Length is too big, just take the lo-part of the length. 1513 SDOperand HiPart; 1514 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1515 break; 1516 } 1517 case Legal: 1518 Tmp4 = LegalizeOp(Node->getOperand(3)); 1519 break; 1520 case Promote: 1521 Tmp4 = PromoteOp(Node->getOperand(3)); 1522 break; 1523 } 1524 1525 SDOperand Tmp5; 1526 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1527 case Expand: assert(0 && "Cannot expand this yet!"); 1528 case Legal: 1529 Tmp5 = LegalizeOp(Node->getOperand(4)); 1530 break; 1531 case Promote: 1532 Tmp5 = PromoteOp(Node->getOperand(4)); 1533 break; 1534 } 1535 1536 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1537 default: assert(0 && "This action not implemented for this operation!"); 1538 case TargetLowering::Custom: { 1539 SDOperand Tmp = 1540 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 1541 Tmp2, Tmp3, Tmp4, Tmp5), DAG); 1542 if (Tmp.Val) { 1543 Result = LegalizeOp(Tmp); 1544 break; 1545 } 1546 // FALLTHROUGH if the target thinks it is legal. 1547 } 1548 case TargetLowering::Legal: 1549 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1550 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 1551 Tmp5 != Node->getOperand(4)) { 1552 std::vector<SDOperand> Ops; 1553 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 1554 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 1555 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 1556 } 1557 break; 1558 case TargetLowering::Expand: { 1559 // Otherwise, the target does not support this operation. Lower the 1560 // operation to an explicit libcall as appropriate. 1561 MVT::ValueType IntPtr = TLI.getPointerTy(); 1562 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1563 std::vector<std::pair<SDOperand, const Type*> > Args; 1564 1565 const char *FnName = 0; 1566 if (Node->getOpcode() == ISD::MEMSET) { 1567 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1568 // Extend the ubyte argument to be an int value for the call. 1569 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1570 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1571 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1572 1573 FnName = "memset"; 1574 } else if (Node->getOpcode() == ISD::MEMCPY || 1575 Node->getOpcode() == ISD::MEMMOVE) { 1576 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1577 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1578 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1579 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1580 } else { 1581 assert(0 && "Unknown op!"); 1582 } 1583 1584 std::pair<SDOperand,SDOperand> CallResult = 1585 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1586 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1587 Result = CallResult.second; 1588 NeedsAnotherIteration = true; 1589 break; 1590 } 1591 } 1592 break; 1593 } 1594 1595 case ISD::READPORT: 1596 Tmp1 = LegalizeOp(Node->getOperand(0)); 1597 Tmp2 = LegalizeOp(Node->getOperand(1)); 1598 1599 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1600 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1601 std::vector<SDOperand> Ops; 1602 Ops.push_back(Tmp1); 1603 Ops.push_back(Tmp2); 1604 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1605 } else 1606 Result = SDOperand(Node, 0); 1607 // Since these produce two values, make sure to remember that we legalized 1608 // both of them. 1609 AddLegalizedOperand(SDOperand(Node, 0), Result); 1610 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1611 return Result.getValue(Op.ResNo); 1612 case ISD::WRITEPORT: 1613 Tmp1 = LegalizeOp(Node->getOperand(0)); 1614 Tmp2 = LegalizeOp(Node->getOperand(1)); 1615 Tmp3 = LegalizeOp(Node->getOperand(2)); 1616 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1617 Tmp3 != Node->getOperand(2)) 1618 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1619 break; 1620 1621 case ISD::READIO: 1622 Tmp1 = LegalizeOp(Node->getOperand(0)); 1623 Tmp2 = LegalizeOp(Node->getOperand(1)); 1624 1625 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1626 case TargetLowering::Custom: 1627 default: assert(0 && "This action not implemented for this operation!"); 1628 case TargetLowering::Legal: 1629 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1630 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1631 std::vector<SDOperand> Ops; 1632 Ops.push_back(Tmp1); 1633 Ops.push_back(Tmp2); 1634 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1635 } else 1636 Result = SDOperand(Node, 0); 1637 break; 1638 case TargetLowering::Expand: 1639 // Replace this with a load from memory. 1640 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 1641 Node->getOperand(1), DAG.getSrcValue(NULL)); 1642 Result = LegalizeOp(Result); 1643 break; 1644 } 1645 1646 // Since these produce two values, make sure to remember that we legalized 1647 // both of them. 1648 AddLegalizedOperand(SDOperand(Node, 0), Result); 1649 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1650 return Result.getValue(Op.ResNo); 1651 1652 case ISD::WRITEIO: 1653 Tmp1 = LegalizeOp(Node->getOperand(0)); 1654 Tmp2 = LegalizeOp(Node->getOperand(1)); 1655 Tmp3 = LegalizeOp(Node->getOperand(2)); 1656 1657 switch (TLI.getOperationAction(Node->getOpcode(), 1658 Node->getOperand(1).getValueType())) { 1659 case TargetLowering::Custom: 1660 default: assert(0 && "This action not implemented for this operation!"); 1661 case TargetLowering::Legal: 1662 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1663 Tmp3 != Node->getOperand(2)) 1664 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1665 break; 1666 case TargetLowering::Expand: 1667 // Replace this with a store to memory. 1668 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 1669 Node->getOperand(1), Node->getOperand(2), 1670 DAG.getSrcValue(NULL)); 1671 Result = LegalizeOp(Result); 1672 break; 1673 } 1674 break; 1675 1676 case ISD::ADD_PARTS: 1677 case ISD::SUB_PARTS: 1678 case ISD::SHL_PARTS: 1679 case ISD::SRA_PARTS: 1680 case ISD::SRL_PARTS: { 1681 std::vector<SDOperand> Ops; 1682 bool Changed = false; 1683 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1684 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1685 Changed |= Ops.back() != Node->getOperand(i); 1686 } 1687 if (Changed) { 1688 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1689 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 1690 } 1691 1692 // Since these produce multiple values, make sure to remember that we 1693 // legalized all of them. 1694 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1695 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1696 return Result.getValue(Op.ResNo); 1697 } 1698 1699 // Binary operators 1700 case ISD::ADD: 1701 case ISD::SUB: 1702 case ISD::MUL: 1703 case ISD::MULHS: 1704 case ISD::MULHU: 1705 case ISD::UDIV: 1706 case ISD::SDIV: 1707 case ISD::AND: 1708 case ISD::OR: 1709 case ISD::XOR: 1710 case ISD::SHL: 1711 case ISD::SRL: 1712 case ISD::SRA: 1713 case ISD::FADD: 1714 case ISD::FSUB: 1715 case ISD::FMUL: 1716 case ISD::FDIV: 1717 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1718 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1719 case Expand: assert(0 && "Not possible"); 1720 case Legal: 1721 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1722 break; 1723 case Promote: 1724 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 1725 break; 1726 } 1727 if (Tmp1 != Node->getOperand(0) || 1728 Tmp2 != Node->getOperand(1)) 1729 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 1730 break; 1731 1732 case ISD::BUILD_PAIR: { 1733 MVT::ValueType PairTy = Node->getValueType(0); 1734 // TODO: handle the case where the Lo and Hi operands are not of legal type 1735 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 1736 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 1737 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 1738 case TargetLowering::Legal: 1739 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1740 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 1741 break; 1742 case TargetLowering::Promote: 1743 case TargetLowering::Custom: 1744 assert(0 && "Cannot promote/custom this yet!"); 1745 case TargetLowering::Expand: 1746 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 1747 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 1748 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 1749 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 1750 TLI.getShiftAmountTy())); 1751 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2)); 1752 break; 1753 } 1754 break; 1755 } 1756 1757 case ISD::UREM: 1758 case ISD::SREM: 1759 case ISD::FREM: 1760 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1761 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1762 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1763 case TargetLowering::Legal: 1764 if (Tmp1 != Node->getOperand(0) || 1765 Tmp2 != Node->getOperand(1)) 1766 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1767 Tmp2); 1768 break; 1769 case TargetLowering::Promote: 1770 case TargetLowering::Custom: 1771 assert(0 && "Cannot promote/custom handle this yet!"); 1772 case TargetLowering::Expand: 1773 if (MVT::isInteger(Node->getValueType(0))) { 1774 MVT::ValueType VT = Node->getValueType(0); 1775 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 1776 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 1777 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 1778 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 1779 } else { 1780 // Floating point mod -> fmod libcall. 1781 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 1782 SDOperand Dummy; 1783 Result = ExpandLibCall(FnName, Node, Dummy); 1784 } 1785 break; 1786 } 1787 break; 1788 1789 case ISD::CTPOP: 1790 case ISD::CTTZ: 1791 case ISD::CTLZ: 1792 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1793 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1794 case TargetLowering::Legal: 1795 if (Tmp1 != Node->getOperand(0)) 1796 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1797 break; 1798 case TargetLowering::Promote: { 1799 MVT::ValueType OVT = Tmp1.getValueType(); 1800 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1801 1802 // Zero extend the argument. 1803 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1804 // Perform the larger operation, then subtract if needed. 1805 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1806 switch(Node->getOpcode()) 1807 { 1808 case ISD::CTPOP: 1809 Result = Tmp1; 1810 break; 1811 case ISD::CTTZ: 1812 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 1813 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 1814 DAG.getConstant(getSizeInBits(NVT), NVT), 1815 ISD::SETEQ); 1816 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 1817 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 1818 break; 1819 case ISD::CTLZ: 1820 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 1821 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 1822 DAG.getConstant(getSizeInBits(NVT) - 1823 getSizeInBits(OVT), NVT)); 1824 break; 1825 } 1826 break; 1827 } 1828 case TargetLowering::Custom: 1829 assert(0 && "Cannot custom handle this yet!"); 1830 case TargetLowering::Expand: 1831 switch(Node->getOpcode()) 1832 { 1833 case ISD::CTPOP: { 1834 static const uint64_t mask[6] = { 1835 0x5555555555555555ULL, 0x3333333333333333ULL, 1836 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 1837 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 1838 }; 1839 MVT::ValueType VT = Tmp1.getValueType(); 1840 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1841 unsigned len = getSizeInBits(VT); 1842 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1843 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 1844 Tmp2 = DAG.getConstant(mask[i], VT); 1845 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1846 Tmp1 = DAG.getNode(ISD::ADD, VT, 1847 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 1848 DAG.getNode(ISD::AND, VT, 1849 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 1850 Tmp2)); 1851 } 1852 Result = Tmp1; 1853 break; 1854 } 1855 case ISD::CTLZ: { 1856 /* for now, we do this: 1857 x = x | (x >> 1); 1858 x = x | (x >> 2); 1859 ... 1860 x = x | (x >>16); 1861 x = x | (x >>32); // for 64-bit input 1862 return popcount(~x); 1863 1864 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ 1865 MVT::ValueType VT = Tmp1.getValueType(); 1866 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1867 unsigned len = getSizeInBits(VT); 1868 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1869 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1870 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, 1871 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); 1872 } 1873 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); 1874 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1875 break; 1876 } 1877 case ISD::CTTZ: { 1878 // for now, we use: { return popcount(~x & (x - 1)); } 1879 // unless the target has ctlz but not ctpop, in which case we use: 1880 // { return 32 - nlz(~x & (x-1)); } 1881 // see also http://www.hackersdelight.org/HDcode/ntz.cc 1882 MVT::ValueType VT = Tmp1.getValueType(); 1883 Tmp2 = DAG.getConstant(~0ULL, VT); 1884 Tmp3 = DAG.getNode(ISD::AND, VT, 1885 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), 1886 DAG.getNode(ISD::SUB, VT, Tmp1, 1887 DAG.getConstant(1, VT))); 1888 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead 1889 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 1890 TLI.isOperationLegal(ISD::CTLZ, VT)) { 1891 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, 1892 DAG.getConstant(getSizeInBits(VT), VT), 1893 DAG.getNode(ISD::CTLZ, VT, Tmp3))); 1894 } else { 1895 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1896 } 1897 break; 1898 } 1899 default: 1900 assert(0 && "Cannot expand this yet!"); 1901 break; 1902 } 1903 break; 1904 } 1905 break; 1906 1907 // Unary operators 1908 case ISD::FABS: 1909 case ISD::FNEG: 1910 case ISD::FSQRT: 1911 case ISD::FSIN: 1912 case ISD::FCOS: 1913 Tmp1 = LegalizeOp(Node->getOperand(0)); 1914 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1915 case TargetLowering::Legal: 1916 if (Tmp1 != Node->getOperand(0)) 1917 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1918 break; 1919 case TargetLowering::Promote: 1920 case TargetLowering::Custom: 1921 assert(0 && "Cannot promote/custom handle this yet!"); 1922 case TargetLowering::Expand: 1923 switch(Node->getOpcode()) { 1924 case ISD::FNEG: { 1925 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 1926 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 1927 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0), 1928 Tmp2, Tmp1)); 1929 break; 1930 } 1931 case ISD::FABS: { 1932 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 1933 MVT::ValueType VT = Node->getValueType(0); 1934 Tmp2 = DAG.getConstantFP(0.0, VT); 1935 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 1936 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 1937 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 1938 Result = LegalizeOp(Result); 1939 break; 1940 } 1941 case ISD::FSQRT: 1942 case ISD::FSIN: 1943 case ISD::FCOS: { 1944 MVT::ValueType VT = Node->getValueType(0); 1945 const char *FnName = 0; 1946 switch(Node->getOpcode()) { 1947 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 1948 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 1949 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 1950 default: assert(0 && "Unreachable!"); 1951 } 1952 SDOperand Dummy; 1953 Result = ExpandLibCall(FnName, Node, Dummy); 1954 break; 1955 } 1956 default: 1957 assert(0 && "Unreachable!"); 1958 } 1959 break; 1960 } 1961 break; 1962 1963 // Conversion operators. The source and destination have different types. 1964 case ISD::SINT_TO_FP: 1965 case ISD::UINT_TO_FP: { 1966 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 1967 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1968 case Legal: 1969 switch (TLI.getOperationAction(Node->getOpcode(), 1970 Node->getOperand(0).getValueType())) { 1971 default: assert(0 && "Unknown operation action!"); 1972 case TargetLowering::Expand: 1973 Result = ExpandLegalINT_TO_FP(isSigned, 1974 LegalizeOp(Node->getOperand(0)), 1975 Node->getValueType(0)); 1976 AddLegalizedOperand(Op, Result); 1977 return Result; 1978 case TargetLowering::Promote: 1979 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 1980 Node->getValueType(0), 1981 isSigned); 1982 AddLegalizedOperand(Op, Result); 1983 return Result; 1984 case TargetLowering::Legal: 1985 break; 1986 case TargetLowering::Custom: { 1987 Tmp1 = LegalizeOp(Node->getOperand(0)); 1988 SDOperand Tmp = 1989 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1990 Tmp = TLI.LowerOperation(Tmp, DAG); 1991 if (Tmp.Val) { 1992 AddLegalizedOperand(Op, Tmp); 1993 NeedsAnotherIteration = true; 1994 return Tmp; 1995 } else { 1996 assert(0 && "Target Must Lower this"); 1997 } 1998 } 1999 } 2000 2001 Tmp1 = LegalizeOp(Node->getOperand(0)); 2002 if (Tmp1 != Node->getOperand(0)) 2003 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2004 break; 2005 case Expand: 2006 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2007 Node->getValueType(0), Node->getOperand(0)); 2008 break; 2009 case Promote: 2010 if (isSigned) { 2011 Result = PromoteOp(Node->getOperand(0)); 2012 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2013 Result, DAG.getValueType(Node->getOperand(0).getValueType())); 2014 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 2015 } else { 2016 Result = PromoteOp(Node->getOperand(0)); 2017 Result = DAG.getZeroExtendInReg(Result, 2018 Node->getOperand(0).getValueType()); 2019 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 2020 } 2021 break; 2022 } 2023 break; 2024 } 2025 case ISD::TRUNCATE: 2026 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2027 case Legal: 2028 Tmp1 = LegalizeOp(Node->getOperand(0)); 2029 if (Tmp1 != Node->getOperand(0)) 2030 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2031 break; 2032 case Expand: 2033 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2034 2035 // Since the result is legal, we should just be able to truncate the low 2036 // part of the source. 2037 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2038 break; 2039 case Promote: 2040 Result = PromoteOp(Node->getOperand(0)); 2041 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2042 break; 2043 } 2044 break; 2045 2046 case ISD::FP_TO_SINT: 2047 case ISD::FP_TO_UINT: 2048 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2049 case Legal: 2050 Tmp1 = LegalizeOp(Node->getOperand(0)); 2051 2052 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2053 default: assert(0 && "Unknown operation action!"); 2054 case TargetLowering::Expand: 2055 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2056 SDOperand True, False; 2057 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2058 MVT::ValueType NVT = Node->getValueType(0); 2059 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2060 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2061 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2062 Node->getOperand(0), Tmp2, ISD::SETLT); 2063 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2064 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2065 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2066 Tmp2)); 2067 False = DAG.getNode(ISD::XOR, NVT, False, 2068 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2069 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False)); 2070 return Result; 2071 } else { 2072 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2073 } 2074 break; 2075 case TargetLowering::Promote: 2076 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2077 Node->getOpcode() == ISD::FP_TO_SINT); 2078 AddLegalizedOperand(Op, Result); 2079 return Result; 2080 case TargetLowering::Custom: { 2081 SDOperand Tmp = 2082 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2083 Tmp = TLI.LowerOperation(Tmp, DAG); 2084 if (Tmp.Val) { 2085 AddLegalizedOperand(Op, Tmp); 2086 NeedsAnotherIteration = true; 2087 return Tmp; 2088 } else { 2089 // The target thinks this is legal afterall. 2090 break; 2091 } 2092 } 2093 case TargetLowering::Legal: 2094 break; 2095 } 2096 2097 if (Tmp1 != Node->getOperand(0)) 2098 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2099 break; 2100 case Expand: 2101 assert(0 && "Shouldn't need to expand other operators here!"); 2102 case Promote: 2103 Result = PromoteOp(Node->getOperand(0)); 2104 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2105 break; 2106 } 2107 break; 2108 2109 case ISD::ANY_EXTEND: 2110 case ISD::ZERO_EXTEND: 2111 case ISD::SIGN_EXTEND: 2112 case ISD::FP_EXTEND: 2113 case ISD::FP_ROUND: 2114 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2115 case Legal: 2116 Tmp1 = LegalizeOp(Node->getOperand(0)); 2117 if (Tmp1 != Node->getOperand(0)) 2118 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2119 break; 2120 case Expand: 2121 assert(0 && "Shouldn't need to expand other operators here!"); 2122 2123 case Promote: 2124 switch (Node->getOpcode()) { 2125 case ISD::ANY_EXTEND: 2126 Result = PromoteOp(Node->getOperand(0)); 2127 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2128 break; 2129 case ISD::ZERO_EXTEND: 2130 Result = PromoteOp(Node->getOperand(0)); 2131 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2132 Result = DAG.getZeroExtendInReg(Result, 2133 Node->getOperand(0).getValueType()); 2134 break; 2135 case ISD::SIGN_EXTEND: 2136 Result = PromoteOp(Node->getOperand(0)); 2137 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2138 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2139 Result, 2140 DAG.getValueType(Node->getOperand(0).getValueType())); 2141 break; 2142 case ISD::FP_EXTEND: 2143 Result = PromoteOp(Node->getOperand(0)); 2144 if (Result.getValueType() != Op.getValueType()) 2145 // Dynamically dead while we have only 2 FP types. 2146 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2147 break; 2148 case ISD::FP_ROUND: 2149 Result = PromoteOp(Node->getOperand(0)); 2150 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2151 break; 2152 } 2153 } 2154 break; 2155 case ISD::FP_ROUND_INREG: 2156 case ISD::SIGN_EXTEND_INREG: { 2157 Tmp1 = LegalizeOp(Node->getOperand(0)); 2158 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2159 2160 // If this operation is not supported, convert it to a shl/shr or load/store 2161 // pair. 2162 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2163 default: assert(0 && "This action not supported for this op yet!"); 2164 case TargetLowering::Legal: 2165 if (Tmp1 != Node->getOperand(0)) 2166 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2167 DAG.getValueType(ExtraVT)); 2168 break; 2169 case TargetLowering::Expand: 2170 // If this is an integer extend and shifts are supported, do that. 2171 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2172 // NOTE: we could fall back on load/store here too for targets without 2173 // SAR. However, it is doubtful that any exist. 2174 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2175 MVT::getSizeInBits(ExtraVT); 2176 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2177 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2178 Node->getOperand(0), ShiftCst); 2179 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2180 Result, ShiftCst); 2181 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2182 // The only way we can lower this is to turn it into a STORETRUNC, 2183 // EXTLOAD pair, targetting a temporary location (a stack slot). 2184 2185 // NOTE: there is a choice here between constantly creating new stack 2186 // slots and always reusing the same one. We currently always create 2187 // new ones, as reuse may inhibit scheduling. 2188 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2189 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2190 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2191 MachineFunction &MF = DAG.getMachineFunction(); 2192 int SSFI = 2193 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2194 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2195 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2196 Node->getOperand(0), StackSlot, 2197 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2198 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2199 Result, StackSlot, DAG.getSrcValue(NULL), 2200 ExtraVT); 2201 } else { 2202 assert(0 && "Unknown op"); 2203 } 2204 Result = LegalizeOp(Result); 2205 break; 2206 } 2207 break; 2208 } 2209 } 2210 2211 // Note that LegalizeOp may be reentered even from single-use nodes, which 2212 // means that we always must cache transformed nodes. 2213 AddLegalizedOperand(Op, Result); 2214 return Result; 2215} 2216 2217/// PromoteOp - Given an operation that produces a value in an invalid type, 2218/// promote it to compute the value into a larger type. The produced value will 2219/// have the correct bits for the low portion of the register, but no guarantee 2220/// is made about the top bits: it may be zero, sign-extended, or garbage. 2221SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2222 MVT::ValueType VT = Op.getValueType(); 2223 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2224 assert(getTypeAction(VT) == Promote && 2225 "Caller should expand or legalize operands that are not promotable!"); 2226 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2227 "Cannot promote to smaller type!"); 2228 2229 SDOperand Tmp1, Tmp2, Tmp3; 2230 2231 SDOperand Result; 2232 SDNode *Node = Op.Val; 2233 2234 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2235 if (I != PromotedNodes.end()) return I->second; 2236 2237 // Promotion needs an optimization step to clean up after it, and is not 2238 // careful to avoid operations the target does not support. Make sure that 2239 // all generated operations are legalized in the next iteration. 2240 NeedsAnotherIteration = true; 2241 2242 switch (Node->getOpcode()) { 2243 case ISD::CopyFromReg: 2244 assert(0 && "CopyFromReg must be legal!"); 2245 default: 2246 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2247 assert(0 && "Do not know how to promote this operator!"); 2248 abort(); 2249 case ISD::UNDEF: 2250 Result = DAG.getNode(ISD::UNDEF, NVT); 2251 break; 2252 case ISD::Constant: 2253 if (VT != MVT::i1) 2254 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2255 else 2256 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2257 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2258 break; 2259 case ISD::ConstantFP: 2260 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2261 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2262 break; 2263 2264 case ISD::SETCC: 2265 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2266 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2267 Node->getOperand(1), Node->getOperand(2)); 2268 Result = LegalizeOp(Result); 2269 break; 2270 2271 case ISD::TRUNCATE: 2272 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2273 case Legal: 2274 Result = LegalizeOp(Node->getOperand(0)); 2275 assert(Result.getValueType() >= NVT && 2276 "This truncation doesn't make sense!"); 2277 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2278 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2279 break; 2280 case Promote: 2281 // The truncation is not required, because we don't guarantee anything 2282 // about high bits anyway. 2283 Result = PromoteOp(Node->getOperand(0)); 2284 break; 2285 case Expand: 2286 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2287 // Truncate the low part of the expanded value to the result type 2288 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2289 } 2290 break; 2291 case ISD::SIGN_EXTEND: 2292 case ISD::ZERO_EXTEND: 2293 case ISD::ANY_EXTEND: 2294 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2295 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2296 case Legal: 2297 // Input is legal? Just do extend all the way to the larger type. 2298 Result = LegalizeOp(Node->getOperand(0)); 2299 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2300 break; 2301 case Promote: 2302 // Promote the reg if it's smaller. 2303 Result = PromoteOp(Node->getOperand(0)); 2304 // The high bits are not guaranteed to be anything. Insert an extend. 2305 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2306 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2307 DAG.getValueType(Node->getOperand(0).getValueType())); 2308 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2309 Result = DAG.getZeroExtendInReg(Result, 2310 Node->getOperand(0).getValueType()); 2311 break; 2312 } 2313 break; 2314 2315 case ISD::FP_EXTEND: 2316 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2317 case ISD::FP_ROUND: 2318 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2319 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2320 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2321 case Legal: 2322 // Input is legal? Do an FP_ROUND_INREG. 2323 Result = LegalizeOp(Node->getOperand(0)); 2324 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2325 DAG.getValueType(VT)); 2326 break; 2327 } 2328 break; 2329 2330 case ISD::SINT_TO_FP: 2331 case ISD::UINT_TO_FP: 2332 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2333 case Legal: 2334 Result = LegalizeOp(Node->getOperand(0)); 2335 // No extra round required here. 2336 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2337 break; 2338 2339 case Promote: 2340 Result = PromoteOp(Node->getOperand(0)); 2341 if (Node->getOpcode() == ISD::SINT_TO_FP) 2342 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2343 Result, 2344 DAG.getValueType(Node->getOperand(0).getValueType())); 2345 else 2346 Result = DAG.getZeroExtendInReg(Result, 2347 Node->getOperand(0).getValueType()); 2348 // No extra round required here. 2349 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2350 break; 2351 case Expand: 2352 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2353 Node->getOperand(0)); 2354 // Round if we cannot tolerate excess precision. 2355 if (NoExcessFPPrecision) 2356 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2357 DAG.getValueType(VT)); 2358 break; 2359 } 2360 break; 2361 2362 case ISD::FP_TO_SINT: 2363 case ISD::FP_TO_UINT: 2364 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2365 case Legal: 2366 Tmp1 = LegalizeOp(Node->getOperand(0)); 2367 break; 2368 case Promote: 2369 // The input result is prerounded, so we don't have to do anything 2370 // special. 2371 Tmp1 = PromoteOp(Node->getOperand(0)); 2372 break; 2373 case Expand: 2374 assert(0 && "not implemented"); 2375 } 2376 // If we're promoting a UINT to a larger size, check to see if the new node 2377 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2378 // we can use that instead. This allows us to generate better code for 2379 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2380 // legal, such as PowerPC. 2381 if (Node->getOpcode() == ISD::FP_TO_UINT && 2382 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2383 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2384 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2385 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2386 } else { 2387 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2388 } 2389 break; 2390 2391 case ISD::FABS: 2392 case ISD::FNEG: 2393 Tmp1 = PromoteOp(Node->getOperand(0)); 2394 assert(Tmp1.getValueType() == NVT); 2395 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2396 // NOTE: we do not have to do any extra rounding here for 2397 // NoExcessFPPrecision, because we know the input will have the appropriate 2398 // precision, and these operations don't modify precision at all. 2399 break; 2400 2401 case ISD::FSQRT: 2402 case ISD::FSIN: 2403 case ISD::FCOS: 2404 Tmp1 = PromoteOp(Node->getOperand(0)); 2405 assert(Tmp1.getValueType() == NVT); 2406 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2407 if(NoExcessFPPrecision) 2408 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2409 DAG.getValueType(VT)); 2410 break; 2411 2412 case ISD::AND: 2413 case ISD::OR: 2414 case ISD::XOR: 2415 case ISD::ADD: 2416 case ISD::SUB: 2417 case ISD::MUL: 2418 // The input may have strange things in the top bits of the registers, but 2419 // these operations don't care. They may have weird bits going out, but 2420 // that too is okay if they are integer operations. 2421 Tmp1 = PromoteOp(Node->getOperand(0)); 2422 Tmp2 = PromoteOp(Node->getOperand(1)); 2423 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2424 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2425 break; 2426 case ISD::FADD: 2427 case ISD::FSUB: 2428 case ISD::FMUL: 2429 // The input may have strange things in the top bits of the registers, but 2430 // these operations don't care. 2431 Tmp1 = PromoteOp(Node->getOperand(0)); 2432 Tmp2 = PromoteOp(Node->getOperand(1)); 2433 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2434 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2435 2436 // Floating point operations will give excess precision that we may not be 2437 // able to tolerate. If we DO allow excess precision, just leave it, 2438 // otherwise excise it. 2439 // FIXME: Why would we need to round FP ops more than integer ones? 2440 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2441 if (NoExcessFPPrecision) 2442 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2443 DAG.getValueType(VT)); 2444 break; 2445 2446 case ISD::SDIV: 2447 case ISD::SREM: 2448 // These operators require that their input be sign extended. 2449 Tmp1 = PromoteOp(Node->getOperand(0)); 2450 Tmp2 = PromoteOp(Node->getOperand(1)); 2451 if (MVT::isInteger(NVT)) { 2452 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2453 DAG.getValueType(VT)); 2454 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2455 DAG.getValueType(VT)); 2456 } 2457 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2458 2459 // Perform FP_ROUND: this is probably overly pessimistic. 2460 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2461 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2462 DAG.getValueType(VT)); 2463 break; 2464 case ISD::FDIV: 2465 case ISD::FREM: 2466 // These operators require that their input be fp extended. 2467 Tmp1 = PromoteOp(Node->getOperand(0)); 2468 Tmp2 = PromoteOp(Node->getOperand(1)); 2469 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2470 2471 // Perform FP_ROUND: this is probably overly pessimistic. 2472 if (NoExcessFPPrecision) 2473 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2474 DAG.getValueType(VT)); 2475 break; 2476 2477 case ISD::UDIV: 2478 case ISD::UREM: 2479 // These operators require that their input be zero extended. 2480 Tmp1 = PromoteOp(Node->getOperand(0)); 2481 Tmp2 = PromoteOp(Node->getOperand(1)); 2482 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2483 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2484 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2485 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2486 break; 2487 2488 case ISD::SHL: 2489 Tmp1 = PromoteOp(Node->getOperand(0)); 2490 Tmp2 = LegalizeOp(Node->getOperand(1)); 2491 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 2492 break; 2493 case ISD::SRA: 2494 // The input value must be properly sign extended. 2495 Tmp1 = PromoteOp(Node->getOperand(0)); 2496 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2497 DAG.getValueType(VT)); 2498 Tmp2 = LegalizeOp(Node->getOperand(1)); 2499 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 2500 break; 2501 case ISD::SRL: 2502 // The input value must be properly zero extended. 2503 Tmp1 = PromoteOp(Node->getOperand(0)); 2504 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2505 Tmp2 = LegalizeOp(Node->getOperand(1)); 2506 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 2507 break; 2508 case ISD::LOAD: 2509 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2510 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2511 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2, 2512 Node->getOperand(2), VT); 2513 // Remember that we legalized the chain. 2514 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2515 break; 2516 case ISD::SEXTLOAD: 2517 case ISD::ZEXTLOAD: 2518 case ISD::EXTLOAD: 2519 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2520 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2521 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2, 2522 Node->getOperand(2), 2523 cast<VTSDNode>(Node->getOperand(3))->getVT()); 2524 // Remember that we legalized the chain. 2525 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2526 break; 2527 case ISD::SELECT: 2528 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2529 case Expand: assert(0 && "It's impossible to expand bools"); 2530 case Legal: 2531 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 2532 break; 2533 case Promote: 2534 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2535 break; 2536 } 2537 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 2538 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 2539 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 2540 break; 2541 case ISD::SELECT_CC: 2542 Tmp2 = PromoteOp(Node->getOperand(2)); // True 2543 Tmp3 = PromoteOp(Node->getOperand(3)); // False 2544 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 2545 Node->getOperand(1), Tmp2, Tmp3, 2546 Node->getOperand(4)); 2547 break; 2548 case ISD::TAILCALL: 2549 case ISD::CALL: { 2550 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2551 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 2552 2553 std::vector<SDOperand> Ops; 2554 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 2555 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2556 2557 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 2558 "Can only promote single result calls"); 2559 std::vector<MVT::ValueType> RetTyVTs; 2560 RetTyVTs.reserve(2); 2561 RetTyVTs.push_back(NVT); 2562 RetTyVTs.push_back(MVT::Other); 2563 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 2564 Node->getOpcode() == ISD::TAILCALL); 2565 Result = SDOperand(NC, 0); 2566 2567 // Insert the new chain mapping. 2568 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2569 break; 2570 } 2571 case ISD::CTPOP: 2572 case ISD::CTTZ: 2573 case ISD::CTLZ: 2574 Tmp1 = Node->getOperand(0); 2575 //Zero extend the argument 2576 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2577 // Perform the larger operation, then subtract if needed. 2578 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2579 switch(Node->getOpcode()) 2580 { 2581 case ISD::CTPOP: 2582 Result = Tmp1; 2583 break; 2584 case ISD::CTTZ: 2585 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2586 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2587 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 2588 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2589 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 2590 break; 2591 case ISD::CTLZ: 2592 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2593 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2594 DAG.getConstant(getSizeInBits(NVT) - 2595 getSizeInBits(VT), NVT)); 2596 break; 2597 } 2598 break; 2599 } 2600 2601 assert(Result.Val && "Didn't set a result!"); 2602 AddPromotedOperand(Op, Result); 2603 return Result; 2604} 2605 2606/// ExpandAddSub - Find a clever way to expand this add operation into 2607/// subcomponents. 2608void SelectionDAGLegalize:: 2609ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 2610 SDOperand &Lo, SDOperand &Hi) { 2611 // Expand the subcomponents. 2612 SDOperand LHSL, LHSH, RHSL, RHSH; 2613 ExpandOp(LHS, LHSL, LHSH); 2614 ExpandOp(RHS, RHSL, RHSH); 2615 2616 std::vector<SDOperand> Ops; 2617 Ops.push_back(LHSL); 2618 Ops.push_back(LHSH); 2619 Ops.push_back(RHSL); 2620 Ops.push_back(RHSH); 2621 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2622 Lo = DAG.getNode(NodeOp, VTs, Ops); 2623 Hi = Lo.getValue(1); 2624} 2625 2626void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 2627 SDOperand Op, SDOperand Amt, 2628 SDOperand &Lo, SDOperand &Hi) { 2629 // Expand the subcomponents. 2630 SDOperand LHSL, LHSH; 2631 ExpandOp(Op, LHSL, LHSH); 2632 2633 std::vector<SDOperand> Ops; 2634 Ops.push_back(LHSL); 2635 Ops.push_back(LHSH); 2636 Ops.push_back(Amt); 2637 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2638 Lo = DAG.getNode(NodeOp, VTs, Ops); 2639 Hi = Lo.getValue(1); 2640} 2641 2642 2643/// ExpandShift - Try to find a clever way to expand this shift operation out to 2644/// smaller elements. If we can't find a way that is more efficient than a 2645/// libcall on this target, return false. Otherwise, return true with the 2646/// low-parts expanded into Lo and Hi. 2647bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 2648 SDOperand &Lo, SDOperand &Hi) { 2649 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 2650 "This is not a shift!"); 2651 2652 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 2653 SDOperand ShAmt = LegalizeOp(Amt); 2654 MVT::ValueType ShTy = ShAmt.getValueType(); 2655 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 2656 unsigned NVTBits = MVT::getSizeInBits(NVT); 2657 2658 // Handle the case when Amt is an immediate. Other cases are currently broken 2659 // and are disabled. 2660 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 2661 unsigned Cst = CN->getValue(); 2662 // Expand the incoming operand to be shifted, so that we have its parts 2663 SDOperand InL, InH; 2664 ExpandOp(Op, InL, InH); 2665 switch(Opc) { 2666 case ISD::SHL: 2667 if (Cst > VTBits) { 2668 Lo = DAG.getConstant(0, NVT); 2669 Hi = DAG.getConstant(0, NVT); 2670 } else if (Cst > NVTBits) { 2671 Lo = DAG.getConstant(0, NVT); 2672 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 2673 } else if (Cst == NVTBits) { 2674 Lo = DAG.getConstant(0, NVT); 2675 Hi = InL; 2676 } else { 2677 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 2678 Hi = DAG.getNode(ISD::OR, NVT, 2679 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 2680 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 2681 } 2682 return true; 2683 case ISD::SRL: 2684 if (Cst > VTBits) { 2685 Lo = DAG.getConstant(0, NVT); 2686 Hi = DAG.getConstant(0, NVT); 2687 } else if (Cst > NVTBits) { 2688 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 2689 Hi = DAG.getConstant(0, NVT); 2690 } else if (Cst == NVTBits) { 2691 Lo = InH; 2692 Hi = DAG.getConstant(0, NVT); 2693 } else { 2694 Lo = DAG.getNode(ISD::OR, NVT, 2695 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2696 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2697 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 2698 } 2699 return true; 2700 case ISD::SRA: 2701 if (Cst > VTBits) { 2702 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 2703 DAG.getConstant(NVTBits-1, ShTy)); 2704 } else if (Cst > NVTBits) { 2705 Lo = DAG.getNode(ISD::SRA, NVT, InH, 2706 DAG.getConstant(Cst-NVTBits, ShTy)); 2707 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2708 DAG.getConstant(NVTBits-1, ShTy)); 2709 } else if (Cst == NVTBits) { 2710 Lo = InH; 2711 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2712 DAG.getConstant(NVTBits-1, ShTy)); 2713 } else { 2714 Lo = DAG.getNode(ISD::OR, NVT, 2715 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2716 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2717 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 2718 } 2719 return true; 2720 } 2721 } 2722 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 2723 // so disable it for now. Currently targets are handling this via SHL_PARTS 2724 // and friends. 2725 return false; 2726 2727 // If we have an efficient select operation (or if the selects will all fold 2728 // away), lower to some complex code, otherwise just emit the libcall. 2729 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt)) 2730 return false; 2731 2732 SDOperand InL, InH; 2733 ExpandOp(Op, InL, InH); 2734 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 2735 DAG.getConstant(NVTBits, ShTy), ShAmt); 2736 2737 // Compare the unmasked shift amount against 32. 2738 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt, 2739 DAG.getConstant(NVTBits, ShTy), ISD::SETGE); 2740 2741 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 2742 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 2743 DAG.getConstant(NVTBits-1, ShTy)); 2744 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 2745 DAG.getConstant(NVTBits-1, ShTy)); 2746 } 2747 2748 if (Opc == ISD::SHL) { 2749 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 2750 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 2751 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 2752 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 2753 2754 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2755 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 2756 } else { 2757 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 2758 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt, 2759 DAG.getConstant(32, ShTy), 2760 ISD::SETEQ), 2761 DAG.getConstant(0, NVT), 2762 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 2763 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 2764 HiLoPart, 2765 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 2766 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 2767 2768 SDOperand HiPart; 2769 if (Opc == ISD::SRA) 2770 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 2771 DAG.getConstant(NVTBits-1, ShTy)); 2772 else 2773 HiPart = DAG.getConstant(0, NVT); 2774 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2775 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 2776 } 2777 return true; 2778} 2779 2780/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 2781/// NodeDepth) node that is an CallSeqStart operation and occurs later than 2782/// Found. 2783static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) { 2784 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 2785 2786 // If we found an CALLSEQ_START, we already know this node occurs later 2787 // than the Found node. Just remember this node and return. 2788 if (Node->getOpcode() == ISD::CALLSEQ_START) { 2789 Found = Node; 2790 return; 2791 } 2792 2793 // Otherwise, scan the operands of Node to see if any of them is a call. 2794 assert(Node->getNumOperands() != 0 && 2795 "All leaves should have depth equal to the entry node!"); 2796 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 2797 FindLatestCallSeqStart(Node->getOperand(i).Val, Found); 2798 2799 // Tail recurse for the last iteration. 2800 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 2801 Found); 2802} 2803 2804 2805/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 2806/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 2807/// than Found. 2808static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 2809 std::set<SDNode*> &Visited) { 2810 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 2811 !Visited.insert(Node).second) return; 2812 2813 // If we found an CALLSEQ_END, we already know this node occurs earlier 2814 // than the Found node. Just remember this node and return. 2815 if (Node->getOpcode() == ISD::CALLSEQ_END) { 2816 Found = Node; 2817 return; 2818 } 2819 2820 // Otherwise, scan the operands of Node to see if any of them is a call. 2821 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 2822 if (UI == E) return; 2823 for (--E; UI != E; ++UI) 2824 FindEarliestCallSeqEnd(*UI, Found, Visited); 2825 2826 // Tail recurse for the last iteration. 2827 FindEarliestCallSeqEnd(*UI, Found, Visited); 2828} 2829 2830/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 2831/// find the CALLSEQ_END node that terminates the call sequence. 2832static SDNode *FindCallSeqEnd(SDNode *Node) { 2833 if (Node->getOpcode() == ISD::CALLSEQ_END) 2834 return Node; 2835 if (Node->use_empty()) 2836 return 0; // No CallSeqEnd 2837 2838 SDOperand TheChain(Node, Node->getNumValues()-1); 2839 if (TheChain.getValueType() != MVT::Other) 2840 TheChain = SDOperand(Node, 0); 2841 if (TheChain.getValueType() != MVT::Other) 2842 return 0; 2843 2844 for (SDNode::use_iterator UI = Node->use_begin(), 2845 E = Node->use_end(); UI != E; ++UI) { 2846 2847 // Make sure to only follow users of our token chain. 2848 SDNode *User = *UI; 2849 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 2850 if (User->getOperand(i) == TheChain) 2851 if (SDNode *Result = FindCallSeqEnd(User)) 2852 return Result; 2853 } 2854 return 0; 2855} 2856 2857/// FindCallSeqStart - Given a chained node that is part of a call sequence, 2858/// find the CALLSEQ_START node that initiates the call sequence. 2859static SDNode *FindCallSeqStart(SDNode *Node) { 2860 assert(Node && "Didn't find callseq_start for a call??"); 2861 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 2862 2863 assert(Node->getOperand(0).getValueType() == MVT::Other && 2864 "Node doesn't have a token chain argument!"); 2865 return FindCallSeqStart(Node->getOperand(0).Val); 2866} 2867 2868 2869/// FindInputOutputChains - If we are replacing an operation with a call we need 2870/// to find the call that occurs before and the call that occurs after it to 2871/// properly serialize the calls in the block. The returned operand is the 2872/// input chain value for the new call (e.g. the entry node or the previous 2873/// call), and OutChain is set to be the chain node to update to point to the 2874/// end of the call chain. 2875static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 2876 SDOperand Entry) { 2877 SDNode *LatestCallSeqStart = Entry.Val; 2878 SDNode *LatestCallSeqEnd = 0; 2879 FindLatestCallSeqStart(OpNode, LatestCallSeqStart); 2880 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 2881 2882 // It is possible that no ISD::CALLSEQ_START was found because there is no 2883 // previous call in the function. LatestCallStackDown may in that case be 2884 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 2885 // unless LatestCallStackDown is an CALLSEQ_START. 2886 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 2887 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 2888 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 2889 } else { 2890 LatestCallSeqEnd = Entry.Val; 2891 } 2892 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 2893 2894 // Finally, find the first call that this must come before, first we find the 2895 // CallSeqEnd that ends the call. 2896 OutChain = 0; 2897 std::set<SDNode*> Visited; 2898 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 2899 2900 // If we found one, translate from the adj up to the callseq_start. 2901 if (OutChain) 2902 OutChain = FindCallSeqStart(OutChain); 2903 2904 return SDOperand(LatestCallSeqEnd, 0); 2905} 2906 2907/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 2908void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 2909 SDNode *OutChain) { 2910 // Nothing to splice it into? 2911 if (OutChain == 0) return; 2912 2913 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 2914 //OutChain->dump(); 2915 2916 // Form a token factor node merging the old inval and the new inval. 2917 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 2918 OutChain->getOperand(0)); 2919 // Change the node to refer to the new token. 2920 OutChain->setAdjCallChain(InToken); 2921} 2922 2923 2924// ExpandLibCall - Expand a node into a call to a libcall. If the result value 2925// does not fit into a register, return the lo part and set the hi part to the 2926// by-reg argument. If it does fit into a single register, return the result 2927// and leave the Hi part unset. 2928SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 2929 SDOperand &Hi) { 2930 SDNode *OutChain; 2931 SDOperand InChain = FindInputOutputChains(Node, OutChain, 2932 DAG.getEntryNode()); 2933 if (InChain.Val == 0) 2934 InChain = DAG.getEntryNode(); 2935 2936 TargetLowering::ArgListTy Args; 2937 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2938 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 2939 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 2940 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 2941 } 2942 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 2943 2944 // Splice the libcall in wherever FindInputOutputChains tells us to. 2945 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 2946 std::pair<SDOperand,SDOperand> CallInfo = 2947 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 2948 Callee, Args, DAG); 2949 2950 SDOperand Result; 2951 switch (getTypeAction(CallInfo.first.getValueType())) { 2952 default: assert(0 && "Unknown thing"); 2953 case Legal: 2954 Result = CallInfo.first; 2955 break; 2956 case Promote: 2957 assert(0 && "Cannot promote this yet!"); 2958 case Expand: 2959 ExpandOp(CallInfo.first, Result, Hi); 2960 CallInfo.second = LegalizeOp(CallInfo.second); 2961 break; 2962 } 2963 2964 SpliceCallInto(CallInfo.second, OutChain); 2965 NeedsAnotherIteration = true; 2966 return Result; 2967} 2968 2969 2970/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 2971/// destination type is legal. 2972SDOperand SelectionDAGLegalize:: 2973ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 2974 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 2975 assert(getTypeAction(Source.getValueType()) == Expand && 2976 "This is not an expansion!"); 2977 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 2978 2979 if (!isSigned) { 2980 assert(Source.getValueType() == MVT::i64 && 2981 "This only works for 64-bit -> FP"); 2982 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 2983 // incoming integer is set. To handle this, we dynamically test to see if 2984 // it is set, and, if so, add a fudge factor. 2985 SDOperand Lo, Hi; 2986 ExpandOp(Source, Lo, Hi); 2987 2988 // If this is unsigned, and not supported, first perform the conversion to 2989 // signed, then adjust the result if the sign bit is set. 2990 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 2991 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 2992 2993 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 2994 DAG.getConstant(0, Hi.getValueType()), 2995 ISD::SETLT); 2996 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 2997 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 2998 SignSet, Four, Zero); 2999 uint64_t FF = 0x5f800000ULL; 3000 if (TLI.isLittleEndian()) FF <<= 32; 3001 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3002 3003 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3004 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3005 SDOperand FudgeInReg; 3006 if (DestTy == MVT::f32) 3007 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3008 DAG.getSrcValue(NULL)); 3009 else { 3010 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3011 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3012 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 3013 } 3014 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3015 } 3016 3017 // Check to see if the target has a custom way to lower this. If so, use it. 3018 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3019 default: assert(0 && "This action not implemented for this operation!"); 3020 case TargetLowering::Legal: 3021 case TargetLowering::Expand: 3022 break; // This case is handled below. 3023 case TargetLowering::Custom: { 3024 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3025 Source), DAG); 3026 if (NV.Val) 3027 return LegalizeOp(NV); 3028 break; // The target decided this was legal after all 3029 } 3030 } 3031 3032 // Expand the source, then glue it back together for the call. We must expand 3033 // the source in case it is shared (this pass of legalize must traverse it). 3034 SDOperand SrcLo, SrcHi; 3035 ExpandOp(Source, SrcLo, SrcHi); 3036 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3037 3038 SDNode *OutChain = 0; 3039 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 3040 DAG.getEntryNode()); 3041 const char *FnName = 0; 3042 if (DestTy == MVT::f32) 3043 FnName = "__floatdisf"; 3044 else { 3045 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3046 FnName = "__floatdidf"; 3047 } 3048 3049 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 3050 3051 TargetLowering::ArgListTy Args; 3052 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 3053 3054 Args.push_back(std::make_pair(Source, ArgTy)); 3055 3056 // We don't care about token chains for libcalls. We just use the entry 3057 // node as our input and ignore the output chain. This allows us to place 3058 // calls wherever we need them to satisfy data dependences. 3059 const Type *RetTy = MVT::getTypeForValueType(DestTy); 3060 3061 std::pair<SDOperand,SDOperand> CallResult = 3062 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 3063 Callee, Args, DAG); 3064 3065 SpliceCallInto(CallResult.second, OutChain); 3066 return CallResult.first; 3067} 3068 3069 3070 3071/// ExpandOp - Expand the specified SDOperand into its two component pieces 3072/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 3073/// LegalizeNodes map is filled in for any results that are not expanded, the 3074/// ExpandedNodes map is filled in for any results that are expanded, and the 3075/// Lo/Hi values are returned. 3076void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 3077 MVT::ValueType VT = Op.getValueType(); 3078 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3079 SDNode *Node = Op.Val; 3080 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 3081 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 3082 "Cannot expand FP values!"); 3083 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 3084 "Cannot expand to FP value or to larger int value!"); 3085 3086 // See if we already expanded it. 3087 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 3088 = ExpandedNodes.find(Op); 3089 if (I != ExpandedNodes.end()) { 3090 Lo = I->second.first; 3091 Hi = I->second.second; 3092 return; 3093 } 3094 3095 // Expanding to multiple registers needs to perform an optimization step, and 3096 // is not careful to avoid operations the target does not support. Make sure 3097 // that all generated operations are legalized in the next iteration. 3098 NeedsAnotherIteration = true; 3099 3100 switch (Node->getOpcode()) { 3101 case ISD::CopyFromReg: 3102 assert(0 && "CopyFromReg must be legal!"); 3103 default: 3104 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 3105 assert(0 && "Do not know how to expand this operator!"); 3106 abort(); 3107 case ISD::UNDEF: 3108 Lo = DAG.getNode(ISD::UNDEF, NVT); 3109 Hi = DAG.getNode(ISD::UNDEF, NVT); 3110 break; 3111 case ISD::Constant: { 3112 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 3113 Lo = DAG.getConstant(Cst, NVT); 3114 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3115 break; 3116 } 3117 3118 case ISD::BUILD_PAIR: 3119 // Legalize both operands. FIXME: in the future we should handle the case 3120 // where the two elements are not legal. 3121 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 3122 Lo = LegalizeOp(Node->getOperand(0)); 3123 Hi = LegalizeOp(Node->getOperand(1)); 3124 break; 3125 3126 case ISD::CTPOP: 3127 ExpandOp(Node->getOperand(0), Lo, Hi); 3128 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3129 DAG.getNode(ISD::CTPOP, NVT, Lo), 3130 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3131 Hi = DAG.getConstant(0, NVT); 3132 break; 3133 3134 case ISD::CTLZ: { 3135 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3136 ExpandOp(Node->getOperand(0), Lo, Hi); 3137 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3138 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3139 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3140 ISD::SETNE); 3141 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3142 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3143 3144 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3145 Hi = DAG.getConstant(0, NVT); 3146 break; 3147 } 3148 3149 case ISD::CTTZ: { 3150 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3151 ExpandOp(Node->getOperand(0), Lo, Hi); 3152 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3153 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3154 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3155 ISD::SETNE); 3156 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3157 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3158 3159 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3160 Hi = DAG.getConstant(0, NVT); 3161 break; 3162 } 3163 3164 case ISD::LOAD: { 3165 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3166 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3167 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3168 3169 // Increment the pointer to the other half. 3170 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3171 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3172 getIntPtrConstant(IncrementSize)); 3173 //Is this safe? declaring that the two parts of the split load 3174 //are from the same instruction? 3175 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3176 3177 // Build a factor node to remember that this load is independent of the 3178 // other one. 3179 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3180 Hi.getValue(1)); 3181 3182 // Remember that we legalized the chain. 3183 AddLegalizedOperand(Op.getValue(1), TF); 3184 if (!TLI.isLittleEndian()) 3185 std::swap(Lo, Hi); 3186 break; 3187 } 3188 case ISD::VLOAD: { 3189 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3190 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3191 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3192 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3193 3194 // If we only have two elements, turn into a pair of scalar loads. 3195 // FIXME: handle case where a vector of two elements is fine, such as 3196 // 2 x double on SSE2. 3197 if (NumElements == 2) { 3198 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3199 // Increment the pointer to the other half. 3200 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8; 3201 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3202 getIntPtrConstant(IncrementSize)); 3203 //Is this safe? declaring that the two parts of the split load 3204 //are from the same instruction? 3205 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3206 } else { 3207 NumElements /= 2; // Split the vector in half 3208 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3209 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8; 3210 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3211 getIntPtrConstant(IncrementSize)); 3212 //Is this safe? declaring that the two parts of the split load 3213 //are from the same instruction? 3214 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3215 } 3216 3217 // Build a factor node to remember that this load is independent of the 3218 // other one. 3219 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3220 Hi.getValue(1)); 3221 3222 // Remember that we legalized the chain. 3223 AddLegalizedOperand(Op.getValue(1), TF); 3224 if (!TLI.isLittleEndian()) 3225 std::swap(Lo, Hi); 3226 break; 3227 } 3228 case ISD::VADD: 3229 case ISD::VSUB: 3230 case ISD::VMUL: { 3231 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3232 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3233 SDOperand LL, LH, RL, RH; 3234 3235 ExpandOp(Node->getOperand(0), LL, LH); 3236 ExpandOp(Node->getOperand(1), RL, RH); 3237 3238 // If we only have two elements, turn into a pair of scalar loads. 3239 // FIXME: handle case where a vector of two elements is fine, such as 3240 // 2 x double on SSE2. 3241 if (NumElements == 2) { 3242 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT); 3243 Lo = DAG.getNode(Opc, EVT, LL, RL); 3244 Hi = DAG.getNode(Opc, EVT, LH, RH); 3245 } else { 3246 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2), 3247 LL.getOperand(3)); 3248 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2), 3249 LH.getOperand(3)); 3250 } 3251 break; 3252 } 3253 case ISD::TAILCALL: 3254 case ISD::CALL: { 3255 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3256 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 3257 3258 bool Changed = false; 3259 std::vector<SDOperand> Ops; 3260 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 3261 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3262 Changed |= Ops.back() != Node->getOperand(i); 3263 } 3264 3265 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 3266 "Can only expand a call once so far, not i64 -> i16!"); 3267 3268 std::vector<MVT::ValueType> RetTyVTs; 3269 RetTyVTs.reserve(3); 3270 RetTyVTs.push_back(NVT); 3271 RetTyVTs.push_back(NVT); 3272 RetTyVTs.push_back(MVT::Other); 3273 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops, 3274 Node->getOpcode() == ISD::TAILCALL); 3275 Lo = SDOperand(NC, 0); 3276 Hi = SDOperand(NC, 1); 3277 3278 // Insert the new chain mapping. 3279 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 3280 break; 3281 } 3282 case ISD::AND: 3283 case ISD::OR: 3284 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 3285 SDOperand LL, LH, RL, RH; 3286 ExpandOp(Node->getOperand(0), LL, LH); 3287 ExpandOp(Node->getOperand(1), RL, RH); 3288 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 3289 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 3290 break; 3291 } 3292 case ISD::SELECT: { 3293 SDOperand C, LL, LH, RL, RH; 3294 3295 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3296 case Expand: assert(0 && "It's impossible to expand bools"); 3297 case Legal: 3298 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 3299 break; 3300 case Promote: 3301 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 3302 break; 3303 } 3304 ExpandOp(Node->getOperand(1), LL, LH); 3305 ExpandOp(Node->getOperand(2), RL, RH); 3306 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 3307 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 3308 break; 3309 } 3310 case ISD::SELECT_CC: { 3311 SDOperand TL, TH, FL, FH; 3312 ExpandOp(Node->getOperand(2), TL, TH); 3313 ExpandOp(Node->getOperand(3), FL, FH); 3314 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3315 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3316 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3317 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3318 Lo = LegalizeOp(Lo); 3319 Hi = LegalizeOp(Hi); 3320 break; 3321 } 3322 case ISD::SEXTLOAD: { 3323 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3324 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3325 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3326 3327 if (EVT == NVT) 3328 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3329 else 3330 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3331 EVT); 3332 3333 // Remember that we legalized the chain. 3334 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3335 3336 // The high part is obtained by SRA'ing all but one of the bits of the lo 3337 // part. 3338 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3339 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3340 TLI.getShiftAmountTy())); 3341 Lo = LegalizeOp(Lo); 3342 Hi = LegalizeOp(Hi); 3343 break; 3344 } 3345 case ISD::ZEXTLOAD: { 3346 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3347 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3348 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3349 3350 if (EVT == NVT) 3351 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3352 else 3353 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3354 EVT); 3355 3356 // Remember that we legalized the chain. 3357 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3358 3359 // The high part is just a zero. 3360 Hi = LegalizeOp(DAG.getConstant(0, NVT)); 3361 Lo = LegalizeOp(Lo); 3362 break; 3363 } 3364 case ISD::EXTLOAD: { 3365 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3366 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3367 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3368 3369 if (EVT == NVT) 3370 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3371 else 3372 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3373 EVT); 3374 3375 // Remember that we legalized the chain. 3376 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3377 3378 // The high part is undefined. 3379 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT)); 3380 Lo = LegalizeOp(Lo); 3381 break; 3382 } 3383 case ISD::ANY_EXTEND: { 3384 SDOperand In; 3385 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3386 case Expand: assert(0 && "expand-expand not implemented yet!"); 3387 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3388 case Promote: 3389 In = PromoteOp(Node->getOperand(0)); 3390 break; 3391 } 3392 3393 // The low part is any extension of the input (which degenerates to a copy). 3394 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In); 3395 // The high part is undefined. 3396 Hi = DAG.getNode(ISD::UNDEF, NVT); 3397 break; 3398 } 3399 case ISD::SIGN_EXTEND: { 3400 SDOperand In; 3401 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3402 case Expand: assert(0 && "expand-expand not implemented yet!"); 3403 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3404 case Promote: 3405 In = PromoteOp(Node->getOperand(0)); 3406 // Emit the appropriate sign_extend_inreg to get the value we want. 3407 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 3408 DAG.getValueType(Node->getOperand(0).getValueType())); 3409 break; 3410 } 3411 3412 // The low part is just a sign extension of the input (which degenerates to 3413 // a copy). 3414 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 3415 3416 // The high part is obtained by SRA'ing all but one of the bits of the lo 3417 // part. 3418 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3419 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3420 TLI.getShiftAmountTy())); 3421 break; 3422 } 3423 case ISD::ZERO_EXTEND: { 3424 SDOperand In; 3425 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3426 case Expand: assert(0 && "expand-expand not implemented yet!"); 3427 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3428 case Promote: 3429 In = PromoteOp(Node->getOperand(0)); 3430 // Emit the appropriate zero_extend_inreg to get the value we want. 3431 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 3432 break; 3433 } 3434 3435 // The low part is just a zero extension of the input (which degenerates to 3436 // a copy). 3437 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 3438 3439 // The high part is just a zero. 3440 Hi = DAG.getConstant(0, NVT); 3441 break; 3442 } 3443 3444 case ISD::READCYCLECOUNTER: { 3445 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 3446 TargetLowering::Custom && 3447 "Must custom expand ReadCycleCounter"); 3448 SDOperand T = TLI.LowerOperation(Op, DAG); 3449 assert(T.Val && "Node must be custom expanded!"); 3450 Lo = LegalizeOp(T.getValue(0)); 3451 Hi = LegalizeOp(T.getValue(1)); 3452 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 3453 LegalizeOp(T.getValue(2))); 3454 break; 3455 } 3456 3457 // These operators cannot be expanded directly, emit them as calls to 3458 // library functions. 3459 case ISD::FP_TO_SINT: 3460 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 3461 SDOperand Op; 3462 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3463 case Expand: assert(0 && "cannot expand FP!"); 3464 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3465 case Promote: Op = PromoteOp(Node->getOperand(0)); break; 3466 } 3467 3468 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 3469 3470 // Now that the custom expander is done, expand the result, which is still 3471 // VT. 3472 if (Op.Val) { 3473 ExpandOp(Op, Lo, Hi); 3474 break; 3475 } 3476 } 3477 3478 if (Node->getOperand(0).getValueType() == MVT::f32) 3479 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 3480 else 3481 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 3482 break; 3483 3484 case ISD::FP_TO_UINT: 3485 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 3486 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, 3487 LegalizeOp(Node->getOperand(0))); 3488 // Now that the custom expander is done, expand the result, which is still 3489 // VT. 3490 Op = TLI.LowerOperation(Op, DAG); 3491 if (Op.Val) { 3492 ExpandOp(Op, Lo, Hi); 3493 break; 3494 } 3495 } 3496 3497 if (Node->getOperand(0).getValueType() == MVT::f32) 3498 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 3499 else 3500 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 3501 break; 3502 3503 case ISD::SHL: 3504 // If the target wants custom lowering, do so. 3505 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 3506 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), 3507 LegalizeOp(Node->getOperand(1))); 3508 Op = TLI.LowerOperation(Op, DAG); 3509 if (Op.Val) { 3510 // Now that the custom expander is done, expand the result, which is 3511 // still VT. 3512 ExpandOp(Op, Lo, Hi); 3513 break; 3514 } 3515 } 3516 3517 // If we can emit an efficient shift operation, do so now. 3518 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3519 break; 3520 3521 // If this target supports SHL_PARTS, use it. 3522 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) { 3523 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 3524 Lo, Hi); 3525 break; 3526 } 3527 3528 // Otherwise, emit a libcall. 3529 Lo = ExpandLibCall("__ashldi3", Node, Hi); 3530 break; 3531 3532 case ISD::SRA: 3533 // If the target wants custom lowering, do so. 3534 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 3535 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), 3536 LegalizeOp(Node->getOperand(1))); 3537 Op = TLI.LowerOperation(Op, DAG); 3538 if (Op.Val) { 3539 // Now that the custom expander is done, expand the result, which is 3540 // still VT. 3541 ExpandOp(Op, Lo, Hi); 3542 break; 3543 } 3544 } 3545 3546 // If we can emit an efficient shift operation, do so now. 3547 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3548 break; 3549 3550 // If this target supports SRA_PARTS, use it. 3551 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) { 3552 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 3553 Lo, Hi); 3554 break; 3555 } 3556 3557 // Otherwise, emit a libcall. 3558 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 3559 break; 3560 case ISD::SRL: 3561 // If the target wants custom lowering, do so. 3562 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 3563 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), 3564 LegalizeOp(Node->getOperand(1))); 3565 Op = TLI.LowerOperation(Op, DAG); 3566 if (Op.Val) { 3567 // Now that the custom expander is done, expand the result, which is 3568 // still VT. 3569 ExpandOp(Op, Lo, Hi); 3570 break; 3571 } 3572 } 3573 3574 // If we can emit an efficient shift operation, do so now. 3575 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3576 break; 3577 3578 // If this target supports SRL_PARTS, use it. 3579 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) { 3580 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 3581 Lo, Hi); 3582 break; 3583 } 3584 3585 // Otherwise, emit a libcall. 3586 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 3587 break; 3588 3589 case ISD::ADD: 3590 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 3591 Lo, Hi); 3592 break; 3593 case ISD::SUB: 3594 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 3595 Lo, Hi); 3596 break; 3597 case ISD::MUL: { 3598 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 3599 SDOperand LL, LH, RL, RH; 3600 ExpandOp(Node->getOperand(0), LL, LH); 3601 ExpandOp(Node->getOperand(1), RL, RH); 3602 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 3603 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 3604 // extended the sign bit of the low half through the upper half, and if so 3605 // emit a MULHS instead of the alternate sequence that is valid for any 3606 // i64 x i64 multiply. 3607 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 3608 // is RH an extension of the sign bit of RL? 3609 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 3610 RH.getOperand(1).getOpcode() == ISD::Constant && 3611 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 3612 // is LH an extension of the sign bit of LL? 3613 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 3614 LH.getOperand(1).getOpcode() == ISD::Constant && 3615 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 3616 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 3617 } else { 3618 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 3619 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 3620 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 3621 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 3622 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 3623 } 3624 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 3625 } else { 3626 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 3627 } 3628 break; 3629 } 3630 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 3631 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 3632 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 3633 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 3634 } 3635 3636 // Remember in a map if the values will be reused later. 3637 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 3638 std::make_pair(Lo, Hi))).second; 3639 assert(isNew && "Value already expanded?!?"); 3640} 3641 3642 3643// SelectionDAG::Legalize - This is the entry point for the file. 3644// 3645void SelectionDAG::Legalize() { 3646 /// run - This is the main entry point to this class. 3647 /// 3648 SelectionDAGLegalize(*this).Run(); 3649} 3650 3651