LegalizeDAG.cpp revision b215823aff08e6a519995bedf3b27b62ed862e9a
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetFrameInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/Target/TargetSubtarget.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/SmallPtrSet.h" 35#include <map> 36using namespace llvm; 37 38//===----------------------------------------------------------------------===// 39/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 40/// hacks on it until the target machine can handle it. This involves 41/// eliminating value sizes the machine cannot handle (promoting small sizes to 42/// large sizes or splitting up large values into small values) as well as 43/// eliminating operations the machine cannot handle. 44/// 45/// This code also does a small amount of optimization and recognition of idioms 46/// as part of its processing. For example, if a target does not support a 47/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 48/// will attempt merge setcc and brc instructions into brcc's. 49/// 50namespace { 51class VISIBILITY_HIDDEN SelectionDAGLegalize { 52 TargetLowering &TLI; 53 SelectionDAG &DAG; 54 55 // Libcall insertion helpers. 56 57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 58 /// legalized. We use this to ensure that calls are properly serialized 59 /// against each other, including inserted libcalls. 60 SDValue LastCALLSEQ_END; 61 62 /// IsLegalizingCall - This member is used *only* for purposes of providing 63 /// helpful assertions that a libcall isn't created while another call is 64 /// being legalized (which could lead to non-serialized call sequences). 65 bool IsLegalizingCall; 66 67 enum LegalizeAction { 68 Legal, // The target natively supports this operation. 69 Promote, // This operation should be executed in a larger type. 70 Expand // Try to expand this to other ops, otherwise use a libcall. 71 }; 72 73 /// ValueTypeActions - This is a bitvector that contains two bits for each 74 /// value type, where the two bits correspond to the LegalizeAction enum. 75 /// This can be queried with "getTypeAction(VT)". 76 TargetLowering::ValueTypeActionImpl ValueTypeActions; 77 78 /// LegalizedNodes - For nodes that are of legal width, and that have more 79 /// than one use, this map indicates what regularized operand to use. This 80 /// allows us to avoid legalizing the same thing more than once. 81 DenseMap<SDValue, SDValue> LegalizedNodes; 82 83 /// PromotedNodes - For nodes that are below legal width, and that have more 84 /// than one use, this map indicates what promoted value to use. This allows 85 /// us to avoid promoting the same thing more than once. 86 DenseMap<SDValue, SDValue> PromotedNodes; 87 88 /// ExpandedNodes - For nodes that need to be expanded this map indicates 89 /// which which operands are the expanded version of the input. This allows 90 /// us to avoid expanding the same node more than once. 91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes; 92 93 /// SplitNodes - For vector nodes that need to be split, this map indicates 94 /// which which operands are the split version of the input. This allows us 95 /// to avoid splitting the same node more than once. 96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes; 97 98 /// ScalarizedNodes - For nodes that need to be converted from vector types to 99 /// scalar types, this contains the mapping of ones we have already 100 /// processed to the result. 101 std::map<SDValue, SDValue> ScalarizedNodes; 102 103 void AddLegalizedOperand(SDValue From, SDValue To) { 104 LegalizedNodes.insert(std::make_pair(From, To)); 105 // If someone requests legalization of the new node, return itself. 106 if (From != To) 107 LegalizedNodes.insert(std::make_pair(To, To)); 108 } 109 void AddPromotedOperand(SDValue From, SDValue To) { 110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 111 assert(isNew && "Got into the map somehow?"); 112 // If someone requests legalization of the new node, return itself. 113 LegalizedNodes.insert(std::make_pair(To, To)); 114 } 115 116public: 117 explicit SelectionDAGLegalize(SelectionDAG &DAG); 118 119 /// getTypeAction - Return how we should legalize values of this type, either 120 /// it is already legal or we need to expand it into multiple registers of 121 /// smaller integer type, or we need to promote it to a larger type. 122 LegalizeAction getTypeAction(MVT VT) const { 123 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 124 } 125 126 /// isTypeLegal - Return true if this type is legal on this target. 127 /// 128 bool isTypeLegal(MVT VT) const { 129 return getTypeAction(VT) == Legal; 130 } 131 132 void LegalizeDAG(); 133 134private: 135 /// HandleOp - Legalize, Promote, or Expand the specified operand as 136 /// appropriate for its type. 137 void HandleOp(SDValue Op); 138 139 /// LegalizeOp - We know that the specified value has a legal type. 140 /// Recursively ensure that the operands have legal types, then return the 141 /// result. 142 SDValue LegalizeOp(SDValue O); 143 144 /// UnrollVectorOp - We know that the given vector has a legal type, however 145 /// the operation it performs is not legal and is an operation that we have 146 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 147 /// operating on each element individually. 148 SDValue UnrollVectorOp(SDValue O); 149 150 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 151 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 152 /// is necessary to spill the vector being inserted into to memory, perform 153 /// the insert there, and then read the result back. 154 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 155 SDValue Idx); 156 157 /// PromoteOp - Given an operation that produces a value in an invalid type, 158 /// promote it to compute the value into a larger type. The produced value 159 /// will have the correct bits for the low portion of the register, but no 160 /// guarantee is made about the top bits: it may be zero, sign-extended, or 161 /// garbage. 162 SDValue PromoteOp(SDValue O); 163 164 /// ExpandOp - Expand the specified SDValue into its two component pieces 165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 166 /// the LegalizeNodes map is filled in for any results that are not expanded, 167 /// the ExpandedNodes map is filled in for any results that are expanded, and 168 /// the Lo/Hi values are returned. This applies to integer types and Vector 169 /// types. 170 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi); 171 172 /// SplitVectorOp - Given an operand of vector type, break it down into 173 /// two smaller values. 174 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi); 175 176 /// ScalarizeVectorOp - Given an operand of single-element vector type 177 /// (e.g. v1f32), convert it into the equivalent operation that returns a 178 /// scalar (e.g. f32) value. 179 SDValue ScalarizeVectorOp(SDValue O); 180 181 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the 182 /// specified mask and type. Targets can specify exactly which masks they 183 /// support and the code generator is tasked with not creating illegal masks. 184 /// 185 /// Note that this will also return true for shuffles that are promoted to a 186 /// different type. 187 /// 188 /// If this is a legal shuffle, this method returns the (possibly promoted) 189 /// build_vector Mask. If it's not a legal shuffle, it returns null. 190 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const; 191 192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 194 195 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC); 196 197 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 198 SDValue &Hi); 199 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source); 200 201 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT); 202 SDValue ExpandBUILD_VECTOR(SDNode *Node); 203 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 204 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op); 205 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT); 206 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned); 207 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned); 208 209 SDValue ExpandBSWAP(SDValue Op); 210 SDValue ExpandBitCount(unsigned Opc, SDValue Op); 211 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt, 212 SDValue &Lo, SDValue &Hi); 213 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt, 214 SDValue &Lo, SDValue &Hi); 215 216 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op); 217 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op); 218}; 219} 220 221/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 222/// specified mask and type. Targets can specify exactly which masks they 223/// support and the code generator is tasked with not creating illegal masks. 224/// 225/// Note that this will also return true for shuffles that are promoted to a 226/// different type. 227SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const { 228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 229 default: return 0; 230 case TargetLowering::Legal: 231 case TargetLowering::Custom: 232 break; 233 case TargetLowering::Promote: { 234 // If this is promoted to a different type, convert the shuffle mask and 235 // ask if it is legal in the promoted type! 236 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 237 MVT EltVT = NVT.getVectorElementType(); 238 239 // If we changed # elements, change the shuffle mask. 240 unsigned NumEltsGrowth = 241 NVT.getVectorNumElements() / VT.getVectorNumElements(); 242 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 243 if (NumEltsGrowth > 1) { 244 // Renumber the elements. 245 SmallVector<SDValue, 8> Ops; 246 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 247 SDValue InOp = Mask.getOperand(i); 248 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 249 if (InOp.getOpcode() == ISD::UNDEF) 250 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 251 else { 252 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 253 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT)); 254 } 255 } 256 } 257 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 258 } 259 VT = NVT; 260 break; 261 } 262 } 263 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 264} 265 266SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 267 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 268 ValueTypeActions(TLI.getValueTypeActions()) { 269 assert(MVT::LAST_VALUETYPE <= 32 && 270 "Too many value types for ValueTypeActions to hold!"); 271} 272 273/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 274/// contains all of a nodes operands before it contains the node. 275static void ComputeTopDownOrdering(SelectionDAG &DAG, 276 SmallVector<SDNode*, 64> &Order) { 277 278 DenseMap<SDNode*, unsigned> Visited; 279 std::vector<SDNode*> Worklist; 280 Worklist.reserve(128); 281 282 // Compute ordering from all of the leaves in the graphs, those (like the 283 // entry node) that have no operands. 284 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 285 E = DAG.allnodes_end(); I != E; ++I) { 286 if (I->getNumOperands() == 0) { 287 Visited[I] = 0 - 1U; 288 Worklist.push_back(I); 289 } 290 } 291 292 while (!Worklist.empty()) { 293 SDNode *N = Worklist.back(); 294 Worklist.pop_back(); 295 296 if (++Visited[N] != N->getNumOperands()) 297 continue; // Haven't visited all operands yet 298 299 Order.push_back(N); 300 301 // Now that we have N in, add anything that uses it if all of their operands 302 // are now done. 303 Worklist.insert(Worklist.end(), N->use_begin(), N->use_end()); 304 } 305 306 assert(Order.size() == Visited.size() && 307 Order.size() == DAG.allnodes_size() && 308 "Error: DAG is cyclic!"); 309} 310 311 312void SelectionDAGLegalize::LegalizeDAG() { 313 LastCALLSEQ_END = DAG.getEntryNode(); 314 IsLegalizingCall = false; 315 316 // The legalize process is inherently a bottom-up recursive process (users 317 // legalize their uses before themselves). Given infinite stack space, we 318 // could just start legalizing on the root and traverse the whole graph. In 319 // practice however, this causes us to run out of stack space on large basic 320 // blocks. To avoid this problem, compute an ordering of the nodes where each 321 // node is only legalized after all of its operands are legalized. 322 SmallVector<SDNode*, 64> Order; 323 ComputeTopDownOrdering(DAG, Order); 324 325 for (unsigned i = 0, e = Order.size(); i != e; ++i) 326 HandleOp(SDValue(Order[i], 0)); 327 328 // Finally, it's possible the root changed. Get the new root. 329 SDValue OldRoot = DAG.getRoot(); 330 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 331 DAG.setRoot(LegalizedNodes[OldRoot]); 332 333 ExpandedNodes.clear(); 334 LegalizedNodes.clear(); 335 PromotedNodes.clear(); 336 SplitNodes.clear(); 337 ScalarizedNodes.clear(); 338 339 // Remove dead nodes now. 340 DAG.RemoveDeadNodes(); 341} 342 343 344/// FindCallEndFromCallStart - Given a chained node that is part of a call 345/// sequence, find the CALLSEQ_END node that terminates the call sequence. 346static SDNode *FindCallEndFromCallStart(SDNode *Node) { 347 if (Node->getOpcode() == ISD::CALLSEQ_END) 348 return Node; 349 if (Node->use_empty()) 350 return 0; // No CallSeqEnd 351 352 // The chain is usually at the end. 353 SDValue TheChain(Node, Node->getNumValues()-1); 354 if (TheChain.getValueType() != MVT::Other) { 355 // Sometimes it's at the beginning. 356 TheChain = SDValue(Node, 0); 357 if (TheChain.getValueType() != MVT::Other) { 358 // Otherwise, hunt for it. 359 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 360 if (Node->getValueType(i) == MVT::Other) { 361 TheChain = SDValue(Node, i); 362 break; 363 } 364 365 // Otherwise, we walked into a node without a chain. 366 if (TheChain.getValueType() != MVT::Other) 367 return 0; 368 } 369 } 370 371 for (SDNode::use_iterator UI = Node->use_begin(), 372 E = Node->use_end(); UI != E; ++UI) { 373 374 // Make sure to only follow users of our token chain. 375 SDNode *User = *UI; 376 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 377 if (User->getOperand(i) == TheChain) 378 if (SDNode *Result = FindCallEndFromCallStart(User)) 379 return Result; 380 } 381 return 0; 382} 383 384/// FindCallStartFromCallEnd - Given a chained node that is part of a call 385/// sequence, find the CALLSEQ_START node that initiates the call sequence. 386static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 387 assert(Node && "Didn't find callseq_start for a call??"); 388 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 389 390 assert(Node->getOperand(0).getValueType() == MVT::Other && 391 "Node doesn't have a token chain argument!"); 392 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 393} 394 395/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 396/// see if any uses can reach Dest. If no dest operands can get to dest, 397/// legalize them, legalize ourself, and return false, otherwise, return true. 398/// 399/// Keep track of the nodes we fine that actually do lead to Dest in 400/// NodesLeadingTo. This avoids retraversing them exponential number of times. 401/// 402bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 403 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 404 if (N == Dest) return true; // N certainly leads to Dest :) 405 406 // If we've already processed this node and it does lead to Dest, there is no 407 // need to reprocess it. 408 if (NodesLeadingTo.count(N)) return true; 409 410 // If the first result of this node has been already legalized, then it cannot 411 // reach N. 412 switch (getTypeAction(N->getValueType(0))) { 413 case Legal: 414 if (LegalizedNodes.count(SDValue(N, 0))) return false; 415 break; 416 case Promote: 417 if (PromotedNodes.count(SDValue(N, 0))) return false; 418 break; 419 case Expand: 420 if (ExpandedNodes.count(SDValue(N, 0))) return false; 421 break; 422 } 423 424 // Okay, this node has not already been legalized. Check and legalize all 425 // operands. If none lead to Dest, then we can legalize this node. 426 bool OperandsLeadToDest = false; 427 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 428 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 429 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 430 431 if (OperandsLeadToDest) { 432 NodesLeadingTo.insert(N); 433 return true; 434 } 435 436 // Okay, this node looks safe, legalize it and return false. 437 HandleOp(SDValue(N, 0)); 438 return false; 439} 440 441/// HandleOp - Legalize, Promote, or Expand the specified operand as 442/// appropriate for its type. 443void SelectionDAGLegalize::HandleOp(SDValue Op) { 444 MVT VT = Op.getValueType(); 445 switch (getTypeAction(VT)) { 446 default: assert(0 && "Bad type action!"); 447 case Legal: (void)LegalizeOp(Op); break; 448 case Promote: (void)PromoteOp(Op); break; 449 case Expand: 450 if (!VT.isVector()) { 451 // If this is an illegal scalar, expand it into its two component 452 // pieces. 453 SDValue X, Y; 454 if (Op.getOpcode() == ISD::TargetConstant) 455 break; // Allow illegal target nodes. 456 ExpandOp(Op, X, Y); 457 } else if (VT.getVectorNumElements() == 1) { 458 // If this is an illegal single element vector, convert it to a 459 // scalar operation. 460 (void)ScalarizeVectorOp(Op); 461 } else { 462 // Otherwise, this is an illegal multiple element vector. 463 // Split it in half and legalize both parts. 464 SDValue X, Y; 465 SplitVectorOp(Op, X, Y); 466 } 467 break; 468 } 469} 470 471/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 472/// a load from the constant pool. 473static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 474 SelectionDAG &DAG, TargetLowering &TLI) { 475 bool Extend = false; 476 477 // If a FP immediate is precise when represented as a float and if the 478 // target can do an extending load from float to double, we put it into 479 // the constant pool as a float, even if it's is statically typed as a 480 // double. This shrinks FP constants and canonicalizes them for targets where 481 // an FP extending load is the same cost as a normal load (such as on the x87 482 // fp stack or PPC FP unit). 483 MVT VT = CFP->getValueType(0); 484 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF()); 485 if (!UseCP) { 486 if (VT!=MVT::f64 && VT!=MVT::f32) 487 assert(0 && "Invalid type expansion"); 488 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(), 489 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 490 } 491 492 MVT OrigVT = VT; 493 MVT SVT = VT; 494 while (SVT != MVT::f32) { 495 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 496 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 497 // Only do this if the target has a native EXTLOAD instruction from 498 // smaller type. 499 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && 500 TLI.ShouldShrinkFPConstant(OrigVT)) { 501 const Type *SType = SVT.getTypeForMVT(); 502 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 503 VT = SVT; 504 Extend = true; 505 } 506 } 507 508 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 509 if (Extend) 510 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), 511 CPIdx, PseudoSourceValue::getConstantPool(), 512 0, VT); 513 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 514 PseudoSourceValue::getConstantPool(), 0); 515} 516 517 518/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 519/// operations. 520static 521SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, 522 SelectionDAG &DAG, TargetLowering &TLI) { 523 MVT VT = Node->getValueType(0); 524 MVT SrcVT = Node->getOperand(1).getValueType(); 525 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 526 "fcopysign expansion only supported for f32 and f64"); 527 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 528 529 // First get the sign bit of second operand. 530 SDValue Mask1 = (SrcVT == MVT::f64) 531 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 532 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 533 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 534 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 535 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 536 // Shift right or sign-extend it if the two operands have different types. 537 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); 538 if (SizeDiff > 0) { 539 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 540 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 541 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 542 } else if (SizeDiff < 0) { 543 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit); 544 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit, 545 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy())); 546 } 547 548 // Clear the sign bit of first operand. 549 SDValue Mask2 = (VT == MVT::f64) 550 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 551 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 552 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 553 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 554 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 555 556 // Or the value with the sign bit. 557 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 558 return Result; 559} 560 561/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 562static 563SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 564 TargetLowering &TLI) { 565 SDValue Chain = ST->getChain(); 566 SDValue Ptr = ST->getBasePtr(); 567 SDValue Val = ST->getValue(); 568 MVT VT = Val.getValueType(); 569 int Alignment = ST->getAlignment(); 570 int SVOffset = ST->getSrcValueOffset(); 571 if (ST->getMemoryVT().isFloatingPoint() || 572 ST->getMemoryVT().isVector()) { 573 // Expand to a bitconvert of the value to the integer type of the 574 // same size, then a (misaligned) int store. 575 MVT intVT; 576 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128) 577 intVT = MVT::i128; 578 else if (VT.is64BitVector() || VT==MVT::f64) 579 intVT = MVT::i64; 580 else if (VT==MVT::f32) 581 intVT = MVT::i32; 582 else 583 assert(0 && "Unaligned store of unsupported type"); 584 585 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 586 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 587 SVOffset, ST->isVolatile(), Alignment); 588 } 589 assert(ST->getMemoryVT().isInteger() && 590 !ST->getMemoryVT().isVector() && 591 "Unaligned store of unknown type."); 592 // Get the half-size VT 593 MVT NewStoredVT = 594 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 595 int NumBits = NewStoredVT.getSizeInBits(); 596 int IncrementSize = NumBits / 8; 597 598 // Divide the stored value in two parts. 599 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 600 SDValue Lo = Val; 601 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 602 603 // Store the two parts 604 SDValue Store1, Store2; 605 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 606 ST->getSrcValue(), SVOffset, NewStoredVT, 607 ST->isVolatile(), Alignment); 608 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 609 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 610 Alignment = MinAlign(Alignment, IncrementSize); 611 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 612 ST->getSrcValue(), SVOffset + IncrementSize, 613 NewStoredVT, ST->isVolatile(), Alignment); 614 615 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 616} 617 618/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 619static 620SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 621 TargetLowering &TLI) { 622 int SVOffset = LD->getSrcValueOffset(); 623 SDValue Chain = LD->getChain(); 624 SDValue Ptr = LD->getBasePtr(); 625 MVT VT = LD->getValueType(0); 626 MVT LoadedVT = LD->getMemoryVT(); 627 if (VT.isFloatingPoint() || VT.isVector()) { 628 // Expand to a (misaligned) integer load of the same size, 629 // then bitconvert to floating point or vector. 630 MVT intVT; 631 if (LoadedVT.is128BitVector() || 632 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128) 633 intVT = MVT::i128; 634 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64) 635 intVT = MVT::i64; 636 else if (LoadedVT == MVT::f32) 637 intVT = MVT::i32; 638 else 639 assert(0 && "Unaligned load of unsupported type"); 640 641 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 642 SVOffset, LD->isVolatile(), 643 LD->getAlignment()); 644 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 645 if (VT.isFloatingPoint() && LoadedVT != VT) 646 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 647 648 SDValue Ops[] = { Result, Chain }; 649 return DAG.getMergeValues(Ops, 2); 650 } 651 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 652 "Unaligned load of unsupported type."); 653 654 // Compute the new VT that is half the size of the old one. This is an 655 // integer MVT. 656 unsigned NumBits = LoadedVT.getSizeInBits(); 657 MVT NewLoadedVT; 658 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 659 NumBits >>= 1; 660 661 unsigned Alignment = LD->getAlignment(); 662 unsigned IncrementSize = NumBits / 8; 663 ISD::LoadExtType HiExtType = LD->getExtensionType(); 664 665 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 666 if (HiExtType == ISD::NON_EXTLOAD) 667 HiExtType = ISD::ZEXTLOAD; 668 669 // Load the value in two parts 670 SDValue Lo, Hi; 671 if (TLI.isLittleEndian()) { 672 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 673 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 674 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 675 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 676 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 677 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 678 MinAlign(Alignment, IncrementSize)); 679 } else { 680 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 681 NewLoadedVT,LD->isVolatile(), Alignment); 682 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 683 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 684 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 685 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 686 MinAlign(Alignment, IncrementSize)); 687 } 688 689 // aggregate the two parts 690 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 691 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 692 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 693 694 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 695 Hi.getValue(1)); 696 697 SDValue Ops[] = { Result, TF }; 698 return DAG.getMergeValues(Ops, 2); 699} 700 701/// UnrollVectorOp - We know that the given vector has a legal type, however 702/// the operation it performs is not legal and is an operation that we have 703/// no way of lowering. "Unroll" the vector, splitting out the scalars and 704/// operating on each element individually. 705SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) { 706 MVT VT = Op.getValueType(); 707 assert(isTypeLegal(VT) && 708 "Caller should expand or promote operands that are not legal!"); 709 assert(Op.Val->getNumValues() == 1 && 710 "Can't unroll a vector with multiple results!"); 711 unsigned NE = VT.getVectorNumElements(); 712 MVT EltVT = VT.getVectorElementType(); 713 714 SmallVector<SDValue, 8> Scalars; 715 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 716 for (unsigned i = 0; i != NE; ++i) { 717 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 718 SDValue Operand = Op.getOperand(j); 719 MVT OperandVT = Operand.getValueType(); 720 if (OperandVT.isVector()) { 721 // A vector operand; extract a single element. 722 MVT OperandEltVT = OperandVT.getVectorElementType(); 723 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 724 OperandEltVT, 725 Operand, 726 DAG.getConstant(i, MVT::i32)); 727 } else { 728 // A scalar operand; just use it as is. 729 Operands[j] = Operand; 730 } 731 } 732 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 733 &Operands[0], Operands.size())); 734 } 735 736 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 737} 738 739/// GetFPLibCall - Return the right libcall for the given floating point type. 740static RTLIB::Libcall GetFPLibCall(MVT VT, 741 RTLIB::Libcall Call_F32, 742 RTLIB::Libcall Call_F64, 743 RTLIB::Libcall Call_F80, 744 RTLIB::Libcall Call_PPCF128) { 745 return 746 VT == MVT::f32 ? Call_F32 : 747 VT == MVT::f64 ? Call_F64 : 748 VT == MVT::f80 ? Call_F80 : 749 VT == MVT::ppcf128 ? Call_PPCF128 : 750 RTLIB::UNKNOWN_LIBCALL; 751} 752 753/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 754/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 755/// is necessary to spill the vector being inserted into to memory, perform 756/// the insert there, and then read the result back. 757SDValue SelectionDAGLegalize:: 758PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) { 759 SDValue Tmp1 = Vec; 760 SDValue Tmp2 = Val; 761 SDValue Tmp3 = Idx; 762 763 // If the target doesn't support this, we have to spill the input vector 764 // to a temporary stack slot, update the element, then reload it. This is 765 // badness. We could also load the value into a vector register (either 766 // with a "move to register" or "extload into register" instruction, then 767 // permute it into place, if the idx is a constant and if the idx is 768 // supported by the target. 769 MVT VT = Tmp1.getValueType(); 770 MVT EltVT = VT.getVectorElementType(); 771 MVT IdxVT = Tmp3.getValueType(); 772 MVT PtrVT = TLI.getPointerTy(); 773 SDValue StackPtr = DAG.CreateStackTemporary(VT); 774 775 int SPFI = cast<FrameIndexSDNode>(StackPtr.Val)->getIndex(); 776 777 // Store the vector. 778 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, 779 PseudoSourceValue::getFixedStack(SPFI), 0); 780 781 // Truncate or zero extend offset to target pointer type. 782 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 783 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 784 // Add the offset to the index. 785 unsigned EltSize = EltVT.getSizeInBits()/8; 786 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 787 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 788 // Store the scalar value. 789 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, 790 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 791 // Load the updated vector. 792 return DAG.getLoad(VT, Ch, StackPtr, 793 PseudoSourceValue::getFixedStack(SPFI), 0); 794} 795 796/// LegalizeOp - We know that the specified value has a legal type, and 797/// that its operands are legal. Now ensure that the operation itself 798/// is legal, recursively ensuring that the operands' operations remain 799/// legal. 800SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 801 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 802 return Op; 803 804 assert(isTypeLegal(Op.getValueType()) && 805 "Caller should expand or promote operands that are not legal!"); 806 SDNode *Node = Op.Val; 807 808 // If this operation defines any values that cannot be represented in a 809 // register on this target, make sure to expand or promote them. 810 if (Node->getNumValues() > 1) { 811 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 812 if (getTypeAction(Node->getValueType(i)) != Legal) { 813 HandleOp(Op.getValue(i)); 814 assert(LegalizedNodes.count(Op) && 815 "Handling didn't add legal operands!"); 816 return LegalizedNodes[Op]; 817 } 818 } 819 820 // Note that LegalizeOp may be reentered even from single-use nodes, which 821 // means that we always must cache transformed nodes. 822 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 823 if (I != LegalizedNodes.end()) return I->second; 824 825 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 826 SDValue Result = Op; 827 bool isCustom = false; 828 829 switch (Node->getOpcode()) { 830 case ISD::FrameIndex: 831 case ISD::EntryToken: 832 case ISD::Register: 833 case ISD::BasicBlock: 834 case ISD::TargetFrameIndex: 835 case ISD::TargetJumpTable: 836 case ISD::TargetConstant: 837 case ISD::TargetConstantFP: 838 case ISD::TargetConstantPool: 839 case ISD::TargetGlobalAddress: 840 case ISD::TargetGlobalTLSAddress: 841 case ISD::TargetExternalSymbol: 842 case ISD::VALUETYPE: 843 case ISD::SRCVALUE: 844 case ISD::MEMOPERAND: 845 case ISD::CONDCODE: 846 case ISD::ARG_FLAGS: 847 // Primitives must all be legal. 848 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 849 "This must be legal!"); 850 break; 851 default: 852 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 853 // If this is a target node, legalize it by legalizing the operands then 854 // passing it through. 855 SmallVector<SDValue, 8> Ops; 856 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 857 Ops.push_back(LegalizeOp(Node->getOperand(i))); 858 859 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 860 861 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 862 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 863 return Result.getValue(Op.ResNo); 864 } 865 // Otherwise this is an unhandled builtin node. splat. 866#ifndef NDEBUG 867 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 868#endif 869 assert(0 && "Do not know how to legalize this operator!"); 870 abort(); 871 case ISD::GLOBAL_OFFSET_TABLE: 872 case ISD::GlobalAddress: 873 case ISD::GlobalTLSAddress: 874 case ISD::ExternalSymbol: 875 case ISD::ConstantPool: 876 case ISD::JumpTable: // Nothing to do. 877 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 878 default: assert(0 && "This action is not supported yet!"); 879 case TargetLowering::Custom: 880 Tmp1 = TLI.LowerOperation(Op, DAG); 881 if (Tmp1.Val) Result = Tmp1; 882 // FALLTHROUGH if the target doesn't want to lower this op after all. 883 case TargetLowering::Legal: 884 break; 885 } 886 break; 887 case ISD::FRAMEADDR: 888 case ISD::RETURNADDR: 889 // The only option for these nodes is to custom lower them. If the target 890 // does not custom lower them, then return zero. 891 Tmp1 = TLI.LowerOperation(Op, DAG); 892 if (Tmp1.Val) 893 Result = Tmp1; 894 else 895 Result = DAG.getConstant(0, TLI.getPointerTy()); 896 break; 897 case ISD::FRAME_TO_ARGS_OFFSET: { 898 MVT VT = Node->getValueType(0); 899 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 900 default: assert(0 && "This action is not supported yet!"); 901 case TargetLowering::Custom: 902 Result = TLI.LowerOperation(Op, DAG); 903 if (Result.Val) break; 904 // Fall Thru 905 case TargetLowering::Legal: 906 Result = DAG.getConstant(0, VT); 907 break; 908 } 909 } 910 break; 911 case ISD::EXCEPTIONADDR: { 912 Tmp1 = LegalizeOp(Node->getOperand(0)); 913 MVT VT = Node->getValueType(0); 914 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 915 default: assert(0 && "This action is not supported yet!"); 916 case TargetLowering::Expand: { 917 unsigned Reg = TLI.getExceptionAddressRegister(); 918 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 919 } 920 break; 921 case TargetLowering::Custom: 922 Result = TLI.LowerOperation(Op, DAG); 923 if (Result.Val) break; 924 // Fall Thru 925 case TargetLowering::Legal: { 926 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 927 Result = DAG.getMergeValues(Ops, 2); 928 break; 929 } 930 } 931 } 932 if (Result.Val->getNumValues() == 1) break; 933 934 assert(Result.Val->getNumValues() == 2 && 935 "Cannot return more than two values!"); 936 937 // Since we produced two values, make sure to remember that we 938 // legalized both of them. 939 Tmp1 = LegalizeOp(Result); 940 Tmp2 = LegalizeOp(Result.getValue(1)); 941 AddLegalizedOperand(Op.getValue(0), Tmp1); 942 AddLegalizedOperand(Op.getValue(1), Tmp2); 943 return Op.ResNo ? Tmp2 : Tmp1; 944 case ISD::EHSELECTION: { 945 Tmp1 = LegalizeOp(Node->getOperand(0)); 946 Tmp2 = LegalizeOp(Node->getOperand(1)); 947 MVT VT = Node->getValueType(0); 948 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 949 default: assert(0 && "This action is not supported yet!"); 950 case TargetLowering::Expand: { 951 unsigned Reg = TLI.getExceptionSelectorRegister(); 952 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 953 } 954 break; 955 case TargetLowering::Custom: 956 Result = TLI.LowerOperation(Op, DAG); 957 if (Result.Val) break; 958 // Fall Thru 959 case TargetLowering::Legal: { 960 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 961 Result = DAG.getMergeValues(Ops, 2); 962 break; 963 } 964 } 965 } 966 if (Result.Val->getNumValues() == 1) break; 967 968 assert(Result.Val->getNumValues() == 2 && 969 "Cannot return more than two values!"); 970 971 // Since we produced two values, make sure to remember that we 972 // legalized both of them. 973 Tmp1 = LegalizeOp(Result); 974 Tmp2 = LegalizeOp(Result.getValue(1)); 975 AddLegalizedOperand(Op.getValue(0), Tmp1); 976 AddLegalizedOperand(Op.getValue(1), Tmp2); 977 return Op.ResNo ? Tmp2 : Tmp1; 978 case ISD::EH_RETURN: { 979 MVT VT = Node->getValueType(0); 980 // The only "good" option for this node is to custom lower it. 981 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 982 default: assert(0 && "This action is not supported at all!"); 983 case TargetLowering::Custom: 984 Result = TLI.LowerOperation(Op, DAG); 985 if (Result.Val) break; 986 // Fall Thru 987 case TargetLowering::Legal: 988 // Target does not know, how to lower this, lower to noop 989 Result = LegalizeOp(Node->getOperand(0)); 990 break; 991 } 992 } 993 break; 994 case ISD::AssertSext: 995 case ISD::AssertZext: 996 Tmp1 = LegalizeOp(Node->getOperand(0)); 997 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 998 break; 999 case ISD::MERGE_VALUES: 1000 // Legalize eliminates MERGE_VALUES nodes. 1001 Result = Node->getOperand(Op.ResNo); 1002 break; 1003 case ISD::CopyFromReg: 1004 Tmp1 = LegalizeOp(Node->getOperand(0)); 1005 Result = Op.getValue(0); 1006 if (Node->getNumValues() == 2) { 1007 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1008 } else { 1009 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 1010 if (Node->getNumOperands() == 3) { 1011 Tmp2 = LegalizeOp(Node->getOperand(2)); 1012 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1013 } else { 1014 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1015 } 1016 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 1017 } 1018 // Since CopyFromReg produces two values, make sure to remember that we 1019 // legalized both of them. 1020 AddLegalizedOperand(Op.getValue(0), Result); 1021 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1022 return Result.getValue(Op.ResNo); 1023 case ISD::UNDEF: { 1024 MVT VT = Op.getValueType(); 1025 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 1026 default: assert(0 && "This action is not supported yet!"); 1027 case TargetLowering::Expand: 1028 if (VT.isInteger()) 1029 Result = DAG.getConstant(0, VT); 1030 else if (VT.isFloatingPoint()) 1031 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), 1032 VT); 1033 else 1034 assert(0 && "Unknown value type!"); 1035 break; 1036 case TargetLowering::Legal: 1037 break; 1038 } 1039 break; 1040 } 1041 1042 case ISD::INTRINSIC_W_CHAIN: 1043 case ISD::INTRINSIC_WO_CHAIN: 1044 case ISD::INTRINSIC_VOID: { 1045 SmallVector<SDValue, 8> Ops; 1046 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1047 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1048 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1049 1050 // Allow the target to custom lower its intrinsics if it wants to. 1051 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1052 TargetLowering::Custom) { 1053 Tmp3 = TLI.LowerOperation(Result, DAG); 1054 if (Tmp3.Val) Result = Tmp3; 1055 } 1056 1057 if (Result.Val->getNumValues() == 1) break; 1058 1059 // Must have return value and chain result. 1060 assert(Result.Val->getNumValues() == 2 && 1061 "Cannot return more than two values!"); 1062 1063 // Since loads produce two values, make sure to remember that we 1064 // legalized both of them. 1065 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1066 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1067 return Result.getValue(Op.ResNo); 1068 } 1069 1070 case ISD::DBG_STOPPOINT: 1071 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!"); 1072 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1073 1074 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) { 1075 case TargetLowering::Promote: 1076 default: assert(0 && "This action is not supported yet!"); 1077 case TargetLowering::Expand: { 1078 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1079 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1080 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other); 1081 1082 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1083 if (MMI && (useDEBUG_LOC || useLABEL)) { 1084 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit(); 1085 unsigned SrcFile = MMI->RecordSource(CompileUnit); 1086 1087 unsigned Line = DSP->getLine(); 1088 unsigned Col = DSP->getColumn(); 1089 1090 if (useDEBUG_LOC) { 1091 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), 1092 DAG.getConstant(Col, MVT::i32), 1093 DAG.getConstant(SrcFile, MVT::i32) }; 1094 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4); 1095 } else { 1096 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 1097 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID); 1098 } 1099 } else { 1100 Result = Tmp1; // chain 1101 } 1102 break; 1103 } 1104 case TargetLowering::Legal: { 1105 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1106 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1107 break; 1108 1109 SmallVector<SDValue, 8> Ops; 1110 Ops.push_back(Tmp1); 1111 if (Action == Legal) { 1112 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1113 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1114 } else { 1115 // Otherwise promote them. 1116 Ops.push_back(PromoteOp(Node->getOperand(1))); 1117 Ops.push_back(PromoteOp(Node->getOperand(2))); 1118 } 1119 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1120 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1121 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1122 break; 1123 } 1124 } 1125 break; 1126 1127 case ISD::DECLARE: 1128 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1129 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1130 default: assert(0 && "This action is not supported yet!"); 1131 case TargetLowering::Legal: 1132 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1133 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1134 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1135 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1136 break; 1137 case TargetLowering::Expand: 1138 Result = LegalizeOp(Node->getOperand(0)); 1139 break; 1140 } 1141 break; 1142 1143 case ISD::DEBUG_LOC: 1144 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1145 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1146 default: assert(0 && "This action is not supported yet!"); 1147 case TargetLowering::Legal: { 1148 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1149 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1150 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1151 break; 1152 if (Action == Legal) { 1153 Tmp2 = Node->getOperand(1); 1154 Tmp3 = Node->getOperand(2); 1155 Tmp4 = Node->getOperand(3); 1156 } else { 1157 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1158 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1159 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1160 } 1161 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1162 break; 1163 } 1164 } 1165 break; 1166 1167 case ISD::DBG_LABEL: 1168 case ISD::EH_LABEL: 1169 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!"); 1170 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1171 default: assert(0 && "This action is not supported yet!"); 1172 case TargetLowering::Legal: 1173 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1174 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1175 break; 1176 case TargetLowering::Expand: 1177 Result = LegalizeOp(Node->getOperand(0)); 1178 break; 1179 } 1180 break; 1181 1182 case ISD::PREFETCH: 1183 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1184 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1185 default: assert(0 && "This action is not supported yet!"); 1186 case TargetLowering::Legal: 1187 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1188 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1189 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1190 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1191 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1192 break; 1193 case TargetLowering::Expand: 1194 // It's a noop. 1195 Result = LegalizeOp(Node->getOperand(0)); 1196 break; 1197 } 1198 break; 1199 1200 case ISD::MEMBARRIER: { 1201 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1202 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1203 default: assert(0 && "This action is not supported yet!"); 1204 case TargetLowering::Legal: { 1205 SDValue Ops[6]; 1206 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1207 for (int x = 1; x < 6; ++x) { 1208 Ops[x] = Node->getOperand(x); 1209 if (!isTypeLegal(Ops[x].getValueType())) 1210 Ops[x] = PromoteOp(Ops[x]); 1211 } 1212 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1213 break; 1214 } 1215 case TargetLowering::Expand: 1216 //There is no libgcc call for this op 1217 Result = Node->getOperand(0); // Noop 1218 break; 1219 } 1220 break; 1221 } 1222 1223 case ISD::ATOMIC_CMP_SWAP: { 1224 unsigned int num_operands = 4; 1225 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1226 SDValue Ops[4]; 1227 for (unsigned int x = 0; x < num_operands; ++x) 1228 Ops[x] = LegalizeOp(Node->getOperand(x)); 1229 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1230 1231 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1232 default: assert(0 && "This action is not supported yet!"); 1233 case TargetLowering::Custom: 1234 Result = TLI.LowerOperation(Result, DAG); 1235 break; 1236 case TargetLowering::Legal: 1237 break; 1238 } 1239 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1240 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1241 return Result.getValue(Op.ResNo); 1242 } 1243 case ISD::ATOMIC_LOAD_ADD: 1244 case ISD::ATOMIC_LOAD_SUB: 1245 case ISD::ATOMIC_LOAD_AND: 1246 case ISD::ATOMIC_LOAD_OR: 1247 case ISD::ATOMIC_LOAD_XOR: 1248 case ISD::ATOMIC_LOAD_NAND: 1249 case ISD::ATOMIC_LOAD_MIN: 1250 case ISD::ATOMIC_LOAD_MAX: 1251 case ISD::ATOMIC_LOAD_UMIN: 1252 case ISD::ATOMIC_LOAD_UMAX: 1253 case ISD::ATOMIC_SWAP: { 1254 unsigned int num_operands = 3; 1255 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1256 SDValue Ops[3]; 1257 for (unsigned int x = 0; x < num_operands; ++x) 1258 Ops[x] = LegalizeOp(Node->getOperand(x)); 1259 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1260 1261 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1262 default: assert(0 && "This action is not supported yet!"); 1263 case TargetLowering::Custom: 1264 Result = TLI.LowerOperation(Result, DAG); 1265 break; 1266 case TargetLowering::Expand: 1267 Result = SDValue(TLI.ReplaceNodeResults(Op.Val, DAG),0); 1268 break; 1269 case TargetLowering::Legal: 1270 break; 1271 } 1272 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1273 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1274 return Result.getValue(Op.ResNo); 1275 } 1276 case ISD::Constant: { 1277 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1278 unsigned opAction = 1279 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1280 1281 // We know we don't need to expand constants here, constants only have one 1282 // value and we check that it is fine above. 1283 1284 if (opAction == TargetLowering::Custom) { 1285 Tmp1 = TLI.LowerOperation(Result, DAG); 1286 if (Tmp1.Val) 1287 Result = Tmp1; 1288 } 1289 break; 1290 } 1291 case ISD::ConstantFP: { 1292 // Spill FP immediates to the constant pool if the target cannot directly 1293 // codegen them. Targets often have some immediate values that can be 1294 // efficiently generated into an FP register without a load. We explicitly 1295 // leave these constants as ConstantFP nodes for the target to deal with. 1296 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1297 1298 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1299 default: assert(0 && "This action is not supported yet!"); 1300 case TargetLowering::Legal: 1301 break; 1302 case TargetLowering::Custom: 1303 Tmp3 = TLI.LowerOperation(Result, DAG); 1304 if (Tmp3.Val) { 1305 Result = Tmp3; 1306 break; 1307 } 1308 // FALLTHROUGH 1309 case TargetLowering::Expand: { 1310 // Check to see if this FP immediate is already legal. 1311 bool isLegal = false; 1312 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1313 E = TLI.legal_fpimm_end(); I != E; ++I) { 1314 if (CFP->isExactlyValue(*I)) { 1315 isLegal = true; 1316 break; 1317 } 1318 } 1319 // If this is a legal constant, turn it into a TargetConstantFP node. 1320 if (isLegal) 1321 break; 1322 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1323 } 1324 } 1325 break; 1326 } 1327 case ISD::TokenFactor: 1328 if (Node->getNumOperands() == 2) { 1329 Tmp1 = LegalizeOp(Node->getOperand(0)); 1330 Tmp2 = LegalizeOp(Node->getOperand(1)); 1331 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1332 } else if (Node->getNumOperands() == 3) { 1333 Tmp1 = LegalizeOp(Node->getOperand(0)); 1334 Tmp2 = LegalizeOp(Node->getOperand(1)); 1335 Tmp3 = LegalizeOp(Node->getOperand(2)); 1336 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1337 } else { 1338 SmallVector<SDValue, 8> Ops; 1339 // Legalize the operands. 1340 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1341 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1342 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1343 } 1344 break; 1345 1346 case ISD::FORMAL_ARGUMENTS: 1347 case ISD::CALL: 1348 // The only option for this is to custom lower it. 1349 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1350 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1351 // A call within a calling sequence must be legalized to something 1352 // other than the normal CALLSEQ_END. Violating this gets Legalize 1353 // into an infinite loop. 1354 assert ((!IsLegalizingCall || 1355 Node->getOpcode() != ISD::CALL || 1356 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) && 1357 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1358 1359 // The number of incoming and outgoing values should match; unless the final 1360 // outgoing value is a flag. 1361 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1362 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1363 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1364 MVT::Flag)) && 1365 "Lowering call/formal_arguments produced unexpected # results!"); 1366 1367 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1368 // remember that we legalized all of them, so it doesn't get relegalized. 1369 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1370 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1371 continue; 1372 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1373 if (Op.ResNo == i) 1374 Tmp2 = Tmp1; 1375 AddLegalizedOperand(SDValue(Node, i), Tmp1); 1376 } 1377 return Tmp2; 1378 case ISD::EXTRACT_SUBREG: { 1379 Tmp1 = LegalizeOp(Node->getOperand(0)); 1380 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1381 assert(idx && "Operand must be a constant"); 1382 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1383 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1384 } 1385 break; 1386 case ISD::INSERT_SUBREG: { 1387 Tmp1 = LegalizeOp(Node->getOperand(0)); 1388 Tmp2 = LegalizeOp(Node->getOperand(1)); 1389 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1390 assert(idx && "Operand must be a constant"); 1391 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1392 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1393 } 1394 break; 1395 case ISD::BUILD_VECTOR: 1396 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1397 default: assert(0 && "This action is not supported yet!"); 1398 case TargetLowering::Custom: 1399 Tmp3 = TLI.LowerOperation(Result, DAG); 1400 if (Tmp3.Val) { 1401 Result = Tmp3; 1402 break; 1403 } 1404 // FALLTHROUGH 1405 case TargetLowering::Expand: 1406 Result = ExpandBUILD_VECTOR(Result.Val); 1407 break; 1408 } 1409 break; 1410 case ISD::INSERT_VECTOR_ELT: 1411 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1412 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1413 1414 // The type of the value to insert may not be legal, even though the vector 1415 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1416 // here. 1417 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1418 default: assert(0 && "Cannot expand insert element operand"); 1419 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1420 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1421 } 1422 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1423 1424 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1425 Node->getValueType(0))) { 1426 default: assert(0 && "This action is not supported yet!"); 1427 case TargetLowering::Legal: 1428 break; 1429 case TargetLowering::Custom: 1430 Tmp4 = TLI.LowerOperation(Result, DAG); 1431 if (Tmp4.Val) { 1432 Result = Tmp4; 1433 break; 1434 } 1435 // FALLTHROUGH 1436 case TargetLowering::Expand: { 1437 // If the insert index is a constant, codegen this as a scalar_to_vector, 1438 // then a shuffle that inserts it into the right position in the vector. 1439 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1440 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1441 // match the element type of the vector being created. 1442 if (Tmp2.getValueType() == 1443 Op.getValueType().getVectorElementType()) { 1444 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1445 Tmp1.getValueType(), Tmp2); 1446 1447 unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); 1448 MVT ShufMaskVT = 1449 MVT::getIntVectorWithNumElements(NumElts); 1450 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); 1451 1452 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1453 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1454 // elt 0 of the RHS. 1455 SmallVector<SDValue, 8> ShufOps; 1456 for (unsigned i = 0; i != NumElts; ++i) { 1457 if (i != InsertPos->getValue()) 1458 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1459 else 1460 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1461 } 1462 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1463 &ShufOps[0], ShufOps.size()); 1464 1465 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1466 Tmp1, ScVec, ShufMask); 1467 Result = LegalizeOp(Result); 1468 break; 1469 } 1470 } 1471 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3); 1472 break; 1473 } 1474 } 1475 break; 1476 case ISD::SCALAR_TO_VECTOR: 1477 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1478 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1479 break; 1480 } 1481 1482 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1483 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1484 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1485 Node->getValueType(0))) { 1486 default: assert(0 && "This action is not supported yet!"); 1487 case TargetLowering::Legal: 1488 break; 1489 case TargetLowering::Custom: 1490 Tmp3 = TLI.LowerOperation(Result, DAG); 1491 if (Tmp3.Val) { 1492 Result = Tmp3; 1493 break; 1494 } 1495 // FALLTHROUGH 1496 case TargetLowering::Expand: 1497 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1498 break; 1499 } 1500 break; 1501 case ISD::VECTOR_SHUFFLE: 1502 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1503 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1504 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1505 1506 // Allow targets to custom lower the SHUFFLEs they support. 1507 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1508 default: assert(0 && "Unknown operation action!"); 1509 case TargetLowering::Legal: 1510 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1511 "vector shuffle should not be created if not legal!"); 1512 break; 1513 case TargetLowering::Custom: 1514 Tmp3 = TLI.LowerOperation(Result, DAG); 1515 if (Tmp3.Val) { 1516 Result = Tmp3; 1517 break; 1518 } 1519 // FALLTHROUGH 1520 case TargetLowering::Expand: { 1521 MVT VT = Node->getValueType(0); 1522 MVT EltVT = VT.getVectorElementType(); 1523 MVT PtrVT = TLI.getPointerTy(); 1524 SDValue Mask = Node->getOperand(2); 1525 unsigned NumElems = Mask.getNumOperands(); 1526 SmallVector<SDValue,8> Ops; 1527 for (unsigned i = 0; i != NumElems; ++i) { 1528 SDValue Arg = Mask.getOperand(i); 1529 if (Arg.getOpcode() == ISD::UNDEF) { 1530 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1531 } else { 1532 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1533 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1534 if (Idx < NumElems) 1535 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1536 DAG.getConstant(Idx, PtrVT))); 1537 else 1538 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1539 DAG.getConstant(Idx - NumElems, PtrVT))); 1540 } 1541 } 1542 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1543 break; 1544 } 1545 case TargetLowering::Promote: { 1546 // Change base type to a different vector type. 1547 MVT OVT = Node->getValueType(0); 1548 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1549 1550 // Cast the two input vectors. 1551 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1552 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1553 1554 // Convert the shuffle mask to the right # elements. 1555 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1556 assert(Tmp3.Val && "Shuffle not legal?"); 1557 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1558 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1559 break; 1560 } 1561 } 1562 break; 1563 1564 case ISD::EXTRACT_VECTOR_ELT: 1565 Tmp1 = Node->getOperand(0); 1566 Tmp2 = LegalizeOp(Node->getOperand(1)); 1567 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1568 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1569 break; 1570 1571 case ISD::EXTRACT_SUBVECTOR: 1572 Tmp1 = Node->getOperand(0); 1573 Tmp2 = LegalizeOp(Node->getOperand(1)); 1574 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1575 Result = ExpandEXTRACT_SUBVECTOR(Result); 1576 break; 1577 1578 case ISD::CALLSEQ_START: { 1579 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1580 1581 // Recursively Legalize all of the inputs of the call end that do not lead 1582 // to this call start. This ensures that any libcalls that need be inserted 1583 // are inserted *before* the CALLSEQ_START. 1584 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1585 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1586 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1587 NodesLeadingTo); 1588 } 1589 1590 // Now that we legalized all of the inputs (which may have inserted 1591 // libcalls) create the new CALLSEQ_START node. 1592 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1593 1594 // Merge in the last call, to ensure that this call start after the last 1595 // call ended. 1596 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1597 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1598 Tmp1 = LegalizeOp(Tmp1); 1599 } 1600 1601 // Do not try to legalize the target-specific arguments (#1+). 1602 if (Tmp1 != Node->getOperand(0)) { 1603 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1604 Ops[0] = Tmp1; 1605 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1606 } 1607 1608 // Remember that the CALLSEQ_START is legalized. 1609 AddLegalizedOperand(Op.getValue(0), Result); 1610 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1611 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1612 1613 // Now that the callseq_start and all of the non-call nodes above this call 1614 // sequence have been legalized, legalize the call itself. During this 1615 // process, no libcalls can/will be inserted, guaranteeing that no calls 1616 // can overlap. 1617 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1618 // Note that we are selecting this call! 1619 LastCALLSEQ_END = SDValue(CallEnd, 0); 1620 IsLegalizingCall = true; 1621 1622 // Legalize the call, starting from the CALLSEQ_END. 1623 LegalizeOp(LastCALLSEQ_END); 1624 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1625 return Result; 1626 } 1627 case ISD::CALLSEQ_END: 1628 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1629 // will cause this node to be legalized as well as handling libcalls right. 1630 if (LastCALLSEQ_END.Val != Node) { 1631 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1632 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1633 assert(I != LegalizedNodes.end() && 1634 "Legalizing the call start should have legalized this node!"); 1635 return I->second; 1636 } 1637 1638 // Otherwise, the call start has been legalized and everything is going 1639 // according to plan. Just legalize ourselves normally here. 1640 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1641 // Do not try to legalize the target-specific arguments (#1+), except for 1642 // an optional flag input. 1643 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1644 if (Tmp1 != Node->getOperand(0)) { 1645 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1646 Ops[0] = Tmp1; 1647 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1648 } 1649 } else { 1650 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1651 if (Tmp1 != Node->getOperand(0) || 1652 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1653 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1654 Ops[0] = Tmp1; 1655 Ops.back() = Tmp2; 1656 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1657 } 1658 } 1659 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1660 // This finishes up call legalization. 1661 IsLegalizingCall = false; 1662 1663 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1664 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1665 if (Node->getNumValues() == 2) 1666 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1667 return Result.getValue(Op.ResNo); 1668 case ISD::DYNAMIC_STACKALLOC: { 1669 MVT VT = Node->getValueType(0); 1670 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1671 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1672 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1673 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1674 1675 Tmp1 = Result.getValue(0); 1676 Tmp2 = Result.getValue(1); 1677 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1678 default: assert(0 && "This action is not supported yet!"); 1679 case TargetLowering::Expand: { 1680 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1681 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1682 " not tell us which reg is the stack pointer!"); 1683 SDValue Chain = Tmp1.getOperand(0); 1684 1685 // Chain the dynamic stack allocation so that it doesn't modify the stack 1686 // pointer when other instructions are using the stack. 1687 Chain = DAG.getCALLSEQ_START(Chain, 1688 DAG.getConstant(0, TLI.getPointerTy())); 1689 1690 SDValue Size = Tmp2.getOperand(1); 1691 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1692 Chain = SP.getValue(1); 1693 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1694 unsigned StackAlign = 1695 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1696 if (Align > StackAlign) 1697 SP = DAG.getNode(ISD::AND, VT, SP, 1698 DAG.getConstant(-(uint64_t)Align, VT)); 1699 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1700 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1701 1702 Tmp2 = 1703 DAG.getCALLSEQ_END(Chain, 1704 DAG.getConstant(0, TLI.getPointerTy()), 1705 DAG.getConstant(0, TLI.getPointerTy()), 1706 SDValue()); 1707 1708 Tmp1 = LegalizeOp(Tmp1); 1709 Tmp2 = LegalizeOp(Tmp2); 1710 break; 1711 } 1712 case TargetLowering::Custom: 1713 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1714 if (Tmp3.Val) { 1715 Tmp1 = LegalizeOp(Tmp3); 1716 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1717 } 1718 break; 1719 case TargetLowering::Legal: 1720 break; 1721 } 1722 // Since this op produce two values, make sure to remember that we 1723 // legalized both of them. 1724 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1725 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1726 return Op.ResNo ? Tmp2 : Tmp1; 1727 } 1728 case ISD::INLINEASM: { 1729 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1730 bool Changed = false; 1731 // Legalize all of the operands of the inline asm, in case they are nodes 1732 // that need to be expanded or something. Note we skip the asm string and 1733 // all of the TargetConstant flags. 1734 SDValue Op = LegalizeOp(Ops[0]); 1735 Changed = Op != Ops[0]; 1736 Ops[0] = Op; 1737 1738 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1739 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1740 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1741 for (++i; NumVals; ++i, --NumVals) { 1742 SDValue Op = LegalizeOp(Ops[i]); 1743 if (Op != Ops[i]) { 1744 Changed = true; 1745 Ops[i] = Op; 1746 } 1747 } 1748 } 1749 1750 if (HasInFlag) { 1751 Op = LegalizeOp(Ops.back()); 1752 Changed |= Op != Ops.back(); 1753 Ops.back() = Op; 1754 } 1755 1756 if (Changed) 1757 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1758 1759 // INLINE asm returns a chain and flag, make sure to add both to the map. 1760 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1761 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1762 return Result.getValue(Op.ResNo); 1763 } 1764 case ISD::BR: 1765 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1766 // Ensure that libcalls are emitted before a branch. 1767 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1768 Tmp1 = LegalizeOp(Tmp1); 1769 LastCALLSEQ_END = DAG.getEntryNode(); 1770 1771 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1772 break; 1773 case ISD::BRIND: 1774 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1775 // Ensure that libcalls are emitted before a branch. 1776 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1777 Tmp1 = LegalizeOp(Tmp1); 1778 LastCALLSEQ_END = DAG.getEntryNode(); 1779 1780 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1781 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1782 case Legal: 1783 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1784 break; 1785 } 1786 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1787 break; 1788 case ISD::BR_JT: 1789 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1790 // Ensure that libcalls are emitted before a branch. 1791 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1792 Tmp1 = LegalizeOp(Tmp1); 1793 LastCALLSEQ_END = DAG.getEntryNode(); 1794 1795 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1796 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1797 1798 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1799 default: assert(0 && "This action is not supported yet!"); 1800 case TargetLowering::Legal: break; 1801 case TargetLowering::Custom: 1802 Tmp1 = TLI.LowerOperation(Result, DAG); 1803 if (Tmp1.Val) Result = Tmp1; 1804 break; 1805 case TargetLowering::Expand: { 1806 SDValue Chain = Result.getOperand(0); 1807 SDValue Table = Result.getOperand(1); 1808 SDValue Index = Result.getOperand(2); 1809 1810 MVT PTy = TLI.getPointerTy(); 1811 MachineFunction &MF = DAG.getMachineFunction(); 1812 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1813 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1814 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1815 1816 SDValue LD; 1817 switch (EntrySize) { 1818 default: assert(0 && "Size of jump table not supported yet."); break; 1819 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, 1820 PseudoSourceValue::getJumpTable(), 0); break; 1821 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, 1822 PseudoSourceValue::getJumpTable(), 0); break; 1823 } 1824 1825 Addr = LD; 1826 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1827 // For PIC, the sequence is: 1828 // BRIND(load(Jumptable + index) + RelocBase) 1829 // RelocBase can be JumpTable, GOT or some sort of global base. 1830 if (PTy != MVT::i32) 1831 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1832 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1833 TLI.getPICJumpTableRelocBase(Table, DAG)); 1834 } 1835 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1836 } 1837 } 1838 break; 1839 case ISD::BRCOND: 1840 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1841 // Ensure that libcalls are emitted before a return. 1842 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1843 Tmp1 = LegalizeOp(Tmp1); 1844 LastCALLSEQ_END = DAG.getEntryNode(); 1845 1846 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1847 case Expand: assert(0 && "It's impossible to expand bools"); 1848 case Legal: 1849 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1850 break; 1851 case Promote: { 1852 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1853 1854 // The top bits of the promoted condition are not necessarily zero, ensure 1855 // that the value is properly zero extended. 1856 unsigned BitWidth = Tmp2.getValueSizeInBits(); 1857 if (!DAG.MaskedValueIsZero(Tmp2, 1858 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 1859 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1860 break; 1861 } 1862 } 1863 1864 // Basic block destination (Op#2) is always legal. 1865 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1866 1867 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1868 default: assert(0 && "This action is not supported yet!"); 1869 case TargetLowering::Legal: break; 1870 case TargetLowering::Custom: 1871 Tmp1 = TLI.LowerOperation(Result, DAG); 1872 if (Tmp1.Val) Result = Tmp1; 1873 break; 1874 case TargetLowering::Expand: 1875 // Expand brcond's setcc into its constituent parts and create a BR_CC 1876 // Node. 1877 if (Tmp2.getOpcode() == ISD::SETCC) { 1878 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1879 Tmp2.getOperand(0), Tmp2.getOperand(1), 1880 Node->getOperand(2)); 1881 } else { 1882 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1883 DAG.getCondCode(ISD::SETNE), Tmp2, 1884 DAG.getConstant(0, Tmp2.getValueType()), 1885 Node->getOperand(2)); 1886 } 1887 break; 1888 } 1889 break; 1890 case ISD::BR_CC: 1891 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1892 // Ensure that libcalls are emitted before a branch. 1893 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1894 Tmp1 = LegalizeOp(Tmp1); 1895 Tmp2 = Node->getOperand(2); // LHS 1896 Tmp3 = Node->getOperand(3); // RHS 1897 Tmp4 = Node->getOperand(1); // CC 1898 1899 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1900 LastCALLSEQ_END = DAG.getEntryNode(); 1901 1902 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1903 // the LHS is a legal SETCC itself. In this case, we need to compare 1904 // the result against zero to select between true and false values. 1905 if (Tmp3.Val == 0) { 1906 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1907 Tmp4 = DAG.getCondCode(ISD::SETNE); 1908 } 1909 1910 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1911 Node->getOperand(4)); 1912 1913 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1914 default: assert(0 && "Unexpected action for BR_CC!"); 1915 case TargetLowering::Legal: break; 1916 case TargetLowering::Custom: 1917 Tmp4 = TLI.LowerOperation(Result, DAG); 1918 if (Tmp4.Val) Result = Tmp4; 1919 break; 1920 } 1921 break; 1922 case ISD::LOAD: { 1923 LoadSDNode *LD = cast<LoadSDNode>(Node); 1924 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1925 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1926 1927 ISD::LoadExtType ExtType = LD->getExtensionType(); 1928 if (ExtType == ISD::NON_EXTLOAD) { 1929 MVT VT = Node->getValueType(0); 1930 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1931 Tmp3 = Result.getValue(0); 1932 Tmp4 = Result.getValue(1); 1933 1934 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1935 default: assert(0 && "This action is not supported yet!"); 1936 case TargetLowering::Legal: 1937 // If this is an unaligned load and the target doesn't support it, 1938 // expand it. 1939 if (!TLI.allowsUnalignedMemoryAccesses()) { 1940 unsigned ABIAlignment = TLI.getTargetData()-> 1941 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 1942 if (LD->getAlignment() < ABIAlignment){ 1943 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1944 TLI); 1945 Tmp3 = Result.getOperand(0); 1946 Tmp4 = Result.getOperand(1); 1947 Tmp3 = LegalizeOp(Tmp3); 1948 Tmp4 = LegalizeOp(Tmp4); 1949 } 1950 } 1951 break; 1952 case TargetLowering::Custom: 1953 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1954 if (Tmp1.Val) { 1955 Tmp3 = LegalizeOp(Tmp1); 1956 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1957 } 1958 break; 1959 case TargetLowering::Promote: { 1960 // Only promote a load of vector type to another. 1961 assert(VT.isVector() && "Cannot promote this load!"); 1962 // Change base type to a different vector type. 1963 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1964 1965 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1966 LD->getSrcValueOffset(), 1967 LD->isVolatile(), LD->getAlignment()); 1968 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1969 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1970 break; 1971 } 1972 } 1973 // Since loads produce two values, make sure to remember that we 1974 // legalized both of them. 1975 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1976 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1977 return Op.ResNo ? Tmp4 : Tmp3; 1978 } else { 1979 MVT SrcVT = LD->getMemoryVT(); 1980 unsigned SrcWidth = SrcVT.getSizeInBits(); 1981 int SVOffset = LD->getSrcValueOffset(); 1982 unsigned Alignment = LD->getAlignment(); 1983 bool isVolatile = LD->isVolatile(); 1984 1985 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1986 // Some targets pretend to have an i1 loading operation, and actually 1987 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1988 // bits are guaranteed to be zero; it helps the optimizers understand 1989 // that these bits are zero. It is also useful for EXTLOAD, since it 1990 // tells the optimizers that those bits are undefined. It would be 1991 // nice to have an effective generic way of getting these benefits... 1992 // Until such a way is found, don't insist on promoting i1 here. 1993 (SrcVT != MVT::i1 || 1994 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1995 // Promote to a byte-sized load if not loading an integral number of 1996 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1997 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1998 MVT NVT = MVT::getIntegerVT(NewWidth); 1999 SDValue Ch; 2000 2001 // The extra bits are guaranteed to be zero, since we stored them that 2002 // way. A zext load from NVT thus automatically gives zext from SrcVT. 2003 2004 ISD::LoadExtType NewExtType = 2005 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2006 2007 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 2008 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2009 NVT, isVolatile, Alignment); 2010 2011 Ch = Result.getValue(1); // The chain. 2012 2013 if (ExtType == ISD::SEXTLOAD) 2014 // Having the top bits zero doesn't help when sign extending. 2015 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2016 Result, DAG.getValueType(SrcVT)); 2017 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2018 // All the top bits are guaranteed to be zero - inform the optimizers. 2019 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 2020 DAG.getValueType(SrcVT)); 2021 2022 Tmp1 = LegalizeOp(Result); 2023 Tmp2 = LegalizeOp(Ch); 2024 } else if (SrcWidth & (SrcWidth - 1)) { 2025 // If not loading a power-of-2 number of bits, expand as two loads. 2026 assert(SrcVT.isExtended() && !SrcVT.isVector() && 2027 "Unsupported extload!"); 2028 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2029 assert(RoundWidth < SrcWidth); 2030 unsigned ExtraWidth = SrcWidth - RoundWidth; 2031 assert(ExtraWidth < RoundWidth); 2032 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2033 "Load size not an integral number of bytes!"); 2034 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2035 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2036 SDValue Lo, Hi, Ch; 2037 unsigned IncrementSize; 2038 2039 if (TLI.isLittleEndian()) { 2040 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2041 // Load the bottom RoundWidth bits. 2042 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2043 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2044 Alignment); 2045 2046 // Load the remaining ExtraWidth bits. 2047 IncrementSize = RoundWidth / 8; 2048 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2049 DAG.getIntPtrConstant(IncrementSize)); 2050 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2051 LD->getSrcValue(), SVOffset + IncrementSize, 2052 ExtraVT, isVolatile, 2053 MinAlign(Alignment, IncrementSize)); 2054 2055 // Build a factor node to remember that this load is independent of the 2056 // other one. 2057 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2058 Hi.getValue(1)); 2059 2060 // Move the top bits to the right place. 2061 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2062 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2063 2064 // Join the hi and lo parts. 2065 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2066 } else { 2067 // Big endian - avoid unaligned loads. 2068 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2069 // Load the top RoundWidth bits. 2070 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2071 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2072 Alignment); 2073 2074 // Load the remaining ExtraWidth bits. 2075 IncrementSize = RoundWidth / 8; 2076 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2077 DAG.getIntPtrConstant(IncrementSize)); 2078 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2079 LD->getSrcValue(), SVOffset + IncrementSize, 2080 ExtraVT, isVolatile, 2081 MinAlign(Alignment, IncrementSize)); 2082 2083 // Build a factor node to remember that this load is independent of the 2084 // other one. 2085 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2086 Hi.getValue(1)); 2087 2088 // Move the top bits to the right place. 2089 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2090 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2091 2092 // Join the hi and lo parts. 2093 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2094 } 2095 2096 Tmp1 = LegalizeOp(Result); 2097 Tmp2 = LegalizeOp(Ch); 2098 } else { 2099 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 2100 default: assert(0 && "This action is not supported yet!"); 2101 case TargetLowering::Custom: 2102 isCustom = true; 2103 // FALLTHROUGH 2104 case TargetLowering::Legal: 2105 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2106 Tmp1 = Result.getValue(0); 2107 Tmp2 = Result.getValue(1); 2108 2109 if (isCustom) { 2110 Tmp3 = TLI.LowerOperation(Result, DAG); 2111 if (Tmp3.Val) { 2112 Tmp1 = LegalizeOp(Tmp3); 2113 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2114 } 2115 } else { 2116 // If this is an unaligned load and the target doesn't support it, 2117 // expand it. 2118 if (!TLI.allowsUnalignedMemoryAccesses()) { 2119 unsigned ABIAlignment = TLI.getTargetData()-> 2120 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2121 if (LD->getAlignment() < ABIAlignment){ 2122 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 2123 TLI); 2124 Tmp1 = Result.getOperand(0); 2125 Tmp2 = Result.getOperand(1); 2126 Tmp1 = LegalizeOp(Tmp1); 2127 Tmp2 = LegalizeOp(Tmp2); 2128 } 2129 } 2130 } 2131 break; 2132 case TargetLowering::Expand: 2133 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2134 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2135 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2136 LD->getSrcValueOffset(), 2137 LD->isVolatile(), LD->getAlignment()); 2138 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2139 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2140 Tmp2 = LegalizeOp(Load.getValue(1)); 2141 break; 2142 } 2143 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2144 // Turn the unsupported load into an EXTLOAD followed by an explicit 2145 // zero/sign extend inreg. 2146 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2147 Tmp1, Tmp2, LD->getSrcValue(), 2148 LD->getSrcValueOffset(), SrcVT, 2149 LD->isVolatile(), LD->getAlignment()); 2150 SDValue ValRes; 2151 if (ExtType == ISD::SEXTLOAD) 2152 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2153 Result, DAG.getValueType(SrcVT)); 2154 else 2155 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2156 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2157 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2158 break; 2159 } 2160 } 2161 2162 // Since loads produce two values, make sure to remember that we legalized 2163 // both of them. 2164 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2165 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2166 return Op.ResNo ? Tmp2 : Tmp1; 2167 } 2168 } 2169 case ISD::EXTRACT_ELEMENT: { 2170 MVT OpTy = Node->getOperand(0).getValueType(); 2171 switch (getTypeAction(OpTy)) { 2172 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2173 case Legal: 2174 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 2175 // 1 -> Hi 2176 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2177 DAG.getConstant(OpTy.getSizeInBits()/2, 2178 TLI.getShiftAmountTy())); 2179 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2180 } else { 2181 // 0 -> Lo 2182 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2183 Node->getOperand(0)); 2184 } 2185 break; 2186 case Expand: 2187 // Get both the low and high parts. 2188 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2189 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 2190 Result = Tmp2; // 1 -> Hi 2191 else 2192 Result = Tmp1; // 0 -> Lo 2193 break; 2194 } 2195 break; 2196 } 2197 2198 case ISD::CopyToReg: 2199 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2200 2201 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2202 "Register type must be legal!"); 2203 // Legalize the incoming value (must be a legal type). 2204 Tmp2 = LegalizeOp(Node->getOperand(2)); 2205 if (Node->getNumValues() == 1) { 2206 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2207 } else { 2208 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2209 if (Node->getNumOperands() == 4) { 2210 Tmp3 = LegalizeOp(Node->getOperand(3)); 2211 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2212 Tmp3); 2213 } else { 2214 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2215 } 2216 2217 // Since this produces two values, make sure to remember that we legalized 2218 // both of them. 2219 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 2220 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 2221 return Result; 2222 } 2223 break; 2224 2225 case ISD::RET: 2226 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2227 2228 // Ensure that libcalls are emitted before a return. 2229 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2230 Tmp1 = LegalizeOp(Tmp1); 2231 LastCALLSEQ_END = DAG.getEntryNode(); 2232 2233 switch (Node->getNumOperands()) { 2234 case 3: // ret val 2235 Tmp2 = Node->getOperand(1); 2236 Tmp3 = Node->getOperand(2); // Signness 2237 switch (getTypeAction(Tmp2.getValueType())) { 2238 case Legal: 2239 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2240 break; 2241 case Expand: 2242 if (!Tmp2.getValueType().isVector()) { 2243 SDValue Lo, Hi; 2244 ExpandOp(Tmp2, Lo, Hi); 2245 2246 // Big endian systems want the hi reg first. 2247 if (TLI.isBigEndian()) 2248 std::swap(Lo, Hi); 2249 2250 if (Hi.Val) 2251 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2252 else 2253 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2254 Result = LegalizeOp(Result); 2255 } else { 2256 SDNode *InVal = Tmp2.Val; 2257 int InIx = Tmp2.ResNo; 2258 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 2259 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 2260 2261 // Figure out if there is a simple type corresponding to this Vector 2262 // type. If so, convert to the vector type. 2263 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2264 if (TLI.isTypeLegal(TVT)) { 2265 // Turn this into a return of the vector type. 2266 Tmp2 = LegalizeOp(Tmp2); 2267 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2268 } else if (NumElems == 1) { 2269 // Turn this into a return of the scalar type. 2270 Tmp2 = ScalarizeVectorOp(Tmp2); 2271 Tmp2 = LegalizeOp(Tmp2); 2272 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2273 2274 // FIXME: Returns of gcc generic vectors smaller than a legal type 2275 // should be returned in integer registers! 2276 2277 // The scalarized value type may not be legal, e.g. it might require 2278 // promotion or expansion. Relegalize the return. 2279 Result = LegalizeOp(Result); 2280 } else { 2281 // FIXME: Returns of gcc generic vectors larger than a legal vector 2282 // type should be returned by reference! 2283 SDValue Lo, Hi; 2284 SplitVectorOp(Tmp2, Lo, Hi); 2285 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2286 Result = LegalizeOp(Result); 2287 } 2288 } 2289 break; 2290 case Promote: 2291 Tmp2 = PromoteOp(Node->getOperand(1)); 2292 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2293 Result = LegalizeOp(Result); 2294 break; 2295 } 2296 break; 2297 case 1: // ret void 2298 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2299 break; 2300 default: { // ret <values> 2301 SmallVector<SDValue, 8> NewValues; 2302 NewValues.push_back(Tmp1); 2303 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2304 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2305 case Legal: 2306 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2307 NewValues.push_back(Node->getOperand(i+1)); 2308 break; 2309 case Expand: { 2310 SDValue Lo, Hi; 2311 assert(!Node->getOperand(i).getValueType().isExtended() && 2312 "FIXME: TODO: implement returning non-legal vector types!"); 2313 ExpandOp(Node->getOperand(i), Lo, Hi); 2314 NewValues.push_back(Lo); 2315 NewValues.push_back(Node->getOperand(i+1)); 2316 if (Hi.Val) { 2317 NewValues.push_back(Hi); 2318 NewValues.push_back(Node->getOperand(i+1)); 2319 } 2320 break; 2321 } 2322 case Promote: 2323 assert(0 && "Can't promote multiple return value yet!"); 2324 } 2325 2326 if (NewValues.size() == Node->getNumOperands()) 2327 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2328 else 2329 Result = DAG.getNode(ISD::RET, MVT::Other, 2330 &NewValues[0], NewValues.size()); 2331 break; 2332 } 2333 } 2334 2335 if (Result.getOpcode() == ISD::RET) { 2336 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2337 default: assert(0 && "This action is not supported yet!"); 2338 case TargetLowering::Legal: break; 2339 case TargetLowering::Custom: 2340 Tmp1 = TLI.LowerOperation(Result, DAG); 2341 if (Tmp1.Val) Result = Tmp1; 2342 break; 2343 } 2344 } 2345 break; 2346 case ISD::STORE: { 2347 StoreSDNode *ST = cast<StoreSDNode>(Node); 2348 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2349 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2350 int SVOffset = ST->getSrcValueOffset(); 2351 unsigned Alignment = ST->getAlignment(); 2352 bool isVolatile = ST->isVolatile(); 2353 2354 if (!ST->isTruncatingStore()) { 2355 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2356 // FIXME: We shouldn't do this for TargetConstantFP's. 2357 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2358 // to phase ordering between legalized code and the dag combiner. This 2359 // probably means that we need to integrate dag combiner and legalizer 2360 // together. 2361 // We generally can't do this one for long doubles. 2362 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2363 if (CFP->getValueType(0) == MVT::f32 && 2364 getTypeAction(MVT::i32) == Legal) { 2365 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2366 convertToAPInt().zextOrTrunc(32), 2367 MVT::i32); 2368 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2369 SVOffset, isVolatile, Alignment); 2370 break; 2371 } else if (CFP->getValueType(0) == MVT::f64) { 2372 // If this target supports 64-bit registers, do a single 64-bit store. 2373 if (getTypeAction(MVT::i64) == Legal) { 2374 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2375 zextOrTrunc(64), MVT::i64); 2376 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2377 SVOffset, isVolatile, Alignment); 2378 break; 2379 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 2380 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2381 // stores. If the target supports neither 32- nor 64-bits, this 2382 // xform is certainly not worth it. 2383 const APInt &IntVal =CFP->getValueAPF().convertToAPInt(); 2384 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2385 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2386 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2387 2388 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2389 SVOffset, isVolatile, Alignment); 2390 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2391 DAG.getIntPtrConstant(4)); 2392 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2393 isVolatile, MinAlign(Alignment, 4U)); 2394 2395 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2396 break; 2397 } 2398 } 2399 } 2400 2401 switch (getTypeAction(ST->getMemoryVT())) { 2402 case Legal: { 2403 Tmp3 = LegalizeOp(ST->getValue()); 2404 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2405 ST->getOffset()); 2406 2407 MVT VT = Tmp3.getValueType(); 2408 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2409 default: assert(0 && "This action is not supported yet!"); 2410 case TargetLowering::Legal: 2411 // If this is an unaligned store and the target doesn't support it, 2412 // expand it. 2413 if (!TLI.allowsUnalignedMemoryAccesses()) { 2414 unsigned ABIAlignment = TLI.getTargetData()-> 2415 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2416 if (ST->getAlignment() < ABIAlignment) 2417 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2418 TLI); 2419 } 2420 break; 2421 case TargetLowering::Custom: 2422 Tmp1 = TLI.LowerOperation(Result, DAG); 2423 if (Tmp1.Val) Result = Tmp1; 2424 break; 2425 case TargetLowering::Promote: 2426 assert(VT.isVector() && "Unknown legal promote case!"); 2427 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2428 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2429 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2430 ST->getSrcValue(), SVOffset, isVolatile, 2431 Alignment); 2432 break; 2433 } 2434 break; 2435 } 2436 case Promote: 2437 // Truncate the value and store the result. 2438 Tmp3 = PromoteOp(ST->getValue()); 2439 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2440 SVOffset, ST->getMemoryVT(), 2441 isVolatile, Alignment); 2442 break; 2443 2444 case Expand: 2445 unsigned IncrementSize = 0; 2446 SDValue Lo, Hi; 2447 2448 // If this is a vector type, then we have to calculate the increment as 2449 // the product of the element size in bytes, and the number of elements 2450 // in the high half of the vector. 2451 if (ST->getValue().getValueType().isVector()) { 2452 SDNode *InVal = ST->getValue().Val; 2453 int InIx = ST->getValue().ResNo; 2454 MVT InVT = InVal->getValueType(InIx); 2455 unsigned NumElems = InVT.getVectorNumElements(); 2456 MVT EVT = InVT.getVectorElementType(); 2457 2458 // Figure out if there is a simple type corresponding to this Vector 2459 // type. If so, convert to the vector type. 2460 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2461 if (TLI.isTypeLegal(TVT)) { 2462 // Turn this into a normal store of the vector type. 2463 Tmp3 = LegalizeOp(ST->getValue()); 2464 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2465 SVOffset, isVolatile, Alignment); 2466 Result = LegalizeOp(Result); 2467 break; 2468 } else if (NumElems == 1) { 2469 // Turn this into a normal store of the scalar type. 2470 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2471 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2472 SVOffset, isVolatile, Alignment); 2473 // The scalarized value type may not be legal, e.g. it might require 2474 // promotion or expansion. Relegalize the scalar store. 2475 Result = LegalizeOp(Result); 2476 break; 2477 } else { 2478 SplitVectorOp(ST->getValue(), Lo, Hi); 2479 IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() * 2480 EVT.getSizeInBits()/8; 2481 } 2482 } else { 2483 ExpandOp(ST->getValue(), Lo, Hi); 2484 IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0; 2485 2486 if (TLI.isBigEndian()) 2487 std::swap(Lo, Hi); 2488 } 2489 2490 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2491 SVOffset, isVolatile, Alignment); 2492 2493 if (Hi.Val == NULL) { 2494 // Must be int <-> float one-to-one expansion. 2495 Result = Lo; 2496 break; 2497 } 2498 2499 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2500 DAG.getIntPtrConstant(IncrementSize)); 2501 assert(isTypeLegal(Tmp2.getValueType()) && 2502 "Pointers must be legal!"); 2503 SVOffset += IncrementSize; 2504 Alignment = MinAlign(Alignment, IncrementSize); 2505 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2506 SVOffset, isVolatile, Alignment); 2507 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2508 break; 2509 } 2510 } else { 2511 switch (getTypeAction(ST->getValue().getValueType())) { 2512 case Legal: 2513 Tmp3 = LegalizeOp(ST->getValue()); 2514 break; 2515 case Promote: 2516 // We can promote the value, the truncstore will still take care of it. 2517 Tmp3 = PromoteOp(ST->getValue()); 2518 break; 2519 case Expand: 2520 // Just store the low part. This may become a non-trunc store, so make 2521 // sure to use getTruncStore, not UpdateNodeOperands below. 2522 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2523 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2524 SVOffset, MVT::i8, isVolatile, Alignment); 2525 } 2526 2527 MVT StVT = ST->getMemoryVT(); 2528 unsigned StWidth = StVT.getSizeInBits(); 2529 2530 if (StWidth != StVT.getStoreSizeInBits()) { 2531 // Promote to a byte-sized store with upper bits zero if not 2532 // storing an integral number of bytes. For example, promote 2533 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2534 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 2535 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2536 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2537 SVOffset, NVT, isVolatile, Alignment); 2538 } else if (StWidth & (StWidth - 1)) { 2539 // If not storing a power-of-2 number of bits, expand as two stores. 2540 assert(StVT.isExtended() && !StVT.isVector() && 2541 "Unsupported truncstore!"); 2542 unsigned RoundWidth = 1 << Log2_32(StWidth); 2543 assert(RoundWidth < StWidth); 2544 unsigned ExtraWidth = StWidth - RoundWidth; 2545 assert(ExtraWidth < RoundWidth); 2546 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2547 "Store size not an integral number of bytes!"); 2548 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2549 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2550 SDValue Lo, Hi; 2551 unsigned IncrementSize; 2552 2553 if (TLI.isLittleEndian()) { 2554 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2555 // Store the bottom RoundWidth bits. 2556 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2557 SVOffset, RoundVT, 2558 isVolatile, Alignment); 2559 2560 // Store the remaining ExtraWidth bits. 2561 IncrementSize = RoundWidth / 8; 2562 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2563 DAG.getIntPtrConstant(IncrementSize)); 2564 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2565 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2566 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2567 SVOffset + IncrementSize, ExtraVT, isVolatile, 2568 MinAlign(Alignment, IncrementSize)); 2569 } else { 2570 // Big endian - avoid unaligned stores. 2571 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2572 // Store the top RoundWidth bits. 2573 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2574 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2575 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2576 RoundVT, isVolatile, Alignment); 2577 2578 // Store the remaining ExtraWidth bits. 2579 IncrementSize = RoundWidth / 8; 2580 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2581 DAG.getIntPtrConstant(IncrementSize)); 2582 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2583 SVOffset + IncrementSize, ExtraVT, isVolatile, 2584 MinAlign(Alignment, IncrementSize)); 2585 } 2586 2587 // The order of the stores doesn't matter. 2588 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2589 } else { 2590 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2591 Tmp2 != ST->getBasePtr()) 2592 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2593 ST->getOffset()); 2594 2595 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2596 default: assert(0 && "This action is not supported yet!"); 2597 case TargetLowering::Legal: 2598 // If this is an unaligned store and the target doesn't support it, 2599 // expand it. 2600 if (!TLI.allowsUnalignedMemoryAccesses()) { 2601 unsigned ABIAlignment = TLI.getTargetData()-> 2602 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2603 if (ST->getAlignment() < ABIAlignment) 2604 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2605 TLI); 2606 } 2607 break; 2608 case TargetLowering::Custom: 2609 Result = TLI.LowerOperation(Result, DAG); 2610 break; 2611 case Expand: 2612 // TRUNCSTORE:i16 i32 -> STORE i16 2613 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2614 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2615 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2616 isVolatile, Alignment); 2617 break; 2618 } 2619 } 2620 } 2621 break; 2622 } 2623 case ISD::PCMARKER: 2624 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2625 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2626 break; 2627 case ISD::STACKSAVE: 2628 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2629 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2630 Tmp1 = Result.getValue(0); 2631 Tmp2 = Result.getValue(1); 2632 2633 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2634 default: assert(0 && "This action is not supported yet!"); 2635 case TargetLowering::Legal: break; 2636 case TargetLowering::Custom: 2637 Tmp3 = TLI.LowerOperation(Result, DAG); 2638 if (Tmp3.Val) { 2639 Tmp1 = LegalizeOp(Tmp3); 2640 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2641 } 2642 break; 2643 case TargetLowering::Expand: 2644 // Expand to CopyFromReg if the target set 2645 // StackPointerRegisterToSaveRestore. 2646 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2647 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2648 Node->getValueType(0)); 2649 Tmp2 = Tmp1.getValue(1); 2650 } else { 2651 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2652 Tmp2 = Node->getOperand(0); 2653 } 2654 break; 2655 } 2656 2657 // Since stacksave produce two values, make sure to remember that we 2658 // legalized both of them. 2659 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2660 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2661 return Op.ResNo ? Tmp2 : Tmp1; 2662 2663 case ISD::STACKRESTORE: 2664 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2665 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2666 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2667 2668 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2669 default: assert(0 && "This action is not supported yet!"); 2670 case TargetLowering::Legal: break; 2671 case TargetLowering::Custom: 2672 Tmp1 = TLI.LowerOperation(Result, DAG); 2673 if (Tmp1.Val) Result = Tmp1; 2674 break; 2675 case TargetLowering::Expand: 2676 // Expand to CopyToReg if the target set 2677 // StackPointerRegisterToSaveRestore. 2678 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2679 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2680 } else { 2681 Result = Tmp1; 2682 } 2683 break; 2684 } 2685 break; 2686 2687 case ISD::READCYCLECOUNTER: 2688 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2689 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2690 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2691 Node->getValueType(0))) { 2692 default: assert(0 && "This action is not supported yet!"); 2693 case TargetLowering::Legal: 2694 Tmp1 = Result.getValue(0); 2695 Tmp2 = Result.getValue(1); 2696 break; 2697 case TargetLowering::Custom: 2698 Result = TLI.LowerOperation(Result, DAG); 2699 Tmp1 = LegalizeOp(Result.getValue(0)); 2700 Tmp2 = LegalizeOp(Result.getValue(1)); 2701 break; 2702 } 2703 2704 // Since rdcc produce two values, make sure to remember that we legalized 2705 // both of them. 2706 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2707 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2708 return Result; 2709 2710 case ISD::SELECT: 2711 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2712 case Expand: assert(0 && "It's impossible to expand bools"); 2713 case Legal: 2714 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2715 break; 2716 case Promote: { 2717 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2718 // Make sure the condition is either zero or one. 2719 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2720 if (!DAG.MaskedValueIsZero(Tmp1, 2721 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2722 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2723 break; 2724 } 2725 } 2726 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2727 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2728 2729 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2730 2731 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2732 default: assert(0 && "This action is not supported yet!"); 2733 case TargetLowering::Legal: break; 2734 case TargetLowering::Custom: { 2735 Tmp1 = TLI.LowerOperation(Result, DAG); 2736 if (Tmp1.Val) Result = Tmp1; 2737 break; 2738 } 2739 case TargetLowering::Expand: 2740 if (Tmp1.getOpcode() == ISD::SETCC) { 2741 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2742 Tmp2, Tmp3, 2743 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2744 } else { 2745 Result = DAG.getSelectCC(Tmp1, 2746 DAG.getConstant(0, Tmp1.getValueType()), 2747 Tmp2, Tmp3, ISD::SETNE); 2748 } 2749 break; 2750 case TargetLowering::Promote: { 2751 MVT NVT = 2752 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2753 unsigned ExtOp, TruncOp; 2754 if (Tmp2.getValueType().isVector()) { 2755 ExtOp = ISD::BIT_CONVERT; 2756 TruncOp = ISD::BIT_CONVERT; 2757 } else if (Tmp2.getValueType().isInteger()) { 2758 ExtOp = ISD::ANY_EXTEND; 2759 TruncOp = ISD::TRUNCATE; 2760 } else { 2761 ExtOp = ISD::FP_EXTEND; 2762 TruncOp = ISD::FP_ROUND; 2763 } 2764 // Promote each of the values to the new type. 2765 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2766 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2767 // Perform the larger operation, then round down. 2768 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2769 if (TruncOp != ISD::FP_ROUND) 2770 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2771 else 2772 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2773 DAG.getIntPtrConstant(0)); 2774 break; 2775 } 2776 } 2777 break; 2778 case ISD::SELECT_CC: { 2779 Tmp1 = Node->getOperand(0); // LHS 2780 Tmp2 = Node->getOperand(1); // RHS 2781 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2782 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2783 SDValue CC = Node->getOperand(4); 2784 2785 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2786 2787 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2788 // the LHS is a legal SETCC itself. In this case, we need to compare 2789 // the result against zero to select between true and false values. 2790 if (Tmp2.Val == 0) { 2791 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2792 CC = DAG.getCondCode(ISD::SETNE); 2793 } 2794 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2795 2796 // Everything is legal, see if we should expand this op or something. 2797 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2798 default: assert(0 && "This action is not supported yet!"); 2799 case TargetLowering::Legal: break; 2800 case TargetLowering::Custom: 2801 Tmp1 = TLI.LowerOperation(Result, DAG); 2802 if (Tmp1.Val) Result = Tmp1; 2803 break; 2804 } 2805 break; 2806 } 2807 case ISD::SETCC: 2808 Tmp1 = Node->getOperand(0); 2809 Tmp2 = Node->getOperand(1); 2810 Tmp3 = Node->getOperand(2); 2811 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2812 2813 // If we had to Expand the SetCC operands into a SELECT node, then it may 2814 // not always be possible to return a true LHS & RHS. In this case, just 2815 // return the value we legalized, returned in the LHS 2816 if (Tmp2.Val == 0) { 2817 Result = Tmp1; 2818 break; 2819 } 2820 2821 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2822 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2823 case TargetLowering::Custom: 2824 isCustom = true; 2825 // FALLTHROUGH. 2826 case TargetLowering::Legal: 2827 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2828 if (isCustom) { 2829 Tmp4 = TLI.LowerOperation(Result, DAG); 2830 if (Tmp4.Val) Result = Tmp4; 2831 } 2832 break; 2833 case TargetLowering::Promote: { 2834 // First step, figure out the appropriate operation to use. 2835 // Allow SETCC to not be supported for all legal data types 2836 // Mostly this targets FP 2837 MVT NewInTy = Node->getOperand(0).getValueType(); 2838 MVT OldVT = NewInTy; OldVT = OldVT; 2839 2840 // Scan for the appropriate larger type to use. 2841 while (1) { 2842 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 2843 2844 assert(NewInTy.isInteger() == OldVT.isInteger() && 2845 "Fell off of the edge of the integer world"); 2846 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 2847 "Fell off of the edge of the floating point world"); 2848 2849 // If the target supports SETCC of this type, use it. 2850 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2851 break; 2852 } 2853 if (NewInTy.isInteger()) 2854 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2855 else { 2856 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2857 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2858 } 2859 Tmp1 = LegalizeOp(Tmp1); 2860 Tmp2 = LegalizeOp(Tmp2); 2861 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2862 Result = LegalizeOp(Result); 2863 break; 2864 } 2865 case TargetLowering::Expand: 2866 // Expand a setcc node into a select_cc of the same condition, lhs, and 2867 // rhs that selects between const 1 (true) and const 0 (false). 2868 MVT VT = Node->getValueType(0); 2869 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2870 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2871 Tmp3); 2872 break; 2873 } 2874 break; 2875 case ISD::VSETCC: { 2876 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2877 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2878 SDValue CC = Node->getOperand(2); 2879 2880 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC); 2881 2882 // Everything is legal, see if we should expand this op or something. 2883 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) { 2884 default: assert(0 && "This action is not supported yet!"); 2885 case TargetLowering::Legal: break; 2886 case TargetLowering::Custom: 2887 Tmp1 = TLI.LowerOperation(Result, DAG); 2888 if (Tmp1.Val) Result = Tmp1; 2889 break; 2890 } 2891 break; 2892 } 2893 2894 case ISD::SHL_PARTS: 2895 case ISD::SRA_PARTS: 2896 case ISD::SRL_PARTS: { 2897 SmallVector<SDValue, 8> Ops; 2898 bool Changed = false; 2899 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2900 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2901 Changed |= Ops.back() != Node->getOperand(i); 2902 } 2903 if (Changed) 2904 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2905 2906 switch (TLI.getOperationAction(Node->getOpcode(), 2907 Node->getValueType(0))) { 2908 default: assert(0 && "This action is not supported yet!"); 2909 case TargetLowering::Legal: break; 2910 case TargetLowering::Custom: 2911 Tmp1 = TLI.LowerOperation(Result, DAG); 2912 if (Tmp1.Val) { 2913 SDValue Tmp2, RetVal(0, 0); 2914 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2915 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2916 AddLegalizedOperand(SDValue(Node, i), Tmp2); 2917 if (i == Op.ResNo) 2918 RetVal = Tmp2; 2919 } 2920 assert(RetVal.Val && "Illegal result number"); 2921 return RetVal; 2922 } 2923 break; 2924 } 2925 2926 // Since these produce multiple values, make sure to remember that we 2927 // legalized all of them. 2928 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2929 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i)); 2930 return Result.getValue(Op.ResNo); 2931 } 2932 2933 // Binary operators 2934 case ISD::ADD: 2935 case ISD::SUB: 2936 case ISD::MUL: 2937 case ISD::MULHS: 2938 case ISD::MULHU: 2939 case ISD::UDIV: 2940 case ISD::SDIV: 2941 case ISD::AND: 2942 case ISD::OR: 2943 case ISD::XOR: 2944 case ISD::SHL: 2945 case ISD::SRL: 2946 case ISD::SRA: 2947 case ISD::FADD: 2948 case ISD::FSUB: 2949 case ISD::FMUL: 2950 case ISD::FDIV: 2951 case ISD::FPOW: 2952 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2953 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2954 case Expand: assert(0 && "Not possible"); 2955 case Legal: 2956 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2957 break; 2958 case Promote: 2959 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2960 break; 2961 } 2962 2963 if ((Node->getOpcode() == ISD::SHL || 2964 Node->getOpcode() == ISD::SRL || 2965 Node->getOpcode() == ISD::SRA) && 2966 !Node->getValueType(0).isVector()) { 2967 if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType())) 2968 Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2); 2969 else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType())) 2970 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2); 2971 } 2972 2973 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2974 2975 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2976 default: assert(0 && "BinOp legalize operation not supported"); 2977 case TargetLowering::Legal: break; 2978 case TargetLowering::Custom: 2979 Tmp1 = TLI.LowerOperation(Result, DAG); 2980 if (Tmp1.Val) { 2981 Result = Tmp1; 2982 break; 2983 } 2984 // Fall through if the custom lower can't deal with the operation 2985 case TargetLowering::Expand: { 2986 MVT VT = Op.getValueType(); 2987 2988 // See if multiply or divide can be lowered using two-result operations. 2989 SDVTList VTs = DAG.getVTList(VT, VT); 2990 if (Node->getOpcode() == ISD::MUL) { 2991 // We just need the low half of the multiply; try both the signed 2992 // and unsigned forms. If the target supports both SMUL_LOHI and 2993 // UMUL_LOHI, form a preference by checking which forms of plain 2994 // MULH it supports. 2995 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2996 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2997 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2998 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2999 unsigned OpToUse = 0; 3000 if (HasSMUL_LOHI && !HasMULHS) { 3001 OpToUse = ISD::SMUL_LOHI; 3002 } else if (HasUMUL_LOHI && !HasMULHU) { 3003 OpToUse = ISD::UMUL_LOHI; 3004 } else if (HasSMUL_LOHI) { 3005 OpToUse = ISD::SMUL_LOHI; 3006 } else if (HasUMUL_LOHI) { 3007 OpToUse = ISD::UMUL_LOHI; 3008 } 3009 if (OpToUse) { 3010 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 3011 break; 3012 } 3013 } 3014 if (Node->getOpcode() == ISD::MULHS && 3015 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 3016 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3017 break; 3018 } 3019 if (Node->getOpcode() == ISD::MULHU && 3020 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 3021 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3022 break; 3023 } 3024 if (Node->getOpcode() == ISD::SDIV && 3025 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3026 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3027 break; 3028 } 3029 if (Node->getOpcode() == ISD::UDIV && 3030 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3031 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3032 break; 3033 } 3034 3035 // Check to see if we have a libcall for this operator. 3036 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3037 bool isSigned = false; 3038 switch (Node->getOpcode()) { 3039 case ISD::UDIV: 3040 case ISD::SDIV: 3041 if (VT == MVT::i32) { 3042 LC = Node->getOpcode() == ISD::UDIV 3043 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3044 isSigned = Node->getOpcode() == ISD::SDIV; 3045 } 3046 break; 3047 case ISD::FPOW: 3048 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3049 RTLIB::POW_PPCF128); 3050 break; 3051 default: break; 3052 } 3053 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3054 SDValue Dummy; 3055 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3056 break; 3057 } 3058 3059 assert(Node->getValueType(0).isVector() && 3060 "Cannot expand this binary operator!"); 3061 // Expand the operation into a bunch of nasty scalar code. 3062 Result = LegalizeOp(UnrollVectorOp(Op)); 3063 break; 3064 } 3065 case TargetLowering::Promote: { 3066 switch (Node->getOpcode()) { 3067 default: assert(0 && "Do not know how to promote this BinOp!"); 3068 case ISD::AND: 3069 case ISD::OR: 3070 case ISD::XOR: { 3071 MVT OVT = Node->getValueType(0); 3072 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3073 assert(OVT.isVector() && "Cannot promote this BinOp!"); 3074 // Bit convert each of the values to the new type. 3075 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3076 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3077 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3078 // Bit convert the result back the original type. 3079 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3080 break; 3081 } 3082 } 3083 } 3084 } 3085 break; 3086 3087 case ISD::SMUL_LOHI: 3088 case ISD::UMUL_LOHI: 3089 case ISD::SDIVREM: 3090 case ISD::UDIVREM: 3091 // These nodes will only be produced by target-specific lowering, so 3092 // they shouldn't be here if they aren't legal. 3093 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3094 "This must be legal!"); 3095 3096 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3097 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3098 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3099 break; 3100 3101 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3102 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3103 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3104 case Expand: assert(0 && "Not possible"); 3105 case Legal: 3106 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3107 break; 3108 case Promote: 3109 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3110 break; 3111 } 3112 3113 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3114 3115 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3116 default: assert(0 && "Operation not supported"); 3117 case TargetLowering::Custom: 3118 Tmp1 = TLI.LowerOperation(Result, DAG); 3119 if (Tmp1.Val) Result = Tmp1; 3120 break; 3121 case TargetLowering::Legal: break; 3122 case TargetLowering::Expand: { 3123 // If this target supports fabs/fneg natively and select is cheap, 3124 // do this efficiently. 3125 if (!TLI.isSelectExpensive() && 3126 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3127 TargetLowering::Legal && 3128 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3129 TargetLowering::Legal) { 3130 // Get the sign bit of the RHS. 3131 MVT IVT = 3132 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3133 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3134 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), 3135 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3136 // Get the absolute value of the result. 3137 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3138 // Select between the nabs and abs value based on the sign bit of 3139 // the input. 3140 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3141 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3142 AbsVal), 3143 AbsVal); 3144 Result = LegalizeOp(Result); 3145 break; 3146 } 3147 3148 // Otherwise, do bitwise ops! 3149 MVT NVT = 3150 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3151 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3152 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3153 Result = LegalizeOp(Result); 3154 break; 3155 } 3156 } 3157 break; 3158 3159 case ISD::ADDC: 3160 case ISD::SUBC: 3161 Tmp1 = LegalizeOp(Node->getOperand(0)); 3162 Tmp2 = LegalizeOp(Node->getOperand(1)); 3163 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3164 // Since this produces two values, make sure to remember that we legalized 3165 // both of them. 3166 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 3167 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 3168 return Result; 3169 3170 case ISD::ADDE: 3171 case ISD::SUBE: 3172 Tmp1 = LegalizeOp(Node->getOperand(0)); 3173 Tmp2 = LegalizeOp(Node->getOperand(1)); 3174 Tmp3 = LegalizeOp(Node->getOperand(2)); 3175 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3176 // Since this produces two values, make sure to remember that we legalized 3177 // both of them. 3178 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 3179 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 3180 return Result; 3181 3182 case ISD::BUILD_PAIR: { 3183 MVT PairTy = Node->getValueType(0); 3184 // TODO: handle the case where the Lo and Hi operands are not of legal type 3185 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3186 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3187 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3188 case TargetLowering::Promote: 3189 case TargetLowering::Custom: 3190 assert(0 && "Cannot promote/custom this yet!"); 3191 case TargetLowering::Legal: 3192 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3193 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3194 break; 3195 case TargetLowering::Expand: 3196 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3197 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3198 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3199 DAG.getConstant(PairTy.getSizeInBits()/2, 3200 TLI.getShiftAmountTy())); 3201 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3202 break; 3203 } 3204 break; 3205 } 3206 3207 case ISD::UREM: 3208 case ISD::SREM: 3209 case ISD::FREM: 3210 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3211 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3212 3213 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3214 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3215 case TargetLowering::Custom: 3216 isCustom = true; 3217 // FALLTHROUGH 3218 case TargetLowering::Legal: 3219 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3220 if (isCustom) { 3221 Tmp1 = TLI.LowerOperation(Result, DAG); 3222 if (Tmp1.Val) Result = Tmp1; 3223 } 3224 break; 3225 case TargetLowering::Expand: { 3226 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3227 bool isSigned = DivOpc == ISD::SDIV; 3228 MVT VT = Node->getValueType(0); 3229 3230 // See if remainder can be lowered using two-result operations. 3231 SDVTList VTs = DAG.getVTList(VT, VT); 3232 if (Node->getOpcode() == ISD::SREM && 3233 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3234 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3235 break; 3236 } 3237 if (Node->getOpcode() == ISD::UREM && 3238 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3239 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3240 break; 3241 } 3242 3243 if (VT.isInteger()) { 3244 if (TLI.getOperationAction(DivOpc, VT) == 3245 TargetLowering::Legal) { 3246 // X % Y -> X-X/Y*Y 3247 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3248 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3249 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3250 } else if (VT.isVector()) { 3251 Result = LegalizeOp(UnrollVectorOp(Op)); 3252 } else { 3253 assert(VT == MVT::i32 && 3254 "Cannot expand this binary operator!"); 3255 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3256 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3257 SDValue Dummy; 3258 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3259 } 3260 } else { 3261 assert(VT.isFloatingPoint() && 3262 "remainder op must have integer or floating-point type"); 3263 if (VT.isVector()) { 3264 Result = LegalizeOp(UnrollVectorOp(Op)); 3265 } else { 3266 // Floating point mod -> fmod libcall. 3267 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3268 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3269 SDValue Dummy; 3270 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3271 } 3272 } 3273 break; 3274 } 3275 } 3276 break; 3277 case ISD::VAARG: { 3278 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3279 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3280 3281 MVT VT = Node->getValueType(0); 3282 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3283 default: assert(0 && "This action is not supported yet!"); 3284 case TargetLowering::Custom: 3285 isCustom = true; 3286 // FALLTHROUGH 3287 case TargetLowering::Legal: 3288 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3289 Result = Result.getValue(0); 3290 Tmp1 = Result.getValue(1); 3291 3292 if (isCustom) { 3293 Tmp2 = TLI.LowerOperation(Result, DAG); 3294 if (Tmp2.Val) { 3295 Result = LegalizeOp(Tmp2); 3296 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3297 } 3298 } 3299 break; 3300 case TargetLowering::Expand: { 3301 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3302 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3303 // Increment the pointer, VAList, to the next vaarg 3304 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3305 DAG.getConstant(VT.getSizeInBits()/8, 3306 TLI.getPointerTy())); 3307 // Store the incremented VAList to the legalized pointer 3308 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3309 // Load the actual argument out of the pointer VAList 3310 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3311 Tmp1 = LegalizeOp(Result.getValue(1)); 3312 Result = LegalizeOp(Result); 3313 break; 3314 } 3315 } 3316 // Since VAARG produces two values, make sure to remember that we 3317 // legalized both of them. 3318 AddLegalizedOperand(SDValue(Node, 0), Result); 3319 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 3320 return Op.ResNo ? Tmp1 : Result; 3321 } 3322 3323 case ISD::VACOPY: 3324 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3325 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3326 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3327 3328 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3329 default: assert(0 && "This action is not supported yet!"); 3330 case TargetLowering::Custom: 3331 isCustom = true; 3332 // FALLTHROUGH 3333 case TargetLowering::Legal: 3334 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3335 Node->getOperand(3), Node->getOperand(4)); 3336 if (isCustom) { 3337 Tmp1 = TLI.LowerOperation(Result, DAG); 3338 if (Tmp1.Val) Result = Tmp1; 3339 } 3340 break; 3341 case TargetLowering::Expand: 3342 // This defaults to loading a pointer from the input and storing it to the 3343 // output, returning the chain. 3344 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3345 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3346 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0); 3347 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0); 3348 break; 3349 } 3350 break; 3351 3352 case ISD::VAEND: 3353 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3354 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3355 3356 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3357 default: assert(0 && "This action is not supported yet!"); 3358 case TargetLowering::Custom: 3359 isCustom = true; 3360 // FALLTHROUGH 3361 case TargetLowering::Legal: 3362 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3363 if (isCustom) { 3364 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3365 if (Tmp1.Val) Result = Tmp1; 3366 } 3367 break; 3368 case TargetLowering::Expand: 3369 Result = Tmp1; // Default to a no-op, return the chain 3370 break; 3371 } 3372 break; 3373 3374 case ISD::VASTART: 3375 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3376 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3377 3378 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3379 3380 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3381 default: assert(0 && "This action is not supported yet!"); 3382 case TargetLowering::Legal: break; 3383 case TargetLowering::Custom: 3384 Tmp1 = TLI.LowerOperation(Result, DAG); 3385 if (Tmp1.Val) Result = Tmp1; 3386 break; 3387 } 3388 break; 3389 3390 case ISD::ROTL: 3391 case ISD::ROTR: 3392 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3393 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3394 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3395 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3396 default: 3397 assert(0 && "ROTL/ROTR legalize operation not supported"); 3398 break; 3399 case TargetLowering::Legal: 3400 break; 3401 case TargetLowering::Custom: 3402 Tmp1 = TLI.LowerOperation(Result, DAG); 3403 if (Tmp1.Val) Result = Tmp1; 3404 break; 3405 case TargetLowering::Promote: 3406 assert(0 && "Do not know how to promote ROTL/ROTR"); 3407 break; 3408 case TargetLowering::Expand: 3409 assert(0 && "Do not know how to expand ROTL/ROTR"); 3410 break; 3411 } 3412 break; 3413 3414 case ISD::BSWAP: 3415 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3416 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3417 case TargetLowering::Custom: 3418 assert(0 && "Cannot custom legalize this yet!"); 3419 case TargetLowering::Legal: 3420 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3421 break; 3422 case TargetLowering::Promote: { 3423 MVT OVT = Tmp1.getValueType(); 3424 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3425 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3426 3427 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3428 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3429 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3430 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3431 break; 3432 } 3433 case TargetLowering::Expand: 3434 Result = ExpandBSWAP(Tmp1); 3435 break; 3436 } 3437 break; 3438 3439 case ISD::CTPOP: 3440 case ISD::CTTZ: 3441 case ISD::CTLZ: 3442 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3443 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3444 case TargetLowering::Custom: 3445 case TargetLowering::Legal: 3446 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3447 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3448 TargetLowering::Custom) { 3449 Tmp1 = TLI.LowerOperation(Result, DAG); 3450 if (Tmp1.Val) { 3451 Result = Tmp1; 3452 } 3453 } 3454 break; 3455 case TargetLowering::Promote: { 3456 MVT OVT = Tmp1.getValueType(); 3457 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3458 3459 // Zero extend the argument. 3460 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3461 // Perform the larger operation, then subtract if needed. 3462 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3463 switch (Node->getOpcode()) { 3464 case ISD::CTPOP: 3465 Result = Tmp1; 3466 break; 3467 case ISD::CTTZ: 3468 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3469 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 3470 DAG.getConstant(NVT.getSizeInBits(), NVT), 3471 ISD::SETEQ); 3472 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3473 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3474 break; 3475 case ISD::CTLZ: 3476 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3477 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3478 DAG.getConstant(NVT.getSizeInBits() - 3479 OVT.getSizeInBits(), NVT)); 3480 break; 3481 } 3482 break; 3483 } 3484 case TargetLowering::Expand: 3485 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3486 break; 3487 } 3488 break; 3489 3490 // Unary operators 3491 case ISD::FABS: 3492 case ISD::FNEG: 3493 case ISD::FSQRT: 3494 case ISD::FSIN: 3495 case ISD::FCOS: 3496 case ISD::FTRUNC: 3497 case ISD::FFLOOR: 3498 case ISD::FCEIL: 3499 case ISD::FRINT: 3500 case ISD::FNEARBYINT: 3501 Tmp1 = LegalizeOp(Node->getOperand(0)); 3502 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3503 case TargetLowering::Promote: 3504 case TargetLowering::Custom: 3505 isCustom = true; 3506 // FALLTHROUGH 3507 case TargetLowering::Legal: 3508 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3509 if (isCustom) { 3510 Tmp1 = TLI.LowerOperation(Result, DAG); 3511 if (Tmp1.Val) Result = Tmp1; 3512 } 3513 break; 3514 case TargetLowering::Expand: 3515 switch (Node->getOpcode()) { 3516 default: assert(0 && "Unreachable!"); 3517 case ISD::FNEG: 3518 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3519 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3520 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3521 break; 3522 case ISD::FABS: { 3523 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3524 MVT VT = Node->getValueType(0); 3525 Tmp2 = DAG.getConstantFP(0.0, VT); 3526 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 3527 ISD::SETUGT); 3528 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3529 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3530 break; 3531 } 3532 case ISD::FTRUNC: 3533 case ISD::FFLOOR: 3534 case ISD::FCEIL: 3535 case ISD::FRINT: 3536 case ISD::FNEARBYINT: 3537 case ISD::FSQRT: 3538 case ISD::FSIN: 3539 case ISD::FCOS: { 3540 MVT VT = Node->getValueType(0); 3541 3542 // Expand unsupported unary vector operators by unrolling them. 3543 if (VT.isVector()) { 3544 Result = LegalizeOp(UnrollVectorOp(Op)); 3545 break; 3546 } 3547 3548 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3549 switch(Node->getOpcode()) { 3550 case ISD::FSQRT: 3551 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3552 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3553 break; 3554 case ISD::FSIN: 3555 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3556 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3557 break; 3558 case ISD::FCOS: 3559 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3560 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3561 break; 3562 case ISD::FTRUNC: 3563 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 3564 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 3565 break; 3566 case ISD::FFLOOR: 3567 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 3568 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 3569 break; 3570 case ISD::FCEIL: 3571 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 3572 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 3573 break; 3574 case ISD::FRINT: 3575 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 3576 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 3577 break; 3578 case ISD::FNEARBYINT: 3579 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 3580 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 3581 break; 3582 default: assert(0 && "Unreachable!"); 3583 } 3584 SDValue Dummy; 3585 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3586 break; 3587 } 3588 } 3589 break; 3590 } 3591 break; 3592 case ISD::FPOWI: { 3593 MVT VT = Node->getValueType(0); 3594 3595 // Expand unsupported unary vector operators by unrolling them. 3596 if (VT.isVector()) { 3597 Result = LegalizeOp(UnrollVectorOp(Op)); 3598 break; 3599 } 3600 3601 // We always lower FPOWI into a libcall. No target support for it yet. 3602 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3603 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3604 SDValue Dummy; 3605 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3606 break; 3607 } 3608 case ISD::BIT_CONVERT: 3609 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3610 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3611 Node->getValueType(0)); 3612 } else if (Op.getOperand(0).getValueType().isVector()) { 3613 // The input has to be a vector type, we have to either scalarize it, pack 3614 // it, or convert it based on whether the input vector type is legal. 3615 SDNode *InVal = Node->getOperand(0).Val; 3616 int InIx = Node->getOperand(0).ResNo; 3617 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 3618 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 3619 3620 // Figure out if there is a simple type corresponding to this Vector 3621 // type. If so, convert to the vector type. 3622 MVT TVT = MVT::getVectorVT(EVT, NumElems); 3623 if (TLI.isTypeLegal(TVT)) { 3624 // Turn this into a bit convert of the vector input. 3625 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3626 LegalizeOp(Node->getOperand(0))); 3627 break; 3628 } else if (NumElems == 1) { 3629 // Turn this into a bit convert of the scalar input. 3630 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3631 ScalarizeVectorOp(Node->getOperand(0))); 3632 break; 3633 } else { 3634 // FIXME: UNIMP! Store then reload 3635 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3636 } 3637 } else { 3638 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3639 Node->getOperand(0).getValueType())) { 3640 default: assert(0 && "Unknown operation action!"); 3641 case TargetLowering::Expand: 3642 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3643 Node->getValueType(0)); 3644 break; 3645 case TargetLowering::Legal: 3646 Tmp1 = LegalizeOp(Node->getOperand(0)); 3647 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3648 break; 3649 } 3650 } 3651 break; 3652 3653 // Conversion operators. The source and destination have different types. 3654 case ISD::SINT_TO_FP: 3655 case ISD::UINT_TO_FP: { 3656 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3657 Result = LegalizeINT_TO_FP(Result, isSigned, 3658 Node->getValueType(0), Node->getOperand(0)); 3659 break; 3660 } 3661 case ISD::TRUNCATE: 3662 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3663 case Legal: 3664 Tmp1 = LegalizeOp(Node->getOperand(0)); 3665 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3666 break; 3667 case Expand: 3668 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3669 3670 // Since the result is legal, we should just be able to truncate the low 3671 // part of the source. 3672 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3673 break; 3674 case Promote: 3675 Result = PromoteOp(Node->getOperand(0)); 3676 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3677 break; 3678 } 3679 break; 3680 3681 case ISD::FP_TO_SINT: 3682 case ISD::FP_TO_UINT: 3683 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3684 case Legal: 3685 Tmp1 = LegalizeOp(Node->getOperand(0)); 3686 3687 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3688 default: assert(0 && "Unknown operation action!"); 3689 case TargetLowering::Custom: 3690 isCustom = true; 3691 // FALLTHROUGH 3692 case TargetLowering::Legal: 3693 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3694 if (isCustom) { 3695 Tmp1 = TLI.LowerOperation(Result, DAG); 3696 if (Tmp1.Val) Result = Tmp1; 3697 } 3698 break; 3699 case TargetLowering::Promote: 3700 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3701 Node->getOpcode() == ISD::FP_TO_SINT); 3702 break; 3703 case TargetLowering::Expand: 3704 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3705 SDValue True, False; 3706 MVT VT = Node->getOperand(0).getValueType(); 3707 MVT NVT = Node->getValueType(0); 3708 const uint64_t zero[] = {0, 0}; 3709 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 3710 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 3711 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 3712 Tmp2 = DAG.getConstantFP(apf, VT); 3713 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), 3714 Node->getOperand(0), Tmp2, ISD::SETLT); 3715 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3716 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3717 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3718 Tmp2)); 3719 False = DAG.getNode(ISD::XOR, NVT, False, 3720 DAG.getConstant(x, NVT)); 3721 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3722 break; 3723 } else { 3724 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3725 } 3726 break; 3727 } 3728 break; 3729 case Expand: { 3730 MVT VT = Op.getValueType(); 3731 MVT OVT = Node->getOperand(0).getValueType(); 3732 // Convert ppcf128 to i32 3733 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3734 if (Node->getOpcode() == ISD::FP_TO_SINT) { 3735 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 3736 Node->getOperand(0), DAG.getValueType(MVT::f64)); 3737 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 3738 DAG.getIntPtrConstant(1)); 3739 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 3740 } else { 3741 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3742 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3743 Tmp2 = DAG.getConstantFP(apf, OVT); 3744 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3745 // FIXME: generated code sucks. 3746 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3747 DAG.getNode(ISD::ADD, MVT::i32, 3748 DAG.getNode(ISD::FP_TO_SINT, VT, 3749 DAG.getNode(ISD::FSUB, OVT, 3750 Node->getOperand(0), Tmp2)), 3751 DAG.getConstant(0x80000000, MVT::i32)), 3752 DAG.getNode(ISD::FP_TO_SINT, VT, 3753 Node->getOperand(0)), 3754 DAG.getCondCode(ISD::SETGE)); 3755 } 3756 break; 3757 } 3758 // Convert f32 / f64 to i32 / i64 / i128. 3759 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ? 3760 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT); 3761 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!"); 3762 SDValue Dummy; 3763 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3764 break; 3765 } 3766 case Promote: 3767 Tmp1 = PromoteOp(Node->getOperand(0)); 3768 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3769 Result = LegalizeOp(Result); 3770 break; 3771 } 3772 break; 3773 3774 case ISD::FP_EXTEND: { 3775 MVT DstVT = Op.getValueType(); 3776 MVT SrcVT = Op.getOperand(0).getValueType(); 3777 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3778 // The only other way we can lower this is to turn it into a STORE, 3779 // LOAD pair, targetting a temporary location (a stack slot). 3780 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 3781 break; 3782 } 3783 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3784 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3785 case Legal: 3786 Tmp1 = LegalizeOp(Node->getOperand(0)); 3787 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3788 break; 3789 case Promote: 3790 Tmp1 = PromoteOp(Node->getOperand(0)); 3791 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3792 break; 3793 } 3794 break; 3795 } 3796 case ISD::FP_ROUND: { 3797 MVT DstVT = Op.getValueType(); 3798 MVT SrcVT = Op.getOperand(0).getValueType(); 3799 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3800 if (SrcVT == MVT::ppcf128) { 3801 SDValue Lo; 3802 ExpandOp(Node->getOperand(0), Lo, Result); 3803 // Round it the rest of the way (e.g. to f32) if needed. 3804 if (DstVT!=MVT::f64) 3805 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 3806 break; 3807 } 3808 // The only other way we can lower this is to turn it into a STORE, 3809 // LOAD pair, targetting a temporary location (a stack slot). 3810 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 3811 break; 3812 } 3813 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3814 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3815 case Legal: 3816 Tmp1 = LegalizeOp(Node->getOperand(0)); 3817 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3818 break; 3819 case Promote: 3820 Tmp1 = PromoteOp(Node->getOperand(0)); 3821 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 3822 Node->getOperand(1)); 3823 break; 3824 } 3825 break; 3826 } 3827 case ISD::ANY_EXTEND: 3828 case ISD::ZERO_EXTEND: 3829 case ISD::SIGN_EXTEND: 3830 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3831 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3832 case Legal: 3833 Tmp1 = LegalizeOp(Node->getOperand(0)); 3834 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3835 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3836 TargetLowering::Custom) { 3837 Tmp1 = TLI.LowerOperation(Result, DAG); 3838 if (Tmp1.Val) Result = Tmp1; 3839 } 3840 break; 3841 case Promote: 3842 switch (Node->getOpcode()) { 3843 case ISD::ANY_EXTEND: 3844 Tmp1 = PromoteOp(Node->getOperand(0)); 3845 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3846 break; 3847 case ISD::ZERO_EXTEND: 3848 Result = PromoteOp(Node->getOperand(0)); 3849 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3850 Result = DAG.getZeroExtendInReg(Result, 3851 Node->getOperand(0).getValueType()); 3852 break; 3853 case ISD::SIGN_EXTEND: 3854 Result = PromoteOp(Node->getOperand(0)); 3855 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3856 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3857 Result, 3858 DAG.getValueType(Node->getOperand(0).getValueType())); 3859 break; 3860 } 3861 } 3862 break; 3863 case ISD::FP_ROUND_INREG: 3864 case ISD::SIGN_EXTEND_INREG: { 3865 Tmp1 = LegalizeOp(Node->getOperand(0)); 3866 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3867 3868 // If this operation is not supported, convert it to a shl/shr or load/store 3869 // pair. 3870 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3871 default: assert(0 && "This action not supported for this op yet!"); 3872 case TargetLowering::Legal: 3873 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3874 break; 3875 case TargetLowering::Expand: 3876 // If this is an integer extend and shifts are supported, do that. 3877 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3878 // NOTE: we could fall back on load/store here too for targets without 3879 // SAR. However, it is doubtful that any exist. 3880 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 3881 ExtraVT.getSizeInBits(); 3882 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3883 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3884 Node->getOperand(0), ShiftCst); 3885 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3886 Result, ShiftCst); 3887 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3888 // The only way we can lower this is to turn it into a TRUNCSTORE, 3889 // EXTLOAD pair, targetting a temporary location (a stack slot). 3890 3891 // NOTE: there is a choice here between constantly creating new stack 3892 // slots and always reusing the same one. We currently always create 3893 // new ones, as reuse may inhibit scheduling. 3894 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 3895 Node->getValueType(0)); 3896 } else { 3897 assert(0 && "Unknown op"); 3898 } 3899 break; 3900 } 3901 break; 3902 } 3903 case ISD::TRAMPOLINE: { 3904 SDValue Ops[6]; 3905 for (unsigned i = 0; i != 6; ++i) 3906 Ops[i] = LegalizeOp(Node->getOperand(i)); 3907 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3908 // The only option for this node is to custom lower it. 3909 Result = TLI.LowerOperation(Result, DAG); 3910 assert(Result.Val && "Should always custom lower!"); 3911 3912 // Since trampoline produces two values, make sure to remember that we 3913 // legalized both of them. 3914 Tmp1 = LegalizeOp(Result.getValue(1)); 3915 Result = LegalizeOp(Result); 3916 AddLegalizedOperand(SDValue(Node, 0), Result); 3917 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 3918 return Op.ResNo ? Tmp1 : Result; 3919 } 3920 case ISD::FLT_ROUNDS_: { 3921 MVT VT = Node->getValueType(0); 3922 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3923 default: assert(0 && "This action not supported for this op yet!"); 3924 case TargetLowering::Custom: 3925 Result = TLI.LowerOperation(Op, DAG); 3926 if (Result.Val) break; 3927 // Fall Thru 3928 case TargetLowering::Legal: 3929 // If this operation is not supported, lower it to constant 1 3930 Result = DAG.getConstant(1, VT); 3931 break; 3932 } 3933 break; 3934 } 3935 case ISD::TRAP: { 3936 MVT VT = Node->getValueType(0); 3937 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3938 default: assert(0 && "This action not supported for this op yet!"); 3939 case TargetLowering::Legal: 3940 Tmp1 = LegalizeOp(Node->getOperand(0)); 3941 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3942 break; 3943 case TargetLowering::Custom: 3944 Result = TLI.LowerOperation(Op, DAG); 3945 if (Result.Val) break; 3946 // Fall Thru 3947 case TargetLowering::Expand: 3948 // If this operation is not supported, lower it to 'abort()' call 3949 Tmp1 = LegalizeOp(Node->getOperand(0)); 3950 TargetLowering::ArgListTy Args; 3951 std::pair<SDValue,SDValue> CallResult = 3952 TLI.LowerCallTo(Tmp1, Type::VoidTy, 3953 false, false, false, CallingConv::C, false, 3954 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 3955 Args, DAG); 3956 Result = CallResult.second; 3957 break; 3958 } 3959 break; 3960 } 3961 } 3962 3963 assert(Result.getValueType() == Op.getValueType() && 3964 "Bad legalization!"); 3965 3966 // Make sure that the generated code is itself legal. 3967 if (Result != Op) 3968 Result = LegalizeOp(Result); 3969 3970 // Note that LegalizeOp may be reentered even from single-use nodes, which 3971 // means that we always must cache transformed nodes. 3972 AddLegalizedOperand(Op, Result); 3973 return Result; 3974} 3975 3976/// PromoteOp - Given an operation that produces a value in an invalid type, 3977/// promote it to compute the value into a larger type. The produced value will 3978/// have the correct bits for the low portion of the register, but no guarantee 3979/// is made about the top bits: it may be zero, sign-extended, or garbage. 3980SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { 3981 MVT VT = Op.getValueType(); 3982 MVT NVT = TLI.getTypeToTransformTo(VT); 3983 assert(getTypeAction(VT) == Promote && 3984 "Caller should expand or legalize operands that are not promotable!"); 3985 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() && 3986 "Cannot promote to smaller type!"); 3987 3988 SDValue Tmp1, Tmp2, Tmp3; 3989 SDValue Result; 3990 SDNode *Node = Op.Val; 3991 3992 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op); 3993 if (I != PromotedNodes.end()) return I->second; 3994 3995 switch (Node->getOpcode()) { 3996 case ISD::CopyFromReg: 3997 assert(0 && "CopyFromReg must be legal!"); 3998 default: 3999#ifndef NDEBUG 4000 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4001#endif 4002 assert(0 && "Do not know how to promote this operator!"); 4003 abort(); 4004 case ISD::UNDEF: 4005 Result = DAG.getNode(ISD::UNDEF, NVT); 4006 break; 4007 case ISD::Constant: 4008 if (VT != MVT::i1) 4009 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4010 else 4011 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4012 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4013 break; 4014 case ISD::ConstantFP: 4015 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4016 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4017 break; 4018 4019 case ISD::SETCC: 4020 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0))) 4021 && "SetCC type is not legal??"); 4022 Result = DAG.getNode(ISD::SETCC, 4023 TLI.getSetCCResultType(Node->getOperand(0)), 4024 Node->getOperand(0), Node->getOperand(1), 4025 Node->getOperand(2)); 4026 break; 4027 4028 case ISD::TRUNCATE: 4029 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4030 case Legal: 4031 Result = LegalizeOp(Node->getOperand(0)); 4032 assert(Result.getValueType().bitsGE(NVT) && 4033 "This truncation doesn't make sense!"); 4034 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT 4035 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4036 break; 4037 case Promote: 4038 // The truncation is not required, because we don't guarantee anything 4039 // about high bits anyway. 4040 Result = PromoteOp(Node->getOperand(0)); 4041 break; 4042 case Expand: 4043 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4044 // Truncate the low part of the expanded value to the result type 4045 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4046 } 4047 break; 4048 case ISD::SIGN_EXTEND: 4049 case ISD::ZERO_EXTEND: 4050 case ISD::ANY_EXTEND: 4051 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4052 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4053 case Legal: 4054 // Input is legal? Just do extend all the way to the larger type. 4055 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4056 break; 4057 case Promote: 4058 // Promote the reg if it's smaller. 4059 Result = PromoteOp(Node->getOperand(0)); 4060 // The high bits are not guaranteed to be anything. Insert an extend. 4061 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4062 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4063 DAG.getValueType(Node->getOperand(0).getValueType())); 4064 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4065 Result = DAG.getZeroExtendInReg(Result, 4066 Node->getOperand(0).getValueType()); 4067 break; 4068 } 4069 break; 4070 case ISD::BIT_CONVERT: 4071 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4072 Node->getValueType(0)); 4073 Result = PromoteOp(Result); 4074 break; 4075 4076 case ISD::FP_EXTEND: 4077 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4078 case ISD::FP_ROUND: 4079 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4080 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4081 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4082 case Legal: 4083 if (Node->getConstantOperandVal(1) == 0) { 4084 // Input is legal? Do an FP_ROUND_INREG. 4085 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4086 DAG.getValueType(VT)); 4087 } else { 4088 // Just remove the truncate, it isn't affecting the value. 4089 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4090 Node->getOperand(1)); 4091 } 4092 break; 4093 } 4094 break; 4095 case ISD::SINT_TO_FP: 4096 case ISD::UINT_TO_FP: 4097 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4098 case Legal: 4099 // No extra round required here. 4100 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4101 break; 4102 4103 case Promote: 4104 Result = PromoteOp(Node->getOperand(0)); 4105 if (Node->getOpcode() == ISD::SINT_TO_FP) 4106 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4107 Result, 4108 DAG.getValueType(Node->getOperand(0).getValueType())); 4109 else 4110 Result = DAG.getZeroExtendInReg(Result, 4111 Node->getOperand(0).getValueType()); 4112 // No extra round required here. 4113 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4114 break; 4115 case Expand: 4116 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4117 Node->getOperand(0)); 4118 // Round if we cannot tolerate excess precision. 4119 if (NoExcessFPPrecision) 4120 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4121 DAG.getValueType(VT)); 4122 break; 4123 } 4124 break; 4125 4126 case ISD::SIGN_EXTEND_INREG: 4127 Result = PromoteOp(Node->getOperand(0)); 4128 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4129 Node->getOperand(1)); 4130 break; 4131 case ISD::FP_TO_SINT: 4132 case ISD::FP_TO_UINT: 4133 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4134 case Legal: 4135 case Expand: 4136 Tmp1 = Node->getOperand(0); 4137 break; 4138 case Promote: 4139 // The input result is prerounded, so we don't have to do anything 4140 // special. 4141 Tmp1 = PromoteOp(Node->getOperand(0)); 4142 break; 4143 } 4144 // If we're promoting a UINT to a larger size, check to see if the new node 4145 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4146 // we can use that instead. This allows us to generate better code for 4147 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4148 // legal, such as PowerPC. 4149 if (Node->getOpcode() == ISD::FP_TO_UINT && 4150 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 4151 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 4152 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4153 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4154 } else { 4155 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4156 } 4157 break; 4158 4159 case ISD::FABS: 4160 case ISD::FNEG: 4161 Tmp1 = PromoteOp(Node->getOperand(0)); 4162 assert(Tmp1.getValueType() == NVT); 4163 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4164 // NOTE: we do not have to do any extra rounding here for 4165 // NoExcessFPPrecision, because we know the input will have the appropriate 4166 // precision, and these operations don't modify precision at all. 4167 break; 4168 4169 case ISD::FSQRT: 4170 case ISD::FSIN: 4171 case ISD::FCOS: 4172 case ISD::FTRUNC: 4173 case ISD::FFLOOR: 4174 case ISD::FCEIL: 4175 case ISD::FRINT: 4176 case ISD::FNEARBYINT: 4177 Tmp1 = PromoteOp(Node->getOperand(0)); 4178 assert(Tmp1.getValueType() == NVT); 4179 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4180 if (NoExcessFPPrecision) 4181 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4182 DAG.getValueType(VT)); 4183 break; 4184 4185 case ISD::FPOWI: { 4186 // Promote f32 powi to f64 powi. Note that this could insert a libcall 4187 // directly as well, which may be better. 4188 Tmp1 = PromoteOp(Node->getOperand(0)); 4189 assert(Tmp1.getValueType() == NVT); 4190 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 4191 if (NoExcessFPPrecision) 4192 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4193 DAG.getValueType(VT)); 4194 break; 4195 } 4196 4197 case ISD::ATOMIC_CMP_SWAP: { 4198 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4199 Tmp2 = PromoteOp(Node->getOperand(2)); 4200 Tmp3 = PromoteOp(Node->getOperand(3)); 4201 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 4202 AtomNode->getBasePtr(), Tmp2, Tmp3, 4203 AtomNode->getSrcValue(), 4204 AtomNode->getAlignment()); 4205 // Remember that we legalized the chain. 4206 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4207 break; 4208 } 4209 case ISD::ATOMIC_LOAD_ADD: 4210 case ISD::ATOMIC_LOAD_SUB: 4211 case ISD::ATOMIC_LOAD_AND: 4212 case ISD::ATOMIC_LOAD_OR: 4213 case ISD::ATOMIC_LOAD_XOR: 4214 case ISD::ATOMIC_LOAD_NAND: 4215 case ISD::ATOMIC_LOAD_MIN: 4216 case ISD::ATOMIC_LOAD_MAX: 4217 case ISD::ATOMIC_LOAD_UMIN: 4218 case ISD::ATOMIC_LOAD_UMAX: 4219 case ISD::ATOMIC_SWAP: { 4220 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4221 Tmp2 = PromoteOp(Node->getOperand(2)); 4222 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 4223 AtomNode->getBasePtr(), Tmp2, 4224 AtomNode->getSrcValue(), 4225 AtomNode->getAlignment()); 4226 // Remember that we legalized the chain. 4227 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4228 break; 4229 } 4230 4231 case ISD::AND: 4232 case ISD::OR: 4233 case ISD::XOR: 4234 case ISD::ADD: 4235 case ISD::SUB: 4236 case ISD::MUL: 4237 // The input may have strange things in the top bits of the registers, but 4238 // these operations don't care. They may have weird bits going out, but 4239 // that too is okay if they are integer operations. 4240 Tmp1 = PromoteOp(Node->getOperand(0)); 4241 Tmp2 = PromoteOp(Node->getOperand(1)); 4242 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4243 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4244 break; 4245 case ISD::FADD: 4246 case ISD::FSUB: 4247 case ISD::FMUL: 4248 Tmp1 = PromoteOp(Node->getOperand(0)); 4249 Tmp2 = PromoteOp(Node->getOperand(1)); 4250 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4251 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4252 4253 // Floating point operations will give excess precision that we may not be 4254 // able to tolerate. If we DO allow excess precision, just leave it, 4255 // otherwise excise it. 4256 // FIXME: Why would we need to round FP ops more than integer ones? 4257 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4258 if (NoExcessFPPrecision) 4259 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4260 DAG.getValueType(VT)); 4261 break; 4262 4263 case ISD::SDIV: 4264 case ISD::SREM: 4265 // These operators require that their input be sign extended. 4266 Tmp1 = PromoteOp(Node->getOperand(0)); 4267 Tmp2 = PromoteOp(Node->getOperand(1)); 4268 if (NVT.isInteger()) { 4269 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4270 DAG.getValueType(VT)); 4271 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4272 DAG.getValueType(VT)); 4273 } 4274 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4275 4276 // Perform FP_ROUND: this is probably overly pessimistic. 4277 if (NVT.isFloatingPoint() && NoExcessFPPrecision) 4278 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4279 DAG.getValueType(VT)); 4280 break; 4281 case ISD::FDIV: 4282 case ISD::FREM: 4283 case ISD::FCOPYSIGN: 4284 // These operators require that their input be fp extended. 4285 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4286 case Expand: assert(0 && "not implemented"); 4287 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4288 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4289 } 4290 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4291 case Expand: assert(0 && "not implemented"); 4292 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4293 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4294 } 4295 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4296 4297 // Perform FP_ROUND: this is probably overly pessimistic. 4298 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4299 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4300 DAG.getValueType(VT)); 4301 break; 4302 4303 case ISD::UDIV: 4304 case ISD::UREM: 4305 // These operators require that their input be zero extended. 4306 Tmp1 = PromoteOp(Node->getOperand(0)); 4307 Tmp2 = PromoteOp(Node->getOperand(1)); 4308 assert(NVT.isInteger() && "Operators don't apply to FP!"); 4309 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4310 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4311 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4312 break; 4313 4314 case ISD::SHL: 4315 Tmp1 = PromoteOp(Node->getOperand(0)); 4316 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4317 break; 4318 case ISD::SRA: 4319 // The input value must be properly sign extended. 4320 Tmp1 = PromoteOp(Node->getOperand(0)); 4321 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4322 DAG.getValueType(VT)); 4323 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4324 break; 4325 case ISD::SRL: 4326 // The input value must be properly zero extended. 4327 Tmp1 = PromoteOp(Node->getOperand(0)); 4328 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4329 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4330 break; 4331 4332 case ISD::VAARG: 4333 Tmp1 = Node->getOperand(0); // Get the chain. 4334 Tmp2 = Node->getOperand(1); // Get the pointer. 4335 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4336 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4337 Result = TLI.LowerOperation(Tmp3, DAG); 4338 } else { 4339 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4340 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4341 // Increment the pointer, VAList, to the next vaarg 4342 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4343 DAG.getConstant(VT.getSizeInBits()/8, 4344 TLI.getPointerTy())); 4345 // Store the incremented VAList to the legalized pointer 4346 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4347 // Load the actual argument out of the pointer VAList 4348 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4349 } 4350 // Remember that we legalized the chain. 4351 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4352 break; 4353 4354 case ISD::LOAD: { 4355 LoadSDNode *LD = cast<LoadSDNode>(Node); 4356 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4357 ? ISD::EXTLOAD : LD->getExtensionType(); 4358 Result = DAG.getExtLoad(ExtType, NVT, 4359 LD->getChain(), LD->getBasePtr(), 4360 LD->getSrcValue(), LD->getSrcValueOffset(), 4361 LD->getMemoryVT(), 4362 LD->isVolatile(), 4363 LD->getAlignment()); 4364 // Remember that we legalized the chain. 4365 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4366 break; 4367 } 4368 case ISD::SELECT: { 4369 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4370 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4371 4372 MVT VT2 = Tmp2.getValueType(); 4373 assert(VT2 == Tmp3.getValueType() 4374 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); 4375 // Ensure that the resulting node is at least the same size as the operands' 4376 // value types, because we cannot assume that TLI.getSetCCValueType() is 4377 // constant. 4378 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3); 4379 break; 4380 } 4381 case ISD::SELECT_CC: 4382 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4383 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4384 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4385 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4386 break; 4387 case ISD::BSWAP: 4388 Tmp1 = Node->getOperand(0); 4389 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4390 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4391 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4392 DAG.getConstant(NVT.getSizeInBits() - 4393 VT.getSizeInBits(), 4394 TLI.getShiftAmountTy())); 4395 break; 4396 case ISD::CTPOP: 4397 case ISD::CTTZ: 4398 case ISD::CTLZ: 4399 // Zero extend the argument 4400 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4401 // Perform the larger operation, then subtract if needed. 4402 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4403 switch(Node->getOpcode()) { 4404 case ISD::CTPOP: 4405 Result = Tmp1; 4406 break; 4407 case ISD::CTTZ: 4408 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4409 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 4410 DAG.getConstant(NVT.getSizeInBits(), NVT), 4411 ISD::SETEQ); 4412 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4413 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); 4414 break; 4415 case ISD::CTLZ: 4416 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4417 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4418 DAG.getConstant(NVT.getSizeInBits() - 4419 VT.getSizeInBits(), NVT)); 4420 break; 4421 } 4422 break; 4423 case ISD::EXTRACT_SUBVECTOR: 4424 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4425 break; 4426 case ISD::EXTRACT_VECTOR_ELT: 4427 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4428 break; 4429 } 4430 4431 assert(Result.Val && "Didn't set a result!"); 4432 4433 // Make sure the result is itself legal. 4434 Result = LegalizeOp(Result); 4435 4436 // Remember that we promoted this! 4437 AddPromotedOperand(Op, Result); 4438 return Result; 4439} 4440 4441/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4442/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4443/// based on the vector type. The return type of this matches the element type 4444/// of the vector, which may not be legal for the target. 4445SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) { 4446 // We know that operand #0 is the Vec vector. If the index is a constant 4447 // or if the invec is a supported hardware type, we can use it. Otherwise, 4448 // lower to a store then an indexed load. 4449 SDValue Vec = Op.getOperand(0); 4450 SDValue Idx = Op.getOperand(1); 4451 4452 MVT TVT = Vec.getValueType(); 4453 unsigned NumElems = TVT.getVectorNumElements(); 4454 4455 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4456 default: assert(0 && "This action is not supported yet!"); 4457 case TargetLowering::Custom: { 4458 Vec = LegalizeOp(Vec); 4459 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4460 SDValue Tmp3 = TLI.LowerOperation(Op, DAG); 4461 if (Tmp3.Val) 4462 return Tmp3; 4463 break; 4464 } 4465 case TargetLowering::Legal: 4466 if (isTypeLegal(TVT)) { 4467 Vec = LegalizeOp(Vec); 4468 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4469 return Op; 4470 } 4471 break; 4472 case TargetLowering::Expand: 4473 break; 4474 } 4475 4476 if (NumElems == 1) { 4477 // This must be an access of the only element. Return it. 4478 Op = ScalarizeVectorOp(Vec); 4479 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4480 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 4481 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4482 SDValue Lo, Hi; 4483 SplitVectorOp(Vec, Lo, Hi); 4484 if (CIdx->getValue() < NumLoElts) { 4485 Vec = Lo; 4486 } else { 4487 Vec = Hi; 4488 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts, 4489 Idx.getValueType()); 4490 } 4491 4492 // It's now an extract from the appropriate high or low part. Recurse. 4493 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4494 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4495 } else { 4496 // Store the value to a temporary stack slot, then LOAD the scalar 4497 // element back out. 4498 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4499 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4500 4501 // Add the offset to the index. 4502 unsigned EltSize = Op.getValueType().getSizeInBits()/8; 4503 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4504 DAG.getConstant(EltSize, Idx.getValueType())); 4505 4506 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 4507 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4508 else 4509 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4510 4511 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4512 4513 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4514 } 4515 return Op; 4516} 4517 4518/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4519/// we assume the operation can be split if it is not already legal. 4520SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) { 4521 // We know that operand #0 is the Vec vector. For now we assume the index 4522 // is a constant and that the extracted result is a supported hardware type. 4523 SDValue Vec = Op.getOperand(0); 4524 SDValue Idx = LegalizeOp(Op.getOperand(1)); 4525 4526 unsigned NumElems = Vec.getValueType().getVectorNumElements(); 4527 4528 if (NumElems == Op.getValueType().getVectorNumElements()) { 4529 // This must be an access of the desired vector length. Return it. 4530 return Vec; 4531 } 4532 4533 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4534 SDValue Lo, Hi; 4535 SplitVectorOp(Vec, Lo, Hi); 4536 if (CIdx->getValue() < NumElems/2) { 4537 Vec = Lo; 4538 } else { 4539 Vec = Hi; 4540 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4541 } 4542 4543 // It's now an extract from the appropriate high or low part. Recurse. 4544 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4545 return ExpandEXTRACT_SUBVECTOR(Op); 4546} 4547 4548/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4549/// with condition CC on the current target. This usually involves legalizing 4550/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4551/// there may be no choice but to create a new SetCC node to represent the 4552/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4553/// LHS, and the SDValue returned in RHS has a nil SDNode value. 4554void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS, 4555 SDValue &RHS, 4556 SDValue &CC) { 4557 SDValue Tmp1, Tmp2, Tmp3, Result; 4558 4559 switch (getTypeAction(LHS.getValueType())) { 4560 case Legal: 4561 Tmp1 = LegalizeOp(LHS); // LHS 4562 Tmp2 = LegalizeOp(RHS); // RHS 4563 break; 4564 case Promote: 4565 Tmp1 = PromoteOp(LHS); // LHS 4566 Tmp2 = PromoteOp(RHS); // RHS 4567 4568 // If this is an FP compare, the operands have already been extended. 4569 if (LHS.getValueType().isInteger()) { 4570 MVT VT = LHS.getValueType(); 4571 MVT NVT = TLI.getTypeToTransformTo(VT); 4572 4573 // Otherwise, we have to insert explicit sign or zero extends. Note 4574 // that we could insert sign extends for ALL conditions, but zero extend 4575 // is cheaper on many machines (an AND instead of two shifts), so prefer 4576 // it. 4577 switch (cast<CondCodeSDNode>(CC)->get()) { 4578 default: assert(0 && "Unknown integer comparison!"); 4579 case ISD::SETEQ: 4580 case ISD::SETNE: 4581 case ISD::SETUGE: 4582 case ISD::SETUGT: 4583 case ISD::SETULE: 4584 case ISD::SETULT: 4585 // ALL of these operations will work if we either sign or zero extend 4586 // the operands (including the unsigned comparisons!). Zero extend is 4587 // usually a simpler/cheaper operation, so prefer it. 4588 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4589 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4590 break; 4591 case ISD::SETGE: 4592 case ISD::SETGT: 4593 case ISD::SETLT: 4594 case ISD::SETLE: 4595 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4596 DAG.getValueType(VT)); 4597 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4598 DAG.getValueType(VT)); 4599 break; 4600 } 4601 } 4602 break; 4603 case Expand: { 4604 MVT VT = LHS.getValueType(); 4605 if (VT == MVT::f32 || VT == MVT::f64) { 4606 // Expand into one or more soft-fp libcall(s). 4607 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; 4608 switch (cast<CondCodeSDNode>(CC)->get()) { 4609 case ISD::SETEQ: 4610 case ISD::SETOEQ: 4611 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4612 break; 4613 case ISD::SETNE: 4614 case ISD::SETUNE: 4615 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4616 break; 4617 case ISD::SETGE: 4618 case ISD::SETOGE: 4619 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4620 break; 4621 case ISD::SETLT: 4622 case ISD::SETOLT: 4623 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4624 break; 4625 case ISD::SETLE: 4626 case ISD::SETOLE: 4627 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4628 break; 4629 case ISD::SETGT: 4630 case ISD::SETOGT: 4631 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4632 break; 4633 case ISD::SETUO: 4634 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4635 break; 4636 case ISD::SETO: 4637 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4638 break; 4639 default: 4640 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4641 switch (cast<CondCodeSDNode>(CC)->get()) { 4642 case ISD::SETONE: 4643 // SETONE = SETOLT | SETOGT 4644 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4645 // Fallthrough 4646 case ISD::SETUGT: 4647 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4648 break; 4649 case ISD::SETUGE: 4650 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4651 break; 4652 case ISD::SETULT: 4653 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4654 break; 4655 case ISD::SETULE: 4656 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4657 break; 4658 case ISD::SETUEQ: 4659 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4660 break; 4661 default: assert(0 && "Unsupported FP setcc!"); 4662 } 4663 } 4664 4665 SDValue Dummy; 4666 SDValue Ops[2] = { LHS, RHS }; 4667 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).Val, 4668 false /*sign irrelevant*/, Dummy); 4669 Tmp2 = DAG.getConstant(0, MVT::i32); 4670 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4671 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4672 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 4673 CC); 4674 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).Val, 4675 false /*sign irrelevant*/, Dummy); 4676 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, 4677 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4678 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4679 Tmp2 = SDValue(); 4680 } 4681 LHS = LegalizeOp(Tmp1); 4682 RHS = Tmp2; 4683 return; 4684 } 4685 4686 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 4687 ExpandOp(LHS, LHSLo, LHSHi); 4688 ExpandOp(RHS, RHSLo, RHSHi); 4689 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4690 4691 if (VT==MVT::ppcf128) { 4692 // FIXME: This generated code sucks. We want to generate 4693 // FCMP crN, hi1, hi2 4694 // BNE crN, L: 4695 // FCMP crN, lo1, lo2 4696 // The following can be improved, but not that much. 4697 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ); 4698 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode); 4699 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4700 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE); 4701 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode); 4702 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4703 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4704 Tmp2 = SDValue(); 4705 break; 4706 } 4707 4708 switch (CCCode) { 4709 case ISD::SETEQ: 4710 case ISD::SETNE: 4711 if (RHSLo == RHSHi) 4712 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4713 if (RHSCST->isAllOnesValue()) { 4714 // Comparison to -1. 4715 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4716 Tmp2 = RHSLo; 4717 break; 4718 } 4719 4720 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4721 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4722 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4723 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4724 break; 4725 default: 4726 // If this is a comparison of the sign bit, just look at the top part. 4727 // X > -1, x < 0 4728 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4729 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4730 CST->isNullValue()) || // X < 0 4731 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4732 CST->isAllOnesValue())) { // X > -1 4733 Tmp1 = LHSHi; 4734 Tmp2 = RHSHi; 4735 break; 4736 } 4737 4738 // FIXME: This generated code sucks. 4739 ISD::CondCode LowCC; 4740 switch (CCCode) { 4741 default: assert(0 && "Unknown integer setcc!"); 4742 case ISD::SETLT: 4743 case ISD::SETULT: LowCC = ISD::SETULT; break; 4744 case ISD::SETGT: 4745 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4746 case ISD::SETLE: 4747 case ISD::SETULE: LowCC = ISD::SETULE; break; 4748 case ISD::SETGE: 4749 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4750 } 4751 4752 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4753 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4754 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4755 4756 // NOTE: on targets without efficient SELECT of bools, we can always use 4757 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4758 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4759 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, 4760 LowCC, false, DagCombineInfo); 4761 if (!Tmp1.Val) 4762 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 4763 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4764 CCCode, false, DagCombineInfo); 4765 if (!Tmp2.Val) 4766 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, 4767 RHSHi,CC); 4768 4769 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4770 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4771 if ((Tmp1C && Tmp1C->isNullValue()) || 4772 (Tmp2C && Tmp2C->isNullValue() && 4773 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4774 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4775 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 4776 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4777 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4778 // low part is known false, returns high part. 4779 // For LE / GE, if high part is known false, ignore the low part. 4780 // For LT / GT, if high part is known true, ignore the low part. 4781 Tmp1 = Tmp2; 4782 Tmp2 = SDValue(); 4783 } else { 4784 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4785 ISD::SETEQ, false, DagCombineInfo); 4786 if (!Result.Val) 4787 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4788 ISD::SETEQ); 4789 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4790 Result, Tmp1, Tmp2)); 4791 Tmp1 = Result; 4792 Tmp2 = SDValue(); 4793 } 4794 } 4795 } 4796 } 4797 LHS = Tmp1; 4798 RHS = Tmp2; 4799} 4800 4801/// EmitStackConvert - Emit a store/load combination to the stack. This stores 4802/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 4803/// a load from the stack slot to DestVT, extending it if needed. 4804/// The resultant code need not be legal. 4805SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 4806 MVT SlotVT, 4807 MVT DestVT) { 4808 // Create the stack frame object. 4809 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment( 4810 SrcOp.getValueType().getTypeForMVT()); 4811 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 4812 4813 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 4814 int SPFI = StackPtrFI->getIndex(); 4815 4816 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 4817 unsigned SlotSize = SlotVT.getSizeInBits(); 4818 unsigned DestSize = DestVT.getSizeInBits(); 4819 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment( 4820 DestVT.getTypeForMVT()); 4821 4822 // Emit a store to the stack slot. Use a truncstore if the input value is 4823 // later than DestVT. 4824 SDValue Store; 4825 4826 if (SrcSize > SlotSize) 4827 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 4828 PseudoSourceValue::getFixedStack(SPFI), 0, 4829 SlotVT, false, SrcAlign); 4830 else { 4831 assert(SrcSize == SlotSize && "Invalid store"); 4832 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 4833 PseudoSourceValue::getFixedStack(SPFI), 0, 4834 false, SrcAlign); 4835 } 4836 4837 // Result is a load from the stack slot. 4838 if (SlotSize == DestSize) 4839 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign); 4840 4841 assert(SlotSize < DestSize && "Unknown extension!"); 4842 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT, 4843 false, DestAlign); 4844} 4845 4846SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4847 // Create a vector sized/aligned stack slot, store the value to element #0, 4848 // then load the whole vector back out. 4849 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4850 4851 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 4852 int SPFI = StackPtrFI->getIndex(); 4853 4854 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4855 PseudoSourceValue::getFixedStack(SPFI), 0); 4856 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 4857 PseudoSourceValue::getFixedStack(SPFI), 0); 4858} 4859 4860 4861/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4862/// support the operation, but do support the resultant vector type. 4863SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4864 4865 // If the only non-undef value is the low element, turn this into a 4866 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4867 unsigned NumElems = Node->getNumOperands(); 4868 bool isOnlyLowElement = true; 4869 SDValue SplatValue = Node->getOperand(0); 4870 4871 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t> 4872 // and use a bitmask instead of a list of elements. 4873 std::map<SDValue, std::vector<unsigned> > Values; 4874 Values[SplatValue].push_back(0); 4875 bool isConstant = true; 4876 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4877 SplatValue.getOpcode() != ISD::UNDEF) 4878 isConstant = false; 4879 4880 for (unsigned i = 1; i < NumElems; ++i) { 4881 SDValue V = Node->getOperand(i); 4882 Values[V].push_back(i); 4883 if (V.getOpcode() != ISD::UNDEF) 4884 isOnlyLowElement = false; 4885 if (SplatValue != V) 4886 SplatValue = SDValue(0,0); 4887 4888 // If this isn't a constant element or an undef, we can't use a constant 4889 // pool load. 4890 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4891 V.getOpcode() != ISD::UNDEF) 4892 isConstant = false; 4893 } 4894 4895 if (isOnlyLowElement) { 4896 // If the low element is an undef too, then this whole things is an undef. 4897 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4898 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4899 // Otherwise, turn this into a scalar_to_vector node. 4900 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4901 Node->getOperand(0)); 4902 } 4903 4904 // If all elements are constants, create a load from the constant pool. 4905 if (isConstant) { 4906 MVT VT = Node->getValueType(0); 4907 std::vector<Constant*> CV; 4908 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4909 if (ConstantFPSDNode *V = 4910 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4911 CV.push_back(ConstantFP::get(V->getValueAPF())); 4912 } else if (ConstantSDNode *V = 4913 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4914 CV.push_back(ConstantInt::get(V->getAPIntValue())); 4915 } else { 4916 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4917 const Type *OpNTy = 4918 Node->getOperand(0).getValueType().getTypeForMVT(); 4919 CV.push_back(UndefValue::get(OpNTy)); 4920 } 4921 } 4922 Constant *CP = ConstantVector::get(CV); 4923 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4924 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4925 PseudoSourceValue::getConstantPool(), 0); 4926 } 4927 4928 if (SplatValue.Val) { // Splat of one value? 4929 // Build the shuffle constant vector: <0, 0, 0, 0> 4930 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 4931 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); 4932 std::vector<SDValue> ZeroVec(NumElems, Zero); 4933 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4934 &ZeroVec[0], ZeroVec.size()); 4935 4936 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4937 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4938 // Get the splatted value into the low element of a vector register. 4939 SDValue LowValVec = 4940 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4941 4942 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4943 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4944 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4945 SplatMask); 4946 } 4947 } 4948 4949 // If there are only two unique elements, we may be able to turn this into a 4950 // vector shuffle. 4951 if (Values.size() == 2) { 4952 // Get the two values in deterministic order. 4953 SDValue Val1 = Node->getOperand(1); 4954 SDValue Val2; 4955 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin(); 4956 if (MI->first != Val1) 4957 Val2 = MI->first; 4958 else 4959 Val2 = (++MI)->first; 4960 4961 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 4962 // vector shuffle has the undef vector on the RHS. 4963 if (Val1.getOpcode() == ISD::UNDEF) 4964 std::swap(Val1, Val2); 4965 4966 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 4967 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 4968 MVT MaskEltVT = MaskVT.getVectorElementType(); 4969 std::vector<SDValue> MaskVec(NumElems); 4970 4971 // Set elements of the shuffle mask for Val1. 4972 std::vector<unsigned> &Val1Elts = Values[Val1]; 4973 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 4974 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 4975 4976 // Set elements of the shuffle mask for Val2. 4977 std::vector<unsigned> &Val2Elts = Values[Val2]; 4978 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 4979 if (Val2.getOpcode() != ISD::UNDEF) 4980 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 4981 else 4982 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); 4983 4984 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4985 &MaskVec[0], MaskVec.size()); 4986 4987 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 4988 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 4989 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 4990 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); 4991 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); 4992 SDValue Ops[] = { Val1, Val2, ShuffleMask }; 4993 4994 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 4995 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); 4996 } 4997 } 4998 4999 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5000 // aligned object on the stack, store each element into it, then load 5001 // the result as a vector. 5002 MVT VT = Node->getValueType(0); 5003 // Create the stack frame object. 5004 SDValue FIPtr = DAG.CreateStackTemporary(VT); 5005 5006 // Emit a store of each element to the stack slot. 5007 SmallVector<SDValue, 8> Stores; 5008 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8; 5009 // Store (in the right endianness) the elements to memory. 5010 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5011 // Ignore undef elements. 5012 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5013 5014 unsigned Offset = TypeByteSize*i; 5015 5016 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5017 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 5018 5019 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 5020 NULL, 0)); 5021 } 5022 5023 SDValue StoreChain; 5024 if (!Stores.empty()) // Not all undef elements? 5025 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5026 &Stores[0], Stores.size()); 5027 else 5028 StoreChain = DAG.getEntryNode(); 5029 5030 // Result is a load from the stack slot. 5031 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 5032} 5033 5034void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5035 SDValue Op, SDValue Amt, 5036 SDValue &Lo, SDValue &Hi) { 5037 // Expand the subcomponents. 5038 SDValue LHSL, LHSH; 5039 ExpandOp(Op, LHSL, LHSH); 5040 5041 SDValue Ops[] = { LHSL, LHSH, Amt }; 5042 MVT VT = LHSL.getValueType(); 5043 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5044 Hi = Lo.getValue(1); 5045} 5046 5047 5048/// ExpandShift - Try to find a clever way to expand this shift operation out to 5049/// smaller elements. If we can't find a way that is more efficient than a 5050/// libcall on this target, return false. Otherwise, return true with the 5051/// low-parts expanded into Lo and Hi. 5052bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, 5053 SDValue &Lo, SDValue &Hi) { 5054 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5055 "This is not a shift!"); 5056 5057 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5058 SDValue ShAmt = LegalizeOp(Amt); 5059 MVT ShTy = ShAmt.getValueType(); 5060 unsigned ShBits = ShTy.getSizeInBits(); 5061 unsigned VTBits = Op.getValueType().getSizeInBits(); 5062 unsigned NVTBits = NVT.getSizeInBits(); 5063 5064 // Handle the case when Amt is an immediate. 5065 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 5066 unsigned Cst = CN->getValue(); 5067 // Expand the incoming operand to be shifted, so that we have its parts 5068 SDValue InL, InH; 5069 ExpandOp(Op, InL, InH); 5070 switch(Opc) { 5071 case ISD::SHL: 5072 if (Cst > VTBits) { 5073 Lo = DAG.getConstant(0, NVT); 5074 Hi = DAG.getConstant(0, NVT); 5075 } else if (Cst > NVTBits) { 5076 Lo = DAG.getConstant(0, NVT); 5077 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5078 } else if (Cst == NVTBits) { 5079 Lo = DAG.getConstant(0, NVT); 5080 Hi = InL; 5081 } else { 5082 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5083 Hi = DAG.getNode(ISD::OR, NVT, 5084 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5085 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5086 } 5087 return true; 5088 case ISD::SRL: 5089 if (Cst > VTBits) { 5090 Lo = DAG.getConstant(0, NVT); 5091 Hi = DAG.getConstant(0, NVT); 5092 } else if (Cst > NVTBits) { 5093 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5094 Hi = DAG.getConstant(0, NVT); 5095 } else if (Cst == NVTBits) { 5096 Lo = InH; 5097 Hi = DAG.getConstant(0, NVT); 5098 } else { 5099 Lo = DAG.getNode(ISD::OR, NVT, 5100 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5101 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5102 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5103 } 5104 return true; 5105 case ISD::SRA: 5106 if (Cst > VTBits) { 5107 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5108 DAG.getConstant(NVTBits-1, ShTy)); 5109 } else if (Cst > NVTBits) { 5110 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5111 DAG.getConstant(Cst-NVTBits, ShTy)); 5112 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5113 DAG.getConstant(NVTBits-1, ShTy)); 5114 } else if (Cst == NVTBits) { 5115 Lo = InH; 5116 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5117 DAG.getConstant(NVTBits-1, ShTy)); 5118 } else { 5119 Lo = DAG.getNode(ISD::OR, NVT, 5120 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5121 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5122 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5123 } 5124 return true; 5125 } 5126 } 5127 5128 // Okay, the shift amount isn't constant. However, if we can tell that it is 5129 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5130 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5131 APInt KnownZero, KnownOne; 5132 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5133 5134 // If we know that if any of the high bits of the shift amount are one, then 5135 // we can do this as a couple of simple shifts. 5136 if (KnownOne.intersects(Mask)) { 5137 // Mask out the high bit, which we know is set. 5138 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5139 DAG.getConstant(~Mask, Amt.getValueType())); 5140 5141 // Expand the incoming operand to be shifted, so that we have its parts 5142 SDValue InL, InH; 5143 ExpandOp(Op, InL, InH); 5144 switch(Opc) { 5145 case ISD::SHL: 5146 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5147 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5148 return true; 5149 case ISD::SRL: 5150 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5151 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5152 return true; 5153 case ISD::SRA: 5154 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5155 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5156 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5157 return true; 5158 } 5159 } 5160 5161 // If we know that the high bits of the shift amount are all zero, then we can 5162 // do this as a couple of simple shifts. 5163 if ((KnownZero & Mask) == Mask) { 5164 // Compute 32-amt. 5165 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5166 DAG.getConstant(NVTBits, Amt.getValueType()), 5167 Amt); 5168 5169 // Expand the incoming operand to be shifted, so that we have its parts 5170 SDValue InL, InH; 5171 ExpandOp(Op, InL, InH); 5172 switch(Opc) { 5173 case ISD::SHL: 5174 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5175 Hi = DAG.getNode(ISD::OR, NVT, 5176 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5177 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5178 return true; 5179 case ISD::SRL: 5180 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5181 Lo = DAG.getNode(ISD::OR, NVT, 5182 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5183 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5184 return true; 5185 case ISD::SRA: 5186 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5187 Lo = DAG.getNode(ISD::OR, NVT, 5188 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5189 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5190 return true; 5191 } 5192 } 5193 5194 return false; 5195} 5196 5197 5198// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5199// does not fit into a register, return the lo part and set the hi part to the 5200// by-reg argument. If it does fit into a single register, return the result 5201// and leave the Hi part unset. 5202SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5203 bool isSigned, SDValue &Hi) { 5204 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5205 // The input chain to this libcall is the entry node of the function. 5206 // Legalizing the call will automatically add the previous call to the 5207 // dependence. 5208 SDValue InChain = DAG.getEntryNode(); 5209 5210 TargetLowering::ArgListTy Args; 5211 TargetLowering::ArgListEntry Entry; 5212 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5213 MVT ArgVT = Node->getOperand(i).getValueType(); 5214 const Type *ArgTy = ArgVT.getTypeForMVT(); 5215 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5216 Entry.isSExt = isSigned; 5217 Entry.isZExt = !isSigned; 5218 Args.push_back(Entry); 5219 } 5220 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5221 TLI.getPointerTy()); 5222 5223 // Splice the libcall in wherever FindInputOutputChains tells us to. 5224 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 5225 std::pair<SDValue,SDValue> CallInfo = 5226 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C, 5227 false, Callee, Args, DAG); 5228 5229 // Legalize the call sequence, starting with the chain. This will advance 5230 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5231 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5232 LegalizeOp(CallInfo.second); 5233 SDValue Result; 5234 switch (getTypeAction(CallInfo.first.getValueType())) { 5235 default: assert(0 && "Unknown thing"); 5236 case Legal: 5237 Result = CallInfo.first; 5238 break; 5239 case Expand: 5240 ExpandOp(CallInfo.first, Result, Hi); 5241 break; 5242 } 5243 return Result; 5244} 5245 5246/// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation. 5247/// 5248SDValue SelectionDAGLegalize:: 5249LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) { 5250 bool isCustom = false; 5251 SDValue Tmp1; 5252 switch (getTypeAction(Op.getValueType())) { 5253 case Legal: 5254 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5255 Op.getValueType())) { 5256 default: assert(0 && "Unknown operation action!"); 5257 case TargetLowering::Custom: 5258 isCustom = true; 5259 // FALLTHROUGH 5260 case TargetLowering::Legal: 5261 Tmp1 = LegalizeOp(Op); 5262 if (Result.Val) 5263 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5264 else 5265 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5266 DestTy, Tmp1); 5267 if (isCustom) { 5268 Tmp1 = TLI.LowerOperation(Result, DAG); 5269 if (Tmp1.Val) Result = Tmp1; 5270 } 5271 break; 5272 case TargetLowering::Expand: 5273 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy); 5274 break; 5275 case TargetLowering::Promote: 5276 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned); 5277 break; 5278 } 5279 break; 5280 case Expand: 5281 Result = ExpandIntToFP(isSigned, DestTy, Op); 5282 break; 5283 case Promote: 5284 Tmp1 = PromoteOp(Op); 5285 if (isSigned) { 5286 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 5287 Tmp1, DAG.getValueType(Op.getValueType())); 5288 } else { 5289 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 5290 Op.getValueType()); 5291 } 5292 if (Result.Val) 5293 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5294 else 5295 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5296 DestTy, Tmp1); 5297 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 5298 break; 5299 } 5300 return Result; 5301} 5302 5303/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5304/// 5305SDValue SelectionDAGLegalize:: 5306ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) { 5307 MVT SourceVT = Source.getValueType(); 5308 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5309 5310 // Expand unsupported int-to-fp vector casts by unrolling them. 5311 if (DestTy.isVector()) { 5312 if (!ExpandSource) 5313 return LegalizeOp(UnrollVectorOp(Source)); 5314 MVT DestEltTy = DestTy.getVectorElementType(); 5315 if (DestTy.getVectorNumElements() == 1) { 5316 SDValue Scalar = ScalarizeVectorOp(Source); 5317 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned, 5318 DestEltTy, Scalar); 5319 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result); 5320 } 5321 SDValue Lo, Hi; 5322 SplitVectorOp(Source, Lo, Hi); 5323 MVT SplitDestTy = MVT::getVectorVT(DestEltTy, 5324 DestTy.getVectorNumElements() / 2); 5325 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo); 5326 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi); 5327 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult, HiResult)); 5328 } 5329 5330 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5331 if (!isSigned && SourceVT != MVT::i32) { 5332 // The integer value loaded will be incorrectly if the 'sign bit' of the 5333 // incoming integer is set. To handle this, we dynamically test to see if 5334 // it is set, and, if so, add a fudge factor. 5335 SDValue Hi; 5336 if (ExpandSource) { 5337 SDValue Lo; 5338 ExpandOp(Source, Lo, Hi); 5339 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); 5340 } else { 5341 // The comparison for the sign bit will use the entire operand. 5342 Hi = Source; 5343 } 5344 5345 // If this is unsigned, and not supported, first perform the conversion to 5346 // signed, then adjust the result if the sign bit is set. 5347 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source); 5348 5349 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 5350 DAG.getConstant(0, Hi.getValueType()), 5351 ISD::SETLT); 5352 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5353 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5354 SignSet, Four, Zero); 5355 uint64_t FF = 0x5f800000ULL; 5356 if (TLI.isLittleEndian()) FF <<= 32; 5357 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5358 5359 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5360 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5361 SDValue FudgeInReg; 5362 if (DestTy == MVT::f32) 5363 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5364 PseudoSourceValue::getConstantPool(), 0); 5365 else if (DestTy.bitsGT(MVT::f32)) 5366 // FIXME: Avoid the extend by construction the right constantpool? 5367 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5368 CPIdx, 5369 PseudoSourceValue::getConstantPool(), 0, 5370 MVT::f32); 5371 else 5372 assert(0 && "Unexpected conversion"); 5373 5374 MVT SCVT = SignedConv.getValueType(); 5375 if (SCVT != DestTy) { 5376 // Destination type needs to be expanded as well. The FADD now we are 5377 // constructing will be expanded into a libcall. 5378 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { 5379 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); 5380 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, 5381 SignedConv, SignedConv.getValue(1)); 5382 } 5383 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5384 } 5385 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5386 } 5387 5388 // Check to see if the target has a custom way to lower this. If so, use it. 5389 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 5390 default: assert(0 && "This action not implemented for this operation!"); 5391 case TargetLowering::Legal: 5392 case TargetLowering::Expand: 5393 break; // This case is handled below. 5394 case TargetLowering::Custom: { 5395 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5396 Source), DAG); 5397 if (NV.Val) 5398 return LegalizeOp(NV); 5399 break; // The target decided this was legal after all 5400 } 5401 } 5402 5403 // Expand the source, then glue it back together for the call. We must expand 5404 // the source in case it is shared (this pass of legalize must traverse it). 5405 if (ExpandSource) { 5406 SDValue SrcLo, SrcHi; 5407 ExpandOp(Source, SrcLo, SrcHi); 5408 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); 5409 } 5410 5411 RTLIB::Libcall LC = isSigned ? 5412 RTLIB::getSINTTOFP(SourceVT, DestTy) : 5413 RTLIB::getUINTTOFP(SourceVT, DestTy); 5414 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type"); 5415 5416 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5417 SDValue HiPart; 5418 SDValue Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart); 5419 if (Result.getValueType() != DestTy && HiPart.Val) 5420 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); 5421 return Result; 5422} 5423 5424/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5425/// INT_TO_FP operation of the specified operand when the target requests that 5426/// we expand it. At this point, we know that the result and operand types are 5427/// legal for the target. 5428SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5429 SDValue Op0, 5430 MVT DestVT) { 5431 if (Op0.getValueType() == MVT::i32) { 5432 // simple 32-bit [signed|unsigned] integer to float/double expansion 5433 5434 // Get the stack frame index of a 8 byte buffer. 5435 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 5436 5437 // word offset constant for Hi/Lo address computation 5438 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5439 // set up Hi and Lo (into buffer) address based on endian 5440 SDValue Hi = StackSlot; 5441 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5442 if (TLI.isLittleEndian()) 5443 std::swap(Hi, Lo); 5444 5445 // if signed map to unsigned space 5446 SDValue Op0Mapped; 5447 if (isSigned) { 5448 // constant used to invert sign bit (signed to unsigned mapping) 5449 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5450 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5451 } else { 5452 Op0Mapped = Op0; 5453 } 5454 // store the lo of the constructed double - based on integer input 5455 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), 5456 Op0Mapped, Lo, NULL, 0); 5457 // initial hi portion of constructed double 5458 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5459 // store the hi of the constructed double - biased exponent 5460 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5461 // load the constructed double 5462 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5463 // FP constant to bias correct the final result 5464 SDValue Bias = DAG.getConstantFP(isSigned ? 5465 BitsToDouble(0x4330000080000000ULL) 5466 : BitsToDouble(0x4330000000000000ULL), 5467 MVT::f64); 5468 // subtract the bias 5469 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5470 // final result 5471 SDValue Result; 5472 // handle final rounding 5473 if (DestVT == MVT::f64) { 5474 // do nothing 5475 Result = Sub; 5476 } else if (DestVT.bitsLT(MVT::f64)) { 5477 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 5478 DAG.getIntPtrConstant(0)); 5479 } else if (DestVT.bitsGT(MVT::f64)) { 5480 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5481 } 5482 return Result; 5483 } 5484 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5485 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5486 5487 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0, 5488 DAG.getConstant(0, Op0.getValueType()), 5489 ISD::SETLT); 5490 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5491 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5492 SignSet, Four, Zero); 5493 5494 // If the sign bit of the integer is set, the large number will be treated 5495 // as a negative number. To counteract this, the dynamic code adds an 5496 // offset depending on the data type. 5497 uint64_t FF; 5498 switch (Op0.getValueType().getSimpleVT()) { 5499 default: assert(0 && "Unsupported integer type!"); 5500 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5501 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5502 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5503 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5504 } 5505 if (TLI.isLittleEndian()) FF <<= 32; 5506 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5507 5508 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5509 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5510 SDValue FudgeInReg; 5511 if (DestVT == MVT::f32) 5512 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5513 PseudoSourceValue::getConstantPool(), 0); 5514 else { 5515 FudgeInReg = 5516 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5517 DAG.getEntryNode(), CPIdx, 5518 PseudoSourceValue::getConstantPool(), 0, 5519 MVT::f32)); 5520 } 5521 5522 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5523} 5524 5525/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5526/// *INT_TO_FP operation of the specified operand when the target requests that 5527/// we promote it. At this point, we know that the result and operand types are 5528/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5529/// operation that takes a larger input. 5530SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 5531 MVT DestVT, 5532 bool isSigned) { 5533 // First step, figure out the appropriate *INT_TO_FP operation to use. 5534 MVT NewInTy = LegalOp.getValueType(); 5535 5536 unsigned OpToUse = 0; 5537 5538 // Scan for the appropriate larger type to use. 5539 while (1) { 5540 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 5541 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 5542 5543 // If the target supports SINT_TO_FP of this type, use it. 5544 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5545 default: break; 5546 case TargetLowering::Legal: 5547 if (!TLI.isTypeLegal(NewInTy)) 5548 break; // Can't use this datatype. 5549 // FALL THROUGH. 5550 case TargetLowering::Custom: 5551 OpToUse = ISD::SINT_TO_FP; 5552 break; 5553 } 5554 if (OpToUse) break; 5555 if (isSigned) continue; 5556 5557 // If the target supports UINT_TO_FP of this type, use it. 5558 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5559 default: break; 5560 case TargetLowering::Legal: 5561 if (!TLI.isTypeLegal(NewInTy)) 5562 break; // Can't use this datatype. 5563 // FALL THROUGH. 5564 case TargetLowering::Custom: 5565 OpToUse = ISD::UINT_TO_FP; 5566 break; 5567 } 5568 if (OpToUse) break; 5569 5570 // Otherwise, try a larger type. 5571 } 5572 5573 // Okay, we found the operation and type to use. Zero extend our input to the 5574 // desired type then run the operation on it. 5575 return DAG.getNode(OpToUse, DestVT, 5576 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5577 NewInTy, LegalOp)); 5578} 5579 5580/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5581/// FP_TO_*INT operation of the specified operand when the target requests that 5582/// we promote it. At this point, we know that the result and operand types are 5583/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5584/// operation that returns a larger result. 5585SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 5586 MVT DestVT, 5587 bool isSigned) { 5588 // First step, figure out the appropriate FP_TO*INT operation to use. 5589 MVT NewOutTy = DestVT; 5590 5591 unsigned OpToUse = 0; 5592 5593 // Scan for the appropriate larger type to use. 5594 while (1) { 5595 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 5596 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 5597 5598 // If the target supports FP_TO_SINT returning this type, use it. 5599 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5600 default: break; 5601 case TargetLowering::Legal: 5602 if (!TLI.isTypeLegal(NewOutTy)) 5603 break; // Can't use this datatype. 5604 // FALL THROUGH. 5605 case TargetLowering::Custom: 5606 OpToUse = ISD::FP_TO_SINT; 5607 break; 5608 } 5609 if (OpToUse) break; 5610 5611 // If the target supports FP_TO_UINT of this type, use it. 5612 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5613 default: break; 5614 case TargetLowering::Legal: 5615 if (!TLI.isTypeLegal(NewOutTy)) 5616 break; // Can't use this datatype. 5617 // FALL THROUGH. 5618 case TargetLowering::Custom: 5619 OpToUse = ISD::FP_TO_UINT; 5620 break; 5621 } 5622 if (OpToUse) break; 5623 5624 // Otherwise, try a larger type. 5625 } 5626 5627 5628 // Okay, we found the operation and type to use. 5629 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5630 5631 // If the operation produces an invalid type, it must be custom lowered. Use 5632 // the target lowering hooks to expand it. Just keep the low part of the 5633 // expanded operation, we know that we're truncating anyway. 5634 if (getTypeAction(NewOutTy) == Expand) { 5635 Operation = SDValue(TLI.ReplaceNodeResults(Operation.Val, DAG), 0); 5636 assert(Operation.Val && "Didn't return anything"); 5637 } 5638 5639 // Truncate the result of the extended FP_TO_*INT operation to the desired 5640 // size. 5641 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5642} 5643 5644/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5645/// 5646SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) { 5647 MVT VT = Op.getValueType(); 5648 MVT SHVT = TLI.getShiftAmountTy(); 5649 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5650 switch (VT.getSimpleVT()) { 5651 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5652 case MVT::i16: 5653 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5654 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5655 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5656 case MVT::i32: 5657 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5658 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5659 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5660 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5661 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5662 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5663 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5664 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5665 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5666 case MVT::i64: 5667 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5668 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5669 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5670 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5671 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5672 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5673 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5674 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5675 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5676 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5677 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5678 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5679 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5680 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5681 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5682 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5683 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5684 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5685 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5686 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5687 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5688 } 5689} 5690 5691/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5692/// 5693SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) { 5694 switch (Opc) { 5695 default: assert(0 && "Cannot expand this yet!"); 5696 case ISD::CTPOP: { 5697 static const uint64_t mask[6] = { 5698 0x5555555555555555ULL, 0x3333333333333333ULL, 5699 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5700 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5701 }; 5702 MVT VT = Op.getValueType(); 5703 MVT ShVT = TLI.getShiftAmountTy(); 5704 unsigned len = VT.getSizeInBits(); 5705 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5706 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5707 SDValue Tmp2 = DAG.getConstant(mask[i], VT); 5708 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5709 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5710 DAG.getNode(ISD::AND, VT, 5711 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5712 } 5713 return Op; 5714 } 5715 case ISD::CTLZ: { 5716 // for now, we do this: 5717 // x = x | (x >> 1); 5718 // x = x | (x >> 2); 5719 // ... 5720 // x = x | (x >>16); 5721 // x = x | (x >>32); // for 64-bit input 5722 // return popcount(~x); 5723 // 5724 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5725 MVT VT = Op.getValueType(); 5726 MVT ShVT = TLI.getShiftAmountTy(); 5727 unsigned len = VT.getSizeInBits(); 5728 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5729 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5730 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5731 } 5732 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5733 return DAG.getNode(ISD::CTPOP, VT, Op); 5734 } 5735 case ISD::CTTZ: { 5736 // for now, we use: { return popcount(~x & (x - 1)); } 5737 // unless the target has ctlz but not ctpop, in which case we use: 5738 // { return 32 - nlz(~x & (x-1)); } 5739 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5740 MVT VT = Op.getValueType(); 5741 SDValue Tmp2 = DAG.getConstant(~0ULL, VT); 5742 SDValue Tmp3 = DAG.getNode(ISD::AND, VT, 5743 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5744 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5745 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5746 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5747 TLI.isOperationLegal(ISD::CTLZ, VT)) 5748 return DAG.getNode(ISD::SUB, VT, 5749 DAG.getConstant(VT.getSizeInBits(), VT), 5750 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5751 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5752 } 5753 } 5754} 5755 5756/// ExpandOp - Expand the specified SDValue into its two component pieces 5757/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5758/// LegalizeNodes map is filled in for any results that are not expanded, the 5759/// ExpandedNodes map is filled in for any results that are expanded, and the 5760/// Lo/Hi values are returned. 5761void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ 5762 MVT VT = Op.getValueType(); 5763 MVT NVT = TLI.getTypeToTransformTo(VT); 5764 SDNode *Node = Op.Val; 5765 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5766 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || 5767 VT.isVector()) && "Cannot expand to FP value or to larger int value!"); 5768 5769 // See if we already expanded it. 5770 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I 5771 = ExpandedNodes.find(Op); 5772 if (I != ExpandedNodes.end()) { 5773 Lo = I->second.first; 5774 Hi = I->second.second; 5775 return; 5776 } 5777 5778 switch (Node->getOpcode()) { 5779 case ISD::CopyFromReg: 5780 assert(0 && "CopyFromReg must be legal!"); 5781 case ISD::FP_ROUND_INREG: 5782 if (VT == MVT::ppcf128 && 5783 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5784 TargetLowering::Custom) { 5785 SDValue SrcLo, SrcHi, Src; 5786 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5787 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5788 SDValue Result = TLI.LowerOperation( 5789 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5790 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5791 Lo = Result.Val->getOperand(0); 5792 Hi = Result.Val->getOperand(1); 5793 break; 5794 } 5795 // fall through 5796 default: 5797#ifndef NDEBUG 5798 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5799#endif 5800 assert(0 && "Do not know how to expand this operator!"); 5801 abort(); 5802 case ISD::EXTRACT_ELEMENT: 5803 ExpandOp(Node->getOperand(0), Lo, Hi); 5804 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 5805 return ExpandOp(Hi, Lo, Hi); 5806 return ExpandOp(Lo, Lo, Hi); 5807 case ISD::EXTRACT_VECTOR_ELT: 5808 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5809 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5810 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5811 return ExpandOp(Lo, Lo, Hi); 5812 case ISD::UNDEF: 5813 Lo = DAG.getNode(ISD::UNDEF, NVT); 5814 Hi = DAG.getNode(ISD::UNDEF, NVT); 5815 break; 5816 case ISD::Constant: { 5817 unsigned NVTBits = NVT.getSizeInBits(); 5818 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 5819 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 5820 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 5821 break; 5822 } 5823 case ISD::ConstantFP: { 5824 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5825 if (CFP->getValueType(0) == MVT::ppcf128) { 5826 APInt api = CFP->getValueAPF().convertToAPInt(); 5827 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5828 MVT::f64); 5829 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5830 MVT::f64); 5831 break; 5832 } 5833 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5834 if (getTypeAction(Lo.getValueType()) == Expand) 5835 ExpandOp(Lo, Lo, Hi); 5836 break; 5837 } 5838 case ISD::BUILD_PAIR: 5839 // Return the operands. 5840 Lo = Node->getOperand(0); 5841 Hi = Node->getOperand(1); 5842 break; 5843 5844 case ISD::MERGE_VALUES: 5845 if (Node->getNumValues() == 1) { 5846 ExpandOp(Op.getOperand(0), Lo, Hi); 5847 break; 5848 } 5849 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5850 assert(Op.ResNo == 0 && Node->getNumValues() == 2 && 5851 Op.getValue(1).getValueType() == MVT::Other && 5852 "unhandled MERGE_VALUES"); 5853 ExpandOp(Op.getOperand(0), Lo, Hi); 5854 // Remember that we legalized the chain. 5855 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5856 break; 5857 5858 case ISD::SIGN_EXTEND_INREG: 5859 ExpandOp(Node->getOperand(0), Lo, Hi); 5860 // sext_inreg the low part if needed. 5861 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5862 5863 // The high part gets the sign extension from the lo-part. This handles 5864 // things like sextinreg V:i64 from i8. 5865 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5866 DAG.getConstant(NVT.getSizeInBits()-1, 5867 TLI.getShiftAmountTy())); 5868 break; 5869 5870 case ISD::BSWAP: { 5871 ExpandOp(Node->getOperand(0), Lo, Hi); 5872 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5873 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5874 Lo = TempLo; 5875 break; 5876 } 5877 5878 case ISD::CTPOP: 5879 ExpandOp(Node->getOperand(0), Lo, Hi); 5880 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5881 DAG.getNode(ISD::CTPOP, NVT, Lo), 5882 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5883 Hi = DAG.getConstant(0, NVT); 5884 break; 5885 5886 case ISD::CTLZ: { 5887 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5888 ExpandOp(Node->getOperand(0), Lo, Hi); 5889 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 5890 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5891 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, 5892 ISD::SETNE); 5893 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5894 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5895 5896 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5897 Hi = DAG.getConstant(0, NVT); 5898 break; 5899 } 5900 5901 case ISD::CTTZ: { 5902 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5903 ExpandOp(Node->getOperand(0), Lo, Hi); 5904 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 5905 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5906 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, 5907 ISD::SETNE); 5908 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5909 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5910 5911 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5912 Hi = DAG.getConstant(0, NVT); 5913 break; 5914 } 5915 5916 case ISD::VAARG: { 5917 SDValue Ch = Node->getOperand(0); // Legalize the chain. 5918 SDValue Ptr = Node->getOperand(1); // Legalize the pointer. 5919 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5920 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5921 5922 // Remember that we legalized the chain. 5923 Hi = LegalizeOp(Hi); 5924 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5925 if (TLI.isBigEndian()) 5926 std::swap(Lo, Hi); 5927 break; 5928 } 5929 5930 case ISD::LOAD: { 5931 LoadSDNode *LD = cast<LoadSDNode>(Node); 5932 SDValue Ch = LD->getChain(); // Legalize the chain. 5933 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer. 5934 ISD::LoadExtType ExtType = LD->getExtensionType(); 5935 const Value *SV = LD->getSrcValue(); 5936 int SVOffset = LD->getSrcValueOffset(); 5937 unsigned Alignment = LD->getAlignment(); 5938 bool isVolatile = LD->isVolatile(); 5939 5940 if (ExtType == ISD::NON_EXTLOAD) { 5941 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset, 5942 isVolatile, Alignment); 5943 if (VT == MVT::f32 || VT == MVT::f64) { 5944 // f32->i32 or f64->i64 one to one expansion. 5945 // Remember that we legalized the chain. 5946 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 5947 // Recursively expand the new load. 5948 if (getTypeAction(NVT) == Expand) 5949 ExpandOp(Lo, Lo, Hi); 5950 break; 5951 } 5952 5953 // Increment the pointer to the other half. 5954 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 5955 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5956 DAG.getIntPtrConstant(IncrementSize)); 5957 SVOffset += IncrementSize; 5958 Alignment = MinAlign(Alignment, IncrementSize); 5959 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset, 5960 isVolatile, Alignment); 5961 5962 // Build a factor node to remember that this load is independent of the 5963 // other one. 5964 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5965 Hi.getValue(1)); 5966 5967 // Remember that we legalized the chain. 5968 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5969 if (TLI.isBigEndian()) 5970 std::swap(Lo, Hi); 5971 } else { 5972 MVT EVT = LD->getMemoryVT(); 5973 5974 if ((VT == MVT::f64 && EVT == MVT::f32) || 5975 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 5976 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5977 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV, 5978 SVOffset, isVolatile, Alignment); 5979 // Remember that we legalized the chain. 5980 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1))); 5981 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 5982 break; 5983 } 5984 5985 if (EVT == NVT) 5986 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, 5987 SVOffset, isVolatile, Alignment); 5988 else 5989 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV, 5990 SVOffset, EVT, isVolatile, 5991 Alignment); 5992 5993 // Remember that we legalized the chain. 5994 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 5995 5996 if (ExtType == ISD::SEXTLOAD) { 5997 // The high part is obtained by SRA'ing all but one of the bits of the 5998 // lo part. 5999 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6000 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6001 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6002 } else if (ExtType == ISD::ZEXTLOAD) { 6003 // The high part is just a zero. 6004 Hi = DAG.getConstant(0, NVT); 6005 } else /* if (ExtType == ISD::EXTLOAD) */ { 6006 // The high part is undefined. 6007 Hi = DAG.getNode(ISD::UNDEF, NVT); 6008 } 6009 } 6010 break; 6011 } 6012 case ISD::AND: 6013 case ISD::OR: 6014 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6015 SDValue LL, LH, RL, RH; 6016 ExpandOp(Node->getOperand(0), LL, LH); 6017 ExpandOp(Node->getOperand(1), RL, RH); 6018 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 6019 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 6020 break; 6021 } 6022 case ISD::SELECT: { 6023 SDValue LL, LH, RL, RH; 6024 ExpandOp(Node->getOperand(1), LL, LH); 6025 ExpandOp(Node->getOperand(2), RL, RH); 6026 if (getTypeAction(NVT) == Expand) 6027 NVT = TLI.getTypeToExpandTo(NVT); 6028 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 6029 if (VT != MVT::f32) 6030 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 6031 break; 6032 } 6033 case ISD::SELECT_CC: { 6034 SDValue TL, TH, FL, FH; 6035 ExpandOp(Node->getOperand(2), TL, TH); 6036 ExpandOp(Node->getOperand(3), FL, FH); 6037 if (getTypeAction(NVT) == Expand) 6038 NVT = TLI.getTypeToExpandTo(NVT); 6039 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6040 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6041 if (VT != MVT::f32) 6042 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6043 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6044 break; 6045 } 6046 case ISD::ANY_EXTEND: 6047 // The low part is any extension of the input (which degenerates to a copy). 6048 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 6049 // The high part is undefined. 6050 Hi = DAG.getNode(ISD::UNDEF, NVT); 6051 break; 6052 case ISD::SIGN_EXTEND: { 6053 // The low part is just a sign extension of the input (which degenerates to 6054 // a copy). 6055 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 6056 6057 // The high part is obtained by SRA'ing all but one of the bits of the lo 6058 // part. 6059 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6060 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6061 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6062 break; 6063 } 6064 case ISD::ZERO_EXTEND: 6065 // The low part is just a zero extension of the input (which degenerates to 6066 // a copy). 6067 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 6068 6069 // The high part is just a zero. 6070 Hi = DAG.getConstant(0, NVT); 6071 break; 6072 6073 case ISD::TRUNCATE: { 6074 // The input value must be larger than this value. Expand *it*. 6075 SDValue NewLo; 6076 ExpandOp(Node->getOperand(0), NewLo, Hi); 6077 6078 // The low part is now either the right size, or it is closer. If not the 6079 // right size, make an illegal truncate so we recursively expand it. 6080 if (NewLo.getValueType() != Node->getValueType(0)) 6081 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 6082 ExpandOp(NewLo, Lo, Hi); 6083 break; 6084 } 6085 6086 case ISD::BIT_CONVERT: { 6087 SDValue Tmp; 6088 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6089 // If the target wants to, allow it to lower this itself. 6090 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6091 case Expand: assert(0 && "cannot expand FP!"); 6092 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6093 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6094 } 6095 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 6096 } 6097 6098 // f32 / f64 must be expanded to i32 / i64. 6099 if (VT == MVT::f32 || VT == MVT::f64) { 6100 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6101 if (getTypeAction(NVT) == Expand) 6102 ExpandOp(Lo, Lo, Hi); 6103 break; 6104 } 6105 6106 // If source operand will be expanded to the same type as VT, i.e. 6107 // i64 <- f64, i32 <- f32, expand the source operand instead. 6108 MVT VT0 = Node->getOperand(0).getValueType(); 6109 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6110 ExpandOp(Node->getOperand(0), Lo, Hi); 6111 break; 6112 } 6113 6114 // Turn this into a load/store pair by default. 6115 if (Tmp.Val == 0) 6116 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 6117 6118 ExpandOp(Tmp, Lo, Hi); 6119 break; 6120 } 6121 6122 case ISD::READCYCLECOUNTER: { 6123 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6124 TargetLowering::Custom && 6125 "Must custom expand ReadCycleCounter"); 6126 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6127 assert(Tmp.Val && "Node must be custom expanded!"); 6128 ExpandOp(Tmp.getValue(0), Lo, Hi); 6129 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6130 LegalizeOp(Tmp.getValue(1))); 6131 break; 6132 } 6133 6134 case ISD::ATOMIC_CMP_SWAP: { 6135 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6136 assert(Tmp.Val && "Node must be custom expanded!"); 6137 ExpandOp(Tmp.getValue(0), Lo, Hi); 6138 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6139 LegalizeOp(Tmp.getValue(1))); 6140 break; 6141 } 6142 6143 6144 6145 // These operators cannot be expanded directly, emit them as calls to 6146 // library functions. 6147 case ISD::FP_TO_SINT: { 6148 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6149 SDValue Op; 6150 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6151 case Expand: assert(0 && "cannot expand FP!"); 6152 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6153 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6154 } 6155 6156 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6157 6158 // Now that the custom expander is done, expand the result, which is still 6159 // VT. 6160 if (Op.Val) { 6161 ExpandOp(Op, Lo, Hi); 6162 break; 6163 } 6164 } 6165 6166 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(), 6167 VT); 6168 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!"); 6169 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6170 break; 6171 } 6172 6173 case ISD::FP_TO_UINT: { 6174 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6175 SDValue Op; 6176 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6177 case Expand: assert(0 && "cannot expand FP!"); 6178 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6179 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6180 } 6181 6182 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6183 6184 // Now that the custom expander is done, expand the result. 6185 if (Op.Val) { 6186 ExpandOp(Op, Lo, Hi); 6187 break; 6188 } 6189 } 6190 6191 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(), 6192 VT); 6193 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 6194 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6195 break; 6196 } 6197 6198 case ISD::SHL: { 6199 // If the target wants custom lowering, do so. 6200 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6201 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6202 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6203 Op = TLI.LowerOperation(Op, DAG); 6204 if (Op.Val) { 6205 // Now that the custom expander is done, expand the result, which is 6206 // still VT. 6207 ExpandOp(Op, Lo, Hi); 6208 break; 6209 } 6210 } 6211 6212 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6213 // this X << 1 as X+X. 6214 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6215 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 6216 TLI.isOperationLegal(ISD::ADDE, NVT)) { 6217 SDValue LoOps[2], HiOps[3]; 6218 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6219 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6220 LoOps[1] = LoOps[0]; 6221 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6222 6223 HiOps[1] = HiOps[0]; 6224 HiOps[2] = Lo.getValue(1); 6225 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6226 break; 6227 } 6228 } 6229 6230 // If we can emit an efficient shift operation, do so now. 6231 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6232 break; 6233 6234 // If this target supports SHL_PARTS, use it. 6235 TargetLowering::LegalizeAction Action = 6236 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6237 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6238 Action == TargetLowering::Custom) { 6239 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6240 break; 6241 } 6242 6243 // Otherwise, emit a libcall. 6244 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6245 break; 6246 } 6247 6248 case ISD::SRA: { 6249 // If the target wants custom lowering, do so. 6250 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6251 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6252 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6253 Op = TLI.LowerOperation(Op, DAG); 6254 if (Op.Val) { 6255 // Now that the custom expander is done, expand the result, which is 6256 // still VT. 6257 ExpandOp(Op, Lo, Hi); 6258 break; 6259 } 6260 } 6261 6262 // If we can emit an efficient shift operation, do so now. 6263 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6264 break; 6265 6266 // If this target supports SRA_PARTS, use it. 6267 TargetLowering::LegalizeAction Action = 6268 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6269 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6270 Action == TargetLowering::Custom) { 6271 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6272 break; 6273 } 6274 6275 // Otherwise, emit a libcall. 6276 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6277 break; 6278 } 6279 6280 case ISD::SRL: { 6281 // If the target wants custom lowering, do so. 6282 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6283 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6284 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6285 Op = TLI.LowerOperation(Op, DAG); 6286 if (Op.Val) { 6287 // Now that the custom expander is done, expand the result, which is 6288 // still VT. 6289 ExpandOp(Op, Lo, Hi); 6290 break; 6291 } 6292 } 6293 6294 // If we can emit an efficient shift operation, do so now. 6295 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6296 break; 6297 6298 // If this target supports SRL_PARTS, use it. 6299 TargetLowering::LegalizeAction Action = 6300 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6301 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6302 Action == TargetLowering::Custom) { 6303 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6304 break; 6305 } 6306 6307 // Otherwise, emit a libcall. 6308 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6309 break; 6310 } 6311 6312 case ISD::ADD: 6313 case ISD::SUB: { 6314 // If the target wants to custom expand this, let them. 6315 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6316 TargetLowering::Custom) { 6317 SDValue Result = TLI.LowerOperation(Op, DAG); 6318 if (Result.Val) { 6319 ExpandOp(Result, Lo, Hi); 6320 break; 6321 } 6322 } 6323 6324 // Expand the subcomponents. 6325 SDValue LHSL, LHSH, RHSL, RHSH; 6326 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6327 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6328 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6329 SDValue LoOps[2], HiOps[3]; 6330 LoOps[0] = LHSL; 6331 LoOps[1] = RHSL; 6332 HiOps[0] = LHSH; 6333 HiOps[1] = RHSH; 6334 if (Node->getOpcode() == ISD::ADD) { 6335 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6336 HiOps[2] = Lo.getValue(1); 6337 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6338 } else { 6339 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6340 HiOps[2] = Lo.getValue(1); 6341 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6342 } 6343 break; 6344 } 6345 6346 case ISD::ADDC: 6347 case ISD::SUBC: { 6348 // Expand the subcomponents. 6349 SDValue LHSL, LHSH, RHSL, RHSH; 6350 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6351 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6352 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6353 SDValue LoOps[2] = { LHSL, RHSL }; 6354 SDValue HiOps[3] = { LHSH, RHSH }; 6355 6356 if (Node->getOpcode() == ISD::ADDC) { 6357 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6358 HiOps[2] = Lo.getValue(1); 6359 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6360 } else { 6361 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6362 HiOps[2] = Lo.getValue(1); 6363 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6364 } 6365 // Remember that we legalized the flag. 6366 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6367 break; 6368 } 6369 case ISD::ADDE: 6370 case ISD::SUBE: { 6371 // Expand the subcomponents. 6372 SDValue LHSL, LHSH, RHSL, RHSH; 6373 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6374 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6375 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6376 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 6377 SDValue HiOps[3] = { LHSH, RHSH }; 6378 6379 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6380 HiOps[2] = Lo.getValue(1); 6381 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6382 6383 // Remember that we legalized the flag. 6384 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6385 break; 6386 } 6387 case ISD::MUL: { 6388 // If the target wants to custom expand this, let them. 6389 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6390 SDValue New = TLI.LowerOperation(Op, DAG); 6391 if (New.Val) { 6392 ExpandOp(New, Lo, Hi); 6393 break; 6394 } 6395 } 6396 6397 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6398 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6399 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6400 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6401 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6402 SDValue LL, LH, RL, RH; 6403 ExpandOp(Node->getOperand(0), LL, LH); 6404 ExpandOp(Node->getOperand(1), RL, RH); 6405 unsigned OuterBitSize = Op.getValueSizeInBits(); 6406 unsigned InnerBitSize = RH.getValueSizeInBits(); 6407 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6408 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6409 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 6410 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 6411 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 6412 // The inputs are both zero-extended. 6413 if (HasUMUL_LOHI) { 6414 // We can emit a umul_lohi. 6415 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6416 Hi = SDValue(Lo.Val, 1); 6417 break; 6418 } 6419 if (HasMULHU) { 6420 // We can emit a mulhu+mul. 6421 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6422 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6423 break; 6424 } 6425 } 6426 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 6427 // The input values are both sign-extended. 6428 if (HasSMUL_LOHI) { 6429 // We can emit a smul_lohi. 6430 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6431 Hi = SDValue(Lo.Val, 1); 6432 break; 6433 } 6434 if (HasMULHS) { 6435 // We can emit a mulhs+mul. 6436 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6437 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6438 break; 6439 } 6440 } 6441 if (HasUMUL_LOHI) { 6442 // Lo,Hi = umul LHS, RHS. 6443 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6444 DAG.getVTList(NVT, NVT), LL, RL); 6445 Lo = UMulLOHI; 6446 Hi = UMulLOHI.getValue(1); 6447 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6448 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6449 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6450 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6451 break; 6452 } 6453 if (HasMULHU) { 6454 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6455 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6456 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6457 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6458 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6459 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6460 break; 6461 } 6462 } 6463 6464 // If nothing else, we can make a libcall. 6465 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 6466 break; 6467 } 6468 case ISD::SDIV: 6469 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 6470 break; 6471 case ISD::UDIV: 6472 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 6473 break; 6474 case ISD::SREM: 6475 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 6476 break; 6477 case ISD::UREM: 6478 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 6479 break; 6480 6481 case ISD::FADD: 6482 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 6483 RTLIB::ADD_F64, 6484 RTLIB::ADD_F80, 6485 RTLIB::ADD_PPCF128), 6486 Node, false, Hi); 6487 break; 6488 case ISD::FSUB: 6489 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 6490 RTLIB::SUB_F64, 6491 RTLIB::SUB_F80, 6492 RTLIB::SUB_PPCF128), 6493 Node, false, Hi); 6494 break; 6495 case ISD::FMUL: 6496 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 6497 RTLIB::MUL_F64, 6498 RTLIB::MUL_F80, 6499 RTLIB::MUL_PPCF128), 6500 Node, false, Hi); 6501 break; 6502 case ISD::FDIV: 6503 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 6504 RTLIB::DIV_F64, 6505 RTLIB::DIV_F80, 6506 RTLIB::DIV_PPCF128), 6507 Node, false, Hi); 6508 break; 6509 case ISD::FP_EXTEND: { 6510 if (VT == MVT::ppcf128) { 6511 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6512 Node->getOperand(0).getValueType()==MVT::f64); 6513 const uint64_t zero = 0; 6514 if (Node->getOperand(0).getValueType()==MVT::f32) 6515 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6516 else 6517 Hi = Node->getOperand(0); 6518 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6519 break; 6520 } 6521 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT); 6522 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!"); 6523 Lo = ExpandLibCall(LC, Node, true, Hi); 6524 break; 6525 } 6526 case ISD::FP_ROUND: { 6527 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(), 6528 VT); 6529 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!"); 6530 Lo = ExpandLibCall(LC, Node, true, Hi); 6531 break; 6532 } 6533 case ISD::FPOWI: 6534 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32, 6535 RTLIB::POWI_F64, 6536 RTLIB::POWI_F80, 6537 RTLIB::POWI_PPCF128), 6538 Node, false, Hi); 6539 break; 6540 case ISD::FTRUNC: 6541 case ISD::FFLOOR: 6542 case ISD::FCEIL: 6543 case ISD::FRINT: 6544 case ISD::FNEARBYINT: 6545 case ISD::FSQRT: 6546 case ISD::FSIN: 6547 case ISD::FCOS: { 6548 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6549 switch(Node->getOpcode()) { 6550 case ISD::FSQRT: 6551 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6552 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6553 break; 6554 case ISD::FSIN: 6555 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6556 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6557 break; 6558 case ISD::FCOS: 6559 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6560 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6561 break; 6562 case ISD::FTRUNC: 6563 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 6564 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 6565 break; 6566 case ISD::FFLOOR: 6567 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 6568 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 6569 break; 6570 case ISD::FCEIL: 6571 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 6572 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 6573 break; 6574 case ISD::FRINT: 6575 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 6576 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 6577 break; 6578 case ISD::FNEARBYINT: 6579 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 6580 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 6581 break; 6582 default: assert(0 && "Unreachable!"); 6583 } 6584 Lo = ExpandLibCall(LC, Node, false, Hi); 6585 break; 6586 } 6587 case ISD::FABS: { 6588 if (VT == MVT::ppcf128) { 6589 SDValue Tmp; 6590 ExpandOp(Node->getOperand(0), Lo, Tmp); 6591 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6592 // lo = hi==fabs(hi) ? lo : -lo; 6593 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6594 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6595 DAG.getCondCode(ISD::SETEQ)); 6596 break; 6597 } 6598 SDValue Mask = (VT == MVT::f64) 6599 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6600 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6601 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6602 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6603 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6604 if (getTypeAction(NVT) == Expand) 6605 ExpandOp(Lo, Lo, Hi); 6606 break; 6607 } 6608 case ISD::FNEG: { 6609 if (VT == MVT::ppcf128) { 6610 ExpandOp(Node->getOperand(0), Lo, Hi); 6611 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6612 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6613 break; 6614 } 6615 SDValue Mask = (VT == MVT::f64) 6616 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6617 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6618 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6619 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6620 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6621 if (getTypeAction(NVT) == Expand) 6622 ExpandOp(Lo, Lo, Hi); 6623 break; 6624 } 6625 case ISD::FCOPYSIGN: { 6626 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6627 if (getTypeAction(NVT) == Expand) 6628 ExpandOp(Lo, Lo, Hi); 6629 break; 6630 } 6631 case ISD::SINT_TO_FP: 6632 case ISD::UINT_TO_FP: { 6633 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6634 MVT SrcVT = Node->getOperand(0).getValueType(); 6635 6636 // Promote the operand if needed. Do this before checking for 6637 // ppcf128 so conversions of i16 and i8 work. 6638 if (getTypeAction(SrcVT) == Promote) { 6639 SDValue Tmp = PromoteOp(Node->getOperand(0)); 6640 Tmp = isSigned 6641 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6642 DAG.getValueType(SrcVT)) 6643 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6644 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6645 SrcVT = Node->getOperand(0).getValueType(); 6646 } 6647 6648 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 6649 static const uint64_t zero = 0; 6650 if (isSigned) { 6651 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6652 Node->getOperand(0))); 6653 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6654 } else { 6655 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6656 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6657 Node->getOperand(0))); 6658 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6659 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6660 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6661 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6662 DAG.getConstant(0, MVT::i32), 6663 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6664 DAG.getConstantFP( 6665 APFloat(APInt(128, 2, TwoE32)), 6666 MVT::ppcf128)), 6667 Hi, 6668 DAG.getCondCode(ISD::SETLT)), 6669 Lo, Hi); 6670 } 6671 break; 6672 } 6673 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6674 // si64->ppcf128 done by libcall, below 6675 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6676 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6677 Lo, Hi); 6678 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6679 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6680 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6681 DAG.getConstant(0, MVT::i64), 6682 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6683 DAG.getConstantFP( 6684 APFloat(APInt(128, 2, TwoE64)), 6685 MVT::ppcf128)), 6686 Hi, 6687 DAG.getCondCode(ISD::SETLT)), 6688 Lo, Hi); 6689 break; 6690 } 6691 6692 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6693 Node->getOperand(0)); 6694 if (getTypeAction(Lo.getValueType()) == Expand) 6695 // float to i32 etc. can be 'expanded' to a single node. 6696 ExpandOp(Lo, Lo, Hi); 6697 break; 6698 } 6699 } 6700 6701 // Make sure the resultant values have been legalized themselves, unless this 6702 // is a type that requires multi-step expansion. 6703 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6704 Lo = LegalizeOp(Lo); 6705 if (Hi.Val) 6706 // Don't legalize the high part if it is expanded to a single node. 6707 Hi = LegalizeOp(Hi); 6708 } 6709 6710 // Remember in a map if the values will be reused later. 6711 bool isNew = 6712 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 6713 assert(isNew && "Value already expanded?!?"); 6714} 6715 6716/// SplitVectorOp - Given an operand of vector type, break it down into 6717/// two smaller values, still of vector type. 6718void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo, 6719 SDValue &Hi) { 6720 assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); 6721 SDNode *Node = Op.Val; 6722 unsigned NumElements = Op.getValueType().getVectorNumElements(); 6723 assert(NumElements > 1 && "Cannot split a single element vector!"); 6724 6725 MVT NewEltVT = Op.getValueType().getVectorElementType(); 6726 6727 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6728 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6729 6730 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); 6731 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); 6732 6733 // See if we already split it. 6734 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I 6735 = SplitNodes.find(Op); 6736 if (I != SplitNodes.end()) { 6737 Lo = I->second.first; 6738 Hi = I->second.second; 6739 return; 6740 } 6741 6742 switch (Node->getOpcode()) { 6743 default: 6744#ifndef NDEBUG 6745 Node->dump(&DAG); 6746#endif 6747 assert(0 && "Unhandled operation in SplitVectorOp!"); 6748 case ISD::UNDEF: 6749 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6750 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6751 break; 6752 case ISD::BUILD_PAIR: 6753 Lo = Node->getOperand(0); 6754 Hi = Node->getOperand(1); 6755 break; 6756 case ISD::INSERT_VECTOR_ELT: { 6757 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 6758 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6759 unsigned Index = Idx->getValue(); 6760 SDValue ScalarOp = Node->getOperand(1); 6761 if (Index < NewNumElts_Lo) 6762 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6763 DAG.getIntPtrConstant(Index)); 6764 else 6765 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6766 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 6767 break; 6768 } 6769 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 6770 Node->getOperand(1), 6771 Node->getOperand(2)); 6772 SplitVectorOp(Tmp, Lo, Hi); 6773 break; 6774 } 6775 case ISD::VECTOR_SHUFFLE: { 6776 // Build the low part. 6777 SDValue Mask = Node->getOperand(2); 6778 SmallVector<SDValue, 8> Ops; 6779 MVT PtrVT = TLI.getPointerTy(); 6780 6781 // Insert all of the elements from the input that are needed. We use 6782 // buildvector of extractelement here because the input vectors will have 6783 // to be legalized, so this makes the code simpler. 6784 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6785 SDValue IdxNode = Mask.getOperand(i); 6786 if (IdxNode.getOpcode() == ISD::UNDEF) { 6787 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6788 continue; 6789 } 6790 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6791 SDValue InVec = Node->getOperand(0); 6792 if (Idx >= NumElements) { 6793 InVec = Node->getOperand(1); 6794 Idx -= NumElements; 6795 } 6796 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6797 DAG.getConstant(Idx, PtrVT))); 6798 } 6799 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6800 Ops.clear(); 6801 6802 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6803 SDValue IdxNode = Mask.getOperand(i); 6804 if (IdxNode.getOpcode() == ISD::UNDEF) { 6805 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6806 continue; 6807 } 6808 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6809 SDValue InVec = Node->getOperand(0); 6810 if (Idx >= NumElements) { 6811 InVec = Node->getOperand(1); 6812 Idx -= NumElements; 6813 } 6814 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6815 DAG.getConstant(Idx, PtrVT))); 6816 } 6817 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size()); 6818 break; 6819 } 6820 case ISD::BUILD_VECTOR: { 6821 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 6822 Node->op_begin()+NewNumElts_Lo); 6823 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6824 6825 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6826 Node->op_end()); 6827 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6828 break; 6829 } 6830 case ISD::CONCAT_VECTORS: { 6831 // FIXME: Handle non-power-of-two vectors? 6832 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6833 if (NewNumSubvectors == 1) { 6834 Lo = Node->getOperand(0); 6835 Hi = Node->getOperand(1); 6836 } else { 6837 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 6838 Node->op_begin()+NewNumSubvectors); 6839 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6840 6841 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6842 Node->op_end()); 6843 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6844 } 6845 break; 6846 } 6847 case ISD::SELECT: { 6848 SDValue Cond = Node->getOperand(0); 6849 6850 SDValue LL, LH, RL, RH; 6851 SplitVectorOp(Node->getOperand(1), LL, LH); 6852 SplitVectorOp(Node->getOperand(2), RL, RH); 6853 6854 if (Cond.getValueType().isVector()) { 6855 // Handle a vector merge. 6856 SDValue CL, CH; 6857 SplitVectorOp(Cond, CL, CH); 6858 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6859 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6860 } else { 6861 // Handle a simple select with vector operands. 6862 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6863 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6864 } 6865 break; 6866 } 6867 case ISD::SELECT_CC: { 6868 SDValue CondLHS = Node->getOperand(0); 6869 SDValue CondRHS = Node->getOperand(1); 6870 SDValue CondCode = Node->getOperand(4); 6871 6872 SDValue LL, LH, RL, RH; 6873 SplitVectorOp(Node->getOperand(2), LL, LH); 6874 SplitVectorOp(Node->getOperand(3), RL, RH); 6875 6876 // Handle a simple select with vector operands. 6877 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS, 6878 LL, RL, CondCode); 6879 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS, 6880 LH, RH, CondCode); 6881 break; 6882 } 6883 case ISD::VSETCC: { 6884 SDValue LL, LH, RL, RH; 6885 SplitVectorOp(Node->getOperand(0), LL, LH); 6886 SplitVectorOp(Node->getOperand(1), RL, RH); 6887 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2)); 6888 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2)); 6889 break; 6890 } 6891 case ISD::ADD: 6892 case ISD::SUB: 6893 case ISD::MUL: 6894 case ISD::FADD: 6895 case ISD::FSUB: 6896 case ISD::FMUL: 6897 case ISD::SDIV: 6898 case ISD::UDIV: 6899 case ISD::FDIV: 6900 case ISD::FPOW: 6901 case ISD::AND: 6902 case ISD::OR: 6903 case ISD::XOR: 6904 case ISD::UREM: 6905 case ISD::SREM: 6906 case ISD::FREM: { 6907 SDValue LL, LH, RL, RH; 6908 SplitVectorOp(Node->getOperand(0), LL, LH); 6909 SplitVectorOp(Node->getOperand(1), RL, RH); 6910 6911 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 6912 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 6913 break; 6914 } 6915 case ISD::FP_ROUND: 6916 case ISD::FPOWI: { 6917 SDValue L, H; 6918 SplitVectorOp(Node->getOperand(0), L, H); 6919 6920 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 6921 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 6922 break; 6923 } 6924 case ISD::CTTZ: 6925 case ISD::CTLZ: 6926 case ISD::CTPOP: 6927 case ISD::FNEG: 6928 case ISD::FABS: 6929 case ISD::FSQRT: 6930 case ISD::FSIN: 6931 case ISD::FCOS: 6932 case ISD::FP_TO_SINT: 6933 case ISD::FP_TO_UINT: 6934 case ISD::SINT_TO_FP: 6935 case ISD::UINT_TO_FP: 6936 case ISD::TRUNCATE: 6937 case ISD::ANY_EXTEND: 6938 case ISD::SIGN_EXTEND: 6939 case ISD::ZERO_EXTEND: 6940 case ISD::FP_EXTEND: { 6941 SDValue L, H; 6942 SplitVectorOp(Node->getOperand(0), L, H); 6943 6944 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 6945 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 6946 break; 6947 } 6948 case ISD::LOAD: { 6949 LoadSDNode *LD = cast<LoadSDNode>(Node); 6950 SDValue Ch = LD->getChain(); 6951 SDValue Ptr = LD->getBasePtr(); 6952 ISD::LoadExtType ExtType = LD->getExtensionType(); 6953 const Value *SV = LD->getSrcValue(); 6954 int SVOffset = LD->getSrcValueOffset(); 6955 MVT MemoryVT = LD->getMemoryVT(); 6956 unsigned Alignment = LD->getAlignment(); 6957 bool isVolatile = LD->isVolatile(); 6958 6959 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 6960 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); 6961 6962 MVT MemNewEltVT = MemoryVT.getVectorElementType(); 6963 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo); 6964 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi); 6965 6966 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, 6967 NewVT_Lo, Ch, Ptr, Offset, 6968 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment); 6969 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8; 6970 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6971 DAG.getIntPtrConstant(IncrementSize)); 6972 SVOffset += IncrementSize; 6973 Alignment = MinAlign(Alignment, IncrementSize); 6974 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, 6975 NewVT_Hi, Ch, Ptr, Offset, 6976 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment); 6977 6978 // Build a factor node to remember that this load is independent of the 6979 // other one. 6980 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6981 Hi.getValue(1)); 6982 6983 // Remember that we legalized the chain. 6984 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6985 break; 6986 } 6987 case ISD::BIT_CONVERT: { 6988 // We know the result is a vector. The input may be either a vector or a 6989 // scalar value. 6990 SDValue InOp = Node->getOperand(0); 6991 if (!InOp.getValueType().isVector() || 6992 InOp.getValueType().getVectorNumElements() == 1) { 6993 // The input is a scalar or single-element vector. 6994 // Lower to a store/load so that it can be split. 6995 // FIXME: this could be improved probably. 6996 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment( 6997 Op.getValueType().getTypeForMVT()); 6998 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign); 6999 int FI = cast<FrameIndexSDNode>(Ptr.Val)->getIndex(); 7000 7001 SDValue St = DAG.getStore(DAG.getEntryNode(), 7002 InOp, Ptr, 7003 PseudoSourceValue::getFixedStack(FI), 0); 7004 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 7005 PseudoSourceValue::getFixedStack(FI), 0); 7006 } 7007 // Split the vector and convert each of the pieces now. 7008 SplitVectorOp(InOp, Lo, Hi); 7009 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 7010 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 7011 break; 7012 } 7013 } 7014 7015 // Remember in a map if the values will be reused later. 7016 bool isNew = 7017 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7018 assert(isNew && "Value already split?!?"); 7019} 7020 7021 7022/// ScalarizeVectorOp - Given an operand of single-element vector type 7023/// (e.g. v1f32), convert it into the equivalent operation that returns a 7024/// scalar (e.g. f32) value. 7025SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) { 7026 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); 7027 SDNode *Node = Op.Val; 7028 MVT NewVT = Op.getValueType().getVectorElementType(); 7029 assert(Op.getValueType().getVectorNumElements() == 1); 7030 7031 // See if we already scalarized it. 7032 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op); 7033 if (I != ScalarizedNodes.end()) return I->second; 7034 7035 SDValue Result; 7036 switch (Node->getOpcode()) { 7037 default: 7038#ifndef NDEBUG 7039 Node->dump(&DAG); cerr << "\n"; 7040#endif 7041 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7042 case ISD::ADD: 7043 case ISD::FADD: 7044 case ISD::SUB: 7045 case ISD::FSUB: 7046 case ISD::MUL: 7047 case ISD::FMUL: 7048 case ISD::SDIV: 7049 case ISD::UDIV: 7050 case ISD::FDIV: 7051 case ISD::SREM: 7052 case ISD::UREM: 7053 case ISD::FREM: 7054 case ISD::FPOW: 7055 case ISD::AND: 7056 case ISD::OR: 7057 case ISD::XOR: 7058 Result = DAG.getNode(Node->getOpcode(), 7059 NewVT, 7060 ScalarizeVectorOp(Node->getOperand(0)), 7061 ScalarizeVectorOp(Node->getOperand(1))); 7062 break; 7063 case ISD::FNEG: 7064 case ISD::FABS: 7065 case ISD::FSQRT: 7066 case ISD::FSIN: 7067 case ISD::FCOS: 7068 case ISD::FP_TO_SINT: 7069 case ISD::FP_TO_UINT: 7070 case ISD::SINT_TO_FP: 7071 case ISD::UINT_TO_FP: 7072 case ISD::SIGN_EXTEND: 7073 case ISD::ZERO_EXTEND: 7074 case ISD::ANY_EXTEND: 7075 case ISD::TRUNCATE: 7076 case ISD::FP_EXTEND: 7077 Result = DAG.getNode(Node->getOpcode(), 7078 NewVT, 7079 ScalarizeVectorOp(Node->getOperand(0))); 7080 break; 7081 case ISD::FPOWI: 7082 case ISD::FP_ROUND: 7083 Result = DAG.getNode(Node->getOpcode(), 7084 NewVT, 7085 ScalarizeVectorOp(Node->getOperand(0)), 7086 Node->getOperand(1)); 7087 break; 7088 case ISD::LOAD: { 7089 LoadSDNode *LD = cast<LoadSDNode>(Node); 7090 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7091 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7092 ISD::LoadExtType ExtType = LD->getExtensionType(); 7093 const Value *SV = LD->getSrcValue(); 7094 int SVOffset = LD->getSrcValueOffset(); 7095 MVT MemoryVT = LD->getMemoryVT(); 7096 unsigned Alignment = LD->getAlignment(); 7097 bool isVolatile = LD->isVolatile(); 7098 7099 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7100 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); 7101 7102 Result = DAG.getLoad(ISD::UNINDEXED, ExtType, 7103 NewVT, Ch, Ptr, Offset, SV, SVOffset, 7104 MemoryVT.getVectorElementType(), 7105 isVolatile, Alignment); 7106 7107 // Remember that we legalized the chain. 7108 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7109 break; 7110 } 7111 case ISD::BUILD_VECTOR: 7112 Result = Node->getOperand(0); 7113 break; 7114 case ISD::INSERT_VECTOR_ELT: 7115 // Returning the inserted scalar element. 7116 Result = Node->getOperand(1); 7117 break; 7118 case ISD::CONCAT_VECTORS: 7119 assert(Node->getOperand(0).getValueType() == NewVT && 7120 "Concat of non-legal vectors not yet supported!"); 7121 Result = Node->getOperand(0); 7122 break; 7123 case ISD::VECTOR_SHUFFLE: { 7124 // Figure out if the scalar is the LHS or RHS and return it. 7125 SDValue EltNum = Node->getOperand(2).getOperand(0); 7126 if (cast<ConstantSDNode>(EltNum)->getValue()) 7127 Result = ScalarizeVectorOp(Node->getOperand(1)); 7128 else 7129 Result = ScalarizeVectorOp(Node->getOperand(0)); 7130 break; 7131 } 7132 case ISD::EXTRACT_SUBVECTOR: 7133 Result = Node->getOperand(0); 7134 assert(Result.getValueType() == NewVT); 7135 break; 7136 case ISD::BIT_CONVERT: { 7137 SDValue Op0 = Op.getOperand(0); 7138 if (Op0.getValueType().getVectorNumElements() == 1) 7139 Op0 = ScalarizeVectorOp(Op0); 7140 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); 7141 break; 7142 } 7143 case ISD::SELECT: 7144 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 7145 ScalarizeVectorOp(Op.getOperand(1)), 7146 ScalarizeVectorOp(Op.getOperand(2))); 7147 break; 7148 case ISD::SELECT_CC: 7149 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0), 7150 Node->getOperand(1), 7151 ScalarizeVectorOp(Op.getOperand(2)), 7152 ScalarizeVectorOp(Op.getOperand(3)), 7153 Node->getOperand(4)); 7154 break; 7155 case ISD::VSETCC: { 7156 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0)); 7157 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1)); 7158 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1, 7159 Op.getOperand(2)); 7160 Result = DAG.getNode(ISD::SELECT, NewVT, Result, 7161 DAG.getConstant(-1ULL, NewVT), 7162 DAG.getConstant(0ULL, NewVT)); 7163 break; 7164 } 7165 } 7166 7167 if (TLI.isTypeLegal(NewVT)) 7168 Result = LegalizeOp(Result); 7169 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7170 assert(isNew && "Value already scalarized?"); 7171 return Result; 7172} 7173 7174 7175// SelectionDAG::Legalize - This is the entry point for the file. 7176// 7177void SelectionDAG::Legalize() { 7178 /// run - This is the main entry point to this class. 7179 /// 7180 SelectionDAGLegalize(*this).LegalizeDAG(); 7181} 7182 7183