LegalizeDAG.cpp revision b7f6ef12f682c7068ca7513e088177a0d1046b35
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned ValueTypeActions; 56 57 /// NeedsAnotherIteration - This is set when we expand a large integer 58 /// operation into smaller integer operations, but the smaller operations are 59 /// not set. This occurs only rarely in practice, for targets that don't have 60 /// 32-bit or larger integer registers. 61 bool NeedsAnotherIteration; 62 63 /// LegalizedNodes - For nodes that are of legal width, and that have more 64 /// than one use, this map indicates what regularized operand to use. This 65 /// allows us to avoid legalizing the same thing more than once. 66 std::map<SDOperand, SDOperand> LegalizedNodes; 67 68 /// PromotedNodes - For nodes that are below legal width, and that have more 69 /// than one use, this map indicates what promoted value to use. This allows 70 /// us to avoid promoting the same thing more than once. 71 std::map<SDOperand, SDOperand> PromotedNodes; 72 73 /// ExpandedNodes - For nodes that need to be expanded, and which have more 74 /// than one use, this map indicates which which operands are the expanded 75 /// version of the input. This allows us to avoid expanding the same node 76 /// more than once. 77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 78 79 void AddLegalizedOperand(SDOperand From, SDOperand To) { 80 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second; 81 assert(isNew && "Got into the map somehow?"); 82 } 83 void AddPromotedOperand(SDOperand From, SDOperand To) { 84 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 85 assert(isNew && "Got into the map somehow?"); 86 } 87 88public: 89 90 SelectionDAGLegalize(SelectionDAG &DAG); 91 92 /// Run - While there is still lowering to do, perform a pass over the DAG. 93 /// Most regularization can be done in a single pass, but targets that require 94 /// large values to be split into registers multiple times (e.g. i64 -> 4x 95 /// i16) require iteration for these values (the first iteration will demote 96 /// to i32, the second will demote to i16). 97 void Run() { 98 do { 99 NeedsAnotherIteration = false; 100 LegalizeDAG(); 101 } while (NeedsAnotherIteration); 102 } 103 104 /// getTypeAction - Return how we should legalize values of this type, either 105 /// it is already legal or we need to expand it into multiple registers of 106 /// smaller integer type, or we need to promote it to a larger type. 107 LegalizeAction getTypeAction(MVT::ValueType VT) const { 108 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 109 } 110 111 /// isTypeLegal - Return true if this type is legal on this target. 112 /// 113 bool isTypeLegal(MVT::ValueType VT) const { 114 return getTypeAction(VT) == Legal; 115 } 116 117private: 118 void LegalizeDAG(); 119 120 SDOperand LegalizeOp(SDOperand O); 121 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 122 SDOperand PromoteOp(SDOperand O); 123 124 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 125 SDOperand &Hi); 126 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 127 SDOperand Source); 128 129 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 130 SDOperand LegalOp, 131 MVT::ValueType DestVT); 132 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 133 bool isSigned); 134 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 135 bool isSigned); 136 137 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 138 SDOperand &Lo, SDOperand &Hi); 139 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 140 SDOperand &Lo, SDOperand &Hi); 141 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 142 SDOperand &Lo, SDOperand &Hi); 143 144 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 145 146 SDOperand getIntPtrConstant(uint64_t Val) { 147 return DAG.getConstant(Val, TLI.getPointerTy()); 148 } 149}; 150} 151 152 153SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 154 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 155 ValueTypeActions(TLI.getValueTypeActions()) { 156 assert(MVT::LAST_VALUETYPE <= 16 && 157 "Too many value types for ValueTypeActions to hold!"); 158} 159 160/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 161/// INT_TO_FP operation of the specified operand when the target requests that 162/// we expand it. At this point, we know that the result and operand types are 163/// legal for the target. 164SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 165 SDOperand Op0, 166 MVT::ValueType DestVT) { 167 if (Op0.getValueType() == MVT::i32) { 168 // simple 32-bit [signed|unsigned] integer to float/double expansion 169 170 // get the stack frame index of a 8 byte buffer 171 MachineFunction &MF = DAG.getMachineFunction(); 172 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 173 // get address of 8 byte buffer 174 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 175 // word offset constant for Hi/Lo address computation 176 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 177 // set up Hi and Lo (into buffer) address based on endian 178 SDOperand Hi, Lo; 179 if (TLI.isLittleEndian()) { 180 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 181 Lo = StackSlot; 182 } else { 183 Hi = StackSlot; 184 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 185 } 186 // if signed map to unsigned space 187 SDOperand Op0Mapped; 188 if (isSigned) { 189 // constant used to invert sign bit (signed to unsigned mapping) 190 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 191 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 192 } else { 193 Op0Mapped = Op0; 194 } 195 // store the lo of the constructed double - based on integer input 196 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 197 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 198 // initial hi portion of constructed double 199 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 200 // store the hi of the constructed double - biased exponent 201 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 202 InitialHi, Hi, DAG.getSrcValue(NULL)); 203 // load the constructed double 204 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 205 DAG.getSrcValue(NULL)); 206 // FP constant to bias correct the final result 207 SDOperand Bias = DAG.getConstantFP(isSigned ? 208 BitsToDouble(0x4330000080000000ULL) 209 : BitsToDouble(0x4330000000000000ULL), 210 MVT::f64); 211 // subtract the bias 212 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 213 // final result 214 SDOperand Result; 215 // handle final rounding 216 if (DestVT == MVT::f64) { 217 // do nothing 218 Result = Sub; 219 } else { 220 // if f32 then cast to f32 221 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 222 } 223 NeedsAnotherIteration = true; 224 return Result; 225 } 226 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 227 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 228 229 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 230 DAG.getConstant(0, Op0.getValueType()), 231 ISD::SETLT); 232 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 233 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 234 SignSet, Four, Zero); 235 236 // If the sign bit of the integer is set, the large number will be treated 237 // as a negative number. To counteract this, the dynamic code adds an 238 // offset depending on the data type. 239 uint64_t FF; 240 switch (Op0.getValueType()) { 241 default: assert(0 && "Unsupported integer type!"); 242 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 243 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 244 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 245 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 246 } 247 if (TLI.isLittleEndian()) FF <<= 32; 248 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 249 250 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 251 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 252 SDOperand FudgeInReg; 253 if (DestVT == MVT::f32) 254 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 255 DAG.getSrcValue(NULL)); 256 else { 257 assert(DestVT == MVT::f64 && "Unexpected conversion"); 258 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 259 DAG.getEntryNode(), CPIdx, 260 DAG.getSrcValue(NULL), MVT::f32)); 261 } 262 263 NeedsAnotherIteration = true; 264 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 265} 266 267/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 268/// *INT_TO_FP operation of the specified operand when the target requests that 269/// we promote it. At this point, we know that the result and operand types are 270/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 271/// operation that takes a larger input. 272SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 273 MVT::ValueType DestVT, 274 bool isSigned) { 275 // First step, figure out the appropriate *INT_TO_FP operation to use. 276 MVT::ValueType NewInTy = LegalOp.getValueType(); 277 278 unsigned OpToUse = 0; 279 280 // Scan for the appropriate larger type to use. 281 while (1) { 282 NewInTy = (MVT::ValueType)(NewInTy+1); 283 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 284 285 // If the target supports SINT_TO_FP of this type, use it. 286 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 287 default: break; 288 case TargetLowering::Legal: 289 if (!TLI.isTypeLegal(NewInTy)) 290 break; // Can't use this datatype. 291 // FALL THROUGH. 292 case TargetLowering::Custom: 293 OpToUse = ISD::SINT_TO_FP; 294 break; 295 } 296 if (OpToUse) break; 297 if (isSigned) continue; 298 299 // If the target supports UINT_TO_FP of this type, use it. 300 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 301 default: break; 302 case TargetLowering::Legal: 303 if (!TLI.isTypeLegal(NewInTy)) 304 break; // Can't use this datatype. 305 // FALL THROUGH. 306 case TargetLowering::Custom: 307 OpToUse = ISD::UINT_TO_FP; 308 break; 309 } 310 if (OpToUse) break; 311 312 // Otherwise, try a larger type. 313 } 314 315 // Make sure to legalize any nodes we create here in the next pass. 316 NeedsAnotherIteration = true; 317 318 // Okay, we found the operation and type to use. Zero extend our input to the 319 // desired type then run the operation on it. 320 return DAG.getNode(OpToUse, DestVT, 321 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 322 NewInTy, LegalOp)); 323} 324 325/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 326/// FP_TO_*INT operation of the specified operand when the target requests that 327/// we promote it. At this point, we know that the result and operand types are 328/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 329/// operation that returns a larger result. 330SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 331 MVT::ValueType DestVT, 332 bool isSigned) { 333 // First step, figure out the appropriate FP_TO*INT operation to use. 334 MVT::ValueType NewOutTy = DestVT; 335 336 unsigned OpToUse = 0; 337 338 // Scan for the appropriate larger type to use. 339 while (1) { 340 NewOutTy = (MVT::ValueType)(NewOutTy+1); 341 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 342 343 // If the target supports FP_TO_SINT returning this type, use it. 344 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 345 default: break; 346 case TargetLowering::Legal: 347 if (!TLI.isTypeLegal(NewOutTy)) 348 break; // Can't use this datatype. 349 // FALL THROUGH. 350 case TargetLowering::Custom: 351 OpToUse = ISD::FP_TO_SINT; 352 break; 353 } 354 if (OpToUse) break; 355 356 // If the target supports FP_TO_UINT of this type, use it. 357 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 358 default: break; 359 case TargetLowering::Legal: 360 if (!TLI.isTypeLegal(NewOutTy)) 361 break; // Can't use this datatype. 362 // FALL THROUGH. 363 case TargetLowering::Custom: 364 OpToUse = ISD::FP_TO_UINT; 365 break; 366 } 367 if (OpToUse) break; 368 369 // Otherwise, try a larger type. 370 } 371 372 // Make sure to legalize any nodes we create here in the next pass. 373 NeedsAnotherIteration = true; 374 375 // Okay, we found the operation and type to use. Truncate the result of the 376 // extended FP_TO_*INT operation to the desired size. 377 return DAG.getNode(ISD::TRUNCATE, DestVT, 378 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 379} 380 381/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 382/// not been visited yet and if all of its operands have already been visited. 383static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 384 std::map<SDNode*, unsigned> &Visited) { 385 if (++Visited[N] != N->getNumOperands()) 386 return; // Haven't visited all operands yet 387 388 Order.push_back(N); 389 390 if (N->hasOneUse()) { // Tail recurse in common case. 391 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 392 return; 393 } 394 395 // Now that we have N in, add anything that uses it if all of their operands 396 // are now done. 397 398 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 399 ComputeTopDownOrdering(*UI, Order, Visited); 400} 401 402 403void SelectionDAGLegalize::LegalizeDAG() { 404 // The legalize process is inherently a bottom-up recursive process (users 405 // legalize their uses before themselves). Given infinite stack space, we 406 // could just start legalizing on the root and traverse the whole graph. In 407 // practice however, this causes us to run out of stack space on large basic 408 // blocks. To avoid this problem, compute an ordering of the nodes where each 409 // node is only legalized after all of its operands are legalized. 410 std::map<SDNode*, unsigned> Visited; 411 std::vector<SDNode*> Order; 412 413 // Compute ordering from all of the leaves in the graphs, those (like the 414 // entry node) that have no operands. 415 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 416 E = DAG.allnodes_end(); I != E; ++I) { 417 if ((*I)->getNumOperands() == 0) { 418 Visited[*I] = 0 - 1U; 419 ComputeTopDownOrdering(*I, Order, Visited); 420 } 421 } 422 423 assert(Order.size() == Visited.size() && Order.size() == DAG.allnodes_size()&& 424 "Error: DAG is cyclic!"); 425 Visited.clear(); 426 427 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 428 SDNode *N = Order[i]; 429 switch (getTypeAction(N->getValueType(0))) { 430 default: assert(0 && "Bad type action!"); 431 case Legal: 432 LegalizeOp(SDOperand(N, 0)); 433 break; 434 case Promote: 435 PromoteOp(SDOperand(N, 0)); 436 break; 437 case Expand: { 438 SDOperand X, Y; 439 ExpandOp(SDOperand(N, 0), X, Y); 440 break; 441 } 442 } 443 } 444 445 // Finally, it's possible the root changed. Get the new root. 446 SDOperand OldRoot = DAG.getRoot(); 447 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 448 DAG.setRoot(LegalizedNodes[OldRoot]); 449 450 ExpandedNodes.clear(); 451 LegalizedNodes.clear(); 452 PromotedNodes.clear(); 453 454 // Remove dead nodes now. 455 DAG.RemoveDeadNodes(OldRoot.Val); 456} 457 458SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 459 assert(isTypeLegal(Op.getValueType()) && 460 "Caller should expand or promote operands that are not legal!"); 461 SDNode *Node = Op.Val; 462 463 // If this operation defines any values that cannot be represented in a 464 // register on this target, make sure to expand or promote them. 465 if (Node->getNumValues() > 1) { 466 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 467 switch (getTypeAction(Node->getValueType(i))) { 468 case Legal: break; // Nothing to do. 469 case Expand: { 470 SDOperand T1, T2; 471 ExpandOp(Op.getValue(i), T1, T2); 472 assert(LegalizedNodes.count(Op) && 473 "Expansion didn't add legal operands!"); 474 return LegalizedNodes[Op]; 475 } 476 case Promote: 477 PromoteOp(Op.getValue(i)); 478 assert(LegalizedNodes.count(Op) && 479 "Expansion didn't add legal operands!"); 480 return LegalizedNodes[Op]; 481 } 482 } 483 484 // Note that LegalizeOp may be reentered even from single-use nodes, which 485 // means that we always must cache transformed nodes. 486 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 487 if (I != LegalizedNodes.end()) return I->second; 488 489 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 490 491 SDOperand Result = Op; 492 493 switch (Node->getOpcode()) { 494 default: 495 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 496 // If this is a target node, legalize it by legalizing the operands then 497 // passing it through. 498 std::vector<SDOperand> Ops; 499 bool Changed = false; 500 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 501 Ops.push_back(LegalizeOp(Node->getOperand(i))); 502 Changed = Changed || Node->getOperand(i) != Ops.back(); 503 } 504 if (Changed) 505 if (Node->getNumValues() == 1) 506 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 507 else { 508 std::vector<MVT::ValueType> VTs(Node->value_begin(), 509 Node->value_end()); 510 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 511 } 512 513 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 514 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 515 return Result.getValue(Op.ResNo); 516 } 517 // Otherwise this is an unhandled builtin node. splat. 518 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 519 assert(0 && "Do not know how to legalize this operator!"); 520 abort(); 521 case ISD::EntryToken: 522 case ISD::FrameIndex: 523 case ISD::TargetFrameIndex: 524 case ISD::Register: 525 case ISD::TargetConstant: 526 case ISD::GlobalAddress: 527 case ISD::ExternalSymbol: 528 case ISD::ConstantPool: // Nothing to do. 529 case ISD::BasicBlock: 530 case ISD::CONDCODE: 531 case ISD::VALUETYPE: 532 case ISD::SRCVALUE: 533 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!"); 534 break; 535 case ISD::AssertSext: 536 case ISD::AssertZext: 537 Tmp1 = LegalizeOp(Node->getOperand(0)); 538 if (Tmp1 != Node->getOperand(0)) 539 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 540 Node->getOperand(1)); 541 break; 542 case ISD::CopyFromReg: 543 Tmp1 = LegalizeOp(Node->getOperand(0)); 544 if (Tmp1 != Node->getOperand(0)) 545 Result = DAG.getCopyFromReg(Tmp1, 546 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 547 Node->getValueType(0)); 548 else 549 Result = Op.getValue(0); 550 551 // Since CopyFromReg produces two values, make sure to remember that we 552 // legalized both of them. 553 AddLegalizedOperand(Op.getValue(0), Result); 554 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 555 return Result.getValue(Op.ResNo); 556 case ISD::ImplicitDef: 557 Tmp1 = LegalizeOp(Node->getOperand(0)); 558 if (Tmp1 != Node->getOperand(0)) 559 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other, 560 Tmp1, Node->getOperand(1)); 561 break; 562 case ISD::UNDEF: { 563 MVT::ValueType VT = Op.getValueType(); 564 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 565 default: assert(0 && "This action is not supported yet!"); 566 case TargetLowering::Expand: 567 case TargetLowering::Promote: 568 if (MVT::isInteger(VT)) 569 Result = DAG.getConstant(0, VT); 570 else if (MVT::isFloatingPoint(VT)) 571 Result = DAG.getConstantFP(0, VT); 572 else 573 assert(0 && "Unknown value type!"); 574 break; 575 case TargetLowering::Legal: 576 break; 577 } 578 break; 579 } 580 case ISD::Constant: 581 // We know we don't need to expand constants here, constants only have one 582 // value and we check that it is fine above. 583 584 // FIXME: Maybe we should handle things like targets that don't support full 585 // 32-bit immediates? 586 break; 587 case ISD::ConstantFP: { 588 // Spill FP immediates to the constant pool if the target cannot directly 589 // codegen them. Targets often have some immediate values that can be 590 // efficiently generated into an FP register without a load. We explicitly 591 // leave these constants as ConstantFP nodes for the target to deal with. 592 593 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 594 595 // Check to see if this FP immediate is already legal. 596 bool isLegal = false; 597 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 598 E = TLI.legal_fpimm_end(); I != E; ++I) 599 if (CFP->isExactlyValue(*I)) { 600 isLegal = true; 601 break; 602 } 603 604 if (!isLegal) { 605 // Otherwise we need to spill the constant to memory. 606 bool Extend = false; 607 608 // If a FP immediate is precise when represented as a float, we put it 609 // into the constant pool as a float, even if it's is statically typed 610 // as a double. 611 MVT::ValueType VT = CFP->getValueType(0); 612 bool isDouble = VT == MVT::f64; 613 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 614 Type::FloatTy, CFP->getValue()); 615 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 616 // Only do this if the target has a native EXTLOAD instruction from 617 // f32. 618 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 619 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 620 VT = MVT::f32; 621 Extend = true; 622 } 623 624 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 625 if (Extend) { 626 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 627 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 628 } else { 629 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 630 DAG.getSrcValue(NULL)); 631 } 632 } 633 break; 634 } 635 case ISD::TokenFactor: { 636 std::vector<SDOperand> Ops; 637 bool Changed = false; 638 // Legalize the operands 639 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 640 SDOperand Op = Node->getOperand(i); 641 Ops.push_back(LegalizeOp(Op)); 642 Changed |= Ops[i] != Op; 643 } 644 if (Changed) 645 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 646 break; 647 } 648 649 case ISD::CALLSEQ_START: 650 case ISD::CALLSEQ_END: 651 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 652 // Do not try to legalize the target-specific arguments (#1+) 653 Tmp2 = Node->getOperand(0); 654 if (Tmp1 != Tmp2) 655 Node->setAdjCallChain(Tmp1); 656 657 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These 658 // nodes are treated specially and are mutated in place. This makes the dag 659 // legalization process more efficient and also makes libcall insertion 660 // easier. 661 break; 662 case ISD::DYNAMIC_STACKALLOC: 663 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 664 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 665 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 666 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 667 Tmp3 != Node->getOperand(2)) { 668 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 669 std::vector<SDOperand> Ops; 670 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 671 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 672 } else 673 Result = Op.getValue(0); 674 675 // Since this op produces two values, make sure to remember that we 676 // legalized both of them. 677 AddLegalizedOperand(SDOperand(Node, 0), Result); 678 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 679 return Result.getValue(Op.ResNo); 680 681 case ISD::TAILCALL: 682 case ISD::CALL: { 683 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 684 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 685 686 bool Changed = false; 687 std::vector<SDOperand> Ops; 688 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 689 Ops.push_back(LegalizeOp(Node->getOperand(i))); 690 Changed |= Ops.back() != Node->getOperand(i); 691 } 692 693 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 694 std::vector<MVT::ValueType> RetTyVTs; 695 RetTyVTs.reserve(Node->getNumValues()); 696 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 697 RetTyVTs.push_back(Node->getValueType(i)); 698 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 699 Node->getOpcode() == ISD::TAILCALL), 0); 700 } else { 701 Result = Result.getValue(0); 702 } 703 // Since calls produce multiple values, make sure to remember that we 704 // legalized all of them. 705 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 706 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 707 return Result.getValue(Op.ResNo); 708 } 709 case ISD::BR: 710 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 711 if (Tmp1 != Node->getOperand(0)) 712 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 713 break; 714 715 case ISD::BRCOND: 716 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 717 718 switch (getTypeAction(Node->getOperand(1).getValueType())) { 719 case Expand: assert(0 && "It's impossible to expand bools"); 720 case Legal: 721 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 722 break; 723 case Promote: 724 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 725 break; 726 } 727 728 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 729 default: assert(0 && "This action is not supported yet!"); 730 case TargetLowering::Expand: 731 // Expand brcond's setcc into its constituent parts and create a BR_CC 732 // Node. 733 if (Tmp2.getOpcode() == ISD::SETCC) { 734 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 735 Tmp2.getOperand(0), Tmp2.getOperand(1), 736 Node->getOperand(2)); 737 } else { 738 // Make sure the condition is either zero or one. It may have been 739 // promoted from something else. 740 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 741 742 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 743 DAG.getCondCode(ISD::SETNE), Tmp2, 744 DAG.getConstant(0, Tmp2.getValueType()), 745 Node->getOperand(2)); 746 } 747 break; 748 case TargetLowering::Legal: 749 // Basic block destination (Op#2) is always legal. 750 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 751 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 752 Node->getOperand(2)); 753 break; 754 } 755 break; 756 case ISD::BR_CC: 757 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 758 759 if (isTypeLegal(Node->getOperand(2).getValueType())) { 760 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 761 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 762 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 763 Tmp3 != Node->getOperand(3)) { 764 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 765 Tmp2, Tmp3, Node->getOperand(4)); 766 } 767 break; 768 } else { 769 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 770 Node->getOperand(2), // LHS 771 Node->getOperand(3), // RHS 772 Node->getOperand(1))); 773 // If we get a SETCC back from legalizing the SETCC node we just 774 // created, then use its LHS, RHS, and CC directly in creating a new 775 // node. Otherwise, select between the true and false value based on 776 // comparing the result of the legalized with zero. 777 if (Tmp2.getOpcode() == ISD::SETCC) { 778 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 779 Tmp2.getOperand(0), Tmp2.getOperand(1), 780 Node->getOperand(4)); 781 } else { 782 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 783 DAG.getCondCode(ISD::SETNE), 784 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 785 Node->getOperand(4)); 786 } 787 } 788 break; 789 case ISD::BRCONDTWOWAY: 790 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 791 switch (getTypeAction(Node->getOperand(1).getValueType())) { 792 case Expand: assert(0 && "It's impossible to expand bools"); 793 case Legal: 794 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 795 break; 796 case Promote: 797 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 798 break; 799 } 800 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 801 // pair. 802 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 803 case TargetLowering::Promote: 804 default: assert(0 && "This action is not supported yet!"); 805 case TargetLowering::Legal: 806 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 807 std::vector<SDOperand> Ops; 808 Ops.push_back(Tmp1); 809 Ops.push_back(Tmp2); 810 Ops.push_back(Node->getOperand(2)); 811 Ops.push_back(Node->getOperand(3)); 812 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 813 } 814 break; 815 case TargetLowering::Expand: 816 // If BRTWOWAY_CC is legal for this target, then simply expand this node 817 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 818 // BRCOND/BR pair. 819 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 820 if (Tmp2.getOpcode() == ISD::SETCC) { 821 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 822 Tmp2.getOperand(0), Tmp2.getOperand(1), 823 Node->getOperand(2), Node->getOperand(3)); 824 } else { 825 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 826 DAG.getConstant(0, Tmp2.getValueType()), 827 Node->getOperand(2), Node->getOperand(3)); 828 } 829 } else { 830 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 831 Node->getOperand(2)); 832 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 833 } 834 break; 835 } 836 break; 837 case ISD::BRTWOWAY_CC: 838 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 839 if (isTypeLegal(Node->getOperand(2).getValueType())) { 840 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 841 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 842 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 843 Tmp3 != Node->getOperand(3)) { 844 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3, 845 Node->getOperand(4), Node->getOperand(5)); 846 } 847 break; 848 } else { 849 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 850 Node->getOperand(2), // LHS 851 Node->getOperand(3), // RHS 852 Node->getOperand(1))); 853 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 854 // pair. 855 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 856 default: assert(0 && "This action is not supported yet!"); 857 case TargetLowering::Legal: 858 // If we get a SETCC back from legalizing the SETCC node we just 859 // created, then use its LHS, RHS, and CC directly in creating a new 860 // node. Otherwise, select between the true and false value based on 861 // comparing the result of the legalized with zero. 862 if (Tmp2.getOpcode() == ISD::SETCC) { 863 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 864 Tmp2.getOperand(0), Tmp2.getOperand(1), 865 Node->getOperand(4), Node->getOperand(5)); 866 } else { 867 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 868 DAG.getConstant(0, Tmp2.getValueType()), 869 Node->getOperand(4), Node->getOperand(5)); 870 } 871 break; 872 case TargetLowering::Expand: 873 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 874 Node->getOperand(4)); 875 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 876 break; 877 } 878 } 879 break; 880 case ISD::LOAD: 881 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 882 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 883 884 if (Tmp1 != Node->getOperand(0) || 885 Tmp2 != Node->getOperand(1)) 886 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, 887 Node->getOperand(2)); 888 else 889 Result = SDOperand(Node, 0); 890 891 // Since loads produce two values, make sure to remember that we legalized 892 // both of them. 893 AddLegalizedOperand(SDOperand(Node, 0), Result); 894 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 895 return Result.getValue(Op.ResNo); 896 897 case ISD::EXTLOAD: 898 case ISD::SEXTLOAD: 899 case ISD::ZEXTLOAD: { 900 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 901 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 902 903 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 904 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 905 default: assert(0 && "This action is not supported yet!"); 906 case TargetLowering::Promote: 907 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 908 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 909 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 910 // Since loads produce two values, make sure to remember that we legalized 911 // both of them. 912 AddLegalizedOperand(SDOperand(Node, 0), Result); 913 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 914 return Result.getValue(Op.ResNo); 915 916 case TargetLowering::Legal: 917 if (Tmp1 != Node->getOperand(0) || 918 Tmp2 != Node->getOperand(1)) 919 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 920 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 921 else 922 Result = SDOperand(Node, 0); 923 924 // Since loads produce two values, make sure to remember that we legalized 925 // both of them. 926 AddLegalizedOperand(SDOperand(Node, 0), Result); 927 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 928 return Result.getValue(Op.ResNo); 929 case TargetLowering::Expand: 930 //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 931 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 932 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 933 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 934 if (Op.ResNo) 935 return Load.getValue(1); 936 return Result; 937 } 938 assert(Node->getOpcode() != ISD::EXTLOAD && 939 "EXTLOAD should always be supported!"); 940 // Turn the unsupported load into an EXTLOAD followed by an explicit 941 // zero/sign extend inreg. 942 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 943 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 944 SDOperand ValRes; 945 if (Node->getOpcode() == ISD::SEXTLOAD) 946 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 947 Result, DAG.getValueType(SrcVT)); 948 else 949 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 950 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 951 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 952 if (Op.ResNo) 953 return Result.getValue(1); 954 return ValRes; 955 } 956 assert(0 && "Unreachable"); 957 } 958 case ISD::EXTRACT_ELEMENT: { 959 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 960 switch (getTypeAction(OpTy)) { 961 default: 962 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 963 break; 964 case Legal: 965 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 966 // 1 -> Hi 967 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 968 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 969 TLI.getShiftAmountTy())); 970 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 971 } else { 972 // 0 -> Lo 973 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 974 Node->getOperand(0)); 975 } 976 Result = LegalizeOp(Result); 977 break; 978 case Expand: 979 // Get both the low and high parts. 980 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 981 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 982 Result = Tmp2; // 1 -> Hi 983 else 984 Result = Tmp1; // 0 -> Lo 985 break; 986 } 987 break; 988 } 989 990 case ISD::CopyToReg: 991 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 992 993 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 994 "Register type must be legal!"); 995 // Legalize the incoming value (must be legal). 996 Tmp2 = LegalizeOp(Node->getOperand(2)); 997 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2)) 998 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1, 999 Node->getOperand(1), Tmp2); 1000 break; 1001 1002 case ISD::RET: 1003 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1004 switch (Node->getNumOperands()) { 1005 case 2: // ret val 1006 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1007 case Legal: 1008 Tmp2 = LegalizeOp(Node->getOperand(1)); 1009 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1010 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1011 break; 1012 case Expand: { 1013 SDOperand Lo, Hi; 1014 ExpandOp(Node->getOperand(1), Lo, Hi); 1015 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1016 break; 1017 } 1018 case Promote: 1019 Tmp2 = PromoteOp(Node->getOperand(1)); 1020 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1021 break; 1022 } 1023 break; 1024 case 1: // ret void 1025 if (Tmp1 != Node->getOperand(0)) 1026 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 1027 break; 1028 default: { // ret <values> 1029 std::vector<SDOperand> NewValues; 1030 NewValues.push_back(Tmp1); 1031 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1032 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1033 case Legal: 1034 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1035 break; 1036 case Expand: { 1037 SDOperand Lo, Hi; 1038 ExpandOp(Node->getOperand(i), Lo, Hi); 1039 NewValues.push_back(Lo); 1040 NewValues.push_back(Hi); 1041 break; 1042 } 1043 case Promote: 1044 assert(0 && "Can't promote multiple return value yet!"); 1045 } 1046 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1047 break; 1048 } 1049 } 1050 break; 1051 case ISD::STORE: 1052 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1053 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1054 1055 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1056 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1057 if (CFP->getValueType(0) == MVT::f32) { 1058 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1059 DAG.getConstant(FloatToBits(CFP->getValue()), 1060 MVT::i32), 1061 Tmp2, 1062 Node->getOperand(3)); 1063 } else { 1064 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1065 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1066 DAG.getConstant(DoubleToBits(CFP->getValue()), 1067 MVT::i64), 1068 Tmp2, 1069 Node->getOperand(3)); 1070 } 1071 Node = Result.Val; 1072 } 1073 1074 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1075 case Legal: { 1076 SDOperand Val = LegalizeOp(Node->getOperand(1)); 1077 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 1078 Tmp2 != Node->getOperand(2)) 1079 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 1080 Node->getOperand(3)); 1081 break; 1082 } 1083 case Promote: 1084 // Truncate the value and store the result. 1085 Tmp3 = PromoteOp(Node->getOperand(1)); 1086 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1087 Node->getOperand(3), 1088 DAG.getValueType(Node->getOperand(1).getValueType())); 1089 break; 1090 1091 case Expand: 1092 SDOperand Lo, Hi; 1093 ExpandOp(Node->getOperand(1), Lo, Hi); 1094 1095 if (!TLI.isLittleEndian()) 1096 std::swap(Lo, Hi); 1097 1098 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1099 Node->getOperand(3)); 1100 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1101 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1102 getIntPtrConstant(IncrementSize)); 1103 assert(isTypeLegal(Tmp2.getValueType()) && 1104 "Pointers must be legal!"); 1105 //Again, claiming both parts of the store came form the same Instr 1106 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1107 Node->getOperand(3)); 1108 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1109 break; 1110 } 1111 break; 1112 case ISD::PCMARKER: 1113 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1114 if (Tmp1 != Node->getOperand(0)) 1115 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 1116 break; 1117 case ISD::TRUNCSTORE: 1118 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1119 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1120 1121 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1122 case Legal: 1123 Tmp2 = LegalizeOp(Node->getOperand(1)); 1124 1125 // The only promote case we handle is TRUNCSTORE:i1 X into 1126 // -> TRUNCSTORE:i8 (and X, 1) 1127 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1128 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1129 TargetLowering::Promote) { 1130 // Promote the bool to a mask then store. 1131 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1132 DAG.getConstant(1, Tmp2.getValueType())); 1133 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1134 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1135 1136 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1137 Tmp3 != Node->getOperand(2)) { 1138 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1139 Node->getOperand(3), Node->getOperand(4)); 1140 } 1141 break; 1142 case Promote: 1143 case Expand: 1144 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 1145 } 1146 break; 1147 case ISD::SELECT: 1148 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1149 case Expand: assert(0 && "It's impossible to expand bools"); 1150 case Legal: 1151 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1152 break; 1153 case Promote: 1154 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1155 break; 1156 } 1157 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1158 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1159 1160 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1161 default: assert(0 && "This action is not supported yet!"); 1162 case TargetLowering::Expand: 1163 if (Tmp1.getOpcode() == ISD::SETCC) { 1164 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1165 Tmp2, Tmp3, 1166 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1167 } else { 1168 // Make sure the condition is either zero or one. It may have been 1169 // promoted from something else. 1170 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1171 Result = DAG.getSelectCC(Tmp1, 1172 DAG.getConstant(0, Tmp1.getValueType()), 1173 Tmp2, Tmp3, ISD::SETNE); 1174 } 1175 break; 1176 case TargetLowering::Legal: 1177 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1178 Tmp3 != Node->getOperand(2)) 1179 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 1180 Tmp1, Tmp2, Tmp3); 1181 break; 1182 case TargetLowering::Promote: { 1183 MVT::ValueType NVT = 1184 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1185 unsigned ExtOp, TruncOp; 1186 if (MVT::isInteger(Tmp2.getValueType())) { 1187 ExtOp = ISD::ANY_EXTEND; 1188 TruncOp = ISD::TRUNCATE; 1189 } else { 1190 ExtOp = ISD::FP_EXTEND; 1191 TruncOp = ISD::FP_ROUND; 1192 } 1193 // Promote each of the values to the new type. 1194 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1195 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1196 // Perform the larger operation, then round down. 1197 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1198 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1199 break; 1200 } 1201 } 1202 break; 1203 case ISD::SELECT_CC: 1204 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1205 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1206 1207 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1208 // Everything is legal, see if we should expand this op or something. 1209 switch (TLI.getOperationAction(ISD::SELECT_CC, 1210 Node->getOperand(0).getValueType())) { 1211 default: assert(0 && "This action is not supported yet!"); 1212 case TargetLowering::Custom: { 1213 SDOperand Tmp = 1214 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), 1215 Node->getOperand(0), 1216 Node->getOperand(1), Tmp3, Tmp4, 1217 Node->getOperand(4)), DAG); 1218 if (Tmp.Val) { 1219 Result = LegalizeOp(Tmp); 1220 break; 1221 } 1222 } // FALLTHROUGH if the target can't lower this operation after all. 1223 case TargetLowering::Legal: 1224 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1225 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1226 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1227 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { 1228 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2, 1229 Tmp3, Tmp4, Node->getOperand(4)); 1230 } 1231 break; 1232 } 1233 break; 1234 } else { 1235 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1236 Node->getOperand(0), // LHS 1237 Node->getOperand(1), // RHS 1238 Node->getOperand(4))); 1239 // If we get a SETCC back from legalizing the SETCC node we just 1240 // created, then use its LHS, RHS, and CC directly in creating a new 1241 // node. Otherwise, select between the true and false value based on 1242 // comparing the result of the legalized with zero. 1243 if (Tmp1.getOpcode() == ISD::SETCC) { 1244 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1245 Tmp1.getOperand(0), Tmp1.getOperand(1), 1246 Tmp3, Tmp4, Tmp1.getOperand(2)); 1247 } else { 1248 Result = DAG.getSelectCC(Tmp1, 1249 DAG.getConstant(0, Tmp1.getValueType()), 1250 Tmp3, Tmp4, ISD::SETNE); 1251 } 1252 } 1253 break; 1254 case ISD::SETCC: 1255 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1256 case Legal: 1257 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1258 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1259 break; 1260 case Promote: 1261 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1262 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1263 1264 // If this is an FP compare, the operands have already been extended. 1265 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1266 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1267 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1268 1269 // Otherwise, we have to insert explicit sign or zero extends. Note 1270 // that we could insert sign extends for ALL conditions, but zero extend 1271 // is cheaper on many machines (an AND instead of two shifts), so prefer 1272 // it. 1273 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1274 default: assert(0 && "Unknown integer comparison!"); 1275 case ISD::SETEQ: 1276 case ISD::SETNE: 1277 case ISD::SETUGE: 1278 case ISD::SETUGT: 1279 case ISD::SETULE: 1280 case ISD::SETULT: 1281 // ALL of these operations will work if we either sign or zero extend 1282 // the operands (including the unsigned comparisons!). Zero extend is 1283 // usually a simpler/cheaper operation, so prefer it. 1284 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1285 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1286 break; 1287 case ISD::SETGE: 1288 case ISD::SETGT: 1289 case ISD::SETLT: 1290 case ISD::SETLE: 1291 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1292 DAG.getValueType(VT)); 1293 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1294 DAG.getValueType(VT)); 1295 break; 1296 } 1297 } 1298 break; 1299 case Expand: 1300 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1301 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1302 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1303 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1304 case ISD::SETEQ: 1305 case ISD::SETNE: 1306 if (RHSLo == RHSHi) 1307 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1308 if (RHSCST->isAllOnesValue()) { 1309 // Comparison to -1. 1310 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1311 Tmp2 = RHSLo; 1312 break; 1313 } 1314 1315 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1316 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1317 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1318 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1319 break; 1320 default: 1321 // If this is a comparison of the sign bit, just look at the top part. 1322 // X > -1, x < 0 1323 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1324 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1325 CST->getValue() == 0) || // X < 0 1326 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1327 (CST->isAllOnesValue()))) { // X > -1 1328 Tmp1 = LHSHi; 1329 Tmp2 = RHSHi; 1330 break; 1331 } 1332 1333 // FIXME: This generated code sucks. 1334 ISD::CondCode LowCC; 1335 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1336 default: assert(0 && "Unknown integer setcc!"); 1337 case ISD::SETLT: 1338 case ISD::SETULT: LowCC = ISD::SETULT; break; 1339 case ISD::SETGT: 1340 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1341 case ISD::SETLE: 1342 case ISD::SETULE: LowCC = ISD::SETULE; break; 1343 case ISD::SETGE: 1344 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1345 } 1346 1347 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1348 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1349 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1350 1351 // NOTE: on targets without efficient SELECT of bools, we can always use 1352 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1353 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1354 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1355 Node->getOperand(2)); 1356 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1357 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1358 Result, Tmp1, Tmp2)); 1359 return Result; 1360 } 1361 } 1362 1363 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) { 1364 default: 1365 assert(0 && "Cannot handle this action for SETCC yet!"); 1366 break; 1367 case TargetLowering::Promote: 1368 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1369 Node->getOperand(2)); 1370 break; 1371 case TargetLowering::Legal: 1372 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1373 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1374 Node->getOperand(2)); 1375 break; 1376 case TargetLowering::Expand: 1377 // Expand a setcc node into a select_cc of the same condition, lhs, and 1378 // rhs that selects between const 1 (true) and const 0 (false). 1379 MVT::ValueType VT = Node->getValueType(0); 1380 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1381 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1382 Node->getOperand(2)); 1383 Result = LegalizeOp(Result); 1384 break; 1385 } 1386 break; 1387 1388 case ISD::MEMSET: 1389 case ISD::MEMCPY: 1390 case ISD::MEMMOVE: { 1391 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1392 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1393 1394 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1395 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1396 case Expand: assert(0 && "Cannot expand a byte!"); 1397 case Legal: 1398 Tmp3 = LegalizeOp(Node->getOperand(2)); 1399 break; 1400 case Promote: 1401 Tmp3 = PromoteOp(Node->getOperand(2)); 1402 break; 1403 } 1404 } else { 1405 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1406 } 1407 1408 SDOperand Tmp4; 1409 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1410 case Expand: { 1411 // Length is too big, just take the lo-part of the length. 1412 SDOperand HiPart; 1413 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1414 break; 1415 } 1416 case Legal: 1417 Tmp4 = LegalizeOp(Node->getOperand(3)); 1418 break; 1419 case Promote: 1420 Tmp4 = PromoteOp(Node->getOperand(3)); 1421 break; 1422 } 1423 1424 SDOperand Tmp5; 1425 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1426 case Expand: assert(0 && "Cannot expand this yet!"); 1427 case Legal: 1428 Tmp5 = LegalizeOp(Node->getOperand(4)); 1429 break; 1430 case Promote: 1431 Tmp5 = PromoteOp(Node->getOperand(4)); 1432 break; 1433 } 1434 1435 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1436 default: assert(0 && "This action not implemented for this operation!"); 1437 case TargetLowering::Custom: { 1438 SDOperand Tmp = 1439 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 1440 Tmp2, Tmp3, Tmp4, Tmp5), DAG); 1441 if (Tmp.Val) { 1442 Result = LegalizeOp(Tmp); 1443 break; 1444 } 1445 // FALLTHROUGH if the target thinks it is legal. 1446 } 1447 case TargetLowering::Legal: 1448 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1449 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 1450 Tmp5 != Node->getOperand(4)) { 1451 std::vector<SDOperand> Ops; 1452 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 1453 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 1454 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 1455 } 1456 break; 1457 case TargetLowering::Expand: { 1458 // Otherwise, the target does not support this operation. Lower the 1459 // operation to an explicit libcall as appropriate. 1460 MVT::ValueType IntPtr = TLI.getPointerTy(); 1461 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1462 std::vector<std::pair<SDOperand, const Type*> > Args; 1463 1464 const char *FnName = 0; 1465 if (Node->getOpcode() == ISD::MEMSET) { 1466 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1467 // Extend the ubyte argument to be an int value for the call. 1468 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1469 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1470 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1471 1472 FnName = "memset"; 1473 } else if (Node->getOpcode() == ISD::MEMCPY || 1474 Node->getOpcode() == ISD::MEMMOVE) { 1475 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1476 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1477 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1478 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1479 } else { 1480 assert(0 && "Unknown op!"); 1481 } 1482 1483 std::pair<SDOperand,SDOperand> CallResult = 1484 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1485 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1486 Result = CallResult.second; 1487 NeedsAnotherIteration = true; 1488 break; 1489 } 1490 } 1491 break; 1492 } 1493 1494 case ISD::READPORT: 1495 Tmp1 = LegalizeOp(Node->getOperand(0)); 1496 Tmp2 = LegalizeOp(Node->getOperand(1)); 1497 1498 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1499 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1500 std::vector<SDOperand> Ops; 1501 Ops.push_back(Tmp1); 1502 Ops.push_back(Tmp2); 1503 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1504 } else 1505 Result = SDOperand(Node, 0); 1506 // Since these produce two values, make sure to remember that we legalized 1507 // both of them. 1508 AddLegalizedOperand(SDOperand(Node, 0), Result); 1509 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1510 return Result.getValue(Op.ResNo); 1511 case ISD::WRITEPORT: 1512 Tmp1 = LegalizeOp(Node->getOperand(0)); 1513 Tmp2 = LegalizeOp(Node->getOperand(1)); 1514 Tmp3 = LegalizeOp(Node->getOperand(2)); 1515 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1516 Tmp3 != Node->getOperand(2)) 1517 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1518 break; 1519 1520 case ISD::READIO: 1521 Tmp1 = LegalizeOp(Node->getOperand(0)); 1522 Tmp2 = LegalizeOp(Node->getOperand(1)); 1523 1524 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1525 case TargetLowering::Custom: 1526 default: assert(0 && "This action not implemented for this operation!"); 1527 case TargetLowering::Legal: 1528 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1529 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1530 std::vector<SDOperand> Ops; 1531 Ops.push_back(Tmp1); 1532 Ops.push_back(Tmp2); 1533 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1534 } else 1535 Result = SDOperand(Node, 0); 1536 break; 1537 case TargetLowering::Expand: 1538 // Replace this with a load from memory. 1539 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 1540 Node->getOperand(1), DAG.getSrcValue(NULL)); 1541 Result = LegalizeOp(Result); 1542 break; 1543 } 1544 1545 // Since these produce two values, make sure to remember that we legalized 1546 // both of them. 1547 AddLegalizedOperand(SDOperand(Node, 0), Result); 1548 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1549 return Result.getValue(Op.ResNo); 1550 1551 case ISD::WRITEIO: 1552 Tmp1 = LegalizeOp(Node->getOperand(0)); 1553 Tmp2 = LegalizeOp(Node->getOperand(1)); 1554 Tmp3 = LegalizeOp(Node->getOperand(2)); 1555 1556 switch (TLI.getOperationAction(Node->getOpcode(), 1557 Node->getOperand(1).getValueType())) { 1558 case TargetLowering::Custom: 1559 default: assert(0 && "This action not implemented for this operation!"); 1560 case TargetLowering::Legal: 1561 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1562 Tmp3 != Node->getOperand(2)) 1563 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1564 break; 1565 case TargetLowering::Expand: 1566 // Replace this with a store to memory. 1567 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 1568 Node->getOperand(1), Node->getOperand(2), 1569 DAG.getSrcValue(NULL)); 1570 Result = LegalizeOp(Result); 1571 break; 1572 } 1573 break; 1574 1575 case ISD::ADD_PARTS: 1576 case ISD::SUB_PARTS: 1577 case ISD::SHL_PARTS: 1578 case ISD::SRA_PARTS: 1579 case ISD::SRL_PARTS: { 1580 std::vector<SDOperand> Ops; 1581 bool Changed = false; 1582 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1583 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1584 Changed |= Ops.back() != Node->getOperand(i); 1585 } 1586 if (Changed) { 1587 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1588 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 1589 } 1590 1591 // Since these produce multiple values, make sure to remember that we 1592 // legalized all of them. 1593 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1594 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1595 return Result.getValue(Op.ResNo); 1596 } 1597 1598 // Binary operators 1599 case ISD::ADD: 1600 case ISD::SUB: 1601 case ISD::MUL: 1602 case ISD::MULHS: 1603 case ISD::MULHU: 1604 case ISD::UDIV: 1605 case ISD::SDIV: 1606 case ISD::AND: 1607 case ISD::OR: 1608 case ISD::XOR: 1609 case ISD::SHL: 1610 case ISD::SRL: 1611 case ISD::SRA: 1612 case ISD::FADD: 1613 case ISD::FSUB: 1614 case ISD::FMUL: 1615 case ISD::FDIV: 1616 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1617 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1618 case Expand: assert(0 && "Not possible"); 1619 case Legal: 1620 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1621 break; 1622 case Promote: 1623 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 1624 break; 1625 } 1626 if (Tmp1 != Node->getOperand(0) || 1627 Tmp2 != Node->getOperand(1)) 1628 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 1629 break; 1630 1631 case ISD::BUILD_PAIR: { 1632 MVT::ValueType PairTy = Node->getValueType(0); 1633 // TODO: handle the case where the Lo and Hi operands are not of legal type 1634 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 1635 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 1636 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 1637 case TargetLowering::Legal: 1638 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1639 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 1640 break; 1641 case TargetLowering::Promote: 1642 case TargetLowering::Custom: 1643 assert(0 && "Cannot promote/custom this yet!"); 1644 case TargetLowering::Expand: 1645 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 1646 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 1647 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 1648 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 1649 TLI.getShiftAmountTy())); 1650 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2)); 1651 break; 1652 } 1653 break; 1654 } 1655 1656 case ISD::UREM: 1657 case ISD::SREM: 1658 case ISD::FREM: 1659 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1660 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1661 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1662 case TargetLowering::Legal: 1663 if (Tmp1 != Node->getOperand(0) || 1664 Tmp2 != Node->getOperand(1)) 1665 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1666 Tmp2); 1667 break; 1668 case TargetLowering::Promote: 1669 case TargetLowering::Custom: 1670 assert(0 && "Cannot promote/custom handle this yet!"); 1671 case TargetLowering::Expand: 1672 if (MVT::isInteger(Node->getValueType(0))) { 1673 MVT::ValueType VT = Node->getValueType(0); 1674 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 1675 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 1676 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 1677 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 1678 } else { 1679 // Floating point mod -> fmod libcall. 1680 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 1681 SDOperand Dummy; 1682 Result = ExpandLibCall(FnName, Node, Dummy); 1683 } 1684 break; 1685 } 1686 break; 1687 1688 case ISD::CTPOP: 1689 case ISD::CTTZ: 1690 case ISD::CTLZ: 1691 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1692 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1693 case TargetLowering::Legal: 1694 if (Tmp1 != Node->getOperand(0)) 1695 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1696 break; 1697 case TargetLowering::Promote: { 1698 MVT::ValueType OVT = Tmp1.getValueType(); 1699 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1700 1701 // Zero extend the argument. 1702 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1703 // Perform the larger operation, then subtract if needed. 1704 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1705 switch(Node->getOpcode()) 1706 { 1707 case ISD::CTPOP: 1708 Result = Tmp1; 1709 break; 1710 case ISD::CTTZ: 1711 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 1712 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 1713 DAG.getConstant(getSizeInBits(NVT), NVT), 1714 ISD::SETEQ); 1715 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 1716 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 1717 break; 1718 case ISD::CTLZ: 1719 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 1720 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 1721 DAG.getConstant(getSizeInBits(NVT) - 1722 getSizeInBits(OVT), NVT)); 1723 break; 1724 } 1725 break; 1726 } 1727 case TargetLowering::Custom: 1728 assert(0 && "Cannot custom handle this yet!"); 1729 case TargetLowering::Expand: 1730 switch(Node->getOpcode()) 1731 { 1732 case ISD::CTPOP: { 1733 static const uint64_t mask[6] = { 1734 0x5555555555555555ULL, 0x3333333333333333ULL, 1735 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 1736 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 1737 }; 1738 MVT::ValueType VT = Tmp1.getValueType(); 1739 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1740 unsigned len = getSizeInBits(VT); 1741 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1742 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 1743 Tmp2 = DAG.getConstant(mask[i], VT); 1744 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1745 Tmp1 = DAG.getNode(ISD::ADD, VT, 1746 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 1747 DAG.getNode(ISD::AND, VT, 1748 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 1749 Tmp2)); 1750 } 1751 Result = Tmp1; 1752 break; 1753 } 1754 case ISD::CTLZ: { 1755 /* for now, we do this: 1756 x = x | (x >> 1); 1757 x = x | (x >> 2); 1758 ... 1759 x = x | (x >>16); 1760 x = x | (x >>32); // for 64-bit input 1761 return popcount(~x); 1762 1763 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ 1764 MVT::ValueType VT = Tmp1.getValueType(); 1765 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1766 unsigned len = getSizeInBits(VT); 1767 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1768 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1769 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, 1770 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); 1771 } 1772 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); 1773 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1774 break; 1775 } 1776 case ISD::CTTZ: { 1777 // for now, we use: { return popcount(~x & (x - 1)); } 1778 // unless the target has ctlz but not ctpop, in which case we use: 1779 // { return 32 - nlz(~x & (x-1)); } 1780 // see also http://www.hackersdelight.org/HDcode/ntz.cc 1781 MVT::ValueType VT = Tmp1.getValueType(); 1782 Tmp2 = DAG.getConstant(~0ULL, VT); 1783 Tmp3 = DAG.getNode(ISD::AND, VT, 1784 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), 1785 DAG.getNode(ISD::SUB, VT, Tmp1, 1786 DAG.getConstant(1, VT))); 1787 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead 1788 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 1789 TLI.isOperationLegal(ISD::CTLZ, VT)) { 1790 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, 1791 DAG.getConstant(getSizeInBits(VT), VT), 1792 DAG.getNode(ISD::CTLZ, VT, Tmp3))); 1793 } else { 1794 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1795 } 1796 break; 1797 } 1798 default: 1799 assert(0 && "Cannot expand this yet!"); 1800 break; 1801 } 1802 break; 1803 } 1804 break; 1805 1806 // Unary operators 1807 case ISD::FABS: 1808 case ISD::FNEG: 1809 case ISD::FSQRT: 1810 case ISD::FSIN: 1811 case ISD::FCOS: 1812 Tmp1 = LegalizeOp(Node->getOperand(0)); 1813 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1814 case TargetLowering::Legal: 1815 if (Tmp1 != Node->getOperand(0)) 1816 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1817 break; 1818 case TargetLowering::Promote: 1819 case TargetLowering::Custom: 1820 assert(0 && "Cannot promote/custom handle this yet!"); 1821 case TargetLowering::Expand: 1822 switch(Node->getOpcode()) { 1823 case ISD::FNEG: { 1824 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 1825 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 1826 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0), 1827 Tmp2, Tmp1)); 1828 break; 1829 } 1830 case ISD::FABS: { 1831 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 1832 MVT::ValueType VT = Node->getValueType(0); 1833 Tmp2 = DAG.getConstantFP(0.0, VT); 1834 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 1835 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 1836 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 1837 Result = LegalizeOp(Result); 1838 break; 1839 } 1840 case ISD::FSQRT: 1841 case ISD::FSIN: 1842 case ISD::FCOS: { 1843 MVT::ValueType VT = Node->getValueType(0); 1844 const char *FnName = 0; 1845 switch(Node->getOpcode()) { 1846 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 1847 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 1848 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 1849 default: assert(0 && "Unreachable!"); 1850 } 1851 SDOperand Dummy; 1852 Result = ExpandLibCall(FnName, Node, Dummy); 1853 break; 1854 } 1855 default: 1856 assert(0 && "Unreachable!"); 1857 } 1858 break; 1859 } 1860 break; 1861 1862 // Conversion operators. The source and destination have different types. 1863 case ISD::SINT_TO_FP: 1864 case ISD::UINT_TO_FP: { 1865 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 1866 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1867 case Legal: 1868 switch (TLI.getOperationAction(Node->getOpcode(), 1869 Node->getOperand(0).getValueType())) { 1870 default: assert(0 && "Unknown operation action!"); 1871 case TargetLowering::Expand: 1872 Result = ExpandLegalINT_TO_FP(isSigned, 1873 LegalizeOp(Node->getOperand(0)), 1874 Node->getValueType(0)); 1875 AddLegalizedOperand(Op, Result); 1876 return Result; 1877 case TargetLowering::Promote: 1878 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 1879 Node->getValueType(0), 1880 isSigned); 1881 AddLegalizedOperand(Op, Result); 1882 return Result; 1883 case TargetLowering::Legal: 1884 break; 1885 } 1886 1887 Tmp1 = LegalizeOp(Node->getOperand(0)); 1888 if (Tmp1 != Node->getOperand(0)) 1889 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1890 break; 1891 case Expand: 1892 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 1893 Node->getValueType(0), Node->getOperand(0)); 1894 break; 1895 case Promote: 1896 if (isSigned) { 1897 Result = PromoteOp(Node->getOperand(0)); 1898 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1899 Result, DAG.getValueType(Node->getOperand(0).getValueType())); 1900 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 1901 } else { 1902 Result = PromoteOp(Node->getOperand(0)); 1903 Result = DAG.getZeroExtendInReg(Result, 1904 Node->getOperand(0).getValueType()); 1905 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 1906 } 1907 break; 1908 } 1909 break; 1910 } 1911 case ISD::TRUNCATE: 1912 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1913 case Legal: 1914 Tmp1 = LegalizeOp(Node->getOperand(0)); 1915 if (Tmp1 != Node->getOperand(0)) 1916 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1917 break; 1918 case Expand: 1919 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1920 1921 // Since the result is legal, we should just be able to truncate the low 1922 // part of the source. 1923 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 1924 break; 1925 case Promote: 1926 Result = PromoteOp(Node->getOperand(0)); 1927 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 1928 break; 1929 } 1930 break; 1931 1932 case ISD::FP_TO_SINT: 1933 case ISD::FP_TO_UINT: 1934 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1935 case Legal: 1936 Tmp1 = LegalizeOp(Node->getOperand(0)); 1937 1938 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 1939 default: assert(0 && "Unknown operation action!"); 1940 case TargetLowering::Expand: 1941 if (Node->getOpcode() == ISD::FP_TO_UINT) { 1942 SDOperand True, False; 1943 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1944 MVT::ValueType NVT = Node->getValueType(0); 1945 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 1946 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 1947 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 1948 Node->getOperand(0), Tmp2, ISD::SETLT); 1949 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 1950 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 1951 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 1952 Tmp2)); 1953 False = DAG.getNode(ISD::XOR, NVT, False, 1954 DAG.getConstant(1ULL << ShiftAmt, NVT)); 1955 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False)); 1956 return Result; 1957 } else { 1958 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 1959 } 1960 break; 1961 case TargetLowering::Promote: 1962 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 1963 Node->getOpcode() == ISD::FP_TO_SINT); 1964 AddLegalizedOperand(Op, Result); 1965 return Result; 1966 case TargetLowering::Custom: { 1967 SDOperand Tmp = 1968 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1969 Tmp = TLI.LowerOperation(Tmp, DAG); 1970 if (Tmp.Val) { 1971 AddLegalizedOperand(Op, Tmp); 1972 NeedsAnotherIteration = true; 1973 return Tmp; 1974 } else { 1975 // The target thinks this is legal afterall. 1976 break; 1977 } 1978 } 1979 case TargetLowering::Legal: 1980 break; 1981 } 1982 1983 if (Tmp1 != Node->getOperand(0)) 1984 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1985 break; 1986 case Expand: 1987 assert(0 && "Shouldn't need to expand other operators here!"); 1988 case Promote: 1989 Result = PromoteOp(Node->getOperand(0)); 1990 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 1991 break; 1992 } 1993 break; 1994 1995 case ISD::ANY_EXTEND: 1996 case ISD::ZERO_EXTEND: 1997 case ISD::SIGN_EXTEND: 1998 case ISD::FP_EXTEND: 1999 case ISD::FP_ROUND: 2000 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2001 case Legal: 2002 Tmp1 = LegalizeOp(Node->getOperand(0)); 2003 if (Tmp1 != Node->getOperand(0)) 2004 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2005 break; 2006 case Expand: 2007 assert(0 && "Shouldn't need to expand other operators here!"); 2008 2009 case Promote: 2010 switch (Node->getOpcode()) { 2011 case ISD::ANY_EXTEND: 2012 Result = PromoteOp(Node->getOperand(0)); 2013 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2014 break; 2015 case ISD::ZERO_EXTEND: 2016 Result = PromoteOp(Node->getOperand(0)); 2017 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2018 Result = DAG.getZeroExtendInReg(Result, 2019 Node->getOperand(0).getValueType()); 2020 break; 2021 case ISD::SIGN_EXTEND: 2022 Result = PromoteOp(Node->getOperand(0)); 2023 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2024 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2025 Result, 2026 DAG.getValueType(Node->getOperand(0).getValueType())); 2027 break; 2028 case ISD::FP_EXTEND: 2029 Result = PromoteOp(Node->getOperand(0)); 2030 if (Result.getValueType() != Op.getValueType()) 2031 // Dynamically dead while we have only 2 FP types. 2032 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2033 break; 2034 case ISD::FP_ROUND: 2035 Result = PromoteOp(Node->getOperand(0)); 2036 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2037 break; 2038 } 2039 } 2040 break; 2041 case ISD::FP_ROUND_INREG: 2042 case ISD::SIGN_EXTEND_INREG: { 2043 Tmp1 = LegalizeOp(Node->getOperand(0)); 2044 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2045 2046 // If this operation is not supported, convert it to a shl/shr or load/store 2047 // pair. 2048 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2049 default: assert(0 && "This action not supported for this op yet!"); 2050 case TargetLowering::Legal: 2051 if (Tmp1 != Node->getOperand(0)) 2052 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2053 DAG.getValueType(ExtraVT)); 2054 break; 2055 case TargetLowering::Expand: 2056 // If this is an integer extend and shifts are supported, do that. 2057 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2058 // NOTE: we could fall back on load/store here too for targets without 2059 // SAR. However, it is doubtful that any exist. 2060 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2061 MVT::getSizeInBits(ExtraVT); 2062 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2063 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2064 Node->getOperand(0), ShiftCst); 2065 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2066 Result, ShiftCst); 2067 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2068 // The only way we can lower this is to turn it into a STORETRUNC, 2069 // EXTLOAD pair, targetting a temporary location (a stack slot). 2070 2071 // NOTE: there is a choice here between constantly creating new stack 2072 // slots and always reusing the same one. We currently always create 2073 // new ones, as reuse may inhibit scheduling. 2074 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2075 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2076 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2077 MachineFunction &MF = DAG.getMachineFunction(); 2078 int SSFI = 2079 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2080 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2081 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2082 Node->getOperand(0), StackSlot, 2083 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2084 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2085 Result, StackSlot, DAG.getSrcValue(NULL), 2086 ExtraVT); 2087 } else { 2088 assert(0 && "Unknown op"); 2089 } 2090 Result = LegalizeOp(Result); 2091 break; 2092 } 2093 break; 2094 } 2095 } 2096 2097 // Note that LegalizeOp may be reentered even from single-use nodes, which 2098 // means that we always must cache transformed nodes. 2099 AddLegalizedOperand(Op, Result); 2100 return Result; 2101} 2102 2103/// PromoteOp - Given an operation that produces a value in an invalid type, 2104/// promote it to compute the value into a larger type. The produced value will 2105/// have the correct bits for the low portion of the register, but no guarantee 2106/// is made about the top bits: it may be zero, sign-extended, or garbage. 2107SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2108 MVT::ValueType VT = Op.getValueType(); 2109 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2110 assert(getTypeAction(VT) == Promote && 2111 "Caller should expand or legalize operands that are not promotable!"); 2112 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2113 "Cannot promote to smaller type!"); 2114 2115 SDOperand Tmp1, Tmp2, Tmp3; 2116 2117 SDOperand Result; 2118 SDNode *Node = Op.Val; 2119 2120 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2121 if (I != PromotedNodes.end()) return I->second; 2122 2123 // Promotion needs an optimization step to clean up after it, and is not 2124 // careful to avoid operations the target does not support. Make sure that 2125 // all generated operations are legalized in the next iteration. 2126 NeedsAnotherIteration = true; 2127 2128 switch (Node->getOpcode()) { 2129 case ISD::CopyFromReg: 2130 assert(0 && "CopyFromReg must be legal!"); 2131 default: 2132 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2133 assert(0 && "Do not know how to promote this operator!"); 2134 abort(); 2135 case ISD::UNDEF: 2136 Result = DAG.getNode(ISD::UNDEF, NVT); 2137 break; 2138 case ISD::Constant: 2139 if (VT != MVT::i1) 2140 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2141 else 2142 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2143 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2144 break; 2145 case ISD::ConstantFP: 2146 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2147 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2148 break; 2149 2150 case ISD::SETCC: 2151 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2152 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2153 Node->getOperand(1), Node->getOperand(2)); 2154 Result = LegalizeOp(Result); 2155 break; 2156 2157 case ISD::TRUNCATE: 2158 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2159 case Legal: 2160 Result = LegalizeOp(Node->getOperand(0)); 2161 assert(Result.getValueType() >= NVT && 2162 "This truncation doesn't make sense!"); 2163 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2164 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2165 break; 2166 case Promote: 2167 // The truncation is not required, because we don't guarantee anything 2168 // about high bits anyway. 2169 Result = PromoteOp(Node->getOperand(0)); 2170 break; 2171 case Expand: 2172 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2173 // Truncate the low part of the expanded value to the result type 2174 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2175 } 2176 break; 2177 case ISD::SIGN_EXTEND: 2178 case ISD::ZERO_EXTEND: 2179 case ISD::ANY_EXTEND: 2180 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2181 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2182 case Legal: 2183 // Input is legal? Just do extend all the way to the larger type. 2184 Result = LegalizeOp(Node->getOperand(0)); 2185 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2186 break; 2187 case Promote: 2188 // Promote the reg if it's smaller. 2189 Result = PromoteOp(Node->getOperand(0)); 2190 // The high bits are not guaranteed to be anything. Insert an extend. 2191 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2192 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2193 DAG.getValueType(Node->getOperand(0).getValueType())); 2194 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2195 Result = DAG.getZeroExtendInReg(Result, 2196 Node->getOperand(0).getValueType()); 2197 break; 2198 } 2199 break; 2200 2201 case ISD::FP_EXTEND: 2202 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2203 case ISD::FP_ROUND: 2204 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2205 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2206 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2207 case Legal: 2208 // Input is legal? Do an FP_ROUND_INREG. 2209 Result = LegalizeOp(Node->getOperand(0)); 2210 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2211 DAG.getValueType(VT)); 2212 break; 2213 } 2214 break; 2215 2216 case ISD::SINT_TO_FP: 2217 case ISD::UINT_TO_FP: 2218 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2219 case Legal: 2220 Result = LegalizeOp(Node->getOperand(0)); 2221 // No extra round required here. 2222 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2223 break; 2224 2225 case Promote: 2226 Result = PromoteOp(Node->getOperand(0)); 2227 if (Node->getOpcode() == ISD::SINT_TO_FP) 2228 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2229 Result, 2230 DAG.getValueType(Node->getOperand(0).getValueType())); 2231 else 2232 Result = DAG.getZeroExtendInReg(Result, 2233 Node->getOperand(0).getValueType()); 2234 // No extra round required here. 2235 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2236 break; 2237 case Expand: 2238 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2239 Node->getOperand(0)); 2240 // Round if we cannot tolerate excess precision. 2241 if (NoExcessFPPrecision) 2242 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2243 DAG.getValueType(VT)); 2244 break; 2245 } 2246 break; 2247 2248 case ISD::FP_TO_SINT: 2249 case ISD::FP_TO_UINT: 2250 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2251 case Legal: 2252 Tmp1 = LegalizeOp(Node->getOperand(0)); 2253 break; 2254 case Promote: 2255 // The input result is prerounded, so we don't have to do anything 2256 // special. 2257 Tmp1 = PromoteOp(Node->getOperand(0)); 2258 break; 2259 case Expand: 2260 assert(0 && "not implemented"); 2261 } 2262 // If we're promoting a UINT to a larger size, check to see if the new node 2263 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2264 // we can use that instead. This allows us to generate better code for 2265 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2266 // legal, such as PowerPC. 2267 if (Node->getOpcode() == ISD::FP_TO_UINT && 2268 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2269 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2270 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2271 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2272 } else { 2273 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2274 } 2275 break; 2276 2277 case ISD::FABS: 2278 case ISD::FNEG: 2279 Tmp1 = PromoteOp(Node->getOperand(0)); 2280 assert(Tmp1.getValueType() == NVT); 2281 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2282 // NOTE: we do not have to do any extra rounding here for 2283 // NoExcessFPPrecision, because we know the input will have the appropriate 2284 // precision, and these operations don't modify precision at all. 2285 break; 2286 2287 case ISD::FSQRT: 2288 case ISD::FSIN: 2289 case ISD::FCOS: 2290 Tmp1 = PromoteOp(Node->getOperand(0)); 2291 assert(Tmp1.getValueType() == NVT); 2292 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2293 if(NoExcessFPPrecision) 2294 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2295 DAG.getValueType(VT)); 2296 break; 2297 2298 case ISD::AND: 2299 case ISD::OR: 2300 case ISD::XOR: 2301 case ISD::ADD: 2302 case ISD::SUB: 2303 case ISD::MUL: 2304 // The input may have strange things in the top bits of the registers, but 2305 // these operations don't care. They may have weird bits going out, but 2306 // that too is okay if they are integer operations. 2307 Tmp1 = PromoteOp(Node->getOperand(0)); 2308 Tmp2 = PromoteOp(Node->getOperand(1)); 2309 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2310 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2311 break; 2312 case ISD::FADD: 2313 case ISD::FSUB: 2314 case ISD::FMUL: 2315 // The input may have strange things in the top bits of the registers, but 2316 // these operations don't care. 2317 Tmp1 = PromoteOp(Node->getOperand(0)); 2318 Tmp2 = PromoteOp(Node->getOperand(1)); 2319 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2320 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2321 2322 // Floating point operations will give excess precision that we may not be 2323 // able to tolerate. If we DO allow excess precision, just leave it, 2324 // otherwise excise it. 2325 // FIXME: Why would we need to round FP ops more than integer ones? 2326 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2327 if (NoExcessFPPrecision) 2328 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2329 DAG.getValueType(VT)); 2330 break; 2331 2332 case ISD::SDIV: 2333 case ISD::SREM: 2334 // These operators require that their input be sign extended. 2335 Tmp1 = PromoteOp(Node->getOperand(0)); 2336 Tmp2 = PromoteOp(Node->getOperand(1)); 2337 if (MVT::isInteger(NVT)) { 2338 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2339 DAG.getValueType(VT)); 2340 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2341 DAG.getValueType(VT)); 2342 } 2343 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2344 2345 // Perform FP_ROUND: this is probably overly pessimistic. 2346 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2347 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2348 DAG.getValueType(VT)); 2349 break; 2350 case ISD::FDIV: 2351 case ISD::FREM: 2352 // These operators require that their input be fp extended. 2353 Tmp1 = PromoteOp(Node->getOperand(0)); 2354 Tmp2 = PromoteOp(Node->getOperand(1)); 2355 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2356 2357 // Perform FP_ROUND: this is probably overly pessimistic. 2358 if (NoExcessFPPrecision) 2359 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2360 DAG.getValueType(VT)); 2361 break; 2362 2363 case ISD::UDIV: 2364 case ISD::UREM: 2365 // These operators require that their input be zero extended. 2366 Tmp1 = PromoteOp(Node->getOperand(0)); 2367 Tmp2 = PromoteOp(Node->getOperand(1)); 2368 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2369 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2370 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2371 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2372 break; 2373 2374 case ISD::SHL: 2375 Tmp1 = PromoteOp(Node->getOperand(0)); 2376 Tmp2 = LegalizeOp(Node->getOperand(1)); 2377 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 2378 break; 2379 case ISD::SRA: 2380 // The input value must be properly sign extended. 2381 Tmp1 = PromoteOp(Node->getOperand(0)); 2382 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2383 DAG.getValueType(VT)); 2384 Tmp2 = LegalizeOp(Node->getOperand(1)); 2385 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 2386 break; 2387 case ISD::SRL: 2388 // The input value must be properly zero extended. 2389 Tmp1 = PromoteOp(Node->getOperand(0)); 2390 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2391 Tmp2 = LegalizeOp(Node->getOperand(1)); 2392 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 2393 break; 2394 case ISD::LOAD: 2395 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2396 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2397 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2, 2398 Node->getOperand(2), VT); 2399 // Remember that we legalized the chain. 2400 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2401 break; 2402 case ISD::SEXTLOAD: 2403 case ISD::ZEXTLOAD: 2404 case ISD::EXTLOAD: 2405 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2406 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2407 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2, 2408 Node->getOperand(2), 2409 cast<VTSDNode>(Node->getOperand(3))->getVT()); 2410 // Remember that we legalized the chain. 2411 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2412 break; 2413 case ISD::SELECT: 2414 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2415 case Expand: assert(0 && "It's impossible to expand bools"); 2416 case Legal: 2417 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 2418 break; 2419 case Promote: 2420 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2421 break; 2422 } 2423 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 2424 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 2425 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 2426 break; 2427 case ISD::SELECT_CC: 2428 Tmp2 = PromoteOp(Node->getOperand(2)); // True 2429 Tmp3 = PromoteOp(Node->getOperand(3)); // False 2430 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 2431 Node->getOperand(1), Tmp2, Tmp3, 2432 Node->getOperand(4)); 2433 break; 2434 case ISD::TAILCALL: 2435 case ISD::CALL: { 2436 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2437 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 2438 2439 std::vector<SDOperand> Ops; 2440 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 2441 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2442 2443 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 2444 "Can only promote single result calls"); 2445 std::vector<MVT::ValueType> RetTyVTs; 2446 RetTyVTs.reserve(2); 2447 RetTyVTs.push_back(NVT); 2448 RetTyVTs.push_back(MVT::Other); 2449 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 2450 Node->getOpcode() == ISD::TAILCALL); 2451 Result = SDOperand(NC, 0); 2452 2453 // Insert the new chain mapping. 2454 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2455 break; 2456 } 2457 case ISD::CTPOP: 2458 case ISD::CTTZ: 2459 case ISD::CTLZ: 2460 Tmp1 = Node->getOperand(0); 2461 //Zero extend the argument 2462 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2463 // Perform the larger operation, then subtract if needed. 2464 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2465 switch(Node->getOpcode()) 2466 { 2467 case ISD::CTPOP: 2468 Result = Tmp1; 2469 break; 2470 case ISD::CTTZ: 2471 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2472 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2473 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 2474 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2475 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 2476 break; 2477 case ISD::CTLZ: 2478 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2479 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2480 DAG.getConstant(getSizeInBits(NVT) - 2481 getSizeInBits(VT), NVT)); 2482 break; 2483 } 2484 break; 2485 } 2486 2487 assert(Result.Val && "Didn't set a result!"); 2488 AddPromotedOperand(Op, Result); 2489 return Result; 2490} 2491 2492/// ExpandAddSub - Find a clever way to expand this add operation into 2493/// subcomponents. 2494void SelectionDAGLegalize:: 2495ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 2496 SDOperand &Lo, SDOperand &Hi) { 2497 // Expand the subcomponents. 2498 SDOperand LHSL, LHSH, RHSL, RHSH; 2499 ExpandOp(LHS, LHSL, LHSH); 2500 ExpandOp(RHS, RHSL, RHSH); 2501 2502 std::vector<SDOperand> Ops; 2503 Ops.push_back(LHSL); 2504 Ops.push_back(LHSH); 2505 Ops.push_back(RHSL); 2506 Ops.push_back(RHSH); 2507 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2508 Lo = DAG.getNode(NodeOp, VTs, Ops); 2509 Hi = Lo.getValue(1); 2510} 2511 2512void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 2513 SDOperand Op, SDOperand Amt, 2514 SDOperand &Lo, SDOperand &Hi) { 2515 // Expand the subcomponents. 2516 SDOperand LHSL, LHSH; 2517 ExpandOp(Op, LHSL, LHSH); 2518 2519 std::vector<SDOperand> Ops; 2520 Ops.push_back(LHSL); 2521 Ops.push_back(LHSH); 2522 Ops.push_back(Amt); 2523 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2524 Lo = DAG.getNode(NodeOp, VTs, Ops); 2525 Hi = Lo.getValue(1); 2526} 2527 2528 2529/// ExpandShift - Try to find a clever way to expand this shift operation out to 2530/// smaller elements. If we can't find a way that is more efficient than a 2531/// libcall on this target, return false. Otherwise, return true with the 2532/// low-parts expanded into Lo and Hi. 2533bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 2534 SDOperand &Lo, SDOperand &Hi) { 2535 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 2536 "This is not a shift!"); 2537 2538 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 2539 SDOperand ShAmt = LegalizeOp(Amt); 2540 MVT::ValueType ShTy = ShAmt.getValueType(); 2541 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 2542 unsigned NVTBits = MVT::getSizeInBits(NVT); 2543 2544 // Handle the case when Amt is an immediate. Other cases are currently broken 2545 // and are disabled. 2546 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 2547 unsigned Cst = CN->getValue(); 2548 // Expand the incoming operand to be shifted, so that we have its parts 2549 SDOperand InL, InH; 2550 ExpandOp(Op, InL, InH); 2551 switch(Opc) { 2552 case ISD::SHL: 2553 if (Cst > VTBits) { 2554 Lo = DAG.getConstant(0, NVT); 2555 Hi = DAG.getConstant(0, NVT); 2556 } else if (Cst > NVTBits) { 2557 Lo = DAG.getConstant(0, NVT); 2558 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 2559 } else if (Cst == NVTBits) { 2560 Lo = DAG.getConstant(0, NVT); 2561 Hi = InL; 2562 } else { 2563 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 2564 Hi = DAG.getNode(ISD::OR, NVT, 2565 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 2566 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 2567 } 2568 return true; 2569 case ISD::SRL: 2570 if (Cst > VTBits) { 2571 Lo = DAG.getConstant(0, NVT); 2572 Hi = DAG.getConstant(0, NVT); 2573 } else if (Cst > NVTBits) { 2574 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 2575 Hi = DAG.getConstant(0, NVT); 2576 } else if (Cst == NVTBits) { 2577 Lo = InH; 2578 Hi = DAG.getConstant(0, NVT); 2579 } else { 2580 Lo = DAG.getNode(ISD::OR, NVT, 2581 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2582 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2583 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 2584 } 2585 return true; 2586 case ISD::SRA: 2587 if (Cst > VTBits) { 2588 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 2589 DAG.getConstant(NVTBits-1, ShTy)); 2590 } else if (Cst > NVTBits) { 2591 Lo = DAG.getNode(ISD::SRA, NVT, InH, 2592 DAG.getConstant(Cst-NVTBits, ShTy)); 2593 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2594 DAG.getConstant(NVTBits-1, ShTy)); 2595 } else if (Cst == NVTBits) { 2596 Lo = InH; 2597 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2598 DAG.getConstant(NVTBits-1, ShTy)); 2599 } else { 2600 Lo = DAG.getNode(ISD::OR, NVT, 2601 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2602 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2603 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 2604 } 2605 return true; 2606 } 2607 } 2608 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 2609 // so disable it for now. Currently targets are handling this via SHL_PARTS 2610 // and friends. 2611 return false; 2612 2613 // If we have an efficient select operation (or if the selects will all fold 2614 // away), lower to some complex code, otherwise just emit the libcall. 2615 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt)) 2616 return false; 2617 2618 SDOperand InL, InH; 2619 ExpandOp(Op, InL, InH); 2620 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 2621 DAG.getConstant(NVTBits, ShTy), ShAmt); 2622 2623 // Compare the unmasked shift amount against 32. 2624 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt, 2625 DAG.getConstant(NVTBits, ShTy), ISD::SETGE); 2626 2627 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 2628 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 2629 DAG.getConstant(NVTBits-1, ShTy)); 2630 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 2631 DAG.getConstant(NVTBits-1, ShTy)); 2632 } 2633 2634 if (Opc == ISD::SHL) { 2635 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 2636 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 2637 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 2638 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 2639 2640 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2641 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 2642 } else { 2643 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 2644 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt, 2645 DAG.getConstant(32, ShTy), 2646 ISD::SETEQ), 2647 DAG.getConstant(0, NVT), 2648 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 2649 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 2650 HiLoPart, 2651 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 2652 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 2653 2654 SDOperand HiPart; 2655 if (Opc == ISD::SRA) 2656 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 2657 DAG.getConstant(NVTBits-1, ShTy)); 2658 else 2659 HiPart = DAG.getConstant(0, NVT); 2660 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2661 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 2662 } 2663 return true; 2664} 2665 2666/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 2667/// NodeDepth) node that is an CallSeqStart operation and occurs later than 2668/// Found. 2669static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) { 2670 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 2671 2672 // If we found an CALLSEQ_START, we already know this node occurs later 2673 // than the Found node. Just remember this node and return. 2674 if (Node->getOpcode() == ISD::CALLSEQ_START) { 2675 Found = Node; 2676 return; 2677 } 2678 2679 // Otherwise, scan the operands of Node to see if any of them is a call. 2680 assert(Node->getNumOperands() != 0 && 2681 "All leaves should have depth equal to the entry node!"); 2682 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 2683 FindLatestCallSeqStart(Node->getOperand(i).Val, Found); 2684 2685 // Tail recurse for the last iteration. 2686 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 2687 Found); 2688} 2689 2690 2691/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 2692/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 2693/// than Found. 2694static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 2695 std::set<SDNode*> &Visited) { 2696 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 2697 !Visited.insert(Node).second) return; 2698 2699 // If we found an CALLSEQ_END, we already know this node occurs earlier 2700 // than the Found node. Just remember this node and return. 2701 if (Node->getOpcode() == ISD::CALLSEQ_END) { 2702 Found = Node; 2703 return; 2704 } 2705 2706 // Otherwise, scan the operands of Node to see if any of them is a call. 2707 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 2708 if (UI == E) return; 2709 for (--E; UI != E; ++UI) 2710 FindEarliestCallSeqEnd(*UI, Found, Visited); 2711 2712 // Tail recurse for the last iteration. 2713 FindEarliestCallSeqEnd(*UI, Found, Visited); 2714} 2715 2716/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 2717/// find the CALLSEQ_END node that terminates the call sequence. 2718static SDNode *FindCallSeqEnd(SDNode *Node) { 2719 if (Node->getOpcode() == ISD::CALLSEQ_END) 2720 return Node; 2721 if (Node->use_empty()) 2722 return 0; // No CallSeqEnd 2723 2724 SDOperand TheChain(Node, Node->getNumValues()-1); 2725 if (TheChain.getValueType() != MVT::Other) 2726 TheChain = SDOperand(Node, 0); 2727 if (TheChain.getValueType() != MVT::Other) 2728 return 0; 2729 2730 for (SDNode::use_iterator UI = Node->use_begin(), 2731 E = Node->use_end(); UI != E; ++UI) { 2732 2733 // Make sure to only follow users of our token chain. 2734 SDNode *User = *UI; 2735 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 2736 if (User->getOperand(i) == TheChain) 2737 if (SDNode *Result = FindCallSeqEnd(User)) 2738 return Result; 2739 } 2740 return 0; 2741} 2742 2743/// FindCallSeqStart - Given a chained node that is part of a call sequence, 2744/// find the CALLSEQ_START node that initiates the call sequence. 2745static SDNode *FindCallSeqStart(SDNode *Node) { 2746 assert(Node && "Didn't find callseq_start for a call??"); 2747 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 2748 2749 assert(Node->getOperand(0).getValueType() == MVT::Other && 2750 "Node doesn't have a token chain argument!"); 2751 return FindCallSeqStart(Node->getOperand(0).Val); 2752} 2753 2754 2755/// FindInputOutputChains - If we are replacing an operation with a call we need 2756/// to find the call that occurs before and the call that occurs after it to 2757/// properly serialize the calls in the block. The returned operand is the 2758/// input chain value for the new call (e.g. the entry node or the previous 2759/// call), and OutChain is set to be the chain node to update to point to the 2760/// end of the call chain. 2761static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 2762 SDOperand Entry) { 2763 SDNode *LatestCallSeqStart = Entry.Val; 2764 SDNode *LatestCallSeqEnd = 0; 2765 FindLatestCallSeqStart(OpNode, LatestCallSeqStart); 2766 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 2767 2768 // It is possible that no ISD::CALLSEQ_START was found because there is no 2769 // previous call in the function. LatestCallStackDown may in that case be 2770 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 2771 // unless LatestCallStackDown is an CALLSEQ_START. 2772 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 2773 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 2774 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 2775 } else { 2776 LatestCallSeqEnd = Entry.Val; 2777 } 2778 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 2779 2780 // Finally, find the first call that this must come before, first we find the 2781 // CallSeqEnd that ends the call. 2782 OutChain = 0; 2783 std::set<SDNode*> Visited; 2784 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 2785 2786 // If we found one, translate from the adj up to the callseq_start. 2787 if (OutChain) 2788 OutChain = FindCallSeqStart(OutChain); 2789 2790 return SDOperand(LatestCallSeqEnd, 0); 2791} 2792 2793/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 2794void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 2795 SDNode *OutChain) { 2796 // Nothing to splice it into? 2797 if (OutChain == 0) return; 2798 2799 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 2800 //OutChain->dump(); 2801 2802 // Form a token factor node merging the old inval and the new inval. 2803 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 2804 OutChain->getOperand(0)); 2805 // Change the node to refer to the new token. 2806 OutChain->setAdjCallChain(InToken); 2807} 2808 2809 2810// ExpandLibCall - Expand a node into a call to a libcall. If the result value 2811// does not fit into a register, return the lo part and set the hi part to the 2812// by-reg argument. If it does fit into a single register, return the result 2813// and leave the Hi part unset. 2814SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 2815 SDOperand &Hi) { 2816 SDNode *OutChain; 2817 SDOperand InChain = FindInputOutputChains(Node, OutChain, 2818 DAG.getEntryNode()); 2819 if (InChain.Val == 0) 2820 InChain = DAG.getEntryNode(); 2821 2822 TargetLowering::ArgListTy Args; 2823 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2824 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 2825 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 2826 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 2827 } 2828 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 2829 2830 // Splice the libcall in wherever FindInputOutputChains tells us to. 2831 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 2832 std::pair<SDOperand,SDOperand> CallInfo = 2833 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 2834 Callee, Args, DAG); 2835 2836 SDOperand Result; 2837 switch (getTypeAction(CallInfo.first.getValueType())) { 2838 default: assert(0 && "Unknown thing"); 2839 case Legal: 2840 Result = CallInfo.first; 2841 break; 2842 case Promote: 2843 assert(0 && "Cannot promote this yet!"); 2844 case Expand: 2845 ExpandOp(CallInfo.first, Result, Hi); 2846 CallInfo.second = LegalizeOp(CallInfo.second); 2847 break; 2848 } 2849 2850 SpliceCallInto(CallInfo.second, OutChain); 2851 NeedsAnotherIteration = true; 2852 return Result; 2853} 2854 2855 2856/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 2857/// destination type is legal. 2858SDOperand SelectionDAGLegalize:: 2859ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 2860 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 2861 assert(getTypeAction(Source.getValueType()) == Expand && 2862 "This is not an expansion!"); 2863 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 2864 2865 if (!isSigned) { 2866 assert(Source.getValueType() == MVT::i64 && 2867 "This only works for 64-bit -> FP"); 2868 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 2869 // incoming integer is set. To handle this, we dynamically test to see if 2870 // it is set, and, if so, add a fudge factor. 2871 SDOperand Lo, Hi; 2872 ExpandOp(Source, Lo, Hi); 2873 2874 // If this is unsigned, and not supported, first perform the conversion to 2875 // signed, then adjust the result if the sign bit is set. 2876 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 2877 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 2878 2879 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 2880 DAG.getConstant(0, Hi.getValueType()), 2881 ISD::SETLT); 2882 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 2883 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 2884 SignSet, Four, Zero); 2885 uint64_t FF = 0x5f800000ULL; 2886 if (TLI.isLittleEndian()) FF <<= 32; 2887 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 2888 2889 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2890 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 2891 SDOperand FudgeInReg; 2892 if (DestTy == MVT::f32) 2893 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 2894 DAG.getSrcValue(NULL)); 2895 else { 2896 assert(DestTy == MVT::f64 && "Unexpected conversion"); 2897 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 2898 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 2899 } 2900 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 2901 } 2902 2903 // Check to see if the target has a custom way to lower this. If so, use it. 2904 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 2905 default: assert(0 && "This action not implemented for this operation!"); 2906 case TargetLowering::Legal: 2907 case TargetLowering::Expand: 2908 break; // This case is handled below. 2909 case TargetLowering::Custom: { 2910 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 2911 Source), DAG); 2912 if (NV.Val) 2913 return LegalizeOp(NV); 2914 break; // The target decided this was legal after all 2915 } 2916 } 2917 2918 // Expand the source, then glue it back together for the call. We must expand 2919 // the source in case it is shared (this pass of legalize must traverse it). 2920 SDOperand SrcLo, SrcHi; 2921 ExpandOp(Source, SrcLo, SrcHi); 2922 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 2923 2924 SDNode *OutChain = 0; 2925 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 2926 DAG.getEntryNode()); 2927 const char *FnName = 0; 2928 if (DestTy == MVT::f32) 2929 FnName = "__floatdisf"; 2930 else { 2931 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 2932 FnName = "__floatdidf"; 2933 } 2934 2935 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 2936 2937 TargetLowering::ArgListTy Args; 2938 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 2939 2940 Args.push_back(std::make_pair(Source, ArgTy)); 2941 2942 // We don't care about token chains for libcalls. We just use the entry 2943 // node as our input and ignore the output chain. This allows us to place 2944 // calls wherever we need them to satisfy data dependences. 2945 const Type *RetTy = MVT::getTypeForValueType(DestTy); 2946 2947 std::pair<SDOperand,SDOperand> CallResult = 2948 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 2949 Callee, Args, DAG); 2950 2951 SpliceCallInto(CallResult.second, OutChain); 2952 return CallResult.first; 2953} 2954 2955 2956 2957/// ExpandOp - Expand the specified SDOperand into its two component pieces 2958/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 2959/// LegalizeNodes map is filled in for any results that are not expanded, the 2960/// ExpandedNodes map is filled in for any results that are expanded, and the 2961/// Lo/Hi values are returned. 2962void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 2963 MVT::ValueType VT = Op.getValueType(); 2964 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2965 SDNode *Node = Op.Val; 2966 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 2967 assert(MVT::isInteger(VT) && "Cannot expand FP values!"); 2968 assert(MVT::isInteger(NVT) && NVT < VT && 2969 "Cannot expand to FP value or to larger int value!"); 2970 2971 // See if we already expanded it. 2972 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 2973 = ExpandedNodes.find(Op); 2974 if (I != ExpandedNodes.end()) { 2975 Lo = I->second.first; 2976 Hi = I->second.second; 2977 return; 2978 } 2979 2980 // Expanding to multiple registers needs to perform an optimization step, and 2981 // is not careful to avoid operations the target does not support. Make sure 2982 // that all generated operations are legalized in the next iteration. 2983 NeedsAnotherIteration = true; 2984 2985 switch (Node->getOpcode()) { 2986 case ISD::CopyFromReg: 2987 assert(0 && "CopyFromReg must be legal!"); 2988 default: 2989 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2990 assert(0 && "Do not know how to expand this operator!"); 2991 abort(); 2992 case ISD::UNDEF: 2993 Lo = DAG.getNode(ISD::UNDEF, NVT); 2994 Hi = DAG.getNode(ISD::UNDEF, NVT); 2995 break; 2996 case ISD::Constant: { 2997 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 2998 Lo = DAG.getConstant(Cst, NVT); 2999 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3000 break; 3001 } 3002 3003 case ISD::BUILD_PAIR: 3004 // Legalize both operands. FIXME: in the future we should handle the case 3005 // where the two elements are not legal. 3006 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 3007 Lo = LegalizeOp(Node->getOperand(0)); 3008 Hi = LegalizeOp(Node->getOperand(1)); 3009 break; 3010 3011 case ISD::CTPOP: 3012 ExpandOp(Node->getOperand(0), Lo, Hi); 3013 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3014 DAG.getNode(ISD::CTPOP, NVT, Lo), 3015 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3016 Hi = DAG.getConstant(0, NVT); 3017 break; 3018 3019 case ISD::CTLZ: { 3020 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3021 ExpandOp(Node->getOperand(0), Lo, Hi); 3022 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3023 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3024 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3025 ISD::SETNE); 3026 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3027 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3028 3029 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3030 Hi = DAG.getConstant(0, NVT); 3031 break; 3032 } 3033 3034 case ISD::CTTZ: { 3035 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3036 ExpandOp(Node->getOperand(0), Lo, Hi); 3037 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3038 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3039 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3040 ISD::SETNE); 3041 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3042 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3043 3044 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3045 Hi = DAG.getConstant(0, NVT); 3046 break; 3047 } 3048 3049 case ISD::LOAD: { 3050 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3051 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3052 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3053 3054 // Increment the pointer to the other half. 3055 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3056 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3057 getIntPtrConstant(IncrementSize)); 3058 //Is this safe? declaring that the two parts of the split load 3059 //are from the same instruction? 3060 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3061 3062 // Build a factor node to remember that this load is independent of the 3063 // other one. 3064 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3065 Hi.getValue(1)); 3066 3067 // Remember that we legalized the chain. 3068 AddLegalizedOperand(Op.getValue(1), TF); 3069 if (!TLI.isLittleEndian()) 3070 std::swap(Lo, Hi); 3071 break; 3072 } 3073 case ISD::TAILCALL: 3074 case ISD::CALL: { 3075 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3076 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 3077 3078 bool Changed = false; 3079 std::vector<SDOperand> Ops; 3080 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 3081 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3082 Changed |= Ops.back() != Node->getOperand(i); 3083 } 3084 3085 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 3086 "Can only expand a call once so far, not i64 -> i16!"); 3087 3088 std::vector<MVT::ValueType> RetTyVTs; 3089 RetTyVTs.reserve(3); 3090 RetTyVTs.push_back(NVT); 3091 RetTyVTs.push_back(NVT); 3092 RetTyVTs.push_back(MVT::Other); 3093 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops, 3094 Node->getOpcode() == ISD::TAILCALL); 3095 Lo = SDOperand(NC, 0); 3096 Hi = SDOperand(NC, 1); 3097 3098 // Insert the new chain mapping. 3099 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 3100 break; 3101 } 3102 case ISD::AND: 3103 case ISD::OR: 3104 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 3105 SDOperand LL, LH, RL, RH; 3106 ExpandOp(Node->getOperand(0), LL, LH); 3107 ExpandOp(Node->getOperand(1), RL, RH); 3108 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 3109 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 3110 break; 3111 } 3112 case ISD::SELECT: { 3113 SDOperand C, LL, LH, RL, RH; 3114 3115 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3116 case Expand: assert(0 && "It's impossible to expand bools"); 3117 case Legal: 3118 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 3119 break; 3120 case Promote: 3121 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 3122 break; 3123 } 3124 ExpandOp(Node->getOperand(1), LL, LH); 3125 ExpandOp(Node->getOperand(2), RL, RH); 3126 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 3127 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 3128 break; 3129 } 3130 case ISD::SELECT_CC: { 3131 SDOperand TL, TH, FL, FH; 3132 ExpandOp(Node->getOperand(2), TL, TH); 3133 ExpandOp(Node->getOperand(3), FL, FH); 3134 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3135 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3136 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3137 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3138 Lo = LegalizeOp(Lo); 3139 Hi = LegalizeOp(Hi); 3140 break; 3141 } 3142 case ISD::SEXTLOAD: { 3143 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3144 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3145 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3146 3147 if (EVT == NVT) 3148 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3149 else 3150 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3151 EVT); 3152 3153 // Remember that we legalized the chain. 3154 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3155 3156 // The high part is obtained by SRA'ing all but one of the bits of the lo 3157 // part. 3158 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3159 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3160 TLI.getShiftAmountTy())); 3161 Lo = LegalizeOp(Lo); 3162 Hi = LegalizeOp(Hi); 3163 break; 3164 } 3165 case ISD::ZEXTLOAD: { 3166 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3167 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3168 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3169 3170 if (EVT == NVT) 3171 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3172 else 3173 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3174 EVT); 3175 3176 // Remember that we legalized the chain. 3177 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3178 3179 // The high part is just a zero. 3180 Hi = LegalizeOp(DAG.getConstant(0, NVT)); 3181 Lo = LegalizeOp(Lo); 3182 break; 3183 } 3184 case ISD::EXTLOAD: { 3185 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3186 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3187 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3188 3189 if (EVT == NVT) 3190 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3191 else 3192 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3193 EVT); 3194 3195 // Remember that we legalized the chain. 3196 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3197 3198 // The high part is undefined. 3199 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT)); 3200 Lo = LegalizeOp(Lo); 3201 break; 3202 } 3203 case ISD::ANY_EXTEND: { 3204 SDOperand In; 3205 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3206 case Expand: assert(0 && "expand-expand not implemented yet!"); 3207 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3208 case Promote: 3209 In = PromoteOp(Node->getOperand(0)); 3210 break; 3211 } 3212 3213 // The low part is any extension of the input (which degenerates to a copy). 3214 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In); 3215 // The high part is undefined. 3216 Hi = DAG.getNode(ISD::UNDEF, NVT); 3217 break; 3218 } 3219 case ISD::SIGN_EXTEND: { 3220 SDOperand In; 3221 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3222 case Expand: assert(0 && "expand-expand not implemented yet!"); 3223 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3224 case Promote: 3225 In = PromoteOp(Node->getOperand(0)); 3226 // Emit the appropriate sign_extend_inreg to get the value we want. 3227 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 3228 DAG.getValueType(Node->getOperand(0).getValueType())); 3229 break; 3230 } 3231 3232 // The low part is just a sign extension of the input (which degenerates to 3233 // a copy). 3234 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 3235 3236 // The high part is obtained by SRA'ing all but one of the bits of the lo 3237 // part. 3238 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3239 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3240 TLI.getShiftAmountTy())); 3241 break; 3242 } 3243 case ISD::ZERO_EXTEND: { 3244 SDOperand In; 3245 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3246 case Expand: assert(0 && "expand-expand not implemented yet!"); 3247 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3248 case Promote: 3249 In = PromoteOp(Node->getOperand(0)); 3250 // Emit the appropriate zero_extend_inreg to get the value we want. 3251 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 3252 break; 3253 } 3254 3255 // The low part is just a zero extension of the input (which degenerates to 3256 // a copy). 3257 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 3258 3259 // The high part is just a zero. 3260 Hi = DAG.getConstant(0, NVT); 3261 break; 3262 } 3263 // These operators cannot be expanded directly, emit them as calls to 3264 // library functions. 3265 case ISD::FP_TO_SINT: 3266 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 3267 SDOperand Op; 3268 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3269 case Expand: assert(0 && "cannot expand FP!"); 3270 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3271 case Promote: Op = PromoteOp(Node->getOperand(0)); break; 3272 } 3273 3274 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 3275 3276 // Now that the custom expander is done, expand the result, which is still 3277 // VT. 3278 if (Op.Val) { 3279 ExpandOp(Op, Lo, Hi); 3280 break; 3281 } 3282 } 3283 3284 if (Node->getOperand(0).getValueType() == MVT::f32) 3285 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 3286 else 3287 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 3288 break; 3289 3290 case ISD::FP_TO_UINT: 3291 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 3292 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, 3293 LegalizeOp(Node->getOperand(0))); 3294 // Now that the custom expander is done, expand the result, which is still 3295 // VT. 3296 Op = TLI.LowerOperation(Op, DAG); 3297 if (Op.Val) { 3298 ExpandOp(Op, Lo, Hi); 3299 break; 3300 } 3301 } 3302 3303 if (Node->getOperand(0).getValueType() == MVT::f32) 3304 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 3305 else 3306 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 3307 break; 3308 3309 case ISD::SHL: 3310 // If the target wants custom lowering, do so. 3311 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 3312 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), 3313 LegalizeOp(Node->getOperand(1))); 3314 Op = TLI.LowerOperation(Op, DAG); 3315 if (Op.Val) { 3316 // Now that the custom expander is done, expand the result, which is 3317 // still VT. 3318 ExpandOp(Op, Lo, Hi); 3319 break; 3320 } 3321 } 3322 3323 // If we can emit an efficient shift operation, do so now. 3324 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3325 break; 3326 3327 // If this target supports SHL_PARTS, use it. 3328 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) { 3329 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 3330 Lo, Hi); 3331 break; 3332 } 3333 3334 // Otherwise, emit a libcall. 3335 Lo = ExpandLibCall("__ashldi3", Node, Hi); 3336 break; 3337 3338 case ISD::SRA: 3339 // If the target wants custom lowering, do so. 3340 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 3341 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), 3342 LegalizeOp(Node->getOperand(1))); 3343 Op = TLI.LowerOperation(Op, DAG); 3344 if (Op.Val) { 3345 // Now that the custom expander is done, expand the result, which is 3346 // still VT. 3347 ExpandOp(Op, Lo, Hi); 3348 break; 3349 } 3350 } 3351 3352 // If we can emit an efficient shift operation, do so now. 3353 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3354 break; 3355 3356 // If this target supports SRA_PARTS, use it. 3357 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) { 3358 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 3359 Lo, Hi); 3360 break; 3361 } 3362 3363 // Otherwise, emit a libcall. 3364 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 3365 break; 3366 case ISD::SRL: 3367 // If the target wants custom lowering, do so. 3368 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 3369 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), 3370 LegalizeOp(Node->getOperand(1))); 3371 Op = TLI.LowerOperation(Op, DAG); 3372 if (Op.Val) { 3373 // Now that the custom expander is done, expand the result, which is 3374 // still VT. 3375 ExpandOp(Op, Lo, Hi); 3376 break; 3377 } 3378 } 3379 3380 // If we can emit an efficient shift operation, do so now. 3381 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3382 break; 3383 3384 // If this target supports SRL_PARTS, use it. 3385 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) { 3386 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 3387 Lo, Hi); 3388 break; 3389 } 3390 3391 // Otherwise, emit a libcall. 3392 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 3393 break; 3394 3395 case ISD::ADD: 3396 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 3397 Lo, Hi); 3398 break; 3399 case ISD::SUB: 3400 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 3401 Lo, Hi); 3402 break; 3403 case ISD::MUL: { 3404 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 3405 SDOperand LL, LH, RL, RH; 3406 ExpandOp(Node->getOperand(0), LL, LH); 3407 ExpandOp(Node->getOperand(1), RL, RH); 3408 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 3409 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 3410 // extended the sign bit of the low half through the upper half, and if so 3411 // emit a MULHS instead of the alternate sequence that is valid for any 3412 // i64 x i64 multiply. 3413 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 3414 // is RH an extension of the sign bit of RL? 3415 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 3416 RH.getOperand(1).getOpcode() == ISD::Constant && 3417 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 3418 // is LH an extension of the sign bit of LL? 3419 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 3420 LH.getOperand(1).getOpcode() == ISD::Constant && 3421 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 3422 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 3423 } else { 3424 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 3425 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 3426 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 3427 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 3428 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 3429 } 3430 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 3431 } else { 3432 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 3433 } 3434 break; 3435 } 3436 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 3437 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 3438 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 3439 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 3440 } 3441 3442 // Remember in a map if the values will be reused later. 3443 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 3444 std::make_pair(Lo, Hi))).second; 3445 assert(isNew && "Value already expanded?!?"); 3446} 3447 3448 3449// SelectionDAG::Legalize - This is the entry point for the file. 3450// 3451void SelectionDAG::Legalize() { 3452 /// run - This is the main entry point to this class. 3453 /// 3454 SelectionDAGLegalize(*this).Run(); 3455} 3456 3457