LegalizeDAG.cpp revision bb5da918545efb54857a09c983a5a7f22a7e04d4
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/DwarfWriter.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/CodeGen/PseudoSourceValue.h" 22#include "llvm/Target/TargetFrameInfo.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetData.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Target/TargetSubtarget.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/DerivedTypes.h" 31#include "llvm/GlobalVariable.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Compiler.h" 34#include "llvm/Support/MathExtras.h" 35#include "llvm/ADT/DenseMap.h" 36#include "llvm/ADT/SmallVector.h" 37#include "llvm/ADT/SmallPtrSet.h" 38#include <map> 39using namespace llvm; 40 41//===----------------------------------------------------------------------===// 42/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 43/// hacks on it until the target machine can handle it. This involves 44/// eliminating value sizes the machine cannot handle (promoting small sizes to 45/// large sizes or splitting up large values into small values) as well as 46/// eliminating operations the machine cannot handle. 47/// 48/// This code also does a small amount of optimization and recognition of idioms 49/// as part of its processing. For example, if a target does not support a 50/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 51/// will attempt merge setcc and brc instructions into brcc's. 52/// 53namespace { 54class VISIBILITY_HIDDEN SelectionDAGLegalize { 55 TargetLowering &TLI; 56 SelectionDAG &DAG; 57 bool TypesNeedLegalizing; 58 59 // Libcall insertion helpers. 60 61 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 62 /// legalized. We use this to ensure that calls are properly serialized 63 /// against each other, including inserted libcalls. 64 SDValue LastCALLSEQ_END; 65 66 /// IsLegalizingCall - This member is used *only* for purposes of providing 67 /// helpful assertions that a libcall isn't created while another call is 68 /// being legalized (which could lead to non-serialized call sequences). 69 bool IsLegalizingCall; 70 71 enum LegalizeAction { 72 Legal, // The target natively supports this operation. 73 Promote, // This operation should be executed in a larger type. 74 Expand // Try to expand this to other ops, otherwise use a libcall. 75 }; 76 77 /// ValueTypeActions - This is a bitvector that contains two bits for each 78 /// value type, where the two bits correspond to the LegalizeAction enum. 79 /// This can be queried with "getTypeAction(VT)". 80 TargetLowering::ValueTypeActionImpl ValueTypeActions; 81 82 /// LegalizedNodes - For nodes that are of legal width, and that have more 83 /// than one use, this map indicates what regularized operand to use. This 84 /// allows us to avoid legalizing the same thing more than once. 85 DenseMap<SDValue, SDValue> LegalizedNodes; 86 87 /// PromotedNodes - For nodes that are below legal width, and that have more 88 /// than one use, this map indicates what promoted value to use. This allows 89 /// us to avoid promoting the same thing more than once. 90 DenseMap<SDValue, SDValue> PromotedNodes; 91 92 /// ExpandedNodes - For nodes that need to be expanded this map indicates 93 /// which operands are the expanded version of the input. This allows 94 /// us to avoid expanding the same node more than once. 95 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes; 96 97 /// SplitNodes - For vector nodes that need to be split, this map indicates 98 /// which operands are the split version of the input. This allows us 99 /// to avoid splitting the same node more than once. 100 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes; 101 102 /// ScalarizedNodes - For nodes that need to be converted from vector types to 103 /// scalar types, this contains the mapping of ones we have already 104 /// processed to the result. 105 std::map<SDValue, SDValue> ScalarizedNodes; 106 107 /// WidenNodes - For nodes that need to be widened from one vector type to 108 /// another, this contains the mapping of those that we have already widen. 109 /// This allows us to avoid widening more than once. 110 std::map<SDValue, SDValue> WidenNodes; 111 112 void AddLegalizedOperand(SDValue From, SDValue To) { 113 LegalizedNodes.insert(std::make_pair(From, To)); 114 // If someone requests legalization of the new node, return itself. 115 if (From != To) 116 LegalizedNodes.insert(std::make_pair(To, To)); 117 } 118 void AddPromotedOperand(SDValue From, SDValue To) { 119 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 120 assert(isNew && "Got into the map somehow?"); 121 isNew = isNew; 122 // If someone requests legalization of the new node, return itself. 123 LegalizedNodes.insert(std::make_pair(To, To)); 124 } 125 void AddWidenedOperand(SDValue From, SDValue To) { 126 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second; 127 assert(isNew && "Got into the map somehow?"); 128 isNew = isNew; 129 // If someone requests legalization of the new node, return itself. 130 LegalizedNodes.insert(std::make_pair(To, To)); 131 } 132 133public: 134 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing); 135 136 /// getTypeAction - Return how we should legalize values of this type, either 137 /// it is already legal or we need to expand it into multiple registers of 138 /// smaller integer type, or we need to promote it to a larger type. 139 LegalizeAction getTypeAction(MVT VT) const { 140 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 141 } 142 143 /// isTypeLegal - Return true if this type is legal on this target. 144 /// 145 bool isTypeLegal(MVT VT) const { 146 return getTypeAction(VT) == Legal; 147 } 148 149 void LegalizeDAG(); 150 151private: 152 /// HandleOp - Legalize, Promote, or Expand the specified operand as 153 /// appropriate for its type. 154 void HandleOp(SDValue Op); 155 156 /// LegalizeOp - We know that the specified value has a legal type. 157 /// Recursively ensure that the operands have legal types, then return the 158 /// result. 159 SDValue LegalizeOp(SDValue O); 160 161 /// UnrollVectorOp - We know that the given vector has a legal type, however 162 /// the operation it performs is not legal and is an operation that we have 163 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 164 /// operating on each element individually. 165 SDValue UnrollVectorOp(SDValue O); 166 167 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 168 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 169 /// is necessary to spill the vector being inserted into to memory, perform 170 /// the insert there, and then read the result back. 171 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 172 SDValue Idx, DebugLoc dl); 173 174 /// PromoteOp - Given an operation that produces a value in an invalid type, 175 /// promote it to compute the value into a larger type. The produced value 176 /// will have the correct bits for the low portion of the register, but no 177 /// guarantee is made about the top bits: it may be zero, sign-extended, or 178 /// garbage. 179 SDValue PromoteOp(SDValue O); 180 181 /// ExpandOp - Expand the specified SDValue into its two component pieces 182 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 183 /// the LegalizedNodes map is filled in for any results that are not expanded, 184 /// the ExpandedNodes map is filled in for any results that are expanded, and 185 /// the Lo/Hi values are returned. This applies to integer types and Vector 186 /// types. 187 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi); 188 189 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT 190 /// (e.g., v3i32 to v4i32). The produced value will have the correct value 191 /// for the existing elements but no guarantee is made about the new elements 192 /// at the end of the vector: it may be zero, ones, or garbage. This is useful 193 /// when we have an instruction operating on an illegal vector type and we 194 /// want to widen it to do the computation on a legal wider vector type. 195 SDValue WidenVectorOp(SDValue Op, MVT WidenVT); 196 197 /// SplitVectorOp - Given an operand of vector type, break it down into 198 /// two smaller values. 199 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi); 200 201 /// ScalarizeVectorOp - Given an operand of single-element vector type 202 /// (e.g. v1f32), convert it into the equivalent operation that returns a 203 /// scalar (e.g. f32) value. 204 SDValue ScalarizeVectorOp(SDValue O); 205 206 /// Useful 16 element vector type that is used to pass operands for widening. 207 typedef SmallVector<SDValue, 16> SDValueVector; 208 209 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if 210 /// the LdChain contains a single load and false if it contains a token 211 /// factor for multiple loads. It takes 212 /// Result: location to return the result 213 /// LdChain: location to return the load chain 214 /// Op: load operation to widen 215 /// NVT: widen vector result type we want for the load 216 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain, 217 SDValue Op, MVT NVT); 218 219 /// Helper genWidenVectorLoads - Helper function to generate a set of 220 /// loads to load a vector with a resulting wider type. It takes 221 /// LdChain: list of chains for the load we have generated 222 /// Chain: incoming chain for the ld vector 223 /// BasePtr: base pointer to load from 224 /// SV: memory disambiguation source value 225 /// SVOffset: memory disambiugation offset 226 /// Alignment: alignment of the memory 227 /// isVolatile: volatile load 228 /// LdWidth: width of memory that we want to load 229 /// ResType: the wider result result type for the resulting loaded vector 230 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain, 231 SDValue BasePtr, const Value *SV, 232 int SVOffset, unsigned Alignment, 233 bool isVolatile, unsigned LdWidth, 234 MVT ResType); 235 236 /// StoreWidenVectorOp - Stores a widen vector into non widen memory 237 /// location. It takes 238 /// ST: store node that we want to replace 239 /// Chain: incoming store chain 240 /// BasePtr: base address of where we want to store into 241 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain, 242 SDValue BasePtr); 243 244 /// Helper genWidenVectorStores - Helper function to generate a set of 245 /// stores to store a widen vector into non widen memory 246 // It takes 247 // StChain: list of chains for the stores we have generated 248 // Chain: incoming chain for the ld vector 249 // BasePtr: base pointer to load from 250 // SV: memory disambiguation source value 251 // SVOffset: memory disambiugation offset 252 // Alignment: alignment of the memory 253 // isVolatile: volatile lod 254 // ValOp: value to store 255 // StWidth: width of memory that we want to store 256 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain, 257 SDValue BasePtr, const Value *SV, 258 int SVOffset, unsigned Alignment, 259 bool isVolatile, SDValue ValOp, 260 unsigned StWidth); 261 262 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the 263 /// specified mask and type. Targets can specify exactly which masks they 264 /// support and the code generator is tasked with not creating illegal masks. 265 /// 266 /// Note that this will also return true for shuffles that are promoted to a 267 /// different type. 268 /// 269 /// If this is a legal shuffle, this method returns the (possibly promoted) 270 /// build_vector Mask. If it's not a legal shuffle, it returns null. 271 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const; 272 273 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 274 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 275 276 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC, 277 DebugLoc dl); 278 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 279 DebugLoc dl); 280 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 281 DebugLoc dl) { 282 LegalizeSetCCOperands(LHS, RHS, CC, dl); 283 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl); 284 } 285 286 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 287 SDValue &Hi); 288 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl); 289 290 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT); 291 SDValue ExpandBUILD_VECTOR(SDNode *Node); 292 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 293 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, 294 SDValue Op, DebugLoc dl); 295 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT, 296 DebugLoc dl); 297 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned, 298 DebugLoc dl); 299 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned, 300 DebugLoc dl); 301 302 SDValue ExpandBSWAP(SDValue Op); 303 SDValue ExpandBitCount(unsigned Opc, SDValue Op); 304 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt, 305 SDValue &Lo, SDValue &Hi); 306 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt, 307 SDValue &Lo, SDValue &Hi); 308 309 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op); 310 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op); 311}; 312} 313 314/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 315/// specified mask and type. Targets can specify exactly which masks they 316/// support and the code generator is tasked with not creating illegal masks. 317/// 318/// Note that this will also return true for shuffles that are promoted to a 319/// different type. 320SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const { 321 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 322 default: return 0; 323 case TargetLowering::Legal: 324 case TargetLowering::Custom: 325 break; 326 case TargetLowering::Promote: { 327 // If this is promoted to a different type, convert the shuffle mask and 328 // ask if it is legal in the promoted type! 329 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 330 MVT EltVT = NVT.getVectorElementType(); 331 332 // If we changed # elements, change the shuffle mask. 333 unsigned NumEltsGrowth = 334 NVT.getVectorNumElements() / VT.getVectorNumElements(); 335 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 336 if (NumEltsGrowth > 1) { 337 // Renumber the elements. 338 SmallVector<SDValue, 8> Ops; 339 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 340 SDValue InOp = Mask.getOperand(i); 341 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 342 if (InOp.getOpcode() == ISD::UNDEF) 343 Ops.push_back(DAG.getNode(ISD::UNDEF, 344 InOp.getNode()->getDebugLoc(), EltVT)); 345 else { 346 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue(); 347 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT)); 348 } 349 } 350 } 351 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getNode()->getDebugLoc(), 352 NVT, &Ops[0], Ops.size()); 353 } 354 VT = NVT; 355 break; 356 } 357 } 358 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0; 359} 360 361SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, bool types) 362 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types), 363 ValueTypeActions(TLI.getValueTypeActions()) { 364 assert(MVT::LAST_VALUETYPE <= 32 && 365 "Too many value types for ValueTypeActions to hold!"); 366} 367 368void SelectionDAGLegalize::LegalizeDAG() { 369 LastCALLSEQ_END = DAG.getEntryNode(); 370 IsLegalizingCall = false; 371 372 // The legalize process is inherently a bottom-up recursive process (users 373 // legalize their uses before themselves). Given infinite stack space, we 374 // could just start legalizing on the root and traverse the whole graph. In 375 // practice however, this causes us to run out of stack space on large basic 376 // blocks. To avoid this problem, compute an ordering of the nodes where each 377 // node is only legalized after all of its operands are legalized. 378 DAG.AssignTopologicalOrder(); 379 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 380 E = prior(DAG.allnodes_end()); I != next(E); ++I) 381 HandleOp(SDValue(I, 0)); 382 383 // Finally, it's possible the root changed. Get the new root. 384 SDValue OldRoot = DAG.getRoot(); 385 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 386 DAG.setRoot(LegalizedNodes[OldRoot]); 387 388 ExpandedNodes.clear(); 389 LegalizedNodes.clear(); 390 PromotedNodes.clear(); 391 SplitNodes.clear(); 392 ScalarizedNodes.clear(); 393 WidenNodes.clear(); 394 395 // Remove dead nodes now. 396 DAG.RemoveDeadNodes(); 397} 398 399 400/// FindCallEndFromCallStart - Given a chained node that is part of a call 401/// sequence, find the CALLSEQ_END node that terminates the call sequence. 402static SDNode *FindCallEndFromCallStart(SDNode *Node) { 403 if (Node->getOpcode() == ISD::CALLSEQ_END) 404 return Node; 405 if (Node->use_empty()) 406 return 0; // No CallSeqEnd 407 408 // The chain is usually at the end. 409 SDValue TheChain(Node, Node->getNumValues()-1); 410 if (TheChain.getValueType() != MVT::Other) { 411 // Sometimes it's at the beginning. 412 TheChain = SDValue(Node, 0); 413 if (TheChain.getValueType() != MVT::Other) { 414 // Otherwise, hunt for it. 415 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 416 if (Node->getValueType(i) == MVT::Other) { 417 TheChain = SDValue(Node, i); 418 break; 419 } 420 421 // Otherwise, we walked into a node without a chain. 422 if (TheChain.getValueType() != MVT::Other) 423 return 0; 424 } 425 } 426 427 for (SDNode::use_iterator UI = Node->use_begin(), 428 E = Node->use_end(); UI != E; ++UI) { 429 430 // Make sure to only follow users of our token chain. 431 SDNode *User = *UI; 432 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 433 if (User->getOperand(i) == TheChain) 434 if (SDNode *Result = FindCallEndFromCallStart(User)) 435 return Result; 436 } 437 return 0; 438} 439 440/// FindCallStartFromCallEnd - Given a chained node that is part of a call 441/// sequence, find the CALLSEQ_START node that initiates the call sequence. 442static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 443 assert(Node && "Didn't find callseq_start for a call??"); 444 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 445 446 assert(Node->getOperand(0).getValueType() == MVT::Other && 447 "Node doesn't have a token chain argument!"); 448 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 449} 450 451/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 452/// see if any uses can reach Dest. If no dest operands can get to dest, 453/// legalize them, legalize ourself, and return false, otherwise, return true. 454/// 455/// Keep track of the nodes we fine that actually do lead to Dest in 456/// NodesLeadingTo. This avoids retraversing them exponential number of times. 457/// 458bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 459 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 460 if (N == Dest) return true; // N certainly leads to Dest :) 461 462 // If we've already processed this node and it does lead to Dest, there is no 463 // need to reprocess it. 464 if (NodesLeadingTo.count(N)) return true; 465 466 // If the first result of this node has been already legalized, then it cannot 467 // reach N. 468 switch (getTypeAction(N->getValueType(0))) { 469 case Legal: 470 if (LegalizedNodes.count(SDValue(N, 0))) return false; 471 break; 472 case Promote: 473 if (PromotedNodes.count(SDValue(N, 0))) return false; 474 break; 475 case Expand: 476 if (ExpandedNodes.count(SDValue(N, 0))) return false; 477 break; 478 } 479 480 // Okay, this node has not already been legalized. Check and legalize all 481 // operands. If none lead to Dest, then we can legalize this node. 482 bool OperandsLeadToDest = false; 483 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 484 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 485 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 486 487 if (OperandsLeadToDest) { 488 NodesLeadingTo.insert(N); 489 return true; 490 } 491 492 // Okay, this node looks safe, legalize it and return false. 493 HandleOp(SDValue(N, 0)); 494 return false; 495} 496 497/// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as 498/// appropriate for its type. 499void SelectionDAGLegalize::HandleOp(SDValue Op) { 500 MVT VT = Op.getValueType(); 501 // If the type legalizer was run then we should never see any illegal result 502 // types here except for target constants (the type legalizer does not touch 503 // those) or for build vector used as a mask for a vector shuffle. 504 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957. 505 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal || 506 Op.getOpcode() == ISD::TargetConstant || 507 Op.getOpcode() == ISD::BUILD_VECTOR) && 508 "Illegal type introduced after type legalization?"); 509 switch (getTypeAction(VT)) { 510 default: assert(0 && "Bad type action!"); 511 case Legal: (void)LegalizeOp(Op); break; 512 case Promote: 513 if (!VT.isVector()) { 514 (void)PromoteOp(Op); 515 break; 516 } 517 else { 518 // See if we can widen otherwise use Expand to either scalarize or split 519 MVT WidenVT = TLI.getWidenVectorType(VT); 520 if (WidenVT != MVT::Other) { 521 (void) WidenVectorOp(Op, WidenVT); 522 break; 523 } 524 // else fall thru to expand since we can't widen the vector 525 } 526 case Expand: 527 if (!VT.isVector()) { 528 // If this is an illegal scalar, expand it into its two component 529 // pieces. 530 SDValue X, Y; 531 if (Op.getOpcode() == ISD::TargetConstant) 532 break; // Allow illegal target nodes. 533 ExpandOp(Op, X, Y); 534 } else if (VT.getVectorNumElements() == 1) { 535 // If this is an illegal single element vector, convert it to a 536 // scalar operation. 537 (void)ScalarizeVectorOp(Op); 538 } else { 539 // This is an illegal multiple element vector. 540 // Split it in half and legalize both parts. 541 SDValue X, Y; 542 SplitVectorOp(Op, X, Y); 543 } 544 break; 545 } 546} 547 548/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 549/// a load from the constant pool. 550static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 551 SelectionDAG &DAG, const TargetLowering &TLI) { 552 bool Extend = false; 553 554 // If a FP immediate is precise when represented as a float and if the 555 // target can do an extending load from float to double, we put it into 556 // the constant pool as a float, even if it's is statically typed as a 557 // double. This shrinks FP constants and canonicalizes them for targets where 558 // an FP extending load is the same cost as a normal load (such as on the x87 559 // fp stack or PPC FP unit). 560 MVT VT = CFP->getValueType(0); 561 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 562 if (!UseCP) { 563 if (VT!=MVT::f64 && VT!=MVT::f32) 564 assert(0 && "Invalid type expansion"); 565 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 566 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 567 } 568 569 MVT OrigVT = VT; 570 MVT SVT = VT; 571 while (SVT != MVT::f32) { 572 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 573 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 574 // Only do this if the target has a native EXTLOAD instruction from 575 // smaller type. 576 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 577 TLI.ShouldShrinkFPConstant(OrigVT)) { 578 const Type *SType = SVT.getTypeForMVT(); 579 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 580 VT = SVT; 581 Extend = true; 582 } 583 } 584 585 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 586 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 587 if (Extend) 588 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), 589 CPIdx, PseudoSourceValue::getConstantPool(), 590 0, VT, false, Alignment); 591 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 592 PseudoSourceValue::getConstantPool(), 0, false, Alignment); 593} 594 595 596/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 597/// operations. 598static 599SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, 600 SelectionDAG &DAG, 601 const TargetLowering &TLI) { 602 DebugLoc dl = Node->getDebugLoc(); 603 MVT VT = Node->getValueType(0); 604 MVT SrcVT = Node->getOperand(1).getValueType(); 605 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 606 "fcopysign expansion only supported for f32 and f64"); 607 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 608 609 // First get the sign bit of second operand. 610 SDValue Mask1 = (SrcVT == MVT::f64) 611 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 612 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 613 Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1); 614 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, 615 Node->getOperand(1)); 616 SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1); 617 // Shift right or sign-extend it if the two operands have different types. 618 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); 619 if (SizeDiff > 0) { 620 SignBit = DAG.getNode(ISD::SRL, dl, SrcNVT, SignBit, 621 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 622 SignBit = DAG.getNode(ISD::TRUNCATE, dl, NVT, SignBit); 623 } else if (SizeDiff < 0) { 624 SignBit = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, SignBit); 625 SignBit = DAG.getNode(ISD::SHL, dl, NVT, SignBit, 626 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy())); 627 } 628 629 // Clear the sign bit of first operand. 630 SDValue Mask2 = (VT == MVT::f64) 631 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 632 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 633 Mask2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask2); 634 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 635 Result = DAG.getNode(ISD::AND, dl, NVT, Result, Mask2); 636 637 // Or the value with the sign bit. 638 Result = DAG.getNode(ISD::OR, dl, NVT, Result, SignBit); 639 return Result; 640} 641 642/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 643static 644SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 645 const TargetLowering &TLI) { 646 SDValue Chain = ST->getChain(); 647 SDValue Ptr = ST->getBasePtr(); 648 SDValue Val = ST->getValue(); 649 MVT VT = Val.getValueType(); 650 int Alignment = ST->getAlignment(); 651 int SVOffset = ST->getSrcValueOffset(); 652 DebugLoc dl = ST->getDebugLoc(); 653 if (ST->getMemoryVT().isFloatingPoint() || 654 ST->getMemoryVT().isVector()) { 655 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits()); 656 if (TLI.isTypeLegal(intVT)) { 657 // Expand to a bitconvert of the value to the integer type of the 658 // same size, then a (misaligned) int store. 659 // FIXME: Does not handle truncating floating point stores! 660 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 661 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 662 SVOffset, ST->isVolatile(), Alignment); 663 } else { 664 // Do a (aligned) store to a stack slot, then copy from the stack slot 665 // to the final destination using (unaligned) integer loads and stores. 666 MVT StoredVT = ST->getMemoryVT(); 667 MVT RegVT = 668 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits())); 669 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 670 unsigned RegBytes = RegVT.getSizeInBits() / 8; 671 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 672 673 // Make sure the stack slot is also aligned for the register type. 674 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 675 676 // Perform the original store, only redirected to the stack slot. 677 SDValue Store = DAG.getTruncStore(Chain, dl, 678 Val, StackPtr, NULL, 0,StoredVT); 679 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 680 SmallVector<SDValue, 8> Stores; 681 unsigned Offset = 0; 682 683 // Do all but one copies using the full register width. 684 for (unsigned i = 1; i < NumRegs; i++) { 685 // Load one integer register's worth from the stack slot. 686 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0); 687 // Store it to the final location. Remember the store. 688 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 689 ST->getSrcValue(), SVOffset + Offset, 690 ST->isVolatile(), 691 MinAlign(ST->getAlignment(), Offset))); 692 // Increment the pointers. 693 Offset += RegBytes; 694 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 695 Increment); 696 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 697 } 698 699 // The last store may be partial. Do a truncating store. On big-endian 700 // machines this requires an extending load from the stack slot to ensure 701 // that the bits are in the right place. 702 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset)); 703 704 // Load from the stack slot. 705 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 706 NULL, 0, MemVT); 707 708 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 709 ST->getSrcValue(), SVOffset + Offset, 710 MemVT, ST->isVolatile(), 711 MinAlign(ST->getAlignment(), Offset))); 712 // The order of the stores doesn't matter - say it with a TokenFactor. 713 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 714 Stores.size()); 715 } 716 } 717 assert(ST->getMemoryVT().isInteger() && 718 !ST->getMemoryVT().isVector() && 719 "Unaligned store of unknown type."); 720 // Get the half-size VT 721 MVT NewStoredVT = 722 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 723 int NumBits = NewStoredVT.getSizeInBits(); 724 int IncrementSize = NumBits / 8; 725 726 // Divide the stored value in two parts. 727 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 728 SDValue Lo = Val; 729 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 730 731 // Store the two parts 732 SDValue Store1, Store2; 733 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 734 ST->getSrcValue(), SVOffset, NewStoredVT, 735 ST->isVolatile(), Alignment); 736 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 737 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 738 Alignment = MinAlign(Alignment, IncrementSize); 739 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 740 ST->getSrcValue(), SVOffset + IncrementSize, 741 NewStoredVT, ST->isVolatile(), Alignment); 742 743 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 744} 745 746/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 747static 748SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 749 const TargetLowering &TLI) { 750 int SVOffset = LD->getSrcValueOffset(); 751 SDValue Chain = LD->getChain(); 752 SDValue Ptr = LD->getBasePtr(); 753 MVT VT = LD->getValueType(0); 754 MVT LoadedVT = LD->getMemoryVT(); 755 DebugLoc dl = LD->getDebugLoc(); 756 if (VT.isFloatingPoint() || VT.isVector()) { 757 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits()); 758 if (TLI.isTypeLegal(intVT)) { 759 // Expand to a (misaligned) integer load of the same size, 760 // then bitconvert to floating point or vector. 761 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 762 SVOffset, LD->isVolatile(), 763 LD->getAlignment()); 764 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 765 if (VT.isFloatingPoint() && LoadedVT != VT) 766 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 767 768 SDValue Ops[] = { Result, Chain }; 769 return DAG.getMergeValues(Ops, 2, dl); 770 } else { 771 // Copy the value to a (aligned) stack slot using (unaligned) integer 772 // loads and stores, then do a (aligned) load from the stack slot. 773 MVT RegVT = TLI.getRegisterType(intVT); 774 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 775 unsigned RegBytes = RegVT.getSizeInBits() / 8; 776 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 777 778 // Make sure the stack slot is also aligned for the register type. 779 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 780 781 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 782 SmallVector<SDValue, 8> Stores; 783 SDValue StackPtr = StackBase; 784 unsigned Offset = 0; 785 786 // Do all but one copies using the full register width. 787 for (unsigned i = 1; i < NumRegs; i++) { 788 // Load one integer register's worth from the original location. 789 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 790 SVOffset + Offset, LD->isVolatile(), 791 MinAlign(LD->getAlignment(), Offset)); 792 // Follow the load with a store to the stack slot. Remember the store. 793 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 794 NULL, 0)); 795 // Increment the pointers. 796 Offset += RegBytes; 797 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 798 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 799 Increment); 800 } 801 802 // The last copy may be partial. Do an extending load. 803 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset)); 804 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 805 LD->getSrcValue(), SVOffset + Offset, 806 MemVT, LD->isVolatile(), 807 MinAlign(LD->getAlignment(), Offset)); 808 // Follow the load with a store to the stack slot. Remember the store. 809 // On big-endian machines this requires a truncating store to ensure 810 // that the bits end up in the right place. 811 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 812 NULL, 0, MemVT)); 813 814 // The order of the stores doesn't matter - say it with a TokenFactor. 815 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 816 Stores.size()); 817 818 // Finally, perform the original load only redirected to the stack slot. 819 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 820 NULL, 0, LoadedVT); 821 822 // Callers expect a MERGE_VALUES node. 823 SDValue Ops[] = { Load, TF }; 824 return DAG.getMergeValues(Ops, 2, dl); 825 } 826 } 827 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 828 "Unaligned load of unsupported type."); 829 830 // Compute the new VT that is half the size of the old one. This is an 831 // integer MVT. 832 unsigned NumBits = LoadedVT.getSizeInBits(); 833 MVT NewLoadedVT; 834 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 835 NumBits >>= 1; 836 837 unsigned Alignment = LD->getAlignment(); 838 unsigned IncrementSize = NumBits / 8; 839 ISD::LoadExtType HiExtType = LD->getExtensionType(); 840 841 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 842 if (HiExtType == ISD::NON_EXTLOAD) 843 HiExtType = ISD::ZEXTLOAD; 844 845 // Load the value in two parts 846 SDValue Lo, Hi; 847 if (TLI.isLittleEndian()) { 848 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 849 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 850 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 851 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 852 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 853 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 854 MinAlign(Alignment, IncrementSize)); 855 } else { 856 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 857 SVOffset, NewLoadedVT,LD->isVolatile(), Alignment); 858 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 859 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 860 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 861 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 862 MinAlign(Alignment, IncrementSize)); 863 } 864 865 // aggregate the two parts 866 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 867 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 868 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 869 870 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 871 Hi.getValue(1)); 872 873 SDValue Ops[] = { Result, TF }; 874 return DAG.getMergeValues(Ops, 2, dl); 875} 876 877/// UnrollVectorOp - We know that the given vector has a legal type, however 878/// the operation it performs is not legal and is an operation that we have 879/// no way of lowering. "Unroll" the vector, splitting out the scalars and 880/// operating on each element individually. 881SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) { 882 MVT VT = Op.getValueType(); 883 assert(isTypeLegal(VT) && 884 "Caller should expand or promote operands that are not legal!"); 885 assert(Op.getNode()->getNumValues() == 1 && 886 "Can't unroll a vector with multiple results!"); 887 unsigned NE = VT.getVectorNumElements(); 888 MVT EltVT = VT.getVectorElementType(); 889 DebugLoc dl = Op.getNode()->getDebugLoc(); 890 891 SmallVector<SDValue, 8> Scalars; 892 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 893 for (unsigned i = 0; i != NE; ++i) { 894 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 895 SDValue Operand = Op.getOperand(j); 896 MVT OperandVT = Operand.getValueType(); 897 if (OperandVT.isVector()) { 898 // A vector operand; extract a single element. 899 MVT OperandEltVT = OperandVT.getVectorElementType(); 900 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 901 OperandEltVT, 902 Operand, 903 DAG.getConstant(i, MVT::i32)); 904 } else { 905 // A scalar operand; just use it as is. 906 Operands[j] = Operand; 907 } 908 } 909 910 switch (Op.getOpcode()) { 911 default: 912 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, 913 &Operands[0], Operands.size())); 914 break; 915 case ISD::SHL: 916 case ISD::SRA: 917 case ISD::SRL: 918 case ISD::ROTL: 919 case ISD::ROTR: 920 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0], 921 DAG.getShiftAmountOperand(Operands[1]))); 922 break; 923 } 924 } 925 926 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size()); 927} 928 929/// GetFPLibCall - Return the right libcall for the given floating point type. 930static RTLIB::Libcall GetFPLibCall(MVT VT, 931 RTLIB::Libcall Call_F32, 932 RTLIB::Libcall Call_F64, 933 RTLIB::Libcall Call_F80, 934 RTLIB::Libcall Call_PPCF128) { 935 return 936 VT == MVT::f32 ? Call_F32 : 937 VT == MVT::f64 ? Call_F64 : 938 VT == MVT::f80 ? Call_F80 : 939 VT == MVT::ppcf128 ? Call_PPCF128 : 940 RTLIB::UNKNOWN_LIBCALL; 941} 942 943/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 944/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 945/// is necessary to spill the vector being inserted into to memory, perform 946/// the insert there, and then read the result back. 947SDValue SelectionDAGLegalize:: 948PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 949 DebugLoc dl) { 950 SDValue Tmp1 = Vec; 951 SDValue Tmp2 = Val; 952 SDValue Tmp3 = Idx; 953 954 // If the target doesn't support this, we have to spill the input vector 955 // to a temporary stack slot, update the element, then reload it. This is 956 // badness. We could also load the value into a vector register (either 957 // with a "move to register" or "extload into register" instruction, then 958 // permute it into place, if the idx is a constant and if the idx is 959 // supported by the target. 960 MVT VT = Tmp1.getValueType(); 961 MVT EltVT = VT.getVectorElementType(); 962 MVT IdxVT = Tmp3.getValueType(); 963 MVT PtrVT = TLI.getPointerTy(); 964 SDValue StackPtr = DAG.CreateStackTemporary(VT); 965 966 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 967 968 // Store the vector. 969 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 970 PseudoSourceValue::getFixedStack(SPFI), 0); 971 972 // Truncate or zero extend offset to target pointer type. 973 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 974 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 975 // Add the offset to the index. 976 unsigned EltSize = EltVT.getSizeInBits()/8; 977 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 978 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 979 // Store the scalar value. 980 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 981 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 982 // Load the updated vector. 983 return DAG.getLoad(VT, dl, Ch, StackPtr, 984 PseudoSourceValue::getFixedStack(SPFI), 0); 985} 986 987 988/// LegalizeOp - We know that the specified value has a legal type, and 989/// that its operands are legal. Now ensure that the operation itself 990/// is legal, recursively ensuring that the operands' operations remain 991/// legal. 992SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 993 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 994 return Op; 995 996 assert(isTypeLegal(Op.getValueType()) && 997 "Caller should expand or promote operands that are not legal!"); 998 SDNode *Node = Op.getNode(); 999 DebugLoc dl = Node->getDebugLoc(); 1000 1001 // If this operation defines any values that cannot be represented in a 1002 // register on this target, make sure to expand or promote them. 1003 if (Node->getNumValues() > 1) { 1004 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1005 if (getTypeAction(Node->getValueType(i)) != Legal) { 1006 HandleOp(Op.getValue(i)); 1007 assert(LegalizedNodes.count(Op) && 1008 "Handling didn't add legal operands!"); 1009 return LegalizedNodes[Op]; 1010 } 1011 } 1012 1013 // Note that LegalizeOp may be reentered even from single-use nodes, which 1014 // means that we always must cache transformed nodes. 1015 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1016 if (I != LegalizedNodes.end()) return I->second; 1017 1018 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 1019 SDValue Result = Op; 1020 bool isCustom = false; 1021 1022 switch (Node->getOpcode()) { 1023 case ISD::FrameIndex: 1024 case ISD::EntryToken: 1025 case ISD::Register: 1026 case ISD::BasicBlock: 1027 case ISD::TargetFrameIndex: 1028 case ISD::TargetJumpTable: 1029 case ISD::TargetConstant: 1030 case ISD::TargetConstantFP: 1031 case ISD::TargetConstantPool: 1032 case ISD::TargetGlobalAddress: 1033 case ISD::TargetGlobalTLSAddress: 1034 case ISD::TargetExternalSymbol: 1035 case ISD::VALUETYPE: 1036 case ISD::SRCVALUE: 1037 case ISD::MEMOPERAND: 1038 case ISD::CONDCODE: 1039 case ISD::ARG_FLAGS: 1040 // Primitives must all be legal. 1041 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 1042 "This must be legal!"); 1043 break; 1044 default: 1045 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 1046 // If this is a target node, legalize it by legalizing the operands then 1047 // passing it through. 1048 SmallVector<SDValue, 8> Ops; 1049 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1050 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1051 1052 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 1053 1054 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1055 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 1056 return Result.getValue(Op.getResNo()); 1057 } 1058 // Otherwise this is an unhandled builtin node. splat. 1059#ifndef NDEBUG 1060 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 1061#endif 1062 assert(0 && "Do not know how to legalize this operator!"); 1063 abort(); 1064 case ISD::GLOBAL_OFFSET_TABLE: 1065 case ISD::GlobalAddress: 1066 case ISD::GlobalTLSAddress: 1067 case ISD::ExternalSymbol: 1068 case ISD::ConstantPool: 1069 case ISD::JumpTable: // Nothing to do. 1070 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1071 default: assert(0 && "This action is not supported yet!"); 1072 case TargetLowering::Custom: 1073 Tmp1 = TLI.LowerOperation(Op, DAG); 1074 if (Tmp1.getNode()) Result = Tmp1; 1075 // FALLTHROUGH if the target doesn't want to lower this op after all. 1076 case TargetLowering::Legal: 1077 break; 1078 } 1079 break; 1080 case ISD::FRAMEADDR: 1081 case ISD::RETURNADDR: 1082 // The only option for these nodes is to custom lower them. If the target 1083 // does not custom lower them, then return zero. 1084 Tmp1 = TLI.LowerOperation(Op, DAG); 1085 if (Tmp1.getNode()) 1086 Result = Tmp1; 1087 else 1088 Result = DAG.getConstant(0, TLI.getPointerTy()); 1089 break; 1090 case ISD::FRAME_TO_ARGS_OFFSET: { 1091 MVT VT = Node->getValueType(0); 1092 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1093 default: assert(0 && "This action is not supported yet!"); 1094 case TargetLowering::Custom: 1095 Result = TLI.LowerOperation(Op, DAG); 1096 if (Result.getNode()) break; 1097 // Fall Thru 1098 case TargetLowering::Legal: 1099 Result = DAG.getConstant(0, VT); 1100 break; 1101 } 1102 } 1103 break; 1104 case ISD::EXCEPTIONADDR: { 1105 Tmp1 = LegalizeOp(Node->getOperand(0)); 1106 MVT VT = Node->getValueType(0); 1107 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1108 default: assert(0 && "This action is not supported yet!"); 1109 case TargetLowering::Expand: { 1110 unsigned Reg = TLI.getExceptionAddressRegister(); 1111 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 1112 } 1113 break; 1114 case TargetLowering::Custom: 1115 Result = TLI.LowerOperation(Op, DAG); 1116 if (Result.getNode()) break; 1117 // Fall Thru 1118 case TargetLowering::Legal: { 1119 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 1120 Result = DAG.getMergeValues(Ops, 2); 1121 break; 1122 } 1123 } 1124 } 1125 if (Result.getNode()->getNumValues() == 1) break; 1126 1127 assert(Result.getNode()->getNumValues() == 2 && 1128 "Cannot return more than two values!"); 1129 1130 // Since we produced two values, make sure to remember that we 1131 // legalized both of them. 1132 Tmp1 = LegalizeOp(Result); 1133 Tmp2 = LegalizeOp(Result.getValue(1)); 1134 AddLegalizedOperand(Op.getValue(0), Tmp1); 1135 AddLegalizedOperand(Op.getValue(1), Tmp2); 1136 return Op.getResNo() ? Tmp2 : Tmp1; 1137 case ISD::EHSELECTION: { 1138 Tmp1 = LegalizeOp(Node->getOperand(0)); 1139 Tmp2 = LegalizeOp(Node->getOperand(1)); 1140 MVT VT = Node->getValueType(0); 1141 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1142 default: assert(0 && "This action is not supported yet!"); 1143 case TargetLowering::Expand: { 1144 unsigned Reg = TLI.getExceptionSelectorRegister(); 1145 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 1146 } 1147 break; 1148 case TargetLowering::Custom: 1149 Result = TLI.LowerOperation(Op, DAG); 1150 if (Result.getNode()) break; 1151 // Fall Thru 1152 case TargetLowering::Legal: { 1153 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 1154 Result = DAG.getMergeValues(Ops, 2); 1155 break; 1156 } 1157 } 1158 } 1159 if (Result.getNode()->getNumValues() == 1) break; 1160 1161 assert(Result.getNode()->getNumValues() == 2 && 1162 "Cannot return more than two values!"); 1163 1164 // Since we produced two values, make sure to remember that we 1165 // legalized both of them. 1166 Tmp1 = LegalizeOp(Result); 1167 Tmp2 = LegalizeOp(Result.getValue(1)); 1168 AddLegalizedOperand(Op.getValue(0), Tmp1); 1169 AddLegalizedOperand(Op.getValue(1), Tmp2); 1170 return Op.getResNo() ? Tmp2 : Tmp1; 1171 case ISD::EH_RETURN: { 1172 MVT VT = Node->getValueType(0); 1173 // The only "good" option for this node is to custom lower it. 1174 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1175 default: assert(0 && "This action is not supported at all!"); 1176 case TargetLowering::Custom: 1177 Result = TLI.LowerOperation(Op, DAG); 1178 if (Result.getNode()) break; 1179 // Fall Thru 1180 case TargetLowering::Legal: 1181 // Target does not know, how to lower this, lower to noop 1182 Result = LegalizeOp(Node->getOperand(0)); 1183 break; 1184 } 1185 } 1186 break; 1187 case ISD::AssertSext: 1188 case ISD::AssertZext: 1189 Tmp1 = LegalizeOp(Node->getOperand(0)); 1190 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1191 break; 1192 case ISD::MERGE_VALUES: 1193 // Legalize eliminates MERGE_VALUES nodes. 1194 Result = Node->getOperand(Op.getResNo()); 1195 break; 1196 case ISD::CopyFromReg: 1197 Tmp1 = LegalizeOp(Node->getOperand(0)); 1198 Result = Op.getValue(0); 1199 if (Node->getNumValues() == 2) { 1200 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1201 } else { 1202 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 1203 if (Node->getNumOperands() == 3) { 1204 Tmp2 = LegalizeOp(Node->getOperand(2)); 1205 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1206 } else { 1207 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1208 } 1209 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 1210 } 1211 // Since CopyFromReg produces two values, make sure to remember that we 1212 // legalized both of them. 1213 AddLegalizedOperand(Op.getValue(0), Result); 1214 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1215 return Result.getValue(Op.getResNo()); 1216 case ISD::UNDEF: { 1217 MVT VT = Op.getValueType(); 1218 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 1219 default: assert(0 && "This action is not supported yet!"); 1220 case TargetLowering::Expand: 1221 if (VT.isInteger()) 1222 Result = DAG.getConstant(0, VT); 1223 else if (VT.isFloatingPoint()) 1224 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), 1225 VT); 1226 else 1227 assert(0 && "Unknown value type!"); 1228 break; 1229 case TargetLowering::Legal: 1230 break; 1231 } 1232 break; 1233 } 1234 1235 case ISD::INTRINSIC_W_CHAIN: 1236 case ISD::INTRINSIC_WO_CHAIN: 1237 case ISD::INTRINSIC_VOID: { 1238 SmallVector<SDValue, 8> Ops; 1239 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1240 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1241 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1242 1243 // Allow the target to custom lower its intrinsics if it wants to. 1244 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1245 TargetLowering::Custom) { 1246 Tmp3 = TLI.LowerOperation(Result, DAG); 1247 if (Tmp3.getNode()) Result = Tmp3; 1248 } 1249 1250 if (Result.getNode()->getNumValues() == 1) break; 1251 1252 // Must have return value and chain result. 1253 assert(Result.getNode()->getNumValues() == 2 && 1254 "Cannot return more than two values!"); 1255 1256 // Since loads produce two values, make sure to remember that we 1257 // legalized both of them. 1258 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1259 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1260 return Result.getValue(Op.getResNo()); 1261 } 1262 1263 case ISD::DBG_STOPPOINT: 1264 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!"); 1265 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1266 1267 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) { 1268 case TargetLowering::Promote: 1269 default: assert(0 && "This action is not supported yet!"); 1270 case TargetLowering::Expand: { 1271 DwarfWriter *DW = DAG.getDwarfWriter(); 1272 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, 1273 MVT::Other); 1274 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); 1275 1276 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1277 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit()); 1278 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) { 1279 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit())); 1280 unsigned SrcFile = DW->RecordSource(CU.getDirectory(), 1281 CU.getFilename()); 1282 1283 unsigned Line = DSP->getLine(); 1284 unsigned Col = DSP->getColumn(); 1285 1286 if (useDEBUG_LOC) { 1287 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), 1288 DAG.getConstant(Col, MVT::i32), 1289 DAG.getConstant(SrcFile, MVT::i32) }; 1290 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4); 1291 } else { 1292 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile); 1293 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID); 1294 } 1295 } else { 1296 Result = Tmp1; // chain 1297 } 1298 break; 1299 } 1300 case TargetLowering::Legal: { 1301 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1302 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1303 break; 1304 1305 SmallVector<SDValue, 8> Ops; 1306 Ops.push_back(Tmp1); 1307 if (Action == Legal) { 1308 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1309 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1310 } else { 1311 // Otherwise promote them. 1312 Ops.push_back(PromoteOp(Node->getOperand(1))); 1313 Ops.push_back(PromoteOp(Node->getOperand(2))); 1314 } 1315 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1316 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1317 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1318 break; 1319 } 1320 } 1321 break; 1322 1323 case ISD::DECLARE: 1324 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1325 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1326 default: assert(0 && "This action is not supported yet!"); 1327 case TargetLowering::Legal: 1328 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1329 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1330 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1331 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1332 break; 1333 case TargetLowering::Expand: 1334 Result = LegalizeOp(Node->getOperand(0)); 1335 break; 1336 } 1337 break; 1338 1339 case ISD::DEBUG_LOC: 1340 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1341 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1342 default: assert(0 && "This action is not supported yet!"); 1343 case TargetLowering::Legal: { 1344 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1345 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1346 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1347 break; 1348 if (Action == Legal) { 1349 Tmp2 = Node->getOperand(1); 1350 Tmp3 = Node->getOperand(2); 1351 Tmp4 = Node->getOperand(3); 1352 } else { 1353 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1354 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1355 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1356 } 1357 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1358 break; 1359 } 1360 } 1361 break; 1362 1363 case ISD::DBG_LABEL: 1364 case ISD::EH_LABEL: 1365 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!"); 1366 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1367 default: assert(0 && "This action is not supported yet!"); 1368 case TargetLowering::Legal: 1369 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1370 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1371 break; 1372 case TargetLowering::Expand: 1373 Result = LegalizeOp(Node->getOperand(0)); 1374 break; 1375 } 1376 break; 1377 1378 case ISD::PREFETCH: 1379 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1380 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1381 default: assert(0 && "This action is not supported yet!"); 1382 case TargetLowering::Legal: 1383 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1384 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1385 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1386 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1387 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1388 break; 1389 case TargetLowering::Expand: 1390 // It's a noop. 1391 Result = LegalizeOp(Node->getOperand(0)); 1392 break; 1393 } 1394 break; 1395 1396 case ISD::MEMBARRIER: { 1397 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1398 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1399 default: assert(0 && "This action is not supported yet!"); 1400 case TargetLowering::Legal: { 1401 SDValue Ops[6]; 1402 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1403 for (int x = 1; x < 6; ++x) { 1404 Ops[x] = Node->getOperand(x); 1405 if (!isTypeLegal(Ops[x].getValueType())) 1406 Ops[x] = PromoteOp(Ops[x]); 1407 } 1408 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1409 break; 1410 } 1411 case TargetLowering::Expand: 1412 //There is no libgcc call for this op 1413 Result = Node->getOperand(0); // Noop 1414 break; 1415 } 1416 break; 1417 } 1418 1419 case ISD::ATOMIC_CMP_SWAP: { 1420 unsigned int num_operands = 4; 1421 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1422 SDValue Ops[4]; 1423 for (unsigned int x = 0; x < num_operands; ++x) 1424 Ops[x] = LegalizeOp(Node->getOperand(x)); 1425 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1426 1427 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1428 default: assert(0 && "This action is not supported yet!"); 1429 case TargetLowering::Custom: 1430 Result = TLI.LowerOperation(Result, DAG); 1431 break; 1432 case TargetLowering::Legal: 1433 break; 1434 } 1435 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1436 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1437 return Result.getValue(Op.getResNo()); 1438 } 1439 case ISD::ATOMIC_LOAD_ADD: 1440 case ISD::ATOMIC_LOAD_SUB: 1441 case ISD::ATOMIC_LOAD_AND: 1442 case ISD::ATOMIC_LOAD_OR: 1443 case ISD::ATOMIC_LOAD_XOR: 1444 case ISD::ATOMIC_LOAD_NAND: 1445 case ISD::ATOMIC_LOAD_MIN: 1446 case ISD::ATOMIC_LOAD_MAX: 1447 case ISD::ATOMIC_LOAD_UMIN: 1448 case ISD::ATOMIC_LOAD_UMAX: 1449 case ISD::ATOMIC_SWAP: { 1450 unsigned int num_operands = 3; 1451 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1452 SDValue Ops[3]; 1453 for (unsigned int x = 0; x < num_operands; ++x) 1454 Ops[x] = LegalizeOp(Node->getOperand(x)); 1455 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1456 1457 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1458 default: assert(0 && "This action is not supported yet!"); 1459 case TargetLowering::Custom: 1460 Result = TLI.LowerOperation(Result, DAG); 1461 break; 1462 case TargetLowering::Legal: 1463 break; 1464 } 1465 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1466 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1467 return Result.getValue(Op.getResNo()); 1468 } 1469 case ISD::Constant: { 1470 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1471 unsigned opAction = 1472 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1473 1474 // We know we don't need to expand constants here, constants only have one 1475 // value and we check that it is fine above. 1476 1477 if (opAction == TargetLowering::Custom) { 1478 Tmp1 = TLI.LowerOperation(Result, DAG); 1479 if (Tmp1.getNode()) 1480 Result = Tmp1; 1481 } 1482 break; 1483 } 1484 case ISD::ConstantFP: { 1485 // Spill FP immediates to the constant pool if the target cannot directly 1486 // codegen them. Targets often have some immediate values that can be 1487 // efficiently generated into an FP register without a load. We explicitly 1488 // leave these constants as ConstantFP nodes for the target to deal with. 1489 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1490 1491 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1492 default: assert(0 && "This action is not supported yet!"); 1493 case TargetLowering::Legal: 1494 break; 1495 case TargetLowering::Custom: 1496 Tmp3 = TLI.LowerOperation(Result, DAG); 1497 if (Tmp3.getNode()) { 1498 Result = Tmp3; 1499 break; 1500 } 1501 // FALLTHROUGH 1502 case TargetLowering::Expand: { 1503 // Check to see if this FP immediate is already legal. 1504 bool isLegal = false; 1505 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1506 E = TLI.legal_fpimm_end(); I != E; ++I) { 1507 if (CFP->isExactlyValue(*I)) { 1508 isLegal = true; 1509 break; 1510 } 1511 } 1512 // If this is a legal constant, turn it into a TargetConstantFP node. 1513 if (isLegal) 1514 break; 1515 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1516 } 1517 } 1518 break; 1519 } 1520 case ISD::TokenFactor: 1521 if (Node->getNumOperands() == 2) { 1522 Tmp1 = LegalizeOp(Node->getOperand(0)); 1523 Tmp2 = LegalizeOp(Node->getOperand(1)); 1524 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1525 } else if (Node->getNumOperands() == 3) { 1526 Tmp1 = LegalizeOp(Node->getOperand(0)); 1527 Tmp2 = LegalizeOp(Node->getOperand(1)); 1528 Tmp3 = LegalizeOp(Node->getOperand(2)); 1529 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1530 } else { 1531 SmallVector<SDValue, 8> Ops; 1532 // Legalize the operands. 1533 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1534 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1535 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1536 } 1537 break; 1538 1539 case ISD::FORMAL_ARGUMENTS: 1540 case ISD::CALL: 1541 // The only option for this is to custom lower it. 1542 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1543 assert(Tmp3.getNode() && "Target didn't custom lower this node!"); 1544 // A call within a calling sequence must be legalized to something 1545 // other than the normal CALLSEQ_END. Violating this gets Legalize 1546 // into an infinite loop. 1547 assert ((!IsLegalizingCall || 1548 Node->getOpcode() != ISD::CALL || 1549 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) && 1550 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1551 1552 // The number of incoming and outgoing values should match; unless the final 1553 // outgoing value is a flag. 1554 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || 1555 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 && 1556 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == 1557 MVT::Flag)) && 1558 "Lowering call/formal_arguments produced unexpected # results!"); 1559 1560 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1561 // remember that we legalized all of them, so it doesn't get relegalized. 1562 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) { 1563 if (Tmp3.getNode()->getValueType(i) == MVT::Flag) 1564 continue; 1565 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1566 if (Op.getResNo() == i) 1567 Tmp2 = Tmp1; 1568 AddLegalizedOperand(SDValue(Node, i), Tmp1); 1569 } 1570 return Tmp2; 1571 case ISD::EXTRACT_SUBREG: { 1572 Tmp1 = LegalizeOp(Node->getOperand(0)); 1573 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1574 assert(idx && "Operand must be a constant"); 1575 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); 1576 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1577 } 1578 break; 1579 case ISD::INSERT_SUBREG: { 1580 Tmp1 = LegalizeOp(Node->getOperand(0)); 1581 Tmp2 = LegalizeOp(Node->getOperand(1)); 1582 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1583 assert(idx && "Operand must be a constant"); 1584 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); 1585 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1586 } 1587 break; 1588 case ISD::BUILD_VECTOR: 1589 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1590 default: assert(0 && "This action is not supported yet!"); 1591 case TargetLowering::Custom: 1592 Tmp3 = TLI.LowerOperation(Result, DAG); 1593 if (Tmp3.getNode()) { 1594 Result = Tmp3; 1595 break; 1596 } 1597 // FALLTHROUGH 1598 case TargetLowering::Expand: 1599 Result = ExpandBUILD_VECTOR(Result.getNode()); 1600 break; 1601 } 1602 break; 1603 case ISD::INSERT_VECTOR_ELT: 1604 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1605 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1606 1607 // The type of the value to insert may not be legal, even though the vector 1608 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1609 // here. 1610 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1611 default: assert(0 && "Cannot expand insert element operand"); 1612 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1613 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1614 case Expand: 1615 // FIXME: An alternative would be to check to see if the target is not 1616 // going to custom lower this operation, we could bitcast to half elt 1617 // width and perform two inserts at that width, if that is legal. 1618 Tmp2 = Node->getOperand(1); 1619 break; 1620 } 1621 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1622 1623 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1624 Node->getValueType(0))) { 1625 default: assert(0 && "This action is not supported yet!"); 1626 case TargetLowering::Legal: 1627 break; 1628 case TargetLowering::Custom: 1629 Tmp4 = TLI.LowerOperation(Result, DAG); 1630 if (Tmp4.getNode()) { 1631 Result = Tmp4; 1632 break; 1633 } 1634 // FALLTHROUGH 1635 case TargetLowering::Promote: 1636 // Fall thru for vector case 1637 case TargetLowering::Expand: { 1638 // If the insert index is a constant, codegen this as a scalar_to_vector, 1639 // then a shuffle that inserts it into the right position in the vector. 1640 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1641 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1642 // match the element type of the vector being created. 1643 if (Tmp2.getValueType() == 1644 Op.getValueType().getVectorElementType()) { 1645 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1646 Tmp1.getValueType(), Tmp2); 1647 1648 unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); 1649 MVT ShufMaskVT = 1650 MVT::getIntVectorWithNumElements(NumElts); 1651 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); 1652 1653 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1654 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1655 // elt 0 of the RHS. 1656 SmallVector<SDValue, 8> ShufOps; 1657 for (unsigned i = 0; i != NumElts; ++i) { 1658 if (i != InsertPos->getZExtValue()) 1659 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1660 else 1661 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1662 } 1663 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1664 &ShufOps[0], ShufOps.size()); 1665 1666 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1667 Tmp1, ScVec, ShufMask); 1668 Result = LegalizeOp(Result); 1669 break; 1670 } 1671 } 1672 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl); 1673 break; 1674 } 1675 } 1676 break; 1677 case ISD::SCALAR_TO_VECTOR: 1678 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1679 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1680 break; 1681 } 1682 1683 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1684 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1685 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1686 Node->getValueType(0))) { 1687 default: assert(0 && "This action is not supported yet!"); 1688 case TargetLowering::Legal: 1689 break; 1690 case TargetLowering::Custom: 1691 Tmp3 = TLI.LowerOperation(Result, DAG); 1692 if (Tmp3.getNode()) { 1693 Result = Tmp3; 1694 break; 1695 } 1696 // FALLTHROUGH 1697 case TargetLowering::Expand: 1698 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1699 break; 1700 } 1701 break; 1702 case ISD::VECTOR_SHUFFLE: 1703 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1704 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1705 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1706 1707 // Allow targets to custom lower the SHUFFLEs they support. 1708 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1709 default: assert(0 && "Unknown operation action!"); 1710 case TargetLowering::Legal: 1711 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1712 "vector shuffle should not be created if not legal!"); 1713 break; 1714 case TargetLowering::Custom: 1715 Tmp3 = TLI.LowerOperation(Result, DAG); 1716 if (Tmp3.getNode()) { 1717 Result = Tmp3; 1718 break; 1719 } 1720 // FALLTHROUGH 1721 case TargetLowering::Expand: { 1722 MVT VT = Node->getValueType(0); 1723 MVT EltVT = VT.getVectorElementType(); 1724 MVT PtrVT = TLI.getPointerTy(); 1725 SDValue Mask = Node->getOperand(2); 1726 unsigned NumElems = Mask.getNumOperands(); 1727 SmallVector<SDValue,8> Ops; 1728 for (unsigned i = 0; i != NumElems; ++i) { 1729 SDValue Arg = Mask.getOperand(i); 1730 if (Arg.getOpcode() == ISD::UNDEF) { 1731 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1732 } else { 1733 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1734 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue(); 1735 if (Idx < NumElems) 1736 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1737 DAG.getConstant(Idx, PtrVT))); 1738 else 1739 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1740 DAG.getConstant(Idx - NumElems, PtrVT))); 1741 } 1742 } 1743 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1744 break; 1745 } 1746 case TargetLowering::Promote: { 1747 // Change base type to a different vector type. 1748 MVT OVT = Node->getValueType(0); 1749 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1750 1751 // Cast the two input vectors. 1752 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1753 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1754 1755 // Convert the shuffle mask to the right # elements. 1756 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1757 assert(Tmp3.getNode() && "Shuffle not legal?"); 1758 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1759 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1760 break; 1761 } 1762 } 1763 break; 1764 1765 case ISD::EXTRACT_VECTOR_ELT: 1766 Tmp1 = Node->getOperand(0); 1767 Tmp2 = LegalizeOp(Node->getOperand(1)); 1768 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1769 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1770 break; 1771 1772 case ISD::EXTRACT_SUBVECTOR: 1773 Tmp1 = Node->getOperand(0); 1774 Tmp2 = LegalizeOp(Node->getOperand(1)); 1775 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1776 Result = ExpandEXTRACT_SUBVECTOR(Result); 1777 break; 1778 1779 case ISD::CONCAT_VECTORS: { 1780 // Use extract/insert/build vector for now. We might try to be 1781 // more clever later. 1782 MVT PtrVT = TLI.getPointerTy(); 1783 SmallVector<SDValue, 8> Ops; 1784 unsigned NumOperands = Node->getNumOperands(); 1785 for (unsigned i=0; i < NumOperands; ++i) { 1786 SDValue SubOp = Node->getOperand(i); 1787 MVT VVT = SubOp.getNode()->getValueType(0); 1788 MVT EltVT = VVT.getVectorElementType(); 1789 unsigned NumSubElem = VVT.getVectorNumElements(); 1790 for (unsigned j=0; j < NumSubElem; ++j) { 1791 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp, 1792 DAG.getConstant(j, PtrVT))); 1793 } 1794 } 1795 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), 1796 &Ops[0], Ops.size())); 1797 } 1798 1799 case ISD::CALLSEQ_START: { 1800 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1801 1802 // Recursively Legalize all of the inputs of the call end that do not lead 1803 // to this call start. This ensures that any libcalls that need be inserted 1804 // are inserted *before* the CALLSEQ_START. 1805 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1806 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1807 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1808 NodesLeadingTo); 1809 } 1810 1811 // Now that we legalized all of the inputs (which may have inserted 1812 // libcalls) create the new CALLSEQ_START node. 1813 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1814 1815 // Merge in the last call, to ensure that this call start after the last 1816 // call ended. 1817 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1818 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1819 Tmp1 = LegalizeOp(Tmp1); 1820 } 1821 1822 // Do not try to legalize the target-specific arguments (#1+). 1823 if (Tmp1 != Node->getOperand(0)) { 1824 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1825 Ops[0] = Tmp1; 1826 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1827 } 1828 1829 // Remember that the CALLSEQ_START is legalized. 1830 AddLegalizedOperand(Op.getValue(0), Result); 1831 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1832 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1833 1834 // Now that the callseq_start and all of the non-call nodes above this call 1835 // sequence have been legalized, legalize the call itself. During this 1836 // process, no libcalls can/will be inserted, guaranteeing that no calls 1837 // can overlap. 1838 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1839 // Note that we are selecting this call! 1840 LastCALLSEQ_END = SDValue(CallEnd, 0); 1841 IsLegalizingCall = true; 1842 1843 // Legalize the call, starting from the CALLSEQ_END. 1844 LegalizeOp(LastCALLSEQ_END); 1845 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1846 return Result; 1847 } 1848 case ISD::CALLSEQ_END: 1849 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1850 // will cause this node to be legalized as well as handling libcalls right. 1851 if (LastCALLSEQ_END.getNode() != Node) { 1852 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1853 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1854 assert(I != LegalizedNodes.end() && 1855 "Legalizing the call start should have legalized this node!"); 1856 return I->second; 1857 } 1858 1859 // Otherwise, the call start has been legalized and everything is going 1860 // according to plan. Just legalize ourselves normally here. 1861 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1862 // Do not try to legalize the target-specific arguments (#1+), except for 1863 // an optional flag input. 1864 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1865 if (Tmp1 != Node->getOperand(0)) { 1866 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1867 Ops[0] = Tmp1; 1868 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1869 } 1870 } else { 1871 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1872 if (Tmp1 != Node->getOperand(0) || 1873 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1874 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1875 Ops[0] = Tmp1; 1876 Ops.back() = Tmp2; 1877 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1878 } 1879 } 1880 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1881 // This finishes up call legalization. 1882 IsLegalizingCall = false; 1883 1884 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1885 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1886 if (Node->getNumValues() == 2) 1887 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1888 return Result.getValue(Op.getResNo()); 1889 case ISD::DYNAMIC_STACKALLOC: { 1890 MVT VT = Node->getValueType(0); 1891 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1892 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1893 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1894 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1895 1896 Tmp1 = Result.getValue(0); 1897 Tmp2 = Result.getValue(1); 1898 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1899 default: assert(0 && "This action is not supported yet!"); 1900 case TargetLowering::Expand: { 1901 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1902 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1903 " not tell us which reg is the stack pointer!"); 1904 SDValue Chain = Tmp1.getOperand(0); 1905 1906 // Chain the dynamic stack allocation so that it doesn't modify the stack 1907 // pointer when other instructions are using the stack. 1908 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1909 1910 SDValue Size = Tmp2.getOperand(1); 1911 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1912 Chain = SP.getValue(1); 1913 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1914 unsigned StackAlign = 1915 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1916 if (Align > StackAlign) 1917 SP = DAG.getNode(ISD::AND, VT, SP, 1918 DAG.getConstant(-(uint64_t)Align, VT)); 1919 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1920 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1921 1922 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1923 DAG.getIntPtrConstant(0, true), SDValue()); 1924 1925 Tmp1 = LegalizeOp(Tmp1); 1926 Tmp2 = LegalizeOp(Tmp2); 1927 break; 1928 } 1929 case TargetLowering::Custom: 1930 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1931 if (Tmp3.getNode()) { 1932 Tmp1 = LegalizeOp(Tmp3); 1933 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1934 } 1935 break; 1936 case TargetLowering::Legal: 1937 break; 1938 } 1939 // Since this op produce two values, make sure to remember that we 1940 // legalized both of them. 1941 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1942 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1943 return Op.getResNo() ? Tmp2 : Tmp1; 1944 } 1945 case ISD::INLINEASM: { 1946 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1947 bool Changed = false; 1948 // Legalize all of the operands of the inline asm, in case they are nodes 1949 // that need to be expanded or something. Note we skip the asm string and 1950 // all of the TargetConstant flags. 1951 SDValue Op = LegalizeOp(Ops[0]); 1952 Changed = Op != Ops[0]; 1953 Ops[0] = Op; 1954 1955 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1956 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1957 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3; 1958 for (++i; NumVals; ++i, --NumVals) { 1959 SDValue Op = LegalizeOp(Ops[i]); 1960 if (Op != Ops[i]) { 1961 Changed = true; 1962 Ops[i] = Op; 1963 } 1964 } 1965 } 1966 1967 if (HasInFlag) { 1968 Op = LegalizeOp(Ops.back()); 1969 Changed |= Op != Ops.back(); 1970 Ops.back() = Op; 1971 } 1972 1973 if (Changed) 1974 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1975 1976 // INLINE asm returns a chain and flag, make sure to add both to the map. 1977 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1978 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1979 return Result.getValue(Op.getResNo()); 1980 } 1981 case ISD::BR: 1982 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1983 // Ensure that libcalls are emitted before a branch. 1984 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1985 Tmp1 = LegalizeOp(Tmp1); 1986 LastCALLSEQ_END = DAG.getEntryNode(); 1987 1988 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1989 break; 1990 case ISD::BRIND: 1991 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1992 // Ensure that libcalls are emitted before a branch. 1993 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1994 Tmp1 = LegalizeOp(Tmp1); 1995 LastCALLSEQ_END = DAG.getEntryNode(); 1996 1997 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1998 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1999 case Legal: 2000 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 2001 break; 2002 } 2003 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2004 break; 2005 case ISD::BR_JT: 2006 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2007 // Ensure that libcalls are emitted before a branch. 2008 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2009 Tmp1 = LegalizeOp(Tmp1); 2010 LastCALLSEQ_END = DAG.getEntryNode(); 2011 2012 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 2013 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2014 2015 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 2016 default: assert(0 && "This action is not supported yet!"); 2017 case TargetLowering::Legal: break; 2018 case TargetLowering::Custom: 2019 Tmp1 = TLI.LowerOperation(Result, DAG); 2020 if (Tmp1.getNode()) Result = Tmp1; 2021 break; 2022 case TargetLowering::Expand: { 2023 SDValue Chain = Result.getOperand(0); 2024 SDValue Table = Result.getOperand(1); 2025 SDValue Index = Result.getOperand(2); 2026 2027 MVT PTy = TLI.getPointerTy(); 2028 MachineFunction &MF = DAG.getMachineFunction(); 2029 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 2030 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 2031 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 2032 2033 MVT MemVT = MVT::getIntegerVT(EntrySize * 8); 2034 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, Chain, Addr, 2035 PseudoSourceValue::getJumpTable(), 0, MemVT); 2036 Addr = LD; 2037 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2038 // For PIC, the sequence is: 2039 // BRIND(load(Jumptable + index) + RelocBase) 2040 // RelocBase can be JumpTable, GOT or some sort of global base. 2041 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 2042 TLI.getPICJumpTableRelocBase(Table, DAG)); 2043 } 2044 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 2045 } 2046 } 2047 break; 2048 case ISD::BRCOND: 2049 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2050 // Ensure that libcalls are emitted before a return. 2051 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2052 Tmp1 = LegalizeOp(Tmp1); 2053 LastCALLSEQ_END = DAG.getEntryNode(); 2054 2055 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2056 case Expand: assert(0 && "It's impossible to expand bools"); 2057 case Legal: 2058 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 2059 break; 2060 case Promote: { 2061 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 2062 2063 // The top bits of the promoted condition are not necessarily zero, ensure 2064 // that the value is properly zero extended. 2065 unsigned BitWidth = Tmp2.getValueSizeInBits(); 2066 if (!DAG.MaskedValueIsZero(Tmp2, 2067 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2068 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 2069 break; 2070 } 2071 } 2072 2073 // Basic block destination (Op#2) is always legal. 2074 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2075 2076 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 2077 default: assert(0 && "This action is not supported yet!"); 2078 case TargetLowering::Legal: break; 2079 case TargetLowering::Custom: 2080 Tmp1 = TLI.LowerOperation(Result, DAG); 2081 if (Tmp1.getNode()) Result = Tmp1; 2082 break; 2083 case TargetLowering::Expand: 2084 // Expand brcond's setcc into its constituent parts and create a BR_CC 2085 // Node. 2086 if (Tmp2.getOpcode() == ISD::SETCC) { 2087 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 2088 Tmp2.getOperand(0), Tmp2.getOperand(1), 2089 Node->getOperand(2)); 2090 } else { 2091 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 2092 DAG.getCondCode(ISD::SETNE), Tmp2, 2093 DAG.getConstant(0, Tmp2.getValueType()), 2094 Node->getOperand(2)); 2095 } 2096 break; 2097 } 2098 break; 2099 case ISD::BR_CC: 2100 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2101 // Ensure that libcalls are emitted before a branch. 2102 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2103 Tmp1 = LegalizeOp(Tmp1); 2104 Tmp2 = Node->getOperand(2); // LHS 2105 Tmp3 = Node->getOperand(3); // RHS 2106 Tmp4 = Node->getOperand(1); // CC 2107 2108 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()), 2109 Tmp2, Tmp3, Tmp4, dl); 2110 LastCALLSEQ_END = DAG.getEntryNode(); 2111 2112 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 2113 // the LHS is a legal SETCC itself. In this case, we need to compare 2114 // the result against zero to select between true and false values. 2115 if (Tmp3.getNode() == 0) { 2116 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 2117 Tmp4 = DAG.getCondCode(ISD::SETNE); 2118 } 2119 2120 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 2121 Node->getOperand(4)); 2122 2123 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 2124 default: assert(0 && "Unexpected action for BR_CC!"); 2125 case TargetLowering::Legal: break; 2126 case TargetLowering::Custom: 2127 Tmp4 = TLI.LowerOperation(Result, DAG); 2128 if (Tmp4.getNode()) Result = Tmp4; 2129 break; 2130 } 2131 break; 2132 case ISD::LOAD: { 2133 LoadSDNode *LD = cast<LoadSDNode>(Node); 2134 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 2135 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 2136 2137 ISD::LoadExtType ExtType = LD->getExtensionType(); 2138 if (ExtType == ISD::NON_EXTLOAD) { 2139 MVT VT = Node->getValueType(0); 2140 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2141 Tmp3 = Result.getValue(0); 2142 Tmp4 = Result.getValue(1); 2143 2144 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 2145 default: assert(0 && "This action is not supported yet!"); 2146 case TargetLowering::Legal: 2147 // If this is an unaligned load and the target doesn't support it, 2148 // expand it. 2149 if (!TLI.allowsUnalignedMemoryAccesses()) { 2150 unsigned ABIAlignment = TLI.getTargetData()-> 2151 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2152 if (LD->getAlignment() < ABIAlignment){ 2153 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 2154 TLI); 2155 Tmp3 = Result.getOperand(0); 2156 Tmp4 = Result.getOperand(1); 2157 Tmp3 = LegalizeOp(Tmp3); 2158 Tmp4 = LegalizeOp(Tmp4); 2159 } 2160 } 2161 break; 2162 case TargetLowering::Custom: 2163 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 2164 if (Tmp1.getNode()) { 2165 Tmp3 = LegalizeOp(Tmp1); 2166 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 2167 } 2168 break; 2169 case TargetLowering::Promote: { 2170 // Only promote a load of vector type to another. 2171 assert(VT.isVector() && "Cannot promote this load!"); 2172 // Change base type to a different vector type. 2173 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 2174 2175 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 2176 LD->getSrcValueOffset(), 2177 LD->isVolatile(), LD->getAlignment()); 2178 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 2179 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 2180 break; 2181 } 2182 } 2183 // Since loads produce two values, make sure to remember that we 2184 // legalized both of them. 2185 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 2186 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 2187 return Op.getResNo() ? Tmp4 : Tmp3; 2188 } else { 2189 MVT SrcVT = LD->getMemoryVT(); 2190 unsigned SrcWidth = SrcVT.getSizeInBits(); 2191 int SVOffset = LD->getSrcValueOffset(); 2192 unsigned Alignment = LD->getAlignment(); 2193 bool isVolatile = LD->isVolatile(); 2194 2195 if (SrcWidth != SrcVT.getStoreSizeInBits() && 2196 // Some targets pretend to have an i1 loading operation, and actually 2197 // load an i8. This trick is correct for ZEXTLOAD because the top 7 2198 // bits are guaranteed to be zero; it helps the optimizers understand 2199 // that these bits are zero. It is also useful for EXTLOAD, since it 2200 // tells the optimizers that those bits are undefined. It would be 2201 // nice to have an effective generic way of getting these benefits... 2202 // Until such a way is found, don't insist on promoting i1 here. 2203 (SrcVT != MVT::i1 || 2204 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 2205 // Promote to a byte-sized load if not loading an integral number of 2206 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 2207 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 2208 MVT NVT = MVT::getIntegerVT(NewWidth); 2209 SDValue Ch; 2210 2211 // The extra bits are guaranteed to be zero, since we stored them that 2212 // way. A zext load from NVT thus automatically gives zext from SrcVT. 2213 2214 ISD::LoadExtType NewExtType = 2215 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2216 2217 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 2218 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2219 NVT, isVolatile, Alignment); 2220 2221 Ch = Result.getValue(1); // The chain. 2222 2223 if (ExtType == ISD::SEXTLOAD) 2224 // Having the top bits zero doesn't help when sign extending. 2225 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2226 Result, DAG.getValueType(SrcVT)); 2227 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2228 // All the top bits are guaranteed to be zero - inform the optimizers. 2229 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 2230 DAG.getValueType(SrcVT)); 2231 2232 Tmp1 = LegalizeOp(Result); 2233 Tmp2 = LegalizeOp(Ch); 2234 } else if (SrcWidth & (SrcWidth - 1)) { 2235 // If not loading a power-of-2 number of bits, expand as two loads. 2236 assert(SrcVT.isExtended() && !SrcVT.isVector() && 2237 "Unsupported extload!"); 2238 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2239 assert(RoundWidth < SrcWidth); 2240 unsigned ExtraWidth = SrcWidth - RoundWidth; 2241 assert(ExtraWidth < RoundWidth); 2242 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2243 "Load size not an integral number of bytes!"); 2244 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2245 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2246 SDValue Lo, Hi, Ch; 2247 unsigned IncrementSize; 2248 2249 if (TLI.isLittleEndian()) { 2250 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2251 // Load the bottom RoundWidth bits. 2252 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2253 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2254 Alignment); 2255 2256 // Load the remaining ExtraWidth bits. 2257 IncrementSize = RoundWidth / 8; 2258 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2259 DAG.getIntPtrConstant(IncrementSize)); 2260 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2261 LD->getSrcValue(), SVOffset + IncrementSize, 2262 ExtraVT, isVolatile, 2263 MinAlign(Alignment, IncrementSize)); 2264 2265 // Build a factor node to remember that this load is independent of the 2266 // other one. 2267 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2268 Hi.getValue(1)); 2269 2270 // Move the top bits to the right place. 2271 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2272 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2273 2274 // Join the hi and lo parts. 2275 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2276 } else { 2277 // Big endian - avoid unaligned loads. 2278 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2279 // Load the top RoundWidth bits. 2280 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2281 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2282 Alignment); 2283 2284 // Load the remaining ExtraWidth bits. 2285 IncrementSize = RoundWidth / 8; 2286 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2287 DAG.getIntPtrConstant(IncrementSize)); 2288 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2289 LD->getSrcValue(), SVOffset + IncrementSize, 2290 ExtraVT, isVolatile, 2291 MinAlign(Alignment, IncrementSize)); 2292 2293 // Build a factor node to remember that this load is independent of the 2294 // other one. 2295 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2296 Hi.getValue(1)); 2297 2298 // Move the top bits to the right place. 2299 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2300 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2301 2302 // Join the hi and lo parts. 2303 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2304 } 2305 2306 Tmp1 = LegalizeOp(Result); 2307 Tmp2 = LegalizeOp(Ch); 2308 } else { 2309 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 2310 default: assert(0 && "This action is not supported yet!"); 2311 case TargetLowering::Custom: 2312 isCustom = true; 2313 // FALLTHROUGH 2314 case TargetLowering::Legal: 2315 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2316 Tmp1 = Result.getValue(0); 2317 Tmp2 = Result.getValue(1); 2318 2319 if (isCustom) { 2320 Tmp3 = TLI.LowerOperation(Result, DAG); 2321 if (Tmp3.getNode()) { 2322 Tmp1 = LegalizeOp(Tmp3); 2323 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2324 } 2325 } else { 2326 // If this is an unaligned load and the target doesn't support it, 2327 // expand it. 2328 if (!TLI.allowsUnalignedMemoryAccesses()) { 2329 unsigned ABIAlignment = TLI.getTargetData()-> 2330 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2331 if (LD->getAlignment() < ABIAlignment){ 2332 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 2333 TLI); 2334 Tmp1 = Result.getOperand(0); 2335 Tmp2 = Result.getOperand(1); 2336 Tmp1 = LegalizeOp(Tmp1); 2337 Tmp2 = LegalizeOp(Tmp2); 2338 } 2339 } 2340 } 2341 break; 2342 case TargetLowering::Expand: 2343 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2344 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2345 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2346 LD->getSrcValueOffset(), 2347 LD->isVolatile(), LD->getAlignment()); 2348 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2349 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2350 Tmp2 = LegalizeOp(Load.getValue(1)); 2351 break; 2352 } 2353 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2354 // Turn the unsupported load into an EXTLOAD followed by an explicit 2355 // zero/sign extend inreg. 2356 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2357 Tmp1, Tmp2, LD->getSrcValue(), 2358 LD->getSrcValueOffset(), SrcVT, 2359 LD->isVolatile(), LD->getAlignment()); 2360 SDValue ValRes; 2361 if (ExtType == ISD::SEXTLOAD) 2362 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2363 Result, DAG.getValueType(SrcVT)); 2364 else 2365 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2366 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2367 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2368 break; 2369 } 2370 } 2371 2372 // Since loads produce two values, make sure to remember that we legalized 2373 // both of them. 2374 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2375 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2376 return Op.getResNo() ? Tmp2 : Tmp1; 2377 } 2378 } 2379 case ISD::EXTRACT_ELEMENT: { 2380 MVT OpTy = Node->getOperand(0).getValueType(); 2381 switch (getTypeAction(OpTy)) { 2382 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2383 case Legal: 2384 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2385 // 1 -> Hi 2386 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2387 DAG.getConstant(OpTy.getSizeInBits()/2, 2388 TLI.getShiftAmountTy())); 2389 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2390 } else { 2391 // 0 -> Lo 2392 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2393 Node->getOperand(0)); 2394 } 2395 break; 2396 case Expand: 2397 // Get both the low and high parts. 2398 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2399 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) 2400 Result = Tmp2; // 1 -> Hi 2401 else 2402 Result = Tmp1; // 0 -> Lo 2403 break; 2404 } 2405 break; 2406 } 2407 2408 case ISD::CopyToReg: 2409 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2410 2411 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2412 "Register type must be legal!"); 2413 // Legalize the incoming value (must be a legal type). 2414 Tmp2 = LegalizeOp(Node->getOperand(2)); 2415 if (Node->getNumValues() == 1) { 2416 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2417 } else { 2418 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2419 if (Node->getNumOperands() == 4) { 2420 Tmp3 = LegalizeOp(Node->getOperand(3)); 2421 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2422 Tmp3); 2423 } else { 2424 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2425 } 2426 2427 // Since this produces two values, make sure to remember that we legalized 2428 // both of them. 2429 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 2430 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 2431 return Result; 2432 } 2433 break; 2434 2435 case ISD::RET: 2436 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2437 2438 // Ensure that libcalls are emitted before a return. 2439 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2440 Tmp1 = LegalizeOp(Tmp1); 2441 LastCALLSEQ_END = DAG.getEntryNode(); 2442 2443 switch (Node->getNumOperands()) { 2444 case 3: // ret val 2445 Tmp2 = Node->getOperand(1); 2446 Tmp3 = Node->getOperand(2); // Signness 2447 switch (getTypeAction(Tmp2.getValueType())) { 2448 case Legal: 2449 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2450 break; 2451 case Expand: 2452 if (!Tmp2.getValueType().isVector()) { 2453 SDValue Lo, Hi; 2454 ExpandOp(Tmp2, Lo, Hi); 2455 2456 // Big endian systems want the hi reg first. 2457 if (TLI.isBigEndian()) 2458 std::swap(Lo, Hi); 2459 2460 if (Hi.getNode()) 2461 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2462 else 2463 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2464 Result = LegalizeOp(Result); 2465 } else { 2466 SDNode *InVal = Tmp2.getNode(); 2467 int InIx = Tmp2.getResNo(); 2468 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 2469 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 2470 2471 // Figure out if there is a simple type corresponding to this Vector 2472 // type. If so, convert to the vector type. 2473 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2474 if (TLI.isTypeLegal(TVT)) { 2475 // Turn this into a return of the vector type. 2476 Tmp2 = LegalizeOp(Tmp2); 2477 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2478 } else if (NumElems == 1) { 2479 // Turn this into a return of the scalar type. 2480 Tmp2 = ScalarizeVectorOp(Tmp2); 2481 Tmp2 = LegalizeOp(Tmp2); 2482 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2483 2484 // FIXME: Returns of gcc generic vectors smaller than a legal type 2485 // should be returned in integer registers! 2486 2487 // The scalarized value type may not be legal, e.g. it might require 2488 // promotion or expansion. Relegalize the return. 2489 Result = LegalizeOp(Result); 2490 } else { 2491 // FIXME: Returns of gcc generic vectors larger than a legal vector 2492 // type should be returned by reference! 2493 SDValue Lo, Hi; 2494 SplitVectorOp(Tmp2, Lo, Hi); 2495 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2496 Result = LegalizeOp(Result); 2497 } 2498 } 2499 break; 2500 case Promote: 2501 Tmp2 = PromoteOp(Node->getOperand(1)); 2502 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2503 Result = LegalizeOp(Result); 2504 break; 2505 } 2506 break; 2507 case 1: // ret void 2508 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2509 break; 2510 default: { // ret <values> 2511 SmallVector<SDValue, 8> NewValues; 2512 NewValues.push_back(Tmp1); 2513 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2514 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2515 case Legal: 2516 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2517 NewValues.push_back(Node->getOperand(i+1)); 2518 break; 2519 case Expand: { 2520 SDValue Lo, Hi; 2521 assert(!Node->getOperand(i).getValueType().isExtended() && 2522 "FIXME: TODO: implement returning non-legal vector types!"); 2523 ExpandOp(Node->getOperand(i), Lo, Hi); 2524 NewValues.push_back(Lo); 2525 NewValues.push_back(Node->getOperand(i+1)); 2526 if (Hi.getNode()) { 2527 NewValues.push_back(Hi); 2528 NewValues.push_back(Node->getOperand(i+1)); 2529 } 2530 break; 2531 } 2532 case Promote: 2533 assert(0 && "Can't promote multiple return value yet!"); 2534 } 2535 2536 if (NewValues.size() == Node->getNumOperands()) 2537 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2538 else 2539 Result = DAG.getNode(ISD::RET, MVT::Other, 2540 &NewValues[0], NewValues.size()); 2541 break; 2542 } 2543 } 2544 2545 if (Result.getOpcode() == ISD::RET) { 2546 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2547 default: assert(0 && "This action is not supported yet!"); 2548 case TargetLowering::Legal: break; 2549 case TargetLowering::Custom: 2550 Tmp1 = TLI.LowerOperation(Result, DAG); 2551 if (Tmp1.getNode()) Result = Tmp1; 2552 break; 2553 } 2554 } 2555 break; 2556 case ISD::STORE: { 2557 StoreSDNode *ST = cast<StoreSDNode>(Node); 2558 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2559 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2560 int SVOffset = ST->getSrcValueOffset(); 2561 unsigned Alignment = ST->getAlignment(); 2562 bool isVolatile = ST->isVolatile(); 2563 2564 if (!ST->isTruncatingStore()) { 2565 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2566 // FIXME: We shouldn't do this for TargetConstantFP's. 2567 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2568 // to phase ordering between legalized code and the dag combiner. This 2569 // probably means that we need to integrate dag combiner and legalizer 2570 // together. 2571 // We generally can't do this one for long doubles. 2572 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2573 if (CFP->getValueType(0) == MVT::f32 && 2574 getTypeAction(MVT::i32) == Legal) { 2575 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2576 bitcastToAPInt().zextOrTrunc(32), 2577 MVT::i32); 2578 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2579 SVOffset, isVolatile, Alignment); 2580 break; 2581 } else if (CFP->getValueType(0) == MVT::f64) { 2582 // If this target supports 64-bit registers, do a single 64-bit store. 2583 if (getTypeAction(MVT::i64) == Legal) { 2584 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 2585 zextOrTrunc(64), MVT::i64); 2586 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2587 SVOffset, isVolatile, Alignment); 2588 break; 2589 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 2590 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2591 // stores. If the target supports neither 32- nor 64-bits, this 2592 // xform is certainly not worth it. 2593 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 2594 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2595 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2596 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2597 2598 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2599 SVOffset, isVolatile, Alignment); 2600 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2601 DAG.getIntPtrConstant(4)); 2602 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2603 isVolatile, MinAlign(Alignment, 4U)); 2604 2605 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2606 break; 2607 } 2608 } 2609 } 2610 2611 switch (getTypeAction(ST->getMemoryVT())) { 2612 case Legal: { 2613 Tmp3 = LegalizeOp(ST->getValue()); 2614 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2615 ST->getOffset()); 2616 2617 MVT VT = Tmp3.getValueType(); 2618 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2619 default: assert(0 && "This action is not supported yet!"); 2620 case TargetLowering::Legal: 2621 // If this is an unaligned store and the target doesn't support it, 2622 // expand it. 2623 if (!TLI.allowsUnalignedMemoryAccesses()) { 2624 unsigned ABIAlignment = TLI.getTargetData()-> 2625 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2626 if (ST->getAlignment() < ABIAlignment) 2627 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 2628 TLI); 2629 } 2630 break; 2631 case TargetLowering::Custom: 2632 Tmp1 = TLI.LowerOperation(Result, DAG); 2633 if (Tmp1.getNode()) Result = Tmp1; 2634 break; 2635 case TargetLowering::Promote: 2636 assert(VT.isVector() && "Unknown legal promote case!"); 2637 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2638 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2639 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2640 ST->getSrcValue(), SVOffset, isVolatile, 2641 Alignment); 2642 break; 2643 } 2644 break; 2645 } 2646 case Promote: 2647 if (!ST->getMemoryVT().isVector()) { 2648 // Truncate the value and store the result. 2649 Tmp3 = PromoteOp(ST->getValue()); 2650 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2651 SVOffset, ST->getMemoryVT(), 2652 isVolatile, Alignment); 2653 break; 2654 } 2655 // Fall thru to expand for vector 2656 case Expand: { 2657 unsigned IncrementSize = 0; 2658 SDValue Lo, Hi; 2659 2660 // If this is a vector type, then we have to calculate the increment as 2661 // the product of the element size in bytes, and the number of elements 2662 // in the high half of the vector. 2663 if (ST->getValue().getValueType().isVector()) { 2664 SDNode *InVal = ST->getValue().getNode(); 2665 int InIx = ST->getValue().getResNo(); 2666 MVT InVT = InVal->getValueType(InIx); 2667 unsigned NumElems = InVT.getVectorNumElements(); 2668 MVT EVT = InVT.getVectorElementType(); 2669 2670 // Figure out if there is a simple type corresponding to this Vector 2671 // type. If so, convert to the vector type. 2672 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2673 if (TLI.isTypeLegal(TVT)) { 2674 // Turn this into a normal store of the vector type. 2675 Tmp3 = LegalizeOp(ST->getValue()); 2676 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2677 SVOffset, isVolatile, Alignment); 2678 Result = LegalizeOp(Result); 2679 break; 2680 } else if (NumElems == 1) { 2681 // Turn this into a normal store of the scalar type. 2682 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2683 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2684 SVOffset, isVolatile, Alignment); 2685 // The scalarized value type may not be legal, e.g. it might require 2686 // promotion or expansion. Relegalize the scalar store. 2687 Result = LegalizeOp(Result); 2688 break; 2689 } else { 2690 // Check if we have widen this node with another value 2691 std::map<SDValue, SDValue>::iterator I = 2692 WidenNodes.find(ST->getValue()); 2693 if (I != WidenNodes.end()) { 2694 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2); 2695 break; 2696 } 2697 else { 2698 SplitVectorOp(ST->getValue(), Lo, Hi); 2699 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() * 2700 EVT.getSizeInBits()/8; 2701 } 2702 } 2703 } else { 2704 ExpandOp(ST->getValue(), Lo, Hi); 2705 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0; 2706 2707 if (Hi.getNode() && TLI.isBigEndian()) 2708 std::swap(Lo, Hi); 2709 } 2710 2711 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2712 SVOffset, isVolatile, Alignment); 2713 2714 if (Hi.getNode() == NULL) { 2715 // Must be int <-> float one-to-one expansion. 2716 Result = Lo; 2717 break; 2718 } 2719 2720 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2721 DAG.getIntPtrConstant(IncrementSize)); 2722 assert(isTypeLegal(Tmp2.getValueType()) && 2723 "Pointers must be legal!"); 2724 SVOffset += IncrementSize; 2725 Alignment = MinAlign(Alignment, IncrementSize); 2726 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2727 SVOffset, isVolatile, Alignment); 2728 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2729 break; 2730 } // case Expand 2731 } 2732 } else { 2733 switch (getTypeAction(ST->getValue().getValueType())) { 2734 case Legal: 2735 Tmp3 = LegalizeOp(ST->getValue()); 2736 break; 2737 case Promote: 2738 if (!ST->getValue().getValueType().isVector()) { 2739 // We can promote the value, the truncstore will still take care of it. 2740 Tmp3 = PromoteOp(ST->getValue()); 2741 break; 2742 } 2743 // Vector case falls through to expand 2744 case Expand: 2745 // Just store the low part. This may become a non-trunc store, so make 2746 // sure to use getTruncStore, not UpdateNodeOperands below. 2747 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2748 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2749 SVOffset, MVT::i8, isVolatile, Alignment); 2750 } 2751 2752 MVT StVT = ST->getMemoryVT(); 2753 unsigned StWidth = StVT.getSizeInBits(); 2754 2755 if (StWidth != StVT.getStoreSizeInBits()) { 2756 // Promote to a byte-sized store with upper bits zero if not 2757 // storing an integral number of bytes. For example, promote 2758 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2759 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 2760 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2761 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2762 SVOffset, NVT, isVolatile, Alignment); 2763 } else if (StWidth & (StWidth - 1)) { 2764 // If not storing a power-of-2 number of bits, expand as two stores. 2765 assert(StVT.isExtended() && !StVT.isVector() && 2766 "Unsupported truncstore!"); 2767 unsigned RoundWidth = 1 << Log2_32(StWidth); 2768 assert(RoundWidth < StWidth); 2769 unsigned ExtraWidth = StWidth - RoundWidth; 2770 assert(ExtraWidth < RoundWidth); 2771 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2772 "Store size not an integral number of bytes!"); 2773 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2774 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2775 SDValue Lo, Hi; 2776 unsigned IncrementSize; 2777 2778 if (TLI.isLittleEndian()) { 2779 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2780 // Store the bottom RoundWidth bits. 2781 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2782 SVOffset, RoundVT, 2783 isVolatile, Alignment); 2784 2785 // Store the remaining ExtraWidth bits. 2786 IncrementSize = RoundWidth / 8; 2787 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2788 DAG.getIntPtrConstant(IncrementSize)); 2789 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2790 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2791 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2792 SVOffset + IncrementSize, ExtraVT, isVolatile, 2793 MinAlign(Alignment, IncrementSize)); 2794 } else { 2795 // Big endian - avoid unaligned stores. 2796 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2797 // Store the top RoundWidth bits. 2798 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2799 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2800 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2801 RoundVT, isVolatile, Alignment); 2802 2803 // Store the remaining ExtraWidth bits. 2804 IncrementSize = RoundWidth / 8; 2805 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2806 DAG.getIntPtrConstant(IncrementSize)); 2807 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2808 SVOffset + IncrementSize, ExtraVT, isVolatile, 2809 MinAlign(Alignment, IncrementSize)); 2810 } 2811 2812 // The order of the stores doesn't matter. 2813 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2814 } else { 2815 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2816 Tmp2 != ST->getBasePtr()) 2817 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2818 ST->getOffset()); 2819 2820 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2821 default: assert(0 && "This action is not supported yet!"); 2822 case TargetLowering::Legal: 2823 // If this is an unaligned store and the target doesn't support it, 2824 // expand it. 2825 if (!TLI.allowsUnalignedMemoryAccesses()) { 2826 unsigned ABIAlignment = TLI.getTargetData()-> 2827 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2828 if (ST->getAlignment() < ABIAlignment) 2829 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 2830 TLI); 2831 } 2832 break; 2833 case TargetLowering::Custom: 2834 Result = TLI.LowerOperation(Result, DAG); 2835 break; 2836 case Expand: 2837 // TRUNCSTORE:i16 i32 -> STORE i16 2838 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2839 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2840 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2841 isVolatile, Alignment); 2842 break; 2843 } 2844 } 2845 } 2846 break; 2847 } 2848 case ISD::PCMARKER: 2849 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2850 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2851 break; 2852 case ISD::STACKSAVE: 2853 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2854 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2855 Tmp1 = Result.getValue(0); 2856 Tmp2 = Result.getValue(1); 2857 2858 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2859 default: assert(0 && "This action is not supported yet!"); 2860 case TargetLowering::Legal: break; 2861 case TargetLowering::Custom: 2862 Tmp3 = TLI.LowerOperation(Result, DAG); 2863 if (Tmp3.getNode()) { 2864 Tmp1 = LegalizeOp(Tmp3); 2865 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2866 } 2867 break; 2868 case TargetLowering::Expand: 2869 // Expand to CopyFromReg if the target set 2870 // StackPointerRegisterToSaveRestore. 2871 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2872 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2873 Node->getValueType(0)); 2874 Tmp2 = Tmp1.getValue(1); 2875 } else { 2876 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2877 Tmp2 = Node->getOperand(0); 2878 } 2879 break; 2880 } 2881 2882 // Since stacksave produce two values, make sure to remember that we 2883 // legalized both of them. 2884 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2885 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2886 return Op.getResNo() ? Tmp2 : Tmp1; 2887 2888 case ISD::STACKRESTORE: 2889 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2890 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2891 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2892 2893 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2894 default: assert(0 && "This action is not supported yet!"); 2895 case TargetLowering::Legal: break; 2896 case TargetLowering::Custom: 2897 Tmp1 = TLI.LowerOperation(Result, DAG); 2898 if (Tmp1.getNode()) Result = Tmp1; 2899 break; 2900 case TargetLowering::Expand: 2901 // Expand to CopyToReg if the target set 2902 // StackPointerRegisterToSaveRestore. 2903 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2904 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2905 } else { 2906 Result = Tmp1; 2907 } 2908 break; 2909 } 2910 break; 2911 2912 case ISD::READCYCLECOUNTER: 2913 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2914 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2915 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2916 Node->getValueType(0))) { 2917 default: assert(0 && "This action is not supported yet!"); 2918 case TargetLowering::Legal: 2919 Tmp1 = Result.getValue(0); 2920 Tmp2 = Result.getValue(1); 2921 break; 2922 case TargetLowering::Custom: 2923 Result = TLI.LowerOperation(Result, DAG); 2924 Tmp1 = LegalizeOp(Result.getValue(0)); 2925 Tmp2 = LegalizeOp(Result.getValue(1)); 2926 break; 2927 } 2928 2929 // Since rdcc produce two values, make sure to remember that we legalized 2930 // both of them. 2931 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2932 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2933 return Result; 2934 2935 case ISD::SELECT: 2936 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2937 case Expand: assert(0 && "It's impossible to expand bools"); 2938 case Legal: 2939 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2940 break; 2941 case Promote: { 2942 assert(!Node->getOperand(0).getValueType().isVector() && "not possible"); 2943 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2944 // Make sure the condition is either zero or one. 2945 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2946 if (!DAG.MaskedValueIsZero(Tmp1, 2947 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2948 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2949 break; 2950 } 2951 } 2952 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2953 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2954 2955 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2956 2957 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2958 default: assert(0 && "This action is not supported yet!"); 2959 case TargetLowering::Legal: break; 2960 case TargetLowering::Custom: { 2961 Tmp1 = TLI.LowerOperation(Result, DAG); 2962 if (Tmp1.getNode()) Result = Tmp1; 2963 break; 2964 } 2965 case TargetLowering::Expand: 2966 if (Tmp1.getOpcode() == ISD::SETCC) { 2967 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2968 Tmp2, Tmp3, 2969 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2970 } else { 2971 Result = DAG.getSelectCC(Tmp1, 2972 DAG.getConstant(0, Tmp1.getValueType()), 2973 Tmp2, Tmp3, ISD::SETNE); 2974 } 2975 break; 2976 case TargetLowering::Promote: { 2977 MVT NVT = 2978 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2979 unsigned ExtOp, TruncOp; 2980 if (Tmp2.getValueType().isVector()) { 2981 ExtOp = ISD::BIT_CONVERT; 2982 TruncOp = ISD::BIT_CONVERT; 2983 } else if (Tmp2.getValueType().isInteger()) { 2984 ExtOp = ISD::ANY_EXTEND; 2985 TruncOp = ISD::TRUNCATE; 2986 } else { 2987 ExtOp = ISD::FP_EXTEND; 2988 TruncOp = ISD::FP_ROUND; 2989 } 2990 // Promote each of the values to the new type. 2991 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2992 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2993 // Perform the larger operation, then round down. 2994 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2995 if (TruncOp != ISD::FP_ROUND) 2996 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2997 else 2998 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2999 DAG.getIntPtrConstant(0)); 3000 break; 3001 } 3002 } 3003 break; 3004 case ISD::SELECT_CC: { 3005 Tmp1 = Node->getOperand(0); // LHS 3006 Tmp2 = Node->getOperand(1); // RHS 3007 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 3008 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 3009 SDValue CC = Node->getOperand(4); 3010 3011 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), 3012 Tmp1, Tmp2, CC, dl); 3013 3014 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 3015 // the LHS is a legal SETCC itself. In this case, we need to compare 3016 // the result against zero to select between true and false values. 3017 if (Tmp2.getNode() == 0) { 3018 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3019 CC = DAG.getCondCode(ISD::SETNE); 3020 } 3021 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 3022 3023 // Everything is legal, see if we should expand this op or something. 3024 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 3025 default: assert(0 && "This action is not supported yet!"); 3026 case TargetLowering::Legal: break; 3027 case TargetLowering::Custom: 3028 Tmp1 = TLI.LowerOperation(Result, DAG); 3029 if (Tmp1.getNode()) Result = Tmp1; 3030 break; 3031 } 3032 break; 3033 } 3034 case ISD::SETCC: 3035 Tmp1 = Node->getOperand(0); 3036 Tmp2 = Node->getOperand(1); 3037 Tmp3 = Node->getOperand(2); 3038 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 3039 3040 // If we had to Expand the SetCC operands into a SELECT node, then it may 3041 // not always be possible to return a true LHS & RHS. In this case, just 3042 // return the value we legalized, returned in the LHS 3043 if (Tmp2.getNode() == 0) { 3044 Result = Tmp1; 3045 break; 3046 } 3047 3048 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 3049 default: assert(0 && "Cannot handle this action for SETCC yet!"); 3050 case TargetLowering::Custom: 3051 isCustom = true; 3052 // FALLTHROUGH. 3053 case TargetLowering::Legal: 3054 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3055 if (isCustom) { 3056 Tmp4 = TLI.LowerOperation(Result, DAG); 3057 if (Tmp4.getNode()) Result = Tmp4; 3058 } 3059 break; 3060 case TargetLowering::Promote: { 3061 // First step, figure out the appropriate operation to use. 3062 // Allow SETCC to not be supported for all legal data types 3063 // Mostly this targets FP 3064 MVT NewInTy = Node->getOperand(0).getValueType(); 3065 MVT OldVT = NewInTy; OldVT = OldVT; 3066 3067 // Scan for the appropriate larger type to use. 3068 while (1) { 3069 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 3070 3071 assert(NewInTy.isInteger() == OldVT.isInteger() && 3072 "Fell off of the edge of the integer world"); 3073 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 3074 "Fell off of the edge of the floating point world"); 3075 3076 // If the target supports SETCC of this type, use it. 3077 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy)) 3078 break; 3079 } 3080 if (NewInTy.isInteger()) 3081 assert(0 && "Cannot promote Legal Integer SETCC yet"); 3082 else { 3083 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 3084 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 3085 } 3086 Tmp1 = LegalizeOp(Tmp1); 3087 Tmp2 = LegalizeOp(Tmp2); 3088 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3089 Result = LegalizeOp(Result); 3090 break; 3091 } 3092 case TargetLowering::Expand: 3093 // Expand a setcc node into a select_cc of the same condition, lhs, and 3094 // rhs that selects between const 1 (true) and const 0 (false). 3095 MVT VT = Node->getValueType(0); 3096 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 3097 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3098 Tmp3); 3099 break; 3100 } 3101 break; 3102 case ISD::VSETCC: { 3103 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3104 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3105 SDValue CC = Node->getOperand(2); 3106 3107 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC); 3108 3109 // Everything is legal, see if we should expand this op or something. 3110 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) { 3111 default: assert(0 && "This action is not supported yet!"); 3112 case TargetLowering::Legal: break; 3113 case TargetLowering::Custom: 3114 Tmp1 = TLI.LowerOperation(Result, DAG); 3115 if (Tmp1.getNode()) Result = Tmp1; 3116 break; 3117 case TargetLowering::Expand: { 3118 // Unroll into a nasty set of scalar code for now. 3119 MVT VT = Node->getValueType(0); 3120 unsigned NumElems = VT.getVectorNumElements(); 3121 MVT EltVT = VT.getVectorElementType(); 3122 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType(); 3123 SmallVector<SDValue, 8> Ops(NumElems); 3124 for (unsigned i = 0; i < NumElems; ++i) { 3125 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT, 3126 Tmp1, DAG.getIntPtrConstant(i)); 3127 Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(TmpEltVT), In1, 3128 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT, 3129 Tmp2, DAG.getIntPtrConstant(i)), 3130 CC); 3131 Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i], DAG.getConstant( 3132 APInt::getAllOnesValue(EltVT.getSizeInBits()), 3133 EltVT), DAG.getConstant(0, EltVT)); 3134 } 3135 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems); 3136 break; 3137 } 3138 } 3139 break; 3140 } 3141 3142 case ISD::SHL_PARTS: 3143 case ISD::SRA_PARTS: 3144 case ISD::SRL_PARTS: { 3145 SmallVector<SDValue, 8> Ops; 3146 bool Changed = false; 3147 unsigned N = Node->getNumOperands(); 3148 for (unsigned i = 0; i + 1 < N; ++i) { 3149 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3150 Changed |= Ops.back() != Node->getOperand(i); 3151 } 3152 Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1)))); 3153 Changed |= Ops.back() != Node->getOperand(N-1); 3154 if (Changed) 3155 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 3156 3157 switch (TLI.getOperationAction(Node->getOpcode(), 3158 Node->getValueType(0))) { 3159 default: assert(0 && "This action is not supported yet!"); 3160 case TargetLowering::Legal: break; 3161 case TargetLowering::Custom: 3162 Tmp1 = TLI.LowerOperation(Result, DAG); 3163 if (Tmp1.getNode()) { 3164 SDValue Tmp2, RetVal(0, 0); 3165 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 3166 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 3167 AddLegalizedOperand(SDValue(Node, i), Tmp2); 3168 if (i == Op.getResNo()) 3169 RetVal = Tmp2; 3170 } 3171 assert(RetVal.getNode() && "Illegal result number"); 3172 return RetVal; 3173 } 3174 break; 3175 } 3176 3177 // Since these produce multiple values, make sure to remember that we 3178 // legalized all of them. 3179 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3180 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i)); 3181 return Result.getValue(Op.getResNo()); 3182 } 3183 3184 // Binary operators 3185 case ISD::ADD: 3186 case ISD::SUB: 3187 case ISD::MUL: 3188 case ISD::MULHS: 3189 case ISD::MULHU: 3190 case ISD::UDIV: 3191 case ISD::SDIV: 3192 case ISD::AND: 3193 case ISD::OR: 3194 case ISD::XOR: 3195 case ISD::SHL: 3196 case ISD::SRL: 3197 case ISD::SRA: 3198 case ISD::FADD: 3199 case ISD::FSUB: 3200 case ISD::FMUL: 3201 case ISD::FDIV: 3202 case ISD::FPOW: 3203 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3204 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3205 3206 if ((Node->getOpcode() == ISD::SHL || 3207 Node->getOpcode() == ISD::SRL || 3208 Node->getOpcode() == ISD::SRA) && 3209 !Node->getValueType(0).isVector()) 3210 Tmp2 = DAG.getShiftAmountOperand(Tmp2); 3211 3212 switch (getTypeAction(Tmp2.getValueType())) { 3213 case Expand: assert(0 && "Not possible"); 3214 case Legal: 3215 Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS. 3216 break; 3217 case Promote: 3218 Tmp2 = PromoteOp(Tmp2); // Promote the RHS. 3219 break; 3220 } 3221 3222 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3223 3224 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3225 default: assert(0 && "BinOp legalize operation not supported"); 3226 case TargetLowering::Legal: break; 3227 case TargetLowering::Custom: 3228 Tmp1 = TLI.LowerOperation(Result, DAG); 3229 if (Tmp1.getNode()) { 3230 Result = Tmp1; 3231 break; 3232 } 3233 // Fall through if the custom lower can't deal with the operation 3234 case TargetLowering::Expand: { 3235 MVT VT = Op.getValueType(); 3236 3237 // See if multiply or divide can be lowered using two-result operations. 3238 SDVTList VTs = DAG.getVTList(VT, VT); 3239 if (Node->getOpcode() == ISD::MUL) { 3240 // We just need the low half of the multiply; try both the signed 3241 // and unsigned forms. If the target supports both SMUL_LOHI and 3242 // UMUL_LOHI, form a preference by checking which forms of plain 3243 // MULH it supports. 3244 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 3245 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 3246 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 3247 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 3248 unsigned OpToUse = 0; 3249 if (HasSMUL_LOHI && !HasMULHS) { 3250 OpToUse = ISD::SMUL_LOHI; 3251 } else if (HasUMUL_LOHI && !HasMULHU) { 3252 OpToUse = ISD::UMUL_LOHI; 3253 } else if (HasSMUL_LOHI) { 3254 OpToUse = ISD::SMUL_LOHI; 3255 } else if (HasUMUL_LOHI) { 3256 OpToUse = ISD::UMUL_LOHI; 3257 } 3258 if (OpToUse) { 3259 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0); 3260 break; 3261 } 3262 } 3263 if (Node->getOpcode() == ISD::MULHS && 3264 TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) { 3265 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 3266 1); 3267 break; 3268 } 3269 if (Node->getOpcode() == ISD::MULHU && 3270 TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) { 3271 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 3272 1); 3273 break; 3274 } 3275 if (Node->getOpcode() == ISD::SDIV && 3276 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) { 3277 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 3278 0); 3279 break; 3280 } 3281 if (Node->getOpcode() == ISD::UDIV && 3282 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) { 3283 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 3284 0); 3285 break; 3286 } 3287 3288 // Check to see if we have a libcall for this operator. 3289 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3290 bool isSigned = false; 3291 switch (Node->getOpcode()) { 3292 case ISD::UDIV: 3293 case ISD::SDIV: 3294 if (VT == MVT::i32) { 3295 LC = Node->getOpcode() == ISD::UDIV 3296 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3297 isSigned = Node->getOpcode() == ISD::SDIV; 3298 } 3299 break; 3300 case ISD::MUL: 3301 if (VT == MVT::i32) 3302 LC = RTLIB::MUL_I32; 3303 else if (VT == MVT::i64) 3304 LC = RTLIB::MUL_I64; 3305 break; 3306 case ISD::FPOW: 3307 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3308 RTLIB::POW_PPCF128); 3309 break; 3310 case ISD::FDIV: 3311 LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80, 3312 RTLIB::DIV_PPCF128); 3313 break; 3314 default: break; 3315 } 3316 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3317 SDValue Dummy; 3318 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3319 break; 3320 } 3321 3322 assert(Node->getValueType(0).isVector() && 3323 "Cannot expand this binary operator!"); 3324 // Expand the operation into a bunch of nasty scalar code. 3325 Result = LegalizeOp(UnrollVectorOp(Op)); 3326 break; 3327 } 3328 case TargetLowering::Promote: { 3329 switch (Node->getOpcode()) { 3330 default: assert(0 && "Do not know how to promote this BinOp!"); 3331 case ISD::AND: 3332 case ISD::OR: 3333 case ISD::XOR: { 3334 MVT OVT = Node->getValueType(0); 3335 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3336 assert(OVT.isVector() && "Cannot promote this BinOp!"); 3337 // Bit convert each of the values to the new type. 3338 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3339 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3340 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3341 // Bit convert the result back the original type. 3342 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3343 break; 3344 } 3345 } 3346 } 3347 } 3348 break; 3349 3350 case ISD::SMUL_LOHI: 3351 case ISD::UMUL_LOHI: 3352 case ISD::SDIVREM: 3353 case ISD::UDIVREM: 3354 // These nodes will only be produced by target-specific lowering, so 3355 // they shouldn't be here if they aren't legal. 3356 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3357 "This must be legal!"); 3358 3359 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3360 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3361 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3362 break; 3363 3364 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3365 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3366 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3367 case Expand: assert(0 && "Not possible"); 3368 case Legal: 3369 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3370 break; 3371 case Promote: 3372 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3373 break; 3374 } 3375 3376 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3377 3378 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3379 default: assert(0 && "Operation not supported"); 3380 case TargetLowering::Custom: 3381 Tmp1 = TLI.LowerOperation(Result, DAG); 3382 if (Tmp1.getNode()) Result = Tmp1; 3383 break; 3384 case TargetLowering::Legal: break; 3385 case TargetLowering::Expand: { 3386 // If this target supports fabs/fneg natively and select is cheap, 3387 // do this efficiently. 3388 if (!TLI.isSelectExpensive() && 3389 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3390 TargetLowering::Legal && 3391 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3392 TargetLowering::Legal) { 3393 // Get the sign bit of the RHS. 3394 MVT IVT = 3395 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3396 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3397 SignBit = DAG.getSetCC(TLI.getSetCCResultType(IVT), 3398 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3399 // Get the absolute value of the result. 3400 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3401 // Select between the nabs and abs value based on the sign bit of 3402 // the input. 3403 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3404 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3405 AbsVal), 3406 AbsVal); 3407 Result = LegalizeOp(Result); 3408 break; 3409 } 3410 3411 // Otherwise, do bitwise ops! 3412 MVT NVT = 3413 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3414 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3415 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3416 Result = LegalizeOp(Result); 3417 break; 3418 } 3419 } 3420 break; 3421 3422 case ISD::ADDC: 3423 case ISD::SUBC: 3424 Tmp1 = LegalizeOp(Node->getOperand(0)); 3425 Tmp2 = LegalizeOp(Node->getOperand(1)); 3426 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3427 Tmp3 = Result.getValue(0); 3428 Tmp4 = Result.getValue(1); 3429 3430 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3431 default: assert(0 && "This action is not supported yet!"); 3432 case TargetLowering::Legal: 3433 break; 3434 case TargetLowering::Custom: 3435 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 3436 if (Tmp1.getNode() != NULL) { 3437 Tmp3 = LegalizeOp(Tmp1); 3438 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 3439 } 3440 break; 3441 } 3442 // Since this produces two values, make sure to remember that we legalized 3443 // both of them. 3444 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 3445 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 3446 return Op.getResNo() ? Tmp4 : Tmp3; 3447 3448 case ISD::ADDE: 3449 case ISD::SUBE: 3450 Tmp1 = LegalizeOp(Node->getOperand(0)); 3451 Tmp2 = LegalizeOp(Node->getOperand(1)); 3452 Tmp3 = LegalizeOp(Node->getOperand(2)); 3453 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3454 Tmp3 = Result.getValue(0); 3455 Tmp4 = Result.getValue(1); 3456 3457 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3458 default: assert(0 && "This action is not supported yet!"); 3459 case TargetLowering::Legal: 3460 break; 3461 case TargetLowering::Custom: 3462 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 3463 if (Tmp1.getNode() != NULL) { 3464 Tmp3 = LegalizeOp(Tmp1); 3465 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 3466 } 3467 break; 3468 } 3469 // Since this produces two values, make sure to remember that we legalized 3470 // both of them. 3471 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 3472 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 3473 return Op.getResNo() ? Tmp4 : Tmp3; 3474 3475 case ISD::BUILD_PAIR: { 3476 MVT PairTy = Node->getValueType(0); 3477 // TODO: handle the case where the Lo and Hi operands are not of legal type 3478 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3479 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3480 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3481 case TargetLowering::Promote: 3482 case TargetLowering::Custom: 3483 assert(0 && "Cannot promote/custom this yet!"); 3484 case TargetLowering::Legal: 3485 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3486 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3487 break; 3488 case TargetLowering::Expand: 3489 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3490 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3491 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3492 DAG.getConstant(PairTy.getSizeInBits()/2, 3493 TLI.getShiftAmountTy())); 3494 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3495 break; 3496 } 3497 break; 3498 } 3499 3500 case ISD::UREM: 3501 case ISD::SREM: 3502 case ISD::FREM: 3503 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3504 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3505 3506 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3507 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3508 case TargetLowering::Custom: 3509 isCustom = true; 3510 // FALLTHROUGH 3511 case TargetLowering::Legal: 3512 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3513 if (isCustom) { 3514 Tmp1 = TLI.LowerOperation(Result, DAG); 3515 if (Tmp1.getNode()) Result = Tmp1; 3516 } 3517 break; 3518 case TargetLowering::Expand: { 3519 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3520 bool isSigned = DivOpc == ISD::SDIV; 3521 MVT VT = Node->getValueType(0); 3522 3523 // See if remainder can be lowered using two-result operations. 3524 SDVTList VTs = DAG.getVTList(VT, VT); 3525 if (Node->getOpcode() == ISD::SREM && 3526 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) { 3527 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1); 3528 break; 3529 } 3530 if (Node->getOpcode() == ISD::UREM && 3531 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) { 3532 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1); 3533 break; 3534 } 3535 3536 if (VT.isInteger()) { 3537 if (TLI.getOperationAction(DivOpc, VT) == 3538 TargetLowering::Legal) { 3539 // X % Y -> X-X/Y*Y 3540 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3541 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3542 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3543 } else if (VT.isVector()) { 3544 Result = LegalizeOp(UnrollVectorOp(Op)); 3545 } else { 3546 assert(VT == MVT::i32 && 3547 "Cannot expand this binary operator!"); 3548 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3549 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3550 SDValue Dummy; 3551 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3552 } 3553 } else { 3554 assert(VT.isFloatingPoint() && 3555 "remainder op must have integer or floating-point type"); 3556 if (VT.isVector()) { 3557 Result = LegalizeOp(UnrollVectorOp(Op)); 3558 } else { 3559 // Floating point mod -> fmod libcall. 3560 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3561 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3562 SDValue Dummy; 3563 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3564 } 3565 } 3566 break; 3567 } 3568 } 3569 break; 3570 case ISD::VAARG: { 3571 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3572 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3573 3574 MVT VT = Node->getValueType(0); 3575 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3576 default: assert(0 && "This action is not supported yet!"); 3577 case TargetLowering::Custom: 3578 isCustom = true; 3579 // FALLTHROUGH 3580 case TargetLowering::Legal: 3581 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3582 Result = Result.getValue(0); 3583 Tmp1 = Result.getValue(1); 3584 3585 if (isCustom) { 3586 Tmp2 = TLI.LowerOperation(Result, DAG); 3587 if (Tmp2.getNode()) { 3588 Result = LegalizeOp(Tmp2); 3589 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3590 } 3591 } 3592 break; 3593 case TargetLowering::Expand: { 3594 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3595 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3596 // Increment the pointer, VAList, to the next vaarg 3597 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3598 DAG.getConstant(TLI.getTargetData()-> 3599 getTypePaddedSize(VT.getTypeForMVT()), 3600 TLI.getPointerTy())); 3601 // Store the incremented VAList to the legalized pointer 3602 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3603 // Load the actual argument out of the pointer VAList 3604 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3605 Tmp1 = LegalizeOp(Result.getValue(1)); 3606 Result = LegalizeOp(Result); 3607 break; 3608 } 3609 } 3610 // Since VAARG produces two values, make sure to remember that we 3611 // legalized both of them. 3612 AddLegalizedOperand(SDValue(Node, 0), Result); 3613 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 3614 return Op.getResNo() ? Tmp1 : Result; 3615 } 3616 3617 case ISD::VACOPY: 3618 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3619 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3620 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3621 3622 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3623 default: assert(0 && "This action is not supported yet!"); 3624 case TargetLowering::Custom: 3625 isCustom = true; 3626 // FALLTHROUGH 3627 case TargetLowering::Legal: 3628 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3629 Node->getOperand(3), Node->getOperand(4)); 3630 if (isCustom) { 3631 Tmp1 = TLI.LowerOperation(Result, DAG); 3632 if (Tmp1.getNode()) Result = Tmp1; 3633 } 3634 break; 3635 case TargetLowering::Expand: 3636 // This defaults to loading a pointer from the input and storing it to the 3637 // output, returning the chain. 3638 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3639 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3640 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0); 3641 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0); 3642 break; 3643 } 3644 break; 3645 3646 case ISD::VAEND: 3647 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3648 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3649 3650 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3651 default: assert(0 && "This action is not supported yet!"); 3652 case TargetLowering::Custom: 3653 isCustom = true; 3654 // FALLTHROUGH 3655 case TargetLowering::Legal: 3656 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3657 if (isCustom) { 3658 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3659 if (Tmp1.getNode()) Result = Tmp1; 3660 } 3661 break; 3662 case TargetLowering::Expand: 3663 Result = Tmp1; // Default to a no-op, return the chain 3664 break; 3665 } 3666 break; 3667 3668 case ISD::VASTART: 3669 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3670 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3671 3672 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3673 3674 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3675 default: assert(0 && "This action is not supported yet!"); 3676 case TargetLowering::Legal: break; 3677 case TargetLowering::Custom: 3678 Tmp1 = TLI.LowerOperation(Result, DAG); 3679 if (Tmp1.getNode()) Result = Tmp1; 3680 break; 3681 } 3682 break; 3683 3684 case ISD::ROTL: 3685 case ISD::ROTR: 3686 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3687 Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS 3688 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3689 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3690 default: 3691 assert(0 && "ROTL/ROTR legalize operation not supported"); 3692 break; 3693 case TargetLowering::Legal: 3694 break; 3695 case TargetLowering::Custom: 3696 Tmp1 = TLI.LowerOperation(Result, DAG); 3697 if (Tmp1.getNode()) Result = Tmp1; 3698 break; 3699 case TargetLowering::Promote: 3700 assert(0 && "Do not know how to promote ROTL/ROTR"); 3701 break; 3702 case TargetLowering::Expand: 3703 assert(0 && "Do not know how to expand ROTL/ROTR"); 3704 break; 3705 } 3706 break; 3707 3708 case ISD::BSWAP: 3709 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3710 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3711 case TargetLowering::Custom: 3712 assert(0 && "Cannot custom legalize this yet!"); 3713 case TargetLowering::Legal: 3714 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3715 break; 3716 case TargetLowering::Promote: { 3717 MVT OVT = Tmp1.getValueType(); 3718 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3719 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3720 3721 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3722 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3723 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3724 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3725 break; 3726 } 3727 case TargetLowering::Expand: 3728 Result = ExpandBSWAP(Tmp1); 3729 break; 3730 } 3731 break; 3732 3733 case ISD::CTPOP: 3734 case ISD::CTTZ: 3735 case ISD::CTLZ: 3736 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3737 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3738 case TargetLowering::Custom: 3739 case TargetLowering::Legal: 3740 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3741 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3742 TargetLowering::Custom) { 3743 Tmp1 = TLI.LowerOperation(Result, DAG); 3744 if (Tmp1.getNode()) { 3745 Result = Tmp1; 3746 } 3747 } 3748 break; 3749 case TargetLowering::Promote: { 3750 MVT OVT = Tmp1.getValueType(); 3751 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3752 3753 // Zero extend the argument. 3754 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3755 // Perform the larger operation, then subtract if needed. 3756 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3757 switch (Node->getOpcode()) { 3758 case ISD::CTPOP: 3759 Result = Tmp1; 3760 break; 3761 case ISD::CTTZ: 3762 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3763 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, 3764 DAG.getConstant(NVT.getSizeInBits(), NVT), 3765 ISD::SETEQ); 3766 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3767 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3768 break; 3769 case ISD::CTLZ: 3770 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3771 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3772 DAG.getConstant(NVT.getSizeInBits() - 3773 OVT.getSizeInBits(), NVT)); 3774 break; 3775 } 3776 break; 3777 } 3778 case TargetLowering::Expand: 3779 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3780 break; 3781 } 3782 break; 3783 3784 // Unary operators 3785 case ISD::FABS: 3786 case ISD::FNEG: 3787 case ISD::FSQRT: 3788 case ISD::FSIN: 3789 case ISD::FCOS: 3790 case ISD::FLOG: 3791 case ISD::FLOG2: 3792 case ISD::FLOG10: 3793 case ISD::FEXP: 3794 case ISD::FEXP2: 3795 case ISD::FTRUNC: 3796 case ISD::FFLOOR: 3797 case ISD::FCEIL: 3798 case ISD::FRINT: 3799 case ISD::FNEARBYINT: 3800 Tmp1 = LegalizeOp(Node->getOperand(0)); 3801 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3802 case TargetLowering::Promote: 3803 case TargetLowering::Custom: 3804 isCustom = true; 3805 // FALLTHROUGH 3806 case TargetLowering::Legal: 3807 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3808 if (isCustom) { 3809 Tmp1 = TLI.LowerOperation(Result, DAG); 3810 if (Tmp1.getNode()) Result = Tmp1; 3811 } 3812 break; 3813 case TargetLowering::Expand: 3814 switch (Node->getOpcode()) { 3815 default: assert(0 && "Unreachable!"); 3816 case ISD::FNEG: 3817 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3818 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3819 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3820 break; 3821 case ISD::FABS: { 3822 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3823 MVT VT = Node->getValueType(0); 3824 Tmp2 = DAG.getConstantFP(0.0, VT); 3825 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), 3826 Tmp1, Tmp2, ISD::SETUGT); 3827 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3828 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3829 break; 3830 } 3831 case ISD::FSQRT: 3832 case ISD::FSIN: 3833 case ISD::FCOS: 3834 case ISD::FLOG: 3835 case ISD::FLOG2: 3836 case ISD::FLOG10: 3837 case ISD::FEXP: 3838 case ISD::FEXP2: 3839 case ISD::FTRUNC: 3840 case ISD::FFLOOR: 3841 case ISD::FCEIL: 3842 case ISD::FRINT: 3843 case ISD::FNEARBYINT: { 3844 MVT VT = Node->getValueType(0); 3845 3846 // Expand unsupported unary vector operators by unrolling them. 3847 if (VT.isVector()) { 3848 Result = LegalizeOp(UnrollVectorOp(Op)); 3849 break; 3850 } 3851 3852 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3853 switch(Node->getOpcode()) { 3854 case ISD::FSQRT: 3855 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3856 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3857 break; 3858 case ISD::FSIN: 3859 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3860 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3861 break; 3862 case ISD::FCOS: 3863 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3864 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3865 break; 3866 case ISD::FLOG: 3867 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64, 3868 RTLIB::LOG_F80, RTLIB::LOG_PPCF128); 3869 break; 3870 case ISD::FLOG2: 3871 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 3872 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128); 3873 break; 3874 case ISD::FLOG10: 3875 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 3876 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128); 3877 break; 3878 case ISD::FEXP: 3879 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64, 3880 RTLIB::EXP_F80, RTLIB::EXP_PPCF128); 3881 break; 3882 case ISD::FEXP2: 3883 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 3884 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128); 3885 break; 3886 case ISD::FTRUNC: 3887 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 3888 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 3889 break; 3890 case ISD::FFLOOR: 3891 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 3892 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 3893 break; 3894 case ISD::FCEIL: 3895 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 3896 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 3897 break; 3898 case ISD::FRINT: 3899 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 3900 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 3901 break; 3902 case ISD::FNEARBYINT: 3903 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 3904 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 3905 break; 3906 break; 3907 default: assert(0 && "Unreachable!"); 3908 } 3909 SDValue Dummy; 3910 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3911 break; 3912 } 3913 } 3914 break; 3915 } 3916 break; 3917 case ISD::FPOWI: { 3918 MVT VT = Node->getValueType(0); 3919 3920 // Expand unsupported unary vector operators by unrolling them. 3921 if (VT.isVector()) { 3922 Result = LegalizeOp(UnrollVectorOp(Op)); 3923 break; 3924 } 3925 3926 // We always lower FPOWI into a libcall. No target support for it yet. 3927 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3928 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3929 SDValue Dummy; 3930 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3931 break; 3932 } 3933 case ISD::BIT_CONVERT: 3934 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3935 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3936 Node->getValueType(0)); 3937 } else if (Op.getOperand(0).getValueType().isVector()) { 3938 // The input has to be a vector type, we have to either scalarize it, pack 3939 // it, or convert it based on whether the input vector type is legal. 3940 SDNode *InVal = Node->getOperand(0).getNode(); 3941 int InIx = Node->getOperand(0).getResNo(); 3942 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 3943 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 3944 3945 // Figure out if there is a simple type corresponding to this Vector 3946 // type. If so, convert to the vector type. 3947 MVT TVT = MVT::getVectorVT(EVT, NumElems); 3948 if (TLI.isTypeLegal(TVT)) { 3949 // Turn this into a bit convert of the vector input. 3950 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3951 LegalizeOp(Node->getOperand(0))); 3952 break; 3953 } else if (NumElems == 1) { 3954 // Turn this into a bit convert of the scalar input. 3955 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3956 ScalarizeVectorOp(Node->getOperand(0))); 3957 break; 3958 } else { 3959 // FIXME: UNIMP! Store then reload 3960 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3961 } 3962 } else { 3963 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3964 Node->getOperand(0).getValueType())) { 3965 default: assert(0 && "Unknown operation action!"); 3966 case TargetLowering::Expand: 3967 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3968 Node->getValueType(0)); 3969 break; 3970 case TargetLowering::Legal: 3971 Tmp1 = LegalizeOp(Node->getOperand(0)); 3972 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3973 break; 3974 } 3975 } 3976 break; 3977 case ISD::CONVERT_RNDSAT: { 3978 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 3979 switch (CvtCode) { 3980 default: assert(0 && "Unknown cvt code!"); 3981 case ISD::CVT_SF: 3982 case ISD::CVT_UF: 3983 case ISD::CVT_FF: 3984 break; 3985 case ISD::CVT_FS: 3986 case ISD::CVT_FU: 3987 case ISD::CVT_SS: 3988 case ISD::CVT_SU: 3989 case ISD::CVT_US: 3990 case ISD::CVT_UU: { 3991 SDValue DTyOp = Node->getOperand(1); 3992 SDValue STyOp = Node->getOperand(2); 3993 SDValue RndOp = Node->getOperand(3); 3994 SDValue SatOp = Node->getOperand(4); 3995 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3996 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3997 case Legal: 3998 Tmp1 = LegalizeOp(Node->getOperand(0)); 3999 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp, 4000 RndOp, SatOp); 4001 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 4002 TargetLowering::Custom) { 4003 Tmp1 = TLI.LowerOperation(Result, DAG); 4004 if (Tmp1.getNode()) Result = Tmp1; 4005 } 4006 break; 4007 case Promote: 4008 Result = PromoteOp(Node->getOperand(0)); 4009 // For FP, make Op1 a i32 4010 4011 Result = DAG.getConvertRndSat(Op.getValueType(), Result, 4012 DTyOp, STyOp, RndOp, SatOp, CvtCode); 4013 break; 4014 } 4015 break; 4016 } 4017 } // end switch CvtCode 4018 break; 4019 } 4020 // Conversion operators. The source and destination have different types. 4021 case ISD::SINT_TO_FP: 4022 case ISD::UINT_TO_FP: { 4023 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 4024 Result = LegalizeINT_TO_FP(Result, isSigned, 4025 Node->getValueType(0), Node->getOperand(0), dl); 4026 break; 4027 } 4028 case ISD::TRUNCATE: 4029 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4030 case Legal: 4031 Tmp1 = LegalizeOp(Node->getOperand(0)); 4032 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 4033 default: assert(0 && "Unknown TRUNCATE legalization operation action!"); 4034 case TargetLowering::Custom: 4035 isCustom = true; 4036 // FALLTHROUGH 4037 case TargetLowering::Legal: 4038 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4039 if (isCustom) { 4040 Tmp1 = TLI.LowerOperation(Result, DAG); 4041 if (Tmp1.getNode()) Result = Tmp1; 4042 } 4043 break; 4044 case TargetLowering::Expand: 4045 assert(Result.getValueType().isVector() && "must be vector type"); 4046 // Unroll the truncate. We should do better. 4047 Result = LegalizeOp(UnrollVectorOp(Result)); 4048 } 4049 break; 4050 case Expand: 4051 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4052 4053 // Since the result is legal, we should just be able to truncate the low 4054 // part of the source. 4055 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 4056 break; 4057 case Promote: 4058 Result = PromoteOp(Node->getOperand(0)); 4059 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 4060 break; 4061 } 4062 break; 4063 4064 case ISD::FP_TO_SINT: 4065 case ISD::FP_TO_UINT: 4066 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4067 case Legal: 4068 Tmp1 = LegalizeOp(Node->getOperand(0)); 4069 4070 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 4071 default: assert(0 && "Unknown operation action!"); 4072 case TargetLowering::Custom: 4073 isCustom = true; 4074 // FALLTHROUGH 4075 case TargetLowering::Legal: 4076 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4077 if (isCustom) { 4078 Tmp1 = TLI.LowerOperation(Result, DAG); 4079 if (Tmp1.getNode()) Result = Tmp1; 4080 } 4081 break; 4082 case TargetLowering::Promote: 4083 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 4084 Node->getOpcode() == ISD::FP_TO_SINT, 4085 dl); 4086 break; 4087 case TargetLowering::Expand: 4088 if (Node->getOpcode() == ISD::FP_TO_UINT) { 4089 SDValue True, False; 4090 MVT VT = Node->getOperand(0).getValueType(); 4091 MVT NVT = Node->getValueType(0); 4092 const uint64_t zero[] = {0, 0}; 4093 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 4094 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 4095 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 4096 Tmp2 = DAG.getConstantFP(apf, VT); 4097 Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 4098 Node->getOperand(0), 4099 Tmp2, ISD::SETLT); 4100 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 4101 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 4102 DAG.getNode(ISD::FSUB, dl, VT, 4103 Node->getOperand(0), Tmp2)); 4104 False = DAG.getNode(ISD::XOR, dl, NVT, False, 4105 DAG.getConstant(x, NVT)); 4106 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False); 4107 break; 4108 } else { 4109 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 4110 } 4111 break; 4112 } 4113 break; 4114 case Expand: { 4115 MVT VT = Op.getValueType(); 4116 MVT OVT = Node->getOperand(0).getValueType(); 4117 // Convert ppcf128 to i32 4118 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 4119 if (Node->getOpcode() == ISD::FP_TO_SINT) { 4120 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128, 4121 Node->getOperand(0), DAG.getValueType(MVT::f64)); 4122 Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result, 4123 DAG.getIntPtrConstant(1)); 4124 Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result); 4125 } else { 4126 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 4127 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 4128 Tmp2 = DAG.getConstantFP(apf, OVT); 4129 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 4130 // FIXME: generated code sucks. 4131 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0), 4132 Tmp2, 4133 DAG.getNode(ISD::ADD, dl, MVT::i32, 4134 DAG.getNode(ISD::FP_TO_SINT, dl, VT, 4135 DAG.getNode(ISD::FSUB, dl, OVT, 4136 Node->getOperand(0), Tmp2)), 4137 DAG.getConstant(0x80000000, MVT::i32)), 4138 DAG.getNode(ISD::FP_TO_SINT, dl, VT, 4139 Node->getOperand(0)), 4140 DAG.getCondCode(ISD::SETGE)); 4141 } 4142 break; 4143 } 4144 // Convert f32 / f64 to i32 / i64 / i128. 4145 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ? 4146 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT); 4147 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!"); 4148 SDValue Dummy; 4149 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 4150 break; 4151 } 4152 case Promote: 4153 Tmp1 = PromoteOp(Node->getOperand(0)); 4154 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 4155 Result = LegalizeOp(Result); 4156 break; 4157 } 4158 break; 4159 4160 case ISD::FP_EXTEND: { 4161 MVT DstVT = Op.getValueType(); 4162 MVT SrcVT = Op.getOperand(0).getValueType(); 4163 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 4164 // The only other way we can lower this is to turn it into a STORE, 4165 // LOAD pair, targetting a temporary location (a stack slot). 4166 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 4167 break; 4168 } 4169 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4170 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4171 case Legal: 4172 Tmp1 = LegalizeOp(Node->getOperand(0)); 4173 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4174 break; 4175 case Promote: 4176 Tmp1 = PromoteOp(Node->getOperand(0)); 4177 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 4178 break; 4179 } 4180 break; 4181 } 4182 case ISD::FP_ROUND: { 4183 MVT DstVT = Op.getValueType(); 4184 MVT SrcVT = Op.getOperand(0).getValueType(); 4185 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 4186 if (SrcVT == MVT::ppcf128) { 4187 SDValue Lo; 4188 ExpandOp(Node->getOperand(0), Lo, Result); 4189 // Round it the rest of the way (e.g. to f32) if needed. 4190 if (DstVT!=MVT::f64) 4191 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 4192 break; 4193 } 4194 // The only other way we can lower this is to turn it into a STORE, 4195 // LOAD pair, targetting a temporary location (a stack slot). 4196 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 4197 break; 4198 } 4199 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4200 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4201 case Legal: 4202 Tmp1 = LegalizeOp(Node->getOperand(0)); 4203 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 4204 break; 4205 case Promote: 4206 Tmp1 = PromoteOp(Node->getOperand(0)); 4207 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 4208 Node->getOperand(1)); 4209 break; 4210 } 4211 break; 4212 } 4213 case ISD::ANY_EXTEND: 4214 case ISD::ZERO_EXTEND: 4215 case ISD::SIGN_EXTEND: 4216 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4217 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4218 case Legal: 4219 Tmp1 = LegalizeOp(Node->getOperand(0)); 4220 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4221 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 4222 TargetLowering::Custom) { 4223 Tmp1 = TLI.LowerOperation(Result, DAG); 4224 if (Tmp1.getNode()) Result = Tmp1; 4225 } 4226 break; 4227 case Promote: 4228 switch (Node->getOpcode()) { 4229 case ISD::ANY_EXTEND: 4230 Tmp1 = PromoteOp(Node->getOperand(0)); 4231 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 4232 break; 4233 case ISD::ZERO_EXTEND: 4234 Result = PromoteOp(Node->getOperand(0)); 4235 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 4236 Result = DAG.getZeroExtendInReg(Result, 4237 Node->getOperand(0).getValueType()); 4238 break; 4239 case ISD::SIGN_EXTEND: 4240 Result = PromoteOp(Node->getOperand(0)); 4241 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 4242 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4243 Result, 4244 DAG.getValueType(Node->getOperand(0).getValueType())); 4245 break; 4246 } 4247 } 4248 break; 4249 case ISD::FP_ROUND_INREG: 4250 case ISD::SIGN_EXTEND_INREG: { 4251 Tmp1 = LegalizeOp(Node->getOperand(0)); 4252 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 4253 4254 // If this operation is not supported, convert it to a shl/shr or load/store 4255 // pair. 4256 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 4257 default: assert(0 && "This action not supported for this op yet!"); 4258 case TargetLowering::Legal: 4259 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 4260 break; 4261 case TargetLowering::Expand: 4262 // If this is an integer extend and shifts are supported, do that. 4263 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 4264 // NOTE: we could fall back on load/store here too for targets without 4265 // SAR. However, it is doubtful that any exist. 4266 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 4267 ExtraVT.getSizeInBits(); 4268 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 4269 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 4270 Node->getOperand(0), ShiftCst); 4271 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 4272 Result, ShiftCst); 4273 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 4274 // The only way we can lower this is to turn it into a TRUNCSTORE, 4275 // EXTLOAD pair, targetting a temporary location (a stack slot). 4276 4277 // NOTE: there is a choice here between constantly creating new stack 4278 // slots and always reusing the same one. We currently always create 4279 // new ones, as reuse may inhibit scheduling. 4280 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 4281 Node->getValueType(0)); 4282 } else { 4283 assert(0 && "Unknown op"); 4284 } 4285 break; 4286 } 4287 break; 4288 } 4289 case ISD::TRAMPOLINE: { 4290 SDValue Ops[6]; 4291 for (unsigned i = 0; i != 6; ++i) 4292 Ops[i] = LegalizeOp(Node->getOperand(i)); 4293 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 4294 // The only option for this node is to custom lower it. 4295 Result = TLI.LowerOperation(Result, DAG); 4296 assert(Result.getNode() && "Should always custom lower!"); 4297 4298 // Since trampoline produces two values, make sure to remember that we 4299 // legalized both of them. 4300 Tmp1 = LegalizeOp(Result.getValue(1)); 4301 Result = LegalizeOp(Result); 4302 AddLegalizedOperand(SDValue(Node, 0), Result); 4303 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 4304 return Op.getResNo() ? Tmp1 : Result; 4305 } 4306 case ISD::FLT_ROUNDS_: { 4307 MVT VT = Node->getValueType(0); 4308 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4309 default: assert(0 && "This action not supported for this op yet!"); 4310 case TargetLowering::Custom: 4311 Result = TLI.LowerOperation(Op, DAG); 4312 if (Result.getNode()) break; 4313 // Fall Thru 4314 case TargetLowering::Legal: 4315 // If this operation is not supported, lower it to constant 1 4316 Result = DAG.getConstant(1, VT); 4317 break; 4318 } 4319 break; 4320 } 4321 case ISD::TRAP: { 4322 MVT VT = Node->getValueType(0); 4323 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4324 default: assert(0 && "This action not supported for this op yet!"); 4325 case TargetLowering::Legal: 4326 Tmp1 = LegalizeOp(Node->getOperand(0)); 4327 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4328 break; 4329 case TargetLowering::Custom: 4330 Result = TLI.LowerOperation(Op, DAG); 4331 if (Result.getNode()) break; 4332 // Fall Thru 4333 case TargetLowering::Expand: 4334 // If this operation is not supported, lower it to 'abort()' call 4335 Tmp1 = LegalizeOp(Node->getOperand(0)); 4336 TargetLowering::ArgListTy Args; 4337 std::pair<SDValue,SDValue> CallResult = 4338 TLI.LowerCallTo(Tmp1, Type::VoidTy, 4339 false, false, false, false, CallingConv::C, false, 4340 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 4341 Args, DAG, dl); 4342 Result = CallResult.second; 4343 break; 4344 } 4345 break; 4346 } 4347 4348 case ISD::SADDO: 4349 case ISD::SSUBO: { 4350 MVT VT = Node->getValueType(0); 4351 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4352 default: assert(0 && "This action not supported for this op yet!"); 4353 case TargetLowering::Custom: 4354 Result = TLI.LowerOperation(Op, DAG); 4355 if (Result.getNode()) break; 4356 // FALLTHROUGH 4357 case TargetLowering::Legal: { 4358 SDValue LHS = LegalizeOp(Node->getOperand(0)); 4359 SDValue RHS = LegalizeOp(Node->getOperand(1)); 4360 4361 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 4362 ISD::ADD : ISD::SUB, LHS.getValueType(), 4363 LHS, RHS); 4364 MVT OType = Node->getValueType(1); 4365 4366 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 4367 4368 // LHSSign -> LHS >= 0 4369 // RHSSign -> RHS >= 0 4370 // SumSign -> Sum >= 0 4371 // 4372 // Add: 4373 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 4374 // Sub: 4375 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 4376 // 4377 SDValue LHSSign = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE); 4378 SDValue RHSSign = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE); 4379 SDValue SignsMatch = DAG.getSetCC(OType, LHSSign, RHSSign, 4380 Node->getOpcode() == ISD::SADDO ? 4381 ISD::SETEQ : ISD::SETNE); 4382 4383 SDValue SumSign = DAG.getSetCC(OType, Sum, Zero, ISD::SETGE); 4384 SDValue SumSignNE = DAG.getSetCC(OType, LHSSign, SumSign, ISD::SETNE); 4385 4386 SDValue Cmp = DAG.getNode(ISD::AND, OType, SignsMatch, SumSignNE); 4387 4388 MVT ValueVTs[] = { LHS.getValueType(), OType }; 4389 SDValue Ops[] = { Sum, Cmp }; 4390 4391 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2), 4392 &Ops[0], 2); 4393 SDNode *RNode = Result.getNode(); 4394 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0)); 4395 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1)); 4396 break; 4397 } 4398 } 4399 4400 break; 4401 } 4402 case ISD::UADDO: 4403 case ISD::USUBO: { 4404 MVT VT = Node->getValueType(0); 4405 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4406 default: assert(0 && "This action not supported for this op yet!"); 4407 case TargetLowering::Custom: 4408 Result = TLI.LowerOperation(Op, DAG); 4409 if (Result.getNode()) break; 4410 // FALLTHROUGH 4411 case TargetLowering::Legal: { 4412 SDValue LHS = LegalizeOp(Node->getOperand(0)); 4413 SDValue RHS = LegalizeOp(Node->getOperand(1)); 4414 4415 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 4416 ISD::ADD : ISD::SUB, LHS.getValueType(), 4417 LHS, RHS); 4418 MVT OType = Node->getValueType(1); 4419 SDValue Cmp = DAG.getSetCC(OType, Sum, LHS, 4420 Node->getOpcode () == ISD::UADDO ? 4421 ISD::SETULT : ISD::SETUGT); 4422 4423 MVT ValueVTs[] = { LHS.getValueType(), OType }; 4424 SDValue Ops[] = { Sum, Cmp }; 4425 4426 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2), 4427 &Ops[0], 2); 4428 SDNode *RNode = Result.getNode(); 4429 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0)); 4430 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1)); 4431 break; 4432 } 4433 } 4434 4435 break; 4436 } 4437 case ISD::SMULO: 4438 case ISD::UMULO: { 4439 MVT VT = Node->getValueType(0); 4440 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4441 default: assert(0 && "This action is not supported at all!"); 4442 case TargetLowering::Custom: 4443 Result = TLI.LowerOperation(Op, DAG); 4444 if (Result.getNode()) break; 4445 // Fall Thru 4446 case TargetLowering::Legal: 4447 // FIXME: According to Hacker's Delight, this can be implemented in 4448 // target independent lowering, but it would be inefficient, since it 4449 // requires a division + a branch. 4450 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!"); 4451 break; 4452 } 4453 break; 4454 } 4455 4456 } 4457 4458 assert(Result.getValueType() == Op.getValueType() && 4459 "Bad legalization!"); 4460 4461 // Make sure that the generated code is itself legal. 4462 if (Result != Op) 4463 Result = LegalizeOp(Result); 4464 4465 // Note that LegalizeOp may be reentered even from single-use nodes, which 4466 // means that we always must cache transformed nodes. 4467 AddLegalizedOperand(Op, Result); 4468 return Result; 4469} 4470 4471/// PromoteOp - Given an operation that produces a value in an invalid type, 4472/// promote it to compute the value into a larger type. The produced value will 4473/// have the correct bits for the low portion of the register, but no guarantee 4474/// is made about the top bits: it may be zero, sign-extended, or garbage. 4475SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { 4476 MVT VT = Op.getValueType(); 4477 MVT NVT = TLI.getTypeToTransformTo(VT); 4478 assert(getTypeAction(VT) == Promote && 4479 "Caller should expand or legalize operands that are not promotable!"); 4480 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() && 4481 "Cannot promote to smaller type!"); 4482 4483 SDValue Tmp1, Tmp2, Tmp3; 4484 SDValue Result; 4485 SDNode *Node = Op.getNode(); 4486 4487 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op); 4488 if (I != PromotedNodes.end()) return I->second; 4489 4490 switch (Node->getOpcode()) { 4491 case ISD::CopyFromReg: 4492 assert(0 && "CopyFromReg must be legal!"); 4493 default: 4494#ifndef NDEBUG 4495 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4496#endif 4497 assert(0 && "Do not know how to promote this operator!"); 4498 abort(); 4499 case ISD::UNDEF: 4500 Result = DAG.getNode(ISD::UNDEF, NVT); 4501 break; 4502 case ISD::Constant: 4503 if (VT != MVT::i1) 4504 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4505 else 4506 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4507 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4508 break; 4509 case ISD::ConstantFP: 4510 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4511 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4512 break; 4513 4514 case ISD::SETCC: { 4515 MVT VT0 = Node->getOperand(0).getValueType(); 4516 assert(isTypeLegal(TLI.getSetCCResultType(VT0)) 4517 && "SetCC type is not legal??"); 4518 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(VT0), 4519 Node->getOperand(0), Node->getOperand(1), 4520 Node->getOperand(2)); 4521 break; 4522 } 4523 case ISD::TRUNCATE: 4524 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4525 case Legal: 4526 Result = LegalizeOp(Node->getOperand(0)); 4527 assert(Result.getValueType().bitsGE(NVT) && 4528 "This truncation doesn't make sense!"); 4529 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT 4530 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4531 break; 4532 case Promote: 4533 // The truncation is not required, because we don't guarantee anything 4534 // about high bits anyway. 4535 Result = PromoteOp(Node->getOperand(0)); 4536 break; 4537 case Expand: 4538 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4539 // Truncate the low part of the expanded value to the result type 4540 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4541 } 4542 break; 4543 case ISD::SIGN_EXTEND: 4544 case ISD::ZERO_EXTEND: 4545 case ISD::ANY_EXTEND: 4546 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4547 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4548 case Legal: 4549 // Input is legal? Just do extend all the way to the larger type. 4550 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4551 break; 4552 case Promote: 4553 // Promote the reg if it's smaller. 4554 Result = PromoteOp(Node->getOperand(0)); 4555 // The high bits are not guaranteed to be anything. Insert an extend. 4556 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4557 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4558 DAG.getValueType(Node->getOperand(0).getValueType())); 4559 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4560 Result = DAG.getZeroExtendInReg(Result, 4561 Node->getOperand(0).getValueType()); 4562 break; 4563 } 4564 break; 4565 case ISD::CONVERT_RNDSAT: { 4566 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 4567 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 4568 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 4569 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 4570 "can only promote integers"); 4571 Result = DAG.getConvertRndSat(NVT, Node->getOperand(0), 4572 Node->getOperand(1), Node->getOperand(2), 4573 Node->getOperand(3), Node->getOperand(4), 4574 CvtCode); 4575 break; 4576 4577 } 4578 case ISD::BIT_CONVERT: 4579 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4580 Node->getValueType(0)); 4581 Result = PromoteOp(Result); 4582 break; 4583 4584 case ISD::FP_EXTEND: 4585 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4586 case ISD::FP_ROUND: 4587 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4588 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4589 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4590 case Legal: 4591 if (Node->getConstantOperandVal(1) == 0) { 4592 // Input is legal? Do an FP_ROUND_INREG. 4593 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4594 DAG.getValueType(VT)); 4595 } else { 4596 // Just remove the truncate, it isn't affecting the value. 4597 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4598 Node->getOperand(1)); 4599 } 4600 break; 4601 } 4602 break; 4603 case ISD::SINT_TO_FP: 4604 case ISD::UINT_TO_FP: 4605 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4606 case Legal: 4607 // No extra round required here. 4608 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4609 break; 4610 4611 case Promote: 4612 Result = PromoteOp(Node->getOperand(0)); 4613 if (Node->getOpcode() == ISD::SINT_TO_FP) 4614 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4615 Result, 4616 DAG.getValueType(Node->getOperand(0).getValueType())); 4617 else 4618 Result = DAG.getZeroExtendInReg(Result, 4619 Node->getOperand(0).getValueType()); 4620 // No extra round required here. 4621 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4622 break; 4623 case Expand: 4624 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4625 Node->getOperand(0), Node->getDebugLoc()); 4626 // Round if we cannot tolerate excess precision. 4627 if (NoExcessFPPrecision) 4628 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4629 DAG.getValueType(VT)); 4630 break; 4631 } 4632 break; 4633 4634 case ISD::SIGN_EXTEND_INREG: 4635 Result = PromoteOp(Node->getOperand(0)); 4636 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4637 Node->getOperand(1)); 4638 break; 4639 case ISD::FP_TO_SINT: 4640 case ISD::FP_TO_UINT: 4641 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4642 case Legal: 4643 case Expand: 4644 Tmp1 = Node->getOperand(0); 4645 break; 4646 case Promote: 4647 // The input result is prerounded, so we don't have to do anything 4648 // special. 4649 Tmp1 = PromoteOp(Node->getOperand(0)); 4650 break; 4651 } 4652 // If we're promoting a UINT to a larger size, check to see if the new node 4653 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4654 // we can use that instead. This allows us to generate better code for 4655 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4656 // legal, such as PowerPC. 4657 if (Node->getOpcode() == ISD::FP_TO_UINT && 4658 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) && 4659 (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) || 4660 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4661 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4662 } else { 4663 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4664 } 4665 break; 4666 4667 case ISD::FABS: 4668 case ISD::FNEG: 4669 Tmp1 = PromoteOp(Node->getOperand(0)); 4670 assert(Tmp1.getValueType() == NVT); 4671 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4672 // NOTE: we do not have to do any extra rounding here for 4673 // NoExcessFPPrecision, because we know the input will have the appropriate 4674 // precision, and these operations don't modify precision at all. 4675 break; 4676 4677 case ISD::FLOG: 4678 case ISD::FLOG2: 4679 case ISD::FLOG10: 4680 case ISD::FEXP: 4681 case ISD::FEXP2: 4682 case ISD::FSQRT: 4683 case ISD::FSIN: 4684 case ISD::FCOS: 4685 case ISD::FTRUNC: 4686 case ISD::FFLOOR: 4687 case ISD::FCEIL: 4688 case ISD::FRINT: 4689 case ISD::FNEARBYINT: 4690 Tmp1 = PromoteOp(Node->getOperand(0)); 4691 assert(Tmp1.getValueType() == NVT); 4692 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4693 if (NoExcessFPPrecision) 4694 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4695 DAG.getValueType(VT)); 4696 break; 4697 4698 case ISD::FPOW: 4699 case ISD::FPOWI: { 4700 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall 4701 // directly as well, which may be better. 4702 Tmp1 = PromoteOp(Node->getOperand(0)); 4703 Tmp2 = Node->getOperand(1); 4704 if (Node->getOpcode() == ISD::FPOW) 4705 Tmp2 = PromoteOp(Tmp2); 4706 assert(Tmp1.getValueType() == NVT); 4707 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4708 if (NoExcessFPPrecision) 4709 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4710 DAG.getValueType(VT)); 4711 break; 4712 } 4713 4714 case ISD::ATOMIC_CMP_SWAP: { 4715 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4716 Tmp2 = PromoteOp(Node->getOperand(2)); 4717 Tmp3 = PromoteOp(Node->getOperand(3)); 4718 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(), 4719 AtomNode->getChain(), 4720 AtomNode->getBasePtr(), Tmp2, Tmp3, 4721 AtomNode->getSrcValue(), 4722 AtomNode->getAlignment()); 4723 // Remember that we legalized the chain. 4724 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4725 break; 4726 } 4727 case ISD::ATOMIC_LOAD_ADD: 4728 case ISD::ATOMIC_LOAD_SUB: 4729 case ISD::ATOMIC_LOAD_AND: 4730 case ISD::ATOMIC_LOAD_OR: 4731 case ISD::ATOMIC_LOAD_XOR: 4732 case ISD::ATOMIC_LOAD_NAND: 4733 case ISD::ATOMIC_LOAD_MIN: 4734 case ISD::ATOMIC_LOAD_MAX: 4735 case ISD::ATOMIC_LOAD_UMIN: 4736 case ISD::ATOMIC_LOAD_UMAX: 4737 case ISD::ATOMIC_SWAP: { 4738 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4739 Tmp2 = PromoteOp(Node->getOperand(2)); 4740 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getMemoryVT(), 4741 AtomNode->getChain(), 4742 AtomNode->getBasePtr(), Tmp2, 4743 AtomNode->getSrcValue(), 4744 AtomNode->getAlignment()); 4745 // Remember that we legalized the chain. 4746 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4747 break; 4748 } 4749 4750 case ISD::AND: 4751 case ISD::OR: 4752 case ISD::XOR: 4753 case ISD::ADD: 4754 case ISD::SUB: 4755 case ISD::MUL: 4756 // The input may have strange things in the top bits of the registers, but 4757 // these operations don't care. They may have weird bits going out, but 4758 // that too is okay if they are integer operations. 4759 Tmp1 = PromoteOp(Node->getOperand(0)); 4760 Tmp2 = PromoteOp(Node->getOperand(1)); 4761 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4762 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4763 break; 4764 case ISD::FADD: 4765 case ISD::FSUB: 4766 case ISD::FMUL: 4767 Tmp1 = PromoteOp(Node->getOperand(0)); 4768 Tmp2 = PromoteOp(Node->getOperand(1)); 4769 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4770 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4771 4772 // Floating point operations will give excess precision that we may not be 4773 // able to tolerate. If we DO allow excess precision, just leave it, 4774 // otherwise excise it. 4775 // FIXME: Why would we need to round FP ops more than integer ones? 4776 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4777 if (NoExcessFPPrecision) 4778 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4779 DAG.getValueType(VT)); 4780 break; 4781 4782 case ISD::SDIV: 4783 case ISD::SREM: 4784 // These operators require that their input be sign extended. 4785 Tmp1 = PromoteOp(Node->getOperand(0)); 4786 Tmp2 = PromoteOp(Node->getOperand(1)); 4787 if (NVT.isInteger()) { 4788 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4789 DAG.getValueType(VT)); 4790 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4791 DAG.getValueType(VT)); 4792 } 4793 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4794 4795 // Perform FP_ROUND: this is probably overly pessimistic. 4796 if (NVT.isFloatingPoint() && NoExcessFPPrecision) 4797 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4798 DAG.getValueType(VT)); 4799 break; 4800 case ISD::FDIV: 4801 case ISD::FREM: 4802 case ISD::FCOPYSIGN: 4803 // These operators require that their input be fp extended. 4804 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4805 case Expand: assert(0 && "not implemented"); 4806 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4807 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4808 } 4809 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4810 case Expand: assert(0 && "not implemented"); 4811 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4812 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4813 } 4814 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4815 4816 // Perform FP_ROUND: this is probably overly pessimistic. 4817 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4818 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4819 DAG.getValueType(VT)); 4820 break; 4821 4822 case ISD::UDIV: 4823 case ISD::UREM: 4824 // These operators require that their input be zero extended. 4825 Tmp1 = PromoteOp(Node->getOperand(0)); 4826 Tmp2 = PromoteOp(Node->getOperand(1)); 4827 assert(NVT.isInteger() && "Operators don't apply to FP!"); 4828 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4829 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4830 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4831 break; 4832 4833 case ISD::SHL: 4834 Tmp1 = PromoteOp(Node->getOperand(0)); 4835 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4836 break; 4837 case ISD::SRA: 4838 // The input value must be properly sign extended. 4839 Tmp1 = PromoteOp(Node->getOperand(0)); 4840 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4841 DAG.getValueType(VT)); 4842 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4843 break; 4844 case ISD::SRL: 4845 // The input value must be properly zero extended. 4846 Tmp1 = PromoteOp(Node->getOperand(0)); 4847 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4848 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4849 break; 4850 4851 case ISD::VAARG: 4852 Tmp1 = Node->getOperand(0); // Get the chain. 4853 Tmp2 = Node->getOperand(1); // Get the pointer. 4854 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4855 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4856 Result = TLI.LowerOperation(Tmp3, DAG); 4857 } else { 4858 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4859 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4860 // Increment the pointer, VAList, to the next vaarg 4861 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4862 DAG.getConstant(VT.getSizeInBits()/8, 4863 TLI.getPointerTy())); 4864 // Store the incremented VAList to the legalized pointer 4865 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4866 // Load the actual argument out of the pointer VAList 4867 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4868 } 4869 // Remember that we legalized the chain. 4870 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4871 break; 4872 4873 case ISD::LOAD: { 4874 LoadSDNode *LD = cast<LoadSDNode>(Node); 4875 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4876 ? ISD::EXTLOAD : LD->getExtensionType(); 4877 Result = DAG.getExtLoad(ExtType, NVT, 4878 LD->getChain(), LD->getBasePtr(), 4879 LD->getSrcValue(), LD->getSrcValueOffset(), 4880 LD->getMemoryVT(), 4881 LD->isVolatile(), 4882 LD->getAlignment()); 4883 // Remember that we legalized the chain. 4884 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4885 break; 4886 } 4887 case ISD::SELECT: { 4888 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4889 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4890 4891 MVT VT2 = Tmp2.getValueType(); 4892 assert(VT2 == Tmp3.getValueType() 4893 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); 4894 // Ensure that the resulting node is at least the same size as the operands' 4895 // value types, because we cannot assume that TLI.getSetCCValueType() is 4896 // constant. 4897 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3); 4898 break; 4899 } 4900 case ISD::SELECT_CC: 4901 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4902 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4903 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4904 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4905 break; 4906 case ISD::BSWAP: 4907 Tmp1 = Node->getOperand(0); 4908 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4909 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4910 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4911 DAG.getConstant(NVT.getSizeInBits() - 4912 VT.getSizeInBits(), 4913 TLI.getShiftAmountTy())); 4914 break; 4915 case ISD::CTPOP: 4916 case ISD::CTTZ: 4917 case ISD::CTLZ: 4918 // Zero extend the argument 4919 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4920 // Perform the larger operation, then subtract if needed. 4921 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4922 switch(Node->getOpcode()) { 4923 case ISD::CTPOP: 4924 Result = Tmp1; 4925 break; 4926 case ISD::CTTZ: 4927 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4928 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, 4929 DAG.getConstant(NVT.getSizeInBits(), NVT), 4930 ISD::SETEQ); 4931 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4932 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); 4933 break; 4934 case ISD::CTLZ: 4935 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4936 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4937 DAG.getConstant(NVT.getSizeInBits() - 4938 VT.getSizeInBits(), NVT)); 4939 break; 4940 } 4941 break; 4942 case ISD::EXTRACT_SUBVECTOR: 4943 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4944 break; 4945 case ISD::EXTRACT_VECTOR_ELT: 4946 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4947 break; 4948 } 4949 4950 assert(Result.getNode() && "Didn't set a result!"); 4951 4952 // Make sure the result is itself legal. 4953 Result = LegalizeOp(Result); 4954 4955 // Remember that we promoted this! 4956 AddPromotedOperand(Op, Result); 4957 return Result; 4958} 4959 4960/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4961/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4962/// based on the vector type. The return type of this matches the element type 4963/// of the vector, which may not be legal for the target. 4964SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) { 4965 // We know that operand #0 is the Vec vector. If the index is a constant 4966 // or if the invec is a supported hardware type, we can use it. Otherwise, 4967 // lower to a store then an indexed load. 4968 SDValue Vec = Op.getOperand(0); 4969 SDValue Idx = Op.getOperand(1); 4970 DebugLoc dl = Op.getNode()->getDebugLoc(); 4971 4972 MVT TVT = Vec.getValueType(); 4973 unsigned NumElems = TVT.getVectorNumElements(); 4974 4975 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4976 default: assert(0 && "This action is not supported yet!"); 4977 case TargetLowering::Custom: { 4978 Vec = LegalizeOp(Vec); 4979 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4980 SDValue Tmp3 = TLI.LowerOperation(Op, DAG); 4981 if (Tmp3.getNode()) 4982 return Tmp3; 4983 break; 4984 } 4985 case TargetLowering::Legal: 4986 if (isTypeLegal(TVT)) { 4987 Vec = LegalizeOp(Vec); 4988 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4989 return Op; 4990 } 4991 break; 4992 case TargetLowering::Promote: 4993 assert(TVT.isVector() && "not vector type"); 4994 // fall thru to expand since vectors are by default are promote 4995 case TargetLowering::Expand: 4996 break; 4997 } 4998 4999 if (NumElems == 1) { 5000 // This must be an access of the only element. Return it. 5001 Op = ScalarizeVectorOp(Vec); 5002 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 5003 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 5004 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 5005 SDValue Lo, Hi; 5006 SplitVectorOp(Vec, Lo, Hi); 5007 if (CIdx->getZExtValue() < NumLoElts) { 5008 Vec = Lo; 5009 } else { 5010 Vec = Hi; 5011 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts, 5012 Idx.getValueType()); 5013 } 5014 5015 // It's now an extract from the appropriate high or low part. Recurse. 5016 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 5017 Op = ExpandEXTRACT_VECTOR_ELT(Op); 5018 } else { 5019 // Store the value to a temporary stack slot, then LOAD the scalar 5020 // element back out. 5021 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 5022 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0); 5023 5024 // Add the offset to the index. 5025 unsigned EltSize = Op.getValueType().getSizeInBits()/8; 5026 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 5027 DAG.getConstant(EltSize, Idx.getValueType())); 5028 5029 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 5030 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 5031 else 5032 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 5033 5034 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 5035 5036 Op = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0); 5037 } 5038 return Op; 5039} 5040 5041/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 5042/// we assume the operation can be split if it is not already legal. 5043SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) { 5044 // We know that operand #0 is the Vec vector. For now we assume the index 5045 // is a constant and that the extracted result is a supported hardware type. 5046 SDValue Vec = Op.getOperand(0); 5047 SDValue Idx = LegalizeOp(Op.getOperand(1)); 5048 5049 unsigned NumElems = Vec.getValueType().getVectorNumElements(); 5050 5051 if (NumElems == Op.getValueType().getVectorNumElements()) { 5052 // This must be an access of the desired vector length. Return it. 5053 return Vec; 5054 } 5055 5056 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 5057 SDValue Lo, Hi; 5058 SplitVectorOp(Vec, Lo, Hi); 5059 if (CIdx->getZExtValue() < NumElems/2) { 5060 Vec = Lo; 5061 } else { 5062 Vec = Hi; 5063 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2, 5064 Idx.getValueType()); 5065 } 5066 5067 // It's now an extract from the appropriate high or low part. Recurse. 5068 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 5069 return ExpandEXTRACT_SUBVECTOR(Op); 5070} 5071 5072/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 5073/// with condition CC on the current target. This usually involves legalizing 5074/// or promoting the arguments. In the case where LHS and RHS must be expanded, 5075/// there may be no choice but to create a new SetCC node to represent the 5076/// legalized value of setcc lhs, rhs. In this case, the value is returned in 5077/// LHS, and the SDValue returned in RHS has a nil SDNode value. 5078void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS, 5079 SDValue &RHS, 5080 SDValue &CC, 5081 DebugLoc dl) { 5082 SDValue Tmp1, Tmp2, Tmp3, Result; 5083 5084 switch (getTypeAction(LHS.getValueType())) { 5085 case Legal: 5086 Tmp1 = LegalizeOp(LHS); // LHS 5087 Tmp2 = LegalizeOp(RHS); // RHS 5088 break; 5089 case Promote: 5090 Tmp1 = PromoteOp(LHS); // LHS 5091 Tmp2 = PromoteOp(RHS); // RHS 5092 5093 // If this is an FP compare, the operands have already been extended. 5094 if (LHS.getValueType().isInteger()) { 5095 MVT VT = LHS.getValueType(); 5096 MVT NVT = TLI.getTypeToTransformTo(VT); 5097 5098 // Otherwise, we have to insert explicit sign or zero extends. Note 5099 // that we could insert sign extends for ALL conditions, but zero extend 5100 // is cheaper on many machines (an AND instead of two shifts), so prefer 5101 // it. 5102 switch (cast<CondCodeSDNode>(CC)->get()) { 5103 default: assert(0 && "Unknown integer comparison!"); 5104 case ISD::SETEQ: 5105 case ISD::SETNE: 5106 case ISD::SETUGE: 5107 case ISD::SETUGT: 5108 case ISD::SETULE: 5109 case ISD::SETULT: 5110 // ALL of these operations will work if we either sign or zero extend 5111 // the operands (including the unsigned comparisons!). Zero extend is 5112 // usually a simpler/cheaper operation, so prefer it. 5113 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT); 5114 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT); 5115 break; 5116 case ISD::SETGE: 5117 case ISD::SETGT: 5118 case ISD::SETLT: 5119 case ISD::SETLE: 5120 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1, 5121 DAG.getValueType(VT)); 5122 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2, 5123 DAG.getValueType(VT)); 5124 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes. 5125 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes. 5126 break; 5127 } 5128 } 5129 break; 5130 case Expand: { 5131 MVT VT = LHS.getValueType(); 5132 if (VT == MVT::f32 || VT == MVT::f64) { 5133 // Expand into one or more soft-fp libcall(s). 5134 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; 5135 switch (cast<CondCodeSDNode>(CC)->get()) { 5136 case ISD::SETEQ: 5137 case ISD::SETOEQ: 5138 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 5139 break; 5140 case ISD::SETNE: 5141 case ISD::SETUNE: 5142 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 5143 break; 5144 case ISD::SETGE: 5145 case ISD::SETOGE: 5146 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 5147 break; 5148 case ISD::SETLT: 5149 case ISD::SETOLT: 5150 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5151 break; 5152 case ISD::SETLE: 5153 case ISD::SETOLE: 5154 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 5155 break; 5156 case ISD::SETGT: 5157 case ISD::SETOGT: 5158 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 5159 break; 5160 case ISD::SETUO: 5161 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 5162 break; 5163 case ISD::SETO: 5164 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 5165 break; 5166 default: 5167 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 5168 switch (cast<CondCodeSDNode>(CC)->get()) { 5169 case ISD::SETONE: 5170 // SETONE = SETOLT | SETOGT 5171 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5172 // Fallthrough 5173 case ISD::SETUGT: 5174 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 5175 break; 5176 case ISD::SETUGE: 5177 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 5178 break; 5179 case ISD::SETULT: 5180 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5181 break; 5182 case ISD::SETULE: 5183 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 5184 break; 5185 case ISD::SETUEQ: 5186 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 5187 break; 5188 default: assert(0 && "Unsupported FP setcc!"); 5189 } 5190 } 5191 5192 SDValue Dummy; 5193 SDValue Ops[2] = { LHS, RHS }; 5194 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2, dl).getNode(), 5195 false /*sign irrelevant*/, Dummy); 5196 Tmp2 = DAG.getConstant(0, MVT::i32); 5197 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 5198 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 5199 Tmp1 = DAG.getNode(ISD::SETCC, dl, 5200 TLI.getSetCCResultType(Tmp1.getValueType()), 5201 Tmp1, Tmp2, CC); 5202 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2, dl).getNode(), 5203 false /*sign irrelevant*/, Dummy); 5204 Tmp2 = DAG.getNode(ISD::SETCC, dl, 5205 TLI.getSetCCResultType(LHS.getValueType()), LHS, 5206 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 5207 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2); 5208 Tmp2 = SDValue(); 5209 } 5210 LHS = LegalizeOp(Tmp1); 5211 RHS = Tmp2; 5212 return; 5213 } 5214 5215 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 5216 ExpandOp(LHS, LHSLo, LHSHi); 5217 ExpandOp(RHS, RHSLo, RHSHi); 5218 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 5219 5220 if (VT==MVT::ppcf128) { 5221 // FIXME: This generated code sucks. We want to generate 5222 // FCMPU crN, hi1, hi2 5223 // BNE crN, L: 5224 // FCMPU crN, lo1, lo2 5225 // The following can be improved, but not that much. 5226 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 5227 LHSHi, RHSHi, ISD::SETOEQ); 5228 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 5229 LHSLo, RHSLo, CCCode); 5230 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); 5231 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 5232 LHSHi, RHSHi, ISD::SETUNE); 5233 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 5234 LHSHi, RHSHi, CCCode); 5235 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); 5236 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); 5237 Tmp2 = SDValue(); 5238 break; 5239 } 5240 5241 switch (CCCode) { 5242 case ISD::SETEQ: 5243 case ISD::SETNE: 5244 if (RHSLo == RHSHi) 5245 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 5246 if (RHSCST->isAllOnesValue()) { 5247 // Comparison to -1. 5248 Tmp1 = DAG.getNode(ISD::AND, dl,LHSLo.getValueType(), LHSLo, LHSHi); 5249 Tmp2 = RHSLo; 5250 break; 5251 } 5252 5253 Tmp1 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 5254 Tmp2 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 5255 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2); 5256 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 5257 break; 5258 default: 5259 // If this is a comparison of the sign bit, just look at the top part. 5260 // X > -1, x < 0 5261 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 5262 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 5263 CST->isNullValue()) || // X < 0 5264 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 5265 CST->isAllOnesValue())) { // X > -1 5266 Tmp1 = LHSHi; 5267 Tmp2 = RHSHi; 5268 break; 5269 } 5270 5271 // FIXME: This generated code sucks. 5272 ISD::CondCode LowCC; 5273 switch (CCCode) { 5274 default: assert(0 && "Unknown integer setcc!"); 5275 case ISD::SETLT: 5276 case ISD::SETULT: LowCC = ISD::SETULT; break; 5277 case ISD::SETGT: 5278 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 5279 case ISD::SETLE: 5280 case ISD::SETULE: LowCC = ISD::SETULE; break; 5281 case ISD::SETGE: 5282 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 5283 } 5284 5285 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 5286 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 5287 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 5288 5289 // NOTE: on targets without efficient SELECT of bools, we can always use 5290 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 5291 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 5292 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), 5293 LHSLo, RHSLo, LowCC, false, DagCombineInfo); 5294 if (!Tmp1.getNode()) 5295 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 5296 LHSLo, RHSLo, LowCC); 5297 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 5298 LHSHi, RHSHi, CCCode, false, DagCombineInfo); 5299 if (!Tmp2.getNode()) 5300 Tmp2 = DAG.getNode(ISD::SETCC, dl, 5301 TLI.getSetCCResultType(LHSHi.getValueType()), 5302 LHSHi, RHSHi,CC); 5303 5304 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 5305 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 5306 if ((Tmp1C && Tmp1C->isNullValue()) || 5307 (Tmp2C && Tmp2C->isNullValue() && 5308 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 5309 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 5310 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 5311 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 5312 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 5313 // low part is known false, returns high part. 5314 // For LE / GE, if high part is known false, ignore the low part. 5315 // For LT / GT, if high part is known true, ignore the low part. 5316 Tmp1 = Tmp2; 5317 Tmp2 = SDValue(); 5318 } else { 5319 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 5320 LHSHi, RHSHi, ISD::SETEQ, false, 5321 DagCombineInfo); 5322 if (!Result.getNode()) 5323 Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 5324 LHSHi, RHSHi, ISD::SETEQ); 5325 Result = LegalizeOp(DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), 5326 Result, Tmp1, Tmp2)); 5327 Tmp1 = Result; 5328 Tmp2 = SDValue(); 5329 } 5330 } 5331 } 5332 } 5333 LHS = Tmp1; 5334 RHS = Tmp2; 5335} 5336 5337/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 5338/// condition code CC on the current target. This routine assumes LHS and rHS 5339/// have already been legalized by LegalizeSetCCOperands. It expands SETCC with 5340/// illegal condition code into AND / OR of multiple SETCC values. 5341void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, 5342 SDValue &LHS, SDValue &RHS, 5343 SDValue &CC, 5344 DebugLoc dl) { 5345 MVT OpVT = LHS.getValueType(); 5346 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 5347 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 5348 default: assert(0 && "Unknown condition code action!"); 5349 case TargetLowering::Legal: 5350 // Nothing to do. 5351 break; 5352 case TargetLowering::Expand: { 5353 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 5354 unsigned Opc = 0; 5355 switch (CCCode) { 5356 default: assert(0 && "Don't know how to expand this condition!"); abort(); 5357 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 5358 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 5359 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5360 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 5361 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5362 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5363 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5364 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5365 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5366 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5367 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5368 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5369 // FIXME: Implement more expansions. 5370 } 5371 5372 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 5373 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 5374 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 5375 RHS = SDValue(); 5376 CC = SDValue(); 5377 break; 5378 } 5379 } 5380} 5381 5382/// EmitStackConvert - Emit a store/load combination to the stack. This stores 5383/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 5384/// a load from the stack slot to DestVT, extending it if needed. 5385/// The resultant code need not be legal. 5386SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 5387 MVT SlotVT, 5388 MVT DestVT) { 5389 // Create the stack frame object. 5390 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment( 5391 SrcOp.getValueType().getTypeForMVT()); 5392 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 5393 5394 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 5395 int SPFI = StackPtrFI->getIndex(); 5396 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 5397 5398 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 5399 unsigned SlotSize = SlotVT.getSizeInBits(); 5400 unsigned DestSize = DestVT.getSizeInBits(); 5401 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment( 5402 DestVT.getTypeForMVT()); 5403 5404 // Emit a store to the stack slot. Use a truncstore if the input value is 5405 // later than DestVT. 5406 SDValue Store; 5407 5408 if (SrcSize > SlotSize) 5409 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 5410 SV, 0, SlotVT, false, SrcAlign); 5411 else { 5412 assert(SrcSize == SlotSize && "Invalid store"); 5413 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 5414 SV, 0, false, SrcAlign); 5415 } 5416 5417 // Result is a load from the stack slot. 5418 if (SlotSize == DestSize) 5419 return DAG.getLoad(DestVT, Store, FIPtr, SV, 0, false, DestAlign); 5420 5421 assert(SlotSize < DestSize && "Unknown extension!"); 5422 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, SV, 0, SlotVT, 5423 false, DestAlign); 5424} 5425 5426SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 5427 // Create a vector sized/aligned stack slot, store the value to element #0, 5428 // then load the whole vector back out. 5429 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 5430 5431 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 5432 int SPFI = StackPtrFI->getIndex(); 5433 5434 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 5435 PseudoSourceValue::getFixedStack(SPFI), 0); 5436 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 5437 PseudoSourceValue::getFixedStack(SPFI), 0); 5438} 5439 5440 5441/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 5442/// support the operation, but do support the resultant vector type. 5443SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 5444 5445 // If the only non-undef value is the low element, turn this into a 5446 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 5447 unsigned NumElems = Node->getNumOperands(); 5448 bool isOnlyLowElement = true; 5449 SDValue SplatValue = Node->getOperand(0); 5450 5451 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t> 5452 // and use a bitmask instead of a list of elements. 5453 std::map<SDValue, std::vector<unsigned> > Values; 5454 Values[SplatValue].push_back(0); 5455 bool isConstant = true; 5456 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 5457 SplatValue.getOpcode() != ISD::UNDEF) 5458 isConstant = false; 5459 5460 for (unsigned i = 1; i < NumElems; ++i) { 5461 SDValue V = Node->getOperand(i); 5462 Values[V].push_back(i); 5463 if (V.getOpcode() != ISD::UNDEF) 5464 isOnlyLowElement = false; 5465 if (SplatValue != V) 5466 SplatValue = SDValue(0,0); 5467 5468 // If this isn't a constant element or an undef, we can't use a constant 5469 // pool load. 5470 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 5471 V.getOpcode() != ISD::UNDEF) 5472 isConstant = false; 5473 } 5474 5475 if (isOnlyLowElement) { 5476 // If the low element is an undef too, then this whole things is an undef. 5477 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 5478 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 5479 // Otherwise, turn this into a scalar_to_vector node. 5480 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 5481 Node->getOperand(0)); 5482 } 5483 5484 // If all elements are constants, create a load from the constant pool. 5485 if (isConstant) { 5486 MVT VT = Node->getValueType(0); 5487 std::vector<Constant*> CV; 5488 for (unsigned i = 0, e = NumElems; i != e; ++i) { 5489 if (ConstantFPSDNode *V = 5490 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 5491 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 5492 } else if (ConstantSDNode *V = 5493 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 5494 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 5495 } else { 5496 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 5497 const Type *OpNTy = 5498 Node->getOperand(0).getValueType().getTypeForMVT(); 5499 CV.push_back(UndefValue::get(OpNTy)); 5500 } 5501 } 5502 Constant *CP = ConstantVector::get(CV); 5503 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 5504 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5505 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 5506 PseudoSourceValue::getConstantPool(), 0, 5507 false, Alignment); 5508 } 5509 5510 if (SplatValue.getNode()) { // Splat of one value? 5511 // Build the shuffle constant vector: <0, 0, 0, 0> 5512 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5513 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); 5514 std::vector<SDValue> ZeroVec(NumElems, Zero); 5515 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5516 &ZeroVec[0], ZeroVec.size()); 5517 5518 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 5519 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 5520 // Get the splatted value into the low element of a vector register. 5521 SDValue LowValVec = 5522 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 5523 5524 // Return shuffle(LowValVec, undef, <0,0,0,0>) 5525 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 5526 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 5527 SplatMask); 5528 } 5529 } 5530 5531 // If there are only two unique elements, we may be able to turn this into a 5532 // vector shuffle. 5533 if (Values.size() == 2) { 5534 // Get the two values in deterministic order. 5535 SDValue Val1 = Node->getOperand(1); 5536 SDValue Val2; 5537 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin(); 5538 if (MI->first != Val1) 5539 Val2 = MI->first; 5540 else 5541 Val2 = (++MI)->first; 5542 5543 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 5544 // vector shuffle has the undef vector on the RHS. 5545 if (Val1.getOpcode() == ISD::UNDEF) 5546 std::swap(Val1, Val2); 5547 5548 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 5549 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5550 MVT MaskEltVT = MaskVT.getVectorElementType(); 5551 std::vector<SDValue> MaskVec(NumElems); 5552 5553 // Set elements of the shuffle mask for Val1. 5554 std::vector<unsigned> &Val1Elts = Values[Val1]; 5555 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 5556 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 5557 5558 // Set elements of the shuffle mask for Val2. 5559 std::vector<unsigned> &Val2Elts = Values[Val2]; 5560 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 5561 if (Val2.getOpcode() != ISD::UNDEF) 5562 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 5563 else 5564 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); 5565 5566 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5567 &MaskVec[0], MaskVec.size()); 5568 5569 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 5570 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, 5571 Node->getValueType(0)) && 5572 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 5573 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); 5574 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); 5575 SDValue Ops[] = { Val1, Val2, ShuffleMask }; 5576 5577 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 5578 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); 5579 } 5580 } 5581 5582 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5583 // aligned object on the stack, store each element into it, then load 5584 // the result as a vector. 5585 MVT VT = Node->getValueType(0); 5586 // Create the stack frame object. 5587 SDValue FIPtr = DAG.CreateStackTemporary(VT); 5588 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 5589 const Value *SV = PseudoSourceValue::getFixedStack(FI); 5590 5591 // Emit a store of each element to the stack slot. 5592 SmallVector<SDValue, 8> Stores; 5593 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8; 5594 // Store (in the right endianness) the elements to memory. 5595 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5596 // Ignore undef elements. 5597 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5598 5599 unsigned Offset = TypeByteSize*i; 5600 5601 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5602 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 5603 5604 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 5605 SV, Offset)); 5606 } 5607 5608 SDValue StoreChain; 5609 if (!Stores.empty()) // Not all undef elements? 5610 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5611 &Stores[0], Stores.size()); 5612 else 5613 StoreChain = DAG.getEntryNode(); 5614 5615 // Result is a load from the stack slot. 5616 return DAG.getLoad(VT, StoreChain, FIPtr, SV, 0); 5617} 5618 5619void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5620 SDValue Op, SDValue Amt, 5621 SDValue &Lo, SDValue &Hi) { 5622 // Expand the subcomponents. 5623 SDValue LHSL, LHSH; 5624 ExpandOp(Op, LHSL, LHSH); 5625 5626 SDValue Ops[] = { LHSL, LHSH, Amt }; 5627 MVT VT = LHSL.getValueType(); 5628 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5629 Hi = Lo.getValue(1); 5630} 5631 5632 5633/// ExpandShift - Try to find a clever way to expand this shift operation out to 5634/// smaller elements. If we can't find a way that is more efficient than a 5635/// libcall on this target, return false. Otherwise, return true with the 5636/// low-parts expanded into Lo and Hi. 5637bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, 5638 SDValue &Lo, SDValue &Hi) { 5639 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5640 "This is not a shift!"); 5641 5642 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5643 SDValue ShAmt = LegalizeOp(Amt); 5644 MVT ShTy = ShAmt.getValueType(); 5645 unsigned ShBits = ShTy.getSizeInBits(); 5646 unsigned VTBits = Op.getValueType().getSizeInBits(); 5647 unsigned NVTBits = NVT.getSizeInBits(); 5648 5649 // Handle the case when Amt is an immediate. 5650 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) { 5651 unsigned Cst = CN->getZExtValue(); 5652 // Expand the incoming operand to be shifted, so that we have its parts 5653 SDValue InL, InH; 5654 ExpandOp(Op, InL, InH); 5655 switch(Opc) { 5656 case ISD::SHL: 5657 if (Cst > VTBits) { 5658 Lo = DAG.getConstant(0, NVT); 5659 Hi = DAG.getConstant(0, NVT); 5660 } else if (Cst > NVTBits) { 5661 Lo = DAG.getConstant(0, NVT); 5662 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5663 } else if (Cst == NVTBits) { 5664 Lo = DAG.getConstant(0, NVT); 5665 Hi = InL; 5666 } else { 5667 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5668 Hi = DAG.getNode(ISD::OR, NVT, 5669 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5670 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5671 } 5672 return true; 5673 case ISD::SRL: 5674 if (Cst > VTBits) { 5675 Lo = DAG.getConstant(0, NVT); 5676 Hi = DAG.getConstant(0, NVT); 5677 } else if (Cst > NVTBits) { 5678 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5679 Hi = DAG.getConstant(0, NVT); 5680 } else if (Cst == NVTBits) { 5681 Lo = InH; 5682 Hi = DAG.getConstant(0, NVT); 5683 } else { 5684 Lo = DAG.getNode(ISD::OR, NVT, 5685 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5686 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5687 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5688 } 5689 return true; 5690 case ISD::SRA: 5691 if (Cst > VTBits) { 5692 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5693 DAG.getConstant(NVTBits-1, ShTy)); 5694 } else if (Cst > NVTBits) { 5695 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5696 DAG.getConstant(Cst-NVTBits, ShTy)); 5697 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5698 DAG.getConstant(NVTBits-1, ShTy)); 5699 } else if (Cst == NVTBits) { 5700 Lo = InH; 5701 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5702 DAG.getConstant(NVTBits-1, ShTy)); 5703 } else { 5704 Lo = DAG.getNode(ISD::OR, NVT, 5705 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5706 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5707 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5708 } 5709 return true; 5710 } 5711 } 5712 5713 // Okay, the shift amount isn't constant. However, if we can tell that it is 5714 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5715 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5716 APInt KnownZero, KnownOne; 5717 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5718 5719 // If we know that if any of the high bits of the shift amount are one, then 5720 // we can do this as a couple of simple shifts. 5721 if (KnownOne.intersects(Mask)) { 5722 // Mask out the high bit, which we know is set. 5723 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5724 DAG.getConstant(~Mask, Amt.getValueType())); 5725 5726 // Expand the incoming operand to be shifted, so that we have its parts 5727 SDValue InL, InH; 5728 ExpandOp(Op, InL, InH); 5729 switch(Opc) { 5730 case ISD::SHL: 5731 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5732 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5733 return true; 5734 case ISD::SRL: 5735 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5736 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5737 return true; 5738 case ISD::SRA: 5739 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5740 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5741 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5742 return true; 5743 } 5744 } 5745 5746 // If we know that the high bits of the shift amount are all zero, then we can 5747 // do this as a couple of simple shifts. 5748 if ((KnownZero & Mask) == Mask) { 5749 // Compute 32-amt. 5750 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5751 DAG.getConstant(NVTBits, Amt.getValueType()), 5752 Amt); 5753 5754 // Expand the incoming operand to be shifted, so that we have its parts 5755 SDValue InL, InH; 5756 ExpandOp(Op, InL, InH); 5757 switch(Opc) { 5758 case ISD::SHL: 5759 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5760 Hi = DAG.getNode(ISD::OR, NVT, 5761 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5762 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5763 return true; 5764 case ISD::SRL: 5765 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5766 Lo = DAG.getNode(ISD::OR, NVT, 5767 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5768 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5769 return true; 5770 case ISD::SRA: 5771 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5772 Lo = DAG.getNode(ISD::OR, NVT, 5773 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5774 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5775 return true; 5776 } 5777 } 5778 5779 return false; 5780} 5781 5782 5783// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5784// does not fit into a register, return the lo part and set the hi part to the 5785// by-reg argument. If it does fit into a single register, return the result 5786// and leave the Hi part unset. 5787SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5788 bool isSigned, SDValue &Hi) { 5789 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5790 // The input chain to this libcall is the entry node of the function. 5791 // Legalizing the call will automatically add the previous call to the 5792 // dependence. 5793 SDValue InChain = DAG.getEntryNode(); 5794 5795 TargetLowering::ArgListTy Args; 5796 TargetLowering::ArgListEntry Entry; 5797 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5798 MVT ArgVT = Node->getOperand(i).getValueType(); 5799 const Type *ArgTy = ArgVT.getTypeForMVT(); 5800 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5801 Entry.isSExt = isSigned; 5802 Entry.isZExt = !isSigned; 5803 Args.push_back(Entry); 5804 } 5805 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5806 TLI.getPointerTy()); 5807 5808 // Splice the libcall in wherever FindInputOutputChains tells us to. 5809 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 5810 std::pair<SDValue,SDValue> CallInfo = 5811 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 5812 CallingConv::C, false, Callee, Args, DAG, 5813 Node->getDebugLoc()); 5814 5815 // Legalize the call sequence, starting with the chain. This will advance 5816 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5817 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5818 LegalizeOp(CallInfo.second); 5819 SDValue Result; 5820 switch (getTypeAction(CallInfo.first.getValueType())) { 5821 default: assert(0 && "Unknown thing"); 5822 case Legal: 5823 Result = CallInfo.first; 5824 break; 5825 case Expand: 5826 ExpandOp(CallInfo.first, Result, Hi); 5827 break; 5828 } 5829 return Result; 5830} 5831 5832/// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation. 5833/// 5834SDValue SelectionDAGLegalize:: 5835LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op, 5836 DebugLoc dl) { 5837 bool isCustom = false; 5838 SDValue Tmp1; 5839 switch (getTypeAction(Op.getValueType())) { 5840 case Legal: 5841 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5842 Op.getValueType())) { 5843 default: assert(0 && "Unknown operation action!"); 5844 case TargetLowering::Custom: 5845 isCustom = true; 5846 // FALLTHROUGH 5847 case TargetLowering::Legal: 5848 Tmp1 = LegalizeOp(Op); 5849 if (Result.getNode()) 5850 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5851 else 5852 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl, 5853 DestTy, Tmp1); 5854 if (isCustom) { 5855 Tmp1 = TLI.LowerOperation(Result, DAG); 5856 if (Tmp1.getNode()) Result = Tmp1; 5857 } 5858 break; 5859 case TargetLowering::Expand: 5860 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy, dl); 5861 break; 5862 case TargetLowering::Promote: 5863 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned, dl); 5864 break; 5865 } 5866 break; 5867 case Expand: 5868 Result = ExpandIntToFP(isSigned, DestTy, Op, dl) ; 5869 break; 5870 case Promote: 5871 Tmp1 = PromoteOp(Op); 5872 if (isSigned) { 5873 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(), 5874 Tmp1, DAG.getValueType(Op.getValueType())); 5875 } else { 5876 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, 5877 Op.getValueType()); 5878 } 5879 if (Result.getNode()) 5880 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5881 else 5882 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl, 5883 DestTy, Tmp1); 5884 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 5885 break; 5886 } 5887 return Result; 5888} 5889 5890/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5891/// 5892SDValue SelectionDAGLegalize:: 5893ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) { 5894 MVT SourceVT = Source.getValueType(); 5895 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5896 5897 // Expand unsupported int-to-fp vector casts by unrolling them. 5898 if (DestTy.isVector()) { 5899 if (!ExpandSource) 5900 return LegalizeOp(UnrollVectorOp(Source)); 5901 MVT DestEltTy = DestTy.getVectorElementType(); 5902 if (DestTy.getVectorNumElements() == 1) { 5903 SDValue Scalar = ScalarizeVectorOp(Source); 5904 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned, 5905 DestEltTy, Scalar, dl); 5906 return DAG.getNode(ISD::BUILD_VECTOR, dl, DestTy, Result); 5907 } 5908 SDValue Lo, Hi; 5909 SplitVectorOp(Source, Lo, Hi); 5910 MVT SplitDestTy = MVT::getVectorVT(DestEltTy, 5911 DestTy.getVectorNumElements() / 2); 5912 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, 5913 Lo, dl); 5914 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, 5915 Hi, dl); 5916 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult, 5917 HiResult)); 5918 } 5919 5920 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5921 if (!isSigned && SourceVT != MVT::i32) { 5922 // The integer value loaded will be incorrectly if the 'sign bit' of the 5923 // incoming integer is set. To handle this, we dynamically test to see if 5924 // it is set, and, if so, add a fudge factor. 5925 SDValue Hi; 5926 if (ExpandSource) { 5927 SDValue Lo; 5928 ExpandOp(Source, Lo, Hi); 5929 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, Lo, Hi); 5930 } else { 5931 // The comparison for the sign bit will use the entire operand. 5932 Hi = Source; 5933 } 5934 5935 // Check to see if the target has a custom way to lower this. If so, use 5936 // it. (Note we've already expanded the operand in this case.) 5937 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) { 5938 default: assert(0 && "This action not implemented for this operation!"); 5939 case TargetLowering::Legal: 5940 case TargetLowering::Expand: 5941 break; // This case is handled below. 5942 case TargetLowering::Custom: { 5943 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy, 5944 Source), DAG); 5945 if (NV.getNode()) 5946 return LegalizeOp(NV); 5947 break; // The target decided this was legal after all 5948 } 5949 } 5950 5951 // If this is unsigned, and not supported, first perform the conversion to 5952 // signed, then adjust the result if the sign bit is set. 5953 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl); 5954 5955 SDValue SignSet = DAG.getSetCC(dl, 5956 TLI.getSetCCResultType(Hi.getValueType()), 5957 Hi, DAG.getConstant(0, Hi.getValueType()), 5958 ISD::SETLT); 5959 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5960 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 5961 SignSet, Four, Zero); 5962 uint64_t FF = 0x5f800000ULL; 5963 if (TLI.isLittleEndian()) FF <<= 32; 5964 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5965 5966 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5967 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5968 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 5969 Alignment = std::min(Alignment, 4u); 5970 SDValue FudgeInReg; 5971 if (DestTy == MVT::f32) 5972 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 5973 PseudoSourceValue::getConstantPool(), 0, 5974 false, Alignment); 5975 else if (DestTy.bitsGT(MVT::f32)) 5976 // FIXME: Avoid the extend by construction the right constantpool? 5977 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, dl, DestTy, DAG.getEntryNode(), 5978 CPIdx, 5979 PseudoSourceValue::getConstantPool(), 0, 5980 MVT::f32, false, Alignment); 5981 else 5982 assert(0 && "Unexpected conversion"); 5983 5984 MVT SCVT = SignedConv.getValueType(); 5985 if (SCVT != DestTy) { 5986 // Destination type needs to be expanded as well. The FADD now we are 5987 // constructing will be expanded into a libcall. 5988 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { 5989 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); 5990 SignedConv = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, 5991 SignedConv, SignedConv.getValue(1)); 5992 } 5993 SignedConv = DAG.getNode(ISD::BIT_CONVERT, dl, DestTy, SignedConv); 5994 } 5995 return DAG.getNode(ISD::FADD, dl, DestTy, SignedConv, FudgeInReg); 5996 } 5997 5998 // Check to see if the target has a custom way to lower this. If so, use it. 5999 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 6000 default: assert(0 && "This action not implemented for this operation!"); 6001 case TargetLowering::Legal: 6002 case TargetLowering::Expand: 6003 break; // This case is handled below. 6004 case TargetLowering::Custom: { 6005 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, 6006 Source), DAG); 6007 if (NV.getNode()) 6008 return LegalizeOp(NV); 6009 break; // The target decided this was legal after all 6010 } 6011 } 6012 6013 // Expand the source, then glue it back together for the call. We must expand 6014 // the source in case it is shared (this pass of legalize must traverse it). 6015 if (ExpandSource) { 6016 SDValue SrcLo, SrcHi; 6017 ExpandOp(Source, SrcLo, SrcHi); 6018 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, SrcLo, SrcHi); 6019 } 6020 6021 RTLIB::Libcall LC = isSigned ? 6022 RTLIB::getSINTTOFP(SourceVT, DestTy) : 6023 RTLIB::getUINTTOFP(SourceVT, DestTy); 6024 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type"); 6025 6026 Source = DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source); 6027 SDValue HiPart; 6028 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart); 6029 if (Result.getValueType() != DestTy && HiPart.getNode()) 6030 Result = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, Result, HiPart); 6031 return Result; 6032} 6033 6034/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 6035/// INT_TO_FP operation of the specified operand when the target requests that 6036/// we expand it. At this point, we know that the result and operand types are 6037/// legal for the target. 6038SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 6039 SDValue Op0, 6040 MVT DestVT, 6041 DebugLoc dl) { 6042 if (Op0.getValueType() == MVT::i32) { 6043 // simple 32-bit [signed|unsigned] integer to float/double expansion 6044 6045 // Get the stack frame index of a 8 byte buffer. 6046 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 6047 6048 // word offset constant for Hi/Lo address computation 6049 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 6050 // set up Hi and Lo (into buffer) address based on endian 6051 SDValue Hi = StackSlot; 6052 SDValue Lo = DAG.getNode(ISD::ADD, dl, 6053 TLI.getPointerTy(), StackSlot,WordOff); 6054 if (TLI.isLittleEndian()) 6055 std::swap(Hi, Lo); 6056 6057 // if signed map to unsigned space 6058 SDValue Op0Mapped; 6059 if (isSigned) { 6060 // constant used to invert sign bit (signed to unsigned mapping) 6061 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 6062 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 6063 } else { 6064 Op0Mapped = Op0; 6065 } 6066 // store the lo of the constructed double - based on integer input 6067 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 6068 Op0Mapped, Lo, NULL, 0); 6069 // initial hi portion of constructed double 6070 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 6071 // store the hi of the constructed double - biased exponent 6072 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0); 6073 // load the constructed double 6074 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0); 6075 // FP constant to bias correct the final result 6076 SDValue Bias = DAG.getConstantFP(isSigned ? 6077 BitsToDouble(0x4330000080000000ULL) 6078 : BitsToDouble(0x4330000000000000ULL), 6079 MVT::f64); 6080 // subtract the bias 6081 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 6082 // final result 6083 SDValue Result; 6084 // handle final rounding 6085 if (DestVT == MVT::f64) { 6086 // do nothing 6087 Result = Sub; 6088 } else if (DestVT.bitsLT(MVT::f64)) { 6089 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 6090 DAG.getIntPtrConstant(0)); 6091 } else if (DestVT.bitsGT(MVT::f64)) { 6092 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 6093 } 6094 return Result; 6095 } 6096 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 6097 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 6098 6099 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 6100 Op0, DAG.getConstant(0, Op0.getValueType()), 6101 ISD::SETLT); 6102 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 6103 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 6104 SignSet, Four, Zero); 6105 6106 // If the sign bit of the integer is set, the large number will be treated 6107 // as a negative number. To counteract this, the dynamic code adds an 6108 // offset depending on the data type. 6109 uint64_t FF; 6110 switch (Op0.getValueType().getSimpleVT()) { 6111 default: assert(0 && "Unsupported integer type!"); 6112 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 6113 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 6114 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 6115 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 6116 } 6117 if (TLI.isLittleEndian()) FF <<= 32; 6118 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 6119 6120 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 6121 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6122 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 6123 Alignment = std::min(Alignment, 4u); 6124 SDValue FudgeInReg; 6125 if (DestVT == MVT::f32) 6126 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 6127 PseudoSourceValue::getConstantPool(), 0, 6128 false, Alignment); 6129 else { 6130 FudgeInReg = 6131 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 6132 DAG.getEntryNode(), CPIdx, 6133 PseudoSourceValue::getConstantPool(), 0, 6134 MVT::f32, false, Alignment)); 6135 } 6136 6137 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 6138} 6139 6140/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 6141/// *INT_TO_FP operation of the specified operand when the target requests that 6142/// we promote it. At this point, we know that the result and operand types are 6143/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 6144/// operation that takes a larger input. 6145SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 6146 MVT DestVT, 6147 bool isSigned, 6148 DebugLoc dl) { 6149 // First step, figure out the appropriate *INT_TO_FP operation to use. 6150 MVT NewInTy = LegalOp.getValueType(); 6151 6152 unsigned OpToUse = 0; 6153 6154 // Scan for the appropriate larger type to use. 6155 while (1) { 6156 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 6157 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 6158 6159 // If the target supports SINT_TO_FP of this type, use it. 6160 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 6161 default: break; 6162 case TargetLowering::Legal: 6163 if (!TLI.isTypeLegal(NewInTy)) 6164 break; // Can't use this datatype. 6165 // FALL THROUGH. 6166 case TargetLowering::Custom: 6167 OpToUse = ISD::SINT_TO_FP; 6168 break; 6169 } 6170 if (OpToUse) break; 6171 if (isSigned) continue; 6172 6173 // If the target supports UINT_TO_FP of this type, use it. 6174 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 6175 default: break; 6176 case TargetLowering::Legal: 6177 if (!TLI.isTypeLegal(NewInTy)) 6178 break; // Can't use this datatype. 6179 // FALL THROUGH. 6180 case TargetLowering::Custom: 6181 OpToUse = ISD::UINT_TO_FP; 6182 break; 6183 } 6184 if (OpToUse) break; 6185 6186 // Otherwise, try a larger type. 6187 } 6188 6189 // Okay, we found the operation and type to use. Zero extend our input to the 6190 // desired type then run the operation on it. 6191 return DAG.getNode(OpToUse, dl, DestVT, 6192 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 6193 dl, NewInTy, LegalOp)); 6194} 6195 6196/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 6197/// FP_TO_*INT operation of the specified operand when the target requests that 6198/// we promote it. At this point, we know that the result and operand types are 6199/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 6200/// operation that returns a larger result. 6201SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 6202 MVT DestVT, 6203 bool isSigned, 6204 DebugLoc dl) { 6205 // First step, figure out the appropriate FP_TO*INT operation to use. 6206 MVT NewOutTy = DestVT; 6207 6208 unsigned OpToUse = 0; 6209 6210 // Scan for the appropriate larger type to use. 6211 while (1) { 6212 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 6213 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 6214 6215 // If the target supports FP_TO_SINT returning this type, use it. 6216 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 6217 default: break; 6218 case TargetLowering::Legal: 6219 if (!TLI.isTypeLegal(NewOutTy)) 6220 break; // Can't use this datatype. 6221 // FALL THROUGH. 6222 case TargetLowering::Custom: 6223 OpToUse = ISD::FP_TO_SINT; 6224 break; 6225 } 6226 if (OpToUse) break; 6227 6228 // If the target supports FP_TO_UINT of this type, use it. 6229 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 6230 default: break; 6231 case TargetLowering::Legal: 6232 if (!TLI.isTypeLegal(NewOutTy)) 6233 break; // Can't use this datatype. 6234 // FALL THROUGH. 6235 case TargetLowering::Custom: 6236 OpToUse = ISD::FP_TO_UINT; 6237 break; 6238 } 6239 if (OpToUse) break; 6240 6241 // Otherwise, try a larger type. 6242 } 6243 6244 6245 // Okay, we found the operation and type to use. 6246 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 6247 6248 // If the operation produces an invalid type, it must be custom lowered. Use 6249 // the target lowering hooks to expand it. Just keep the low part of the 6250 // expanded operation, we know that we're truncating anyway. 6251 if (getTypeAction(NewOutTy) == Expand) { 6252 SmallVector<SDValue, 2> Results; 6253 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG); 6254 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!"); 6255 Operation = Results[0]; 6256 } 6257 6258 // Truncate the result of the extended FP_TO_*INT operation to the desired 6259 // size. 6260 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 6261} 6262 6263/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 6264/// 6265SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) { 6266 MVT VT = Op.getValueType(); 6267 MVT SHVT = TLI.getShiftAmountTy(); 6268 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 6269 switch (VT.getSimpleVT()) { 6270 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 6271 case MVT::i16: 6272 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 6273 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 6274 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 6275 case MVT::i32: 6276 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 6277 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 6278 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 6279 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 6280 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 6281 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 6282 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 6283 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 6284 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 6285 case MVT::i64: 6286 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 6287 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 6288 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 6289 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 6290 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 6291 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 6292 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 6293 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 6294 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 6295 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 6296 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 6297 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 6298 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 6299 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 6300 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 6301 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 6302 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 6303 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 6304 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 6305 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 6306 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 6307 } 6308} 6309 6310/// ExpandBitCount - Expand the specified bitcount instruction into operations. 6311/// 6312SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) { 6313 switch (Opc) { 6314 default: assert(0 && "Cannot expand this yet!"); 6315 case ISD::CTPOP: { 6316 static const uint64_t mask[6] = { 6317 0x5555555555555555ULL, 0x3333333333333333ULL, 6318 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 6319 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 6320 }; 6321 MVT VT = Op.getValueType(); 6322 MVT ShVT = TLI.getShiftAmountTy(); 6323 unsigned len = VT.getSizeInBits(); 6324 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 6325 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 6326 unsigned EltSize = VT.isVector() ? 6327 VT.getVectorElementType().getSizeInBits() : len; 6328 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 6329 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 6330 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 6331 DAG.getNode(ISD::AND, VT, 6332 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 6333 } 6334 return Op; 6335 } 6336 case ISD::CTLZ: { 6337 // for now, we do this: 6338 // x = x | (x >> 1); 6339 // x = x | (x >> 2); 6340 // ... 6341 // x = x | (x >>16); 6342 // x = x | (x >>32); // for 64-bit input 6343 // return popcount(~x); 6344 // 6345 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 6346 MVT VT = Op.getValueType(); 6347 MVT ShVT = TLI.getShiftAmountTy(); 6348 unsigned len = VT.getSizeInBits(); 6349 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 6350 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 6351 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 6352 } 6353 Op = DAG.getNOT(DebugLoc::getUnknownLoc(), Op, VT); 6354 return DAG.getNode(ISD::CTPOP, VT, Op); 6355 } 6356 case ISD::CTTZ: { 6357 // for now, we use: { return popcount(~x & (x - 1)); } 6358 // unless the target has ctlz but not ctpop, in which case we use: 6359 // { return 32 - nlz(~x & (x-1)); } 6360 // see also http://www.hackersdelight.org/HDcode/ntz.cc 6361 MVT VT = Op.getValueType(); 6362 SDValue Tmp3 = DAG.getNode(ISD::AND, VT, 6363 DAG.getNOT(DebugLoc::getUnknownLoc(), Op, VT), 6364 DAG.getNode(ISD::SUB, VT, Op, 6365 DAG.getConstant(1, VT))); 6366 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 6367 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 6368 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 6369 return DAG.getNode(ISD::SUB, VT, 6370 DAG.getConstant(VT.getSizeInBits(), VT), 6371 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 6372 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 6373 } 6374 } 6375} 6376 6377/// ExpandOp - Expand the specified SDValue into its two component pieces 6378/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 6379/// LegalizedNodes map is filled in for any results that are not expanded, the 6380/// ExpandedNodes map is filled in for any results that are expanded, and the 6381/// Lo/Hi values are returned. 6382void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ 6383 MVT VT = Op.getValueType(); 6384 MVT NVT = TLI.getTypeToTransformTo(VT); 6385 SDNode *Node = Op.getNode(); 6386 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 6387 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || 6388 VT.isVector()) && "Cannot expand to FP value or to larger int value!"); 6389 6390 // See if we already expanded it. 6391 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I 6392 = ExpandedNodes.find(Op); 6393 if (I != ExpandedNodes.end()) { 6394 Lo = I->second.first; 6395 Hi = I->second.second; 6396 return; 6397 } 6398 6399 switch (Node->getOpcode()) { 6400 case ISD::CopyFromReg: 6401 assert(0 && "CopyFromReg must be legal!"); 6402 case ISD::FP_ROUND_INREG: 6403 if (VT == MVT::ppcf128 && 6404 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 6405 TargetLowering::Custom) { 6406 SDValue SrcLo, SrcHi, Src; 6407 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 6408 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 6409 SDValue Result = TLI.LowerOperation( 6410 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 6411 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR); 6412 Lo = Result.getNode()->getOperand(0); 6413 Hi = Result.getNode()->getOperand(1); 6414 break; 6415 } 6416 // fall through 6417 default: 6418#ifndef NDEBUG 6419 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 6420#endif 6421 assert(0 && "Do not know how to expand this operator!"); 6422 abort(); 6423 case ISD::EXTRACT_ELEMENT: 6424 ExpandOp(Node->getOperand(0), Lo, Hi); 6425 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) 6426 return ExpandOp(Hi, Lo, Hi); 6427 return ExpandOp(Lo, Lo, Hi); 6428 case ISD::EXTRACT_VECTOR_ELT: 6429 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 6430 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 6431 return ExpandOp(Lo, Lo, Hi); 6432 case ISD::UNDEF: 6433 Lo = DAG.getNode(ISD::UNDEF, NVT); 6434 Hi = DAG.getNode(ISD::UNDEF, NVT); 6435 break; 6436 case ISD::Constant: { 6437 unsigned NVTBits = NVT.getSizeInBits(); 6438 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 6439 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 6440 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 6441 break; 6442 } 6443 case ISD::ConstantFP: { 6444 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 6445 if (CFP->getValueType(0) == MVT::ppcf128) { 6446 APInt api = CFP->getValueAPF().bitcastToAPInt(); 6447 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 6448 MVT::f64); 6449 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 6450 MVT::f64); 6451 break; 6452 } 6453 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 6454 if (getTypeAction(Lo.getValueType()) == Expand) 6455 ExpandOp(Lo, Lo, Hi); 6456 break; 6457 } 6458 case ISD::BUILD_PAIR: 6459 // Return the operands. 6460 Lo = Node->getOperand(0); 6461 Hi = Node->getOperand(1); 6462 break; 6463 6464 case ISD::MERGE_VALUES: 6465 if (Node->getNumValues() == 1) { 6466 ExpandOp(Op.getOperand(0), Lo, Hi); 6467 break; 6468 } 6469 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 6470 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 && 6471 Op.getValue(1).getValueType() == MVT::Other && 6472 "unhandled MERGE_VALUES"); 6473 ExpandOp(Op.getOperand(0), Lo, Hi); 6474 // Remember that we legalized the chain. 6475 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 6476 break; 6477 6478 case ISD::SIGN_EXTEND_INREG: 6479 ExpandOp(Node->getOperand(0), Lo, Hi); 6480 // sext_inreg the low part if needed. 6481 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 6482 6483 // The high part gets the sign extension from the lo-part. This handles 6484 // things like sextinreg V:i64 from i8. 6485 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6486 DAG.getConstant(NVT.getSizeInBits()-1, 6487 TLI.getShiftAmountTy())); 6488 break; 6489 6490 case ISD::BSWAP: { 6491 ExpandOp(Node->getOperand(0), Lo, Hi); 6492 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 6493 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 6494 Lo = TempLo; 6495 break; 6496 } 6497 6498 case ISD::CTPOP: 6499 ExpandOp(Node->getOperand(0), Lo, Hi); 6500 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 6501 DAG.getNode(ISD::CTPOP, NVT, Lo), 6502 DAG.getNode(ISD::CTPOP, NVT, Hi)); 6503 Hi = DAG.getConstant(0, NVT); 6504 break; 6505 6506 case ISD::CTLZ: { 6507 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 6508 ExpandOp(Node->getOperand(0), Lo, Hi); 6509 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 6510 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 6511 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), HLZ, BitsC, 6512 ISD::SETNE); 6513 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 6514 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 6515 6516 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 6517 Hi = DAG.getConstant(0, NVT); 6518 break; 6519 } 6520 6521 case ISD::CTTZ: { 6522 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 6523 ExpandOp(Node->getOperand(0), Lo, Hi); 6524 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 6525 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 6526 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), LTZ, BitsC, 6527 ISD::SETNE); 6528 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 6529 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 6530 6531 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 6532 Hi = DAG.getConstant(0, NVT); 6533 break; 6534 } 6535 6536 case ISD::VAARG: { 6537 SDValue Ch = Node->getOperand(0); // Legalize the chain. 6538 SDValue Ptr = Node->getOperand(1); // Legalize the pointer. 6539 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 6540 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 6541 6542 // Remember that we legalized the chain. 6543 Hi = LegalizeOp(Hi); 6544 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 6545 if (TLI.isBigEndian()) 6546 std::swap(Lo, Hi); 6547 break; 6548 } 6549 6550 case ISD::LOAD: { 6551 LoadSDNode *LD = cast<LoadSDNode>(Node); 6552 SDValue Ch = LD->getChain(); // Legalize the chain. 6553 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer. 6554 ISD::LoadExtType ExtType = LD->getExtensionType(); 6555 const Value *SV = LD->getSrcValue(); 6556 int SVOffset = LD->getSrcValueOffset(); 6557 unsigned Alignment = LD->getAlignment(); 6558 bool isVolatile = LD->isVolatile(); 6559 6560 if (ExtType == ISD::NON_EXTLOAD) { 6561 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset, 6562 isVolatile, Alignment); 6563 if (VT == MVT::f32 || VT == MVT::f64) { 6564 // f32->i32 or f64->i64 one to one expansion. 6565 // Remember that we legalized the chain. 6566 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 6567 // Recursively expand the new load. 6568 if (getTypeAction(NVT) == Expand) 6569 ExpandOp(Lo, Lo, Hi); 6570 break; 6571 } 6572 6573 // Increment the pointer to the other half. 6574 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 6575 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6576 DAG.getIntPtrConstant(IncrementSize)); 6577 SVOffset += IncrementSize; 6578 Alignment = MinAlign(Alignment, IncrementSize); 6579 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset, 6580 isVolatile, Alignment); 6581 6582 // Build a factor node to remember that this load is independent of the 6583 // other one. 6584 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6585 Hi.getValue(1)); 6586 6587 // Remember that we legalized the chain. 6588 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6589 if (TLI.isBigEndian()) 6590 std::swap(Lo, Hi); 6591 } else { 6592 MVT EVT = LD->getMemoryVT(); 6593 6594 if ((VT == MVT::f64 && EVT == MVT::f32) || 6595 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 6596 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 6597 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV, 6598 SVOffset, isVolatile, Alignment); 6599 // Remember that we legalized the chain. 6600 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1))); 6601 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 6602 break; 6603 } 6604 6605 if (EVT == NVT) 6606 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, 6607 SVOffset, isVolatile, Alignment); 6608 else 6609 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV, 6610 SVOffset, EVT, isVolatile, 6611 Alignment); 6612 6613 // Remember that we legalized the chain. 6614 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 6615 6616 if (ExtType == ISD::SEXTLOAD) { 6617 // The high part is obtained by SRA'ing all but one of the bits of the 6618 // lo part. 6619 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6620 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6621 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6622 } else if (ExtType == ISD::ZEXTLOAD) { 6623 // The high part is just a zero. 6624 Hi = DAG.getConstant(0, NVT); 6625 } else /* if (ExtType == ISD::EXTLOAD) */ { 6626 // The high part is undefined. 6627 Hi = DAG.getNode(ISD::UNDEF, NVT); 6628 } 6629 } 6630 break; 6631 } 6632 case ISD::AND: 6633 case ISD::OR: 6634 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6635 SDValue LL, LH, RL, RH; 6636 ExpandOp(Node->getOperand(0), LL, LH); 6637 ExpandOp(Node->getOperand(1), RL, RH); 6638 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 6639 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 6640 break; 6641 } 6642 case ISD::SELECT: { 6643 SDValue LL, LH, RL, RH; 6644 ExpandOp(Node->getOperand(1), LL, LH); 6645 ExpandOp(Node->getOperand(2), RL, RH); 6646 if (getTypeAction(NVT) == Expand) 6647 NVT = TLI.getTypeToExpandTo(NVT); 6648 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 6649 if (VT != MVT::f32) 6650 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 6651 break; 6652 } 6653 case ISD::SELECT_CC: { 6654 SDValue TL, TH, FL, FH; 6655 ExpandOp(Node->getOperand(2), TL, TH); 6656 ExpandOp(Node->getOperand(3), FL, FH); 6657 if (getTypeAction(NVT) == Expand) 6658 NVT = TLI.getTypeToExpandTo(NVT); 6659 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6660 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6661 if (VT != MVT::f32) 6662 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6663 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6664 break; 6665 } 6666 case ISD::ANY_EXTEND: 6667 // The low part is any extension of the input (which degenerates to a copy). 6668 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 6669 // The high part is undefined. 6670 Hi = DAG.getNode(ISD::UNDEF, NVT); 6671 break; 6672 case ISD::SIGN_EXTEND: { 6673 // The low part is just a sign extension of the input (which degenerates to 6674 // a copy). 6675 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 6676 6677 // The high part is obtained by SRA'ing all but one of the bits of the lo 6678 // part. 6679 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6680 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6681 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6682 break; 6683 } 6684 case ISD::ZERO_EXTEND: 6685 // The low part is just a zero extension of the input (which degenerates to 6686 // a copy). 6687 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 6688 6689 // The high part is just a zero. 6690 Hi = DAG.getConstant(0, NVT); 6691 break; 6692 6693 case ISD::TRUNCATE: { 6694 // The input value must be larger than this value. Expand *it*. 6695 SDValue NewLo; 6696 ExpandOp(Node->getOperand(0), NewLo, Hi); 6697 6698 // The low part is now either the right size, or it is closer. If not the 6699 // right size, make an illegal truncate so we recursively expand it. 6700 if (NewLo.getValueType() != Node->getValueType(0)) 6701 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 6702 ExpandOp(NewLo, Lo, Hi); 6703 break; 6704 } 6705 6706 case ISD::BIT_CONVERT: { 6707 SDValue Tmp; 6708 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6709 // If the target wants to, allow it to lower this itself. 6710 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6711 case Expand: assert(0 && "cannot expand FP!"); 6712 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6713 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6714 } 6715 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 6716 } 6717 6718 // f32 / f64 must be expanded to i32 / i64. 6719 if (VT == MVT::f32 || VT == MVT::f64) { 6720 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6721 if (getTypeAction(NVT) == Expand) 6722 ExpandOp(Lo, Lo, Hi); 6723 break; 6724 } 6725 6726 // If source operand will be expanded to the same type as VT, i.e. 6727 // i64 <- f64, i32 <- f32, expand the source operand instead. 6728 MVT VT0 = Node->getOperand(0).getValueType(); 6729 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6730 ExpandOp(Node->getOperand(0), Lo, Hi); 6731 break; 6732 } 6733 6734 // Turn this into a load/store pair by default. 6735 if (Tmp.getNode() == 0) 6736 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 6737 6738 ExpandOp(Tmp, Lo, Hi); 6739 break; 6740 } 6741 6742 case ISD::READCYCLECOUNTER: { 6743 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6744 TargetLowering::Custom && 6745 "Must custom expand ReadCycleCounter"); 6746 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6747 assert(Tmp.getNode() && "Node must be custom expanded!"); 6748 ExpandOp(Tmp.getValue(0), Lo, Hi); 6749 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6750 LegalizeOp(Tmp.getValue(1))); 6751 break; 6752 } 6753 6754 case ISD::ATOMIC_CMP_SWAP: { 6755 // This operation does not need a loop. 6756 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6757 assert(Tmp.getNode() && "Node must be custom expanded!"); 6758 ExpandOp(Tmp.getValue(0), Lo, Hi); 6759 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6760 LegalizeOp(Tmp.getValue(1))); 6761 break; 6762 } 6763 6764 case ISD::ATOMIC_LOAD_ADD: 6765 case ISD::ATOMIC_LOAD_SUB: 6766 case ISD::ATOMIC_LOAD_AND: 6767 case ISD::ATOMIC_LOAD_OR: 6768 case ISD::ATOMIC_LOAD_XOR: 6769 case ISD::ATOMIC_LOAD_NAND: 6770 case ISD::ATOMIC_SWAP: { 6771 // These operations require a loop to be generated. We can't do that yet, 6772 // so substitute a target-dependent pseudo and expand that later. 6773 SDValue In2Lo, In2Hi, In2; 6774 ExpandOp(Op.getOperand(2), In2Lo, In2Hi); 6775 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi); 6776 AtomicSDNode* Anode = cast<AtomicSDNode>(Node); 6777 SDValue Replace = 6778 DAG.getAtomic(Op.getOpcode(), Anode->getMemoryVT(), 6779 Op.getOperand(0), Op.getOperand(1), In2, 6780 Anode->getSrcValue(), Anode->getAlignment()); 6781 SDValue Result = TLI.LowerOperation(Replace, DAG); 6782 ExpandOp(Result.getValue(0), Lo, Hi); 6783 // Remember that we legalized the chain. 6784 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1))); 6785 break; 6786 } 6787 6788 // These operators cannot be expanded directly, emit them as calls to 6789 // library functions. 6790 case ISD::FP_TO_SINT: { 6791 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6792 SDValue Op; 6793 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6794 case Expand: assert(0 && "cannot expand FP!"); 6795 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6796 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6797 } 6798 6799 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6800 6801 // Now that the custom expander is done, expand the result, which is still 6802 // VT. 6803 if (Op.getNode()) { 6804 ExpandOp(Op, Lo, Hi); 6805 break; 6806 } 6807 } 6808 6809 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(), 6810 VT); 6811 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!"); 6812 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6813 break; 6814 } 6815 6816 case ISD::FP_TO_UINT: { 6817 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6818 SDValue Op; 6819 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6820 case Expand: assert(0 && "cannot expand FP!"); 6821 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6822 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6823 } 6824 6825 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6826 6827 // Now that the custom expander is done, expand the result. 6828 if (Op.getNode()) { 6829 ExpandOp(Op, Lo, Hi); 6830 break; 6831 } 6832 } 6833 6834 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(), 6835 VT); 6836 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 6837 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6838 break; 6839 } 6840 6841 case ISD::SHL: { 6842 // If the target wants custom lowering, do so. 6843 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6844 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6845 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6846 Op = TLI.LowerOperation(Op, DAG); 6847 if (Op.getNode()) { 6848 // Now that the custom expander is done, expand the result, which is 6849 // still VT. 6850 ExpandOp(Op, Lo, Hi); 6851 break; 6852 } 6853 } 6854 6855 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6856 // this X << 1 as X+X. 6857 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6858 if (ShAmt->getAPIntValue() == 1 && 6859 TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) && 6860 TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) { 6861 SDValue LoOps[2], HiOps[3]; 6862 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6863 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6864 LoOps[1] = LoOps[0]; 6865 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6866 6867 HiOps[1] = HiOps[0]; 6868 HiOps[2] = Lo.getValue(1); 6869 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6870 break; 6871 } 6872 } 6873 6874 // If we can emit an efficient shift operation, do so now. 6875 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6876 break; 6877 6878 // If this target supports SHL_PARTS, use it. 6879 TargetLowering::LegalizeAction Action = 6880 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6881 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6882 Action == TargetLowering::Custom) { 6883 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6884 break; 6885 } 6886 6887 // Otherwise, emit a libcall. 6888 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6889 break; 6890 } 6891 6892 case ISD::SRA: { 6893 // If the target wants custom lowering, do so. 6894 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6895 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6896 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6897 Op = TLI.LowerOperation(Op, DAG); 6898 if (Op.getNode()) { 6899 // Now that the custom expander is done, expand the result, which is 6900 // still VT. 6901 ExpandOp(Op, Lo, Hi); 6902 break; 6903 } 6904 } 6905 6906 // If we can emit an efficient shift operation, do so now. 6907 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6908 break; 6909 6910 // If this target supports SRA_PARTS, use it. 6911 TargetLowering::LegalizeAction Action = 6912 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6913 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6914 Action == TargetLowering::Custom) { 6915 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6916 break; 6917 } 6918 6919 // Otherwise, emit a libcall. 6920 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6921 break; 6922 } 6923 6924 case ISD::SRL: { 6925 // If the target wants custom lowering, do so. 6926 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6927 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6928 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6929 Op = TLI.LowerOperation(Op, DAG); 6930 if (Op.getNode()) { 6931 // Now that the custom expander is done, expand the result, which is 6932 // still VT. 6933 ExpandOp(Op, Lo, Hi); 6934 break; 6935 } 6936 } 6937 6938 // If we can emit an efficient shift operation, do so now. 6939 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6940 break; 6941 6942 // If this target supports SRL_PARTS, use it. 6943 TargetLowering::LegalizeAction Action = 6944 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6945 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6946 Action == TargetLowering::Custom) { 6947 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6948 break; 6949 } 6950 6951 // Otherwise, emit a libcall. 6952 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6953 break; 6954 } 6955 6956 case ISD::ADD: 6957 case ISD::SUB: { 6958 // If the target wants to custom expand this, let them. 6959 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6960 TargetLowering::Custom) { 6961 SDValue Result = TLI.LowerOperation(Op, DAG); 6962 if (Result.getNode()) { 6963 ExpandOp(Result, Lo, Hi); 6964 break; 6965 } 6966 } 6967 // Expand the subcomponents. 6968 SDValue LHSL, LHSH, RHSL, RHSH; 6969 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6970 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6971 SDValue LoOps[2], HiOps[3]; 6972 LoOps[0] = LHSL; 6973 LoOps[1] = RHSL; 6974 HiOps[0] = LHSH; 6975 HiOps[1] = RHSH; 6976 6977 //cascaded check to see if any smaller size has a a carry flag. 6978 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC; 6979 bool hasCarry = false; 6980 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) { 6981 MVT AVT = MVT::getIntegerVT(BitSize); 6982 if (TLI.isOperationLegalOrCustom(OpV, AVT)) { 6983 hasCarry = true; 6984 break; 6985 } 6986 } 6987 6988 if(hasCarry) { 6989 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6990 if (Node->getOpcode() == ISD::ADD) { 6991 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6992 HiOps[2] = Lo.getValue(1); 6993 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6994 } else { 6995 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6996 HiOps[2] = Lo.getValue(1); 6997 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6998 } 6999 break; 7000 } else { 7001 if (Node->getOpcode() == ISD::ADD) { 7002 Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2); 7003 Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2); 7004 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(NVT), 7005 Lo, LoOps[0], ISD::SETULT); 7006 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, 7007 DAG.getConstant(1, NVT), 7008 DAG.getConstant(0, NVT)); 7009 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(NVT), 7010 Lo, LoOps[1], ISD::SETULT); 7011 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2, 7012 DAG.getConstant(1, NVT), 7013 Carry1); 7014 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2); 7015 } else { 7016 Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2); 7017 Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2); 7018 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT); 7019 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp, 7020 DAG.getConstant(1, NVT), 7021 DAG.getConstant(0, NVT)); 7022 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow); 7023 } 7024 break; 7025 } 7026 } 7027 7028 case ISD::ADDC: 7029 case ISD::SUBC: { 7030 // Expand the subcomponents. 7031 SDValue LHSL, LHSH, RHSL, RHSH; 7032 ExpandOp(Node->getOperand(0), LHSL, LHSH); 7033 ExpandOp(Node->getOperand(1), RHSL, RHSH); 7034 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 7035 SDValue LoOps[2] = { LHSL, RHSL }; 7036 SDValue HiOps[3] = { LHSH, RHSH }; 7037 7038 if (Node->getOpcode() == ISD::ADDC) { 7039 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 7040 HiOps[2] = Lo.getValue(1); 7041 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 7042 } else { 7043 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 7044 HiOps[2] = Lo.getValue(1); 7045 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 7046 } 7047 // Remember that we legalized the flag. 7048 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 7049 break; 7050 } 7051 case ISD::ADDE: 7052 case ISD::SUBE: { 7053 // Expand the subcomponents. 7054 SDValue LHSL, LHSH, RHSL, RHSH; 7055 ExpandOp(Node->getOperand(0), LHSL, LHSH); 7056 ExpandOp(Node->getOperand(1), RHSL, RHSH); 7057 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 7058 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 7059 SDValue HiOps[3] = { LHSH, RHSH }; 7060 7061 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 7062 HiOps[2] = Lo.getValue(1); 7063 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 7064 7065 // Remember that we legalized the flag. 7066 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 7067 break; 7068 } 7069 case ISD::MUL: { 7070 // If the target wants to custom expand this, let them. 7071 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 7072 SDValue New = TLI.LowerOperation(Op, DAG); 7073 if (New.getNode()) { 7074 ExpandOp(New, Lo, Hi); 7075 break; 7076 } 7077 } 7078 7079 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 7080 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 7081 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 7082 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 7083 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 7084 SDValue LL, LH, RL, RH; 7085 ExpandOp(Node->getOperand(0), LL, LH); 7086 ExpandOp(Node->getOperand(1), RL, RH); 7087 unsigned OuterBitSize = Op.getValueSizeInBits(); 7088 unsigned InnerBitSize = RH.getValueSizeInBits(); 7089 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 7090 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 7091 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 7092 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 7093 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 7094 // The inputs are both zero-extended. 7095 if (HasUMUL_LOHI) { 7096 // We can emit a umul_lohi. 7097 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 7098 Hi = SDValue(Lo.getNode(), 1); 7099 break; 7100 } 7101 if (HasMULHU) { 7102 // We can emit a mulhu+mul. 7103 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 7104 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 7105 break; 7106 } 7107 } 7108 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 7109 // The input values are both sign-extended. 7110 if (HasSMUL_LOHI) { 7111 // We can emit a smul_lohi. 7112 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 7113 Hi = SDValue(Lo.getNode(), 1); 7114 break; 7115 } 7116 if (HasMULHS) { 7117 // We can emit a mulhs+mul. 7118 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 7119 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 7120 break; 7121 } 7122 } 7123 if (HasUMUL_LOHI) { 7124 // Lo,Hi = umul LHS, RHS. 7125 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 7126 DAG.getVTList(NVT, NVT), LL, RL); 7127 Lo = UMulLOHI; 7128 Hi = UMulLOHI.getValue(1); 7129 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 7130 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 7131 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 7132 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 7133 break; 7134 } 7135 if (HasMULHU) { 7136 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 7137 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 7138 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 7139 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 7140 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 7141 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 7142 break; 7143 } 7144 } 7145 7146 // If nothing else, we can make a libcall. 7147 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 7148 break; 7149 } 7150 case ISD::SDIV: 7151 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 7152 break; 7153 case ISD::UDIV: 7154 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 7155 break; 7156 case ISD::SREM: 7157 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 7158 break; 7159 case ISD::UREM: 7160 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 7161 break; 7162 7163 case ISD::FADD: 7164 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 7165 RTLIB::ADD_F64, 7166 RTLIB::ADD_F80, 7167 RTLIB::ADD_PPCF128), 7168 Node, false, Hi); 7169 break; 7170 case ISD::FSUB: 7171 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 7172 RTLIB::SUB_F64, 7173 RTLIB::SUB_F80, 7174 RTLIB::SUB_PPCF128), 7175 Node, false, Hi); 7176 break; 7177 case ISD::FMUL: 7178 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 7179 RTLIB::MUL_F64, 7180 RTLIB::MUL_F80, 7181 RTLIB::MUL_PPCF128), 7182 Node, false, Hi); 7183 break; 7184 case ISD::FDIV: 7185 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 7186 RTLIB::DIV_F64, 7187 RTLIB::DIV_F80, 7188 RTLIB::DIV_PPCF128), 7189 Node, false, Hi); 7190 break; 7191 case ISD::FP_EXTEND: { 7192 if (VT == MVT::ppcf128) { 7193 assert(Node->getOperand(0).getValueType()==MVT::f32 || 7194 Node->getOperand(0).getValueType()==MVT::f64); 7195 const uint64_t zero = 0; 7196 if (Node->getOperand(0).getValueType()==MVT::f32) 7197 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 7198 else 7199 Hi = Node->getOperand(0); 7200 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7201 break; 7202 } 7203 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT); 7204 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!"); 7205 Lo = ExpandLibCall(LC, Node, true, Hi); 7206 break; 7207 } 7208 case ISD::FP_ROUND: { 7209 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(), 7210 VT); 7211 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!"); 7212 Lo = ExpandLibCall(LC, Node, true, Hi); 7213 break; 7214 } 7215 case ISD::FSQRT: 7216 case ISD::FSIN: 7217 case ISD::FCOS: 7218 case ISD::FLOG: 7219 case ISD::FLOG2: 7220 case ISD::FLOG10: 7221 case ISD::FEXP: 7222 case ISD::FEXP2: 7223 case ISD::FTRUNC: 7224 case ISD::FFLOOR: 7225 case ISD::FCEIL: 7226 case ISD::FRINT: 7227 case ISD::FNEARBYINT: 7228 case ISD::FPOW: 7229 case ISD::FPOWI: { 7230 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 7231 switch(Node->getOpcode()) { 7232 case ISD::FSQRT: 7233 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 7234 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 7235 break; 7236 case ISD::FSIN: 7237 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 7238 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 7239 break; 7240 case ISD::FCOS: 7241 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 7242 RTLIB::COS_F80, RTLIB::COS_PPCF128); 7243 break; 7244 case ISD::FLOG: 7245 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64, 7246 RTLIB::LOG_F80, RTLIB::LOG_PPCF128); 7247 break; 7248 case ISD::FLOG2: 7249 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 7250 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128); 7251 break; 7252 case ISD::FLOG10: 7253 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 7254 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128); 7255 break; 7256 case ISD::FEXP: 7257 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64, 7258 RTLIB::EXP_F80, RTLIB::EXP_PPCF128); 7259 break; 7260 case ISD::FEXP2: 7261 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 7262 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128); 7263 break; 7264 case ISD::FTRUNC: 7265 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 7266 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 7267 break; 7268 case ISD::FFLOOR: 7269 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 7270 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 7271 break; 7272 case ISD::FCEIL: 7273 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 7274 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 7275 break; 7276 case ISD::FRINT: 7277 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 7278 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 7279 break; 7280 case ISD::FNEARBYINT: 7281 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 7282 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 7283 break; 7284 case ISD::FPOW: 7285 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 7286 RTLIB::POW_PPCF128); 7287 break; 7288 case ISD::FPOWI: 7289 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80, 7290 RTLIB::POWI_PPCF128); 7291 break; 7292 default: assert(0 && "Unreachable!"); 7293 } 7294 Lo = ExpandLibCall(LC, Node, false, Hi); 7295 break; 7296 } 7297 case ISD::FABS: { 7298 if (VT == MVT::ppcf128) { 7299 SDValue Tmp; 7300 ExpandOp(Node->getOperand(0), Lo, Tmp); 7301 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 7302 // lo = hi==fabs(hi) ? lo : -lo; 7303 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 7304 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 7305 DAG.getCondCode(ISD::SETEQ)); 7306 break; 7307 } 7308 SDValue Mask = (VT == MVT::f64) 7309 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 7310 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 7311 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 7312 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 7313 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 7314 if (getTypeAction(NVT) == Expand) 7315 ExpandOp(Lo, Lo, Hi); 7316 break; 7317 } 7318 case ISD::FNEG: { 7319 if (VT == MVT::ppcf128) { 7320 ExpandOp(Node->getOperand(0), Lo, Hi); 7321 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 7322 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 7323 break; 7324 } 7325 SDValue Mask = (VT == MVT::f64) 7326 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 7327 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 7328 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 7329 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 7330 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 7331 if (getTypeAction(NVT) == Expand) 7332 ExpandOp(Lo, Lo, Hi); 7333 break; 7334 } 7335 case ISD::FCOPYSIGN: { 7336 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 7337 if (getTypeAction(NVT) == Expand) 7338 ExpandOp(Lo, Lo, Hi); 7339 break; 7340 } 7341 case ISD::SINT_TO_FP: 7342 case ISD::UINT_TO_FP: { 7343 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 7344 MVT SrcVT = Node->getOperand(0).getValueType(); 7345 7346 // Promote the operand if needed. Do this before checking for 7347 // ppcf128 so conversions of i16 and i8 work. 7348 if (getTypeAction(SrcVT) == Promote) { 7349 SDValue Tmp = PromoteOp(Node->getOperand(0)); 7350 Tmp = isSigned 7351 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 7352 DAG.getValueType(SrcVT)) 7353 : DAG.getZeroExtendInReg(Tmp, SrcVT); 7354 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode(); 7355 SrcVT = Node->getOperand(0).getValueType(); 7356 } 7357 7358 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 7359 static const uint64_t zero = 0; 7360 if (isSigned) { 7361 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 7362 Node->getOperand(0))); 7363 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7364 } else { 7365 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 7366 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 7367 Node->getOperand(0))); 7368 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7369 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 7370 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 7371 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 7372 DAG.getConstant(0, MVT::i32), 7373 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 7374 DAG.getConstantFP( 7375 APFloat(APInt(128, 2, TwoE32)), 7376 MVT::ppcf128)), 7377 Hi, 7378 DAG.getCondCode(ISD::SETLT)), 7379 Lo, Hi); 7380 } 7381 break; 7382 } 7383 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 7384 // si64->ppcf128 done by libcall, below 7385 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 7386 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 7387 Lo, Hi); 7388 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 7389 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 7390 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 7391 DAG.getConstant(0, MVT::i64), 7392 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 7393 DAG.getConstantFP( 7394 APFloat(APInt(128, 2, TwoE64)), 7395 MVT::ppcf128)), 7396 Hi, 7397 DAG.getCondCode(ISD::SETLT)), 7398 Lo, Hi); 7399 break; 7400 } 7401 7402 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 7403 Node->getOperand(0), Node->getDebugLoc()); 7404 if (getTypeAction(Lo.getValueType()) == Expand) 7405 // float to i32 etc. can be 'expanded' to a single node. 7406 ExpandOp(Lo, Lo, Hi); 7407 break; 7408 } 7409 } 7410 7411 // Make sure the resultant values have been legalized themselves, unless this 7412 // is a type that requires multi-step expansion. 7413 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 7414 Lo = LegalizeOp(Lo); 7415 if (Hi.getNode()) 7416 // Don't legalize the high part if it is expanded to a single node. 7417 Hi = LegalizeOp(Hi); 7418 } 7419 7420 // Remember in a map if the values will be reused later. 7421 bool isNew = 7422 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7423 assert(isNew && "Value already expanded?!?"); 7424 isNew = isNew; 7425} 7426 7427/// SplitVectorOp - Given an operand of vector type, break it down into 7428/// two smaller values, still of vector type. 7429void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo, 7430 SDValue &Hi) { 7431 assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); 7432 SDNode *Node = Op.getNode(); 7433 DebugLoc dl = Node->getDebugLoc(); 7434 unsigned NumElements = Op.getValueType().getVectorNumElements(); 7435 assert(NumElements > 1 && "Cannot split a single element vector!"); 7436 7437 MVT NewEltVT = Op.getValueType().getVectorElementType(); 7438 7439 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 7440 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 7441 7442 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); 7443 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); 7444 7445 // See if we already split it. 7446 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I 7447 = SplitNodes.find(Op); 7448 if (I != SplitNodes.end()) { 7449 Lo = I->second.first; 7450 Hi = I->second.second; 7451 return; 7452 } 7453 7454 switch (Node->getOpcode()) { 7455 default: 7456#ifndef NDEBUG 7457 Node->dump(&DAG); 7458#endif 7459 assert(0 && "Unhandled operation in SplitVectorOp!"); 7460 case ISD::UNDEF: 7461 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 7462 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 7463 break; 7464 case ISD::BUILD_PAIR: 7465 Lo = Node->getOperand(0); 7466 Hi = Node->getOperand(1); 7467 break; 7468 case ISD::INSERT_VECTOR_ELT: { 7469 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 7470 SplitVectorOp(Node->getOperand(0), Lo, Hi); 7471 unsigned Index = Idx->getZExtValue(); 7472 SDValue ScalarOp = Node->getOperand(1); 7473 if (Index < NewNumElts_Lo) 7474 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 7475 DAG.getIntPtrConstant(Index)); 7476 else 7477 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 7478 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 7479 break; 7480 } 7481 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 7482 Node->getOperand(1), 7483 Node->getOperand(2), dl); 7484 SplitVectorOp(Tmp, Lo, Hi); 7485 break; 7486 } 7487 case ISD::VECTOR_SHUFFLE: { 7488 // Build the low part. 7489 SDValue Mask = Node->getOperand(2); 7490 SmallVector<SDValue, 8> Ops; 7491 MVT PtrVT = TLI.getPointerTy(); 7492 7493 // Insert all of the elements from the input that are needed. We use 7494 // buildvector of extractelement here because the input vectors will have 7495 // to be legalized, so this makes the code simpler. 7496 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 7497 SDValue IdxNode = Mask.getOperand(i); 7498 if (IdxNode.getOpcode() == ISD::UNDEF) { 7499 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 7500 continue; 7501 } 7502 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); 7503 SDValue InVec = Node->getOperand(0); 7504 if (Idx >= NumElements) { 7505 InVec = Node->getOperand(1); 7506 Idx -= NumElements; 7507 } 7508 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 7509 DAG.getConstant(Idx, PtrVT))); 7510 } 7511 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 7512 Ops.clear(); 7513 7514 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 7515 SDValue IdxNode = Mask.getOperand(i); 7516 if (IdxNode.getOpcode() == ISD::UNDEF) { 7517 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 7518 continue; 7519 } 7520 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); 7521 SDValue InVec = Node->getOperand(0); 7522 if (Idx >= NumElements) { 7523 InVec = Node->getOperand(1); 7524 Idx -= NumElements; 7525 } 7526 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 7527 DAG.getConstant(Idx, PtrVT))); 7528 } 7529 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size()); 7530 break; 7531 } 7532 case ISD::BUILD_VECTOR: { 7533 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 7534 Node->op_begin()+NewNumElts_Lo); 7535 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 7536 7537 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 7538 Node->op_end()); 7539 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 7540 break; 7541 } 7542 case ISD::CONCAT_VECTORS: { 7543 // FIXME: Handle non-power-of-two vectors? 7544 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 7545 if (NewNumSubvectors == 1) { 7546 Lo = Node->getOperand(0); 7547 Hi = Node->getOperand(1); 7548 } else { 7549 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 7550 Node->op_begin()+NewNumSubvectors); 7551 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 7552 7553 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors, 7554 Node->op_end()); 7555 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 7556 } 7557 break; 7558 } 7559 case ISD::EXTRACT_SUBVECTOR: { 7560 SDValue Vec = Op.getOperand(0); 7561 SDValue Idx = Op.getOperand(1); 7562 MVT IdxVT = Idx.getValueType(); 7563 7564 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Lo, Vec, Idx); 7565 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx); 7566 if (CIdx) { 7567 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, 7568 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo, 7569 IdxVT)); 7570 } else { 7571 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx, 7572 DAG.getConstant(NewNumElts_Lo, IdxVT)); 7573 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, Idx); 7574 } 7575 break; 7576 } 7577 case ISD::SELECT: { 7578 SDValue Cond = Node->getOperand(0); 7579 7580 SDValue LL, LH, RL, RH; 7581 SplitVectorOp(Node->getOperand(1), LL, LH); 7582 SplitVectorOp(Node->getOperand(2), RL, RH); 7583 7584 if (Cond.getValueType().isVector()) { 7585 // Handle a vector merge. 7586 SDValue CL, CH; 7587 SplitVectorOp(Cond, CL, CH); 7588 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 7589 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 7590 } else { 7591 // Handle a simple select with vector operands. 7592 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 7593 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 7594 } 7595 break; 7596 } 7597 case ISD::SELECT_CC: { 7598 SDValue CondLHS = Node->getOperand(0); 7599 SDValue CondRHS = Node->getOperand(1); 7600 SDValue CondCode = Node->getOperand(4); 7601 7602 SDValue LL, LH, RL, RH; 7603 SplitVectorOp(Node->getOperand(2), LL, LH); 7604 SplitVectorOp(Node->getOperand(3), RL, RH); 7605 7606 // Handle a simple select with vector operands. 7607 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS, 7608 LL, RL, CondCode); 7609 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS, 7610 LH, RH, CondCode); 7611 break; 7612 } 7613 case ISD::VSETCC: { 7614 SDValue LL, LH, RL, RH; 7615 SplitVectorOp(Node->getOperand(0), LL, LH); 7616 SplitVectorOp(Node->getOperand(1), RL, RH); 7617 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2)); 7618 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2)); 7619 break; 7620 } 7621 case ISD::ADD: 7622 case ISD::SUB: 7623 case ISD::MUL: 7624 case ISD::FADD: 7625 case ISD::FSUB: 7626 case ISD::FMUL: 7627 case ISD::SDIV: 7628 case ISD::UDIV: 7629 case ISD::FDIV: 7630 case ISD::FPOW: 7631 case ISD::AND: 7632 case ISD::OR: 7633 case ISD::XOR: 7634 case ISD::UREM: 7635 case ISD::SREM: 7636 case ISD::FREM: 7637 case ISD::SHL: 7638 case ISD::SRA: 7639 case ISD::SRL: { 7640 SDValue LL, LH, RL, RH; 7641 SplitVectorOp(Node->getOperand(0), LL, LH); 7642 SplitVectorOp(Node->getOperand(1), RL, RH); 7643 7644 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 7645 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 7646 break; 7647 } 7648 case ISD::FP_ROUND: 7649 case ISD::FPOWI: { 7650 SDValue L, H; 7651 SplitVectorOp(Node->getOperand(0), L, H); 7652 7653 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 7654 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 7655 break; 7656 } 7657 case ISD::CTTZ: 7658 case ISD::CTLZ: 7659 case ISD::CTPOP: 7660 case ISD::FNEG: 7661 case ISD::FABS: 7662 case ISD::FSQRT: 7663 case ISD::FSIN: 7664 case ISD::FCOS: 7665 case ISD::FLOG: 7666 case ISD::FLOG2: 7667 case ISD::FLOG10: 7668 case ISD::FEXP: 7669 case ISD::FEXP2: 7670 case ISD::FP_TO_SINT: 7671 case ISD::FP_TO_UINT: 7672 case ISD::SINT_TO_FP: 7673 case ISD::UINT_TO_FP: 7674 case ISD::TRUNCATE: 7675 case ISD::ANY_EXTEND: 7676 case ISD::SIGN_EXTEND: 7677 case ISD::ZERO_EXTEND: 7678 case ISD::FP_EXTEND: { 7679 SDValue L, H; 7680 SplitVectorOp(Node->getOperand(0), L, H); 7681 7682 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 7683 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 7684 break; 7685 } 7686 case ISD::CONVERT_RNDSAT: { 7687 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 7688 SDValue L, H; 7689 SplitVectorOp(Node->getOperand(0), L, H); 7690 SDValue DTyOpL = DAG.getValueType(NewVT_Lo); 7691 SDValue DTyOpH = DAG.getValueType(NewVT_Hi); 7692 SDValue STyOpL = DAG.getValueType(L.getValueType()); 7693 SDValue STyOpH = DAG.getValueType(H.getValueType()); 7694 7695 SDValue RndOp = Node->getOperand(3); 7696 SDValue SatOp = Node->getOperand(4); 7697 7698 Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL, 7699 RndOp, SatOp, CvtCode); 7700 Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH, 7701 RndOp, SatOp, CvtCode); 7702 break; 7703 } 7704 case ISD::LOAD: { 7705 LoadSDNode *LD = cast<LoadSDNode>(Node); 7706 SDValue Ch = LD->getChain(); 7707 SDValue Ptr = LD->getBasePtr(); 7708 ISD::LoadExtType ExtType = LD->getExtensionType(); 7709 const Value *SV = LD->getSrcValue(); 7710 int SVOffset = LD->getSrcValueOffset(); 7711 MVT MemoryVT = LD->getMemoryVT(); 7712 unsigned Alignment = LD->getAlignment(); 7713 bool isVolatile = LD->isVolatile(); 7714 7715 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7716 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); 7717 7718 MVT MemNewEltVT = MemoryVT.getVectorElementType(); 7719 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo); 7720 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi); 7721 7722 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, 7723 NewVT_Lo, Ch, Ptr, Offset, 7724 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment); 7725 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8; 7726 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 7727 DAG.getIntPtrConstant(IncrementSize)); 7728 SVOffset += IncrementSize; 7729 Alignment = MinAlign(Alignment, IncrementSize); 7730 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, 7731 NewVT_Hi, Ch, Ptr, Offset, 7732 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment); 7733 7734 // Build a factor node to remember that this load is independent of the 7735 // other one. 7736 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 7737 Hi.getValue(1)); 7738 7739 // Remember that we legalized the chain. 7740 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 7741 break; 7742 } 7743 case ISD::BIT_CONVERT: { 7744 // We know the result is a vector. The input may be either a vector or a 7745 // scalar value. 7746 SDValue InOp = Node->getOperand(0); 7747 if (!InOp.getValueType().isVector() || 7748 InOp.getValueType().getVectorNumElements() == 1) { 7749 // The input is a scalar or single-element vector. 7750 // Lower to a store/load so that it can be split. 7751 // FIXME: this could be improved probably. 7752 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment( 7753 Op.getValueType().getTypeForMVT()); 7754 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign); 7755 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex(); 7756 7757 SDValue St = DAG.getStore(DAG.getEntryNode(), 7758 InOp, Ptr, 7759 PseudoSourceValue::getFixedStack(FI), 0); 7760 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 7761 PseudoSourceValue::getFixedStack(FI), 0); 7762 } 7763 // Split the vector and convert each of the pieces now. 7764 SplitVectorOp(InOp, Lo, Hi); 7765 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 7766 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 7767 break; 7768 } 7769 } 7770 7771 // Remember in a map if the values will be reused later. 7772 bool isNew = 7773 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7774 assert(isNew && "Value already split?!?"); 7775 isNew = isNew; 7776} 7777 7778 7779/// ScalarizeVectorOp - Given an operand of single-element vector type 7780/// (e.g. v1f32), convert it into the equivalent operation that returns a 7781/// scalar (e.g. f32) value. 7782SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) { 7783 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); 7784 SDNode *Node = Op.getNode(); 7785 MVT NewVT = Op.getValueType().getVectorElementType(); 7786 assert(Op.getValueType().getVectorNumElements() == 1); 7787 7788 // See if we already scalarized it. 7789 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op); 7790 if (I != ScalarizedNodes.end()) return I->second; 7791 7792 SDValue Result; 7793 switch (Node->getOpcode()) { 7794 default: 7795#ifndef NDEBUG 7796 Node->dump(&DAG); cerr << "\n"; 7797#endif 7798 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7799 case ISD::ADD: 7800 case ISD::FADD: 7801 case ISD::SUB: 7802 case ISD::FSUB: 7803 case ISD::MUL: 7804 case ISD::FMUL: 7805 case ISD::SDIV: 7806 case ISD::UDIV: 7807 case ISD::FDIV: 7808 case ISD::SREM: 7809 case ISD::UREM: 7810 case ISD::FREM: 7811 case ISD::FPOW: 7812 case ISD::AND: 7813 case ISD::OR: 7814 case ISD::XOR: 7815 Result = DAG.getNode(Node->getOpcode(), 7816 NewVT, 7817 ScalarizeVectorOp(Node->getOperand(0)), 7818 ScalarizeVectorOp(Node->getOperand(1))); 7819 break; 7820 case ISD::FNEG: 7821 case ISD::FABS: 7822 case ISD::FSQRT: 7823 case ISD::FSIN: 7824 case ISD::FCOS: 7825 case ISD::FLOG: 7826 case ISD::FLOG2: 7827 case ISD::FLOG10: 7828 case ISD::FEXP: 7829 case ISD::FEXP2: 7830 case ISD::FP_TO_SINT: 7831 case ISD::FP_TO_UINT: 7832 case ISD::SINT_TO_FP: 7833 case ISD::UINT_TO_FP: 7834 case ISD::SIGN_EXTEND: 7835 case ISD::ZERO_EXTEND: 7836 case ISD::ANY_EXTEND: 7837 case ISD::TRUNCATE: 7838 case ISD::FP_EXTEND: 7839 Result = DAG.getNode(Node->getOpcode(), 7840 NewVT, 7841 ScalarizeVectorOp(Node->getOperand(0))); 7842 break; 7843 case ISD::CONVERT_RNDSAT: { 7844 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0)); 7845 Result = DAG.getConvertRndSat(NewVT, Op0, 7846 DAG.getValueType(NewVT), 7847 DAG.getValueType(Op0.getValueType()), 7848 Node->getOperand(3), 7849 Node->getOperand(4), 7850 cast<CvtRndSatSDNode>(Node)->getCvtCode()); 7851 break; 7852 } 7853 case ISD::FPOWI: 7854 case ISD::FP_ROUND: 7855 Result = DAG.getNode(Node->getOpcode(), 7856 NewVT, 7857 ScalarizeVectorOp(Node->getOperand(0)), 7858 Node->getOperand(1)); 7859 break; 7860 case ISD::LOAD: { 7861 LoadSDNode *LD = cast<LoadSDNode>(Node); 7862 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7863 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7864 ISD::LoadExtType ExtType = LD->getExtensionType(); 7865 const Value *SV = LD->getSrcValue(); 7866 int SVOffset = LD->getSrcValueOffset(); 7867 MVT MemoryVT = LD->getMemoryVT(); 7868 unsigned Alignment = LD->getAlignment(); 7869 bool isVolatile = LD->isVolatile(); 7870 7871 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7872 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); 7873 7874 Result = DAG.getLoad(ISD::UNINDEXED, ExtType, 7875 NewVT, Ch, Ptr, Offset, SV, SVOffset, 7876 MemoryVT.getVectorElementType(), 7877 isVolatile, Alignment); 7878 7879 // Remember that we legalized the chain. 7880 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7881 break; 7882 } 7883 case ISD::BUILD_VECTOR: 7884 Result = Node->getOperand(0); 7885 break; 7886 case ISD::INSERT_VECTOR_ELT: 7887 // Returning the inserted scalar element. 7888 Result = Node->getOperand(1); 7889 break; 7890 case ISD::CONCAT_VECTORS: 7891 assert(Node->getOperand(0).getValueType() == NewVT && 7892 "Concat of non-legal vectors not yet supported!"); 7893 Result = Node->getOperand(0); 7894 break; 7895 case ISD::VECTOR_SHUFFLE: { 7896 // Figure out if the scalar is the LHS or RHS and return it. 7897 SDValue EltNum = Node->getOperand(2).getOperand(0); 7898 if (cast<ConstantSDNode>(EltNum)->getZExtValue()) 7899 Result = ScalarizeVectorOp(Node->getOperand(1)); 7900 else 7901 Result = ScalarizeVectorOp(Node->getOperand(0)); 7902 break; 7903 } 7904 case ISD::EXTRACT_SUBVECTOR: 7905 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, Node->getOperand(0), 7906 Node->getOperand(1)); 7907 break; 7908 case ISD::BIT_CONVERT: { 7909 SDValue Op0 = Op.getOperand(0); 7910 if (Op0.getValueType().getVectorNumElements() == 1) 7911 Op0 = ScalarizeVectorOp(Op0); 7912 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); 7913 break; 7914 } 7915 case ISD::SELECT: 7916 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 7917 ScalarizeVectorOp(Op.getOperand(1)), 7918 ScalarizeVectorOp(Op.getOperand(2))); 7919 break; 7920 case ISD::SELECT_CC: 7921 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0), 7922 Node->getOperand(1), 7923 ScalarizeVectorOp(Op.getOperand(2)), 7924 ScalarizeVectorOp(Op.getOperand(3)), 7925 Node->getOperand(4)); 7926 break; 7927 case ISD::VSETCC: { 7928 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0)); 7929 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1)); 7930 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0.getValueType()), 7931 Op0, Op1, Op.getOperand(2)); 7932 Result = DAG.getNode(ISD::SELECT, NewVT, Result, 7933 DAG.getConstant(-1ULL, NewVT), 7934 DAG.getConstant(0ULL, NewVT)); 7935 break; 7936 } 7937 } 7938 7939 if (TLI.isTypeLegal(NewVT)) 7940 Result = LegalizeOp(Result); 7941 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7942 assert(isNew && "Value already scalarized?"); 7943 isNew = isNew; 7944 return Result; 7945} 7946 7947 7948SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) { 7949 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op); 7950 if (I != WidenNodes.end()) return I->second; 7951 7952 MVT VT = Op.getValueType(); 7953 assert(VT.isVector() && "Cannot widen non-vector type!"); 7954 7955 SDValue Result; 7956 SDNode *Node = Op.getNode(); 7957 MVT EVT = VT.getVectorElementType(); 7958 7959 unsigned NumElts = VT.getVectorNumElements(); 7960 unsigned NewNumElts = WidenVT.getVectorNumElements(); 7961 assert(NewNumElts > NumElts && "Cannot widen to smaller type!"); 7962 assert(NewNumElts < 17); 7963 7964 // When widen is called, it is assumed that it is more efficient to use a 7965 // wide type. The default action is to widen to operation to a wider legal 7966 // vector type and then do the operation if it is legal by calling LegalizeOp 7967 // again. If there is no vector equivalent, we will unroll the operation, do 7968 // it, and rebuild the vector. If most of the operations are vectorizible to 7969 // the legal type, the resulting code will be more efficient. If this is not 7970 // the case, the resulting code will preform badly as we end up generating 7971 // code to pack/unpack the results. It is the function that calls widen 7972 // that is responsible for seeing this doesn't happen. 7973 switch (Node->getOpcode()) { 7974 default: 7975#ifndef NDEBUG 7976 Node->dump(&DAG); 7977#endif 7978 assert(0 && "Unexpected operation in WidenVectorOp!"); 7979 break; 7980 case ISD::CopyFromReg: 7981 assert(0 && "CopyFromReg doesn't need widening!"); 7982 case ISD::Constant: 7983 case ISD::ConstantFP: 7984 // To build a vector of these elements, clients should call BuildVector 7985 // and with each element instead of creating a node with a vector type 7986 assert(0 && "Unexpected operation in WidenVectorOp!"); 7987 case ISD::VAARG: 7988 // Variable Arguments with vector types doesn't make any sense to me 7989 assert(0 && "Unexpected operation in WidenVectorOp!"); 7990 break; 7991 case ISD::UNDEF: 7992 Result = DAG.getNode(ISD::UNDEF, WidenVT); 7993 break; 7994 case ISD::BUILD_VECTOR: { 7995 // Build a vector with undefined for the new nodes 7996 SDValueVector NewOps(Node->op_begin(), Node->op_end()); 7997 for (unsigned i = NumElts; i < NewNumElts; ++i) { 7998 NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT)); 7999 } 8000 Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size()); 8001 break; 8002 } 8003 case ISD::INSERT_VECTOR_ELT: { 8004 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8005 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1, 8006 Node->getOperand(1), Node->getOperand(2)); 8007 break; 8008 } 8009 case ISD::VECTOR_SHUFFLE: { 8010 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8011 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT); 8012 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is 8013 // used as permutation array. We build the vector here instead of widening 8014 // because we don't want to legalize and have it turned to something else. 8015 SDValue PermOp = Node->getOperand(2); 8016 SDValueVector NewOps; 8017 MVT PVT = PermOp.getValueType().getVectorElementType(); 8018 for (unsigned i = 0; i < NumElts; ++i) { 8019 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) { 8020 NewOps.push_back(PermOp.getOperand(i)); 8021 } else { 8022 unsigned Idx = 8023 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue(); 8024 if (Idx < NumElts) { 8025 NewOps.push_back(PermOp.getOperand(i)); 8026 } 8027 else { 8028 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts, 8029 PermOp.getOperand(i).getValueType())); 8030 } 8031 } 8032 } 8033 for (unsigned i = NumElts; i < NewNumElts; ++i) { 8034 NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT)); 8035 } 8036 8037 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, 8038 MVT::getVectorVT(PVT, NewOps.size()), 8039 &NewOps[0], NewOps.size()); 8040 8041 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3); 8042 break; 8043 } 8044 case ISD::LOAD: { 8045 // If the load widen returns true, we can use a single load for the 8046 // vector. Otherwise, it is returning a token factor for multiple 8047 // loads. 8048 SDValue TFOp; 8049 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT)) 8050 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1))); 8051 else 8052 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0))); 8053 break; 8054 } 8055 8056 case ISD::BIT_CONVERT: { 8057 SDValue Tmp1 = Node->getOperand(0); 8058 // Converts between two different types so we need to determine 8059 // the correct widen type for the input operand. 8060 MVT InVT = Tmp1.getValueType(); 8061 unsigned WidenSize = WidenVT.getSizeInBits(); 8062 if (InVT.isVector()) { 8063 MVT InEltVT = InVT.getVectorElementType(); 8064 unsigned InEltSize = InEltVT.getSizeInBits(); 8065 assert(WidenSize % InEltSize == 0 && 8066 "can not widen bit convert that are not multiple of element type"); 8067 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize); 8068 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT); 8069 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits()); 8070 Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Tmp1); 8071 } else { 8072 // If the result size is a multiple of the input size, widen the input 8073 // and then convert. 8074 unsigned InSize = InVT.getSizeInBits(); 8075 assert(WidenSize % InSize == 0 && 8076 "can not widen bit convert that are not multiple of element type"); 8077 unsigned NewNumElts = WidenSize / InSize; 8078 SmallVector<SDValue, 16> Ops(NewNumElts); 8079 SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT); 8080 Ops[0] = Tmp1; 8081 for (unsigned i = 1; i < NewNumElts; ++i) 8082 Ops[i] = UndefVal; 8083 8084 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts); 8085 Result = DAG.getNode(ISD::BUILD_VECTOR, NewInVT, &Ops[0], NewNumElts); 8086 Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Result); 8087 } 8088 break; 8089 } 8090 8091 case ISD::SINT_TO_FP: 8092 case ISD::UINT_TO_FP: 8093 case ISD::FP_TO_SINT: 8094 case ISD::FP_TO_UINT: 8095 case ISD::FP_ROUND: { 8096 SDValue Tmp1 = Node->getOperand(0); 8097 // Converts between two different types so we need to determine 8098 // the correct widen type for the input operand. 8099 MVT TVT = Tmp1.getValueType(); 8100 assert(TVT.isVector() && "can not widen non vector type"); 8101 MVT TEVT = TVT.getVectorElementType(); 8102 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts); 8103 Tmp1 = WidenVectorOp(Tmp1, TWidenVT); 8104 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts); 8105 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1); 8106 break; 8107 } 8108 8109 case ISD::FP_EXTEND: 8110 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 8111 case ISD::TRUNCATE: 8112 case ISD::SIGN_EXTEND: 8113 case ISD::ZERO_EXTEND: 8114 case ISD::ANY_EXTEND: 8115 case ISD::SIGN_EXTEND_INREG: 8116 case ISD::FABS: 8117 case ISD::FNEG: 8118 case ISD::FSQRT: 8119 case ISD::FSIN: 8120 case ISD::FCOS: 8121 case ISD::CTPOP: 8122 case ISD::CTTZ: 8123 case ISD::CTLZ: { 8124 // Unary op widening 8125 SDValue Tmp1; 8126 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8127 assert(Tmp1.getValueType() == WidenVT); 8128 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1); 8129 break; 8130 } 8131 case ISD::CONVERT_RNDSAT: { 8132 SDValue RndOp = Node->getOperand(3); 8133 SDValue SatOp = Node->getOperand(4); 8134 SDValue SrcOp = Node->getOperand(0); 8135 8136 // Converts between two different types so we need to determine 8137 // the correct widen type for the input operand. 8138 MVT SVT = SrcOp.getValueType(); 8139 assert(SVT.isVector() && "can not widen non vector type"); 8140 MVT SEVT = SVT.getVectorElementType(); 8141 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts); 8142 8143 SrcOp = WidenVectorOp(SrcOp, SWidenVT); 8144 assert(SrcOp.getValueType() == WidenVT); 8145 SDValue DTyOp = DAG.getValueType(WidenVT); 8146 SDValue STyOp = DAG.getValueType(SrcOp.getValueType()); 8147 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 8148 8149 Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp, 8150 RndOp, SatOp, CvtCode); 8151 break; 8152 } 8153 case ISD::FPOW: 8154 case ISD::FPOWI: 8155 case ISD::ADD: 8156 case ISD::SUB: 8157 case ISD::MUL: 8158 case ISD::MULHS: 8159 case ISD::MULHU: 8160 case ISD::AND: 8161 case ISD::OR: 8162 case ISD::XOR: 8163 case ISD::FADD: 8164 case ISD::FSUB: 8165 case ISD::FMUL: 8166 case ISD::SDIV: 8167 case ISD::SREM: 8168 case ISD::FDIV: 8169 case ISD::FREM: 8170 case ISD::FCOPYSIGN: 8171 case ISD::UDIV: 8172 case ISD::UREM: 8173 case ISD::BSWAP: { 8174 // Binary op widening 8175 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8176 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT); 8177 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT); 8178 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2); 8179 break; 8180 } 8181 8182 case ISD::SHL: 8183 case ISD::SRA: 8184 case ISD::SRL: { 8185 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8186 assert(Tmp1.getValueType() == WidenVT); 8187 SDValue ShOp = Node->getOperand(1); 8188 MVT ShVT = ShOp.getValueType(); 8189 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(), 8190 WidenVT.getVectorNumElements()); 8191 ShOp = WidenVectorOp(ShOp, NewShVT); 8192 assert(ShOp.getValueType() == NewShVT); 8193 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, ShOp); 8194 break; 8195 } 8196 8197 case ISD::EXTRACT_VECTOR_ELT: { 8198 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8199 assert(Tmp1.getValueType() == WidenVT); 8200 Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1)); 8201 break; 8202 } 8203 case ISD::CONCAT_VECTORS: { 8204 // We concurrently support only widen on a multiple of the incoming vector. 8205 // We could widen on a multiple of the incoming operand if necessary. 8206 unsigned NumConcat = NewNumElts / NumElts; 8207 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector"); 8208 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT); 8209 SmallVector<SDValue, 8> MOps; 8210 MOps.push_back(Op); 8211 for (unsigned i = 1; i != NumConcat; ++i) { 8212 MOps.push_back(UndefVal); 8213 } 8214 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT, 8215 &MOps[0], MOps.size())); 8216 break; 8217 } 8218 case ISD::EXTRACT_SUBVECTOR: { 8219 SDValue Tmp1 = Node->getOperand(0); 8220 SDValue Idx = Node->getOperand(1); 8221 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx); 8222 if (CIdx && CIdx->getZExtValue() == 0) { 8223 // Since we are access the start of the vector, the incoming 8224 // vector type might be the proper. 8225 MVT Tmp1VT = Tmp1.getValueType(); 8226 if (Tmp1VT == WidenVT) 8227 return Tmp1; 8228 else { 8229 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements(); 8230 if (Tmp1VTNumElts < NewNumElts) 8231 Result = WidenVectorOp(Tmp1, WidenVT); 8232 else 8233 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, Tmp1, Idx); 8234 } 8235 } else if (NewNumElts % NumElts == 0) { 8236 // Widen the extracted subvector. 8237 unsigned NumConcat = NewNumElts / NumElts; 8238 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT); 8239 SmallVector<SDValue, 8> MOps; 8240 MOps.push_back(Op); 8241 for (unsigned i = 1; i != NumConcat; ++i) { 8242 MOps.push_back(UndefVal); 8243 } 8244 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT, 8245 &MOps[0], MOps.size())); 8246 } else { 8247 assert(0 && "can not widen extract subvector"); 8248 // This could be implemented using insert and build vector but I would 8249 // like to see when this happens. 8250 } 8251 break; 8252 } 8253 8254 case ISD::SELECT: { 8255 // Determine new condition widen type and widen 8256 SDValue Cond1 = Node->getOperand(0); 8257 MVT CondVT = Cond1.getValueType(); 8258 assert(CondVT.isVector() && "can not widen non vector type"); 8259 MVT CondEVT = CondVT.getVectorElementType(); 8260 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts); 8261 Cond1 = WidenVectorOp(Cond1, CondWidenVT); 8262 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen"); 8263 8264 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT); 8265 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT); 8266 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT); 8267 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2); 8268 break; 8269 } 8270 8271 case ISD::SELECT_CC: { 8272 // Determine new condition widen type and widen 8273 SDValue Cond1 = Node->getOperand(0); 8274 SDValue Cond2 = Node->getOperand(1); 8275 MVT CondVT = Cond1.getValueType(); 8276 assert(CondVT.isVector() && "can not widen non vector type"); 8277 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs"); 8278 MVT CondEVT = CondVT.getVectorElementType(); 8279 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts); 8280 Cond1 = WidenVectorOp(Cond1, CondWidenVT); 8281 Cond2 = WidenVectorOp(Cond2, CondWidenVT); 8282 assert(Cond1.getValueType() == CondWidenVT && 8283 Cond2.getValueType() == CondWidenVT && "condition not widen"); 8284 8285 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT); 8286 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT); 8287 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT && 8288 "operands not widen"); 8289 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1, 8290 Tmp2, Node->getOperand(4)); 8291 break; 8292 } 8293 case ISD::VSETCC: { 8294 // Determine widen for the operand 8295 SDValue Tmp1 = Node->getOperand(0); 8296 MVT TmpVT = Tmp1.getValueType(); 8297 assert(TmpVT.isVector() && "can not widen non vector type"); 8298 MVT TmpEVT = TmpVT.getVectorElementType(); 8299 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts); 8300 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT); 8301 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT); 8302 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2, 8303 Node->getOperand(2)); 8304 break; 8305 } 8306 case ISD::ATOMIC_CMP_SWAP: 8307 case ISD::ATOMIC_LOAD_ADD: 8308 case ISD::ATOMIC_LOAD_SUB: 8309 case ISD::ATOMIC_LOAD_AND: 8310 case ISD::ATOMIC_LOAD_OR: 8311 case ISD::ATOMIC_LOAD_XOR: 8312 case ISD::ATOMIC_LOAD_NAND: 8313 case ISD::ATOMIC_LOAD_MIN: 8314 case ISD::ATOMIC_LOAD_MAX: 8315 case ISD::ATOMIC_LOAD_UMIN: 8316 case ISD::ATOMIC_LOAD_UMAX: 8317 case ISD::ATOMIC_SWAP: { 8318 // For now, we assume that using vectors for these operations don't make 8319 // much sense so we just split it. We return an empty result 8320 SDValue X, Y; 8321 SplitVectorOp(Op, X, Y); 8322 return Result; 8323 break; 8324 } 8325 8326 } // end switch (Node->getOpcode()) 8327 8328 assert(Result.getNode() && "Didn't set a result!"); 8329 if (Result != Op) 8330 Result = LegalizeOp(Result); 8331 8332 AddWidenedOperand(Op, Result); 8333 return Result; 8334} 8335 8336// Utility function to find a legal vector type and its associated element 8337// type from a preferred width and whose vector type must be the same size 8338// as the VVT. 8339// TLI: Target lowering used to determine legal types 8340// Width: Preferred width of element type 8341// VVT: Vector value type whose size we must match. 8342// Returns VecEVT and EVT - the vector type and its associated element type 8343static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT, 8344 MVT& EVT, MVT& VecEVT) { 8345 // We start with the preferred width, make it a power of 2 and see if 8346 // we can find a vector type of that width. If not, we reduce it by 8347 // another power of 2. If we have widen the type, a vector of bytes should 8348 // always be legal. 8349 assert(TLI.isTypeLegal(VVT)); 8350 unsigned EWidth = Width + 1; 8351 do { 8352 assert(EWidth > 0); 8353 EWidth = (1 << Log2_32(EWidth-1)); 8354 EVT = MVT::getIntegerVT(EWidth); 8355 unsigned NumEVT = VVT.getSizeInBits()/EWidth; 8356 VecEVT = MVT::getVectorVT(EVT, NumEVT); 8357 } while (!TLI.isTypeLegal(VecEVT) || 8358 VVT.getSizeInBits() != VecEVT.getSizeInBits()); 8359} 8360 8361SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain, 8362 SDValue Chain, 8363 SDValue BasePtr, 8364 const Value *SV, 8365 int SVOffset, 8366 unsigned Alignment, 8367 bool isVolatile, 8368 unsigned LdWidth, 8369 MVT ResType) { 8370 // We assume that we have good rules to handle loading power of two loads so 8371 // we break down the operations to power of 2 loads. The strategy is to 8372 // load the largest power of 2 that we can easily transform to a legal vector 8373 // and then insert into that vector, and the cast the result into the legal 8374 // vector that we want. This avoids unnecessary stack converts. 8375 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and 8376 // the load is nonvolatile, we an use a wider load for the value. 8377 // Find a vector length we can load a large chunk 8378 MVT EVT, VecEVT; 8379 unsigned EVTWidth; 8380 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT); 8381 EVTWidth = EVT.getSizeInBits(); 8382 8383 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset, 8384 isVolatile, Alignment); 8385 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp); 8386 LdChain.push_back(LdOp.getValue(1)); 8387 8388 // Check if we can load the element with one instruction 8389 if (LdWidth == EVTWidth) { 8390 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp); 8391 } 8392 8393 // The vector element order is endianness dependent. 8394 unsigned Idx = 1; 8395 LdWidth -= EVTWidth; 8396 unsigned Offset = 0; 8397 8398 while (LdWidth > 0) { 8399 unsigned Increment = EVTWidth / 8; 8400 Offset += Increment; 8401 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr, 8402 DAG.getIntPtrConstant(Increment)); 8403 8404 if (LdWidth < EVTWidth) { 8405 // Our current type we are using is too large, use a smaller size by 8406 // using a smaller power of 2 8407 unsigned oEVTWidth = EVTWidth; 8408 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT); 8409 EVTWidth = EVT.getSizeInBits(); 8410 // Readjust position and vector position based on new load type 8411 Idx = Idx * (oEVTWidth/EVTWidth); 8412 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp); 8413 } 8414 8415 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, 8416 SVOffset+Offset, isVolatile, 8417 MinAlign(Alignment, Offset)); 8418 LdChain.push_back(LdOp.getValue(1)); 8419 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp, 8420 DAG.getIntPtrConstant(Idx++)); 8421 8422 LdWidth -= EVTWidth; 8423 } 8424 8425 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp); 8426} 8427 8428bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result, 8429 SDValue& TFOp, 8430 SDValue Op, 8431 MVT NVT) { 8432 // TODO: Add support for ConcatVec and the ability to load many vector 8433 // types (e.g., v4i8). This will not work when a vector register 8434 // to memory mapping is strange (e.g., vector elements are not 8435 // stored in some sequential order). 8436 8437 // It must be true that the widen vector type is bigger than where 8438 // we need to load from. 8439 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); 8440 MVT LdVT = LD->getMemoryVT(); 8441 assert(LdVT.isVector() && NVT.isVector()); 8442 assert(LdVT.getVectorElementType() == NVT.getVectorElementType()); 8443 8444 // Load information 8445 SDValue Chain = LD->getChain(); 8446 SDValue BasePtr = LD->getBasePtr(); 8447 int SVOffset = LD->getSrcValueOffset(); 8448 unsigned Alignment = LD->getAlignment(); 8449 bool isVolatile = LD->isVolatile(); 8450 const Value *SV = LD->getSrcValue(); 8451 unsigned int LdWidth = LdVT.getSizeInBits(); 8452 8453 // Load value as a large register 8454 SDValueVector LdChain; 8455 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset, 8456 Alignment, isVolatile, LdWidth, NVT); 8457 8458 if (LdChain.size() == 1) { 8459 TFOp = LdChain[0]; 8460 return true; 8461 } 8462 else { 8463 TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size()); 8464 return false; 8465 } 8466} 8467 8468 8469void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain, 8470 SDValue Chain, 8471 SDValue BasePtr, 8472 const Value *SV, 8473 int SVOffset, 8474 unsigned Alignment, 8475 bool isVolatile, 8476 SDValue ValOp, 8477 unsigned StWidth) { 8478 // Breaks the stores into a series of power of 2 width stores. For any 8479 // width, we convert the vector to the vector of element size that we 8480 // want to store. This avoids requiring a stack convert. 8481 8482 // Find a width of the element type we can store with 8483 MVT VVT = ValOp.getValueType(); 8484 MVT EVT, VecEVT; 8485 unsigned EVTWidth; 8486 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT); 8487 EVTWidth = EVT.getSizeInBits(); 8488 8489 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp); 8490 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp, 8491 DAG.getIntPtrConstant(0)); 8492 SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset, 8493 isVolatile, Alignment); 8494 StChain.push_back(StOp); 8495 8496 // Check if we are done 8497 if (StWidth == EVTWidth) { 8498 return; 8499 } 8500 8501 unsigned Idx = 1; 8502 StWidth -= EVTWidth; 8503 unsigned Offset = 0; 8504 8505 while (StWidth > 0) { 8506 unsigned Increment = EVTWidth / 8; 8507 Offset += Increment; 8508 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr, 8509 DAG.getIntPtrConstant(Increment)); 8510 8511 if (StWidth < EVTWidth) { 8512 // Our current type we are using is too large, use a smaller size by 8513 // using a smaller power of 2 8514 unsigned oEVTWidth = EVTWidth; 8515 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT); 8516 EVTWidth = EVT.getSizeInBits(); 8517 // Readjust position and vector position based on new load type 8518 Idx = Idx * (oEVTWidth/EVTWidth); 8519 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp); 8520 } 8521 8522 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp, 8523 DAG.getIntPtrConstant(Idx++)); 8524 StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV, 8525 SVOffset + Offset, isVolatile, 8526 MinAlign(Alignment, Offset))); 8527 StWidth -= EVTWidth; 8528 } 8529} 8530 8531 8532SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST, 8533 SDValue Chain, 8534 SDValue BasePtr) { 8535 // TODO: It might be cleaner if we can use SplitVector and have more legal 8536 // vector types that can be stored into memory (e.g., v4xi8 can 8537 // be stored as a word). This will not work when a vector register 8538 // to memory mapping is strange (e.g., vector elements are not 8539 // stored in some sequential order). 8540 8541 MVT StVT = ST->getMemoryVT(); 8542 SDValue ValOp = ST->getValue(); 8543 8544 // Check if we have widen this node with another value 8545 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp); 8546 if (I != WidenNodes.end()) 8547 ValOp = I->second; 8548 8549 MVT VVT = ValOp.getValueType(); 8550 8551 // It must be true that we the widen vector type is bigger than where 8552 // we need to store. 8553 assert(StVT.isVector() && VVT.isVector()); 8554 assert(StVT.bitsLT(VVT)); 8555 assert(StVT.getVectorElementType() == VVT.getVectorElementType()); 8556 8557 // Store value 8558 SDValueVector StChain; 8559 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(), 8560 ST->getSrcValueOffset(), ST->getAlignment(), 8561 ST->isVolatile(), ValOp, StVT.getSizeInBits()); 8562 if (StChain.size() == 1) 8563 return StChain[0]; 8564 else 8565 return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size()); 8566} 8567 8568 8569// SelectionDAG::Legalize - This is the entry point for the file. 8570// 8571void SelectionDAG::Legalize(bool TypesNeedLegalizing) { 8572 /// run - This is the main entry point to this class. 8573 /// 8574 SelectionDAGLegalize(*this, TypesNeedLegalizing).LegalizeDAG(); 8575} 8576 8577