LegalizeDAG.cpp revision bcc8017c738e92d9c1af221b11c4916cb524184e
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/Analysis/DebugInfo.h" 20#include "llvm/CodeGen/PseudoSourceValue.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetOptions.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Function.h" 30#include "llvm/GlobalVariable.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/ADT/DenseMap.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/SmallPtrSet.h" 40using namespace llvm; 41 42//===----------------------------------------------------------------------===// 43/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 44/// hacks on it until the target machine can handle it. This involves 45/// eliminating value sizes the machine cannot handle (promoting small sizes to 46/// large sizes or splitting up large values into small values) as well as 47/// eliminating operations the machine cannot handle. 48/// 49/// This code also does a small amount of optimization and recognition of idioms 50/// as part of its processing. For example, if a target does not support a 51/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 52/// will attempt merge setcc and brc instructions into brcc's. 53/// 54namespace { 55class SelectionDAGLegalize { 56 const TargetMachine &TM; 57 const TargetLowering &TLI; 58 SelectionDAG &DAG; 59 CodeGenOpt::Level OptLevel; 60 61 // Libcall insertion helpers. 62 63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 64 /// legalized. We use this to ensure that calls are properly serialized 65 /// against each other, including inserted libcalls. 66 SDValue LastCALLSEQ_END; 67 68 /// IsLegalizingCall - This member is used *only* for purposes of providing 69 /// helpful assertions that a libcall isn't created while another call is 70 /// being legalized (which could lead to non-serialized call sequences). 71 bool IsLegalizingCall; 72 73 enum LegalizeAction { 74 Legal, // The target natively supports this operation. 75 Promote, // This operation should be executed in a larger type. 76 Expand // Try to expand this to other ops, otherwise use a libcall. 77 }; 78 79 /// ValueTypeActions - This is a bitvector that contains two bits for each 80 /// value type, where the two bits correspond to the LegalizeAction enum. 81 /// This can be queried with "getTypeAction(VT)". 82 TargetLowering::ValueTypeActionImpl ValueTypeActions; 83 84 /// LegalizedNodes - For nodes that are of legal width, and that have more 85 /// than one use, this map indicates what regularized operand to use. This 86 /// allows us to avoid legalizing the same thing more than once. 87 DenseMap<SDValue, SDValue> LegalizedNodes; 88 89 void AddLegalizedOperand(SDValue From, SDValue To) { 90 LegalizedNodes.insert(std::make_pair(From, To)); 91 // If someone requests legalization of the new node, return itself. 92 if (From != To) 93 LegalizedNodes.insert(std::make_pair(To, To)); 94 } 95 96public: 97 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 98 99 /// getTypeAction - Return how we should legalize values of this type, either 100 /// it is already legal or we need to expand it into multiple registers of 101 /// smaller integer type, or we need to promote it to a larger type. 102 LegalizeAction getTypeAction(EVT VT) const { 103 return 104 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT); 105 } 106 107 /// isTypeLegal - Return true if this type is legal on this target. 108 /// 109 bool isTypeLegal(EVT VT) const { 110 return getTypeAction(VT) == Legal; 111 } 112 113 void LegalizeDAG(); 114 115private: 116 /// LegalizeOp - We know that the specified value has a legal type. 117 /// Recursively ensure that the operands have legal types, then return the 118 /// result. 119 SDValue LegalizeOp(SDValue O); 120 121 SDValue OptimizeFloatStore(StoreSDNode *ST); 122 123 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 124 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 125 /// is necessary to spill the vector being inserted into to memory, perform 126 /// the insert there, and then read the result back. 127 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 128 SDValue Idx, DebugLoc dl); 129 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 130 SDValue Idx, DebugLoc dl); 131 132 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 133 /// performs the same shuffe in terms of order or result bytes, but on a type 134 /// whose vector element type is narrower than the original shuffle type. 135 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 136 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 137 SDValue N1, SDValue N2, 138 SmallVectorImpl<int> &Mask) const; 139 140 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 141 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 142 143 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 144 DebugLoc dl); 145 146 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 147 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC, 148 SDNode *Node, bool isSigned); 149 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 150 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 151 RTLIB::Libcall Call_PPCF128); 152 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 153 RTLIB::Libcall Call_I8, 154 RTLIB::Libcall Call_I16, 155 RTLIB::Libcall Call_I32, 156 RTLIB::Libcall Call_I64, 157 RTLIB::Libcall Call_I128); 158 159 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 160 SDValue ExpandBUILD_VECTOR(SDNode *Node); 161 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 162 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 163 SmallVectorImpl<SDValue> &Results); 164 SDValue ExpandFCOPYSIGN(SDNode *Node); 165 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 166 DebugLoc dl); 167 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 168 DebugLoc dl); 169 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 170 DebugLoc dl); 171 172 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 173 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 174 175 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 176 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 177 178 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node); 179 180 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 181 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 182}; 183} 184 185/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 186/// performs the same shuffe in terms of order or result bytes, but on a type 187/// whose vector element type is narrower than the original shuffle type. 188/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 189SDValue 190SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 191 SDValue N1, SDValue N2, 192 SmallVectorImpl<int> &Mask) const { 193 unsigned NumMaskElts = VT.getVectorNumElements(); 194 unsigned NumDestElts = NVT.getVectorNumElements(); 195 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 196 197 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 198 199 if (NumEltsGrowth == 1) 200 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 201 202 SmallVector<int, 8> NewMask; 203 for (unsigned i = 0; i != NumMaskElts; ++i) { 204 int Idx = Mask[i]; 205 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 206 if (Idx < 0) 207 NewMask.push_back(-1); 208 else 209 NewMask.push_back(Idx * NumEltsGrowth + j); 210 } 211 } 212 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 213 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 214 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 215} 216 217SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 218 CodeGenOpt::Level ol) 219 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 220 DAG(dag), OptLevel(ol), 221 ValueTypeActions(TLI.getValueTypeActions()) { 222 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 223 "Too many value types for ValueTypeActions to hold!"); 224} 225 226void SelectionDAGLegalize::LegalizeDAG() { 227 LastCALLSEQ_END = DAG.getEntryNode(); 228 IsLegalizingCall = false; 229 230 // The legalize process is inherently a bottom-up recursive process (users 231 // legalize their uses before themselves). Given infinite stack space, we 232 // could just start legalizing on the root and traverse the whole graph. In 233 // practice however, this causes us to run out of stack space on large basic 234 // blocks. To avoid this problem, compute an ordering of the nodes where each 235 // node is only legalized after all of its operands are legalized. 236 DAG.AssignTopologicalOrder(); 237 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 238 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 239 LegalizeOp(SDValue(I, 0)); 240 241 // Finally, it's possible the root changed. Get the new root. 242 SDValue OldRoot = DAG.getRoot(); 243 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 244 DAG.setRoot(LegalizedNodes[OldRoot]); 245 246 LegalizedNodes.clear(); 247 248 // Remove dead nodes now. 249 DAG.RemoveDeadNodes(); 250} 251 252 253/// FindCallEndFromCallStart - Given a chained node that is part of a call 254/// sequence, find the CALLSEQ_END node that terminates the call sequence. 255static SDNode *FindCallEndFromCallStart(SDNode *Node) { 256 if (Node->getOpcode() == ISD::CALLSEQ_END) 257 return Node; 258 if (Node->use_empty()) 259 return 0; // No CallSeqEnd 260 261 // The chain is usually at the end. 262 SDValue TheChain(Node, Node->getNumValues()-1); 263 if (TheChain.getValueType() != MVT::Other) { 264 // Sometimes it's at the beginning. 265 TheChain = SDValue(Node, 0); 266 if (TheChain.getValueType() != MVT::Other) { 267 // Otherwise, hunt for it. 268 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 269 if (Node->getValueType(i) == MVT::Other) { 270 TheChain = SDValue(Node, i); 271 break; 272 } 273 274 // Otherwise, we walked into a node without a chain. 275 if (TheChain.getValueType() != MVT::Other) 276 return 0; 277 } 278 } 279 280 for (SDNode::use_iterator UI = Node->use_begin(), 281 E = Node->use_end(); UI != E; ++UI) { 282 283 // Make sure to only follow users of our token chain. 284 SDNode *User = *UI; 285 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 286 if (User->getOperand(i) == TheChain) 287 if (SDNode *Result = FindCallEndFromCallStart(User)) 288 return Result; 289 } 290 return 0; 291} 292 293/// FindCallStartFromCallEnd - Given a chained node that is part of a call 294/// sequence, find the CALLSEQ_START node that initiates the call sequence. 295static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 296 assert(Node && "Didn't find callseq_start for a call??"); 297 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 298 299 assert(Node->getOperand(0).getValueType() == MVT::Other && 300 "Node doesn't have a token chain argument!"); 301 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 302} 303 304/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 305/// see if any uses can reach Dest. If no dest operands can get to dest, 306/// legalize them, legalize ourself, and return false, otherwise, return true. 307/// 308/// Keep track of the nodes we fine that actually do lead to Dest in 309/// NodesLeadingTo. This avoids retraversing them exponential number of times. 310/// 311bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 312 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 313 if (N == Dest) return true; // N certainly leads to Dest :) 314 315 // If we've already processed this node and it does lead to Dest, there is no 316 // need to reprocess it. 317 if (NodesLeadingTo.count(N)) return true; 318 319 // If the first result of this node has been already legalized, then it cannot 320 // reach N. 321 if (LegalizedNodes.count(SDValue(N, 0))) return false; 322 323 // Okay, this node has not already been legalized. Check and legalize all 324 // operands. If none lead to Dest, then we can legalize this node. 325 bool OperandsLeadToDest = false; 326 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 327 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 328 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, 329 NodesLeadingTo); 330 331 if (OperandsLeadToDest) { 332 NodesLeadingTo.insert(N); 333 return true; 334 } 335 336 // Okay, this node looks safe, legalize it and return false. 337 LegalizeOp(SDValue(N, 0)); 338 return false; 339} 340 341/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 342/// a load from the constant pool. 343static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 344 SelectionDAG &DAG, const TargetLowering &TLI) { 345 bool Extend = false; 346 DebugLoc dl = CFP->getDebugLoc(); 347 348 // If a FP immediate is precise when represented as a float and if the 349 // target can do an extending load from float to double, we put it into 350 // the constant pool as a float, even if it's is statically typed as a 351 // double. This shrinks FP constants and canonicalizes them for targets where 352 // an FP extending load is the same cost as a normal load (such as on the x87 353 // fp stack or PPC FP unit). 354 EVT VT = CFP->getValueType(0); 355 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 356 if (!UseCP) { 357 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 358 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 359 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 360 } 361 362 EVT OrigVT = VT; 363 EVT SVT = VT; 364 while (SVT != MVT::f32) { 365 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 366 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) && 367 // Only do this if the target has a native EXTLOAD instruction from 368 // smaller type. 369 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 370 TLI.ShouldShrinkFPConstant(OrigVT)) { 371 const Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 372 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 373 VT = SVT; 374 Extend = true; 375 } 376 } 377 378 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 379 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 380 if (Extend) 381 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, dl, 382 DAG.getEntryNode(), 383 CPIdx, PseudoSourceValue::getConstantPool(), 384 0, VT, false, false, Alignment); 385 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 386 PseudoSourceValue::getConstantPool(), 0, false, false, 387 Alignment); 388} 389 390/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 391static 392SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 393 const TargetLowering &TLI) { 394 SDValue Chain = ST->getChain(); 395 SDValue Ptr = ST->getBasePtr(); 396 SDValue Val = ST->getValue(); 397 EVT VT = Val.getValueType(); 398 int Alignment = ST->getAlignment(); 399 int SVOffset = ST->getSrcValueOffset(); 400 DebugLoc dl = ST->getDebugLoc(); 401 if (ST->getMemoryVT().isFloatingPoint() || 402 ST->getMemoryVT().isVector()) { 403 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 404 if (TLI.isTypeLegal(intVT)) { 405 // Expand to a bitconvert of the value to the integer type of the 406 // same size, then a (misaligned) int store. 407 // FIXME: Does not handle truncating floating point stores! 408 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 409 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 410 SVOffset, ST->isVolatile(), ST->isNonTemporal(), 411 Alignment); 412 } else { 413 // Do a (aligned) store to a stack slot, then copy from the stack slot 414 // to the final destination using (unaligned) integer loads and stores. 415 EVT StoredVT = ST->getMemoryVT(); 416 EVT RegVT = 417 TLI.getRegisterType(*DAG.getContext(), 418 EVT::getIntegerVT(*DAG.getContext(), 419 StoredVT.getSizeInBits())); 420 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 421 unsigned RegBytes = RegVT.getSizeInBits() / 8; 422 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 423 424 // Make sure the stack slot is also aligned for the register type. 425 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 426 427 // Perform the original store, only redirected to the stack slot. 428 SDValue Store = DAG.getTruncStore(Chain, dl, 429 Val, StackPtr, NULL, 0, StoredVT, 430 false, false, 0); 431 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 432 SmallVector<SDValue, 8> Stores; 433 unsigned Offset = 0; 434 435 // Do all but one copies using the full register width. 436 for (unsigned i = 1; i < NumRegs; i++) { 437 // Load one integer register's worth from the stack slot. 438 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0, 439 false, false, 0); 440 // Store it to the final location. Remember the store. 441 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 442 ST->getSrcValue(), SVOffset + Offset, 443 ST->isVolatile(), ST->isNonTemporal(), 444 MinAlign(ST->getAlignment(), Offset))); 445 // Increment the pointers. 446 Offset += RegBytes; 447 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 448 Increment); 449 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 450 } 451 452 // The last store may be partial. Do a truncating store. On big-endian 453 // machines this requires an extending load from the stack slot to ensure 454 // that the bits are in the right place. 455 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 456 8 * (StoredBytes - Offset)); 457 458 // Load from the stack slot. 459 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Store, StackPtr, 460 NULL, 0, MemVT, false, false, 0); 461 462 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 463 ST->getSrcValue(), SVOffset + Offset, 464 MemVT, ST->isVolatile(), 465 ST->isNonTemporal(), 466 MinAlign(ST->getAlignment(), Offset))); 467 // The order of the stores doesn't matter - say it with a TokenFactor. 468 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 469 Stores.size()); 470 } 471 } 472 assert(ST->getMemoryVT().isInteger() && 473 !ST->getMemoryVT().isVector() && 474 "Unaligned store of unknown type."); 475 // Get the half-size VT 476 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 477 int NumBits = NewStoredVT.getSizeInBits(); 478 int IncrementSize = NumBits / 8; 479 480 // Divide the stored value in two parts. 481 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 482 SDValue Lo = Val; 483 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 484 485 // Store the two parts 486 SDValue Store1, Store2; 487 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 488 ST->getSrcValue(), SVOffset, NewStoredVT, 489 ST->isVolatile(), ST->isNonTemporal(), Alignment); 490 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 491 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 492 Alignment = MinAlign(Alignment, IncrementSize); 493 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 494 ST->getSrcValue(), SVOffset + IncrementSize, 495 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 496 Alignment); 497 498 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 499} 500 501/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 502static 503SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 504 const TargetLowering &TLI) { 505 int SVOffset = LD->getSrcValueOffset(); 506 SDValue Chain = LD->getChain(); 507 SDValue Ptr = LD->getBasePtr(); 508 EVT VT = LD->getValueType(0); 509 EVT LoadedVT = LD->getMemoryVT(); 510 DebugLoc dl = LD->getDebugLoc(); 511 if (VT.isFloatingPoint() || VT.isVector()) { 512 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 513 if (TLI.isTypeLegal(intVT)) { 514 // Expand to a (misaligned) integer load of the same size, 515 // then bitconvert to floating point or vector. 516 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 517 SVOffset, LD->isVolatile(), 518 LD->isNonTemporal(), LD->getAlignment()); 519 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 520 if (VT.isFloatingPoint() && LoadedVT != VT) 521 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 522 523 SDValue Ops[] = { Result, Chain }; 524 return DAG.getMergeValues(Ops, 2, dl); 525 } else { 526 // Copy the value to a (aligned) stack slot using (unaligned) integer 527 // loads and stores, then do a (aligned) load from the stack slot. 528 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 529 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 530 unsigned RegBytes = RegVT.getSizeInBits() / 8; 531 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 532 533 // Make sure the stack slot is also aligned for the register type. 534 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 535 536 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 537 SmallVector<SDValue, 8> Stores; 538 SDValue StackPtr = StackBase; 539 unsigned Offset = 0; 540 541 // Do all but one copies using the full register width. 542 for (unsigned i = 1; i < NumRegs; i++) { 543 // Load one integer register's worth from the original location. 544 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 545 SVOffset + Offset, LD->isVolatile(), 546 LD->isNonTemporal(), 547 MinAlign(LD->getAlignment(), Offset)); 548 // Follow the load with a store to the stack slot. Remember the store. 549 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 550 NULL, 0, false, false, 0)); 551 // Increment the pointers. 552 Offset += RegBytes; 553 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 554 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 555 Increment); 556 } 557 558 // The last copy may be partial. Do an extending load. 559 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 560 8 * (LoadedBytes - Offset)); 561 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Chain, Ptr, 562 LD->getSrcValue(), SVOffset + Offset, 563 MemVT, LD->isVolatile(), 564 LD->isNonTemporal(), 565 MinAlign(LD->getAlignment(), Offset)); 566 // Follow the load with a store to the stack slot. Remember the store. 567 // On big-endian machines this requires a truncating store to ensure 568 // that the bits end up in the right place. 569 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 570 NULL, 0, MemVT, false, false, 0)); 571 572 // The order of the stores doesn't matter - say it with a TokenFactor. 573 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 574 Stores.size()); 575 576 // Finally, perform the original load only redirected to the stack slot. 577 Load = DAG.getExtLoad(LD->getExtensionType(), VT, dl, TF, StackBase, 578 NULL, 0, LoadedVT, false, false, 0); 579 580 // Callers expect a MERGE_VALUES node. 581 SDValue Ops[] = { Load, TF }; 582 return DAG.getMergeValues(Ops, 2, dl); 583 } 584 } 585 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 586 "Unaligned load of unsupported type."); 587 588 // Compute the new VT that is half the size of the old one. This is an 589 // integer MVT. 590 unsigned NumBits = LoadedVT.getSizeInBits(); 591 EVT NewLoadedVT; 592 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 593 NumBits >>= 1; 594 595 unsigned Alignment = LD->getAlignment(); 596 unsigned IncrementSize = NumBits / 8; 597 ISD::LoadExtType HiExtType = LD->getExtensionType(); 598 599 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 600 if (HiExtType == ISD::NON_EXTLOAD) 601 HiExtType = ISD::ZEXTLOAD; 602 603 // Load the value in two parts 604 SDValue Lo, Hi; 605 if (TLI.isLittleEndian()) { 606 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getSrcValue(), 607 SVOffset, NewLoadedVT, LD->isVolatile(), 608 LD->isNonTemporal(), Alignment); 609 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 610 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 611 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getSrcValue(), 612 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 613 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 614 } else { 615 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getSrcValue(), 616 SVOffset, NewLoadedVT, LD->isVolatile(), 617 LD->isNonTemporal(), Alignment); 618 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 619 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 620 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getSrcValue(), 621 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 622 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 623 } 624 625 // aggregate the two parts 626 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 627 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 628 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 629 630 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 631 Hi.getValue(1)); 632 633 SDValue Ops[] = { Result, TF }; 634 return DAG.getMergeValues(Ops, 2, dl); 635} 636 637/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 638/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 639/// is necessary to spill the vector being inserted into to memory, perform 640/// the insert there, and then read the result back. 641SDValue SelectionDAGLegalize:: 642PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 643 DebugLoc dl) { 644 SDValue Tmp1 = Vec; 645 SDValue Tmp2 = Val; 646 SDValue Tmp3 = Idx; 647 648 // If the target doesn't support this, we have to spill the input vector 649 // to a temporary stack slot, update the element, then reload it. This is 650 // badness. We could also load the value into a vector register (either 651 // with a "move to register" or "extload into register" instruction, then 652 // permute it into place, if the idx is a constant and if the idx is 653 // supported by the target. 654 EVT VT = Tmp1.getValueType(); 655 EVT EltVT = VT.getVectorElementType(); 656 EVT IdxVT = Tmp3.getValueType(); 657 EVT PtrVT = TLI.getPointerTy(); 658 SDValue StackPtr = DAG.CreateStackTemporary(VT); 659 660 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 661 662 // Store the vector. 663 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 664 PseudoSourceValue::getFixedStack(SPFI), 0, 665 false, false, 0); 666 667 // Truncate or zero extend offset to target pointer type. 668 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 669 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 670 // Add the offset to the index. 671 unsigned EltSize = EltVT.getSizeInBits()/8; 672 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 673 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 674 // Store the scalar value. 675 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 676 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT, 677 false, false, 0); 678 // Load the updated vector. 679 return DAG.getLoad(VT, dl, Ch, StackPtr, 680 PseudoSourceValue::getFixedStack(SPFI), 0, 681 false, false, 0); 682} 683 684 685SDValue SelectionDAGLegalize:: 686ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 687 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 688 // SCALAR_TO_VECTOR requires that the type of the value being inserted 689 // match the element type of the vector being created, except for 690 // integers in which case the inserted value can be over width. 691 EVT EltVT = Vec.getValueType().getVectorElementType(); 692 if (Val.getValueType() == EltVT || 693 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 694 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 695 Vec.getValueType(), Val); 696 697 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 698 // We generate a shuffle of InVec and ScVec, so the shuffle mask 699 // should be 0,1,2,3,4,5... with the appropriate element replaced with 700 // elt 0 of the RHS. 701 SmallVector<int, 8> ShufOps; 702 for (unsigned i = 0; i != NumElts; ++i) 703 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 704 705 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 706 &ShufOps[0]); 707 } 708 } 709 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 710} 711 712SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 713 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 714 // FIXME: We shouldn't do this for TargetConstantFP's. 715 // FIXME: move this to the DAG Combiner! Note that we can't regress due 716 // to phase ordering between legalized code and the dag combiner. This 717 // probably means that we need to integrate dag combiner and legalizer 718 // together. 719 // We generally can't do this one for long doubles. 720 SDValue Tmp1 = ST->getChain(); 721 SDValue Tmp2 = ST->getBasePtr(); 722 SDValue Tmp3; 723 int SVOffset = ST->getSrcValueOffset(); 724 unsigned Alignment = ST->getAlignment(); 725 bool isVolatile = ST->isVolatile(); 726 bool isNonTemporal = ST->isNonTemporal(); 727 DebugLoc dl = ST->getDebugLoc(); 728 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 729 if (CFP->getValueType(0) == MVT::f32 && 730 getTypeAction(MVT::i32) == Legal) { 731 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 732 bitcastToAPInt().zextOrTrunc(32), 733 MVT::i32); 734 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 735 SVOffset, isVolatile, isNonTemporal, Alignment); 736 } else if (CFP->getValueType(0) == MVT::f64) { 737 // If this target supports 64-bit registers, do a single 64-bit store. 738 if (getTypeAction(MVT::i64) == Legal) { 739 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 740 zextOrTrunc(64), MVT::i64); 741 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 742 SVOffset, isVolatile, isNonTemporal, Alignment); 743 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 744 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 745 // stores. If the target supports neither 32- nor 64-bits, this 746 // xform is certainly not worth it. 747 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 748 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 749 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 750 if (TLI.isBigEndian()) std::swap(Lo, Hi); 751 752 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 753 SVOffset, isVolatile, isNonTemporal, Alignment); 754 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 755 DAG.getIntPtrConstant(4)); 756 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 757 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 758 759 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 760 } 761 } 762 } 763 return SDValue(); 764} 765 766/// LegalizeOp - We know that the specified value has a legal type, and 767/// that its operands are legal. Now ensure that the operation itself 768/// is legal, recursively ensuring that the operands' operations remain 769/// legal. 770SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 771 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 772 return Op; 773 774 SDNode *Node = Op.getNode(); 775 DebugLoc dl = Node->getDebugLoc(); 776 777 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 778 assert(getTypeAction(Node->getValueType(i)) == Legal && 779 "Unexpected illegal type!"); 780 781 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 782 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 783 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 784 "Unexpected illegal type!"); 785 786 // Note that LegalizeOp may be reentered even from single-use nodes, which 787 // means that we always must cache transformed nodes. 788 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 789 if (I != LegalizedNodes.end()) return I->second; 790 791 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 792 SDValue Result = Op; 793 bool isCustom = false; 794 795 // Figure out the correct action; the way to query this varies by opcode 796 TargetLowering::LegalizeAction Action; 797 bool SimpleFinishLegalizing = true; 798 switch (Node->getOpcode()) { 799 case ISD::INTRINSIC_W_CHAIN: 800 case ISD::INTRINSIC_WO_CHAIN: 801 case ISD::INTRINSIC_VOID: 802 case ISD::VAARG: 803 case ISD::STACKSAVE: 804 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 805 break; 806 case ISD::SINT_TO_FP: 807 case ISD::UINT_TO_FP: 808 case ISD::EXTRACT_VECTOR_ELT: 809 Action = TLI.getOperationAction(Node->getOpcode(), 810 Node->getOperand(0).getValueType()); 811 break; 812 case ISD::FP_ROUND_INREG: 813 case ISD::SIGN_EXTEND_INREG: { 814 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 815 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 816 break; 817 } 818 case ISD::SELECT_CC: 819 case ISD::SETCC: 820 case ISD::BR_CC: { 821 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 822 Node->getOpcode() == ISD::SETCC ? 2 : 1; 823 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 824 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 825 ISD::CondCode CCCode = 826 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 827 Action = TLI.getCondCodeAction(CCCode, OpVT); 828 if (Action == TargetLowering::Legal) { 829 if (Node->getOpcode() == ISD::SELECT_CC) 830 Action = TLI.getOperationAction(Node->getOpcode(), 831 Node->getValueType(0)); 832 else 833 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 834 } 835 break; 836 } 837 case ISD::LOAD: 838 case ISD::STORE: 839 // FIXME: Model these properly. LOAD and STORE are complicated, and 840 // STORE expects the unlegalized operand in some cases. 841 SimpleFinishLegalizing = false; 842 break; 843 case ISD::CALLSEQ_START: 844 case ISD::CALLSEQ_END: 845 // FIXME: This shouldn't be necessary. These nodes have special properties 846 // dealing with the recursive nature of legalization. Removing this 847 // special case should be done as part of making LegalizeDAG non-recursive. 848 SimpleFinishLegalizing = false; 849 break; 850 case ISD::EXTRACT_ELEMENT: 851 case ISD::FLT_ROUNDS_: 852 case ISD::SADDO: 853 case ISD::SSUBO: 854 case ISD::UADDO: 855 case ISD::USUBO: 856 case ISD::SMULO: 857 case ISD::UMULO: 858 case ISD::FPOWI: 859 case ISD::MERGE_VALUES: 860 case ISD::EH_RETURN: 861 case ISD::FRAME_TO_ARGS_OFFSET: 862 case ISD::EH_SJLJ_SETJMP: 863 case ISD::EH_SJLJ_LONGJMP: 864 // These operations lie about being legal: when they claim to be legal, 865 // they should actually be expanded. 866 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 867 if (Action == TargetLowering::Legal) 868 Action = TargetLowering::Expand; 869 break; 870 case ISD::TRAMPOLINE: 871 case ISD::FRAMEADDR: 872 case ISD::RETURNADDR: 873 // These operations lie about being legal: when they claim to be legal, 874 // they should actually be custom-lowered. 875 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 876 if (Action == TargetLowering::Legal) 877 Action = TargetLowering::Custom; 878 break; 879 case ISD::BUILD_VECTOR: 880 // A weird case: legalization for BUILD_VECTOR never legalizes the 881 // operands! 882 // FIXME: This really sucks... changing it isn't semantically incorrect, 883 // but it massively pessimizes the code for floating-point BUILD_VECTORs 884 // because ConstantFP operands get legalized into constant pool loads 885 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 886 // though, because BUILD_VECTORS usually get lowered into other nodes 887 // which get legalized properly. 888 SimpleFinishLegalizing = false; 889 break; 890 default: 891 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 892 Action = TargetLowering::Legal; 893 } else { 894 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 895 } 896 break; 897 } 898 899 if (SimpleFinishLegalizing) { 900 SmallVector<SDValue, 8> Ops, ResultVals; 901 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 902 Ops.push_back(LegalizeOp(Node->getOperand(i))); 903 switch (Node->getOpcode()) { 904 default: break; 905 case ISD::BR: 906 case ISD::BRIND: 907 case ISD::BR_JT: 908 case ISD::BR_CC: 909 case ISD::BRCOND: 910 // Branches tweak the chain to include LastCALLSEQ_END 911 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 912 LastCALLSEQ_END); 913 Ops[0] = LegalizeOp(Ops[0]); 914 LastCALLSEQ_END = DAG.getEntryNode(); 915 break; 916 case ISD::SHL: 917 case ISD::SRL: 918 case ISD::SRA: 919 case ISD::ROTL: 920 case ISD::ROTR: 921 // Legalizing shifts/rotates requires adjusting the shift amount 922 // to the appropriate width. 923 if (!Ops[1].getValueType().isVector()) 924 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 925 break; 926 case ISD::SRL_PARTS: 927 case ISD::SRA_PARTS: 928 case ISD::SHL_PARTS: 929 // Legalizing shifts/rotates requires adjusting the shift amount 930 // to the appropriate width. 931 if (!Ops[2].getValueType().isVector()) 932 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2])); 933 break; 934 } 935 936 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(), 937 Ops.size()), 0); 938 switch (Action) { 939 case TargetLowering::Legal: 940 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 941 ResultVals.push_back(Result.getValue(i)); 942 break; 943 case TargetLowering::Custom: 944 // FIXME: The handling for custom lowering with multiple results is 945 // a complete mess. 946 Tmp1 = TLI.LowerOperation(Result, DAG); 947 if (Tmp1.getNode()) { 948 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 949 if (e == 1) 950 ResultVals.push_back(Tmp1); 951 else 952 ResultVals.push_back(Tmp1.getValue(i)); 953 } 954 break; 955 } 956 957 // FALL THROUGH 958 case TargetLowering::Expand: 959 ExpandNode(Result.getNode(), ResultVals); 960 break; 961 case TargetLowering::Promote: 962 PromoteNode(Result.getNode(), ResultVals); 963 break; 964 } 965 if (!ResultVals.empty()) { 966 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 967 if (ResultVals[i] != SDValue(Node, i)) 968 ResultVals[i] = LegalizeOp(ResultVals[i]); 969 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 970 } 971 return ResultVals[Op.getResNo()]; 972 } 973 } 974 975 switch (Node->getOpcode()) { 976 default: 977#ifndef NDEBUG 978 dbgs() << "NODE: "; 979 Node->dump( &DAG); 980 dbgs() << "\n"; 981#endif 982 assert(0 && "Do not know how to legalize this operator!"); 983 984 case ISD::BUILD_VECTOR: 985 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 986 default: assert(0 && "This action is not supported yet!"); 987 case TargetLowering::Custom: 988 Tmp3 = TLI.LowerOperation(Result, DAG); 989 if (Tmp3.getNode()) { 990 Result = Tmp3; 991 break; 992 } 993 // FALLTHROUGH 994 case TargetLowering::Expand: 995 Result = ExpandBUILD_VECTOR(Result.getNode()); 996 break; 997 } 998 break; 999 case ISD::CALLSEQ_START: { 1000 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1001 1002 // Recursively Legalize all of the inputs of the call end that do not lead 1003 // to this call start. This ensures that any libcalls that need be inserted 1004 // are inserted *before* the CALLSEQ_START. 1005 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1006 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1007 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1008 NodesLeadingTo); 1009 } 1010 1011 // Now that we have legalized all of the inputs (which may have inserted 1012 // libcalls), create the new CALLSEQ_START node. 1013 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1014 1015 // Merge in the last call to ensure that this call starts after the last 1016 // call ended. 1017 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1018 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1019 Tmp1, LastCALLSEQ_END); 1020 Tmp1 = LegalizeOp(Tmp1); 1021 } 1022 1023 // Do not try to legalize the target-specific arguments (#1+). 1024 if (Tmp1 != Node->getOperand(0)) { 1025 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1026 Ops[0] = Tmp1; 1027 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0], 1028 Ops.size()), Result.getResNo()); 1029 } 1030 1031 // Remember that the CALLSEQ_START is legalized. 1032 AddLegalizedOperand(Op.getValue(0), Result); 1033 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1034 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1035 1036 // Now that the callseq_start and all of the non-call nodes above this call 1037 // sequence have been legalized, legalize the call itself. During this 1038 // process, no libcalls can/will be inserted, guaranteeing that no calls 1039 // can overlap. 1040 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1041 // Note that we are selecting this call! 1042 LastCALLSEQ_END = SDValue(CallEnd, 0); 1043 IsLegalizingCall = true; 1044 1045 // Legalize the call, starting from the CALLSEQ_END. 1046 LegalizeOp(LastCALLSEQ_END); 1047 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1048 return Result; 1049 } 1050 case ISD::CALLSEQ_END: 1051 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1052 // will cause this node to be legalized as well as handling libcalls right. 1053 if (LastCALLSEQ_END.getNode() != Node) { 1054 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1055 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1056 assert(I != LegalizedNodes.end() && 1057 "Legalizing the call start should have legalized this node!"); 1058 return I->second; 1059 } 1060 1061 // Otherwise, the call start has been legalized and everything is going 1062 // according to plan. Just legalize ourselves normally here. 1063 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1064 // Do not try to legalize the target-specific arguments (#1+), except for 1065 // an optional flag input. 1066 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1067 if (Tmp1 != Node->getOperand(0)) { 1068 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1069 Ops[0] = Tmp1; 1070 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1071 &Ops[0], Ops.size()), 1072 Result.getResNo()); 1073 } 1074 } else { 1075 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1076 if (Tmp1 != Node->getOperand(0) || 1077 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1078 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1079 Ops[0] = Tmp1; 1080 Ops.back() = Tmp2; 1081 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1082 &Ops[0], Ops.size()), 1083 Result.getResNo()); 1084 } 1085 } 1086 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1087 // This finishes up call legalization. 1088 IsLegalizingCall = false; 1089 1090 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1091 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1092 if (Node->getNumValues() == 2) 1093 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1094 return Result.getValue(Op.getResNo()); 1095 case ISD::LOAD: { 1096 LoadSDNode *LD = cast<LoadSDNode>(Node); 1097 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1098 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1099 1100 ISD::LoadExtType ExtType = LD->getExtensionType(); 1101 if (ExtType == ISD::NON_EXTLOAD) { 1102 EVT VT = Node->getValueType(0); 1103 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1104 Tmp1, Tmp2, LD->getOffset()), 1105 Result.getResNo()); 1106 Tmp3 = Result.getValue(0); 1107 Tmp4 = Result.getValue(1); 1108 1109 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1110 default: assert(0 && "This action is not supported yet!"); 1111 case TargetLowering::Legal: 1112 // If this is an unaligned load and the target doesn't support it, 1113 // expand it. 1114 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1115 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1116 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1117 if (LD->getAlignment() < ABIAlignment){ 1118 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1119 DAG, TLI); 1120 Tmp3 = Result.getOperand(0); 1121 Tmp4 = Result.getOperand(1); 1122 Tmp3 = LegalizeOp(Tmp3); 1123 Tmp4 = LegalizeOp(Tmp4); 1124 } 1125 } 1126 break; 1127 case TargetLowering::Custom: 1128 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1129 if (Tmp1.getNode()) { 1130 Tmp3 = LegalizeOp(Tmp1); 1131 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1132 } 1133 break; 1134 case TargetLowering::Promote: { 1135 // Only promote a load of vector type to another. 1136 assert(VT.isVector() && "Cannot promote this load!"); 1137 // Change base type to a different vector type. 1138 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1139 1140 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1141 LD->getSrcValueOffset(), 1142 LD->isVolatile(), LD->isNonTemporal(), 1143 LD->getAlignment()); 1144 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1145 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1146 break; 1147 } 1148 } 1149 // Since loads produce two values, make sure to remember that we 1150 // legalized both of them. 1151 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1152 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1153 return Op.getResNo() ? Tmp4 : Tmp3; 1154 } else { 1155 EVT SrcVT = LD->getMemoryVT(); 1156 unsigned SrcWidth = SrcVT.getSizeInBits(); 1157 int SVOffset = LD->getSrcValueOffset(); 1158 unsigned Alignment = LD->getAlignment(); 1159 bool isVolatile = LD->isVolatile(); 1160 bool isNonTemporal = LD->isNonTemporal(); 1161 1162 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1163 // Some targets pretend to have an i1 loading operation, and actually 1164 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1165 // bits are guaranteed to be zero; it helps the optimizers understand 1166 // that these bits are zero. It is also useful for EXTLOAD, since it 1167 // tells the optimizers that those bits are undefined. It would be 1168 // nice to have an effective generic way of getting these benefits... 1169 // Until such a way is found, don't insist on promoting i1 here. 1170 (SrcVT != MVT::i1 || 1171 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1172 // Promote to a byte-sized load if not loading an integral number of 1173 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1174 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1175 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 1176 SDValue Ch; 1177 1178 // The extra bits are guaranteed to be zero, since we stored them that 1179 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1180 1181 ISD::LoadExtType NewExtType = 1182 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1183 1184 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), dl, 1185 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1186 NVT, isVolatile, isNonTemporal, Alignment); 1187 1188 Ch = Result.getValue(1); // The chain. 1189 1190 if (ExtType == ISD::SEXTLOAD) 1191 // Having the top bits zero doesn't help when sign extending. 1192 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1193 Result.getValueType(), 1194 Result, DAG.getValueType(SrcVT)); 1195 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1196 // All the top bits are guaranteed to be zero - inform the optimizers. 1197 Result = DAG.getNode(ISD::AssertZext, dl, 1198 Result.getValueType(), Result, 1199 DAG.getValueType(SrcVT)); 1200 1201 Tmp1 = LegalizeOp(Result); 1202 Tmp2 = LegalizeOp(Ch); 1203 } else if (SrcWidth & (SrcWidth - 1)) { 1204 // If not loading a power-of-2 number of bits, expand as two loads. 1205 assert(!SrcVT.isVector() && "Unsupported extload!"); 1206 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1207 assert(RoundWidth < SrcWidth); 1208 unsigned ExtraWidth = SrcWidth - RoundWidth; 1209 assert(ExtraWidth < RoundWidth); 1210 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1211 "Load size not an integral number of bytes!"); 1212 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1213 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1214 SDValue Lo, Hi, Ch; 1215 unsigned IncrementSize; 1216 1217 if (TLI.isLittleEndian()) { 1218 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1219 // Load the bottom RoundWidth bits. 1220 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), dl, 1221 Tmp1, Tmp2, 1222 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1223 isNonTemporal, Alignment); 1224 1225 // Load the remaining ExtraWidth bits. 1226 IncrementSize = RoundWidth / 8; 1227 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1228 DAG.getIntPtrConstant(IncrementSize)); 1229 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2, 1230 LD->getSrcValue(), SVOffset + IncrementSize, 1231 ExtraVT, isVolatile, isNonTemporal, 1232 MinAlign(Alignment, IncrementSize)); 1233 1234 // Build a factor node to remember that this load is independent of 1235 // the other one. 1236 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1237 Hi.getValue(1)); 1238 1239 // Move the top bits to the right place. 1240 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1241 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1242 1243 // Join the hi and lo parts. 1244 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1245 } else { 1246 // Big endian - avoid unaligned loads. 1247 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1248 // Load the top RoundWidth bits. 1249 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2, 1250 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1251 isNonTemporal, Alignment); 1252 1253 // Load the remaining ExtraWidth bits. 1254 IncrementSize = RoundWidth / 8; 1255 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1256 DAG.getIntPtrConstant(IncrementSize)); 1257 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, 1258 Node->getValueType(0), dl, Tmp1, Tmp2, 1259 LD->getSrcValue(), SVOffset + IncrementSize, 1260 ExtraVT, isVolatile, isNonTemporal, 1261 MinAlign(Alignment, IncrementSize)); 1262 1263 // Build a factor node to remember that this load is independent of 1264 // the other one. 1265 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1266 Hi.getValue(1)); 1267 1268 // Move the top bits to the right place. 1269 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1270 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1271 1272 // Join the hi and lo parts. 1273 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1274 } 1275 1276 Tmp1 = LegalizeOp(Result); 1277 Tmp2 = LegalizeOp(Ch); 1278 } else { 1279 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1280 default: assert(0 && "This action is not supported yet!"); 1281 case TargetLowering::Custom: 1282 isCustom = true; 1283 // FALLTHROUGH 1284 case TargetLowering::Legal: 1285 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1286 Tmp1, Tmp2, LD->getOffset()), 1287 Result.getResNo()); 1288 Tmp1 = Result.getValue(0); 1289 Tmp2 = Result.getValue(1); 1290 1291 if (isCustom) { 1292 Tmp3 = TLI.LowerOperation(Result, DAG); 1293 if (Tmp3.getNode()) { 1294 Tmp1 = LegalizeOp(Tmp3); 1295 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1296 } 1297 } else { 1298 // If this is an unaligned load and the target doesn't support it, 1299 // expand it. 1300 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1301 const Type *Ty = 1302 LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1303 unsigned ABIAlignment = 1304 TLI.getTargetData()->getABITypeAlignment(Ty); 1305 if (LD->getAlignment() < ABIAlignment){ 1306 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1307 DAG, TLI); 1308 Tmp1 = Result.getOperand(0); 1309 Tmp2 = Result.getOperand(1); 1310 Tmp1 = LegalizeOp(Tmp1); 1311 Tmp2 = LegalizeOp(Tmp2); 1312 } 1313 } 1314 } 1315 break; 1316 case TargetLowering::Expand: 1317 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1318 // f128 = EXTLOAD {f32,f64} too 1319 if ((SrcVT == MVT::f32 && (Node->getValueType(0) == MVT::f64 || 1320 Node->getValueType(0) == MVT::f128)) || 1321 (SrcVT == MVT::f64 && Node->getValueType(0) == MVT::f128)) { 1322 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1323 LD->getSrcValueOffset(), 1324 LD->isVolatile(), LD->isNonTemporal(), 1325 LD->getAlignment()); 1326 Result = DAG.getNode(ISD::FP_EXTEND, dl, 1327 Node->getValueType(0), Load); 1328 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1329 Tmp2 = LegalizeOp(Load.getValue(1)); 1330 break; 1331 } 1332 assert(ExtType != ISD::EXTLOAD && 1333 "EXTLOAD should always be supported!"); 1334 // Turn the unsupported load into an EXTLOAD followed by an explicit 1335 // zero/sign extend inreg. 1336 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), dl, 1337 Tmp1, Tmp2, LD->getSrcValue(), 1338 LD->getSrcValueOffset(), SrcVT, 1339 LD->isVolatile(), LD->isNonTemporal(), 1340 LD->getAlignment()); 1341 SDValue ValRes; 1342 if (ExtType == ISD::SEXTLOAD) 1343 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1344 Result.getValueType(), 1345 Result, DAG.getValueType(SrcVT)); 1346 else 1347 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1348 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1349 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1350 break; 1351 } 1352 } 1353 1354 // Since loads produce two values, make sure to remember that we legalized 1355 // both of them. 1356 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1357 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1358 return Op.getResNo() ? Tmp2 : Tmp1; 1359 } 1360 } 1361 case ISD::STORE: { 1362 StoreSDNode *ST = cast<StoreSDNode>(Node); 1363 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1364 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1365 int SVOffset = ST->getSrcValueOffset(); 1366 unsigned Alignment = ST->getAlignment(); 1367 bool isVolatile = ST->isVolatile(); 1368 bool isNonTemporal = ST->isNonTemporal(); 1369 1370 if (!ST->isTruncatingStore()) { 1371 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1372 Result = SDValue(OptStore, 0); 1373 break; 1374 } 1375 1376 { 1377 Tmp3 = LegalizeOp(ST->getValue()); 1378 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1379 Tmp1, Tmp3, Tmp2, 1380 ST->getOffset()), 1381 Result.getResNo()); 1382 1383 EVT VT = Tmp3.getValueType(); 1384 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1385 default: assert(0 && "This action is not supported yet!"); 1386 case TargetLowering::Legal: 1387 // If this is an unaligned store and the target doesn't support it, 1388 // expand it. 1389 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1390 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1391 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1392 if (ST->getAlignment() < ABIAlignment) 1393 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1394 DAG, TLI); 1395 } 1396 break; 1397 case TargetLowering::Custom: 1398 Tmp1 = TLI.LowerOperation(Result, DAG); 1399 if (Tmp1.getNode()) Result = Tmp1; 1400 break; 1401 case TargetLowering::Promote: 1402 assert(VT.isVector() && "Unknown legal promote case!"); 1403 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1404 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1405 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1406 ST->getSrcValue(), SVOffset, isVolatile, 1407 isNonTemporal, Alignment); 1408 break; 1409 } 1410 break; 1411 } 1412 } else { 1413 Tmp3 = LegalizeOp(ST->getValue()); 1414 1415 EVT StVT = ST->getMemoryVT(); 1416 unsigned StWidth = StVT.getSizeInBits(); 1417 1418 if (StWidth != StVT.getStoreSizeInBits()) { 1419 // Promote to a byte-sized store with upper bits zero if not 1420 // storing an integral number of bytes. For example, promote 1421 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1422 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), 1423 StVT.getStoreSizeInBits()); 1424 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1425 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1426 SVOffset, NVT, isVolatile, isNonTemporal, 1427 Alignment); 1428 } else if (StWidth & (StWidth - 1)) { 1429 // If not storing a power-of-2 number of bits, expand as two stores. 1430 assert(!StVT.isVector() && "Unsupported truncstore!"); 1431 unsigned RoundWidth = 1 << Log2_32(StWidth); 1432 assert(RoundWidth < StWidth); 1433 unsigned ExtraWidth = StWidth - RoundWidth; 1434 assert(ExtraWidth < RoundWidth); 1435 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1436 "Store size not an integral number of bytes!"); 1437 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1438 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1439 SDValue Lo, Hi; 1440 unsigned IncrementSize; 1441 1442 if (TLI.isLittleEndian()) { 1443 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1444 // Store the bottom RoundWidth bits. 1445 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1446 SVOffset, RoundVT, 1447 isVolatile, isNonTemporal, Alignment); 1448 1449 // Store the remaining ExtraWidth bits. 1450 IncrementSize = RoundWidth / 8; 1451 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1452 DAG.getIntPtrConstant(IncrementSize)); 1453 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1454 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1455 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1456 SVOffset + IncrementSize, ExtraVT, isVolatile, 1457 isNonTemporal, 1458 MinAlign(Alignment, IncrementSize)); 1459 } else { 1460 // Big endian - avoid unaligned stores. 1461 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1462 // Store the top RoundWidth bits. 1463 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1464 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1465 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1466 SVOffset, RoundVT, isVolatile, isNonTemporal, 1467 Alignment); 1468 1469 // Store the remaining ExtraWidth bits. 1470 IncrementSize = RoundWidth / 8; 1471 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1472 DAG.getIntPtrConstant(IncrementSize)); 1473 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1474 SVOffset + IncrementSize, ExtraVT, isVolatile, 1475 isNonTemporal, 1476 MinAlign(Alignment, IncrementSize)); 1477 } 1478 1479 // The order of the stores doesn't matter. 1480 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1481 } else { 1482 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1483 Tmp2 != ST->getBasePtr()) 1484 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1485 Tmp1, Tmp3, Tmp2, 1486 ST->getOffset()), 1487 Result.getResNo()); 1488 1489 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1490 default: assert(0 && "This action is not supported yet!"); 1491 case TargetLowering::Legal: 1492 // If this is an unaligned store and the target doesn't support it, 1493 // expand it. 1494 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1495 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1496 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1497 if (ST->getAlignment() < ABIAlignment) 1498 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1499 DAG, TLI); 1500 } 1501 break; 1502 case TargetLowering::Custom: 1503 Result = TLI.LowerOperation(Result, DAG); 1504 break; 1505 case Expand: 1506 // TRUNCSTORE:i16 i32 -> STORE i16 1507 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1508 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1509 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1510 SVOffset, isVolatile, isNonTemporal, 1511 Alignment); 1512 break; 1513 } 1514 } 1515 } 1516 break; 1517 } 1518 } 1519 assert(Result.getValueType() == Op.getValueType() && 1520 "Bad legalization!"); 1521 1522 // Make sure that the generated code is itself legal. 1523 if (Result != Op) 1524 Result = LegalizeOp(Result); 1525 1526 // Note that LegalizeOp may be reentered even from single-use nodes, which 1527 // means that we always must cache transformed nodes. 1528 AddLegalizedOperand(Op, Result); 1529 return Result; 1530} 1531 1532SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1533 SDValue Vec = Op.getOperand(0); 1534 SDValue Idx = Op.getOperand(1); 1535 DebugLoc dl = Op.getDebugLoc(); 1536 // Store the value to a temporary stack slot, then LOAD the returned part. 1537 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1538 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0, 1539 false, false, 0); 1540 1541 // Add the offset to the index. 1542 unsigned EltSize = 1543 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1544 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1545 DAG.getConstant(EltSize, Idx.getValueType())); 1546 1547 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1548 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1549 else 1550 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1551 1552 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1553 1554 if (Op.getValueType().isVector()) 1555 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0, 1556 false, false, 0); 1557 else 1558 return DAG.getExtLoad(ISD::EXTLOAD, Op.getValueType(), dl, Ch, StackPtr, 1559 NULL, 0, Vec.getValueType().getVectorElementType(), 1560 false, false, 0); 1561} 1562 1563SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1564 // We can't handle this case efficiently. Allocate a sufficiently 1565 // aligned object on the stack, store each element into it, then load 1566 // the result as a vector. 1567 // Create the stack frame object. 1568 EVT VT = Node->getValueType(0); 1569 EVT EltVT = VT.getVectorElementType(); 1570 DebugLoc dl = Node->getDebugLoc(); 1571 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1572 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1573 const Value *SV = PseudoSourceValue::getFixedStack(FI); 1574 1575 // Emit a store of each element to the stack slot. 1576 SmallVector<SDValue, 8> Stores; 1577 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1578 // Store (in the right endianness) the elements to memory. 1579 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1580 // Ignore undef elements. 1581 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1582 1583 unsigned Offset = TypeByteSize*i; 1584 1585 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1586 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1587 1588 // If the destination vector element type is narrower than the source 1589 // element type, only store the bits necessary. 1590 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1591 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1592 Node->getOperand(i), Idx, SV, Offset, 1593 EltVT, false, false, 0)); 1594 } else 1595 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1596 Node->getOperand(i), Idx, SV, Offset, 1597 false, false, 0)); 1598 } 1599 1600 SDValue StoreChain; 1601 if (!Stores.empty()) // Not all undef elements? 1602 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1603 &Stores[0], Stores.size()); 1604 else 1605 StoreChain = DAG.getEntryNode(); 1606 1607 // Result is a load from the stack slot. 1608 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0, false, false, 0); 1609} 1610 1611SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1612 DebugLoc dl = Node->getDebugLoc(); 1613 SDValue Tmp1 = Node->getOperand(0); 1614 SDValue Tmp2 = Node->getOperand(1); 1615 1616 // Get the sign bit of the RHS. First obtain a value that has the same 1617 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1618 SDValue SignBit; 1619 EVT FloatVT = Tmp2.getValueType(); 1620 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1621 if (isTypeLegal(IVT)) { 1622 // Convert to an integer with the same sign bit. 1623 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1624 } else { 1625 // Store the float to memory, then load the sign part out as an integer. 1626 MVT LoadTy = TLI.getPointerTy(); 1627 // First create a temporary that is aligned for both the load and store. 1628 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1629 // Then store the float to it. 1630 SDValue Ch = 1631 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL, 0, 1632 false, false, 0); 1633 if (TLI.isBigEndian()) { 1634 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1635 // Load out a legal integer with the same sign bit as the float. 1636 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, NULL, 0, false, false, 0); 1637 } else { // Little endian 1638 SDValue LoadPtr = StackPtr; 1639 // The float may be wider than the integer we are going to load. Advance 1640 // the pointer so that the loaded integer will contain the sign bit. 1641 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1642 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1643 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1644 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1645 // Load a legal integer containing the sign bit. 1646 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, NULL, 0, false, false, 0); 1647 // Move the sign bit to the top bit of the loaded integer. 1648 unsigned BitShift = LoadTy.getSizeInBits() - 1649 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1650 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1651 if (BitShift) 1652 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1653 DAG.getConstant(BitShift,TLI.getShiftAmountTy())); 1654 } 1655 } 1656 // Now get the sign bit proper, by seeing whether the value is negative. 1657 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1658 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1659 ISD::SETLT); 1660 // Get the absolute value of the result. 1661 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1662 // Select between the nabs and abs value based on the sign bit of 1663 // the input. 1664 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1665 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1666 AbsVal); 1667} 1668 1669void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1670 SmallVectorImpl<SDValue> &Results) { 1671 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1672 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1673 " not tell us which reg is the stack pointer!"); 1674 DebugLoc dl = Node->getDebugLoc(); 1675 EVT VT = Node->getValueType(0); 1676 SDValue Tmp1 = SDValue(Node, 0); 1677 SDValue Tmp2 = SDValue(Node, 1); 1678 SDValue Tmp3 = Node->getOperand(2); 1679 SDValue Chain = Tmp1.getOperand(0); 1680 1681 // Chain the dynamic stack allocation so that it doesn't modify the stack 1682 // pointer when other instructions are using the stack. 1683 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1684 1685 SDValue Size = Tmp2.getOperand(1); 1686 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1687 Chain = SP.getValue(1); 1688 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1689 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); 1690 if (Align > StackAlign) 1691 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1692 DAG.getConstant(-(uint64_t)Align, VT)); 1693 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1694 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1695 1696 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1697 DAG.getIntPtrConstant(0, true), SDValue()); 1698 1699 Results.push_back(Tmp1); 1700 Results.push_back(Tmp2); 1701} 1702 1703/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1704/// condition code CC on the current target. This routine expands SETCC with 1705/// illegal condition code into AND / OR of multiple SETCC values. 1706void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1707 SDValue &LHS, SDValue &RHS, 1708 SDValue &CC, 1709 DebugLoc dl) { 1710 EVT OpVT = LHS.getValueType(); 1711 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1712 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1713 default: assert(0 && "Unknown condition code action!"); 1714 case TargetLowering::Legal: 1715 // Nothing to do. 1716 break; 1717 case TargetLowering::Expand: { 1718 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1719 unsigned Opc = 0; 1720 switch (CCCode) { 1721 default: assert(0 && "Don't know how to expand this condition!"); 1722 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1723 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1724 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1725 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1726 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1727 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1728 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1729 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1730 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1731 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1732 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1733 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1734 // FIXME: Implement more expansions. 1735 } 1736 1737 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1738 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1739 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1740 RHS = SDValue(); 1741 CC = SDValue(); 1742 break; 1743 } 1744 } 1745} 1746 1747/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1748/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1749/// a load from the stack slot to DestVT, extending it if needed. 1750/// The resultant code need not be legal. 1751SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1752 EVT SlotVT, 1753 EVT DestVT, 1754 DebugLoc dl) { 1755 // Create the stack frame object. 1756 unsigned SrcAlign = 1757 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1758 getTypeForEVT(*DAG.getContext())); 1759 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1760 1761 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1762 int SPFI = StackPtrFI->getIndex(); 1763 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1764 1765 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1766 unsigned SlotSize = SlotVT.getSizeInBits(); 1767 unsigned DestSize = DestVT.getSizeInBits(); 1768 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); 1769 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType); 1770 1771 // Emit a store to the stack slot. Use a truncstore if the input value is 1772 // later than DestVT. 1773 SDValue Store; 1774 1775 if (SrcSize > SlotSize) 1776 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1777 SV, 0, SlotVT, false, false, SrcAlign); 1778 else { 1779 assert(SrcSize == SlotSize && "Invalid store"); 1780 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1781 SV, 0, false, false, SrcAlign); 1782 } 1783 1784 // Result is a load from the stack slot. 1785 if (SlotSize == DestSize) 1786 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, false, 1787 DestAlign); 1788 1789 assert(SlotSize < DestSize && "Unknown extension!"); 1790 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, Store, FIPtr, SV, 0, SlotVT, 1791 false, false, DestAlign); 1792} 1793 1794SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1795 DebugLoc dl = Node->getDebugLoc(); 1796 // Create a vector sized/aligned stack slot, store the value to element #0, 1797 // then load the whole vector back out. 1798 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1799 1800 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1801 int SPFI = StackPtrFI->getIndex(); 1802 1803 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1804 StackPtr, 1805 PseudoSourceValue::getFixedStack(SPFI), 0, 1806 Node->getValueType(0).getVectorElementType(), 1807 false, false, 0); 1808 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1809 PseudoSourceValue::getFixedStack(SPFI), 0, 1810 false, false, 0); 1811} 1812 1813 1814/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1815/// support the operation, but do support the resultant vector type. 1816SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1817 unsigned NumElems = Node->getNumOperands(); 1818 SDValue Value1, Value2; 1819 DebugLoc dl = Node->getDebugLoc(); 1820 EVT VT = Node->getValueType(0); 1821 EVT OpVT = Node->getOperand(0).getValueType(); 1822 EVT EltVT = VT.getVectorElementType(); 1823 1824 // If the only non-undef value is the low element, turn this into a 1825 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1826 bool isOnlyLowElement = true; 1827 bool MoreThanTwoValues = false; 1828 bool isConstant = true; 1829 for (unsigned i = 0; i < NumElems; ++i) { 1830 SDValue V = Node->getOperand(i); 1831 if (V.getOpcode() == ISD::UNDEF) 1832 continue; 1833 if (i > 0) 1834 isOnlyLowElement = false; 1835 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1836 isConstant = false; 1837 1838 if (!Value1.getNode()) { 1839 Value1 = V; 1840 } else if (!Value2.getNode()) { 1841 if (V != Value1) 1842 Value2 = V; 1843 } else if (V != Value1 && V != Value2) { 1844 MoreThanTwoValues = true; 1845 } 1846 } 1847 1848 if (!Value1.getNode()) 1849 return DAG.getUNDEF(VT); 1850 1851 if (isOnlyLowElement) 1852 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1853 1854 // If all elements are constants, create a load from the constant pool. 1855 if (isConstant) { 1856 std::vector<Constant*> CV; 1857 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1858 if (ConstantFPSDNode *V = 1859 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1860 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1861 } else if (ConstantSDNode *V = 1862 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1863 if (OpVT==EltVT) 1864 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1865 else { 1866 // If OpVT and EltVT don't match, EltVT is not legal and the 1867 // element values have been promoted/truncated earlier. Undo this; 1868 // we don't want a v16i8 to become a v16i32 for example. 1869 const ConstantInt *CI = V->getConstantIntValue(); 1870 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1871 CI->getZExtValue())); 1872 } 1873 } else { 1874 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1875 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1876 CV.push_back(UndefValue::get(OpNTy)); 1877 } 1878 } 1879 Constant *CP = ConstantVector::get(CV); 1880 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1881 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1882 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1883 PseudoSourceValue::getConstantPool(), 0, 1884 false, false, Alignment); 1885 } 1886 1887 if (!MoreThanTwoValues) { 1888 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1889 for (unsigned i = 0; i < NumElems; ++i) { 1890 SDValue V = Node->getOperand(i); 1891 if (V.getOpcode() == ISD::UNDEF) 1892 continue; 1893 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1894 } 1895 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1896 // Get the splatted value into the low element of a vector register. 1897 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1898 SDValue Vec2; 1899 if (Value2.getNode()) 1900 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1901 else 1902 Vec2 = DAG.getUNDEF(VT); 1903 1904 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1905 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1906 } 1907 } 1908 1909 // Otherwise, we can't handle this case efficiently. 1910 return ExpandVectorBuildThroughStack(Node); 1911} 1912 1913// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1914// does not fit into a register, return the lo part and set the hi part to the 1915// by-reg argument. If it does fit into a single register, return the result 1916// and leave the Hi part unset. 1917SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1918 bool isSigned) { 1919 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1920 // The input chain to this libcall is the entry node of the function. 1921 // Legalizing the call will automatically add the previous call to the 1922 // dependence. 1923 SDValue InChain = DAG.getEntryNode(); 1924 1925 TargetLowering::ArgListTy Args; 1926 TargetLowering::ArgListEntry Entry; 1927 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1928 EVT ArgVT = Node->getOperand(i).getValueType(); 1929 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1930 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1931 Entry.isSExt = isSigned; 1932 Entry.isZExt = !isSigned; 1933 Args.push_back(Entry); 1934 } 1935 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1936 TLI.getPointerTy()); 1937 1938 // Splice the libcall in wherever FindInputOutputChains tells us to. 1939 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1940 std::pair<SDValue, SDValue> CallInfo = 1941 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1942 0, TLI.getLibcallCallingConv(LC), false, 1943 /*isReturnValueUsed=*/true, 1944 Callee, Args, DAG, Node->getDebugLoc()); 1945 1946 // Legalize the call sequence, starting with the chain. This will advance 1947 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1948 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1949 LegalizeOp(CallInfo.second); 1950 return CallInfo.first; 1951} 1952 1953// ExpandChainLibCall - Expand a node into a call to a libcall. Similar to 1954// ExpandLibCall except that the first operand is the in-chain. 1955std::pair<SDValue, SDValue> 1956SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC, 1957 SDNode *Node, 1958 bool isSigned) { 1959 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1960 SDValue InChain = Node->getOperand(0); 1961 1962 TargetLowering::ArgListTy Args; 1963 TargetLowering::ArgListEntry Entry; 1964 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) { 1965 EVT ArgVT = Node->getOperand(i).getValueType(); 1966 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1967 Entry.Node = Node->getOperand(i); 1968 Entry.Ty = ArgTy; 1969 Entry.isSExt = isSigned; 1970 Entry.isZExt = !isSigned; 1971 Args.push_back(Entry); 1972 } 1973 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1974 TLI.getPointerTy()); 1975 1976 // Splice the libcall in wherever FindInputOutputChains tells us to. 1977 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1978 std::pair<SDValue, SDValue> CallInfo = 1979 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1980 0, TLI.getLibcallCallingConv(LC), false, 1981 /*isReturnValueUsed=*/true, 1982 Callee, Args, DAG, Node->getDebugLoc()); 1983 1984 // Legalize the call sequence, starting with the chain. This will advance 1985 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1986 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1987 LegalizeOp(CallInfo.second); 1988 return CallInfo; 1989} 1990 1991SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1992 RTLIB::Libcall Call_F32, 1993 RTLIB::Libcall Call_F64, 1994 RTLIB::Libcall Call_F80, 1995 RTLIB::Libcall Call_PPCF128) { 1996 RTLIB::Libcall LC; 1997 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1998 default: assert(0 && "Unexpected request for libcall!"); 1999 case MVT::f32: LC = Call_F32; break; 2000 case MVT::f64: LC = Call_F64; break; 2001 case MVT::f80: LC = Call_F80; break; 2002 case MVT::ppcf128: LC = Call_PPCF128; break; 2003 } 2004 return ExpandLibCall(LC, Node, false); 2005} 2006 2007SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 2008 RTLIB::Libcall Call_I8, 2009 RTLIB::Libcall Call_I16, 2010 RTLIB::Libcall Call_I32, 2011 RTLIB::Libcall Call_I64, 2012 RTLIB::Libcall Call_I128) { 2013 RTLIB::Libcall LC; 2014 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2015 default: assert(0 && "Unexpected request for libcall!"); 2016 case MVT::i8: LC = Call_I8; break; 2017 case MVT::i16: LC = Call_I16; break; 2018 case MVT::i32: LC = Call_I32; break; 2019 case MVT::i64: LC = Call_I64; break; 2020 case MVT::i128: LC = Call_I128; break; 2021 } 2022 return ExpandLibCall(LC, Node, isSigned); 2023} 2024 2025/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 2026/// INT_TO_FP operation of the specified operand when the target requests that 2027/// we expand it. At this point, we know that the result and operand types are 2028/// legal for the target. 2029SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 2030 SDValue Op0, 2031 EVT DestVT, 2032 DebugLoc dl) { 2033 if (Op0.getValueType() == MVT::i32) { 2034 // simple 32-bit [signed|unsigned] integer to float/double expansion 2035 2036 // Get the stack frame index of a 8 byte buffer. 2037 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 2038 2039 // word offset constant for Hi/Lo address computation 2040 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 2041 // set up Hi and Lo (into buffer) address based on endian 2042 SDValue Hi = StackSlot; 2043 SDValue Lo = DAG.getNode(ISD::ADD, dl, 2044 TLI.getPointerTy(), StackSlot, WordOff); 2045 if (TLI.isLittleEndian()) 2046 std::swap(Hi, Lo); 2047 2048 // if signed map to unsigned space 2049 SDValue Op0Mapped; 2050 if (isSigned) { 2051 // constant used to invert sign bit (signed to unsigned mapping) 2052 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 2053 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 2054 } else { 2055 Op0Mapped = Op0; 2056 } 2057 // store the lo of the constructed double - based on integer input 2058 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 2059 Op0Mapped, Lo, NULL, 0, 2060 false, false, 0); 2061 // initial hi portion of constructed double 2062 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2063 // store the hi of the constructed double - biased exponent 2064 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0, 2065 false, false, 0); 2066 // load the constructed double 2067 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0, 2068 false, false, 0); 2069 // FP constant to bias correct the final result 2070 SDValue Bias = DAG.getConstantFP(isSigned ? 2071 BitsToDouble(0x4330000080000000ULL) : 2072 BitsToDouble(0x4330000000000000ULL), 2073 MVT::f64); 2074 // subtract the bias 2075 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2076 // final result 2077 SDValue Result; 2078 // handle final rounding 2079 if (DestVT == MVT::f64) { 2080 // do nothing 2081 Result = Sub; 2082 } else if (DestVT.bitsLT(MVT::f64)) { 2083 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2084 DAG.getIntPtrConstant(0)); 2085 } else if (DestVT.bitsGT(MVT::f64)) { 2086 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2087 } 2088 return Result; 2089 } 2090 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2091 // Code below here assumes !isSigned without checking again. 2092 2093 // Implementation of unsigned i64 to f64 following the algorithm in 2094 // __floatundidf in compiler_rt. This implementation has the advantage 2095 // of performing rounding correctly, both in the default rounding mode 2096 // and in all alternate rounding modes. 2097 // TODO: Generalize this for use with other types. 2098 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2099 SDValue TwoP52 = 2100 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2101 SDValue TwoP84PlusTwoP52 = 2102 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2103 SDValue TwoP84 = 2104 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2105 2106 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2107 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2108 DAG.getConstant(32, MVT::i64)); 2109 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2110 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2111 SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr); 2112 SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr); 2113 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, 2114 TwoP84PlusTwoP52); 2115 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2116 } 2117 2118 // Implementation of unsigned i64 to f32. This implementation has the 2119 // advantage of performing rounding correctly. 2120 // TODO: Generalize this for use with other types. 2121 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { 2122 EVT SHVT = TLI.getShiftAmountTy(); 2123 2124 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2125 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64)); 2126 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, 2127 DAG.getConstant(UINT64_C(0x800), MVT::i64)); 2128 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2129 DAG.getConstant(UINT64_C(0x7ff), MVT::i64)); 2130 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2131 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); 2132 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0); 2133 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2134 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64), 2135 ISD::SETUGE); 2136 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0); 2137 2138 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2139 DAG.getConstant(32, SHVT)); 2140 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); 2141 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); 2142 SDValue TwoP32 = 2143 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64); 2144 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); 2145 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); 2146 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); 2147 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); 2148 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, 2149 DAG.getIntPtrConstant(0)); 2150 2151 } 2152 2153 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2154 2155 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2156 Op0, DAG.getConstant(0, Op0.getValueType()), 2157 ISD::SETLT); 2158 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2159 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2160 SignSet, Four, Zero); 2161 2162 // If the sign bit of the integer is set, the large number will be treated 2163 // as a negative number. To counteract this, the dynamic code adds an 2164 // offset depending on the data type. 2165 uint64_t FF; 2166 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2167 default: assert(0 && "Unsupported integer type!"); 2168 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2169 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2170 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2171 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2172 } 2173 if (TLI.isLittleEndian()) FF <<= 32; 2174 Constant *FudgeFactor = ConstantInt::get( 2175 Type::getInt64Ty(*DAG.getContext()), FF); 2176 2177 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2178 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2179 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2180 Alignment = std::min(Alignment, 4u); 2181 SDValue FudgeInReg; 2182 if (DestVT == MVT::f32) 2183 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2184 PseudoSourceValue::getConstantPool(), 0, 2185 false, false, Alignment); 2186 else { 2187 FudgeInReg = 2188 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, 2189 DAG.getEntryNode(), CPIdx, 2190 PseudoSourceValue::getConstantPool(), 0, 2191 MVT::f32, false, false, Alignment)); 2192 } 2193 2194 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2195} 2196 2197/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2198/// *INT_TO_FP operation of the specified operand when the target requests that 2199/// we promote it. At this point, we know that the result and operand types are 2200/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2201/// operation that takes a larger input. 2202SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2203 EVT DestVT, 2204 bool isSigned, 2205 DebugLoc dl) { 2206 // First step, figure out the appropriate *INT_TO_FP operation to use. 2207 EVT NewInTy = LegalOp.getValueType(); 2208 2209 unsigned OpToUse = 0; 2210 2211 // Scan for the appropriate larger type to use. 2212 while (1) { 2213 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2214 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2215 2216 // If the target supports SINT_TO_FP of this type, use it. 2217 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2218 OpToUse = ISD::SINT_TO_FP; 2219 break; 2220 } 2221 if (isSigned) continue; 2222 2223 // If the target supports UINT_TO_FP of this type, use it. 2224 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2225 OpToUse = ISD::UINT_TO_FP; 2226 break; 2227 } 2228 2229 // Otherwise, try a larger type. 2230 } 2231 2232 // Okay, we found the operation and type to use. Zero extend our input to the 2233 // desired type then run the operation on it. 2234 return DAG.getNode(OpToUse, dl, DestVT, 2235 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2236 dl, NewInTy, LegalOp)); 2237} 2238 2239/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2240/// FP_TO_*INT operation of the specified operand when the target requests that 2241/// we promote it. At this point, we know that the result and operand types are 2242/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2243/// operation that returns a larger result. 2244SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2245 EVT DestVT, 2246 bool isSigned, 2247 DebugLoc dl) { 2248 // First step, figure out the appropriate FP_TO*INT operation to use. 2249 EVT NewOutTy = DestVT; 2250 2251 unsigned OpToUse = 0; 2252 2253 // Scan for the appropriate larger type to use. 2254 while (1) { 2255 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2256 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2257 2258 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2259 OpToUse = ISD::FP_TO_SINT; 2260 break; 2261 } 2262 2263 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2264 OpToUse = ISD::FP_TO_UINT; 2265 break; 2266 } 2267 2268 // Otherwise, try a larger type. 2269 } 2270 2271 2272 // Okay, we found the operation and type to use. 2273 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2274 2275 // Truncate the result of the extended FP_TO_*INT operation to the desired 2276 // size. 2277 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2278} 2279 2280/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2281/// 2282SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2283 EVT VT = Op.getValueType(); 2284 EVT SHVT = TLI.getShiftAmountTy(); 2285 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2286 switch (VT.getSimpleVT().SimpleTy) { 2287 default: assert(0 && "Unhandled Expand type in BSWAP!"); 2288 case MVT::i16: 2289 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2290 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2291 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2292 case MVT::i32: 2293 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2294 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2295 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2296 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2297 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2298 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2299 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2300 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2301 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2302 case MVT::i64: 2303 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2304 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2305 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2306 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2307 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2308 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2309 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2310 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2311 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2312 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2313 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2314 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2315 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2316 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2317 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2318 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2319 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2320 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2321 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2322 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2323 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2324 } 2325} 2326 2327/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2328/// 2329SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2330 DebugLoc dl) { 2331 switch (Opc) { 2332 default: assert(0 && "Cannot expand this yet!"); 2333 case ISD::CTPOP: { 2334 static const uint64_t mask[6] = { 2335 0x5555555555555555ULL, 0x3333333333333333ULL, 2336 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2337 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2338 }; 2339 EVT VT = Op.getValueType(); 2340 EVT ShVT = TLI.getShiftAmountTy(); 2341 unsigned len = VT.getSizeInBits(); 2342 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2343 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2344 unsigned EltSize = VT.isVector() ? 2345 VT.getVectorElementType().getSizeInBits() : len; 2346 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2347 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2348 Op = DAG.getNode(ISD::ADD, dl, VT, 2349 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2350 DAG.getNode(ISD::AND, dl, VT, 2351 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2352 Tmp2)); 2353 } 2354 return Op; 2355 } 2356 case ISD::CTLZ: { 2357 // for now, we do this: 2358 // x = x | (x >> 1); 2359 // x = x | (x >> 2); 2360 // ... 2361 // x = x | (x >>16); 2362 // x = x | (x >>32); // for 64-bit input 2363 // return popcount(~x); 2364 // 2365 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2366 EVT VT = Op.getValueType(); 2367 EVT ShVT = TLI.getShiftAmountTy(); 2368 unsigned len = VT.getSizeInBits(); 2369 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2370 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2371 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2372 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2373 } 2374 Op = DAG.getNOT(dl, Op, VT); 2375 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2376 } 2377 case ISD::CTTZ: { 2378 // for now, we use: { return popcount(~x & (x - 1)); } 2379 // unless the target has ctlz but not ctpop, in which case we use: 2380 // { return 32 - nlz(~x & (x-1)); } 2381 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2382 EVT VT = Op.getValueType(); 2383 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2384 DAG.getNOT(dl, Op, VT), 2385 DAG.getNode(ISD::SUB, dl, VT, Op, 2386 DAG.getConstant(1, VT))); 2387 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2388 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2389 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2390 return DAG.getNode(ISD::SUB, dl, VT, 2391 DAG.getConstant(VT.getSizeInBits(), VT), 2392 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2393 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2394 } 2395 } 2396} 2397 2398std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) { 2399 unsigned Opc = Node->getOpcode(); 2400 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 2401 RTLIB::Libcall LC; 2402 2403 switch (Opc) { 2404 default: 2405 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 2406 break; 2407 case ISD::ATOMIC_SWAP: 2408 switch (VT.SimpleTy) { 2409 default: llvm_unreachable("Unexpected value type for atomic!"); 2410 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 2411 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 2412 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 2413 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 2414 } 2415 break; 2416 case ISD::ATOMIC_CMP_SWAP: 2417 switch (VT.SimpleTy) { 2418 default: llvm_unreachable("Unexpected value type for atomic!"); 2419 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 2420 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 2421 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 2422 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 2423 } 2424 break; 2425 case ISD::ATOMIC_LOAD_ADD: 2426 switch (VT.SimpleTy) { 2427 default: llvm_unreachable("Unexpected value type for atomic!"); 2428 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 2429 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 2430 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 2431 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 2432 } 2433 break; 2434 case ISD::ATOMIC_LOAD_SUB: 2435 switch (VT.SimpleTy) { 2436 default: llvm_unreachable("Unexpected value type for atomic!"); 2437 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 2438 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 2439 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 2440 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 2441 } 2442 break; 2443 case ISD::ATOMIC_LOAD_AND: 2444 switch (VT.SimpleTy) { 2445 default: llvm_unreachable("Unexpected value type for atomic!"); 2446 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 2447 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 2448 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 2449 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 2450 } 2451 break; 2452 case ISD::ATOMIC_LOAD_OR: 2453 switch (VT.SimpleTy) { 2454 default: llvm_unreachable("Unexpected value type for atomic!"); 2455 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 2456 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 2457 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 2458 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 2459 } 2460 break; 2461 case ISD::ATOMIC_LOAD_XOR: 2462 switch (VT.SimpleTy) { 2463 default: llvm_unreachable("Unexpected value type for atomic!"); 2464 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 2465 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 2466 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 2467 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 2468 } 2469 break; 2470 case ISD::ATOMIC_LOAD_NAND: 2471 switch (VT.SimpleTy) { 2472 default: llvm_unreachable("Unexpected value type for atomic!"); 2473 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 2474 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 2475 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 2476 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 2477 } 2478 break; 2479 } 2480 2481 return ExpandChainLibCall(LC, Node, false); 2482} 2483 2484void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2485 SmallVectorImpl<SDValue> &Results) { 2486 DebugLoc dl = Node->getDebugLoc(); 2487 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2488 switch (Node->getOpcode()) { 2489 case ISD::CTPOP: 2490 case ISD::CTLZ: 2491 case ISD::CTTZ: 2492 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2493 Results.push_back(Tmp1); 2494 break; 2495 case ISD::BSWAP: 2496 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2497 break; 2498 case ISD::FRAMEADDR: 2499 case ISD::RETURNADDR: 2500 case ISD::FRAME_TO_ARGS_OFFSET: 2501 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2502 break; 2503 case ISD::FLT_ROUNDS_: 2504 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2505 break; 2506 case ISD::EH_RETURN: 2507 case ISD::EH_LABEL: 2508 case ISD::PREFETCH: 2509 case ISD::VAEND: 2510 case ISD::EH_SJLJ_LONGJMP: 2511 Results.push_back(Node->getOperand(0)); 2512 break; 2513 case ISD::EH_SJLJ_SETJMP: 2514 Results.push_back(DAG.getConstant(0, MVT::i32)); 2515 Results.push_back(Node->getOperand(0)); 2516 break; 2517 case ISD::MEMBARRIER: { 2518 // If the target didn't lower this, lower it to '__sync_synchronize()' call 2519 TargetLowering::ArgListTy Args; 2520 std::pair<SDValue, SDValue> CallResult = 2521 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2522 false, false, false, false, 0, CallingConv::C, false, 2523 /*isReturnValueUsed=*/true, 2524 DAG.getExternalSymbol("__sync_synchronize", 2525 TLI.getPointerTy()), 2526 Args, DAG, dl); 2527 Results.push_back(CallResult.second); 2528 break; 2529 } 2530 // By default, atomic intrinsics are marked Legal and lowered. Targets 2531 // which don't support them directly, however, may want libcalls, in which 2532 // case they mark them Expand, and we get here. 2533 // FIXME: Unimplemented for now. Add libcalls. 2534 case ISD::ATOMIC_SWAP: 2535 case ISD::ATOMIC_LOAD_ADD: 2536 case ISD::ATOMIC_LOAD_SUB: 2537 case ISD::ATOMIC_LOAD_AND: 2538 case ISD::ATOMIC_LOAD_OR: 2539 case ISD::ATOMIC_LOAD_XOR: 2540 case ISD::ATOMIC_LOAD_NAND: 2541 case ISD::ATOMIC_LOAD_MIN: 2542 case ISD::ATOMIC_LOAD_MAX: 2543 case ISD::ATOMIC_LOAD_UMIN: 2544 case ISD::ATOMIC_LOAD_UMAX: 2545 case ISD::ATOMIC_CMP_SWAP: { 2546 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node); 2547 Results.push_back(Tmp.first); 2548 Results.push_back(Tmp.second); 2549 break; 2550 } 2551 case ISD::DYNAMIC_STACKALLOC: 2552 ExpandDYNAMIC_STACKALLOC(Node, Results); 2553 break; 2554 case ISD::MERGE_VALUES: 2555 for (unsigned i = 0; i < Node->getNumValues(); i++) 2556 Results.push_back(Node->getOperand(i)); 2557 break; 2558 case ISD::UNDEF: { 2559 EVT VT = Node->getValueType(0); 2560 if (VT.isInteger()) 2561 Results.push_back(DAG.getConstant(0, VT)); 2562 else { 2563 assert(VT.isFloatingPoint() && "Unknown value type!"); 2564 Results.push_back(DAG.getConstantFP(0, VT)); 2565 } 2566 break; 2567 } 2568 case ISD::TRAP: { 2569 // If this operation is not supported, lower it to 'abort()' call 2570 TargetLowering::ArgListTy Args; 2571 std::pair<SDValue, SDValue> CallResult = 2572 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2573 false, false, false, false, 0, CallingConv::C, false, 2574 /*isReturnValueUsed=*/true, 2575 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2576 Args, DAG, dl); 2577 Results.push_back(CallResult.second); 2578 break; 2579 } 2580 case ISD::FP_ROUND: 2581 case ISD::BIT_CONVERT: 2582 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2583 Node->getValueType(0), dl); 2584 Results.push_back(Tmp1); 2585 break; 2586 case ISD::FP_EXTEND: 2587 Tmp1 = EmitStackConvert(Node->getOperand(0), 2588 Node->getOperand(0).getValueType(), 2589 Node->getValueType(0), dl); 2590 Results.push_back(Tmp1); 2591 break; 2592 case ISD::SIGN_EXTEND_INREG: { 2593 // NOTE: we could fall back on load/store here too for targets without 2594 // SAR. However, it is doubtful that any exist. 2595 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2596 EVT VT = Node->getValueType(0); 2597 EVT ShiftAmountTy = TLI.getShiftAmountTy(); 2598 if (VT.isVector()) 2599 ShiftAmountTy = VT; 2600 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2601 ExtraVT.getScalarType().getSizeInBits(); 2602 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2603 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2604 Node->getOperand(0), ShiftCst); 2605 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2606 Results.push_back(Tmp1); 2607 break; 2608 } 2609 case ISD::FP_ROUND_INREG: { 2610 // The only way we can lower this is to turn it into a TRUNCSTORE, 2611 // EXTLOAD pair, targetting a temporary location (a stack slot). 2612 2613 // NOTE: there is a choice here between constantly creating new stack 2614 // slots and always reusing the same one. We currently always create 2615 // new ones, as reuse may inhibit scheduling. 2616 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2617 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2618 Node->getValueType(0), dl); 2619 Results.push_back(Tmp1); 2620 break; 2621 } 2622 case ISD::SINT_TO_FP: 2623 case ISD::UINT_TO_FP: 2624 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2625 Node->getOperand(0), Node->getValueType(0), dl); 2626 Results.push_back(Tmp1); 2627 break; 2628 case ISD::FP_TO_UINT: { 2629 SDValue True, False; 2630 EVT VT = Node->getOperand(0).getValueType(); 2631 EVT NVT = Node->getValueType(0); 2632 const uint64_t zero[] = {0, 0}; 2633 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2634 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2635 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2636 Tmp1 = DAG.getConstantFP(apf, VT); 2637 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2638 Node->getOperand(0), 2639 Tmp1, ISD::SETLT); 2640 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2641 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2642 DAG.getNode(ISD::FSUB, dl, VT, 2643 Node->getOperand(0), Tmp1)); 2644 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2645 DAG.getConstant(x, NVT)); 2646 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2647 Results.push_back(Tmp1); 2648 break; 2649 } 2650 case ISD::VAARG: { 2651 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2652 EVT VT = Node->getValueType(0); 2653 Tmp1 = Node->getOperand(0); 2654 Tmp2 = Node->getOperand(1); 2655 unsigned Align = Node->getConstantOperandVal(3); 2656 2657 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0, 2658 false, false, 0); 2659 SDValue VAList = VAListLoad; 2660 2661 if (Align != 0 ) { 2662 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2663 DAG.getConstant(Align - 1, 2664 TLI.getPointerTy())); 2665 2666 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList, 2667 DAG.getConstant(-Align, 2668 TLI.getPointerTy())); 2669 } 2670 2671 // Increment the pointer, VAList, to the next vaarg 2672 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2673 DAG.getConstant(TLI.getTargetData()-> 2674 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2675 TLI.getPointerTy())); 2676 // Store the incremented VAList to the legalized pointer 2677 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, V, 0, 2678 false, false, 0); 2679 // Load the actual argument out of the pointer VAList 2680 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0, 2681 false, false, 0)); 2682 Results.push_back(Results[0].getValue(1)); 2683 break; 2684 } 2685 case ISD::VACOPY: { 2686 // This defaults to loading a pointer from the input and storing it to the 2687 // output, returning the chain. 2688 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2689 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2690 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2691 Node->getOperand(2), VS, 0, false, false, 0); 2692 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0, 2693 false, false, 0); 2694 Results.push_back(Tmp1); 2695 break; 2696 } 2697 case ISD::EXTRACT_VECTOR_ELT: 2698 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2699 // This must be an access of the only element. Return it. 2700 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2701 Node->getOperand(0)); 2702 else 2703 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2704 Results.push_back(Tmp1); 2705 break; 2706 case ISD::EXTRACT_SUBVECTOR: 2707 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2708 break; 2709 case ISD::CONCAT_VECTORS: { 2710 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2711 break; 2712 } 2713 case ISD::SCALAR_TO_VECTOR: 2714 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2715 break; 2716 case ISD::INSERT_VECTOR_ELT: 2717 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2718 Node->getOperand(1), 2719 Node->getOperand(2), dl)); 2720 break; 2721 case ISD::VECTOR_SHUFFLE: { 2722 SmallVector<int, 8> Mask; 2723 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2724 2725 EVT VT = Node->getValueType(0); 2726 EVT EltVT = VT.getVectorElementType(); 2727 if (getTypeAction(EltVT) == Promote) 2728 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT); 2729 unsigned NumElems = VT.getVectorNumElements(); 2730 SmallVector<SDValue, 8> Ops; 2731 for (unsigned i = 0; i != NumElems; ++i) { 2732 if (Mask[i] < 0) { 2733 Ops.push_back(DAG.getUNDEF(EltVT)); 2734 continue; 2735 } 2736 unsigned Idx = Mask[i]; 2737 if (Idx < NumElems) 2738 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2739 Node->getOperand(0), 2740 DAG.getIntPtrConstant(Idx))); 2741 else 2742 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2743 Node->getOperand(1), 2744 DAG.getIntPtrConstant(Idx - NumElems))); 2745 } 2746 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2747 Results.push_back(Tmp1); 2748 break; 2749 } 2750 case ISD::EXTRACT_ELEMENT: { 2751 EVT OpTy = Node->getOperand(0).getValueType(); 2752 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2753 // 1 -> Hi 2754 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2755 DAG.getConstant(OpTy.getSizeInBits()/2, 2756 TLI.getShiftAmountTy())); 2757 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2758 } else { 2759 // 0 -> Lo 2760 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2761 Node->getOperand(0)); 2762 } 2763 Results.push_back(Tmp1); 2764 break; 2765 } 2766 case ISD::STACKSAVE: 2767 // Expand to CopyFromReg if the target set 2768 // StackPointerRegisterToSaveRestore. 2769 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2770 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2771 Node->getValueType(0))); 2772 Results.push_back(Results[0].getValue(1)); 2773 } else { 2774 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2775 Results.push_back(Node->getOperand(0)); 2776 } 2777 break; 2778 case ISD::STACKRESTORE: 2779 // Expand to CopyToReg if the target set 2780 // StackPointerRegisterToSaveRestore. 2781 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2782 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2783 Node->getOperand(1))); 2784 } else { 2785 Results.push_back(Node->getOperand(0)); 2786 } 2787 break; 2788 case ISD::FCOPYSIGN: 2789 Results.push_back(ExpandFCOPYSIGN(Node)); 2790 break; 2791 case ISD::FNEG: 2792 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2793 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2794 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2795 Node->getOperand(0)); 2796 Results.push_back(Tmp1); 2797 break; 2798 case ISD::FABS: { 2799 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2800 EVT VT = Node->getValueType(0); 2801 Tmp1 = Node->getOperand(0); 2802 Tmp2 = DAG.getConstantFP(0.0, VT); 2803 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2804 Tmp1, Tmp2, ISD::SETUGT); 2805 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2806 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2807 Results.push_back(Tmp1); 2808 break; 2809 } 2810 case ISD::FSQRT: 2811 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2812 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2813 break; 2814 case ISD::FSIN: 2815 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2816 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2817 break; 2818 case ISD::FCOS: 2819 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2820 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2821 break; 2822 case ISD::FLOG: 2823 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2824 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2825 break; 2826 case ISD::FLOG2: 2827 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2828 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2829 break; 2830 case ISD::FLOG10: 2831 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2832 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2833 break; 2834 case ISD::FEXP: 2835 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2836 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2837 break; 2838 case ISD::FEXP2: 2839 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2840 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2841 break; 2842 case ISD::FTRUNC: 2843 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2844 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2845 break; 2846 case ISD::FFLOOR: 2847 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2848 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2849 break; 2850 case ISD::FCEIL: 2851 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2852 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2853 break; 2854 case ISD::FRINT: 2855 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2856 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2857 break; 2858 case ISD::FNEARBYINT: 2859 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2860 RTLIB::NEARBYINT_F64, 2861 RTLIB::NEARBYINT_F80, 2862 RTLIB::NEARBYINT_PPCF128)); 2863 break; 2864 case ISD::FPOWI: 2865 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2866 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2867 break; 2868 case ISD::FPOW: 2869 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2870 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2871 break; 2872 case ISD::FDIV: 2873 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2874 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2875 break; 2876 case ISD::FREM: 2877 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2878 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2879 break; 2880 case ISD::FP16_TO_FP32: 2881 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 2882 break; 2883 case ISD::FP32_TO_FP16: 2884 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 2885 break; 2886 case ISD::ConstantFP: { 2887 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2888 // Check to see if this FP immediate is already legal. 2889 // If this is a legal constant, turn it into a TargetConstantFP node. 2890 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 2891 Results.push_back(SDValue(Node, 0)); 2892 else 2893 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2894 break; 2895 } 2896 case ISD::EHSELECTION: { 2897 unsigned Reg = TLI.getExceptionSelectorRegister(); 2898 assert(Reg && "Can't expand to unknown register!"); 2899 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2900 Node->getValueType(0))); 2901 Results.push_back(Results[0].getValue(1)); 2902 break; 2903 } 2904 case ISD::EXCEPTIONADDR: { 2905 unsigned Reg = TLI.getExceptionAddressRegister(); 2906 assert(Reg && "Can't expand to unknown register!"); 2907 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2908 Node->getValueType(0))); 2909 Results.push_back(Results[0].getValue(1)); 2910 break; 2911 } 2912 case ISD::SUB: { 2913 EVT VT = Node->getValueType(0); 2914 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2915 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2916 "Don't know how to expand this subtraction!"); 2917 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2918 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2919 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2920 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2921 break; 2922 } 2923 case ISD::UREM: 2924 case ISD::SREM: { 2925 EVT VT = Node->getValueType(0); 2926 SDVTList VTs = DAG.getVTList(VT, VT); 2927 bool isSigned = Node->getOpcode() == ISD::SREM; 2928 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2929 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2930 Tmp2 = Node->getOperand(0); 2931 Tmp3 = Node->getOperand(1); 2932 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2933 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2934 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2935 // X % Y -> X-X/Y*Y 2936 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2937 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2938 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2939 } else if (isSigned) { 2940 Tmp1 = ExpandIntLibCall(Node, true, 2941 RTLIB::SREM_I8, 2942 RTLIB::SREM_I16, RTLIB::SREM_I32, 2943 RTLIB::SREM_I64, RTLIB::SREM_I128); 2944 } else { 2945 Tmp1 = ExpandIntLibCall(Node, false, 2946 RTLIB::UREM_I8, 2947 RTLIB::UREM_I16, RTLIB::UREM_I32, 2948 RTLIB::UREM_I64, RTLIB::UREM_I128); 2949 } 2950 Results.push_back(Tmp1); 2951 break; 2952 } 2953 case ISD::UDIV: 2954 case ISD::SDIV: { 2955 bool isSigned = Node->getOpcode() == ISD::SDIV; 2956 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2957 EVT VT = Node->getValueType(0); 2958 SDVTList VTs = DAG.getVTList(VT, VT); 2959 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2960 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2961 Node->getOperand(1)); 2962 else if (isSigned) 2963 Tmp1 = ExpandIntLibCall(Node, true, 2964 RTLIB::SDIV_I8, 2965 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2966 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2967 else 2968 Tmp1 = ExpandIntLibCall(Node, false, 2969 RTLIB::UDIV_I8, 2970 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2971 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2972 Results.push_back(Tmp1); 2973 break; 2974 } 2975 case ISD::MULHU: 2976 case ISD::MULHS: { 2977 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2978 ISD::SMUL_LOHI; 2979 EVT VT = Node->getValueType(0); 2980 SDVTList VTs = DAG.getVTList(VT, VT); 2981 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2982 "If this wasn't legal, it shouldn't have been created!"); 2983 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 2984 Node->getOperand(1)); 2985 Results.push_back(Tmp1.getValue(1)); 2986 break; 2987 } 2988 case ISD::MUL: { 2989 EVT VT = Node->getValueType(0); 2990 SDVTList VTs = DAG.getVTList(VT, VT); 2991 // See if multiply or divide can be lowered using two-result operations. 2992 // We just need the low half of the multiply; try both the signed 2993 // and unsigned forms. If the target supports both SMUL_LOHI and 2994 // UMUL_LOHI, form a preference by checking which forms of plain 2995 // MULH it supports. 2996 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 2997 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 2998 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 2999 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 3000 unsigned OpToUse = 0; 3001 if (HasSMUL_LOHI && !HasMULHS) { 3002 OpToUse = ISD::SMUL_LOHI; 3003 } else if (HasUMUL_LOHI && !HasMULHU) { 3004 OpToUse = ISD::UMUL_LOHI; 3005 } else if (HasSMUL_LOHI) { 3006 OpToUse = ISD::SMUL_LOHI; 3007 } else if (HasUMUL_LOHI) { 3008 OpToUse = ISD::UMUL_LOHI; 3009 } 3010 if (OpToUse) { 3011 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 3012 Node->getOperand(1))); 3013 break; 3014 } 3015 Tmp1 = ExpandIntLibCall(Node, false, 3016 RTLIB::MUL_I8, 3017 RTLIB::MUL_I16, RTLIB::MUL_I32, 3018 RTLIB::MUL_I64, RTLIB::MUL_I128); 3019 Results.push_back(Tmp1); 3020 break; 3021 } 3022 case ISD::SADDO: 3023 case ISD::SSUBO: { 3024 SDValue LHS = Node->getOperand(0); 3025 SDValue RHS = Node->getOperand(1); 3026 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 3027 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3028 LHS, RHS); 3029 Results.push_back(Sum); 3030 EVT OType = Node->getValueType(1); 3031 3032 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 3033 3034 // LHSSign -> LHS >= 0 3035 // RHSSign -> RHS >= 0 3036 // SumSign -> Sum >= 0 3037 // 3038 // Add: 3039 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 3040 // Sub: 3041 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 3042 // 3043 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 3044 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 3045 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 3046 Node->getOpcode() == ISD::SADDO ? 3047 ISD::SETEQ : ISD::SETNE); 3048 3049 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 3050 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 3051 3052 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 3053 Results.push_back(Cmp); 3054 break; 3055 } 3056 case ISD::UADDO: 3057 case ISD::USUBO: { 3058 SDValue LHS = Node->getOperand(0); 3059 SDValue RHS = Node->getOperand(1); 3060 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 3061 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3062 LHS, RHS); 3063 Results.push_back(Sum); 3064 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 3065 Node->getOpcode () == ISD::UADDO ? 3066 ISD::SETULT : ISD::SETUGT)); 3067 break; 3068 } 3069 case ISD::UMULO: 3070 case ISD::SMULO: { 3071 EVT VT = Node->getValueType(0); 3072 SDValue LHS = Node->getOperand(0); 3073 SDValue RHS = Node->getOperand(1); 3074 SDValue BottomHalf; 3075 SDValue TopHalf; 3076 static const unsigned Ops[2][3] = 3077 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 3078 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 3079 bool isSigned = Node->getOpcode() == ISD::SMULO; 3080 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 3081 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 3082 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 3083 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 3084 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 3085 RHS); 3086 TopHalf = BottomHalf.getValue(1); 3087 } else { 3088 // FIXME: We should be able to fall back to a libcall with an illegal 3089 // type in some cases. 3090 // Also, we can fall back to a division in some cases, but that's a big 3091 // performance hit in the general case. 3092 assert(TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), 3093 VT.getSizeInBits() * 2)) && 3094 "Don't know how to expand this operation yet!"); 3095 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 3096 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 3097 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 3098 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 3099 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3100 DAG.getIntPtrConstant(0)); 3101 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3102 DAG.getIntPtrConstant(1)); 3103 } 3104 if (isSigned) { 3105 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); 3106 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 3107 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 3108 ISD::SETNE); 3109 } else { 3110 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 3111 DAG.getConstant(0, VT), ISD::SETNE); 3112 } 3113 Results.push_back(BottomHalf); 3114 Results.push_back(TopHalf); 3115 break; 3116 } 3117 case ISD::BUILD_PAIR: { 3118 EVT PairTy = Node->getValueType(0); 3119 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 3120 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 3121 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 3122 DAG.getConstant(PairTy.getSizeInBits()/2, 3123 TLI.getShiftAmountTy())); 3124 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 3125 break; 3126 } 3127 case ISD::SELECT: 3128 Tmp1 = Node->getOperand(0); 3129 Tmp2 = Node->getOperand(1); 3130 Tmp3 = Node->getOperand(2); 3131 if (Tmp1.getOpcode() == ISD::SETCC) { 3132 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 3133 Tmp2, Tmp3, 3134 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 3135 } else { 3136 Tmp1 = DAG.getSelectCC(dl, Tmp1, 3137 DAG.getConstant(0, Tmp1.getValueType()), 3138 Tmp2, Tmp3, ISD::SETNE); 3139 } 3140 Results.push_back(Tmp1); 3141 break; 3142 case ISD::BR_JT: { 3143 SDValue Chain = Node->getOperand(0); 3144 SDValue Table = Node->getOperand(1); 3145 SDValue Index = Node->getOperand(2); 3146 3147 EVT PTy = TLI.getPointerTy(); 3148 3149 const TargetData &TD = *TLI.getTargetData(); 3150 unsigned EntrySize = 3151 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 3152 3153 Index = DAG.getNode(ISD::MUL, dl, PTy, 3154 Index, DAG.getConstant(EntrySize, PTy)); 3155 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 3156 3157 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 3158 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, dl, Chain, Addr, 3159 PseudoSourceValue::getJumpTable(), 0, MemVT, 3160 false, false, 0); 3161 Addr = LD; 3162 if (TM.getRelocationModel() == Reloc::PIC_) { 3163 // For PIC, the sequence is: 3164 // BRIND(load(Jumptable + index) + RelocBase) 3165 // RelocBase can be JumpTable, GOT or some sort of global base. 3166 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 3167 TLI.getPICJumpTableRelocBase(Table, DAG)); 3168 } 3169 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 3170 Results.push_back(Tmp1); 3171 break; 3172 } 3173 case ISD::BRCOND: 3174 // Expand brcond's setcc into its constituent parts and create a BR_CC 3175 // Node. 3176 Tmp1 = Node->getOperand(0); 3177 Tmp2 = Node->getOperand(1); 3178 if (Tmp2.getOpcode() == ISD::SETCC) { 3179 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 3180 Tmp1, Tmp2.getOperand(2), 3181 Tmp2.getOperand(0), Tmp2.getOperand(1), 3182 Node->getOperand(2)); 3183 } else { 3184 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 3185 DAG.getCondCode(ISD::SETNE), Tmp2, 3186 DAG.getConstant(0, Tmp2.getValueType()), 3187 Node->getOperand(2)); 3188 } 3189 Results.push_back(Tmp1); 3190 break; 3191 case ISD::SETCC: { 3192 Tmp1 = Node->getOperand(0); 3193 Tmp2 = Node->getOperand(1); 3194 Tmp3 = Node->getOperand(2); 3195 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 3196 3197 // If we expanded the SETCC into an AND/OR, return the new node 3198 if (Tmp2.getNode() == 0) { 3199 Results.push_back(Tmp1); 3200 break; 3201 } 3202 3203 // Otherwise, SETCC for the given comparison type must be completely 3204 // illegal; expand it into a SELECT_CC. 3205 EVT VT = Node->getValueType(0); 3206 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3207 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 3208 Results.push_back(Tmp1); 3209 break; 3210 } 3211 case ISD::SELECT_CC: { 3212 Tmp1 = Node->getOperand(0); // LHS 3213 Tmp2 = Node->getOperand(1); // RHS 3214 Tmp3 = Node->getOperand(2); // True 3215 Tmp4 = Node->getOperand(3); // False 3216 SDValue CC = Node->getOperand(4); 3217 3218 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 3219 Tmp1, Tmp2, CC, dl); 3220 3221 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 3222 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3223 CC = DAG.getCondCode(ISD::SETNE); 3224 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 3225 Tmp3, Tmp4, CC); 3226 Results.push_back(Tmp1); 3227 break; 3228 } 3229 case ISD::BR_CC: { 3230 Tmp1 = Node->getOperand(0); // Chain 3231 Tmp2 = Node->getOperand(2); // LHS 3232 Tmp3 = Node->getOperand(3); // RHS 3233 Tmp4 = Node->getOperand(1); // CC 3234 3235 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 3236 Tmp2, Tmp3, Tmp4, dl); 3237 LastCALLSEQ_END = DAG.getEntryNode(); 3238 3239 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 3240 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 3241 Tmp4 = DAG.getCondCode(ISD::SETNE); 3242 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3243 Tmp3, Node->getOperand(4)); 3244 Results.push_back(Tmp1); 3245 break; 3246 } 3247 case ISD::GLOBAL_OFFSET_TABLE: 3248 case ISD::GlobalAddress: 3249 case ISD::GlobalTLSAddress: 3250 case ISD::ExternalSymbol: 3251 case ISD::ConstantPool: 3252 case ISD::JumpTable: 3253 case ISD::INTRINSIC_W_CHAIN: 3254 case ISD::INTRINSIC_WO_CHAIN: 3255 case ISD::INTRINSIC_VOID: 3256 // FIXME: Custom lowering for these operations shouldn't return null! 3257 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3258 Results.push_back(SDValue(Node, i)); 3259 break; 3260 } 3261} 3262void SelectionDAGLegalize::PromoteNode(SDNode *Node, 3263 SmallVectorImpl<SDValue> &Results) { 3264 EVT OVT = Node->getValueType(0); 3265 if (Node->getOpcode() == ISD::UINT_TO_FP || 3266 Node->getOpcode() == ISD::SINT_TO_FP || 3267 Node->getOpcode() == ISD::SETCC) { 3268 OVT = Node->getOperand(0).getValueType(); 3269 } 3270 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3271 DebugLoc dl = Node->getDebugLoc(); 3272 SDValue Tmp1, Tmp2, Tmp3; 3273 switch (Node->getOpcode()) { 3274 case ISD::CTTZ: 3275 case ISD::CTLZ: 3276 case ISD::CTPOP: 3277 // Zero extend the argument. 3278 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3279 // Perform the larger operation. 3280 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3281 if (Node->getOpcode() == ISD::CTTZ) { 3282 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3283 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3284 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3285 ISD::SETEQ); 3286 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3287 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3288 } else if (Node->getOpcode() == ISD::CTLZ) { 3289 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3290 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3291 DAG.getConstant(NVT.getSizeInBits() - 3292 OVT.getSizeInBits(), NVT)); 3293 } 3294 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3295 break; 3296 case ISD::BSWAP: { 3297 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3298 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3299 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3300 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3301 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3302 Results.push_back(Tmp1); 3303 break; 3304 } 3305 case ISD::FP_TO_UINT: 3306 case ISD::FP_TO_SINT: 3307 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3308 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3309 Results.push_back(Tmp1); 3310 break; 3311 case ISD::UINT_TO_FP: 3312 case ISD::SINT_TO_FP: 3313 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3314 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3315 Results.push_back(Tmp1); 3316 break; 3317 case ISD::AND: 3318 case ISD::OR: 3319 case ISD::XOR: { 3320 unsigned ExtOp, TruncOp; 3321 if (OVT.isVector()) { 3322 ExtOp = ISD::BIT_CONVERT; 3323 TruncOp = ISD::BIT_CONVERT; 3324 } else { 3325 assert(OVT.isInteger() && "Cannot promote logic operation"); 3326 ExtOp = ISD::ANY_EXTEND; 3327 TruncOp = ISD::TRUNCATE; 3328 } 3329 // Promote each of the values to the new type. 3330 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3331 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3332 // Perform the larger operation, then convert back 3333 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3334 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3335 break; 3336 } 3337 case ISD::SELECT: { 3338 unsigned ExtOp, TruncOp; 3339 if (Node->getValueType(0).isVector()) { 3340 ExtOp = ISD::BIT_CONVERT; 3341 TruncOp = ISD::BIT_CONVERT; 3342 } else if (Node->getValueType(0).isInteger()) { 3343 ExtOp = ISD::ANY_EXTEND; 3344 TruncOp = ISD::TRUNCATE; 3345 } else { 3346 ExtOp = ISD::FP_EXTEND; 3347 TruncOp = ISD::FP_ROUND; 3348 } 3349 Tmp1 = Node->getOperand(0); 3350 // Promote each of the values to the new type. 3351 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3352 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3353 // Perform the larger operation, then round down. 3354 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3355 if (TruncOp != ISD::FP_ROUND) 3356 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3357 else 3358 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3359 DAG.getIntPtrConstant(0)); 3360 Results.push_back(Tmp1); 3361 break; 3362 } 3363 case ISD::VECTOR_SHUFFLE: { 3364 SmallVector<int, 8> Mask; 3365 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3366 3367 // Cast the two input vectors. 3368 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3369 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3370 3371 // Convert the shuffle mask to the right # elements. 3372 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3373 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3374 Results.push_back(Tmp1); 3375 break; 3376 } 3377 case ISD::SETCC: { 3378 unsigned ExtOp = ISD::FP_EXTEND; 3379 if (NVT.isInteger()) { 3380 ISD::CondCode CCCode = 3381 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3382 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3383 } 3384 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3385 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3386 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3387 Tmp1, Tmp2, Node->getOperand(2))); 3388 break; 3389 } 3390 } 3391} 3392 3393// SelectionDAG::Legalize - This is the entry point for the file. 3394// 3395void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) { 3396 /// run - This is the main entry point to this class. 3397 /// 3398 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3399} 3400 3401