LegalizeDAG.cpp revision bd564bfc63163e31f320c3da9749db70992dc35e
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SelectionDAG::Legalize method.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/SelectionDAG.h"
15#include "llvm/CodeGen/MachineFunction.h"
16#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/Target/TargetLowering.h"
18#include "llvm/Target/TargetData.h"
19#include "llvm/Target/TargetOptions.h"
20#include "llvm/CallingConv.h"
21#include "llvm/Constants.h"
22#include "llvm/Support/MathExtras.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/Visibility.h"
25#include "llvm/ADT/SmallVector.h"
26#include <iostream>
27#include <map>
28using namespace llvm;
29
30#ifndef NDEBUG
31static cl::opt<bool>
32ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
33                 cl::desc("Pop up a window to show dags before legalize"));
34#else
35static const bool ViewLegalizeDAGs = 0;
36#endif
37
38//===----------------------------------------------------------------------===//
39/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40/// hacks on it until the target machine can handle it.  This involves
41/// eliminating value sizes the machine cannot handle (promoting small sizes to
42/// large sizes or splitting up large values into small values) as well as
43/// eliminating operations the machine cannot handle.
44///
45/// This code also does a small amount of optimization and recognition of idioms
46/// as part of its processing.  For example, if a target does not support a
47/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48/// will attempt merge setcc and brc instructions into brcc's.
49///
50namespace {
51class VISIBILITY_HIDDEN SelectionDAGLegalize {
52  TargetLowering &TLI;
53  SelectionDAG &DAG;
54
55  // Libcall insertion helpers.
56
57  /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58  /// legalized.  We use this to ensure that calls are properly serialized
59  /// against each other, including inserted libcalls.
60  SDOperand LastCALLSEQ_END;
61
62  /// IsLegalizingCall - This member is used *only* for purposes of providing
63  /// helpful assertions that a libcall isn't created while another call is
64  /// being legalized (which could lead to non-serialized call sequences).
65  bool IsLegalizingCall;
66
67  enum LegalizeAction {
68    Legal,      // The target natively supports this operation.
69    Promote,    // This operation should be executed in a larger type.
70    Expand      // Try to expand this to other ops, otherwise use a libcall.
71  };
72
73  /// ValueTypeActions - This is a bitvector that contains two bits for each
74  /// value type, where the two bits correspond to the LegalizeAction enum.
75  /// This can be queried with "getTypeAction(VT)".
76  TargetLowering::ValueTypeActionImpl ValueTypeActions;
77
78  /// LegalizedNodes - For nodes that are of legal width, and that have more
79  /// than one use, this map indicates what regularized operand to use.  This
80  /// allows us to avoid legalizing the same thing more than once.
81  std::map<SDOperand, SDOperand> LegalizedNodes;
82
83  /// PromotedNodes - For nodes that are below legal width, and that have more
84  /// than one use, this map indicates what promoted value to use.  This allows
85  /// us to avoid promoting the same thing more than once.
86  std::map<SDOperand, SDOperand> PromotedNodes;
87
88  /// ExpandedNodes - For nodes that need to be expanded this map indicates
89  /// which which operands are the expanded version of the input.  This allows
90  /// us to avoid expanding the same node more than once.
91  std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
92
93  /// SplitNodes - For vector nodes that need to be split, this map indicates
94  /// which which operands are the split version of the input.  This allows us
95  /// to avoid splitting the same node more than once.
96  std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
97
98  /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
99  /// concrete packed types, this contains the mapping of ones we have already
100  /// processed to the result.
101  std::map<SDOperand, SDOperand> PackedNodes;
102
103  void AddLegalizedOperand(SDOperand From, SDOperand To) {
104    LegalizedNodes.insert(std::make_pair(From, To));
105    // If someone requests legalization of the new node, return itself.
106    if (From != To)
107      LegalizedNodes.insert(std::make_pair(To, To));
108  }
109  void AddPromotedOperand(SDOperand From, SDOperand To) {
110    bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111    assert(isNew && "Got into the map somehow?");
112    // If someone requests legalization of the new node, return itself.
113    LegalizedNodes.insert(std::make_pair(To, To));
114  }
115
116public:
117
118  SelectionDAGLegalize(SelectionDAG &DAG);
119
120  /// getTypeAction - Return how we should legalize values of this type, either
121  /// it is already legal or we need to expand it into multiple registers of
122  /// smaller integer type, or we need to promote it to a larger type.
123  LegalizeAction getTypeAction(MVT::ValueType VT) const {
124    return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
125  }
126
127  /// isTypeLegal - Return true if this type is legal on this target.
128  ///
129  bool isTypeLegal(MVT::ValueType VT) const {
130    return getTypeAction(VT) == Legal;
131  }
132
133  void LegalizeDAG();
134
135private:
136  /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
137  /// appropriate for its type.
138  void HandleOp(SDOperand Op);
139
140  /// LegalizeOp - We know that the specified value has a legal type.
141  /// Recursively ensure that the operands have legal types, then return the
142  /// result.
143  SDOperand LegalizeOp(SDOperand O);
144
145  /// PromoteOp - Given an operation that produces a value in an invalid type,
146  /// promote it to compute the value into a larger type.  The produced value
147  /// will have the correct bits for the low portion of the register, but no
148  /// guarantee is made about the top bits: it may be zero, sign-extended, or
149  /// garbage.
150  SDOperand PromoteOp(SDOperand O);
151
152  /// ExpandOp - Expand the specified SDOperand into its two component pieces
153  /// Lo&Hi.  Note that the Op MUST be an expanded type.  As a result of this,
154  /// the LegalizeNodes map is filled in for any results that are not expanded,
155  /// the ExpandedNodes map is filled in for any results that are expanded, and
156  /// the Lo/Hi values are returned.   This applies to integer types and Vector
157  /// types.
158  void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
159
160  /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
161  /// two smaller values of MVT::Vector type.
162  void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
163
164  /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
165  /// equivalent operation that returns a packed value (e.g. MVT::V4F32).  When
166  /// this is called, we know that PackedVT is the right type for the result and
167  /// we know that this type is legal for the target.
168  SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
169
170  /// isShuffleLegal - Return true if a vector shuffle is legal with the
171  /// specified mask and type.  Targets can specify exactly which masks they
172  /// support and the code generator is tasked with not creating illegal masks.
173  ///
174  /// Note that this will also return true for shuffles that are promoted to a
175  /// different type.
176  ///
177  /// If this is a legal shuffle, this method returns the (possibly promoted)
178  /// build_vector Mask.  If it's not a legal shuffle, it returns null.
179  SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
180
181  bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
182                                    std::set<SDNode*> &NodesLeadingTo);
183
184  void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
185
186  SDOperand CreateStackTemporary(MVT::ValueType VT);
187
188  SDOperand ExpandLibCall(const char *Name, SDNode *Node,
189                          SDOperand &Hi);
190  SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
191                          SDOperand Source);
192
193  SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
194  SDOperand ExpandBUILD_VECTOR(SDNode *Node);
195  SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
196  SDOperand ExpandLegalINT_TO_FP(bool isSigned,
197                                 SDOperand LegalOp,
198                                 MVT::ValueType DestVT);
199  SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
200                                  bool isSigned);
201  SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
202                                  bool isSigned);
203
204  SDOperand ExpandBSWAP(SDOperand Op);
205  SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
206  bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
207                   SDOperand &Lo, SDOperand &Hi);
208  void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
209                        SDOperand &Lo, SDOperand &Hi);
210
211  SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
212  SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
213
214  SDOperand getIntPtrConstant(uint64_t Val) {
215    return DAG.getConstant(Val, TLI.getPointerTy());
216  }
217};
218}
219
220/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
221/// specified mask and type.  Targets can specify exactly which masks they
222/// support and the code generator is tasked with not creating illegal masks.
223///
224/// Note that this will also return true for shuffles that are promoted to a
225/// different type.
226SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
227                                             SDOperand Mask) const {
228  switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
229  default: return 0;
230  case TargetLowering::Legal:
231  case TargetLowering::Custom:
232    break;
233  case TargetLowering::Promote: {
234    // If this is promoted to a different type, convert the shuffle mask and
235    // ask if it is legal in the promoted type!
236    MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
237
238    // If we changed # elements, change the shuffle mask.
239    unsigned NumEltsGrowth =
240      MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
241    assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
242    if (NumEltsGrowth > 1) {
243      // Renumber the elements.
244      SmallVector<SDOperand, 8> Ops;
245      for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
246        SDOperand InOp = Mask.getOperand(i);
247        for (unsigned j = 0; j != NumEltsGrowth; ++j) {
248          if (InOp.getOpcode() == ISD::UNDEF)
249            Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
250          else {
251            unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
252            Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
253          }
254        }
255      }
256      Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
257    }
258    VT = NVT;
259    break;
260  }
261  }
262  return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
263}
264
265/// getScalarizedOpcode - Return the scalar opcode that corresponds to the
266/// specified vector opcode.
267static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
268  switch (VecOp) {
269  default: assert(0 && "Don't know how to scalarize this opcode!");
270  case ISD::VADD:  return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
271  case ISD::VSUB:  return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
272  case ISD::VMUL:  return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
273  case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
274  case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
275  case ISD::VAND:  return MVT::isInteger(VT) ? ISD::AND : 0;
276  case ISD::VOR:   return MVT::isInteger(VT) ? ISD::OR  : 0;
277  case ISD::VXOR:  return MVT::isInteger(VT) ? ISD::XOR : 0;
278  }
279}
280
281SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
282  : TLI(dag.getTargetLoweringInfo()), DAG(dag),
283    ValueTypeActions(TLI.getValueTypeActions()) {
284  assert(MVT::LAST_VALUETYPE <= 32 &&
285         "Too many value types for ValueTypeActions to hold!");
286}
287
288/// ComputeTopDownOrdering - Add the specified node to the Order list if it has
289/// not been visited yet and if all of its operands have already been visited.
290static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
291                                   std::map<SDNode*, unsigned> &Visited) {
292  if (++Visited[N] != N->getNumOperands())
293    return;  // Haven't visited all operands yet
294
295  Order.push_back(N);
296
297  if (N->hasOneUse()) { // Tail recurse in common case.
298    ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
299    return;
300  }
301
302  // Now that we have N in, add anything that uses it if all of their operands
303  // are now done.
304  for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
305    ComputeTopDownOrdering(*UI, Order, Visited);
306}
307
308
309void SelectionDAGLegalize::LegalizeDAG() {
310  LastCALLSEQ_END = DAG.getEntryNode();
311  IsLegalizingCall = false;
312
313  // The legalize process is inherently a bottom-up recursive process (users
314  // legalize their uses before themselves).  Given infinite stack space, we
315  // could just start legalizing on the root and traverse the whole graph.  In
316  // practice however, this causes us to run out of stack space on large basic
317  // blocks.  To avoid this problem, compute an ordering of the nodes where each
318  // node is only legalized after all of its operands are legalized.
319  std::map<SDNode*, unsigned> Visited;
320  std::vector<SDNode*> Order;
321
322  // Compute ordering from all of the leaves in the graphs, those (like the
323  // entry node) that have no operands.
324  for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
325       E = DAG.allnodes_end(); I != E; ++I) {
326    if (I->getNumOperands() == 0) {
327      Visited[I] = 0 - 1U;
328      ComputeTopDownOrdering(I, Order, Visited);
329    }
330  }
331
332  assert(Order.size() == Visited.size() &&
333         Order.size() ==
334            (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
335         "Error: DAG is cyclic!");
336  Visited.clear();
337
338  for (unsigned i = 0, e = Order.size(); i != e; ++i)
339    HandleOp(SDOperand(Order[i], 0));
340
341  // Finally, it's possible the root changed.  Get the new root.
342  SDOperand OldRoot = DAG.getRoot();
343  assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
344  DAG.setRoot(LegalizedNodes[OldRoot]);
345
346  ExpandedNodes.clear();
347  LegalizedNodes.clear();
348  PromotedNodes.clear();
349  SplitNodes.clear();
350  PackedNodes.clear();
351
352  // Remove dead nodes now.
353  DAG.RemoveDeadNodes();
354}
355
356
357/// FindCallEndFromCallStart - Given a chained node that is part of a call
358/// sequence, find the CALLSEQ_END node that terminates the call sequence.
359static SDNode *FindCallEndFromCallStart(SDNode *Node) {
360  if (Node->getOpcode() == ISD::CALLSEQ_END)
361    return Node;
362  if (Node->use_empty())
363    return 0;   // No CallSeqEnd
364
365  // The chain is usually at the end.
366  SDOperand TheChain(Node, Node->getNumValues()-1);
367  if (TheChain.getValueType() != MVT::Other) {
368    // Sometimes it's at the beginning.
369    TheChain = SDOperand(Node, 0);
370    if (TheChain.getValueType() != MVT::Other) {
371      // Otherwise, hunt for it.
372      for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
373        if (Node->getValueType(i) == MVT::Other) {
374          TheChain = SDOperand(Node, i);
375          break;
376        }
377
378      // Otherwise, we walked into a node without a chain.
379      if (TheChain.getValueType() != MVT::Other)
380        return 0;
381    }
382  }
383
384  for (SDNode::use_iterator UI = Node->use_begin(),
385       E = Node->use_end(); UI != E; ++UI) {
386
387    // Make sure to only follow users of our token chain.
388    SDNode *User = *UI;
389    for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
390      if (User->getOperand(i) == TheChain)
391        if (SDNode *Result = FindCallEndFromCallStart(User))
392          return Result;
393  }
394  return 0;
395}
396
397/// FindCallStartFromCallEnd - Given a chained node that is part of a call
398/// sequence, find the CALLSEQ_START node that initiates the call sequence.
399static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
400  assert(Node && "Didn't find callseq_start for a call??");
401  if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
402
403  assert(Node->getOperand(0).getValueType() == MVT::Other &&
404         "Node doesn't have a token chain argument!");
405  return FindCallStartFromCallEnd(Node->getOperand(0).Val);
406}
407
408/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
409/// see if any uses can reach Dest.  If no dest operands can get to dest,
410/// legalize them, legalize ourself, and return false, otherwise, return true.
411///
412/// Keep track of the nodes we fine that actually do lead to Dest in
413/// NodesLeadingTo.  This avoids retraversing them exponential number of times.
414///
415bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
416                                            std::set<SDNode*> &NodesLeadingTo) {
417  if (N == Dest) return true;  // N certainly leads to Dest :)
418
419  // If we've already processed this node and it does lead to Dest, there is no
420  // need to reprocess it.
421  if (NodesLeadingTo.count(N)) return true;
422
423  // If the first result of this node has been already legalized, then it cannot
424  // reach N.
425  switch (getTypeAction(N->getValueType(0))) {
426  case Legal:
427    if (LegalizedNodes.count(SDOperand(N, 0))) return false;
428    break;
429  case Promote:
430    if (PromotedNodes.count(SDOperand(N, 0))) return false;
431    break;
432  case Expand:
433    if (ExpandedNodes.count(SDOperand(N, 0))) return false;
434    break;
435  }
436
437  // Okay, this node has not already been legalized.  Check and legalize all
438  // operands.  If none lead to Dest, then we can legalize this node.
439  bool OperandsLeadToDest = false;
440  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
441    OperandsLeadToDest |=     // If an operand leads to Dest, so do we.
442      LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
443
444  if (OperandsLeadToDest) {
445    NodesLeadingTo.insert(N);
446    return true;
447  }
448
449  // Okay, this node looks safe, legalize it and return false.
450  HandleOp(SDOperand(N, 0));
451  return false;
452}
453
454/// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
455/// appropriate for its type.
456void SelectionDAGLegalize::HandleOp(SDOperand Op) {
457  switch (getTypeAction(Op.getValueType())) {
458  default: assert(0 && "Bad type action!");
459  case Legal:   LegalizeOp(Op); break;
460  case Promote: PromoteOp(Op);  break;
461  case Expand:
462    if (Op.getValueType() != MVT::Vector) {
463      SDOperand X, Y;
464      ExpandOp(Op, X, Y);
465    } else {
466      SDNode *N = Op.Val;
467      unsigned NumOps = N->getNumOperands();
468      unsigned NumElements =
469        cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
470      MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
471      MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
472      if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
473        // In the common case, this is a legal vector type, convert it to the
474        // packed operation and type now.
475        PackVectorOp(Op, PackedVT);
476      } else if (NumElements == 1) {
477        // Otherwise, if this is a single element vector, convert it to a
478        // scalar operation.
479        PackVectorOp(Op, EVT);
480      } else {
481        // Otherwise, this is a multiple element vector that isn't supported.
482        // Split it in half and legalize both parts.
483        SDOperand X, Y;
484        SplitVectorOp(Op, X, Y);
485      }
486    }
487    break;
488  }
489}
490
491
492/// LegalizeOp - We know that the specified value has a legal type.
493/// Recursively ensure that the operands have legal types, then return the
494/// result.
495SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
496  assert(isTypeLegal(Op.getValueType()) &&
497         "Caller should expand or promote operands that are not legal!");
498  SDNode *Node = Op.Val;
499
500  // If this operation defines any values that cannot be represented in a
501  // register on this target, make sure to expand or promote them.
502  if (Node->getNumValues() > 1) {
503    for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
504      if (getTypeAction(Node->getValueType(i)) != Legal) {
505        HandleOp(Op.getValue(i));
506        assert(LegalizedNodes.count(Op) &&
507               "Handling didn't add legal operands!");
508        return LegalizedNodes[Op];
509      }
510  }
511
512  // Note that LegalizeOp may be reentered even from single-use nodes, which
513  // means that we always must cache transformed nodes.
514  std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
515  if (I != LegalizedNodes.end()) return I->second;
516
517  SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
518  SDOperand Result = Op;
519  bool isCustom = false;
520
521  switch (Node->getOpcode()) {
522  case ISD::FrameIndex:
523  case ISD::EntryToken:
524  case ISD::Register:
525  case ISD::BasicBlock:
526  case ISD::TargetFrameIndex:
527  case ISD::TargetJumpTable:
528  case ISD::TargetConstant:
529  case ISD::TargetConstantFP:
530  case ISD::TargetConstantPool:
531  case ISD::TargetGlobalAddress:
532  case ISD::TargetExternalSymbol:
533  case ISD::VALUETYPE:
534  case ISD::SRCVALUE:
535  case ISD::STRING:
536  case ISD::CONDCODE:
537    // Primitives must all be legal.
538    assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
539           "This must be legal!");
540    break;
541  default:
542    if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
543      // If this is a target node, legalize it by legalizing the operands then
544      // passing it through.
545      SmallVector<SDOperand, 8> Ops;
546      for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
547        Ops.push_back(LegalizeOp(Node->getOperand(i)));
548
549      Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
550
551      for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
552        AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
553      return Result.getValue(Op.ResNo);
554    }
555    // Otherwise this is an unhandled builtin node.  splat.
556#ifndef NDEBUG
557    std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
558#endif
559    assert(0 && "Do not know how to legalize this operator!");
560    abort();
561  case ISD::GlobalAddress:
562  case ISD::ExternalSymbol:
563  case ISD::ConstantPool:
564  case ISD::JumpTable: // Nothing to do.
565    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
566    default: assert(0 && "This action is not supported yet!");
567    case TargetLowering::Custom:
568      Tmp1 = TLI.LowerOperation(Op, DAG);
569      if (Tmp1.Val) Result = Tmp1;
570      // FALLTHROUGH if the target doesn't want to lower this op after all.
571    case TargetLowering::Legal:
572      break;
573    }
574    break;
575  case ISD::AssertSext:
576  case ISD::AssertZext:
577    Tmp1 = LegalizeOp(Node->getOperand(0));
578    Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
579    break;
580  case ISD::MERGE_VALUES:
581    // Legalize eliminates MERGE_VALUES nodes.
582    Result = Node->getOperand(Op.ResNo);
583    break;
584  case ISD::CopyFromReg:
585    Tmp1 = LegalizeOp(Node->getOperand(0));
586    Result = Op.getValue(0);
587    if (Node->getNumValues() == 2) {
588      Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
589    } else {
590      assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
591      if (Node->getNumOperands() == 3) {
592        Tmp2 = LegalizeOp(Node->getOperand(2));
593        Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
594      } else {
595        Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
596      }
597      AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
598    }
599    // Since CopyFromReg produces two values, make sure to remember that we
600    // legalized both of them.
601    AddLegalizedOperand(Op.getValue(0), Result);
602    AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
603    return Result.getValue(Op.ResNo);
604  case ISD::UNDEF: {
605    MVT::ValueType VT = Op.getValueType();
606    switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
607    default: assert(0 && "This action is not supported yet!");
608    case TargetLowering::Expand:
609      if (MVT::isInteger(VT))
610        Result = DAG.getConstant(0, VT);
611      else if (MVT::isFloatingPoint(VT))
612        Result = DAG.getConstantFP(0, VT);
613      else
614        assert(0 && "Unknown value type!");
615      break;
616    case TargetLowering::Legal:
617      break;
618    }
619    break;
620  }
621
622  case ISD::INTRINSIC_W_CHAIN:
623  case ISD::INTRINSIC_WO_CHAIN:
624  case ISD::INTRINSIC_VOID: {
625    SmallVector<SDOperand, 8> Ops;
626    for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
627      Ops.push_back(LegalizeOp(Node->getOperand(i)));
628    Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
629
630    // Allow the target to custom lower its intrinsics if it wants to.
631    if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
632        TargetLowering::Custom) {
633      Tmp3 = TLI.LowerOperation(Result, DAG);
634      if (Tmp3.Val) Result = Tmp3;
635    }
636
637    if (Result.Val->getNumValues() == 1) break;
638
639    // Must have return value and chain result.
640    assert(Result.Val->getNumValues() == 2 &&
641           "Cannot return more than two values!");
642
643    // Since loads produce two values, make sure to remember that we
644    // legalized both of them.
645    AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
646    AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
647    return Result.getValue(Op.ResNo);
648  }
649
650  case ISD::LOCATION:
651    assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
652    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the input chain.
653
654    switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
655    case TargetLowering::Promote:
656    default: assert(0 && "This action is not supported yet!");
657    case TargetLowering::Expand: {
658      MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
659      bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
660      bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
661
662      if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
663        const std::string &FName =
664          cast<StringSDNode>(Node->getOperand(3))->getValue();
665        const std::string &DirName =
666          cast<StringSDNode>(Node->getOperand(4))->getValue();
667        unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
668
669        SmallVector<SDOperand, 8> Ops;
670        Ops.push_back(Tmp1);  // chain
671        SDOperand LineOp = Node->getOperand(1);
672        SDOperand ColOp = Node->getOperand(2);
673
674        if (useDEBUG_LOC) {
675          Ops.push_back(LineOp);  // line #
676          Ops.push_back(ColOp);  // col #
677          Ops.push_back(DAG.getConstant(SrcFile, MVT::i32));  // source file id
678          Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
679        } else {
680          unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
681          unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
682          unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
683          Ops.push_back(DAG.getConstant(ID, MVT::i32));
684          Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
685        }
686      } else {
687        Result = Tmp1;  // chain
688      }
689      break;
690    }
691    case TargetLowering::Legal:
692      if (Tmp1 != Node->getOperand(0) ||
693          getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
694        SmallVector<SDOperand, 8> Ops;
695        Ops.push_back(Tmp1);
696        if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
697          Ops.push_back(Node->getOperand(1));  // line # must be legal.
698          Ops.push_back(Node->getOperand(2));  // col # must be legal.
699        } else {
700          // Otherwise promote them.
701          Ops.push_back(PromoteOp(Node->getOperand(1)));
702          Ops.push_back(PromoteOp(Node->getOperand(2)));
703        }
704        Ops.push_back(Node->getOperand(3));  // filename must be legal.
705        Ops.push_back(Node->getOperand(4));  // working dir # must be legal.
706        Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
707      }
708      break;
709    }
710    break;
711
712  case ISD::DEBUG_LOC:
713    assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
714    switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
715    default: assert(0 && "This action is not supported yet!");
716    case TargetLowering::Legal:
717      Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
718      Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the line #.
719      Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the col #.
720      Tmp4 = LegalizeOp(Node->getOperand(3));  // Legalize the source file id.
721      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
722      break;
723    }
724    break;
725
726  case ISD::DEBUG_LABEL:
727    assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
728    switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
729    default: assert(0 && "This action is not supported yet!");
730    case TargetLowering::Legal:
731      Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
732      Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the label id.
733      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
734      break;
735    }
736    break;
737
738  case ISD::Constant:
739    // We know we don't need to expand constants here, constants only have one
740    // value and we check that it is fine above.
741
742    // FIXME: Maybe we should handle things like targets that don't support full
743    // 32-bit immediates?
744    break;
745  case ISD::ConstantFP: {
746    // Spill FP immediates to the constant pool if the target cannot directly
747    // codegen them.  Targets often have some immediate values that can be
748    // efficiently generated into an FP register without a load.  We explicitly
749    // leave these constants as ConstantFP nodes for the target to deal with.
750    ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
751
752    // Check to see if this FP immediate is already legal.
753    bool isLegal = false;
754    for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
755           E = TLI.legal_fpimm_end(); I != E; ++I)
756      if (CFP->isExactlyValue(*I)) {
757        isLegal = true;
758        break;
759      }
760
761    // If this is a legal constant, turn it into a TargetConstantFP node.
762    if (isLegal) {
763      Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
764      break;
765    }
766
767    switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
768    default: assert(0 && "This action is not supported yet!");
769    case TargetLowering::Custom:
770      Tmp3 = TLI.LowerOperation(Result, DAG);
771      if (Tmp3.Val) {
772        Result = Tmp3;
773        break;
774      }
775      // FALLTHROUGH
776    case TargetLowering::Expand:
777      // Otherwise we need to spill the constant to memory.
778      bool Extend = false;
779
780      // If a FP immediate is precise when represented as a float and if the
781      // target can do an extending load from float to double, we put it into
782      // the constant pool as a float, even if it's is statically typed as a
783      // double.
784      MVT::ValueType VT = CFP->getValueType(0);
785      bool isDouble = VT == MVT::f64;
786      ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
787                                             Type::FloatTy, CFP->getValue());
788      if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
789          // Only do this if the target has a native EXTLOAD instruction from
790          // f32.
791          TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
792        LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
793        VT = MVT::f32;
794        Extend = true;
795      }
796
797      SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
798      if (Extend) {
799        Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
800                                CPIdx, DAG.getSrcValue(NULL), MVT::f32);
801      } else {
802        Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
803                             DAG.getSrcValue(NULL));
804      }
805    }
806    break;
807  }
808  case ISD::TokenFactor:
809    if (Node->getNumOperands() == 2) {
810      Tmp1 = LegalizeOp(Node->getOperand(0));
811      Tmp2 = LegalizeOp(Node->getOperand(1));
812      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
813    } else if (Node->getNumOperands() == 3) {
814      Tmp1 = LegalizeOp(Node->getOperand(0));
815      Tmp2 = LegalizeOp(Node->getOperand(1));
816      Tmp3 = LegalizeOp(Node->getOperand(2));
817      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
818    } else {
819      SmallVector<SDOperand, 8> Ops;
820      // Legalize the operands.
821      for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
822        Ops.push_back(LegalizeOp(Node->getOperand(i)));
823      Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
824    }
825    break;
826
827  case ISD::FORMAL_ARGUMENTS:
828  case ISD::CALL:
829    // The only option for this is to custom lower it.
830    Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
831    assert(Tmp3.Val && "Target didn't custom lower this node!");
832    assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
833           "Lowering call/formal_arguments produced unexpected # results!");
834
835    // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
836    // remember that we legalized all of them, so it doesn't get relegalized.
837    for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
838      Tmp1 = LegalizeOp(Tmp3.getValue(i));
839      if (Op.ResNo == i)
840        Tmp2 = Tmp1;
841      AddLegalizedOperand(SDOperand(Node, i), Tmp1);
842    }
843    return Tmp2;
844
845  case ISD::BUILD_VECTOR:
846    switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
847    default: assert(0 && "This action is not supported yet!");
848    case TargetLowering::Custom:
849      Tmp3 = TLI.LowerOperation(Result, DAG);
850      if (Tmp3.Val) {
851        Result = Tmp3;
852        break;
853      }
854      // FALLTHROUGH
855    case TargetLowering::Expand:
856      Result = ExpandBUILD_VECTOR(Result.Val);
857      break;
858    }
859    break;
860  case ISD::INSERT_VECTOR_ELT:
861    Tmp1 = LegalizeOp(Node->getOperand(0));  // InVec
862    Tmp2 = LegalizeOp(Node->getOperand(1));  // InVal
863    Tmp3 = LegalizeOp(Node->getOperand(2));  // InEltNo
864    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
865
866    switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
867                                   Node->getValueType(0))) {
868    default: assert(0 && "This action is not supported yet!");
869    case TargetLowering::Legal:
870      break;
871    case TargetLowering::Custom:
872      Tmp3 = TLI.LowerOperation(Result, DAG);
873      if (Tmp3.Val) {
874        Result = Tmp3;
875        break;
876      }
877      // FALLTHROUGH
878    case TargetLowering::Expand: {
879      // If the insert index is a constant, codegen this as a scalar_to_vector,
880      // then a shuffle that inserts it into the right position in the vector.
881      if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
882        SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
883                                      Tmp1.getValueType(), Tmp2);
884
885        unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
886        MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
887        MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
888
889        // We generate a shuffle of InVec and ScVec, so the shuffle mask should
890        // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
891        // the RHS.
892        SmallVector<SDOperand, 8> ShufOps;
893        for (unsigned i = 0; i != NumElts; ++i) {
894          if (i != InsertPos->getValue())
895            ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
896          else
897            ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
898        }
899        SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
900                                         &ShufOps[0], ShufOps.size());
901
902        Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
903                             Tmp1, ScVec, ShufMask);
904        Result = LegalizeOp(Result);
905        break;
906      }
907
908      // If the target doesn't support this, we have to spill the input vector
909      // to a temporary stack slot, update the element, then reload it.  This is
910      // badness.  We could also load the value into a vector register (either
911      // with a "move to register" or "extload into register" instruction, then
912      // permute it into place, if the idx is a constant and if the idx is
913      // supported by the target.
914      MVT::ValueType VT    = Tmp1.getValueType();
915      MVT::ValueType EltVT = Tmp2.getValueType();
916      MVT::ValueType IdxVT = Tmp3.getValueType();
917      MVT::ValueType PtrVT = TLI.getPointerTy();
918      SDOperand StackPtr = CreateStackTemporary(VT);
919      // Store the vector.
920      SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
921                                 Tmp1, StackPtr, DAG.getSrcValue(NULL));
922
923      // Truncate or zero extend offset to target pointer type.
924      unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
925      Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
926      // Add the offset to the index.
927      unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
928      Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
929      SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
930      // Store the scalar value.
931      Ch = DAG.getNode(ISD::STORE, MVT::Other, Ch,
932                       Tmp2, StackPtr2, DAG.getSrcValue(NULL));
933      // Load the updated vector.
934      Result = DAG.getLoad(VT, Ch, StackPtr, DAG.getSrcValue(NULL));
935      break;
936    }
937    }
938    break;
939  case ISD::SCALAR_TO_VECTOR:
940    if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
941      Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
942      break;
943    }
944
945    Tmp1 = LegalizeOp(Node->getOperand(0));  // InVal
946    Result = DAG.UpdateNodeOperands(Result, Tmp1);
947    switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
948                                   Node->getValueType(0))) {
949    default: assert(0 && "This action is not supported yet!");
950    case TargetLowering::Legal:
951      break;
952    case TargetLowering::Custom:
953      Tmp3 = TLI.LowerOperation(Result, DAG);
954      if (Tmp3.Val) {
955        Result = Tmp3;
956        break;
957      }
958      // FALLTHROUGH
959    case TargetLowering::Expand:
960      Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
961      break;
962    }
963    break;
964  case ISD::VECTOR_SHUFFLE:
965    Tmp1 = LegalizeOp(Node->getOperand(0));   // Legalize the input vectors,
966    Tmp2 = LegalizeOp(Node->getOperand(1));   // but not the shuffle mask.
967    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
968
969    // Allow targets to custom lower the SHUFFLEs they support.
970    switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
971    default: assert(0 && "Unknown operation action!");
972    case TargetLowering::Legal:
973      assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
974             "vector shuffle should not be created if not legal!");
975      break;
976    case TargetLowering::Custom:
977      Tmp3 = TLI.LowerOperation(Result, DAG);
978      if (Tmp3.Val) {
979        Result = Tmp3;
980        break;
981      }
982      // FALLTHROUGH
983    case TargetLowering::Expand: {
984      MVT::ValueType VT = Node->getValueType(0);
985      MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
986      MVT::ValueType PtrVT = TLI.getPointerTy();
987      SDOperand Mask = Node->getOperand(2);
988      unsigned NumElems = Mask.getNumOperands();
989      SmallVector<SDOperand,8> Ops;
990      for (unsigned i = 0; i != NumElems; ++i) {
991        SDOperand Arg = Mask.getOperand(i);
992        if (Arg.getOpcode() == ISD::UNDEF) {
993          Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
994        } else {
995          assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
996          unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
997          if (Idx < NumElems)
998            Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
999                                      DAG.getConstant(Idx, PtrVT)));
1000          else
1001            Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1002                                      DAG.getConstant(Idx - NumElems, PtrVT)));
1003        }
1004      }
1005      Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1006      break;
1007    }
1008    case TargetLowering::Promote: {
1009      // Change base type to a different vector type.
1010      MVT::ValueType OVT = Node->getValueType(0);
1011      MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1012
1013      // Cast the two input vectors.
1014      Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1015      Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1016
1017      // Convert the shuffle mask to the right # elements.
1018      Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1019      assert(Tmp3.Val && "Shuffle not legal?");
1020      Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1021      Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1022      break;
1023    }
1024    }
1025    break;
1026
1027  case ISD::EXTRACT_VECTOR_ELT:
1028    Tmp1 = LegalizeOp(Node->getOperand(0));
1029    Tmp2 = LegalizeOp(Node->getOperand(1));
1030    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1031
1032    switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1033                                   Tmp1.getValueType())) {
1034    default: assert(0 && "This action is not supported yet!");
1035    case TargetLowering::Legal:
1036      break;
1037    case TargetLowering::Custom:
1038      Tmp3 = TLI.LowerOperation(Result, DAG);
1039      if (Tmp3.Val) {
1040        Result = Tmp3;
1041        break;
1042      }
1043      // FALLTHROUGH
1044    case TargetLowering::Expand:
1045      Result = ExpandEXTRACT_VECTOR_ELT(Result);
1046      break;
1047    }
1048    break;
1049
1050  case ISD::VEXTRACT_VECTOR_ELT:
1051    Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1052    break;
1053
1054  case ISD::CALLSEQ_START: {
1055    SDNode *CallEnd = FindCallEndFromCallStart(Node);
1056
1057    // Recursively Legalize all of the inputs of the call end that do not lead
1058    // to this call start.  This ensures that any libcalls that need be inserted
1059    // are inserted *before* the CALLSEQ_START.
1060    {std::set<SDNode*> NodesLeadingTo;
1061    for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1062      LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1063                                   NodesLeadingTo);
1064    }
1065
1066    // Now that we legalized all of the inputs (which may have inserted
1067    // libcalls) create the new CALLSEQ_START node.
1068    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1069
1070    // Merge in the last call, to ensure that this call start after the last
1071    // call ended.
1072    if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1073      Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1074      Tmp1 = LegalizeOp(Tmp1);
1075    }
1076
1077    // Do not try to legalize the target-specific arguments (#1+).
1078    if (Tmp1 != Node->getOperand(0)) {
1079      SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1080      Ops[0] = Tmp1;
1081      Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1082    }
1083
1084    // Remember that the CALLSEQ_START is legalized.
1085    AddLegalizedOperand(Op.getValue(0), Result);
1086    if (Node->getNumValues() == 2)    // If this has a flag result, remember it.
1087      AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1088
1089    // Now that the callseq_start and all of the non-call nodes above this call
1090    // sequence have been legalized, legalize the call itself.  During this
1091    // process, no libcalls can/will be inserted, guaranteeing that no calls
1092    // can overlap.
1093    assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1094    SDOperand InCallSEQ = LastCALLSEQ_END;
1095    // Note that we are selecting this call!
1096    LastCALLSEQ_END = SDOperand(CallEnd, 0);
1097    IsLegalizingCall = true;
1098
1099    // Legalize the call, starting from the CALLSEQ_END.
1100    LegalizeOp(LastCALLSEQ_END);
1101    assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1102    return Result;
1103  }
1104  case ISD::CALLSEQ_END:
1105    // If the CALLSEQ_START node hasn't been legalized first, legalize it.  This
1106    // will cause this node to be legalized as well as handling libcalls right.
1107    if (LastCALLSEQ_END.Val != Node) {
1108      LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1109      std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1110      assert(I != LegalizedNodes.end() &&
1111             "Legalizing the call start should have legalized this node!");
1112      return I->second;
1113    }
1114
1115    // Otherwise, the call start has been legalized and everything is going
1116    // according to plan.  Just legalize ourselves normally here.
1117    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1118    // Do not try to legalize the target-specific arguments (#1+), except for
1119    // an optional flag input.
1120    if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1121      if (Tmp1 != Node->getOperand(0)) {
1122        SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1123        Ops[0] = Tmp1;
1124        Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1125      }
1126    } else {
1127      Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1128      if (Tmp1 != Node->getOperand(0) ||
1129          Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1130        SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1131        Ops[0] = Tmp1;
1132        Ops.back() = Tmp2;
1133        Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1134      }
1135    }
1136    assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1137    // This finishes up call legalization.
1138    IsLegalizingCall = false;
1139
1140    // If the CALLSEQ_END node has a flag, remember that we legalized it.
1141    AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1142    if (Node->getNumValues() == 2)
1143      AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1144    return Result.getValue(Op.ResNo);
1145  case ISD::DYNAMIC_STACKALLOC: {
1146    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1147    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the size.
1148    Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the alignment.
1149    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1150
1151    Tmp1 = Result.getValue(0);
1152    Tmp2 = Result.getValue(1);
1153    switch (TLI.getOperationAction(Node->getOpcode(),
1154                                   Node->getValueType(0))) {
1155    default: assert(0 && "This action is not supported yet!");
1156    case TargetLowering::Expand: {
1157      unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1158      assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1159             " not tell us which reg is the stack pointer!");
1160      SDOperand Chain = Tmp1.getOperand(0);
1161      SDOperand Size  = Tmp2.getOperand(1);
1162      SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1163      Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size);    // Value
1164      Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1);      // Output chain
1165      Tmp1 = LegalizeOp(Tmp1);
1166      Tmp2 = LegalizeOp(Tmp2);
1167      break;
1168    }
1169    case TargetLowering::Custom:
1170      Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1171      if (Tmp3.Val) {
1172        Tmp1 = LegalizeOp(Tmp3);
1173        Tmp2 = LegalizeOp(Tmp3.getValue(1));
1174      }
1175      break;
1176    case TargetLowering::Legal:
1177      break;
1178    }
1179    // Since this op produce two values, make sure to remember that we
1180    // legalized both of them.
1181    AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1182    AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1183    return Op.ResNo ? Tmp2 : Tmp1;
1184  }
1185  case ISD::INLINEASM: {
1186    SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1187    bool Changed = false;
1188    // Legalize all of the operands of the inline asm, in case they are nodes
1189    // that need to be expanded or something.  Note we skip the asm string and
1190    // all of the TargetConstant flags.
1191    SDOperand Op = LegalizeOp(Ops[0]);
1192    Changed = Op != Ops[0];
1193    Ops[0] = Op;
1194
1195    bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1196    for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1197      unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1198      for (++i; NumVals; ++i, --NumVals) {
1199        SDOperand Op = LegalizeOp(Ops[i]);
1200        if (Op != Ops[i]) {
1201          Changed = true;
1202          Ops[i] = Op;
1203        }
1204      }
1205    }
1206
1207    if (HasInFlag) {
1208      Op = LegalizeOp(Ops.back());
1209      Changed |= Op != Ops.back();
1210      Ops.back() = Op;
1211    }
1212
1213    if (Changed)
1214      Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1215
1216    // INLINE asm returns a chain and flag, make sure to add both to the map.
1217    AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1218    AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1219    return Result.getValue(Op.ResNo);
1220  }
1221  case ISD::BR:
1222    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1223    // Ensure that libcalls are emitted before a branch.
1224    Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1225    Tmp1 = LegalizeOp(Tmp1);
1226    LastCALLSEQ_END = DAG.getEntryNode();
1227
1228    Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1229    break;
1230  case ISD::BRIND:
1231    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1232    // Ensure that libcalls are emitted before a branch.
1233    Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1234    Tmp1 = LegalizeOp(Tmp1);
1235    LastCALLSEQ_END = DAG.getEntryNode();
1236
1237    switch (getTypeAction(Node->getOperand(1).getValueType())) {
1238    default: assert(0 && "Indirect target must be legal type (pointer)!");
1239    case Legal:
1240      Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1241      break;
1242    }
1243    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1244    break;
1245  case ISD::BRCOND:
1246    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1247    // Ensure that libcalls are emitted before a return.
1248    Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1249    Tmp1 = LegalizeOp(Tmp1);
1250    LastCALLSEQ_END = DAG.getEntryNode();
1251
1252    switch (getTypeAction(Node->getOperand(1).getValueType())) {
1253    case Expand: assert(0 && "It's impossible to expand bools");
1254    case Legal:
1255      Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1256      break;
1257    case Promote:
1258      Tmp2 = PromoteOp(Node->getOperand(1));  // Promote the condition.
1259      break;
1260    }
1261
1262    // Basic block destination (Op#2) is always legal.
1263    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1264
1265    switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1266    default: assert(0 && "This action is not supported yet!");
1267    case TargetLowering::Legal: break;
1268    case TargetLowering::Custom:
1269      Tmp1 = TLI.LowerOperation(Result, DAG);
1270      if (Tmp1.Val) Result = Tmp1;
1271      break;
1272    case TargetLowering::Expand:
1273      // Expand brcond's setcc into its constituent parts and create a BR_CC
1274      // Node.
1275      if (Tmp2.getOpcode() == ISD::SETCC) {
1276        Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1277                             Tmp2.getOperand(0), Tmp2.getOperand(1),
1278                             Node->getOperand(2));
1279      } else {
1280        // Make sure the condition is either zero or one.  It may have been
1281        // promoted from something else.
1282        unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
1283        if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
1284          Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1285
1286        Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1287                             DAG.getCondCode(ISD::SETNE), Tmp2,
1288                             DAG.getConstant(0, Tmp2.getValueType()),
1289                             Node->getOperand(2));
1290      }
1291      break;
1292    }
1293    break;
1294  case ISD::BR_CC:
1295    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1296    // Ensure that libcalls are emitted before a branch.
1297    Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1298    Tmp1 = LegalizeOp(Tmp1);
1299    LastCALLSEQ_END = DAG.getEntryNode();
1300
1301    Tmp2 = Node->getOperand(2);              // LHS
1302    Tmp3 = Node->getOperand(3);              // RHS
1303    Tmp4 = Node->getOperand(1);              // CC
1304
1305    LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1306
1307    // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1308    // the LHS is a legal SETCC itself.  In this case, we need to compare
1309    // the result against zero to select between true and false values.
1310    if (Tmp3.Val == 0) {
1311      Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1312      Tmp4 = DAG.getCondCode(ISD::SETNE);
1313    }
1314
1315    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1316                                    Node->getOperand(4));
1317
1318    switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1319    default: assert(0 && "Unexpected action for BR_CC!");
1320    case TargetLowering::Legal: break;
1321    case TargetLowering::Custom:
1322      Tmp4 = TLI.LowerOperation(Result, DAG);
1323      if (Tmp4.Val) Result = Tmp4;
1324      break;
1325    }
1326    break;
1327  case ISD::LOAD: {
1328    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1329    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
1330
1331    MVT::ValueType VT = Node->getValueType(0);
1332    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1333    Tmp3 = Result.getValue(0);
1334    Tmp4 = Result.getValue(1);
1335
1336    switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1337    default: assert(0 && "This action is not supported yet!");
1338    case TargetLowering::Legal: break;
1339    case TargetLowering::Custom:
1340      Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1341      if (Tmp1.Val) {
1342        Tmp3 = LegalizeOp(Tmp1);
1343        Tmp4 = LegalizeOp(Tmp1.getValue(1));
1344      }
1345      break;
1346    case TargetLowering::Promote: {
1347      // Only promote a load of vector type to another.
1348      assert(MVT::isVector(VT) && "Cannot promote this load!");
1349      // Change base type to a different vector type.
1350      MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1351
1352      Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, Node->getOperand(2));
1353      Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1354      Tmp4 = LegalizeOp(Tmp1.getValue(1));
1355      break;
1356    }
1357    }
1358    // Since loads produce two values, make sure to remember that we
1359    // legalized both of them.
1360    AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1361    AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1362    return Op.ResNo ? Tmp4 : Tmp3;
1363  }
1364  case ISD::EXTLOAD:
1365  case ISD::SEXTLOAD:
1366  case ISD::ZEXTLOAD: {
1367    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1368    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
1369
1370    MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1371    switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1372    default: assert(0 && "This action is not supported yet!");
1373    case TargetLowering::Promote:
1374      assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1375      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1376                                      DAG.getValueType(MVT::i8));
1377      Tmp1 = Result.getValue(0);
1378      Tmp2 = Result.getValue(1);
1379      break;
1380    case TargetLowering::Custom:
1381      isCustom = true;
1382      // FALLTHROUGH
1383    case TargetLowering::Legal:
1384      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1385                                      Node->getOperand(3));
1386      Tmp1 = Result.getValue(0);
1387      Tmp2 = Result.getValue(1);
1388
1389      if (isCustom) {
1390        Tmp3 = TLI.LowerOperation(Tmp3, DAG);
1391        if (Tmp3.Val) {
1392          Tmp1 = LegalizeOp(Tmp3);
1393          Tmp2 = LegalizeOp(Tmp3.getValue(1));
1394        }
1395      }
1396      break;
1397    case TargetLowering::Expand:
1398      // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1399      if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1400        SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1401        Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1402        Tmp1 = LegalizeOp(Result);  // Relegalize new nodes.
1403        Tmp2 = LegalizeOp(Load.getValue(1));
1404        break;
1405      }
1406      assert(Node->getOpcode() != ISD::EXTLOAD &&
1407             "EXTLOAD should always be supported!");
1408      // Turn the unsupported load into an EXTLOAD followed by an explicit
1409      // zero/sign extend inreg.
1410      Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1411                              Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1412      SDOperand ValRes;
1413      if (Node->getOpcode() == ISD::SEXTLOAD)
1414        ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1415                             Result, DAG.getValueType(SrcVT));
1416      else
1417        ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1418      Tmp1 = LegalizeOp(ValRes);  // Relegalize new nodes.
1419      Tmp2 = LegalizeOp(Result.getValue(1));  // Relegalize new nodes.
1420      break;
1421    }
1422    // Since loads produce two values, make sure to remember that we legalized
1423    // both of them.
1424    AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1425    AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1426    return Op.ResNo ? Tmp2 : Tmp1;
1427  }
1428  case ISD::EXTRACT_ELEMENT: {
1429    MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1430    switch (getTypeAction(OpTy)) {
1431    default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1432    case Legal:
1433      if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1434        // 1 -> Hi
1435        Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1436                             DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1437                                             TLI.getShiftAmountTy()));
1438        Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1439      } else {
1440        // 0 -> Lo
1441        Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1442                             Node->getOperand(0));
1443      }
1444      break;
1445    case Expand:
1446      // Get both the low and high parts.
1447      ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1448      if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1449        Result = Tmp2;  // 1 -> Hi
1450      else
1451        Result = Tmp1;  // 0 -> Lo
1452      break;
1453    }
1454    break;
1455  }
1456
1457  case ISD::CopyToReg:
1458    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1459
1460    assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1461           "Register type must be legal!");
1462    // Legalize the incoming value (must be a legal type).
1463    Tmp2 = LegalizeOp(Node->getOperand(2));
1464    if (Node->getNumValues() == 1) {
1465      Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1466    } else {
1467      assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1468      if (Node->getNumOperands() == 4) {
1469        Tmp3 = LegalizeOp(Node->getOperand(3));
1470        Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1471                                        Tmp3);
1472      } else {
1473        Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1474      }
1475
1476      // Since this produces two values, make sure to remember that we legalized
1477      // both of them.
1478      AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1479      AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1480      return Result;
1481    }
1482    break;
1483
1484  case ISD::RET:
1485    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1486
1487    // Ensure that libcalls are emitted before a return.
1488    Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1489    Tmp1 = LegalizeOp(Tmp1);
1490    LastCALLSEQ_END = DAG.getEntryNode();
1491
1492    switch (Node->getNumOperands()) {
1493    case 3:  // ret val
1494      Tmp2 = Node->getOperand(1);
1495      Tmp3 = Node->getOperand(2);  // Signness
1496      switch (getTypeAction(Tmp2.getValueType())) {
1497      case Legal:
1498        Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1499        break;
1500      case Expand:
1501        if (Tmp2.getValueType() != MVT::Vector) {
1502          SDOperand Lo, Hi;
1503          ExpandOp(Tmp2, Lo, Hi);
1504          Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1505        } else {
1506          SDNode *InVal = Tmp2.Val;
1507          unsigned NumElems =
1508            cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1509          MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1510
1511          // Figure out if there is a Packed type corresponding to this Vector
1512          // type.  If so, convert to the packed type.
1513          MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1514          if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1515            // Turn this into a return of the packed type.
1516            Tmp2 = PackVectorOp(Tmp2, TVT);
1517            Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1518          } else if (NumElems == 1) {
1519            // Turn this into a return of the scalar type.
1520            Tmp2 = PackVectorOp(Tmp2, EVT);
1521            Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1522
1523            // FIXME: Returns of gcc generic vectors smaller than a legal type
1524            // should be returned in integer registers!
1525
1526            // The scalarized value type may not be legal, e.g. it might require
1527            // promotion or expansion.  Relegalize the return.
1528            Result = LegalizeOp(Result);
1529          } else {
1530            // FIXME: Returns of gcc generic vectors larger than a legal vector
1531            // type should be returned by reference!
1532            SDOperand Lo, Hi;
1533            SplitVectorOp(Tmp2, Lo, Hi);
1534            Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1535            Result = LegalizeOp(Result);
1536          }
1537        }
1538        break;
1539      case Promote:
1540        Tmp2 = PromoteOp(Node->getOperand(1));
1541        Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1542        Result = LegalizeOp(Result);
1543        break;
1544      }
1545      break;
1546    case 1:  // ret void
1547      Result = DAG.UpdateNodeOperands(Result, Tmp1);
1548      break;
1549    default: { // ret <values>
1550      SmallVector<SDOperand, 8> NewValues;
1551      NewValues.push_back(Tmp1);
1552      for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1553        switch (getTypeAction(Node->getOperand(i).getValueType())) {
1554        case Legal:
1555          NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1556          NewValues.push_back(Node->getOperand(i+1));
1557          break;
1558        case Expand: {
1559          SDOperand Lo, Hi;
1560          assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1561                 "FIXME: TODO: implement returning non-legal vector types!");
1562          ExpandOp(Node->getOperand(i), Lo, Hi);
1563          NewValues.push_back(Lo);
1564          NewValues.push_back(Node->getOperand(i+1));
1565          NewValues.push_back(Hi);
1566          NewValues.push_back(Node->getOperand(i+1));
1567          break;
1568        }
1569        case Promote:
1570          assert(0 && "Can't promote multiple return value yet!");
1571        }
1572
1573      if (NewValues.size() == Node->getNumOperands())
1574        Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1575      else
1576        Result = DAG.getNode(ISD::RET, MVT::Other,
1577                             &NewValues[0], NewValues.size());
1578      break;
1579    }
1580    }
1581
1582    if (Result.getOpcode() == ISD::RET) {
1583      switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1584      default: assert(0 && "This action is not supported yet!");
1585      case TargetLowering::Legal: break;
1586      case TargetLowering::Custom:
1587        Tmp1 = TLI.LowerOperation(Result, DAG);
1588        if (Tmp1.Val) Result = Tmp1;
1589        break;
1590      }
1591    }
1592    break;
1593  case ISD::STORE: {
1594    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1595    Tmp2 = LegalizeOp(Node->getOperand(2));  // Legalize the pointer.
1596
1597    // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1598    // FIXME: We shouldn't do this for TargetConstantFP's.
1599    // FIXME: move this to the DAG Combiner!
1600    if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1601      if (CFP->getValueType(0) == MVT::f32) {
1602        Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1603      } else {
1604        assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1605        Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1606      }
1607      Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1608                           Node->getOperand(3));
1609      break;
1610    }
1611
1612    switch (getTypeAction(Node->getOperand(1).getValueType())) {
1613    case Legal: {
1614      Tmp3 = LegalizeOp(Node->getOperand(1));
1615      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1616                                      Node->getOperand(3));
1617
1618      MVT::ValueType VT = Tmp3.getValueType();
1619      switch (TLI.getOperationAction(ISD::STORE, VT)) {
1620      default: assert(0 && "This action is not supported yet!");
1621      case TargetLowering::Legal:  break;
1622      case TargetLowering::Custom:
1623        Tmp1 = TLI.LowerOperation(Result, DAG);
1624        if (Tmp1.Val) Result = Tmp1;
1625        break;
1626      case TargetLowering::Promote:
1627        assert(MVT::isVector(VT) && "Unknown legal promote case!");
1628        Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1629                           TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1630        Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1631                                        Node->getOperand(3));
1632        break;
1633      }
1634      break;
1635    }
1636    case Promote:
1637      // Truncate the value and store the result.
1638      Tmp3 = PromoteOp(Node->getOperand(1));
1639      Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1640                           Node->getOperand(3),
1641                          DAG.getValueType(Node->getOperand(1).getValueType()));
1642      break;
1643
1644    case Expand:
1645      unsigned IncrementSize = 0;
1646      SDOperand Lo, Hi;
1647
1648      // If this is a vector type, then we have to calculate the increment as
1649      // the product of the element size in bytes, and the number of elements
1650      // in the high half of the vector.
1651      if (Node->getOperand(1).getValueType() == MVT::Vector) {
1652        SDNode *InVal = Node->getOperand(1).Val;
1653        unsigned NumElems =
1654          cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1655        MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1656
1657        // Figure out if there is a Packed type corresponding to this Vector
1658        // type.  If so, convert to the packed type.
1659        MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1660        if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1661          // Turn this into a normal store of the packed type.
1662          Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1663          Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1664                                          Node->getOperand(3));
1665          Result = LegalizeOp(Result);
1666          break;
1667        } else if (NumElems == 1) {
1668          // Turn this into a normal store of the scalar type.
1669          Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1670          Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1671                                          Node->getOperand(3));
1672          // The scalarized value type may not be legal, e.g. it might require
1673          // promotion or expansion.  Relegalize the scalar store.
1674          Result = LegalizeOp(Result);
1675          break;
1676        } else {
1677          SplitVectorOp(Node->getOperand(1), Lo, Hi);
1678          IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1679        }
1680      } else {
1681        ExpandOp(Node->getOperand(1), Lo, Hi);
1682        IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1683
1684        if (!TLI.isLittleEndian())
1685          std::swap(Lo, Hi);
1686      }
1687
1688      Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1689                       Node->getOperand(3));
1690      Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1691                         getIntPtrConstant(IncrementSize));
1692      assert(isTypeLegal(Tmp2.getValueType()) &&
1693             "Pointers must be legal!");
1694      // FIXME: This sets the srcvalue of both halves to be the same, which is
1695      // wrong.
1696      Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1697                       Node->getOperand(3));
1698      Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1699      break;
1700    }
1701    break;
1702  }
1703  case ISD::PCMARKER:
1704    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1705    Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1706    break;
1707  case ISD::STACKSAVE:
1708    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1709    Result = DAG.UpdateNodeOperands(Result, Tmp1);
1710    Tmp1 = Result.getValue(0);
1711    Tmp2 = Result.getValue(1);
1712
1713    switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1714    default: assert(0 && "This action is not supported yet!");
1715    case TargetLowering::Legal: break;
1716    case TargetLowering::Custom:
1717      Tmp3 = TLI.LowerOperation(Result, DAG);
1718      if (Tmp3.Val) {
1719        Tmp1 = LegalizeOp(Tmp3);
1720        Tmp2 = LegalizeOp(Tmp3.getValue(1));
1721      }
1722      break;
1723    case TargetLowering::Expand:
1724      // Expand to CopyFromReg if the target set
1725      // StackPointerRegisterToSaveRestore.
1726      if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1727        Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1728                                  Node->getValueType(0));
1729        Tmp2 = Tmp1.getValue(1);
1730      } else {
1731        Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1732        Tmp2 = Node->getOperand(0);
1733      }
1734      break;
1735    }
1736
1737    // Since stacksave produce two values, make sure to remember that we
1738    // legalized both of them.
1739    AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1740    AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1741    return Op.ResNo ? Tmp2 : Tmp1;
1742
1743  case ISD::STACKRESTORE:
1744    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1745    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
1746    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1747
1748    switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1749    default: assert(0 && "This action is not supported yet!");
1750    case TargetLowering::Legal: break;
1751    case TargetLowering::Custom:
1752      Tmp1 = TLI.LowerOperation(Result, DAG);
1753      if (Tmp1.Val) Result = Tmp1;
1754      break;
1755    case TargetLowering::Expand:
1756      // Expand to CopyToReg if the target set
1757      // StackPointerRegisterToSaveRestore.
1758      if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1759        Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1760      } else {
1761        Result = Tmp1;
1762      }
1763      break;
1764    }
1765    break;
1766
1767  case ISD::READCYCLECOUNTER:
1768    Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1769    Result = DAG.UpdateNodeOperands(Result, Tmp1);
1770
1771    // Since rdcc produce two values, make sure to remember that we legalized
1772    // both of them.
1773    AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1774    AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1775    return Result;
1776
1777  case ISD::TRUNCSTORE: {
1778    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
1779    Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the pointer.
1780
1781    assert(isTypeLegal(Node->getOperand(1).getValueType()) &&
1782           "Cannot handle illegal TRUNCSTORE yet!");
1783    Tmp2 = LegalizeOp(Node->getOperand(1));
1784
1785    // The only promote case we handle is TRUNCSTORE:i1 X into
1786    //   -> TRUNCSTORE:i8 (and X, 1)
1787    if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1788        TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1789              TargetLowering::Promote) {
1790      // Promote the bool to a mask then store.
1791      Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1792                         DAG.getConstant(1, Tmp2.getValueType()));
1793      Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1794                           Node->getOperand(3), DAG.getValueType(MVT::i8));
1795
1796    } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1797               Tmp3 != Node->getOperand(2)) {
1798      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
1799                                      Node->getOperand(3), Node->getOperand(4));
1800    }
1801
1802    MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1803    switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1804    default: assert(0 && "This action is not supported yet!");
1805    case TargetLowering::Legal: break;
1806    case TargetLowering::Custom:
1807      Tmp1 = TLI.LowerOperation(Result, DAG);
1808      if (Tmp1.Val) Result = Tmp1;
1809      break;
1810    }
1811    break;
1812  }
1813  case ISD::SELECT:
1814    switch (getTypeAction(Node->getOperand(0).getValueType())) {
1815    case Expand: assert(0 && "It's impossible to expand bools");
1816    case Legal:
1817      Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1818      break;
1819    case Promote:
1820      Tmp1 = PromoteOp(Node->getOperand(0));  // Promote the condition.
1821      break;
1822    }
1823    Tmp2 = LegalizeOp(Node->getOperand(1));   // TrueVal
1824    Tmp3 = LegalizeOp(Node->getOperand(2));   // FalseVal
1825
1826    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1827
1828    switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1829    default: assert(0 && "This action is not supported yet!");
1830    case TargetLowering::Legal: break;
1831    case TargetLowering::Custom: {
1832      Tmp1 = TLI.LowerOperation(Result, DAG);
1833      if (Tmp1.Val) Result = Tmp1;
1834      break;
1835    }
1836    case TargetLowering::Expand:
1837      if (Tmp1.getOpcode() == ISD::SETCC) {
1838        Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1839                              Tmp2, Tmp3,
1840                              cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1841      } else {
1842        // Make sure the condition is either zero or one.  It may have been
1843        // promoted from something else.
1844        unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
1845        if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
1846          Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1847        Result = DAG.getSelectCC(Tmp1,
1848                                 DAG.getConstant(0, Tmp1.getValueType()),
1849                                 Tmp2, Tmp3, ISD::SETNE);
1850      }
1851      break;
1852    case TargetLowering::Promote: {
1853      MVT::ValueType NVT =
1854        TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1855      unsigned ExtOp, TruncOp;
1856      if (MVT::isVector(Tmp2.getValueType())) {
1857        ExtOp   = ISD::BIT_CONVERT;
1858        TruncOp = ISD::BIT_CONVERT;
1859      } else if (MVT::isInteger(Tmp2.getValueType())) {
1860        ExtOp   = ISD::ANY_EXTEND;
1861        TruncOp = ISD::TRUNCATE;
1862      } else {
1863        ExtOp   = ISD::FP_EXTEND;
1864        TruncOp = ISD::FP_ROUND;
1865      }
1866      // Promote each of the values to the new type.
1867      Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1868      Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1869      // Perform the larger operation, then round down.
1870      Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1871      Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1872      break;
1873    }
1874    }
1875    break;
1876  case ISD::SELECT_CC: {
1877    Tmp1 = Node->getOperand(0);               // LHS
1878    Tmp2 = Node->getOperand(1);               // RHS
1879    Tmp3 = LegalizeOp(Node->getOperand(2));   // True
1880    Tmp4 = LegalizeOp(Node->getOperand(3));   // False
1881    SDOperand CC = Node->getOperand(4);
1882
1883    LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1884
1885    // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1886    // the LHS is a legal SETCC itself.  In this case, we need to compare
1887    // the result against zero to select between true and false values.
1888    if (Tmp2.Val == 0) {
1889      Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1890      CC = DAG.getCondCode(ISD::SETNE);
1891    }
1892    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1893
1894    // Everything is legal, see if we should expand this op or something.
1895    switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1896    default: assert(0 && "This action is not supported yet!");
1897    case TargetLowering::Legal: break;
1898    case TargetLowering::Custom:
1899      Tmp1 = TLI.LowerOperation(Result, DAG);
1900      if (Tmp1.Val) Result = Tmp1;
1901      break;
1902    }
1903    break;
1904  }
1905  case ISD::SETCC:
1906    Tmp1 = Node->getOperand(0);
1907    Tmp2 = Node->getOperand(1);
1908    Tmp3 = Node->getOperand(2);
1909    LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1910
1911    // If we had to Expand the SetCC operands into a SELECT node, then it may
1912    // not always be possible to return a true LHS & RHS.  In this case, just
1913    // return the value we legalized, returned in the LHS
1914    if (Tmp2.Val == 0) {
1915      Result = Tmp1;
1916      break;
1917    }
1918
1919    switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1920    default: assert(0 && "Cannot handle this action for SETCC yet!");
1921    case TargetLowering::Custom:
1922      isCustom = true;
1923      // FALLTHROUGH.
1924    case TargetLowering::Legal:
1925      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1926      if (isCustom) {
1927        Tmp3 = TLI.LowerOperation(Result, DAG);
1928        if (Tmp3.Val) Result = Tmp3;
1929      }
1930      break;
1931    case TargetLowering::Promote: {
1932      // First step, figure out the appropriate operation to use.
1933      // Allow SETCC to not be supported for all legal data types
1934      // Mostly this targets FP
1935      MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1936      MVT::ValueType OldVT = NewInTy;
1937
1938      // Scan for the appropriate larger type to use.
1939      while (1) {
1940        NewInTy = (MVT::ValueType)(NewInTy+1);
1941
1942        assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1943               "Fell off of the edge of the integer world");
1944        assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1945               "Fell off of the edge of the floating point world");
1946
1947        // If the target supports SETCC of this type, use it.
1948        if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1949          break;
1950      }
1951      if (MVT::isInteger(NewInTy))
1952        assert(0 && "Cannot promote Legal Integer SETCC yet");
1953      else {
1954        Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1955        Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1956      }
1957      Tmp1 = LegalizeOp(Tmp1);
1958      Tmp2 = LegalizeOp(Tmp2);
1959      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1960      Result = LegalizeOp(Result);
1961      break;
1962    }
1963    case TargetLowering::Expand:
1964      // Expand a setcc node into a select_cc of the same condition, lhs, and
1965      // rhs that selects between const 1 (true) and const 0 (false).
1966      MVT::ValueType VT = Node->getValueType(0);
1967      Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1968                           DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1969                           Node->getOperand(2));
1970      break;
1971    }
1972    break;
1973  case ISD::MEMSET:
1974  case ISD::MEMCPY:
1975  case ISD::MEMMOVE: {
1976    Tmp1 = LegalizeOp(Node->getOperand(0));      // Chain
1977    Tmp2 = LegalizeOp(Node->getOperand(1));      // Pointer
1978
1979    if (Node->getOpcode() == ISD::MEMSET) {      // memset = ubyte
1980      switch (getTypeAction(Node->getOperand(2).getValueType())) {
1981      case Expand: assert(0 && "Cannot expand a byte!");
1982      case Legal:
1983        Tmp3 = LegalizeOp(Node->getOperand(2));
1984        break;
1985      case Promote:
1986        Tmp3 = PromoteOp(Node->getOperand(2));
1987        break;
1988      }
1989    } else {
1990      Tmp3 = LegalizeOp(Node->getOperand(2));    // memcpy/move = pointer,
1991    }
1992
1993    SDOperand Tmp4;
1994    switch (getTypeAction(Node->getOperand(3).getValueType())) {
1995    case Expand: {
1996      // Length is too big, just take the lo-part of the length.
1997      SDOperand HiPart;
1998      ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1999      break;
2000    }
2001    case Legal:
2002      Tmp4 = LegalizeOp(Node->getOperand(3));
2003      break;
2004    case Promote:
2005      Tmp4 = PromoteOp(Node->getOperand(3));
2006      break;
2007    }
2008
2009    SDOperand Tmp5;
2010    switch (getTypeAction(Node->getOperand(4).getValueType())) {  // uint
2011    case Expand: assert(0 && "Cannot expand this yet!");
2012    case Legal:
2013      Tmp5 = LegalizeOp(Node->getOperand(4));
2014      break;
2015    case Promote:
2016      Tmp5 = PromoteOp(Node->getOperand(4));
2017      break;
2018    }
2019
2020    switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2021    default: assert(0 && "This action not implemented for this operation!");
2022    case TargetLowering::Custom:
2023      isCustom = true;
2024      // FALLTHROUGH
2025    case TargetLowering::Legal:
2026      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2027      if (isCustom) {
2028        Tmp1 = TLI.LowerOperation(Result, DAG);
2029        if (Tmp1.Val) Result = Tmp1;
2030      }
2031      break;
2032    case TargetLowering::Expand: {
2033      // Otherwise, the target does not support this operation.  Lower the
2034      // operation to an explicit libcall as appropriate.
2035      MVT::ValueType IntPtr = TLI.getPointerTy();
2036      const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2037      std::vector<std::pair<SDOperand, const Type*> > Args;
2038
2039      const char *FnName = 0;
2040      if (Node->getOpcode() == ISD::MEMSET) {
2041        Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2042        // Extend the (previously legalized) ubyte argument to be an int value
2043        // for the call.
2044        if (Tmp3.getValueType() > MVT::i32)
2045          Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2046        else
2047          Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2048        Args.push_back(std::make_pair(Tmp3, Type::IntTy));
2049        Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2050
2051        FnName = "memset";
2052      } else if (Node->getOpcode() == ISD::MEMCPY ||
2053                 Node->getOpcode() == ISD::MEMMOVE) {
2054        Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2055        Args.push_back(std::make_pair(Tmp3, IntPtrTy));
2056        Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2057        FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2058      } else {
2059        assert(0 && "Unknown op!");
2060      }
2061
2062      std::pair<SDOperand,SDOperand> CallResult =
2063        TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
2064                        DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2065      Result = CallResult.second;
2066      break;
2067    }
2068    }
2069    break;
2070  }
2071
2072  case ISD::SHL_PARTS:
2073  case ISD::SRA_PARTS:
2074  case ISD::SRL_PARTS: {
2075    SmallVector<SDOperand, 8> Ops;
2076    bool Changed = false;
2077    for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2078      Ops.push_back(LegalizeOp(Node->getOperand(i)));
2079      Changed |= Ops.back() != Node->getOperand(i);
2080    }
2081    if (Changed)
2082      Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2083
2084    switch (TLI.getOperationAction(Node->getOpcode(),
2085                                   Node->getValueType(0))) {
2086    default: assert(0 && "This action is not supported yet!");
2087    case TargetLowering::Legal: break;
2088    case TargetLowering::Custom:
2089      Tmp1 = TLI.LowerOperation(Result, DAG);
2090      if (Tmp1.Val) {
2091        SDOperand Tmp2, RetVal(0, 0);
2092        for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2093          Tmp2 = LegalizeOp(Tmp1.getValue(i));
2094          AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2095          if (i == Op.ResNo)
2096            RetVal = Tmp2;
2097        }
2098        assert(RetVal.Val && "Illegal result number");
2099        return RetVal;
2100      }
2101      break;
2102    }
2103
2104    // Since these produce multiple values, make sure to remember that we
2105    // legalized all of them.
2106    for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2107      AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2108    return Result.getValue(Op.ResNo);
2109  }
2110
2111    // Binary operators
2112  case ISD::ADD:
2113  case ISD::SUB:
2114  case ISD::MUL:
2115  case ISD::MULHS:
2116  case ISD::MULHU:
2117  case ISD::UDIV:
2118  case ISD::SDIV:
2119  case ISD::AND:
2120  case ISD::OR:
2121  case ISD::XOR:
2122  case ISD::SHL:
2123  case ISD::SRL:
2124  case ISD::SRA:
2125  case ISD::FADD:
2126  case ISD::FSUB:
2127  case ISD::FMUL:
2128  case ISD::FDIV:
2129    Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
2130    switch (getTypeAction(Node->getOperand(1).getValueType())) {
2131    case Expand: assert(0 && "Not possible");
2132    case Legal:
2133      Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2134      break;
2135    case Promote:
2136      Tmp2 = PromoteOp(Node->getOperand(1));  // Promote the RHS.
2137      break;
2138    }
2139
2140    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2141
2142    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2143    default: assert(0 && "BinOp legalize operation not supported");
2144    case TargetLowering::Legal: break;
2145    case TargetLowering::Custom:
2146      Tmp1 = TLI.LowerOperation(Result, DAG);
2147      if (Tmp1.Val) Result = Tmp1;
2148      break;
2149    case TargetLowering::Expand: {
2150      assert(MVT::isVector(Node->getValueType(0)) &&
2151             "Cannot expand this binary operator!");
2152      // Expand the operation into a bunch of nasty scalar code.
2153      SmallVector<SDOperand, 8> Ops;
2154      MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2155      MVT::ValueType PtrVT = TLI.getPointerTy();
2156      for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2157           i != e; ++i) {
2158        SDOperand Idx = DAG.getConstant(i, PtrVT);
2159        SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2160        SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2161        Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2162      }
2163      Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2164                           &Ops[0], Ops.size());
2165      break;
2166    }
2167    case TargetLowering::Promote: {
2168      switch (Node->getOpcode()) {
2169      default:  assert(0 && "Do not know how to promote this BinOp!");
2170      case ISD::AND:
2171      case ISD::OR:
2172      case ISD::XOR: {
2173        MVT::ValueType OVT = Node->getValueType(0);
2174        MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2175        assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2176        // Bit convert each of the values to the new type.
2177        Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2178        Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2179        Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2180        // Bit convert the result back the original type.
2181        Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2182        break;
2183      }
2184      }
2185    }
2186    }
2187    break;
2188
2189  case ISD::FCOPYSIGN:  // FCOPYSIGN does not require LHS/RHS to match type!
2190    Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
2191    switch (getTypeAction(Node->getOperand(1).getValueType())) {
2192      case Expand: assert(0 && "Not possible");
2193      case Legal:
2194        Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2195        break;
2196      case Promote:
2197        Tmp2 = PromoteOp(Node->getOperand(1));  // Promote the RHS.
2198        break;
2199    }
2200
2201    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2202
2203    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2204    default: assert(0 && "Operation not supported");
2205    case TargetLowering::Custom:
2206      Tmp1 = TLI.LowerOperation(Result, DAG);
2207      if (Tmp1.Val) Result = Tmp1;
2208      break;
2209    case TargetLowering::Legal: break;
2210    case TargetLowering::Expand:
2211      // If this target supports fabs/fneg natively, do this efficiently.
2212      if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
2213          TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
2214        // Get the sign bit of the RHS.
2215        MVT::ValueType IVT =
2216          Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2217        SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2218        SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2219                               SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2220        // Get the absolute value of the result.
2221        SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2222        // Select between the nabs and abs value based on the sign bit of
2223        // the input.
2224        Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2225                             DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2226                                         AbsVal),
2227                             AbsVal);
2228        Result = LegalizeOp(Result);
2229        break;
2230      }
2231
2232      // Otherwise, do bitwise ops!
2233
2234      // copysign -> copysignf/copysign libcall.
2235      const char *FnName;
2236      if (Node->getValueType(0) == MVT::f32) {
2237        FnName = "copysignf";
2238        if (Tmp2.getValueType() != MVT::f32)  // Force operands to match type.
2239          Result = DAG.UpdateNodeOperands(Result, Tmp1,
2240                                    DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
2241      } else {
2242        FnName = "copysign";
2243        if (Tmp2.getValueType() != MVT::f64)  // Force operands to match type.
2244          Result = DAG.UpdateNodeOperands(Result, Tmp1,
2245                                   DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
2246      }
2247      SDOperand Dummy;
2248      Result = ExpandLibCall(FnName, Node, Dummy);
2249      break;
2250    }
2251    break;
2252
2253  case ISD::ADDC:
2254  case ISD::SUBC:
2255    Tmp1 = LegalizeOp(Node->getOperand(0));
2256    Tmp2 = LegalizeOp(Node->getOperand(1));
2257    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2258    // Since this produces two values, make sure to remember that we legalized
2259    // both of them.
2260    AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2261    AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2262    return Result;
2263
2264  case ISD::ADDE:
2265  case ISD::SUBE:
2266    Tmp1 = LegalizeOp(Node->getOperand(0));
2267    Tmp2 = LegalizeOp(Node->getOperand(1));
2268    Tmp3 = LegalizeOp(Node->getOperand(2));
2269    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2270    // Since this produces two values, make sure to remember that we legalized
2271    // both of them.
2272    AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2273    AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2274    return Result;
2275
2276  case ISD::BUILD_PAIR: {
2277    MVT::ValueType PairTy = Node->getValueType(0);
2278    // TODO: handle the case where the Lo and Hi operands are not of legal type
2279    Tmp1 = LegalizeOp(Node->getOperand(0));   // Lo
2280    Tmp2 = LegalizeOp(Node->getOperand(1));   // Hi
2281    switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2282    case TargetLowering::Promote:
2283    case TargetLowering::Custom:
2284      assert(0 && "Cannot promote/custom this yet!");
2285    case TargetLowering::Legal:
2286      if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2287        Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2288      break;
2289    case TargetLowering::Expand:
2290      Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2291      Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2292      Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2293                         DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2294                                         TLI.getShiftAmountTy()));
2295      Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2296      break;
2297    }
2298    break;
2299  }
2300
2301  case ISD::UREM:
2302  case ISD::SREM:
2303  case ISD::FREM:
2304    Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
2305    Tmp2 = LegalizeOp(Node->getOperand(1));   // RHS
2306
2307    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2308    case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2309    case TargetLowering::Custom:
2310      isCustom = true;
2311      // FALLTHROUGH
2312    case TargetLowering::Legal:
2313      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2314      if (isCustom) {
2315        Tmp1 = TLI.LowerOperation(Result, DAG);
2316        if (Tmp1.Val) Result = Tmp1;
2317      }
2318      break;
2319    case TargetLowering::Expand:
2320      if (MVT::isInteger(Node->getValueType(0))) {
2321        // X % Y -> X-X/Y*Y
2322        MVT::ValueType VT = Node->getValueType(0);
2323        unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
2324        Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
2325        Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2326        Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2327      } else {
2328        // Floating point mod -> fmod libcall.
2329        const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2330        SDOperand Dummy;
2331        Result = ExpandLibCall(FnName, Node, Dummy);
2332      }
2333      break;
2334    }
2335    break;
2336  case ISD::VAARG: {
2337    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
2338    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
2339
2340    MVT::ValueType VT = Node->getValueType(0);
2341    switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2342    default: assert(0 && "This action is not supported yet!");
2343    case TargetLowering::Custom:
2344      isCustom = true;
2345      // FALLTHROUGH
2346    case TargetLowering::Legal:
2347      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2348      Result = Result.getValue(0);
2349      Tmp1 = Result.getValue(1);
2350
2351      if (isCustom) {
2352        Tmp2 = TLI.LowerOperation(Result, DAG);
2353        if (Tmp2.Val) {
2354          Result = LegalizeOp(Tmp2);
2355          Tmp1 = LegalizeOp(Tmp2.getValue(1));
2356        }
2357      }
2358      break;
2359    case TargetLowering::Expand: {
2360      SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2361                                     Node->getOperand(2));
2362      // Increment the pointer, VAList, to the next vaarg
2363      Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2364                         DAG.getConstant(MVT::getSizeInBits(VT)/8,
2365                                         TLI.getPointerTy()));
2366      // Store the incremented VAList to the legalized pointer
2367      Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
2368                         Node->getOperand(2));
2369      // Load the actual argument out of the pointer VAList
2370      Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0));
2371      Tmp1 = LegalizeOp(Result.getValue(1));
2372      Result = LegalizeOp(Result);
2373      break;
2374    }
2375    }
2376    // Since VAARG produces two values, make sure to remember that we
2377    // legalized both of them.
2378    AddLegalizedOperand(SDOperand(Node, 0), Result);
2379    AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2380    return Op.ResNo ? Tmp1 : Result;
2381  }
2382
2383  case ISD::VACOPY:
2384    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
2385    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the dest pointer.
2386    Tmp3 = LegalizeOp(Node->getOperand(2));  // Legalize the source pointer.
2387
2388    switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2389    default: assert(0 && "This action is not supported yet!");
2390    case TargetLowering::Custom:
2391      isCustom = true;
2392      // FALLTHROUGH
2393    case TargetLowering::Legal:
2394      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2395                                      Node->getOperand(3), Node->getOperand(4));
2396      if (isCustom) {
2397        Tmp1 = TLI.LowerOperation(Result, DAG);
2398        if (Tmp1.Val) Result = Tmp1;
2399      }
2400      break;
2401    case TargetLowering::Expand:
2402      // This defaults to loading a pointer from the input and storing it to the
2403      // output, returning the chain.
2404      Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3));
2405      Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2,
2406                           Node->getOperand(4));
2407      break;
2408    }
2409    break;
2410
2411  case ISD::VAEND:
2412    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
2413    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
2414
2415    switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2416    default: assert(0 && "This action is not supported yet!");
2417    case TargetLowering::Custom:
2418      isCustom = true;
2419      // FALLTHROUGH
2420    case TargetLowering::Legal:
2421      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2422      if (isCustom) {
2423        Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2424        if (Tmp1.Val) Result = Tmp1;
2425      }
2426      break;
2427    case TargetLowering::Expand:
2428      Result = Tmp1; // Default to a no-op, return the chain
2429      break;
2430    }
2431    break;
2432
2433  case ISD::VASTART:
2434    Tmp1 = LegalizeOp(Node->getOperand(0));  // Legalize the chain.
2435    Tmp2 = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
2436
2437    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2438
2439    switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2440    default: assert(0 && "This action is not supported yet!");
2441    case TargetLowering::Legal: break;
2442    case TargetLowering::Custom:
2443      Tmp1 = TLI.LowerOperation(Result, DAG);
2444      if (Tmp1.Val) Result = Tmp1;
2445      break;
2446    }
2447    break;
2448
2449  case ISD::ROTL:
2450  case ISD::ROTR:
2451    Tmp1 = LegalizeOp(Node->getOperand(0));   // LHS
2452    Tmp2 = LegalizeOp(Node->getOperand(1));   // RHS
2453
2454    assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2455           "Cannot handle this yet!");
2456    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2457    break;
2458
2459  case ISD::BSWAP:
2460    Tmp1 = LegalizeOp(Node->getOperand(0));   // Op
2461    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2462    case TargetLowering::Custom:
2463      assert(0 && "Cannot custom legalize this yet!");
2464    case TargetLowering::Legal:
2465      Result = DAG.UpdateNodeOperands(Result, Tmp1);
2466      break;
2467    case TargetLowering::Promote: {
2468      MVT::ValueType OVT = Tmp1.getValueType();
2469      MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2470      unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2471
2472      Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2473      Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2474      Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2475                           DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2476      break;
2477    }
2478    case TargetLowering::Expand:
2479      Result = ExpandBSWAP(Tmp1);
2480      break;
2481    }
2482    break;
2483
2484  case ISD::CTPOP:
2485  case ISD::CTTZ:
2486  case ISD::CTLZ:
2487    Tmp1 = LegalizeOp(Node->getOperand(0));   // Op
2488    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2489    case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2490    case TargetLowering::Legal:
2491      Result = DAG.UpdateNodeOperands(Result, Tmp1);
2492      break;
2493    case TargetLowering::Promote: {
2494      MVT::ValueType OVT = Tmp1.getValueType();
2495      MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2496
2497      // Zero extend the argument.
2498      Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2499      // Perform the larger operation, then subtract if needed.
2500      Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2501      switch (Node->getOpcode()) {
2502      case ISD::CTPOP:
2503        Result = Tmp1;
2504        break;
2505      case ISD::CTTZ:
2506        //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2507        Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2508                            DAG.getConstant(getSizeInBits(NVT), NVT),
2509                            ISD::SETEQ);
2510        Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2511                           DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2512        break;
2513      case ISD::CTLZ:
2514        // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2515        Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2516                             DAG.getConstant(getSizeInBits(NVT) -
2517                                             getSizeInBits(OVT), NVT));
2518        break;
2519      }
2520      break;
2521    }
2522    case TargetLowering::Expand:
2523      Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2524      break;
2525    }
2526    break;
2527
2528    // Unary operators
2529  case ISD::FABS:
2530  case ISD::FNEG:
2531  case ISD::FSQRT:
2532  case ISD::FSIN:
2533  case ISD::FCOS:
2534    Tmp1 = LegalizeOp(Node->getOperand(0));
2535    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2536    case TargetLowering::Promote:
2537    case TargetLowering::Custom:
2538     isCustom = true;
2539     // FALLTHROUGH
2540    case TargetLowering::Legal:
2541      Result = DAG.UpdateNodeOperands(Result, Tmp1);
2542      if (isCustom) {
2543        Tmp1 = TLI.LowerOperation(Result, DAG);
2544        if (Tmp1.Val) Result = Tmp1;
2545      }
2546      break;
2547    case TargetLowering::Expand:
2548      switch (Node->getOpcode()) {
2549      default: assert(0 && "Unreachable!");
2550      case ISD::FNEG:
2551        // Expand Y = FNEG(X) ->  Y = SUB -0.0, X
2552        Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2553        Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2554        break;
2555      case ISD::FABS: {
2556        // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2557        MVT::ValueType VT = Node->getValueType(0);
2558        Tmp2 = DAG.getConstantFP(0.0, VT);
2559        Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2560        Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2561        Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2562        break;
2563      }
2564      case ISD::FSQRT:
2565      case ISD::FSIN:
2566      case ISD::FCOS: {
2567        MVT::ValueType VT = Node->getValueType(0);
2568        const char *FnName = 0;
2569        switch(Node->getOpcode()) {
2570        case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2571        case ISD::FSIN:  FnName = VT == MVT::f32 ? "sinf"  : "sin"; break;
2572        case ISD::FCOS:  FnName = VT == MVT::f32 ? "cosf"  : "cos"; break;
2573        default: assert(0 && "Unreachable!");
2574        }
2575        SDOperand Dummy;
2576        Result = ExpandLibCall(FnName, Node, Dummy);
2577        break;
2578      }
2579      }
2580      break;
2581    }
2582    break;
2583
2584  case ISD::BIT_CONVERT:
2585    if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2586      Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2587    } else {
2588      switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2589                                     Node->getOperand(0).getValueType())) {
2590      default: assert(0 && "Unknown operation action!");
2591      case TargetLowering::Expand:
2592        Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2593        break;
2594      case TargetLowering::Legal:
2595        Tmp1 = LegalizeOp(Node->getOperand(0));
2596        Result = DAG.UpdateNodeOperands(Result, Tmp1);
2597        break;
2598      }
2599    }
2600    break;
2601  case ISD::VBIT_CONVERT: {
2602    assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2603           "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2604
2605    // The input has to be a vector type, we have to either scalarize it, pack
2606    // it, or convert it based on whether the input vector type is legal.
2607    SDNode *InVal = Node->getOperand(0).Val;
2608    unsigned NumElems =
2609      cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2610    MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2611
2612    // Figure out if there is a Packed type corresponding to this Vector
2613    // type.  If so, convert to the packed type.
2614    MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2615    if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2616      // Turn this into a bit convert of the packed input.
2617      Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2618                           PackVectorOp(Node->getOperand(0), TVT));
2619      break;
2620    } else if (NumElems == 1) {
2621      // Turn this into a bit convert of the scalar input.
2622      Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2623                           PackVectorOp(Node->getOperand(0), EVT));
2624      break;
2625    } else {
2626      // FIXME: UNIMP!  Store then reload
2627      assert(0 && "Cast from unsupported vector type not implemented yet!");
2628    }
2629  }
2630
2631    // Conversion operators.  The source and destination have different types.
2632  case ISD::SINT_TO_FP:
2633  case ISD::UINT_TO_FP: {
2634    bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2635    switch (getTypeAction(Node->getOperand(0).getValueType())) {
2636    case Legal:
2637      switch (TLI.getOperationAction(Node->getOpcode(),
2638                                     Node->getOperand(0).getValueType())) {
2639      default: assert(0 && "Unknown operation action!");
2640      case TargetLowering::Custom:
2641        isCustom = true;
2642        // FALLTHROUGH
2643      case TargetLowering::Legal:
2644        Tmp1 = LegalizeOp(Node->getOperand(0));
2645        Result = DAG.UpdateNodeOperands(Result, Tmp1);
2646        if (isCustom) {
2647          Tmp1 = TLI.LowerOperation(Result, DAG);
2648          if (Tmp1.Val) Result = Tmp1;
2649        }
2650        break;
2651      case TargetLowering::Expand:
2652        Result = ExpandLegalINT_TO_FP(isSigned,
2653                                      LegalizeOp(Node->getOperand(0)),
2654                                      Node->getValueType(0));
2655        break;
2656      case TargetLowering::Promote:
2657        Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2658                                       Node->getValueType(0),
2659                                       isSigned);
2660        break;
2661      }
2662      break;
2663    case Expand:
2664      Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2665                             Node->getValueType(0), Node->getOperand(0));
2666      break;
2667    case Promote:
2668      Tmp1 = PromoteOp(Node->getOperand(0));
2669      if (isSigned) {
2670        Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2671                 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2672      } else {
2673        Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2674                                      Node->getOperand(0).getValueType());
2675      }
2676      Result = DAG.UpdateNodeOperands(Result, Tmp1);
2677      Result = LegalizeOp(Result);  // The 'op' is not necessarily legal!
2678      break;
2679    }
2680    break;
2681  }
2682  case ISD::TRUNCATE:
2683    switch (getTypeAction(Node->getOperand(0).getValueType())) {
2684    case Legal:
2685      Tmp1 = LegalizeOp(Node->getOperand(0));
2686      Result = DAG.UpdateNodeOperands(Result, Tmp1);
2687      break;
2688    case Expand:
2689      ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2690
2691      // Since the result is legal, we should just be able to truncate the low
2692      // part of the source.
2693      Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2694      break;
2695    case Promote:
2696      Result = PromoteOp(Node->getOperand(0));
2697      Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2698      break;
2699    }
2700    break;
2701
2702  case ISD::FP_TO_SINT:
2703  case ISD::FP_TO_UINT:
2704    switch (getTypeAction(Node->getOperand(0).getValueType())) {
2705    case Legal:
2706      Tmp1 = LegalizeOp(Node->getOperand(0));
2707
2708      switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2709      default: assert(0 && "Unknown operation action!");
2710      case TargetLowering::Custom:
2711        isCustom = true;
2712        // FALLTHROUGH
2713      case TargetLowering::Legal:
2714        Result = DAG.UpdateNodeOperands(Result, Tmp1);
2715        if (isCustom) {
2716          Tmp1 = TLI.LowerOperation(Result, DAG);
2717          if (Tmp1.Val) Result = Tmp1;
2718        }
2719        break;
2720      case TargetLowering::Promote:
2721        Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2722                                       Node->getOpcode() == ISD::FP_TO_SINT);
2723        break;
2724      case TargetLowering::Expand:
2725        if (Node->getOpcode() == ISD::FP_TO_UINT) {
2726          SDOperand True, False;
2727          MVT::ValueType VT =  Node->getOperand(0).getValueType();
2728          MVT::ValueType NVT = Node->getValueType(0);
2729          unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2730          Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2731          Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2732                            Node->getOperand(0), Tmp2, ISD::SETLT);
2733          True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2734          False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2735                              DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2736                                          Tmp2));
2737          False = DAG.getNode(ISD::XOR, NVT, False,
2738                              DAG.getConstant(1ULL << ShiftAmt, NVT));
2739          Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2740          break;
2741        } else {
2742          assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2743        }
2744        break;
2745      }
2746      break;
2747    case Expand:
2748      assert(0 && "Shouldn't need to expand other operators here!");
2749    case Promote:
2750      Tmp1 = PromoteOp(Node->getOperand(0));
2751      Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2752      Result = LegalizeOp(Result);
2753      break;
2754    }
2755    break;
2756
2757  case ISD::ANY_EXTEND:
2758  case ISD::ZERO_EXTEND:
2759  case ISD::SIGN_EXTEND:
2760  case ISD::FP_EXTEND:
2761  case ISD::FP_ROUND:
2762    switch (getTypeAction(Node->getOperand(0).getValueType())) {
2763    case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2764    case Legal:
2765      Tmp1 = LegalizeOp(Node->getOperand(0));
2766      Result = DAG.UpdateNodeOperands(Result, Tmp1);
2767      break;
2768    case Promote:
2769      switch (Node->getOpcode()) {
2770      case ISD::ANY_EXTEND:
2771        Tmp1 = PromoteOp(Node->getOperand(0));
2772        Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2773        break;
2774      case ISD::ZERO_EXTEND:
2775        Result = PromoteOp(Node->getOperand(0));
2776        Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2777        Result = DAG.getZeroExtendInReg(Result,
2778                                        Node->getOperand(0).getValueType());
2779        break;
2780      case ISD::SIGN_EXTEND:
2781        Result = PromoteOp(Node->getOperand(0));
2782        Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2783        Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2784                             Result,
2785                          DAG.getValueType(Node->getOperand(0).getValueType()));
2786        break;
2787      case ISD::FP_EXTEND:
2788        Result = PromoteOp(Node->getOperand(0));
2789        if (Result.getValueType() != Op.getValueType())
2790          // Dynamically dead while we have only 2 FP types.
2791          Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2792        break;
2793      case ISD::FP_ROUND:
2794        Result = PromoteOp(Node->getOperand(0));
2795        Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2796        break;
2797      }
2798    }
2799    break;
2800  case ISD::FP_ROUND_INREG:
2801  case ISD::SIGN_EXTEND_INREG: {
2802    Tmp1 = LegalizeOp(Node->getOperand(0));
2803    MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2804
2805    // If this operation is not supported, convert it to a shl/shr or load/store
2806    // pair.
2807    switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2808    default: assert(0 && "This action not supported for this op yet!");
2809    case TargetLowering::Legal:
2810      Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2811      break;
2812    case TargetLowering::Expand:
2813      // If this is an integer extend and shifts are supported, do that.
2814      if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2815        // NOTE: we could fall back on load/store here too for targets without
2816        // SAR.  However, it is doubtful that any exist.
2817        unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2818                            MVT::getSizeInBits(ExtraVT);
2819        SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2820        Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2821                             Node->getOperand(0), ShiftCst);
2822        Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2823                             Result, ShiftCst);
2824      } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2825        // The only way we can lower this is to turn it into a STORETRUNC,
2826        // EXTLOAD pair, targetting a temporary location (a stack slot).
2827
2828        // NOTE: there is a choice here between constantly creating new stack
2829        // slots and always reusing the same one.  We currently always create
2830        // new ones, as reuse may inhibit scheduling.
2831        const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2832        unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
2833        unsigned Align  = TLI.getTargetData()->getTypeAlignment(Ty);
2834        MachineFunction &MF = DAG.getMachineFunction();
2835        int SSFI =
2836          MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2837        SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2838        Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2839                             Node->getOperand(0), StackSlot,
2840                             DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2841        Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2842                                Result, StackSlot, DAG.getSrcValue(NULL),
2843                                ExtraVT);
2844      } else {
2845        assert(0 && "Unknown op");
2846      }
2847      break;
2848    }
2849    break;
2850  }
2851  }
2852
2853  assert(Result.getValueType() == Op.getValueType() &&
2854         "Bad legalization!");
2855
2856  // Make sure that the generated code is itself legal.
2857  if (Result != Op)
2858    Result = LegalizeOp(Result);
2859
2860  // Note that LegalizeOp may be reentered even from single-use nodes, which
2861  // means that we always must cache transformed nodes.
2862  AddLegalizedOperand(Op, Result);
2863  return Result;
2864}
2865
2866/// PromoteOp - Given an operation that produces a value in an invalid type,
2867/// promote it to compute the value into a larger type.  The produced value will
2868/// have the correct bits for the low portion of the register, but no guarantee
2869/// is made about the top bits: it may be zero, sign-extended, or garbage.
2870SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2871  MVT::ValueType VT = Op.getValueType();
2872  MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2873  assert(getTypeAction(VT) == Promote &&
2874         "Caller should expand or legalize operands that are not promotable!");
2875  assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2876         "Cannot promote to smaller type!");
2877
2878  SDOperand Tmp1, Tmp2, Tmp3;
2879  SDOperand Result;
2880  SDNode *Node = Op.Val;
2881
2882  std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2883  if (I != PromotedNodes.end()) return I->second;
2884
2885  switch (Node->getOpcode()) {
2886  case ISD::CopyFromReg:
2887    assert(0 && "CopyFromReg must be legal!");
2888  default:
2889#ifndef NDEBUG
2890    std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2891#endif
2892    assert(0 && "Do not know how to promote this operator!");
2893    abort();
2894  case ISD::UNDEF:
2895    Result = DAG.getNode(ISD::UNDEF, NVT);
2896    break;
2897  case ISD::Constant:
2898    if (VT != MVT::i1)
2899      Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2900    else
2901      Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2902    assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2903    break;
2904  case ISD::ConstantFP:
2905    Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2906    assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2907    break;
2908
2909  case ISD::SETCC:
2910    assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2911    Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2912                         Node->getOperand(1), Node->getOperand(2));
2913    break;
2914
2915  case ISD::TRUNCATE:
2916    switch (getTypeAction(Node->getOperand(0).getValueType())) {
2917    case Legal:
2918      Result = LegalizeOp(Node->getOperand(0));
2919      assert(Result.getValueType() >= NVT &&
2920             "This truncation doesn't make sense!");
2921      if (Result.getValueType() > NVT)    // Truncate to NVT instead of VT
2922        Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2923      break;
2924    case Promote:
2925      // The truncation is not required, because we don't guarantee anything
2926      // about high bits anyway.
2927      Result = PromoteOp(Node->getOperand(0));
2928      break;
2929    case Expand:
2930      ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2931      // Truncate the low part of the expanded value to the result type
2932      Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2933    }
2934    break;
2935  case ISD::SIGN_EXTEND:
2936  case ISD::ZERO_EXTEND:
2937  case ISD::ANY_EXTEND:
2938    switch (getTypeAction(Node->getOperand(0).getValueType())) {
2939    case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2940    case Legal:
2941      // Input is legal?  Just do extend all the way to the larger type.
2942      Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2943      break;
2944    case Promote:
2945      // Promote the reg if it's smaller.
2946      Result = PromoteOp(Node->getOperand(0));
2947      // The high bits are not guaranteed to be anything.  Insert an extend.
2948      if (Node->getOpcode() == ISD::SIGN_EXTEND)
2949        Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2950                         DAG.getValueType(Node->getOperand(0).getValueType()));
2951      else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2952        Result = DAG.getZeroExtendInReg(Result,
2953                                        Node->getOperand(0).getValueType());
2954      break;
2955    }
2956    break;
2957  case ISD::BIT_CONVERT:
2958    Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2959    Result = PromoteOp(Result);
2960    break;
2961
2962  case ISD::FP_EXTEND:
2963    assert(0 && "Case not implemented.  Dynamically dead with 2 FP types!");
2964  case ISD::FP_ROUND:
2965    switch (getTypeAction(Node->getOperand(0).getValueType())) {
2966    case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2967    case Promote:  assert(0 && "Unreachable with 2 FP types!");
2968    case Legal:
2969      // Input is legal?  Do an FP_ROUND_INREG.
2970      Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
2971                           DAG.getValueType(VT));
2972      break;
2973    }
2974    break;
2975
2976  case ISD::SINT_TO_FP:
2977  case ISD::UINT_TO_FP:
2978    switch (getTypeAction(Node->getOperand(0).getValueType())) {
2979    case Legal:
2980      // No extra round required here.
2981      Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2982      break;
2983
2984    case Promote:
2985      Result = PromoteOp(Node->getOperand(0));
2986      if (Node->getOpcode() == ISD::SINT_TO_FP)
2987        Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2988                             Result,
2989                         DAG.getValueType(Node->getOperand(0).getValueType()));
2990      else
2991        Result = DAG.getZeroExtendInReg(Result,
2992                                        Node->getOperand(0).getValueType());
2993      // No extra round required here.
2994      Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2995      break;
2996    case Expand:
2997      Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2998                             Node->getOperand(0));
2999      // Round if we cannot tolerate excess precision.
3000      if (NoExcessFPPrecision)
3001        Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3002                             DAG.getValueType(VT));
3003      break;
3004    }
3005    break;
3006
3007  case ISD::SIGN_EXTEND_INREG:
3008    Result = PromoteOp(Node->getOperand(0));
3009    Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3010                         Node->getOperand(1));
3011    break;
3012  case ISD::FP_TO_SINT:
3013  case ISD::FP_TO_UINT:
3014    switch (getTypeAction(Node->getOperand(0).getValueType())) {
3015    case Legal:
3016      Tmp1 = Node->getOperand(0);
3017      break;
3018    case Promote:
3019      // The input result is prerounded, so we don't have to do anything
3020      // special.
3021      Tmp1 = PromoteOp(Node->getOperand(0));
3022      break;
3023    case Expand:
3024      assert(0 && "not implemented");
3025    }
3026    // If we're promoting a UINT to a larger size, check to see if the new node
3027    // will be legal.  If it isn't, check to see if FP_TO_SINT is legal, since
3028    // we can use that instead.  This allows us to generate better code for
3029    // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3030    // legal, such as PowerPC.
3031    if (Node->getOpcode() == ISD::FP_TO_UINT &&
3032        !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3033        (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3034         TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3035      Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3036    } else {
3037      Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3038    }
3039    break;
3040
3041  case ISD::FABS:
3042  case ISD::FNEG:
3043    Tmp1 = PromoteOp(Node->getOperand(0));
3044    assert(Tmp1.getValueType() == NVT);
3045    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3046    // NOTE: we do not have to do any extra rounding here for
3047    // NoExcessFPPrecision, because we know the input will have the appropriate
3048    // precision, and these operations don't modify precision at all.
3049    break;
3050
3051  case ISD::FSQRT:
3052  case ISD::FSIN:
3053  case ISD::FCOS:
3054    Tmp1 = PromoteOp(Node->getOperand(0));
3055    assert(Tmp1.getValueType() == NVT);
3056    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3057    if (NoExcessFPPrecision)
3058      Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3059                           DAG.getValueType(VT));
3060    break;
3061
3062  case ISD::AND:
3063  case ISD::OR:
3064  case ISD::XOR:
3065  case ISD::ADD:
3066  case ISD::SUB:
3067  case ISD::MUL:
3068    // The input may have strange things in the top bits of the registers, but
3069    // these operations don't care.  They may have weird bits going out, but
3070    // that too is okay if they are integer operations.
3071    Tmp1 = PromoteOp(Node->getOperand(0));
3072    Tmp2 = PromoteOp(Node->getOperand(1));
3073    assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3074    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3075    break;
3076  case ISD::FADD:
3077  case ISD::FSUB:
3078  case ISD::FMUL:
3079    Tmp1 = PromoteOp(Node->getOperand(0));
3080    Tmp2 = PromoteOp(Node->getOperand(1));
3081    assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3082    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3083
3084    // Floating point operations will give excess precision that we may not be
3085    // able to tolerate.  If we DO allow excess precision, just leave it,
3086    // otherwise excise it.
3087    // FIXME: Why would we need to round FP ops more than integer ones?
3088    //     Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3089    if (NoExcessFPPrecision)
3090      Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3091                           DAG.getValueType(VT));
3092    break;
3093
3094  case ISD::SDIV:
3095  case ISD::SREM:
3096    // These operators require that their input be sign extended.
3097    Tmp1 = PromoteOp(Node->getOperand(0));
3098    Tmp2 = PromoteOp(Node->getOperand(1));
3099    if (MVT::isInteger(NVT)) {
3100      Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3101                         DAG.getValueType(VT));
3102      Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3103                         DAG.getValueType(VT));
3104    }
3105    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3106
3107    // Perform FP_ROUND: this is probably overly pessimistic.
3108    if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3109      Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3110                           DAG.getValueType(VT));
3111    break;
3112  case ISD::FDIV:
3113  case ISD::FREM:
3114  case ISD::FCOPYSIGN:
3115    // These operators require that their input be fp extended.
3116    switch (getTypeAction(Node->getOperand(0).getValueType())) {
3117      case Legal:
3118        Tmp1 = LegalizeOp(Node->getOperand(0));
3119        break;
3120      case Promote:
3121        Tmp1 = PromoteOp(Node->getOperand(0));
3122        break;
3123      case Expand:
3124        assert(0 && "not implemented");
3125    }
3126    switch (getTypeAction(Node->getOperand(1).getValueType())) {
3127      case Legal:
3128        Tmp2 = LegalizeOp(Node->getOperand(1));
3129        break;
3130      case Promote:
3131        Tmp2 = PromoteOp(Node->getOperand(1));
3132        break;
3133      case Expand:
3134        assert(0 && "not implemented");
3135    }
3136    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3137
3138    // Perform FP_ROUND: this is probably overly pessimistic.
3139    if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3140      Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3141                           DAG.getValueType(VT));
3142    break;
3143
3144  case ISD::UDIV:
3145  case ISD::UREM:
3146    // These operators require that their input be zero extended.
3147    Tmp1 = PromoteOp(Node->getOperand(0));
3148    Tmp2 = PromoteOp(Node->getOperand(1));
3149    assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3150    Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3151    Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3152    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3153    break;
3154
3155  case ISD::SHL:
3156    Tmp1 = PromoteOp(Node->getOperand(0));
3157    Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3158    break;
3159  case ISD::SRA:
3160    // The input value must be properly sign extended.
3161    Tmp1 = PromoteOp(Node->getOperand(0));
3162    Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3163                       DAG.getValueType(VT));
3164    Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3165    break;
3166  case ISD::SRL:
3167    // The input value must be properly zero extended.
3168    Tmp1 = PromoteOp(Node->getOperand(0));
3169    Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3170    Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3171    break;
3172
3173  case ISD::VAARG:
3174    Tmp1 = Node->getOperand(0);   // Get the chain.
3175    Tmp2 = Node->getOperand(1);   // Get the pointer.
3176    if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3177      Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3178      Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3179    } else {
3180      SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3181                                     Node->getOperand(2));
3182      // Increment the pointer, VAList, to the next vaarg
3183      Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3184                         DAG.getConstant(MVT::getSizeInBits(VT)/8,
3185                                         TLI.getPointerTy()));
3186      // Store the incremented VAList to the legalized pointer
3187      Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
3188                         Node->getOperand(2));
3189      // Load the actual argument out of the pointer VAList
3190      Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList,
3191                              DAG.getSrcValue(0), VT);
3192    }
3193    // Remember that we legalized the chain.
3194    AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3195    break;
3196
3197  case ISD::LOAD:
3198    Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0),
3199                            Node->getOperand(1), Node->getOperand(2), VT);
3200    // Remember that we legalized the chain.
3201    AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3202    break;
3203  case ISD::SEXTLOAD:
3204  case ISD::ZEXTLOAD:
3205  case ISD::EXTLOAD:
3206    Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0),
3207                            Node->getOperand(1), Node->getOperand(2),
3208                            cast<VTSDNode>(Node->getOperand(3))->getVT());
3209    // Remember that we legalized the chain.
3210    AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3211    break;
3212  case ISD::SELECT:
3213    Tmp2 = PromoteOp(Node->getOperand(1));   // Legalize the op0
3214    Tmp3 = PromoteOp(Node->getOperand(2));   // Legalize the op1
3215    Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3216    break;
3217  case ISD::SELECT_CC:
3218    Tmp2 = PromoteOp(Node->getOperand(2));   // True
3219    Tmp3 = PromoteOp(Node->getOperand(3));   // False
3220    Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3221                         Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3222    break;
3223  case ISD::BSWAP:
3224    Tmp1 = Node->getOperand(0);
3225    Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3226    Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3227    Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3228                         DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3229                                         TLI.getShiftAmountTy()));
3230    break;
3231  case ISD::CTPOP:
3232  case ISD::CTTZ:
3233  case ISD::CTLZ:
3234    // Zero extend the argument
3235    Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3236    // Perform the larger operation, then subtract if needed.
3237    Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3238    switch(Node->getOpcode()) {
3239    case ISD::CTPOP:
3240      Result = Tmp1;
3241      break;
3242    case ISD::CTTZ:
3243      // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3244      Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3245                          DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3246      Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3247                           DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3248      break;
3249    case ISD::CTLZ:
3250      //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3251      Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3252                           DAG.getConstant(getSizeInBits(NVT) -
3253                                           getSizeInBits(VT), NVT));
3254      break;
3255    }
3256    break;
3257  case ISD::VEXTRACT_VECTOR_ELT:
3258    Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3259    break;
3260  case ISD::EXTRACT_VECTOR_ELT:
3261    Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3262    break;
3263  }
3264
3265  assert(Result.Val && "Didn't set a result!");
3266
3267  // Make sure the result is itself legal.
3268  Result = LegalizeOp(Result);
3269
3270  // Remember that we promoted this!
3271  AddPromotedOperand(Op, Result);
3272  return Result;
3273}
3274
3275/// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3276/// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3277/// on the vector type.  The return type of this matches the element type of the
3278/// vector, which may not be legal for the target.
3279SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3280  // We know that operand #0 is the Vec vector.  If the index is a constant
3281  // or if the invec is a supported hardware type, we can use it.  Otherwise,
3282  // lower to a store then an indexed load.
3283  SDOperand Vec = Op.getOperand(0);
3284  SDOperand Idx = LegalizeOp(Op.getOperand(1));
3285
3286  SDNode *InVal = Vec.Val;
3287  unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3288  MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3289
3290  // Figure out if there is a Packed type corresponding to this Vector
3291  // type.  If so, convert to the packed type.
3292  MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3293  if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3294    // Turn this into a packed extract_vector_elt operation.
3295    Vec = PackVectorOp(Vec, TVT);
3296    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3297  } else if (NumElems == 1) {
3298    // This must be an access of the only element.  Return it.
3299    return PackVectorOp(Vec, EVT);
3300  } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3301    SDOperand Lo, Hi;
3302    SplitVectorOp(Vec, Lo, Hi);
3303    if (CIdx->getValue() < NumElems/2) {
3304      Vec = Lo;
3305    } else {
3306      Vec = Hi;
3307      Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3308    }
3309
3310    // It's now an extract from the appropriate high or low part.  Recurse.
3311    Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3312    return LowerVEXTRACT_VECTOR_ELT(Op);
3313  } else {
3314    // Variable index case for extract element.
3315    // FIXME: IMPLEMENT STORE/LOAD lowering.  Need alignment of stack slot!!
3316    assert(0 && "unimp!");
3317    return SDOperand();
3318  }
3319}
3320
3321/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3322/// memory traffic.
3323SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3324  SDOperand Vector = Op.getOperand(0);
3325  SDOperand Idx    = Op.getOperand(1);
3326
3327  // If the target doesn't support this, store the value to a temporary
3328  // stack slot, then LOAD the scalar element back out.
3329  SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3330  SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3331                             Vector, StackPtr, DAG.getSrcValue(NULL));
3332
3333  // Add the offset to the index.
3334  unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3335  Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3336                    DAG.getConstant(EltSize, Idx.getValueType()));
3337  StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3338
3339  return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL));
3340}
3341
3342
3343/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3344/// with condition CC on the current target.  This usually involves legalizing
3345/// or promoting the arguments.  In the case where LHS and RHS must be expanded,
3346/// there may be no choice but to create a new SetCC node to represent the
3347/// legalized value of setcc lhs, rhs.  In this case, the value is returned in
3348/// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3349void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3350                                                 SDOperand &RHS,
3351                                                 SDOperand &CC) {
3352  SDOperand Tmp1, Tmp2, Result;
3353
3354  switch (getTypeAction(LHS.getValueType())) {
3355  case Legal:
3356    Tmp1 = LegalizeOp(LHS);   // LHS
3357    Tmp2 = LegalizeOp(RHS);   // RHS
3358    break;
3359  case Promote:
3360    Tmp1 = PromoteOp(LHS);   // LHS
3361    Tmp2 = PromoteOp(RHS);   // RHS
3362
3363    // If this is an FP compare, the operands have already been extended.
3364    if (MVT::isInteger(LHS.getValueType())) {
3365      MVT::ValueType VT = LHS.getValueType();
3366      MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3367
3368      // Otherwise, we have to insert explicit sign or zero extends.  Note
3369      // that we could insert sign extends for ALL conditions, but zero extend
3370      // is cheaper on many machines (an AND instead of two shifts), so prefer
3371      // it.
3372      switch (cast<CondCodeSDNode>(CC)->get()) {
3373      default: assert(0 && "Unknown integer comparison!");
3374      case ISD::SETEQ:
3375      case ISD::SETNE:
3376      case ISD::SETUGE:
3377      case ISD::SETUGT:
3378      case ISD::SETULE:
3379      case ISD::SETULT:
3380        // ALL of these operations will work if we either sign or zero extend
3381        // the operands (including the unsigned comparisons!).  Zero extend is
3382        // usually a simpler/cheaper operation, so prefer it.
3383        Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3384        Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3385        break;
3386      case ISD::SETGE:
3387      case ISD::SETGT:
3388      case ISD::SETLT:
3389      case ISD::SETLE:
3390        Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3391                           DAG.getValueType(VT));
3392        Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3393                           DAG.getValueType(VT));
3394        break;
3395      }
3396    }
3397    break;
3398  case Expand:
3399    SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3400    ExpandOp(LHS, LHSLo, LHSHi);
3401    ExpandOp(RHS, RHSLo, RHSHi);
3402    switch (cast<CondCodeSDNode>(CC)->get()) {
3403    case ISD::SETEQ:
3404    case ISD::SETNE:
3405      if (RHSLo == RHSHi)
3406        if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3407          if (RHSCST->isAllOnesValue()) {
3408            // Comparison to -1.
3409            Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3410            Tmp2 = RHSLo;
3411            break;
3412          }
3413
3414      Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3415      Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3416      Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3417      Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3418      break;
3419    default:
3420      // If this is a comparison of the sign bit, just look at the top part.
3421      // X > -1,  x < 0
3422      if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3423        if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3424             CST->getValue() == 0) ||             // X < 0
3425            (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3426             CST->isAllOnesValue())) {            // X > -1
3427          Tmp1 = LHSHi;
3428          Tmp2 = RHSHi;
3429          break;
3430        }
3431
3432      // FIXME: This generated code sucks.
3433      ISD::CondCode LowCC;
3434      switch (cast<CondCodeSDNode>(CC)->get()) {
3435      default: assert(0 && "Unknown integer setcc!");
3436      case ISD::SETLT:
3437      case ISD::SETULT: LowCC = ISD::SETULT; break;
3438      case ISD::SETGT:
3439      case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3440      case ISD::SETLE:
3441      case ISD::SETULE: LowCC = ISD::SETULE; break;
3442      case ISD::SETGE:
3443      case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3444      }
3445
3446      // Tmp1 = lo(op1) < lo(op2)   // Always unsigned comparison
3447      // Tmp2 = hi(op1) < hi(op2)   // Signedness depends on operands
3448      // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3449
3450      // NOTE: on targets without efficient SELECT of bools, we can always use
3451      // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3452      Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3453      Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3454      Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3455      Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3456                                      Result, Tmp1, Tmp2));
3457      Tmp1 = Result;
3458      Tmp2 = SDOperand();
3459    }
3460  }
3461  LHS = Tmp1;
3462  RHS = Tmp2;
3463}
3464
3465/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3466/// The resultant code need not be legal.  Note that SrcOp is the input operand
3467/// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3468SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3469                                                  SDOperand SrcOp) {
3470  // Create the stack frame object.
3471  SDOperand FIPtr = CreateStackTemporary(DestVT);
3472
3473  // Emit a store to the stack slot.
3474  SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3475                                SrcOp, FIPtr, DAG.getSrcValue(NULL));
3476  // Result is a load from the stack slot.
3477  return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
3478}
3479
3480SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3481  // Create a vector sized/aligned stack slot, store the value to element #0,
3482  // then load the whole vector back out.
3483  SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3484  SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3485                             Node->getOperand(0), StackPtr,
3486                             DAG.getSrcValue(NULL));
3487  return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL));
3488}
3489
3490
3491/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3492/// support the operation, but do support the resultant packed vector type.
3493SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3494
3495  // If the only non-undef value is the low element, turn this into a
3496  // SCALAR_TO_VECTOR node.  If this is { X, X, X, X }, determine X.
3497  unsigned NumElems = Node->getNumOperands();
3498  bool isOnlyLowElement = true;
3499  SDOperand SplatValue = Node->getOperand(0);
3500  std::map<SDOperand, std::vector<unsigned> > Values;
3501  Values[SplatValue].push_back(0);
3502  bool isConstant = true;
3503  if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3504      SplatValue.getOpcode() != ISD::UNDEF)
3505    isConstant = false;
3506
3507  for (unsigned i = 1; i < NumElems; ++i) {
3508    SDOperand V = Node->getOperand(i);
3509    Values[V].push_back(i);
3510    if (V.getOpcode() != ISD::UNDEF)
3511      isOnlyLowElement = false;
3512    if (SplatValue != V)
3513      SplatValue = SDOperand(0,0);
3514
3515    // If this isn't a constant element or an undef, we can't use a constant
3516    // pool load.
3517    if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3518        V.getOpcode() != ISD::UNDEF)
3519      isConstant = false;
3520  }
3521
3522  if (isOnlyLowElement) {
3523    // If the low element is an undef too, then this whole things is an undef.
3524    if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3525      return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3526    // Otherwise, turn this into a scalar_to_vector node.
3527    return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3528                       Node->getOperand(0));
3529  }
3530
3531  // If all elements are constants, create a load from the constant pool.
3532  if (isConstant) {
3533    MVT::ValueType VT = Node->getValueType(0);
3534    const Type *OpNTy =
3535      MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3536    std::vector<Constant*> CV;
3537    for (unsigned i = 0, e = NumElems; i != e; ++i) {
3538      if (ConstantFPSDNode *V =
3539          dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3540        CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3541      } else if (ConstantSDNode *V =
3542                 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3543        CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
3544      } else {
3545        assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3546        CV.push_back(UndefValue::get(OpNTy));
3547      }
3548    }
3549    Constant *CP = ConstantPacked::get(CV);
3550    SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3551    return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
3552                       DAG.getSrcValue(NULL));
3553  }
3554
3555  if (SplatValue.Val) {   // Splat of one value?
3556    // Build the shuffle constant vector: <0, 0, 0, 0>
3557    MVT::ValueType MaskVT =
3558      MVT::getIntVectorWithNumElements(NumElems);
3559    SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3560    std::vector<SDOperand> ZeroVec(NumElems, Zero);
3561    SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3562                                      &ZeroVec[0], ZeroVec.size());
3563
3564    // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3565    if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3566      // Get the splatted value into the low element of a vector register.
3567      SDOperand LowValVec =
3568        DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3569
3570      // Return shuffle(LowValVec, undef, <0,0,0,0>)
3571      return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3572                         DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3573                         SplatMask);
3574    }
3575  }
3576
3577  // If there are only two unique elements, we may be able to turn this into a
3578  // vector shuffle.
3579  if (Values.size() == 2) {
3580    // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3581    MVT::ValueType MaskVT =
3582      MVT::getIntVectorWithNumElements(NumElems);
3583    std::vector<SDOperand> MaskVec(NumElems);
3584    unsigned i = 0;
3585    for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3586           E = Values.end(); I != E; ++I) {
3587      for (std::vector<unsigned>::iterator II = I->second.begin(),
3588             EE = I->second.end(); II != EE; ++II)
3589        MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3590      i += NumElems;
3591    }
3592    SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3593                                        &MaskVec[0], MaskVec.size());
3594
3595    // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3596    if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3597        isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3598      SmallVector<SDOperand, 8> Ops;
3599      for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3600            E = Values.end(); I != E; ++I) {
3601        SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3602                                   I->first);
3603        Ops.push_back(Op);
3604      }
3605      Ops.push_back(ShuffleMask);
3606
3607      // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3608      return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
3609                         &Ops[0], Ops.size());
3610    }
3611  }
3612
3613  // Otherwise, we can't handle this case efficiently.  Allocate a sufficiently
3614  // aligned object on the stack, store each element into it, then load
3615  // the result as a vector.
3616  MVT::ValueType VT = Node->getValueType(0);
3617  // Create the stack frame object.
3618  SDOperand FIPtr = CreateStackTemporary(VT);
3619
3620  // Emit a store of each element to the stack slot.
3621  SmallVector<SDOperand, 8> Stores;
3622  unsigned TypeByteSize =
3623    MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3624  unsigned VectorSize = MVT::getSizeInBits(VT)/8;
3625  // Store (in the right endianness) the elements to memory.
3626  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3627    // Ignore undef elements.
3628    if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3629
3630    unsigned Offset = TypeByteSize*i;
3631
3632    SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3633    Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3634
3635    Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3636                                 Node->getOperand(i), Idx,
3637                                 DAG.getSrcValue(NULL)));
3638  }
3639
3640  SDOperand StoreChain;
3641  if (!Stores.empty())    // Not all undef elements?
3642    StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3643                             &Stores[0], Stores.size());
3644  else
3645    StoreChain = DAG.getEntryNode();
3646
3647  // Result is a load from the stack slot.
3648  return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
3649}
3650
3651/// CreateStackTemporary - Create a stack temporary, suitable for holding the
3652/// specified value type.
3653SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3654  MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3655  unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3656  int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3657  return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3658}
3659
3660void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3661                                            SDOperand Op, SDOperand Amt,
3662                                            SDOperand &Lo, SDOperand &Hi) {
3663  // Expand the subcomponents.
3664  SDOperand LHSL, LHSH;
3665  ExpandOp(Op, LHSL, LHSH);
3666
3667  SDOperand Ops[] = { LHSL, LHSH, Amt };
3668  std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
3669  Lo = DAG.getNode(NodeOp, VTs, Ops, 3);
3670  Hi = Lo.getValue(1);
3671}
3672
3673
3674/// ExpandShift - Try to find a clever way to expand this shift operation out to
3675/// smaller elements.  If we can't find a way that is more efficient than a
3676/// libcall on this target, return false.  Otherwise, return true with the
3677/// low-parts expanded into Lo and Hi.
3678bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3679                                       SDOperand &Lo, SDOperand &Hi) {
3680  assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3681         "This is not a shift!");
3682
3683  MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3684  SDOperand ShAmt = LegalizeOp(Amt);
3685  MVT::ValueType ShTy = ShAmt.getValueType();
3686  unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3687  unsigned NVTBits = MVT::getSizeInBits(NVT);
3688
3689  // Handle the case when Amt is an immediate.  Other cases are currently broken
3690  // and are disabled.
3691  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3692    unsigned Cst = CN->getValue();
3693    // Expand the incoming operand to be shifted, so that we have its parts
3694    SDOperand InL, InH;
3695    ExpandOp(Op, InL, InH);
3696    switch(Opc) {
3697    case ISD::SHL:
3698      if (Cst > VTBits) {
3699        Lo = DAG.getConstant(0, NVT);
3700        Hi = DAG.getConstant(0, NVT);
3701      } else if (Cst > NVTBits) {
3702        Lo = DAG.getConstant(0, NVT);
3703        Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3704      } else if (Cst == NVTBits) {
3705        Lo = DAG.getConstant(0, NVT);
3706        Hi = InL;
3707      } else {
3708        Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3709        Hi = DAG.getNode(ISD::OR, NVT,
3710           DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3711           DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3712      }
3713      return true;
3714    case ISD::SRL:
3715      if (Cst > VTBits) {
3716        Lo = DAG.getConstant(0, NVT);
3717        Hi = DAG.getConstant(0, NVT);
3718      } else if (Cst > NVTBits) {
3719        Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3720        Hi = DAG.getConstant(0, NVT);
3721      } else if (Cst == NVTBits) {
3722        Lo = InH;
3723        Hi = DAG.getConstant(0, NVT);
3724      } else {
3725        Lo = DAG.getNode(ISD::OR, NVT,
3726           DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3727           DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3728        Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3729      }
3730      return true;
3731    case ISD::SRA:
3732      if (Cst > VTBits) {
3733        Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3734                              DAG.getConstant(NVTBits-1, ShTy));
3735      } else if (Cst > NVTBits) {
3736        Lo = DAG.getNode(ISD::SRA, NVT, InH,
3737                           DAG.getConstant(Cst-NVTBits, ShTy));
3738        Hi = DAG.getNode(ISD::SRA, NVT, InH,
3739                              DAG.getConstant(NVTBits-1, ShTy));
3740      } else if (Cst == NVTBits) {
3741        Lo = InH;
3742        Hi = DAG.getNode(ISD::SRA, NVT, InH,
3743                              DAG.getConstant(NVTBits-1, ShTy));
3744      } else {
3745        Lo = DAG.getNode(ISD::OR, NVT,
3746           DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3747           DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3748        Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3749      }
3750      return true;
3751    }
3752  }
3753  return false;
3754}
3755
3756
3757// ExpandLibCall - Expand a node into a call to a libcall.  If the result value
3758// does not fit into a register, return the lo part and set the hi part to the
3759// by-reg argument.  If it does fit into a single register, return the result
3760// and leave the Hi part unset.
3761SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3762                                              SDOperand &Hi) {
3763  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3764  // The input chain to this libcall is the entry node of the function.
3765  // Legalizing the call will automatically add the previous call to the
3766  // dependence.
3767  SDOperand InChain = DAG.getEntryNode();
3768
3769  TargetLowering::ArgListTy Args;
3770  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3771    MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3772    const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3773    Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3774  }
3775  SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3776
3777  // Splice the libcall in wherever FindInputOutputChains tells us to.
3778  const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3779  std::pair<SDOperand,SDOperand> CallInfo =
3780    TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3781                    Callee, Args, DAG);
3782
3783  // Legalize the call sequence, starting with the chain.  This will advance
3784  // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3785  // was added by LowerCallTo (guaranteeing proper serialization of calls).
3786  LegalizeOp(CallInfo.second);
3787  SDOperand Result;
3788  switch (getTypeAction(CallInfo.first.getValueType())) {
3789  default: assert(0 && "Unknown thing");
3790  case Legal:
3791    Result = CallInfo.first;
3792    break;
3793  case Expand:
3794    ExpandOp(CallInfo.first, Result, Hi);
3795    break;
3796  }
3797  return Result;
3798}
3799
3800
3801/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3802/// destination type is legal.
3803SDOperand SelectionDAGLegalize::
3804ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3805  assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3806  assert(getTypeAction(Source.getValueType()) == Expand &&
3807         "This is not an expansion!");
3808  assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3809
3810  if (!isSigned) {
3811    assert(Source.getValueType() == MVT::i64 &&
3812           "This only works for 64-bit -> FP");
3813    // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3814    // incoming integer is set.  To handle this, we dynamically test to see if
3815    // it is set, and, if so, add a fudge factor.
3816    SDOperand Lo, Hi;
3817    ExpandOp(Source, Lo, Hi);
3818
3819    // If this is unsigned, and not supported, first perform the conversion to
3820    // signed, then adjust the result if the sign bit is set.
3821    SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3822                   DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3823
3824    SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3825                                     DAG.getConstant(0, Hi.getValueType()),
3826                                     ISD::SETLT);
3827    SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3828    SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3829                                      SignSet, Four, Zero);
3830    uint64_t FF = 0x5f800000ULL;
3831    if (TLI.isLittleEndian()) FF <<= 32;
3832    static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3833
3834    SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3835    CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3836    SDOperand FudgeInReg;
3837    if (DestTy == MVT::f32)
3838      FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3839                               DAG.getSrcValue(NULL));
3840    else {
3841      assert(DestTy == MVT::f64 && "Unexpected conversion");
3842      FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3843                                  CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3844    }
3845    return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3846  }
3847
3848  // Check to see if the target has a custom way to lower this.  If so, use it.
3849  switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3850  default: assert(0 && "This action not implemented for this operation!");
3851  case TargetLowering::Legal:
3852  case TargetLowering::Expand:
3853    break;   // This case is handled below.
3854  case TargetLowering::Custom: {
3855    SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3856                                                  Source), DAG);
3857    if (NV.Val)
3858      return LegalizeOp(NV);
3859    break;   // The target decided this was legal after all
3860  }
3861  }
3862
3863  // Expand the source, then glue it back together for the call.  We must expand
3864  // the source in case it is shared (this pass of legalize must traverse it).
3865  SDOperand SrcLo, SrcHi;
3866  ExpandOp(Source, SrcLo, SrcHi);
3867  Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3868
3869  const char *FnName = 0;
3870  if (DestTy == MVT::f32)
3871    FnName = "__floatdisf";
3872  else {
3873    assert(DestTy == MVT::f64 && "Unknown fp value type!");
3874    FnName = "__floatdidf";
3875  }
3876
3877  Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
3878  SDOperand UnusedHiPart;
3879  return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
3880}
3881
3882/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
3883/// INT_TO_FP operation of the specified operand when the target requests that
3884/// we expand it.  At this point, we know that the result and operand types are
3885/// legal for the target.
3886SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
3887                                                     SDOperand Op0,
3888                                                     MVT::ValueType DestVT) {
3889  if (Op0.getValueType() == MVT::i32) {
3890    // simple 32-bit [signed|unsigned] integer to float/double expansion
3891
3892    // get the stack frame index of a 8 byte buffer
3893    MachineFunction &MF = DAG.getMachineFunction();
3894    int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3895    // get address of 8 byte buffer
3896    SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3897    // word offset constant for Hi/Lo address computation
3898    SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
3899    // set up Hi and Lo (into buffer) address based on endian
3900    SDOperand Hi = StackSlot;
3901    SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
3902    if (TLI.isLittleEndian())
3903      std::swap(Hi, Lo);
3904
3905    // if signed map to unsigned space
3906    SDOperand Op0Mapped;
3907    if (isSigned) {
3908      // constant used to invert sign bit (signed to unsigned mapping)
3909      SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
3910      Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
3911    } else {
3912      Op0Mapped = Op0;
3913    }
3914    // store the lo of the constructed double - based on integer input
3915    SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3916                                   Op0Mapped, Lo, DAG.getSrcValue(NULL));
3917    // initial hi portion of constructed double
3918    SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
3919    // store the hi of the constructed double - biased exponent
3920    SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
3921                                   InitialHi, Hi, DAG.getSrcValue(NULL));
3922    // load the constructed double
3923    SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
3924                               DAG.getSrcValue(NULL));
3925    // FP constant to bias correct the final result
3926    SDOperand Bias = DAG.getConstantFP(isSigned ?
3927                                            BitsToDouble(0x4330000080000000ULL)
3928                                          : BitsToDouble(0x4330000000000000ULL),
3929                                     MVT::f64);
3930    // subtract the bias
3931    SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
3932    // final result
3933    SDOperand Result;
3934    // handle final rounding
3935    if (DestVT == MVT::f64) {
3936      // do nothing
3937      Result = Sub;
3938    } else {
3939     // if f32 then cast to f32
3940      Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
3941    }
3942    return Result;
3943  }
3944  assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
3945  SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
3946
3947  SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
3948                                   DAG.getConstant(0, Op0.getValueType()),
3949                                   ISD::SETLT);
3950  SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3951  SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3952                                    SignSet, Four, Zero);
3953
3954  // If the sign bit of the integer is set, the large number will be treated
3955  // as a negative number.  To counteract this, the dynamic code adds an
3956  // offset depending on the data type.
3957  uint64_t FF;
3958  switch (Op0.getValueType()) {
3959  default: assert(0 && "Unsupported integer type!");
3960  case MVT::i8 : FF = 0x43800000ULL; break;  // 2^8  (as a float)
3961  case MVT::i16: FF = 0x47800000ULL; break;  // 2^16 (as a float)
3962  case MVT::i32: FF = 0x4F800000ULL; break;  // 2^32 (as a float)
3963  case MVT::i64: FF = 0x5F800000ULL; break;  // 2^64 (as a float)
3964  }
3965  if (TLI.isLittleEndian()) FF <<= 32;
3966  static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3967
3968  SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3969  CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3970  SDOperand FudgeInReg;
3971  if (DestVT == MVT::f32)
3972    FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3973                             DAG.getSrcValue(NULL));
3974  else {
3975    assert(DestVT == MVT::f64 && "Unexpected conversion");
3976    FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
3977                                           DAG.getEntryNode(), CPIdx,
3978                                           DAG.getSrcValue(NULL), MVT::f32));
3979  }
3980
3981  return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
3982}
3983
3984/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
3985/// *INT_TO_FP operation of the specified operand when the target requests that
3986/// we promote it.  At this point, we know that the result and operand types are
3987/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
3988/// operation that takes a larger input.
3989SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
3990                                                      MVT::ValueType DestVT,
3991                                                      bool isSigned) {
3992  // First step, figure out the appropriate *INT_TO_FP operation to use.
3993  MVT::ValueType NewInTy = LegalOp.getValueType();
3994
3995  unsigned OpToUse = 0;
3996
3997  // Scan for the appropriate larger type to use.
3998  while (1) {
3999    NewInTy = (MVT::ValueType)(NewInTy+1);
4000    assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4001
4002    // If the target supports SINT_TO_FP of this type, use it.
4003    switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4004      default: break;
4005      case TargetLowering::Legal:
4006        if (!TLI.isTypeLegal(NewInTy))
4007          break;  // Can't use this datatype.
4008        // FALL THROUGH.
4009      case TargetLowering::Custom:
4010        OpToUse = ISD::SINT_TO_FP;
4011        break;
4012    }
4013    if (OpToUse) break;
4014    if (isSigned) continue;
4015
4016    // If the target supports UINT_TO_FP of this type, use it.
4017    switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4018      default: break;
4019      case TargetLowering::Legal:
4020        if (!TLI.isTypeLegal(NewInTy))
4021          break;  // Can't use this datatype.
4022        // FALL THROUGH.
4023      case TargetLowering::Custom:
4024        OpToUse = ISD::UINT_TO_FP;
4025        break;
4026    }
4027    if (OpToUse) break;
4028
4029    // Otherwise, try a larger type.
4030  }
4031
4032  // Okay, we found the operation and type to use.  Zero extend our input to the
4033  // desired type then run the operation on it.
4034  return DAG.getNode(OpToUse, DestVT,
4035                     DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4036                                 NewInTy, LegalOp));
4037}
4038
4039/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4040/// FP_TO_*INT operation of the specified operand when the target requests that
4041/// we promote it.  At this point, we know that the result and operand types are
4042/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4043/// operation that returns a larger result.
4044SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4045                                                      MVT::ValueType DestVT,
4046                                                      bool isSigned) {
4047  // First step, figure out the appropriate FP_TO*INT operation to use.
4048  MVT::ValueType NewOutTy = DestVT;
4049
4050  unsigned OpToUse = 0;
4051
4052  // Scan for the appropriate larger type to use.
4053  while (1) {
4054    NewOutTy = (MVT::ValueType)(NewOutTy+1);
4055    assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4056
4057    // If the target supports FP_TO_SINT returning this type, use it.
4058    switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4059    default: break;
4060    case TargetLowering::Legal:
4061      if (!TLI.isTypeLegal(NewOutTy))
4062        break;  // Can't use this datatype.
4063      // FALL THROUGH.
4064    case TargetLowering::Custom:
4065      OpToUse = ISD::FP_TO_SINT;
4066      break;
4067    }
4068    if (OpToUse) break;
4069
4070    // If the target supports FP_TO_UINT of this type, use it.
4071    switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4072    default: break;
4073    case TargetLowering::Legal:
4074      if (!TLI.isTypeLegal(NewOutTy))
4075        break;  // Can't use this datatype.
4076      // FALL THROUGH.
4077    case TargetLowering::Custom:
4078      OpToUse = ISD::FP_TO_UINT;
4079      break;
4080    }
4081    if (OpToUse) break;
4082
4083    // Otherwise, try a larger type.
4084  }
4085
4086  // Okay, we found the operation and type to use.  Truncate the result of the
4087  // extended FP_TO_*INT operation to the desired size.
4088  return DAG.getNode(ISD::TRUNCATE, DestVT,
4089                     DAG.getNode(OpToUse, NewOutTy, LegalOp));
4090}
4091
4092/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4093///
4094SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4095  MVT::ValueType VT = Op.getValueType();
4096  MVT::ValueType SHVT = TLI.getShiftAmountTy();
4097  SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4098  switch (VT) {
4099  default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4100  case MVT::i16:
4101    Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4102    Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4103    return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4104  case MVT::i32:
4105    Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4106    Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4107    Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4108    Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4109    Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4110    Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4111    Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4112    Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4113    return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4114  case MVT::i64:
4115    Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4116    Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4117    Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4118    Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4119    Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4120    Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4121    Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4122    Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4123    Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4124    Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4125    Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4126    Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4127    Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4128    Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4129    Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4130    Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4131    Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4132    Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4133    Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4134    Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4135    return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4136  }
4137}
4138
4139/// ExpandBitCount - Expand the specified bitcount instruction into operations.
4140///
4141SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4142  switch (Opc) {
4143  default: assert(0 && "Cannot expand this yet!");
4144  case ISD::CTPOP: {
4145    static const uint64_t mask[6] = {
4146      0x5555555555555555ULL, 0x3333333333333333ULL,
4147      0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4148      0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4149    };
4150    MVT::ValueType VT = Op.getValueType();
4151    MVT::ValueType ShVT = TLI.getShiftAmountTy();
4152    unsigned len = getSizeInBits(VT);
4153    for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4154      //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4155      SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4156      SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4157      Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4158                       DAG.getNode(ISD::AND, VT,
4159                                   DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4160    }
4161    return Op;
4162  }
4163  case ISD::CTLZ: {
4164    // for now, we do this:
4165    // x = x | (x >> 1);
4166    // x = x | (x >> 2);
4167    // ...
4168    // x = x | (x >>16);
4169    // x = x | (x >>32); // for 64-bit input
4170    // return popcount(~x);
4171    //
4172    // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4173    MVT::ValueType VT = Op.getValueType();
4174    MVT::ValueType ShVT = TLI.getShiftAmountTy();
4175    unsigned len = getSizeInBits(VT);
4176    for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4177      SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4178      Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4179    }
4180    Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4181    return DAG.getNode(ISD::CTPOP, VT, Op);
4182  }
4183  case ISD::CTTZ: {
4184    // for now, we use: { return popcount(~x & (x - 1)); }
4185    // unless the target has ctlz but not ctpop, in which case we use:
4186    // { return 32 - nlz(~x & (x-1)); }
4187    // see also http://www.hackersdelight.org/HDcode/ntz.cc
4188    MVT::ValueType VT = Op.getValueType();
4189    SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4190    SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4191                       DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4192                       DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4193    // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4194    if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4195        TLI.isOperationLegal(ISD::CTLZ, VT))
4196      return DAG.getNode(ISD::SUB, VT,
4197                         DAG.getConstant(getSizeInBits(VT), VT),
4198                         DAG.getNode(ISD::CTLZ, VT, Tmp3));
4199    return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4200  }
4201  }
4202}
4203
4204/// ExpandOp - Expand the specified SDOperand into its two component pieces
4205/// Lo&Hi.  Note that the Op MUST be an expanded type.  As a result of this, the
4206/// LegalizeNodes map is filled in for any results that are not expanded, the
4207/// ExpandedNodes map is filled in for any results that are expanded, and the
4208/// Lo/Hi values are returned.
4209void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4210  MVT::ValueType VT = Op.getValueType();
4211  MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4212  SDNode *Node = Op.Val;
4213  assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4214  assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
4215         "Cannot expand FP values!");
4216  assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
4217         "Cannot expand to FP value or to larger int value!");
4218
4219  // See if we already expanded it.
4220  std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4221    = ExpandedNodes.find(Op);
4222  if (I != ExpandedNodes.end()) {
4223    Lo = I->second.first;
4224    Hi = I->second.second;
4225    return;
4226  }
4227
4228  switch (Node->getOpcode()) {
4229  case ISD::CopyFromReg:
4230    assert(0 && "CopyFromReg must be legal!");
4231  default:
4232#ifndef NDEBUG
4233    std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
4234#endif
4235    assert(0 && "Do not know how to expand this operator!");
4236    abort();
4237  case ISD::UNDEF:
4238    Lo = DAG.getNode(ISD::UNDEF, NVT);
4239    Hi = DAG.getNode(ISD::UNDEF, NVT);
4240    break;
4241  case ISD::Constant: {
4242    uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4243    Lo = DAG.getConstant(Cst, NVT);
4244    Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4245    break;
4246  }
4247  case ISD::BUILD_PAIR:
4248    // Return the operands.
4249    Lo = Node->getOperand(0);
4250    Hi = Node->getOperand(1);
4251    break;
4252
4253  case ISD::SIGN_EXTEND_INREG:
4254    ExpandOp(Node->getOperand(0), Lo, Hi);
4255    // Sign extend the lo-part.
4256    Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4257                     DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4258                                     TLI.getShiftAmountTy()));
4259    // sext_inreg the low part if needed.
4260    Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4261    break;
4262
4263  case ISD::BSWAP: {
4264    ExpandOp(Node->getOperand(0), Lo, Hi);
4265    SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4266    Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4267    Lo = TempLo;
4268    break;
4269  }
4270
4271  case ISD::CTPOP:
4272    ExpandOp(Node->getOperand(0), Lo, Hi);
4273    Lo = DAG.getNode(ISD::ADD, NVT,          // ctpop(HL) -> ctpop(H)+ctpop(L)
4274                     DAG.getNode(ISD::CTPOP, NVT, Lo),
4275                     DAG.getNode(ISD::CTPOP, NVT, Hi));
4276    Hi = DAG.getConstant(0, NVT);
4277    break;
4278
4279  case ISD::CTLZ: {
4280    // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4281    ExpandOp(Node->getOperand(0), Lo, Hi);
4282    SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4283    SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4284    SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4285                                        ISD::SETNE);
4286    SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4287    LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4288
4289    Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4290    Hi = DAG.getConstant(0, NVT);
4291    break;
4292  }
4293
4294  case ISD::CTTZ: {
4295    // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4296    ExpandOp(Node->getOperand(0), Lo, Hi);
4297    SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4298    SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4299    SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4300                                        ISD::SETNE);
4301    SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4302    HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4303
4304    Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4305    Hi = DAG.getConstant(0, NVT);
4306    break;
4307  }
4308
4309  case ISD::VAARG: {
4310    SDOperand Ch = Node->getOperand(0);   // Legalize the chain.
4311    SDOperand Ptr = Node->getOperand(1);  // Legalize the pointer.
4312    Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4313    Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4314
4315    // Remember that we legalized the chain.
4316    Hi = LegalizeOp(Hi);
4317    AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4318    if (!TLI.isLittleEndian())
4319      std::swap(Lo, Hi);
4320    break;
4321  }
4322
4323  case ISD::LOAD: {
4324    SDOperand Ch = Node->getOperand(0);   // Legalize the chain.
4325    SDOperand Ptr = Node->getOperand(1);  // Legalize the pointer.
4326    Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4327
4328    // Increment the pointer to the other half.
4329    unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4330    Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4331                      getIntPtrConstant(IncrementSize));
4332    // FIXME: This creates a bogus srcvalue!
4333    Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4334
4335    // Build a factor node to remember that this load is independent of the
4336    // other one.
4337    SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4338                               Hi.getValue(1));
4339
4340    // Remember that we legalized the chain.
4341    AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4342    if (!TLI.isLittleEndian())
4343      std::swap(Lo, Hi);
4344    break;
4345  }
4346  case ISD::AND:
4347  case ISD::OR:
4348  case ISD::XOR: {   // Simple logical operators -> two trivial pieces.
4349    SDOperand LL, LH, RL, RH;
4350    ExpandOp(Node->getOperand(0), LL, LH);
4351    ExpandOp(Node->getOperand(1), RL, RH);
4352    Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4353    Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4354    break;
4355  }
4356  case ISD::SELECT: {
4357    SDOperand LL, LH, RL, RH;
4358    ExpandOp(Node->getOperand(1), LL, LH);
4359    ExpandOp(Node->getOperand(2), RL, RH);
4360    Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4361    Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4362    break;
4363  }
4364  case ISD::SELECT_CC: {
4365    SDOperand TL, TH, FL, FH;
4366    ExpandOp(Node->getOperand(2), TL, TH);
4367    ExpandOp(Node->getOperand(3), FL, FH);
4368    Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4369                     Node->getOperand(1), TL, FL, Node->getOperand(4));
4370    Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4371                     Node->getOperand(1), TH, FH, Node->getOperand(4));
4372    break;
4373  }
4374  case ISD::SEXTLOAD: {
4375    SDOperand Chain = Node->getOperand(0);
4376    SDOperand Ptr   = Node->getOperand(1);
4377    MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4378
4379    if (EVT == NVT)
4380      Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4381    else
4382      Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4383                          EVT);
4384
4385    // Remember that we legalized the chain.
4386    AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4387
4388    // The high part is obtained by SRA'ing all but one of the bits of the lo
4389    // part.
4390    unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4391    Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
4392                                                       TLI.getShiftAmountTy()));
4393    break;
4394  }
4395  case ISD::ZEXTLOAD: {
4396    SDOperand Chain = Node->getOperand(0);
4397    SDOperand Ptr   = Node->getOperand(1);
4398    MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4399
4400    if (EVT == NVT)
4401      Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4402    else
4403      Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4404                          EVT);
4405
4406    // Remember that we legalized the chain.
4407    AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4408
4409    // The high part is just a zero.
4410    Hi = DAG.getConstant(0, NVT);
4411    break;
4412  }
4413  case ISD::EXTLOAD: {
4414    SDOperand Chain = Node->getOperand(0);
4415    SDOperand Ptr   = Node->getOperand(1);
4416    MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4417
4418    if (EVT == NVT)
4419      Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4420    else
4421      Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4422                          EVT);
4423
4424    // Remember that we legalized the chain.
4425    AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4426
4427    // The high part is undefined.
4428    Hi = DAG.getNode(ISD::UNDEF, NVT);
4429    break;
4430  }
4431  case ISD::ANY_EXTEND:
4432    // The low part is any extension of the input (which degenerates to a copy).
4433    Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4434    // The high part is undefined.
4435    Hi = DAG.getNode(ISD::UNDEF, NVT);
4436    break;
4437  case ISD::SIGN_EXTEND: {
4438    // The low part is just a sign extension of the input (which degenerates to
4439    // a copy).
4440    Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4441
4442    // The high part is obtained by SRA'ing all but one of the bits of the lo
4443    // part.
4444    unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4445    Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4446                     DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4447    break;
4448  }
4449  case ISD::ZERO_EXTEND:
4450    // The low part is just a zero extension of the input (which degenerates to
4451    // a copy).
4452    Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4453
4454    // The high part is just a zero.
4455    Hi = DAG.getConstant(0, NVT);
4456    break;
4457
4458  case ISD::BIT_CONVERT: {
4459    SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
4460                                      Node->getOperand(0));
4461    ExpandOp(Tmp, Lo, Hi);
4462    break;
4463  }
4464
4465  case ISD::READCYCLECOUNTER:
4466    assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4467                 TargetLowering::Custom &&
4468           "Must custom expand ReadCycleCounter");
4469    Lo = TLI.LowerOperation(Op, DAG);
4470    assert(Lo.Val && "Node must be custom expanded!");
4471    Hi = Lo.getValue(1);
4472    AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4473                        LegalizeOp(Lo.getValue(2)));
4474    break;
4475
4476    // These operators cannot be expanded directly, emit them as calls to
4477    // library functions.
4478  case ISD::FP_TO_SINT:
4479    if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4480      SDOperand Op;
4481      switch (getTypeAction(Node->getOperand(0).getValueType())) {
4482      case Expand: assert(0 && "cannot expand FP!");
4483      case Legal:   Op = LegalizeOp(Node->getOperand(0)); break;
4484      case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4485      }
4486
4487      Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4488
4489      // Now that the custom expander is done, expand the result, which is still
4490      // VT.
4491      if (Op.Val) {
4492        ExpandOp(Op, Lo, Hi);
4493        break;
4494      }
4495    }
4496
4497    if (Node->getOperand(0).getValueType() == MVT::f32)
4498      Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4499    else
4500      Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4501    break;
4502
4503  case ISD::FP_TO_UINT:
4504    if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4505      SDOperand Op;
4506      switch (getTypeAction(Node->getOperand(0).getValueType())) {
4507        case Expand: assert(0 && "cannot expand FP!");
4508        case Legal:   Op = LegalizeOp(Node->getOperand(0)); break;
4509        case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4510      }
4511
4512      Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4513
4514      // Now that the custom expander is done, expand the result.
4515      if (Op.Val) {
4516        ExpandOp(Op, Lo, Hi);
4517        break;
4518      }
4519    }
4520
4521    if (Node->getOperand(0).getValueType() == MVT::f32)
4522      Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4523    else
4524      Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4525    break;
4526
4527  case ISD::SHL: {
4528    // If the target wants custom lowering, do so.
4529    SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4530    if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4531      SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4532      Op = TLI.LowerOperation(Op, DAG);
4533      if (Op.Val) {
4534        // Now that the custom expander is done, expand the result, which is
4535        // still VT.
4536        ExpandOp(Op, Lo, Hi);
4537        break;
4538      }
4539    }
4540
4541    // If we can emit an efficient shift operation, do so now.
4542    if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4543      break;
4544
4545    // If this target supports SHL_PARTS, use it.
4546    TargetLowering::LegalizeAction Action =
4547      TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4548    if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4549        Action == TargetLowering::Custom) {
4550      ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4551      break;
4552    }
4553
4554    // Otherwise, emit a libcall.
4555    Lo = ExpandLibCall("__ashldi3", Node, Hi);
4556    break;
4557  }
4558
4559  case ISD::SRA: {
4560    // If the target wants custom lowering, do so.
4561    SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4562    if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4563      SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4564      Op = TLI.LowerOperation(Op, DAG);
4565      if (Op.Val) {
4566        // Now that the custom expander is done, expand the result, which is
4567        // still VT.
4568        ExpandOp(Op, Lo, Hi);
4569        break;
4570      }
4571    }
4572
4573    // If we can emit an efficient shift operation, do so now.
4574    if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4575      break;
4576
4577    // If this target supports SRA_PARTS, use it.
4578    TargetLowering::LegalizeAction Action =
4579      TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4580    if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4581        Action == TargetLowering::Custom) {
4582      ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4583      break;
4584    }
4585
4586    // Otherwise, emit a libcall.
4587    Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4588    break;
4589  }
4590
4591  case ISD::SRL: {
4592    // If the target wants custom lowering, do so.
4593    SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4594    if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4595      SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4596      Op = TLI.LowerOperation(Op, DAG);
4597      if (Op.Val) {
4598        // Now that the custom expander is done, expand the result, which is
4599        // still VT.
4600        ExpandOp(Op, Lo, Hi);
4601        break;
4602      }
4603    }
4604
4605    // If we can emit an efficient shift operation, do so now.
4606    if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4607      break;
4608
4609    // If this target supports SRL_PARTS, use it.
4610    TargetLowering::LegalizeAction Action =
4611      TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4612    if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4613        Action == TargetLowering::Custom) {
4614      ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4615      break;
4616    }
4617
4618    // Otherwise, emit a libcall.
4619    Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4620    break;
4621  }
4622
4623  case ISD::ADD:
4624  case ISD::SUB: {
4625    // If the target wants to custom expand this, let them.
4626    if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4627            TargetLowering::Custom) {
4628      Op = TLI.LowerOperation(Op, DAG);
4629      if (Op.Val) {
4630        ExpandOp(Op, Lo, Hi);
4631        break;
4632      }
4633    }
4634
4635    // Expand the subcomponents.
4636    SDOperand LHSL, LHSH, RHSL, RHSH;
4637    ExpandOp(Node->getOperand(0), LHSL, LHSH);
4638    ExpandOp(Node->getOperand(1), RHSL, RHSH);
4639    std::vector<MVT::ValueType> VTs;
4640    SDOperand LoOps[2], HiOps[2];
4641    VTs.push_back(LHSL.getValueType());
4642    VTs.push_back(MVT::Flag);
4643    LoOps[0] = LHSL;
4644    LoOps[1] = RHSL;
4645    HiOps[0] = LHSH;
4646    HiOps[1] = RHSH;
4647    if (Node->getOpcode() == ISD::ADD) {
4648      Lo = DAG.getNode(ISD::ADDC, VTs, LoOps, 2);
4649      HiOps[2] = Lo.getValue(1);
4650      Hi = DAG.getNode(ISD::ADDE, VTs, HiOps, 3);
4651    } else {
4652      Lo = DAG.getNode(ISD::SUBC, VTs, LoOps, 2);
4653      HiOps[2] = Lo.getValue(1);
4654      Hi = DAG.getNode(ISD::SUBE, VTs, HiOps, 3);
4655    }
4656    break;
4657  }
4658  case ISD::MUL: {
4659    if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
4660      SDOperand LL, LH, RL, RH;
4661      ExpandOp(Node->getOperand(0), LL, LH);
4662      ExpandOp(Node->getOperand(1), RL, RH);
4663      unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4664      // MULHS implicitly sign extends its inputs.  Check to see if ExpandOp
4665      // extended the sign bit of the low half through the upper half, and if so
4666      // emit a MULHS instead of the alternate sequence that is valid for any
4667      // i64 x i64 multiply.
4668      if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
4669          // is RH an extension of the sign bit of RL?
4670          RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4671          RH.getOperand(1).getOpcode() == ISD::Constant &&
4672          cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4673          // is LH an extension of the sign bit of LL?
4674          LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4675          LH.getOperand(1).getOpcode() == ISD::Constant &&
4676          cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4677        Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4678      } else {
4679        Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4680        RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4681        LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4682        Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4683        Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4684      }
4685      Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4686    } else {
4687      Lo = ExpandLibCall("__muldi3" , Node, Hi);
4688    }
4689    break;
4690  }
4691  case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4692  case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4693  case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4694  case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4695  }
4696
4697  // Make sure the resultant values have been legalized themselves, unless this
4698  // is a type that requires multi-step expansion.
4699  if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4700    Lo = LegalizeOp(Lo);
4701    Hi = LegalizeOp(Hi);
4702  }
4703
4704  // Remember in a map if the values will be reused later.
4705  bool isNew =
4706    ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4707  assert(isNew && "Value already expanded?!?");
4708}
4709
4710/// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4711/// two smaller values of MVT::Vector type.
4712void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4713                                         SDOperand &Hi) {
4714  assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4715  SDNode *Node = Op.Val;
4716  unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4717  assert(NumElements > 1 && "Cannot split a single element vector!");
4718  unsigned NewNumElts = NumElements/2;
4719  SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4720  SDOperand TypeNode = *(Node->op_end()-1);
4721
4722  // See if we already split it.
4723  std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4724    = SplitNodes.find(Op);
4725  if (I != SplitNodes.end()) {
4726    Lo = I->second.first;
4727    Hi = I->second.second;
4728    return;
4729  }
4730
4731  switch (Node->getOpcode()) {
4732  default:
4733#ifndef NDEBUG
4734    Node->dump();
4735#endif
4736    assert(0 && "Unhandled operation in SplitVectorOp!");
4737  case ISD::VBUILD_VECTOR: {
4738    SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
4739                                    Node->op_begin()+NewNumElts);
4740    LoOps.push_back(NewNumEltsNode);
4741    LoOps.push_back(TypeNode);
4742    Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
4743
4744    SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
4745                                    Node->op_end()-2);
4746    HiOps.push_back(NewNumEltsNode);
4747    HiOps.push_back(TypeNode);
4748    Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
4749    break;
4750  }
4751  case ISD::VADD:
4752  case ISD::VSUB:
4753  case ISD::VMUL:
4754  case ISD::VSDIV:
4755  case ISD::VUDIV:
4756  case ISD::VAND:
4757  case ISD::VOR:
4758  case ISD::VXOR: {
4759    SDOperand LL, LH, RL, RH;
4760    SplitVectorOp(Node->getOperand(0), LL, LH);
4761    SplitVectorOp(Node->getOperand(1), RL, RH);
4762
4763    Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4764                     NewNumEltsNode, TypeNode);
4765    Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4766                     NewNumEltsNode, TypeNode);
4767    break;
4768  }
4769  case ISD::VLOAD: {
4770    SDOperand Ch = Node->getOperand(0);   // Legalize the chain.
4771    SDOperand Ptr = Node->getOperand(1);  // Legalize the pointer.
4772    MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4773
4774    Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4775    unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4776    Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4777                      getIntPtrConstant(IncrementSize));
4778    // FIXME: This creates a bogus srcvalue!
4779    Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4780
4781    // Build a factor node to remember that this load is independent of the
4782    // other one.
4783    SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4784                               Hi.getValue(1));
4785
4786    // Remember that we legalized the chain.
4787    AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4788    break;
4789  }
4790  case ISD::VBIT_CONVERT: {
4791    // We know the result is a vector.  The input may be either a vector or a
4792    // scalar value.
4793    if (Op.getOperand(0).getValueType() != MVT::Vector) {
4794      // Lower to a store/load.  FIXME: this could be improved probably.
4795      SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
4796
4797      SDOperand St = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
4798                                 Op.getOperand(0), Ptr, DAG.getSrcValue(0));
4799      MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4800      St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
4801      SplitVectorOp(St, Lo, Hi);
4802    } else {
4803      // If the input is a vector type, we have to either scalarize it, pack it
4804      // or convert it based on whether the input vector type is legal.
4805      SDNode *InVal = Node->getOperand(0).Val;
4806      unsigned NumElems =
4807        cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4808      MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4809
4810      // If the input is from a single element vector, scalarize the vector,
4811      // then treat like a scalar.
4812      if (NumElems == 1) {
4813        SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
4814        Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
4815                             Op.getOperand(1), Op.getOperand(2));
4816        SplitVectorOp(Scalar, Lo, Hi);
4817      } else {
4818        // Split the input vector.
4819        SplitVectorOp(Op.getOperand(0), Lo, Hi);
4820
4821        // Convert each of the pieces now.
4822        Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
4823                         NewNumEltsNode, TypeNode);
4824        Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
4825                         NewNumEltsNode, TypeNode);
4826      }
4827      break;
4828    }
4829  }
4830  }
4831
4832  // Remember in a map if the values will be reused later.
4833  bool isNew =
4834    SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4835  assert(isNew && "Value already expanded?!?");
4836}
4837
4838
4839/// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
4840/// equivalent operation that returns a scalar (e.g. F32) or packed value
4841/// (e.g. MVT::V4F32).  When this is called, we know that PackedVT is the right
4842/// type for the result.
4843SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
4844                                             MVT::ValueType NewVT) {
4845  assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
4846  SDNode *Node = Op.Val;
4847
4848  // See if we already packed it.
4849  std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
4850  if (I != PackedNodes.end()) return I->second;
4851
4852  SDOperand Result;
4853  switch (Node->getOpcode()) {
4854  default:
4855#ifndef NDEBUG
4856    Node->dump(); std::cerr << "\n";
4857#endif
4858    assert(0 && "Unknown vector operation in PackVectorOp!");
4859  case ISD::VADD:
4860  case ISD::VSUB:
4861  case ISD::VMUL:
4862  case ISD::VSDIV:
4863  case ISD::VUDIV:
4864  case ISD::VAND:
4865  case ISD::VOR:
4866  case ISD::VXOR:
4867    Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
4868                         NewVT,
4869                         PackVectorOp(Node->getOperand(0), NewVT),
4870                         PackVectorOp(Node->getOperand(1), NewVT));
4871    break;
4872  case ISD::VLOAD: {
4873    SDOperand Ch = LegalizeOp(Node->getOperand(0));   // Legalize the chain.
4874    SDOperand Ptr = LegalizeOp(Node->getOperand(1));  // Legalize the pointer.
4875
4876    Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2));
4877
4878    // Remember that we legalized the chain.
4879    AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4880    break;
4881  }
4882  case ISD::VBUILD_VECTOR:
4883    if (Node->getOperand(0).getValueType() == NewVT) {
4884      // Returning a scalar?
4885      Result = Node->getOperand(0);
4886    } else {
4887      // Returning a BUILD_VECTOR?
4888
4889      // If all elements of the build_vector are undefs, return an undef.
4890      bool AllUndef = true;
4891      for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
4892        if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
4893          AllUndef = false;
4894          break;
4895        }
4896      if (AllUndef) {
4897        Result = DAG.getNode(ISD::UNDEF, NewVT);
4898      } else {
4899        Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
4900                             Node->getNumOperands()-2);
4901      }
4902    }
4903    break;
4904  case ISD::VINSERT_VECTOR_ELT:
4905    if (!MVT::isVector(NewVT)) {
4906      // Returning a scalar?  Must be the inserted element.
4907      Result = Node->getOperand(1);
4908    } else {
4909      Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
4910                           PackVectorOp(Node->getOperand(0), NewVT),
4911                           Node->getOperand(1), Node->getOperand(2));
4912    }
4913    break;
4914  case ISD::VVECTOR_SHUFFLE:
4915    if (!MVT::isVector(NewVT)) {
4916      // Returning a scalar?  Figure out if it is the LHS or RHS and return it.
4917      SDOperand EltNum = Node->getOperand(2).getOperand(0);
4918      if (cast<ConstantSDNode>(EltNum)->getValue())
4919        Result = PackVectorOp(Node->getOperand(1), NewVT);
4920      else
4921        Result = PackVectorOp(Node->getOperand(0), NewVT);
4922    } else {
4923      // Otherwise, return a VECTOR_SHUFFLE node.  First convert the index
4924      // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
4925      std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
4926                                         Node->getOperand(2).Val->op_end()-2);
4927      MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
4928      SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
4929                                 Node->getOperand(2).Val->op_begin(),
4930                                 Node->getOperand(2).Val->getNumOperands()-2);
4931
4932      Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
4933                           PackVectorOp(Node->getOperand(0), NewVT),
4934                           PackVectorOp(Node->getOperand(1), NewVT), BV);
4935    }
4936    break;
4937  case ISD::VBIT_CONVERT:
4938    if (Op.getOperand(0).getValueType() != MVT::Vector)
4939      Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
4940    else {
4941      // If the input is a vector type, we have to either scalarize it, pack it
4942      // or convert it based on whether the input vector type is legal.
4943      SDNode *InVal = Node->getOperand(0).Val;
4944      unsigned NumElems =
4945        cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4946      MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4947
4948      // Figure out if there is a Packed type corresponding to this Vector
4949      // type.  If so, convert to the packed type.
4950      MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
4951      if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
4952        // Turn this into a bit convert of the packed input.
4953        Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
4954                             PackVectorOp(Node->getOperand(0), TVT));
4955        break;
4956      } else if (NumElems == 1) {
4957        // Turn this into a bit convert of the scalar input.
4958        Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
4959                             PackVectorOp(Node->getOperand(0), EVT));
4960        break;
4961      } else {
4962        // FIXME: UNIMP!
4963        assert(0 && "Cast from unsupported vector type not implemented yet!");
4964      }
4965    }
4966    break;
4967  case ISD::VSELECT:
4968    Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
4969                         PackVectorOp(Op.getOperand(1), NewVT),
4970                         PackVectorOp(Op.getOperand(2), NewVT));
4971    break;
4972  }
4973
4974  if (TLI.isTypeLegal(NewVT))
4975    Result = LegalizeOp(Result);
4976  bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
4977  assert(isNew && "Value already packed?");
4978  return Result;
4979}
4980
4981
4982// SelectionDAG::Legalize - This is the entry point for the file.
4983//
4984void SelectionDAG::Legalize() {
4985  if (ViewLegalizeDAGs) viewGraph();
4986
4987  /// run - This is the main entry point to this class.
4988  ///
4989  SelectionDAGLegalize(*this).LegalizeDAG();
4990}
4991
4992