LegalizeDAG.cpp revision bee98c66c0c3d1f43244cdf237e572a9df031e40
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetFrameInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/Target/TargetSubtarget.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/SmallPtrSet.h" 35#include <map> 36using namespace llvm; 37 38#ifndef NDEBUG 39static cl::opt<bool> 40ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 41 cl::desc("Pop up a window to show dags before legalize")); 42#else 43static const bool ViewLegalizeDAGs = 0; 44#endif 45 46//===----------------------------------------------------------------------===// 47/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 48/// hacks on it until the target machine can handle it. This involves 49/// eliminating value sizes the machine cannot handle (promoting small sizes to 50/// large sizes or splitting up large values into small values) as well as 51/// eliminating operations the machine cannot handle. 52/// 53/// This code also does a small amount of optimization and recognition of idioms 54/// as part of its processing. For example, if a target does not support a 55/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 56/// will attempt merge setcc and brc instructions into brcc's. 57/// 58namespace { 59class VISIBILITY_HIDDEN SelectionDAGLegalize { 60 TargetLowering &TLI; 61 SelectionDAG &DAG; 62 63 // Libcall insertion helpers. 64 65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 66 /// legalized. We use this to ensure that calls are properly serialized 67 /// against each other, including inserted libcalls. 68 SDOperand LastCALLSEQ_END; 69 70 /// IsLegalizingCall - This member is used *only* for purposes of providing 71 /// helpful assertions that a libcall isn't created while another call is 72 /// being legalized (which could lead to non-serialized call sequences). 73 bool IsLegalizingCall; 74 75 enum LegalizeAction { 76 Legal, // The target natively supports this operation. 77 Promote, // This operation should be executed in a larger type. 78 Expand // Try to expand this to other ops, otherwise use a libcall. 79 }; 80 81 /// ValueTypeActions - This is a bitvector that contains two bits for each 82 /// value type, where the two bits correspond to the LegalizeAction enum. 83 /// This can be queried with "getTypeAction(VT)". 84 TargetLowering::ValueTypeActionImpl ValueTypeActions; 85 86 /// LegalizedNodes - For nodes that are of legal width, and that have more 87 /// than one use, this map indicates what regularized operand to use. This 88 /// allows us to avoid legalizing the same thing more than once. 89 DenseMap<SDOperand, SDOperand> LegalizedNodes; 90 91 /// PromotedNodes - For nodes that are below legal width, and that have more 92 /// than one use, this map indicates what promoted value to use. This allows 93 /// us to avoid promoting the same thing more than once. 94 DenseMap<SDOperand, SDOperand> PromotedNodes; 95 96 /// ExpandedNodes - For nodes that need to be expanded this map indicates 97 /// which which operands are the expanded version of the input. This allows 98 /// us to avoid expanding the same node more than once. 99 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 100 101 /// SplitNodes - For vector nodes that need to be split, this map indicates 102 /// which which operands are the split version of the input. This allows us 103 /// to avoid splitting the same node more than once. 104 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 105 106 /// ScalarizedNodes - For nodes that need to be converted from vector types to 107 /// scalar types, this contains the mapping of ones we have already 108 /// processed to the result. 109 std::map<SDOperand, SDOperand> ScalarizedNodes; 110 111 void AddLegalizedOperand(SDOperand From, SDOperand To) { 112 LegalizedNodes.insert(std::make_pair(From, To)); 113 // If someone requests legalization of the new node, return itself. 114 if (From != To) 115 LegalizedNodes.insert(std::make_pair(To, To)); 116 } 117 void AddPromotedOperand(SDOperand From, SDOperand To) { 118 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 119 assert(isNew && "Got into the map somehow?"); 120 // If someone requests legalization of the new node, return itself. 121 LegalizedNodes.insert(std::make_pair(To, To)); 122 } 123 124public: 125 126 SelectionDAGLegalize(SelectionDAG &DAG); 127 128 /// getTypeAction - Return how we should legalize values of this type, either 129 /// it is already legal or we need to expand it into multiple registers of 130 /// smaller integer type, or we need to promote it to a larger type. 131 LegalizeAction getTypeAction(MVT VT) const { 132 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 133 } 134 135 /// isTypeLegal - Return true if this type is legal on this target. 136 /// 137 bool isTypeLegal(MVT VT) const { 138 return getTypeAction(VT) == Legal; 139 } 140 141 void LegalizeDAG(); 142 143private: 144 /// HandleOp - Legalize, Promote, or Expand the specified operand as 145 /// appropriate for its type. 146 void HandleOp(SDOperand Op); 147 148 /// LegalizeOp - We know that the specified value has a legal type. 149 /// Recursively ensure that the operands have legal types, then return the 150 /// result. 151 SDOperand LegalizeOp(SDOperand O); 152 153 /// UnrollVectorOp - We know that the given vector has a legal type, however 154 /// the operation it performs is not legal and is an operation that we have 155 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 156 /// operating on each element individually. 157 SDOperand UnrollVectorOp(SDOperand O); 158 159 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 160 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 161 /// is necessary to spill the vector being inserted into to memory, perform 162 /// the insert there, and then read the result back. 163 SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, 164 SDOperand Idx); 165 166 /// PromoteOp - Given an operation that produces a value in an invalid type, 167 /// promote it to compute the value into a larger type. The produced value 168 /// will have the correct bits for the low portion of the register, but no 169 /// guarantee is made about the top bits: it may be zero, sign-extended, or 170 /// garbage. 171 SDOperand PromoteOp(SDOperand O); 172 173 /// ExpandOp - Expand the specified SDOperand into its two component pieces 174 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 175 /// the LegalizeNodes map is filled in for any results that are not expanded, 176 /// the ExpandedNodes map is filled in for any results that are expanded, and 177 /// the Lo/Hi values are returned. This applies to integer types and Vector 178 /// types. 179 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 180 181 /// SplitVectorOp - Given an operand of vector type, break it down into 182 /// two smaller values. 183 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 184 185 /// ScalarizeVectorOp - Given an operand of single-element vector type 186 /// (e.g. v1f32), convert it into the equivalent operation that returns a 187 /// scalar (e.g. f32) value. 188 SDOperand ScalarizeVectorOp(SDOperand O); 189 190 /// isShuffleLegal - Return true if a vector shuffle is legal with the 191 /// specified mask and type. Targets can specify exactly which masks they 192 /// support and the code generator is tasked with not creating illegal masks. 193 /// 194 /// Note that this will also return true for shuffles that are promoted to a 195 /// different type. 196 /// 197 /// If this is a legal shuffle, this method returns the (possibly promoted) 198 /// build_vector Mask. If it's not a legal shuffle, it returns null. 199 SDNode *isShuffleLegal(MVT VT, SDOperand Mask) const; 200 201 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 202 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 203 204 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 205 206 SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 207 SDOperand &Hi); 208 SDOperand ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source); 209 210 SDOperand EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT); 211 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 212 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 213 SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT DestVT); 214 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT DestVT, bool isSigned); 215 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT DestVT, bool isSigned); 216 217 SDOperand ExpandBSWAP(SDOperand Op); 218 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 219 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 220 SDOperand &Lo, SDOperand &Hi); 221 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 222 SDOperand &Lo, SDOperand &Hi); 223 224 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 225 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 226}; 227} 228 229/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 230/// specified mask and type. Targets can specify exactly which masks they 231/// support and the code generator is tasked with not creating illegal masks. 232/// 233/// Note that this will also return true for shuffles that are promoted to a 234/// different type. 235SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const { 236 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 237 default: return 0; 238 case TargetLowering::Legal: 239 case TargetLowering::Custom: 240 break; 241 case TargetLowering::Promote: { 242 // If this is promoted to a different type, convert the shuffle mask and 243 // ask if it is legal in the promoted type! 244 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 245 246 // If we changed # elements, change the shuffle mask. 247 unsigned NumEltsGrowth = 248 NVT.getVectorNumElements() / VT.getVectorNumElements(); 249 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 250 if (NumEltsGrowth > 1) { 251 // Renumber the elements. 252 SmallVector<SDOperand, 8> Ops; 253 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 254 SDOperand InOp = Mask.getOperand(i); 255 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 256 if (InOp.getOpcode() == ISD::UNDEF) 257 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 258 else { 259 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 260 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 261 } 262 } 263 } 264 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 265 } 266 VT = NVT; 267 break; 268 } 269 } 270 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 271} 272 273SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 274 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 275 ValueTypeActions(TLI.getValueTypeActions()) { 276 assert(MVT::LAST_VALUETYPE <= 32 && 277 "Too many value types for ValueTypeActions to hold!"); 278} 279 280/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 281/// contains all of a nodes operands before it contains the node. 282static void ComputeTopDownOrdering(SelectionDAG &DAG, 283 SmallVector<SDNode*, 64> &Order) { 284 285 DenseMap<SDNode*, unsigned> Visited; 286 std::vector<SDNode*> Worklist; 287 Worklist.reserve(128); 288 289 // Compute ordering from all of the leaves in the graphs, those (like the 290 // entry node) that have no operands. 291 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 292 E = DAG.allnodes_end(); I != E; ++I) { 293 if (I->getNumOperands() == 0) { 294 Visited[I] = 0 - 1U; 295 Worklist.push_back(I); 296 } 297 } 298 299 while (!Worklist.empty()) { 300 SDNode *N = Worklist.back(); 301 Worklist.pop_back(); 302 303 if (++Visited[N] != N->getNumOperands()) 304 continue; // Haven't visited all operands yet 305 306 Order.push_back(N); 307 308 // Now that we have N in, add anything that uses it if all of their operands 309 // are now done. 310 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 311 UI != E; ++UI) 312 Worklist.push_back(UI->getUser()); 313 } 314 315 assert(Order.size() == Visited.size() && 316 Order.size() == DAG.allnodes_size() && 317 "Error: DAG is cyclic!"); 318} 319 320 321void SelectionDAGLegalize::LegalizeDAG() { 322 LastCALLSEQ_END = DAG.getEntryNode(); 323 IsLegalizingCall = false; 324 325 // The legalize process is inherently a bottom-up recursive process (users 326 // legalize their uses before themselves). Given infinite stack space, we 327 // could just start legalizing on the root and traverse the whole graph. In 328 // practice however, this causes us to run out of stack space on large basic 329 // blocks. To avoid this problem, compute an ordering of the nodes where each 330 // node is only legalized after all of its operands are legalized. 331 SmallVector<SDNode*, 64> Order; 332 ComputeTopDownOrdering(DAG, Order); 333 334 for (unsigned i = 0, e = Order.size(); i != e; ++i) 335 HandleOp(SDOperand(Order[i], 0)); 336 337 // Finally, it's possible the root changed. Get the new root. 338 SDOperand OldRoot = DAG.getRoot(); 339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 340 DAG.setRoot(LegalizedNodes[OldRoot]); 341 342 ExpandedNodes.clear(); 343 LegalizedNodes.clear(); 344 PromotedNodes.clear(); 345 SplitNodes.clear(); 346 ScalarizedNodes.clear(); 347 348 // Remove dead nodes now. 349 DAG.RemoveDeadNodes(); 350} 351 352 353/// FindCallEndFromCallStart - Given a chained node that is part of a call 354/// sequence, find the CALLSEQ_END node that terminates the call sequence. 355static SDNode *FindCallEndFromCallStart(SDNode *Node) { 356 if (Node->getOpcode() == ISD::CALLSEQ_END) 357 return Node; 358 if (Node->use_empty()) 359 return 0; // No CallSeqEnd 360 361 // The chain is usually at the end. 362 SDOperand TheChain(Node, Node->getNumValues()-1); 363 if (TheChain.getValueType() != MVT::Other) { 364 // Sometimes it's at the beginning. 365 TheChain = SDOperand(Node, 0); 366 if (TheChain.getValueType() != MVT::Other) { 367 // Otherwise, hunt for it. 368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 369 if (Node->getValueType(i) == MVT::Other) { 370 TheChain = SDOperand(Node, i); 371 break; 372 } 373 374 // Otherwise, we walked into a node without a chain. 375 if (TheChain.getValueType() != MVT::Other) 376 return 0; 377 } 378 } 379 380 for (SDNode::use_iterator UI = Node->use_begin(), 381 E = Node->use_end(); UI != E; ++UI) { 382 383 // Make sure to only follow users of our token chain. 384 SDNode *User = UI->getUser(); 385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 386 if (User->getOperand(i) == TheChain) 387 if (SDNode *Result = FindCallEndFromCallStart(User)) 388 return Result; 389 } 390 return 0; 391} 392 393/// FindCallStartFromCallEnd - Given a chained node that is part of a call 394/// sequence, find the CALLSEQ_START node that initiates the call sequence. 395static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 396 assert(Node && "Didn't find callseq_start for a call??"); 397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 398 399 assert(Node->getOperand(0).getValueType() == MVT::Other && 400 "Node doesn't have a token chain argument!"); 401 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 402} 403 404/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 405/// see if any uses can reach Dest. If no dest operands can get to dest, 406/// legalize them, legalize ourself, and return false, otherwise, return true. 407/// 408/// Keep track of the nodes we fine that actually do lead to Dest in 409/// NodesLeadingTo. This avoids retraversing them exponential number of times. 410/// 411bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 413 if (N == Dest) return true; // N certainly leads to Dest :) 414 415 // If we've already processed this node and it does lead to Dest, there is no 416 // need to reprocess it. 417 if (NodesLeadingTo.count(N)) return true; 418 419 // If the first result of this node has been already legalized, then it cannot 420 // reach N. 421 switch (getTypeAction(N->getValueType(0))) { 422 case Legal: 423 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 424 break; 425 case Promote: 426 if (PromotedNodes.count(SDOperand(N, 0))) return false; 427 break; 428 case Expand: 429 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 430 break; 431 } 432 433 // Okay, this node has not already been legalized. Check and legalize all 434 // operands. If none lead to Dest, then we can legalize this node. 435 bool OperandsLeadToDest = false; 436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 437 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 439 440 if (OperandsLeadToDest) { 441 NodesLeadingTo.insert(N); 442 return true; 443 } 444 445 // Okay, this node looks safe, legalize it and return false. 446 HandleOp(SDOperand(N, 0)); 447 return false; 448} 449 450/// HandleOp - Legalize, Promote, or Expand the specified operand as 451/// appropriate for its type. 452void SelectionDAGLegalize::HandleOp(SDOperand Op) { 453 MVT VT = Op.getValueType(); 454 switch (getTypeAction(VT)) { 455 default: assert(0 && "Bad type action!"); 456 case Legal: (void)LegalizeOp(Op); break; 457 case Promote: (void)PromoteOp(Op); break; 458 case Expand: 459 if (!VT.isVector()) { 460 // If this is an illegal scalar, expand it into its two component 461 // pieces. 462 SDOperand X, Y; 463 if (Op.getOpcode() == ISD::TargetConstant) 464 break; // Allow illegal target nodes. 465 ExpandOp(Op, X, Y); 466 } else if (VT.getVectorNumElements() == 1) { 467 // If this is an illegal single element vector, convert it to a 468 // scalar operation. 469 (void)ScalarizeVectorOp(Op); 470 } else { 471 // Otherwise, this is an illegal multiple element vector. 472 // Split it in half and legalize both parts. 473 SDOperand X, Y; 474 SplitVectorOp(Op, X, Y); 475 } 476 break; 477 } 478} 479 480/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 481/// a load from the constant pool. 482static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 483 SelectionDAG &DAG, TargetLowering &TLI) { 484 bool Extend = false; 485 486 // If a FP immediate is precise when represented as a float and if the 487 // target can do an extending load from float to double, we put it into 488 // the constant pool as a float, even if it's is statically typed as a 489 // double. This shrinks FP constants and canonicalizes them for targets where 490 // an FP extending load is the same cost as a normal load (such as on the x87 491 // fp stack or PPC FP unit). 492 MVT VT = CFP->getValueType(0); 493 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF()); 494 if (!UseCP) { 495 if (VT!=MVT::f64 && VT!=MVT::f32) 496 assert(0 && "Invalid type expansion"); 497 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(), 498 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 499 } 500 501 MVT OrigVT = VT; 502 MVT SVT = VT; 503 while (SVT != MVT::f32) { 504 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 505 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 506 // Only do this if the target has a native EXTLOAD instruction from 507 // smaller type. 508 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && 509 TLI.ShouldShrinkFPConstant(OrigVT)) { 510 const Type *SType = SVT.getTypeForMVT(); 511 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 512 VT = SVT; 513 Extend = true; 514 } 515 } 516 517 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 518 if (Extend) 519 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), 520 CPIdx, PseudoSourceValue::getConstantPool(), 521 0, VT); 522 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 523 PseudoSourceValue::getConstantPool(), 0); 524} 525 526 527/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 528/// operations. 529static 530SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, 531 SelectionDAG &DAG, TargetLowering &TLI) { 532 MVT VT = Node->getValueType(0); 533 MVT SrcVT = Node->getOperand(1).getValueType(); 534 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 535 "fcopysign expansion only supported for f32 and f64"); 536 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 537 538 // First get the sign bit of second operand. 539 SDOperand Mask1 = (SrcVT == MVT::f64) 540 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 541 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 542 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 543 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 544 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 545 // Shift right or sign-extend it if the two operands have different types. 546 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); 547 if (SizeDiff > 0) { 548 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 549 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 550 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 551 } else if (SizeDiff < 0) 552 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 553 554 // Clear the sign bit of first operand. 555 SDOperand Mask2 = (VT == MVT::f64) 556 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 557 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 558 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 559 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 560 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 561 562 // Or the value with the sign bit. 563 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 564 return Result; 565} 566 567/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 568static 569SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 570 TargetLowering &TLI) { 571 SDOperand Chain = ST->getChain(); 572 SDOperand Ptr = ST->getBasePtr(); 573 SDOperand Val = ST->getValue(); 574 MVT VT = Val.getValueType(); 575 int Alignment = ST->getAlignment(); 576 int SVOffset = ST->getSrcValueOffset(); 577 if (ST->getMemoryVT().isFloatingPoint() || 578 ST->getMemoryVT().isVector()) { 579 // Expand to a bitconvert of the value to the integer type of the 580 // same size, then a (misaligned) int store. 581 MVT intVT; 582 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128) 583 intVT = MVT::i128; 584 else if (VT.is64BitVector() || VT==MVT::f64) 585 intVT = MVT::i64; 586 else if (VT==MVT::f32) 587 intVT = MVT::i32; 588 else 589 assert(0 && "Unaligned store of unsupported type"); 590 591 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 592 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 593 SVOffset, ST->isVolatile(), Alignment); 594 } 595 assert(ST->getMemoryVT().isInteger() && 596 !ST->getMemoryVT().isVector() && 597 "Unaligned store of unknown type."); 598 // Get the half-size VT 599 MVT NewStoredVT = 600 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 601 int NumBits = NewStoredVT.getSizeInBits(); 602 int IncrementSize = NumBits / 8; 603 604 // Divide the stored value in two parts. 605 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 606 SDOperand Lo = Val; 607 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 608 609 // Store the two parts 610 SDOperand Store1, Store2; 611 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 612 ST->getSrcValue(), SVOffset, NewStoredVT, 613 ST->isVolatile(), Alignment); 614 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 615 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 616 Alignment = MinAlign(Alignment, IncrementSize); 617 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 618 ST->getSrcValue(), SVOffset + IncrementSize, 619 NewStoredVT, ST->isVolatile(), Alignment); 620 621 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 622} 623 624/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 625static 626SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 627 TargetLowering &TLI) { 628 int SVOffset = LD->getSrcValueOffset(); 629 SDOperand Chain = LD->getChain(); 630 SDOperand Ptr = LD->getBasePtr(); 631 MVT VT = LD->getValueType(0); 632 MVT LoadedVT = LD->getMemoryVT(); 633 if (VT.isFloatingPoint() || VT.isVector()) { 634 // Expand to a (misaligned) integer load of the same size, 635 // then bitconvert to floating point or vector. 636 MVT intVT; 637 if (LoadedVT.is128BitVector() || 638 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128) 639 intVT = MVT::i128; 640 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64) 641 intVT = MVT::i64; 642 else if (LoadedVT == MVT::f32) 643 intVT = MVT::i32; 644 else 645 assert(0 && "Unaligned load of unsupported type"); 646 647 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 648 SVOffset, LD->isVolatile(), 649 LD->getAlignment()); 650 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 651 if (VT.isFloatingPoint() && LoadedVT != VT) 652 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 653 654 SDOperand Ops[] = { Result, Chain }; 655 return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); 656 } 657 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 658 "Unaligned load of unsupported type."); 659 660 // Compute the new VT that is half the size of the old one. This is an 661 // integer MVT. 662 unsigned NumBits = LoadedVT.getSizeInBits(); 663 MVT NewLoadedVT; 664 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 665 NumBits >>= 1; 666 667 unsigned Alignment = LD->getAlignment(); 668 unsigned IncrementSize = NumBits / 8; 669 ISD::LoadExtType HiExtType = LD->getExtensionType(); 670 671 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 672 if (HiExtType == ISD::NON_EXTLOAD) 673 HiExtType = ISD::ZEXTLOAD; 674 675 // Load the value in two parts 676 SDOperand Lo, Hi; 677 if (TLI.isLittleEndian()) { 678 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 679 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 680 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 681 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 682 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 683 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 684 MinAlign(Alignment, IncrementSize)); 685 } else { 686 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 687 NewLoadedVT,LD->isVolatile(), Alignment); 688 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 689 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 690 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 691 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 692 MinAlign(Alignment, IncrementSize)); 693 } 694 695 // aggregate the two parts 696 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 697 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 698 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 699 700 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 701 Hi.getValue(1)); 702 703 SDOperand Ops[] = { Result, TF }; 704 return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); 705} 706 707/// UnrollVectorOp - We know that the given vector has a legal type, however 708/// the operation it performs is not legal and is an operation that we have 709/// no way of lowering. "Unroll" the vector, splitting out the scalars and 710/// operating on each element individually. 711SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 712 MVT VT = Op.getValueType(); 713 assert(isTypeLegal(VT) && 714 "Caller should expand or promote operands that are not legal!"); 715 assert(Op.Val->getNumValues() == 1 && 716 "Can't unroll a vector with multiple results!"); 717 unsigned NE = VT.getVectorNumElements(); 718 MVT EltVT = VT.getVectorElementType(); 719 720 SmallVector<SDOperand, 8> Scalars; 721 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 722 for (unsigned i = 0; i != NE; ++i) { 723 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 724 SDOperand Operand = Op.getOperand(j); 725 MVT OperandVT = Operand.getValueType(); 726 if (OperandVT.isVector()) { 727 // A vector operand; extract a single element. 728 MVT OperandEltVT = OperandVT.getVectorElementType(); 729 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 730 OperandEltVT, 731 Operand, 732 DAG.getConstant(i, MVT::i32)); 733 } else { 734 // A scalar operand; just use it as is. 735 Operands[j] = Operand; 736 } 737 } 738 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 739 &Operands[0], Operands.size())); 740 } 741 742 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 743} 744 745/// GetFPLibCall - Return the right libcall for the given floating point type. 746static RTLIB::Libcall GetFPLibCall(MVT VT, 747 RTLIB::Libcall Call_F32, 748 RTLIB::Libcall Call_F64, 749 RTLIB::Libcall Call_F80, 750 RTLIB::Libcall Call_PPCF128) { 751 return 752 VT == MVT::f32 ? Call_F32 : 753 VT == MVT::f64 ? Call_F64 : 754 VT == MVT::f80 ? Call_F80 : 755 VT == MVT::ppcf128 ? Call_PPCF128 : 756 RTLIB::UNKNOWN_LIBCALL; 757} 758 759/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 760/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 761/// is necessary to spill the vector being inserted into to memory, perform 762/// the insert there, and then read the result back. 763SDOperand SelectionDAGLegalize:: 764PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) { 765 SDOperand Tmp1 = Vec; 766 SDOperand Tmp2 = Val; 767 SDOperand Tmp3 = Idx; 768 769 // If the target doesn't support this, we have to spill the input vector 770 // to a temporary stack slot, update the element, then reload it. This is 771 // badness. We could also load the value into a vector register (either 772 // with a "move to register" or "extload into register" instruction, then 773 // permute it into place, if the idx is a constant and if the idx is 774 // supported by the target. 775 MVT VT = Tmp1.getValueType(); 776 MVT EltVT = VT.getVectorElementType(); 777 MVT IdxVT = Tmp3.getValueType(); 778 MVT PtrVT = TLI.getPointerTy(); 779 SDOperand StackPtr = DAG.CreateStackTemporary(VT); 780 781 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val); 782 int SPFI = StackPtrFI->getIndex(); 783 784 // Store the vector. 785 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, 786 PseudoSourceValue::getFixedStack(), 787 SPFI); 788 789 // Truncate or zero extend offset to target pointer type. 790 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 791 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 792 // Add the offset to the index. 793 unsigned EltSize = EltVT.getSizeInBits()/8; 794 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 795 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 796 // Store the scalar value. 797 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, 798 PseudoSourceValue::getFixedStack(), SPFI, EltVT); 799 // Load the updated vector. 800 return DAG.getLoad(VT, Ch, StackPtr, PseudoSourceValue::getFixedStack(),SPFI); 801} 802 803/// LegalizeOp - We know that the specified value has a legal type, and 804/// that its operands are legal. Now ensure that the operation itself 805/// is legal, recursively ensuring that the operands' operations remain 806/// legal. 807SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 808 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 809 return Op; 810 811 assert(isTypeLegal(Op.getValueType()) && 812 "Caller should expand or promote operands that are not legal!"); 813 SDNode *Node = Op.Val; 814 815 // If this operation defines any values that cannot be represented in a 816 // register on this target, make sure to expand or promote them. 817 if (Node->getNumValues() > 1) { 818 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 819 if (getTypeAction(Node->getValueType(i)) != Legal) { 820 HandleOp(Op.getValue(i)); 821 assert(LegalizedNodes.count(Op) && 822 "Handling didn't add legal operands!"); 823 return LegalizedNodes[Op]; 824 } 825 } 826 827 // Note that LegalizeOp may be reentered even from single-use nodes, which 828 // means that we always must cache transformed nodes. 829 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 830 if (I != LegalizedNodes.end()) return I->second; 831 832 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 833 SDOperand Result = Op; 834 bool isCustom = false; 835 836 switch (Node->getOpcode()) { 837 case ISD::FrameIndex: 838 case ISD::EntryToken: 839 case ISD::Register: 840 case ISD::BasicBlock: 841 case ISD::TargetFrameIndex: 842 case ISD::TargetJumpTable: 843 case ISD::TargetConstant: 844 case ISD::TargetConstantFP: 845 case ISD::TargetConstantPool: 846 case ISD::TargetGlobalAddress: 847 case ISD::TargetGlobalTLSAddress: 848 case ISD::TargetExternalSymbol: 849 case ISD::VALUETYPE: 850 case ISD::SRCVALUE: 851 case ISD::MEMOPERAND: 852 case ISD::CONDCODE: 853 case ISD::ARG_FLAGS: 854 // Primitives must all be legal. 855 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 856 "This must be legal!"); 857 break; 858 default: 859 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 860 // If this is a target node, legalize it by legalizing the operands then 861 // passing it through. 862 SmallVector<SDOperand, 8> Ops; 863 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 864 Ops.push_back(LegalizeOp(Node->getOperand(i))); 865 866 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 867 868 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 869 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 870 return Result.getValue(Op.ResNo); 871 } 872 // Otherwise this is an unhandled builtin node. splat. 873#ifndef NDEBUG 874 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 875#endif 876 assert(0 && "Do not know how to legalize this operator!"); 877 abort(); 878 case ISD::GLOBAL_OFFSET_TABLE: 879 case ISD::GlobalAddress: 880 case ISD::GlobalTLSAddress: 881 case ISD::ExternalSymbol: 882 case ISD::ConstantPool: 883 case ISD::JumpTable: // Nothing to do. 884 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 885 default: assert(0 && "This action is not supported yet!"); 886 case TargetLowering::Custom: 887 Tmp1 = TLI.LowerOperation(Op, DAG); 888 if (Tmp1.Val) Result = Tmp1; 889 // FALLTHROUGH if the target doesn't want to lower this op after all. 890 case TargetLowering::Legal: 891 break; 892 } 893 break; 894 case ISD::FRAMEADDR: 895 case ISD::RETURNADDR: 896 // The only option for these nodes is to custom lower them. If the target 897 // does not custom lower them, then return zero. 898 Tmp1 = TLI.LowerOperation(Op, DAG); 899 if (Tmp1.Val) 900 Result = Tmp1; 901 else 902 Result = DAG.getConstant(0, TLI.getPointerTy()); 903 break; 904 case ISD::FRAME_TO_ARGS_OFFSET: { 905 MVT VT = Node->getValueType(0); 906 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 907 default: assert(0 && "This action is not supported yet!"); 908 case TargetLowering::Custom: 909 Result = TLI.LowerOperation(Op, DAG); 910 if (Result.Val) break; 911 // Fall Thru 912 case TargetLowering::Legal: 913 Result = DAG.getConstant(0, VT); 914 break; 915 } 916 } 917 break; 918 case ISD::EXCEPTIONADDR: { 919 Tmp1 = LegalizeOp(Node->getOperand(0)); 920 MVT VT = Node->getValueType(0); 921 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 922 default: assert(0 && "This action is not supported yet!"); 923 case TargetLowering::Expand: { 924 unsigned Reg = TLI.getExceptionAddressRegister(); 925 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 926 } 927 break; 928 case TargetLowering::Custom: 929 Result = TLI.LowerOperation(Op, DAG); 930 if (Result.Val) break; 931 // Fall Thru 932 case TargetLowering::Legal: { 933 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 934 Result = DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); 935 break; 936 } 937 } 938 } 939 if (Result.Val->getNumValues() == 1) break; 940 941 assert(Result.Val->getNumValues() == 2 && 942 "Cannot return more than two values!"); 943 944 // Since we produced two values, make sure to remember that we 945 // legalized both of them. 946 Tmp1 = LegalizeOp(Result); 947 Tmp2 = LegalizeOp(Result.getValue(1)); 948 AddLegalizedOperand(Op.getValue(0), Tmp1); 949 AddLegalizedOperand(Op.getValue(1), Tmp2); 950 return Op.ResNo ? Tmp2 : Tmp1; 951 case ISD::EHSELECTION: { 952 Tmp1 = LegalizeOp(Node->getOperand(0)); 953 Tmp2 = LegalizeOp(Node->getOperand(1)); 954 MVT VT = Node->getValueType(0); 955 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 956 default: assert(0 && "This action is not supported yet!"); 957 case TargetLowering::Expand: { 958 unsigned Reg = TLI.getExceptionSelectorRegister(); 959 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 960 } 961 break; 962 case TargetLowering::Custom: 963 Result = TLI.LowerOperation(Op, DAG); 964 if (Result.Val) break; 965 // Fall Thru 966 case TargetLowering::Legal: { 967 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 968 Result = DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); 969 break; 970 } 971 } 972 } 973 if (Result.Val->getNumValues() == 1) break; 974 975 assert(Result.Val->getNumValues() == 2 && 976 "Cannot return more than two values!"); 977 978 // Since we produced two values, make sure to remember that we 979 // legalized both of them. 980 Tmp1 = LegalizeOp(Result); 981 Tmp2 = LegalizeOp(Result.getValue(1)); 982 AddLegalizedOperand(Op.getValue(0), Tmp1); 983 AddLegalizedOperand(Op.getValue(1), Tmp2); 984 return Op.ResNo ? Tmp2 : Tmp1; 985 case ISD::EH_RETURN: { 986 MVT VT = Node->getValueType(0); 987 // The only "good" option for this node is to custom lower it. 988 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 989 default: assert(0 && "This action is not supported at all!"); 990 case TargetLowering::Custom: 991 Result = TLI.LowerOperation(Op, DAG); 992 if (Result.Val) break; 993 // Fall Thru 994 case TargetLowering::Legal: 995 // Target does not know, how to lower this, lower to noop 996 Result = LegalizeOp(Node->getOperand(0)); 997 break; 998 } 999 } 1000 break; 1001 case ISD::AssertSext: 1002 case ISD::AssertZext: 1003 Tmp1 = LegalizeOp(Node->getOperand(0)); 1004 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1005 break; 1006 case ISD::MERGE_VALUES: 1007 // Legalize eliminates MERGE_VALUES nodes. 1008 Result = Node->getOperand(Op.ResNo); 1009 break; 1010 case ISD::CopyFromReg: 1011 Tmp1 = LegalizeOp(Node->getOperand(0)); 1012 Result = Op.getValue(0); 1013 if (Node->getNumValues() == 2) { 1014 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1015 } else { 1016 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 1017 if (Node->getNumOperands() == 3) { 1018 Tmp2 = LegalizeOp(Node->getOperand(2)); 1019 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1020 } else { 1021 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1022 } 1023 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 1024 } 1025 // Since CopyFromReg produces two values, make sure to remember that we 1026 // legalized both of them. 1027 AddLegalizedOperand(Op.getValue(0), Result); 1028 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1029 return Result.getValue(Op.ResNo); 1030 case ISD::UNDEF: { 1031 MVT VT = Op.getValueType(); 1032 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 1033 default: assert(0 && "This action is not supported yet!"); 1034 case TargetLowering::Expand: 1035 if (VT.isInteger()) 1036 Result = DAG.getConstant(0, VT); 1037 else if (VT.isFloatingPoint()) 1038 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), 1039 VT); 1040 else 1041 assert(0 && "Unknown value type!"); 1042 break; 1043 case TargetLowering::Legal: 1044 break; 1045 } 1046 break; 1047 } 1048 1049 case ISD::INTRINSIC_W_CHAIN: 1050 case ISD::INTRINSIC_WO_CHAIN: 1051 case ISD::INTRINSIC_VOID: { 1052 SmallVector<SDOperand, 8> Ops; 1053 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1054 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1055 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1056 1057 // Allow the target to custom lower its intrinsics if it wants to. 1058 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1059 TargetLowering::Custom) { 1060 Tmp3 = TLI.LowerOperation(Result, DAG); 1061 if (Tmp3.Val) Result = Tmp3; 1062 } 1063 1064 if (Result.Val->getNumValues() == 1) break; 1065 1066 // Must have return value and chain result. 1067 assert(Result.Val->getNumValues() == 2 && 1068 "Cannot return more than two values!"); 1069 1070 // Since loads produce two values, make sure to remember that we 1071 // legalized both of them. 1072 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1073 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1074 return Result.getValue(Op.ResNo); 1075 } 1076 1077 case ISD::DBG_STOPPOINT: 1078 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!"); 1079 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1080 1081 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) { 1082 case TargetLowering::Promote: 1083 default: assert(0 && "This action is not supported yet!"); 1084 case TargetLowering::Expand: { 1085 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1086 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1087 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other); 1088 1089 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1090 if (MMI && (useDEBUG_LOC || useLABEL)) { 1091 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit(); 1092 unsigned SrcFile = MMI->RecordSource(CompileUnit); 1093 1094 unsigned Line = DSP->getLine(); 1095 unsigned Col = DSP->getColumn(); 1096 1097 if (useDEBUG_LOC) { 1098 SmallVector<SDOperand, 8> Ops; 1099 Ops.push_back(Tmp1); // chain 1100 Ops.push_back(DAG.getConstant(Line, MVT::i32)); // line # 1101 Ops.push_back(DAG.getConstant(Col, MVT::i32)); // col # 1102 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1103 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1104 } else { 1105 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 1106 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID); 1107 } 1108 } else { 1109 Result = Tmp1; // chain 1110 } 1111 break; 1112 } 1113 case TargetLowering::Legal: 1114 if (Tmp1 != Node->getOperand(0) || 1115 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1116 SmallVector<SDOperand, 8> Ops; 1117 Ops.push_back(Tmp1); 1118 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1119 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1120 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1121 } else { 1122 // Otherwise promote them. 1123 Ops.push_back(PromoteOp(Node->getOperand(1))); 1124 Ops.push_back(PromoteOp(Node->getOperand(2))); 1125 } 1126 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1127 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1128 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1129 } 1130 break; 1131 } 1132 break; 1133 1134 case ISD::DECLARE: 1135 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1136 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1137 default: assert(0 && "This action is not supported yet!"); 1138 case TargetLowering::Legal: 1139 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1140 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1141 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1142 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1143 break; 1144 case TargetLowering::Expand: 1145 Result = LegalizeOp(Node->getOperand(0)); 1146 break; 1147 } 1148 break; 1149 1150 case ISD::DEBUG_LOC: 1151 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1152 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1153 default: assert(0 && "This action is not supported yet!"); 1154 case TargetLowering::Legal: 1155 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1156 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1157 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1158 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1159 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1160 break; 1161 } 1162 break; 1163 1164 case ISD::DBG_LABEL: 1165 case ISD::EH_LABEL: 1166 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!"); 1167 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1168 default: assert(0 && "This action is not supported yet!"); 1169 case TargetLowering::Legal: 1170 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1171 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1172 break; 1173 case TargetLowering::Expand: 1174 Result = LegalizeOp(Node->getOperand(0)); 1175 break; 1176 } 1177 break; 1178 1179 case ISD::PREFETCH: 1180 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1181 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1182 default: assert(0 && "This action is not supported yet!"); 1183 case TargetLowering::Legal: 1184 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1185 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1186 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1187 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1188 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1189 break; 1190 case TargetLowering::Expand: 1191 // It's a noop. 1192 Result = LegalizeOp(Node->getOperand(0)); 1193 break; 1194 } 1195 break; 1196 1197 case ISD::MEMBARRIER: { 1198 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1199 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1200 default: assert(0 && "This action is not supported yet!"); 1201 case TargetLowering::Legal: { 1202 SDOperand Ops[6]; 1203 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1204 for (int x = 1; x < 6; ++x) { 1205 Ops[x] = Node->getOperand(x); 1206 if (!isTypeLegal(Ops[x].getValueType())) 1207 Ops[x] = PromoteOp(Ops[x]); 1208 } 1209 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1210 break; 1211 } 1212 case TargetLowering::Expand: 1213 //There is no libgcc call for this op 1214 Result = Node->getOperand(0); // Noop 1215 break; 1216 } 1217 break; 1218 } 1219 1220 case ISD::ATOMIC_CMP_SWAP: { 1221 unsigned int num_operands = 4; 1222 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1223 SDOperand Ops[4]; 1224 for (unsigned int x = 0; x < num_operands; ++x) 1225 Ops[x] = LegalizeOp(Node->getOperand(x)); 1226 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1227 1228 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1229 default: assert(0 && "This action is not supported yet!"); 1230 case TargetLowering::Custom: 1231 Result = TLI.LowerOperation(Result, DAG); 1232 break; 1233 case TargetLowering::Legal: 1234 break; 1235 } 1236 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1237 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1238 return Result.getValue(Op.ResNo); 1239 } 1240 case ISD::ATOMIC_LOAD_ADD: 1241 case ISD::ATOMIC_LOAD_SUB: 1242 case ISD::ATOMIC_LOAD_AND: 1243 case ISD::ATOMIC_LOAD_OR: 1244 case ISD::ATOMIC_LOAD_XOR: 1245 case ISD::ATOMIC_LOAD_NAND: 1246 case ISD::ATOMIC_LOAD_MIN: 1247 case ISD::ATOMIC_LOAD_MAX: 1248 case ISD::ATOMIC_LOAD_UMIN: 1249 case ISD::ATOMIC_LOAD_UMAX: 1250 case ISD::ATOMIC_SWAP: { 1251 unsigned int num_operands = 3; 1252 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1253 SDOperand Ops[3]; 1254 for (unsigned int x = 0; x < num_operands; ++x) 1255 Ops[x] = LegalizeOp(Node->getOperand(x)); 1256 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1257 1258 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1259 default: assert(0 && "This action is not supported yet!"); 1260 case TargetLowering::Custom: 1261 Result = TLI.LowerOperation(Result, DAG); 1262 break; 1263 case TargetLowering::Expand: 1264 Result = SDOperand(TLI.ExpandOperationResult(Op.Val, DAG),0); 1265 break; 1266 case TargetLowering::Legal: 1267 break; 1268 } 1269 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1270 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1271 return Result.getValue(Op.ResNo); 1272 } 1273 case ISD::Constant: { 1274 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1275 unsigned opAction = 1276 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1277 1278 // We know we don't need to expand constants here, constants only have one 1279 // value and we check that it is fine above. 1280 1281 if (opAction == TargetLowering::Custom) { 1282 Tmp1 = TLI.LowerOperation(Result, DAG); 1283 if (Tmp1.Val) 1284 Result = Tmp1; 1285 } 1286 break; 1287 } 1288 case ISD::ConstantFP: { 1289 // Spill FP immediates to the constant pool if the target cannot directly 1290 // codegen them. Targets often have some immediate values that can be 1291 // efficiently generated into an FP register without a load. We explicitly 1292 // leave these constants as ConstantFP nodes for the target to deal with. 1293 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1294 1295 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1296 default: assert(0 && "This action is not supported yet!"); 1297 case TargetLowering::Legal: 1298 break; 1299 case TargetLowering::Custom: 1300 Tmp3 = TLI.LowerOperation(Result, DAG); 1301 if (Tmp3.Val) { 1302 Result = Tmp3; 1303 break; 1304 } 1305 // FALLTHROUGH 1306 case TargetLowering::Expand: { 1307 // Check to see if this FP immediate is already legal. 1308 bool isLegal = false; 1309 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1310 E = TLI.legal_fpimm_end(); I != E; ++I) { 1311 if (CFP->isExactlyValue(*I)) { 1312 isLegal = true; 1313 break; 1314 } 1315 } 1316 // If this is a legal constant, turn it into a TargetConstantFP node. 1317 if (isLegal) 1318 break; 1319 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1320 } 1321 } 1322 break; 1323 } 1324 case ISD::TokenFactor: 1325 if (Node->getNumOperands() == 2) { 1326 Tmp1 = LegalizeOp(Node->getOperand(0)); 1327 Tmp2 = LegalizeOp(Node->getOperand(1)); 1328 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1329 } else if (Node->getNumOperands() == 3) { 1330 Tmp1 = LegalizeOp(Node->getOperand(0)); 1331 Tmp2 = LegalizeOp(Node->getOperand(1)); 1332 Tmp3 = LegalizeOp(Node->getOperand(2)); 1333 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1334 } else { 1335 SmallVector<SDOperand, 8> Ops; 1336 // Legalize the operands. 1337 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1338 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1339 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1340 } 1341 break; 1342 1343 case ISD::FORMAL_ARGUMENTS: 1344 case ISD::CALL: 1345 // The only option for this is to custom lower it. 1346 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1347 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1348 // A call within a calling sequence must be legalized to something 1349 // other than the normal CALLSEQ_END. Violating this gets Legalize 1350 // into an infinite loop. 1351 assert ((!IsLegalizingCall || 1352 Node->getOpcode() != ISD::CALL || 1353 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) && 1354 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1355 1356 // The number of incoming and outgoing values should match; unless the final 1357 // outgoing value is a flag. 1358 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1359 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1360 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1361 MVT::Flag)) && 1362 "Lowering call/formal_arguments produced unexpected # results!"); 1363 1364 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1365 // remember that we legalized all of them, so it doesn't get relegalized. 1366 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1367 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1368 continue; 1369 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1370 if (Op.ResNo == i) 1371 Tmp2 = Tmp1; 1372 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1373 } 1374 return Tmp2; 1375 case ISD::EXTRACT_SUBREG: { 1376 Tmp1 = LegalizeOp(Node->getOperand(0)); 1377 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1378 assert(idx && "Operand must be a constant"); 1379 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1381 } 1382 break; 1383 case ISD::INSERT_SUBREG: { 1384 Tmp1 = LegalizeOp(Node->getOperand(0)); 1385 Tmp2 = LegalizeOp(Node->getOperand(1)); 1386 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1387 assert(idx && "Operand must be a constant"); 1388 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1389 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1390 } 1391 break; 1392 case ISD::BUILD_VECTOR: 1393 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1394 default: assert(0 && "This action is not supported yet!"); 1395 case TargetLowering::Custom: 1396 Tmp3 = TLI.LowerOperation(Result, DAG); 1397 if (Tmp3.Val) { 1398 Result = Tmp3; 1399 break; 1400 } 1401 // FALLTHROUGH 1402 case TargetLowering::Expand: 1403 Result = ExpandBUILD_VECTOR(Result.Val); 1404 break; 1405 } 1406 break; 1407 case ISD::INSERT_VECTOR_ELT: 1408 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1409 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1410 1411 // The type of the value to insert may not be legal, even though the vector 1412 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1413 // here. 1414 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1415 default: assert(0 && "Cannot expand insert element operand"); 1416 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1417 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1418 } 1419 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1420 1421 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1422 Node->getValueType(0))) { 1423 default: assert(0 && "This action is not supported yet!"); 1424 case TargetLowering::Legal: 1425 break; 1426 case TargetLowering::Custom: 1427 Tmp4 = TLI.LowerOperation(Result, DAG); 1428 if (Tmp4.Val) { 1429 Result = Tmp4; 1430 break; 1431 } 1432 // FALLTHROUGH 1433 case TargetLowering::Expand: { 1434 // If the insert index is a constant, codegen this as a scalar_to_vector, 1435 // then a shuffle that inserts it into the right position in the vector. 1436 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1437 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1438 // match the element type of the vector being created. 1439 if (Tmp2.getValueType() == 1440 Op.getValueType().getVectorElementType()) { 1441 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1442 Tmp1.getValueType(), Tmp2); 1443 1444 unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); 1445 MVT ShufMaskVT = 1446 MVT::getIntVectorWithNumElements(NumElts); 1447 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); 1448 1449 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1450 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1451 // elt 0 of the RHS. 1452 SmallVector<SDOperand, 8> ShufOps; 1453 for (unsigned i = 0; i != NumElts; ++i) { 1454 if (i != InsertPos->getValue()) 1455 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1456 else 1457 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1458 } 1459 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1460 &ShufOps[0], ShufOps.size()); 1461 1462 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1463 Tmp1, ScVec, ShufMask); 1464 Result = LegalizeOp(Result); 1465 break; 1466 } 1467 } 1468 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3); 1469 break; 1470 } 1471 } 1472 break; 1473 case ISD::SCALAR_TO_VECTOR: 1474 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1475 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1476 break; 1477 } 1478 1479 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1480 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1481 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1482 Node->getValueType(0))) { 1483 default: assert(0 && "This action is not supported yet!"); 1484 case TargetLowering::Legal: 1485 break; 1486 case TargetLowering::Custom: 1487 Tmp3 = TLI.LowerOperation(Result, DAG); 1488 if (Tmp3.Val) { 1489 Result = Tmp3; 1490 break; 1491 } 1492 // FALLTHROUGH 1493 case TargetLowering::Expand: 1494 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1495 break; 1496 } 1497 break; 1498 case ISD::VECTOR_SHUFFLE: 1499 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1500 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1501 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1502 1503 // Allow targets to custom lower the SHUFFLEs they support. 1504 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1505 default: assert(0 && "Unknown operation action!"); 1506 case TargetLowering::Legal: 1507 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1508 "vector shuffle should not be created if not legal!"); 1509 break; 1510 case TargetLowering::Custom: 1511 Tmp3 = TLI.LowerOperation(Result, DAG); 1512 if (Tmp3.Val) { 1513 Result = Tmp3; 1514 break; 1515 } 1516 // FALLTHROUGH 1517 case TargetLowering::Expand: { 1518 MVT VT = Node->getValueType(0); 1519 MVT EltVT = VT.getVectorElementType(); 1520 MVT PtrVT = TLI.getPointerTy(); 1521 SDOperand Mask = Node->getOperand(2); 1522 unsigned NumElems = Mask.getNumOperands(); 1523 SmallVector<SDOperand,8> Ops; 1524 for (unsigned i = 0; i != NumElems; ++i) { 1525 SDOperand Arg = Mask.getOperand(i); 1526 if (Arg.getOpcode() == ISD::UNDEF) { 1527 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1528 } else { 1529 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1530 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1531 if (Idx < NumElems) 1532 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1533 DAG.getConstant(Idx, PtrVT))); 1534 else 1535 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1536 DAG.getConstant(Idx - NumElems, PtrVT))); 1537 } 1538 } 1539 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1540 break; 1541 } 1542 case TargetLowering::Promote: { 1543 // Change base type to a different vector type. 1544 MVT OVT = Node->getValueType(0); 1545 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1546 1547 // Cast the two input vectors. 1548 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1549 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1550 1551 // Convert the shuffle mask to the right # elements. 1552 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1553 assert(Tmp3.Val && "Shuffle not legal?"); 1554 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1555 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1556 break; 1557 } 1558 } 1559 break; 1560 1561 case ISD::EXTRACT_VECTOR_ELT: 1562 Tmp1 = Node->getOperand(0); 1563 Tmp2 = LegalizeOp(Node->getOperand(1)); 1564 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1565 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1566 break; 1567 1568 case ISD::EXTRACT_SUBVECTOR: 1569 Tmp1 = Node->getOperand(0); 1570 Tmp2 = LegalizeOp(Node->getOperand(1)); 1571 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1572 Result = ExpandEXTRACT_SUBVECTOR(Result); 1573 break; 1574 1575 case ISD::CALLSEQ_START: { 1576 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1577 1578 // Recursively Legalize all of the inputs of the call end that do not lead 1579 // to this call start. This ensures that any libcalls that need be inserted 1580 // are inserted *before* the CALLSEQ_START. 1581 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1582 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1583 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1584 NodesLeadingTo); 1585 } 1586 1587 // Now that we legalized all of the inputs (which may have inserted 1588 // libcalls) create the new CALLSEQ_START node. 1589 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1590 1591 // Merge in the last call, to ensure that this call start after the last 1592 // call ended. 1593 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1594 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1595 Tmp1 = LegalizeOp(Tmp1); 1596 } 1597 1598 // Do not try to legalize the target-specific arguments (#1+). 1599 if (Tmp1 != Node->getOperand(0)) { 1600 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1601 Ops[0] = Tmp1; 1602 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1603 } 1604 1605 // Remember that the CALLSEQ_START is legalized. 1606 AddLegalizedOperand(Op.getValue(0), Result); 1607 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1608 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1609 1610 // Now that the callseq_start and all of the non-call nodes above this call 1611 // sequence have been legalized, legalize the call itself. During this 1612 // process, no libcalls can/will be inserted, guaranteeing that no calls 1613 // can overlap. 1614 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1615 // Note that we are selecting this call! 1616 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1617 IsLegalizingCall = true; 1618 1619 // Legalize the call, starting from the CALLSEQ_END. 1620 LegalizeOp(LastCALLSEQ_END); 1621 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1622 return Result; 1623 } 1624 case ISD::CALLSEQ_END: 1625 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1626 // will cause this node to be legalized as well as handling libcalls right. 1627 if (LastCALLSEQ_END.Val != Node) { 1628 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1629 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1630 assert(I != LegalizedNodes.end() && 1631 "Legalizing the call start should have legalized this node!"); 1632 return I->second; 1633 } 1634 1635 // Otherwise, the call start has been legalized and everything is going 1636 // according to plan. Just legalize ourselves normally here. 1637 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1638 // Do not try to legalize the target-specific arguments (#1+), except for 1639 // an optional flag input. 1640 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1641 if (Tmp1 != Node->getOperand(0)) { 1642 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1643 Ops[0] = Tmp1; 1644 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1645 } 1646 } else { 1647 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1648 if (Tmp1 != Node->getOperand(0) || 1649 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1650 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1651 Ops[0] = Tmp1; 1652 Ops.back() = Tmp2; 1653 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1654 } 1655 } 1656 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1657 // This finishes up call legalization. 1658 IsLegalizingCall = false; 1659 1660 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1661 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1662 if (Node->getNumValues() == 2) 1663 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1664 return Result.getValue(Op.ResNo); 1665 case ISD::DYNAMIC_STACKALLOC: { 1666 MVT VT = Node->getValueType(0); 1667 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1668 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1669 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1670 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1671 1672 Tmp1 = Result.getValue(0); 1673 Tmp2 = Result.getValue(1); 1674 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1675 default: assert(0 && "This action is not supported yet!"); 1676 case TargetLowering::Expand: { 1677 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1678 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1679 " not tell us which reg is the stack pointer!"); 1680 SDOperand Chain = Tmp1.getOperand(0); 1681 1682 // Chain the dynamic stack allocation so that it doesn't modify the stack 1683 // pointer when other instructions are using the stack. 1684 Chain = DAG.getCALLSEQ_START(Chain, 1685 DAG.getConstant(0, TLI.getPointerTy())); 1686 1687 SDOperand Size = Tmp2.getOperand(1); 1688 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1689 Chain = SP.getValue(1); 1690 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1691 unsigned StackAlign = 1692 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1693 if (Align > StackAlign) 1694 SP = DAG.getNode(ISD::AND, VT, SP, 1695 DAG.getConstant(-(uint64_t)Align, VT)); 1696 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1697 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1698 1699 Tmp2 = 1700 DAG.getCALLSEQ_END(Chain, 1701 DAG.getConstant(0, TLI.getPointerTy()), 1702 DAG.getConstant(0, TLI.getPointerTy()), 1703 SDOperand()); 1704 1705 Tmp1 = LegalizeOp(Tmp1); 1706 Tmp2 = LegalizeOp(Tmp2); 1707 break; 1708 } 1709 case TargetLowering::Custom: 1710 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1711 if (Tmp3.Val) { 1712 Tmp1 = LegalizeOp(Tmp3); 1713 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1714 } 1715 break; 1716 case TargetLowering::Legal: 1717 break; 1718 } 1719 // Since this op produce two values, make sure to remember that we 1720 // legalized both of them. 1721 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1722 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1723 return Op.ResNo ? Tmp2 : Tmp1; 1724 } 1725 case ISD::INLINEASM: { 1726 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1727 bool Changed = false; 1728 // Legalize all of the operands of the inline asm, in case they are nodes 1729 // that need to be expanded or something. Note we skip the asm string and 1730 // all of the TargetConstant flags. 1731 SDOperand Op = LegalizeOp(Ops[0]); 1732 Changed = Op != Ops[0]; 1733 Ops[0] = Op; 1734 1735 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1736 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1737 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1738 for (++i; NumVals; ++i, --NumVals) { 1739 SDOperand Op = LegalizeOp(Ops[i]); 1740 if (Op != Ops[i]) { 1741 Changed = true; 1742 Ops[i] = Op; 1743 } 1744 } 1745 } 1746 1747 if (HasInFlag) { 1748 Op = LegalizeOp(Ops.back()); 1749 Changed |= Op != Ops.back(); 1750 Ops.back() = Op; 1751 } 1752 1753 if (Changed) 1754 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1755 1756 // INLINE asm returns a chain and flag, make sure to add both to the map. 1757 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1758 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1759 return Result.getValue(Op.ResNo); 1760 } 1761 case ISD::BR: 1762 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1763 // Ensure that libcalls are emitted before a branch. 1764 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1765 Tmp1 = LegalizeOp(Tmp1); 1766 LastCALLSEQ_END = DAG.getEntryNode(); 1767 1768 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1769 break; 1770 case ISD::BRIND: 1771 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1772 // Ensure that libcalls are emitted before a branch. 1773 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1774 Tmp1 = LegalizeOp(Tmp1); 1775 LastCALLSEQ_END = DAG.getEntryNode(); 1776 1777 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1778 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1779 case Legal: 1780 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1781 break; 1782 } 1783 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1784 break; 1785 case ISD::BR_JT: 1786 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1787 // Ensure that libcalls are emitted before a branch. 1788 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1789 Tmp1 = LegalizeOp(Tmp1); 1790 LastCALLSEQ_END = DAG.getEntryNode(); 1791 1792 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1793 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1794 1795 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1796 default: assert(0 && "This action is not supported yet!"); 1797 case TargetLowering::Legal: break; 1798 case TargetLowering::Custom: 1799 Tmp1 = TLI.LowerOperation(Result, DAG); 1800 if (Tmp1.Val) Result = Tmp1; 1801 break; 1802 case TargetLowering::Expand: { 1803 SDOperand Chain = Result.getOperand(0); 1804 SDOperand Table = Result.getOperand(1); 1805 SDOperand Index = Result.getOperand(2); 1806 1807 MVT PTy = TLI.getPointerTy(); 1808 MachineFunction &MF = DAG.getMachineFunction(); 1809 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1810 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1811 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1812 1813 SDOperand LD; 1814 switch (EntrySize) { 1815 default: assert(0 && "Size of jump table not supported yet."); break; 1816 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, 1817 PseudoSourceValue::getJumpTable(), 0); break; 1818 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, 1819 PseudoSourceValue::getJumpTable(), 0); break; 1820 } 1821 1822 Addr = LD; 1823 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1824 // For PIC, the sequence is: 1825 // BRIND(load(Jumptable + index) + RelocBase) 1826 // RelocBase can be JumpTable, GOT or some sort of global base. 1827 if (PTy != MVT::i32) 1828 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1829 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1830 TLI.getPICJumpTableRelocBase(Table, DAG)); 1831 } 1832 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1833 } 1834 } 1835 break; 1836 case ISD::BRCOND: 1837 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1838 // Ensure that libcalls are emitted before a return. 1839 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1840 Tmp1 = LegalizeOp(Tmp1); 1841 LastCALLSEQ_END = DAG.getEntryNode(); 1842 1843 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1844 case Expand: assert(0 && "It's impossible to expand bools"); 1845 case Legal: 1846 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1847 break; 1848 case Promote: { 1849 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1850 1851 // The top bits of the promoted condition are not necessarily zero, ensure 1852 // that the value is properly zero extended. 1853 unsigned BitWidth = Tmp2.getValueSizeInBits(); 1854 if (!DAG.MaskedValueIsZero(Tmp2, 1855 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 1856 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1857 break; 1858 } 1859 } 1860 1861 // Basic block destination (Op#2) is always legal. 1862 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1863 1864 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1865 default: assert(0 && "This action is not supported yet!"); 1866 case TargetLowering::Legal: break; 1867 case TargetLowering::Custom: 1868 Tmp1 = TLI.LowerOperation(Result, DAG); 1869 if (Tmp1.Val) Result = Tmp1; 1870 break; 1871 case TargetLowering::Expand: 1872 // Expand brcond's setcc into its constituent parts and create a BR_CC 1873 // Node. 1874 if (Tmp2.getOpcode() == ISD::SETCC) { 1875 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1876 Tmp2.getOperand(0), Tmp2.getOperand(1), 1877 Node->getOperand(2)); 1878 } else { 1879 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1880 DAG.getCondCode(ISD::SETNE), Tmp2, 1881 DAG.getConstant(0, Tmp2.getValueType()), 1882 Node->getOperand(2)); 1883 } 1884 break; 1885 } 1886 break; 1887 case ISD::BR_CC: 1888 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1889 // Ensure that libcalls are emitted before a branch. 1890 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1891 Tmp1 = LegalizeOp(Tmp1); 1892 Tmp2 = Node->getOperand(2); // LHS 1893 Tmp3 = Node->getOperand(3); // RHS 1894 Tmp4 = Node->getOperand(1); // CC 1895 1896 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1897 LastCALLSEQ_END = DAG.getEntryNode(); 1898 1899 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1900 // the LHS is a legal SETCC itself. In this case, we need to compare 1901 // the result against zero to select between true and false values. 1902 if (Tmp3.Val == 0) { 1903 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1904 Tmp4 = DAG.getCondCode(ISD::SETNE); 1905 } 1906 1907 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1908 Node->getOperand(4)); 1909 1910 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1911 default: assert(0 && "Unexpected action for BR_CC!"); 1912 case TargetLowering::Legal: break; 1913 case TargetLowering::Custom: 1914 Tmp4 = TLI.LowerOperation(Result, DAG); 1915 if (Tmp4.Val) Result = Tmp4; 1916 break; 1917 } 1918 break; 1919 case ISD::LOAD: { 1920 LoadSDNode *LD = cast<LoadSDNode>(Node); 1921 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1922 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1923 1924 ISD::LoadExtType ExtType = LD->getExtensionType(); 1925 if (ExtType == ISD::NON_EXTLOAD) { 1926 MVT VT = Node->getValueType(0); 1927 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1928 Tmp3 = Result.getValue(0); 1929 Tmp4 = Result.getValue(1); 1930 1931 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1932 default: assert(0 && "This action is not supported yet!"); 1933 case TargetLowering::Legal: 1934 // If this is an unaligned load and the target doesn't support it, 1935 // expand it. 1936 if (!TLI.allowsUnalignedMemoryAccesses()) { 1937 unsigned ABIAlignment = TLI.getTargetData()-> 1938 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 1939 if (LD->getAlignment() < ABIAlignment){ 1940 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1941 TLI); 1942 Tmp3 = Result.getOperand(0); 1943 Tmp4 = Result.getOperand(1); 1944 Tmp3 = LegalizeOp(Tmp3); 1945 Tmp4 = LegalizeOp(Tmp4); 1946 } 1947 } 1948 break; 1949 case TargetLowering::Custom: 1950 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1951 if (Tmp1.Val) { 1952 Tmp3 = LegalizeOp(Tmp1); 1953 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1954 } 1955 break; 1956 case TargetLowering::Promote: { 1957 // Only promote a load of vector type to another. 1958 assert(VT.isVector() && "Cannot promote this load!"); 1959 // Change base type to a different vector type. 1960 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1961 1962 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1963 LD->getSrcValueOffset(), 1964 LD->isVolatile(), LD->getAlignment()); 1965 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1966 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1967 break; 1968 } 1969 } 1970 // Since loads produce two values, make sure to remember that we 1971 // legalized both of them. 1972 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1973 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1974 return Op.ResNo ? Tmp4 : Tmp3; 1975 } else { 1976 MVT SrcVT = LD->getMemoryVT(); 1977 unsigned SrcWidth = SrcVT.getSizeInBits(); 1978 int SVOffset = LD->getSrcValueOffset(); 1979 unsigned Alignment = LD->getAlignment(); 1980 bool isVolatile = LD->isVolatile(); 1981 1982 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1983 // Some targets pretend to have an i1 loading operation, and actually 1984 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1985 // bits are guaranteed to be zero; it helps the optimizers understand 1986 // that these bits are zero. It is also useful for EXTLOAD, since it 1987 // tells the optimizers that those bits are undefined. It would be 1988 // nice to have an effective generic way of getting these benefits... 1989 // Until such a way is found, don't insist on promoting i1 here. 1990 (SrcVT != MVT::i1 || 1991 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1992 // Promote to a byte-sized load if not loading an integral number of 1993 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1994 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1995 MVT NVT = MVT::getIntegerVT(NewWidth); 1996 SDOperand Ch; 1997 1998 // The extra bits are guaranteed to be zero, since we stored them that 1999 // way. A zext load from NVT thus automatically gives zext from SrcVT. 2000 2001 ISD::LoadExtType NewExtType = 2002 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2003 2004 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 2005 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2006 NVT, isVolatile, Alignment); 2007 2008 Ch = Result.getValue(1); // The chain. 2009 2010 if (ExtType == ISD::SEXTLOAD) 2011 // Having the top bits zero doesn't help when sign extending. 2012 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2013 Result, DAG.getValueType(SrcVT)); 2014 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2015 // All the top bits are guaranteed to be zero - inform the optimizers. 2016 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 2017 DAG.getValueType(SrcVT)); 2018 2019 Tmp1 = LegalizeOp(Result); 2020 Tmp2 = LegalizeOp(Ch); 2021 } else if (SrcWidth & (SrcWidth - 1)) { 2022 // If not loading a power-of-2 number of bits, expand as two loads. 2023 assert(SrcVT.isExtended() && !SrcVT.isVector() && 2024 "Unsupported extload!"); 2025 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2026 assert(RoundWidth < SrcWidth); 2027 unsigned ExtraWidth = SrcWidth - RoundWidth; 2028 assert(ExtraWidth < RoundWidth); 2029 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2030 "Load size not an integral number of bytes!"); 2031 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2032 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2033 SDOperand Lo, Hi, Ch; 2034 unsigned IncrementSize; 2035 2036 if (TLI.isLittleEndian()) { 2037 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2038 // Load the bottom RoundWidth bits. 2039 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2040 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2041 Alignment); 2042 2043 // Load the remaining ExtraWidth bits. 2044 IncrementSize = RoundWidth / 8; 2045 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2046 DAG.getIntPtrConstant(IncrementSize)); 2047 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2048 LD->getSrcValue(), SVOffset + IncrementSize, 2049 ExtraVT, isVolatile, 2050 MinAlign(Alignment, IncrementSize)); 2051 2052 // Build a factor node to remember that this load is independent of the 2053 // other one. 2054 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2055 Hi.getValue(1)); 2056 2057 // Move the top bits to the right place. 2058 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2059 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2060 2061 // Join the hi and lo parts. 2062 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2063 } else { 2064 // Big endian - avoid unaligned loads. 2065 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2066 // Load the top RoundWidth bits. 2067 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2068 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2069 Alignment); 2070 2071 // Load the remaining ExtraWidth bits. 2072 IncrementSize = RoundWidth / 8; 2073 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2074 DAG.getIntPtrConstant(IncrementSize)); 2075 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2076 LD->getSrcValue(), SVOffset + IncrementSize, 2077 ExtraVT, isVolatile, 2078 MinAlign(Alignment, IncrementSize)); 2079 2080 // Build a factor node to remember that this load is independent of the 2081 // other one. 2082 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2083 Hi.getValue(1)); 2084 2085 // Move the top bits to the right place. 2086 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2087 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2088 2089 // Join the hi and lo parts. 2090 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2091 } 2092 2093 Tmp1 = LegalizeOp(Result); 2094 Tmp2 = LegalizeOp(Ch); 2095 } else { 2096 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 2097 default: assert(0 && "This action is not supported yet!"); 2098 case TargetLowering::Custom: 2099 isCustom = true; 2100 // FALLTHROUGH 2101 case TargetLowering::Legal: 2102 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2103 Tmp1 = Result.getValue(0); 2104 Tmp2 = Result.getValue(1); 2105 2106 if (isCustom) { 2107 Tmp3 = TLI.LowerOperation(Result, DAG); 2108 if (Tmp3.Val) { 2109 Tmp1 = LegalizeOp(Tmp3); 2110 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2111 } 2112 } else { 2113 // If this is an unaligned load and the target doesn't support it, 2114 // expand it. 2115 if (!TLI.allowsUnalignedMemoryAccesses()) { 2116 unsigned ABIAlignment = TLI.getTargetData()-> 2117 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2118 if (LD->getAlignment() < ABIAlignment){ 2119 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 2120 TLI); 2121 Tmp1 = Result.getOperand(0); 2122 Tmp2 = Result.getOperand(1); 2123 Tmp1 = LegalizeOp(Tmp1); 2124 Tmp2 = LegalizeOp(Tmp2); 2125 } 2126 } 2127 } 2128 break; 2129 case TargetLowering::Expand: 2130 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2131 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2132 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2133 LD->getSrcValueOffset(), 2134 LD->isVolatile(), LD->getAlignment()); 2135 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2136 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2137 Tmp2 = LegalizeOp(Load.getValue(1)); 2138 break; 2139 } 2140 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2141 // Turn the unsupported load into an EXTLOAD followed by an explicit 2142 // zero/sign extend inreg. 2143 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2144 Tmp1, Tmp2, LD->getSrcValue(), 2145 LD->getSrcValueOffset(), SrcVT, 2146 LD->isVolatile(), LD->getAlignment()); 2147 SDOperand ValRes; 2148 if (ExtType == ISD::SEXTLOAD) 2149 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2150 Result, DAG.getValueType(SrcVT)); 2151 else 2152 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2153 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2154 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2155 break; 2156 } 2157 } 2158 2159 // Since loads produce two values, make sure to remember that we legalized 2160 // both of them. 2161 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2162 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2163 return Op.ResNo ? Tmp2 : Tmp1; 2164 } 2165 } 2166 case ISD::EXTRACT_ELEMENT: { 2167 MVT OpTy = Node->getOperand(0).getValueType(); 2168 switch (getTypeAction(OpTy)) { 2169 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2170 case Legal: 2171 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 2172 // 1 -> Hi 2173 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2174 DAG.getConstant(OpTy.getSizeInBits()/2, 2175 TLI.getShiftAmountTy())); 2176 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2177 } else { 2178 // 0 -> Lo 2179 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2180 Node->getOperand(0)); 2181 } 2182 break; 2183 case Expand: 2184 // Get both the low and high parts. 2185 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2186 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 2187 Result = Tmp2; // 1 -> Hi 2188 else 2189 Result = Tmp1; // 0 -> Lo 2190 break; 2191 } 2192 break; 2193 } 2194 2195 case ISD::CopyToReg: 2196 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2197 2198 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2199 "Register type must be legal!"); 2200 // Legalize the incoming value (must be a legal type). 2201 Tmp2 = LegalizeOp(Node->getOperand(2)); 2202 if (Node->getNumValues() == 1) { 2203 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2204 } else { 2205 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2206 if (Node->getNumOperands() == 4) { 2207 Tmp3 = LegalizeOp(Node->getOperand(3)); 2208 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2209 Tmp3); 2210 } else { 2211 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2212 } 2213 2214 // Since this produces two values, make sure to remember that we legalized 2215 // both of them. 2216 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2217 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2218 return Result; 2219 } 2220 break; 2221 2222 case ISD::RET: 2223 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2224 2225 // Ensure that libcalls are emitted before a return. 2226 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2227 Tmp1 = LegalizeOp(Tmp1); 2228 LastCALLSEQ_END = DAG.getEntryNode(); 2229 2230 switch (Node->getNumOperands()) { 2231 case 3: // ret val 2232 Tmp2 = Node->getOperand(1); 2233 Tmp3 = Node->getOperand(2); // Signness 2234 switch (getTypeAction(Tmp2.getValueType())) { 2235 case Legal: 2236 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2237 break; 2238 case Expand: 2239 if (!Tmp2.getValueType().isVector()) { 2240 SDOperand Lo, Hi; 2241 ExpandOp(Tmp2, Lo, Hi); 2242 2243 // Big endian systems want the hi reg first. 2244 if (TLI.isBigEndian()) 2245 std::swap(Lo, Hi); 2246 2247 if (Hi.Val) 2248 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2249 else 2250 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2251 Result = LegalizeOp(Result); 2252 } else { 2253 SDNode *InVal = Tmp2.Val; 2254 int InIx = Tmp2.ResNo; 2255 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 2256 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 2257 2258 // Figure out if there is a simple type corresponding to this Vector 2259 // type. If so, convert to the vector type. 2260 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2261 if (TLI.isTypeLegal(TVT)) { 2262 // Turn this into a return of the vector type. 2263 Tmp2 = LegalizeOp(Tmp2); 2264 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2265 } else if (NumElems == 1) { 2266 // Turn this into a return of the scalar type. 2267 Tmp2 = ScalarizeVectorOp(Tmp2); 2268 Tmp2 = LegalizeOp(Tmp2); 2269 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2270 2271 // FIXME: Returns of gcc generic vectors smaller than a legal type 2272 // should be returned in integer registers! 2273 2274 // The scalarized value type may not be legal, e.g. it might require 2275 // promotion or expansion. Relegalize the return. 2276 Result = LegalizeOp(Result); 2277 } else { 2278 // FIXME: Returns of gcc generic vectors larger than a legal vector 2279 // type should be returned by reference! 2280 SDOperand Lo, Hi; 2281 SplitVectorOp(Tmp2, Lo, Hi); 2282 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2283 Result = LegalizeOp(Result); 2284 } 2285 } 2286 break; 2287 case Promote: 2288 Tmp2 = PromoteOp(Node->getOperand(1)); 2289 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2290 Result = LegalizeOp(Result); 2291 break; 2292 } 2293 break; 2294 case 1: // ret void 2295 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2296 break; 2297 default: { // ret <values> 2298 SmallVector<SDOperand, 8> NewValues; 2299 NewValues.push_back(Tmp1); 2300 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2301 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2302 case Legal: 2303 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2304 NewValues.push_back(Node->getOperand(i+1)); 2305 break; 2306 case Expand: { 2307 SDOperand Lo, Hi; 2308 assert(!Node->getOperand(i).getValueType().isExtended() && 2309 "FIXME: TODO: implement returning non-legal vector types!"); 2310 ExpandOp(Node->getOperand(i), Lo, Hi); 2311 NewValues.push_back(Lo); 2312 NewValues.push_back(Node->getOperand(i+1)); 2313 if (Hi.Val) { 2314 NewValues.push_back(Hi); 2315 NewValues.push_back(Node->getOperand(i+1)); 2316 } 2317 break; 2318 } 2319 case Promote: 2320 assert(0 && "Can't promote multiple return value yet!"); 2321 } 2322 2323 if (NewValues.size() == Node->getNumOperands()) 2324 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2325 else 2326 Result = DAG.getNode(ISD::RET, MVT::Other, 2327 &NewValues[0], NewValues.size()); 2328 break; 2329 } 2330 } 2331 2332 if (Result.getOpcode() == ISD::RET) { 2333 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2334 default: assert(0 && "This action is not supported yet!"); 2335 case TargetLowering::Legal: break; 2336 case TargetLowering::Custom: 2337 Tmp1 = TLI.LowerOperation(Result, DAG); 2338 if (Tmp1.Val) Result = Tmp1; 2339 break; 2340 } 2341 } 2342 break; 2343 case ISD::STORE: { 2344 StoreSDNode *ST = cast<StoreSDNode>(Node); 2345 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2346 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2347 int SVOffset = ST->getSrcValueOffset(); 2348 unsigned Alignment = ST->getAlignment(); 2349 bool isVolatile = ST->isVolatile(); 2350 2351 if (!ST->isTruncatingStore()) { 2352 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2353 // FIXME: We shouldn't do this for TargetConstantFP's. 2354 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2355 // to phase ordering between legalized code and the dag combiner. This 2356 // probably means that we need to integrate dag combiner and legalizer 2357 // together. 2358 // We generally can't do this one for long doubles. 2359 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2360 if (CFP->getValueType(0) == MVT::f32 && 2361 getTypeAction(MVT::i32) == Legal) { 2362 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2363 convertToAPInt().zextOrTrunc(32), 2364 MVT::i32); 2365 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2366 SVOffset, isVolatile, Alignment); 2367 break; 2368 } else if (CFP->getValueType(0) == MVT::f64) { 2369 // If this target supports 64-bit registers, do a single 64-bit store. 2370 if (getTypeAction(MVT::i64) == Legal) { 2371 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2372 zextOrTrunc(64), MVT::i64); 2373 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2374 SVOffset, isVolatile, Alignment); 2375 break; 2376 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 2377 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2378 // stores. If the target supports neither 32- nor 64-bits, this 2379 // xform is certainly not worth it. 2380 const APInt &IntVal =CFP->getValueAPF().convertToAPInt(); 2381 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2382 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2383 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2384 2385 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2386 SVOffset, isVolatile, Alignment); 2387 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2388 DAG.getIntPtrConstant(4)); 2389 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2390 isVolatile, MinAlign(Alignment, 4U)); 2391 2392 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2393 break; 2394 } 2395 } 2396 } 2397 2398 switch (getTypeAction(ST->getMemoryVT())) { 2399 case Legal: { 2400 Tmp3 = LegalizeOp(ST->getValue()); 2401 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2402 ST->getOffset()); 2403 2404 MVT VT = Tmp3.getValueType(); 2405 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2406 default: assert(0 && "This action is not supported yet!"); 2407 case TargetLowering::Legal: 2408 // If this is an unaligned store and the target doesn't support it, 2409 // expand it. 2410 if (!TLI.allowsUnalignedMemoryAccesses()) { 2411 unsigned ABIAlignment = TLI.getTargetData()-> 2412 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2413 if (ST->getAlignment() < ABIAlignment) 2414 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2415 TLI); 2416 } 2417 break; 2418 case TargetLowering::Custom: 2419 Tmp1 = TLI.LowerOperation(Result, DAG); 2420 if (Tmp1.Val) Result = Tmp1; 2421 break; 2422 case TargetLowering::Promote: 2423 assert(VT.isVector() && "Unknown legal promote case!"); 2424 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2425 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2426 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2427 ST->getSrcValue(), SVOffset, isVolatile, 2428 Alignment); 2429 break; 2430 } 2431 break; 2432 } 2433 case Promote: 2434 // Truncate the value and store the result. 2435 Tmp3 = PromoteOp(ST->getValue()); 2436 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2437 SVOffset, ST->getMemoryVT(), 2438 isVolatile, Alignment); 2439 break; 2440 2441 case Expand: 2442 unsigned IncrementSize = 0; 2443 SDOperand Lo, Hi; 2444 2445 // If this is a vector type, then we have to calculate the increment as 2446 // the product of the element size in bytes, and the number of elements 2447 // in the high half of the vector. 2448 if (ST->getValue().getValueType().isVector()) { 2449 SDNode *InVal = ST->getValue().Val; 2450 int InIx = ST->getValue().ResNo; 2451 MVT InVT = InVal->getValueType(InIx); 2452 unsigned NumElems = InVT.getVectorNumElements(); 2453 MVT EVT = InVT.getVectorElementType(); 2454 2455 // Figure out if there is a simple type corresponding to this Vector 2456 // type. If so, convert to the vector type. 2457 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2458 if (TLI.isTypeLegal(TVT)) { 2459 // Turn this into a normal store of the vector type. 2460 Tmp3 = LegalizeOp(ST->getValue()); 2461 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2462 SVOffset, isVolatile, Alignment); 2463 Result = LegalizeOp(Result); 2464 break; 2465 } else if (NumElems == 1) { 2466 // Turn this into a normal store of the scalar type. 2467 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2468 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2469 SVOffset, isVolatile, Alignment); 2470 // The scalarized value type may not be legal, e.g. it might require 2471 // promotion or expansion. Relegalize the scalar store. 2472 Result = LegalizeOp(Result); 2473 break; 2474 } else { 2475 SplitVectorOp(ST->getValue(), Lo, Hi); 2476 IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() * 2477 EVT.getSizeInBits()/8; 2478 } 2479 } else { 2480 ExpandOp(ST->getValue(), Lo, Hi); 2481 IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0; 2482 2483 if (TLI.isBigEndian()) 2484 std::swap(Lo, Hi); 2485 } 2486 2487 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2488 SVOffset, isVolatile, Alignment); 2489 2490 if (Hi.Val == NULL) { 2491 // Must be int <-> float one-to-one expansion. 2492 Result = Lo; 2493 break; 2494 } 2495 2496 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2497 DAG.getIntPtrConstant(IncrementSize)); 2498 assert(isTypeLegal(Tmp2.getValueType()) && 2499 "Pointers must be legal!"); 2500 SVOffset += IncrementSize; 2501 Alignment = MinAlign(Alignment, IncrementSize); 2502 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2503 SVOffset, isVolatile, Alignment); 2504 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2505 break; 2506 } 2507 } else { 2508 switch (getTypeAction(ST->getValue().getValueType())) { 2509 case Legal: 2510 Tmp3 = LegalizeOp(ST->getValue()); 2511 break; 2512 case Promote: 2513 // We can promote the value, the truncstore will still take care of it. 2514 Tmp3 = PromoteOp(ST->getValue()); 2515 break; 2516 case Expand: 2517 // Just store the low part. This may become a non-trunc store, so make 2518 // sure to use getTruncStore, not UpdateNodeOperands below. 2519 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2520 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2521 SVOffset, MVT::i8, isVolatile, Alignment); 2522 } 2523 2524 MVT StVT = ST->getMemoryVT(); 2525 unsigned StWidth = StVT.getSizeInBits(); 2526 2527 if (StWidth != StVT.getStoreSizeInBits()) { 2528 // Promote to a byte-sized store with upper bits zero if not 2529 // storing an integral number of bytes. For example, promote 2530 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2531 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 2532 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2533 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2534 SVOffset, NVT, isVolatile, Alignment); 2535 } else if (StWidth & (StWidth - 1)) { 2536 // If not storing a power-of-2 number of bits, expand as two stores. 2537 assert(StVT.isExtended() && !StVT.isVector() && 2538 "Unsupported truncstore!"); 2539 unsigned RoundWidth = 1 << Log2_32(StWidth); 2540 assert(RoundWidth < StWidth); 2541 unsigned ExtraWidth = StWidth - RoundWidth; 2542 assert(ExtraWidth < RoundWidth); 2543 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2544 "Store size not an integral number of bytes!"); 2545 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2546 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2547 SDOperand Lo, Hi; 2548 unsigned IncrementSize; 2549 2550 if (TLI.isLittleEndian()) { 2551 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2552 // Store the bottom RoundWidth bits. 2553 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2554 SVOffset, RoundVT, 2555 isVolatile, Alignment); 2556 2557 // Store the remaining ExtraWidth bits. 2558 IncrementSize = RoundWidth / 8; 2559 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2560 DAG.getIntPtrConstant(IncrementSize)); 2561 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2562 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2563 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2564 SVOffset + IncrementSize, ExtraVT, isVolatile, 2565 MinAlign(Alignment, IncrementSize)); 2566 } else { 2567 // Big endian - avoid unaligned stores. 2568 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2569 // Store the top RoundWidth bits. 2570 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2571 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2572 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2573 RoundVT, isVolatile, Alignment); 2574 2575 // Store the remaining ExtraWidth bits. 2576 IncrementSize = RoundWidth / 8; 2577 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2578 DAG.getIntPtrConstant(IncrementSize)); 2579 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2580 SVOffset + IncrementSize, ExtraVT, isVolatile, 2581 MinAlign(Alignment, IncrementSize)); 2582 } 2583 2584 // The order of the stores doesn't matter. 2585 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2586 } else { 2587 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2588 Tmp2 != ST->getBasePtr()) 2589 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2590 ST->getOffset()); 2591 2592 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2593 default: assert(0 && "This action is not supported yet!"); 2594 case TargetLowering::Legal: 2595 // If this is an unaligned store and the target doesn't support it, 2596 // expand it. 2597 if (!TLI.allowsUnalignedMemoryAccesses()) { 2598 unsigned ABIAlignment = TLI.getTargetData()-> 2599 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2600 if (ST->getAlignment() < ABIAlignment) 2601 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2602 TLI); 2603 } 2604 break; 2605 case TargetLowering::Custom: 2606 Result = TLI.LowerOperation(Result, DAG); 2607 break; 2608 case Expand: 2609 // TRUNCSTORE:i16 i32 -> STORE i16 2610 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2611 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2612 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2613 isVolatile, Alignment); 2614 break; 2615 } 2616 } 2617 } 2618 break; 2619 } 2620 case ISD::PCMARKER: 2621 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2622 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2623 break; 2624 case ISD::STACKSAVE: 2625 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2626 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2627 Tmp1 = Result.getValue(0); 2628 Tmp2 = Result.getValue(1); 2629 2630 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2631 default: assert(0 && "This action is not supported yet!"); 2632 case TargetLowering::Legal: break; 2633 case TargetLowering::Custom: 2634 Tmp3 = TLI.LowerOperation(Result, DAG); 2635 if (Tmp3.Val) { 2636 Tmp1 = LegalizeOp(Tmp3); 2637 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2638 } 2639 break; 2640 case TargetLowering::Expand: 2641 // Expand to CopyFromReg if the target set 2642 // StackPointerRegisterToSaveRestore. 2643 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2644 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2645 Node->getValueType(0)); 2646 Tmp2 = Tmp1.getValue(1); 2647 } else { 2648 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2649 Tmp2 = Node->getOperand(0); 2650 } 2651 break; 2652 } 2653 2654 // Since stacksave produce two values, make sure to remember that we 2655 // legalized both of them. 2656 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2657 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2658 return Op.ResNo ? Tmp2 : Tmp1; 2659 2660 case ISD::STACKRESTORE: 2661 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2662 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2663 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2664 2665 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2666 default: assert(0 && "This action is not supported yet!"); 2667 case TargetLowering::Legal: break; 2668 case TargetLowering::Custom: 2669 Tmp1 = TLI.LowerOperation(Result, DAG); 2670 if (Tmp1.Val) Result = Tmp1; 2671 break; 2672 case TargetLowering::Expand: 2673 // Expand to CopyToReg if the target set 2674 // StackPointerRegisterToSaveRestore. 2675 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2676 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2677 } else { 2678 Result = Tmp1; 2679 } 2680 break; 2681 } 2682 break; 2683 2684 case ISD::READCYCLECOUNTER: 2685 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2686 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2687 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2688 Node->getValueType(0))) { 2689 default: assert(0 && "This action is not supported yet!"); 2690 case TargetLowering::Legal: 2691 Tmp1 = Result.getValue(0); 2692 Tmp2 = Result.getValue(1); 2693 break; 2694 case TargetLowering::Custom: 2695 Result = TLI.LowerOperation(Result, DAG); 2696 Tmp1 = LegalizeOp(Result.getValue(0)); 2697 Tmp2 = LegalizeOp(Result.getValue(1)); 2698 break; 2699 } 2700 2701 // Since rdcc produce two values, make sure to remember that we legalized 2702 // both of them. 2703 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2704 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2705 return Result; 2706 2707 case ISD::SELECT: 2708 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2709 case Expand: assert(0 && "It's impossible to expand bools"); 2710 case Legal: 2711 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2712 break; 2713 case Promote: { 2714 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2715 // Make sure the condition is either zero or one. 2716 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2717 if (!DAG.MaskedValueIsZero(Tmp1, 2718 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2719 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2720 break; 2721 } 2722 } 2723 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2724 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2725 2726 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2727 2728 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2729 default: assert(0 && "This action is not supported yet!"); 2730 case TargetLowering::Legal: break; 2731 case TargetLowering::Custom: { 2732 Tmp1 = TLI.LowerOperation(Result, DAG); 2733 if (Tmp1.Val) Result = Tmp1; 2734 break; 2735 } 2736 case TargetLowering::Expand: 2737 if (Tmp1.getOpcode() == ISD::SETCC) { 2738 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2739 Tmp2, Tmp3, 2740 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2741 } else { 2742 Result = DAG.getSelectCC(Tmp1, 2743 DAG.getConstant(0, Tmp1.getValueType()), 2744 Tmp2, Tmp3, ISD::SETNE); 2745 } 2746 break; 2747 case TargetLowering::Promote: { 2748 MVT NVT = 2749 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2750 unsigned ExtOp, TruncOp; 2751 if (Tmp2.getValueType().isVector()) { 2752 ExtOp = ISD::BIT_CONVERT; 2753 TruncOp = ISD::BIT_CONVERT; 2754 } else if (Tmp2.getValueType().isInteger()) { 2755 ExtOp = ISD::ANY_EXTEND; 2756 TruncOp = ISD::TRUNCATE; 2757 } else { 2758 ExtOp = ISD::FP_EXTEND; 2759 TruncOp = ISD::FP_ROUND; 2760 } 2761 // Promote each of the values to the new type. 2762 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2763 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2764 // Perform the larger operation, then round down. 2765 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2766 if (TruncOp != ISD::FP_ROUND) 2767 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2768 else 2769 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2770 DAG.getIntPtrConstant(0)); 2771 break; 2772 } 2773 } 2774 break; 2775 case ISD::SELECT_CC: { 2776 Tmp1 = Node->getOperand(0); // LHS 2777 Tmp2 = Node->getOperand(1); // RHS 2778 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2779 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2780 SDOperand CC = Node->getOperand(4); 2781 2782 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2783 2784 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2785 // the LHS is a legal SETCC itself. In this case, we need to compare 2786 // the result against zero to select between true and false values. 2787 if (Tmp2.Val == 0) { 2788 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2789 CC = DAG.getCondCode(ISD::SETNE); 2790 } 2791 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2792 2793 // Everything is legal, see if we should expand this op or something. 2794 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2795 default: assert(0 && "This action is not supported yet!"); 2796 case TargetLowering::Legal: break; 2797 case TargetLowering::Custom: 2798 Tmp1 = TLI.LowerOperation(Result, DAG); 2799 if (Tmp1.Val) Result = Tmp1; 2800 break; 2801 } 2802 break; 2803 } 2804 case ISD::SETCC: 2805 Tmp1 = Node->getOperand(0); 2806 Tmp2 = Node->getOperand(1); 2807 Tmp3 = Node->getOperand(2); 2808 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2809 2810 // If we had to Expand the SetCC operands into a SELECT node, then it may 2811 // not always be possible to return a true LHS & RHS. In this case, just 2812 // return the value we legalized, returned in the LHS 2813 if (Tmp2.Val == 0) { 2814 Result = Tmp1; 2815 break; 2816 } 2817 2818 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2819 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2820 case TargetLowering::Custom: 2821 isCustom = true; 2822 // FALLTHROUGH. 2823 case TargetLowering::Legal: 2824 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2825 if (isCustom) { 2826 Tmp4 = TLI.LowerOperation(Result, DAG); 2827 if (Tmp4.Val) Result = Tmp4; 2828 } 2829 break; 2830 case TargetLowering::Promote: { 2831 // First step, figure out the appropriate operation to use. 2832 // Allow SETCC to not be supported for all legal data types 2833 // Mostly this targets FP 2834 MVT NewInTy = Node->getOperand(0).getValueType(); 2835 MVT OldVT = NewInTy; OldVT = OldVT; 2836 2837 // Scan for the appropriate larger type to use. 2838 while (1) { 2839 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 2840 2841 assert(NewInTy.isInteger() == OldVT.isInteger() && 2842 "Fell off of the edge of the integer world"); 2843 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 2844 "Fell off of the edge of the floating point world"); 2845 2846 // If the target supports SETCC of this type, use it. 2847 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2848 break; 2849 } 2850 if (NewInTy.isInteger()) 2851 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2852 else { 2853 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2854 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2855 } 2856 Tmp1 = LegalizeOp(Tmp1); 2857 Tmp2 = LegalizeOp(Tmp2); 2858 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2859 Result = LegalizeOp(Result); 2860 break; 2861 } 2862 case TargetLowering::Expand: 2863 // Expand a setcc node into a select_cc of the same condition, lhs, and 2864 // rhs that selects between const 1 (true) and const 0 (false). 2865 MVT VT = Node->getValueType(0); 2866 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2867 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2868 Tmp3); 2869 break; 2870 } 2871 break; 2872 case ISD::VSETCC: { 2873 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2874 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2875 SDOperand CC = Node->getOperand(2); 2876 2877 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC); 2878 2879 // Everything is legal, see if we should expand this op or something. 2880 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) { 2881 default: assert(0 && "This action is not supported yet!"); 2882 case TargetLowering::Legal: break; 2883 case TargetLowering::Custom: 2884 Tmp1 = TLI.LowerOperation(Result, DAG); 2885 if (Tmp1.Val) Result = Tmp1; 2886 break; 2887 } 2888 break; 2889 } 2890 2891 case ISD::SHL_PARTS: 2892 case ISD::SRA_PARTS: 2893 case ISD::SRL_PARTS: { 2894 SmallVector<SDOperand, 8> Ops; 2895 bool Changed = false; 2896 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2897 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2898 Changed |= Ops.back() != Node->getOperand(i); 2899 } 2900 if (Changed) 2901 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2902 2903 switch (TLI.getOperationAction(Node->getOpcode(), 2904 Node->getValueType(0))) { 2905 default: assert(0 && "This action is not supported yet!"); 2906 case TargetLowering::Legal: break; 2907 case TargetLowering::Custom: 2908 Tmp1 = TLI.LowerOperation(Result, DAG); 2909 if (Tmp1.Val) { 2910 SDOperand Tmp2, RetVal(0, 0); 2911 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2912 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2913 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2914 if (i == Op.ResNo) 2915 RetVal = Tmp2; 2916 } 2917 assert(RetVal.Val && "Illegal result number"); 2918 return RetVal; 2919 } 2920 break; 2921 } 2922 2923 // Since these produce multiple values, make sure to remember that we 2924 // legalized all of them. 2925 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2926 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2927 return Result.getValue(Op.ResNo); 2928 } 2929 2930 // Binary operators 2931 case ISD::ADD: 2932 case ISD::SUB: 2933 case ISD::MUL: 2934 case ISD::MULHS: 2935 case ISD::MULHU: 2936 case ISD::UDIV: 2937 case ISD::SDIV: 2938 case ISD::AND: 2939 case ISD::OR: 2940 case ISD::XOR: 2941 case ISD::SHL: 2942 case ISD::SRL: 2943 case ISD::SRA: 2944 case ISD::FADD: 2945 case ISD::FSUB: 2946 case ISD::FMUL: 2947 case ISD::FDIV: 2948 case ISD::FPOW: 2949 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2950 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2951 case Expand: assert(0 && "Not possible"); 2952 case Legal: 2953 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2954 break; 2955 case Promote: 2956 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2957 break; 2958 } 2959 2960 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2961 2962 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2963 default: assert(0 && "BinOp legalize operation not supported"); 2964 case TargetLowering::Legal: break; 2965 case TargetLowering::Custom: 2966 Tmp1 = TLI.LowerOperation(Result, DAG); 2967 if (Tmp1.Val) Result = Tmp1; 2968 break; 2969 case TargetLowering::Expand: { 2970 MVT VT = Op.getValueType(); 2971 2972 // See if multiply or divide can be lowered using two-result operations. 2973 SDVTList VTs = DAG.getVTList(VT, VT); 2974 if (Node->getOpcode() == ISD::MUL) { 2975 // We just need the low half of the multiply; try both the signed 2976 // and unsigned forms. If the target supports both SMUL_LOHI and 2977 // UMUL_LOHI, form a preference by checking which forms of plain 2978 // MULH it supports. 2979 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2980 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2981 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2982 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2983 unsigned OpToUse = 0; 2984 if (HasSMUL_LOHI && !HasMULHS) { 2985 OpToUse = ISD::SMUL_LOHI; 2986 } else if (HasUMUL_LOHI && !HasMULHU) { 2987 OpToUse = ISD::UMUL_LOHI; 2988 } else if (HasSMUL_LOHI) { 2989 OpToUse = ISD::SMUL_LOHI; 2990 } else if (HasUMUL_LOHI) { 2991 OpToUse = ISD::UMUL_LOHI; 2992 } 2993 if (OpToUse) { 2994 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 2995 break; 2996 } 2997 } 2998 if (Node->getOpcode() == ISD::MULHS && 2999 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 3000 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3001 break; 3002 } 3003 if (Node->getOpcode() == ISD::MULHU && 3004 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 3005 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3006 break; 3007 } 3008 if (Node->getOpcode() == ISD::SDIV && 3009 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3010 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3011 break; 3012 } 3013 if (Node->getOpcode() == ISD::UDIV && 3014 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3015 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3016 break; 3017 } 3018 3019 // Check to see if we have a libcall for this operator. 3020 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3021 bool isSigned = false; 3022 switch (Node->getOpcode()) { 3023 case ISD::UDIV: 3024 case ISD::SDIV: 3025 if (VT == MVT::i32) { 3026 LC = Node->getOpcode() == ISD::UDIV 3027 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3028 isSigned = Node->getOpcode() == ISD::SDIV; 3029 } 3030 break; 3031 case ISD::FPOW: 3032 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3033 RTLIB::POW_PPCF128); 3034 break; 3035 default: break; 3036 } 3037 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3038 SDOperand Dummy; 3039 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3040 break; 3041 } 3042 3043 assert(Node->getValueType(0).isVector() && 3044 "Cannot expand this binary operator!"); 3045 // Expand the operation into a bunch of nasty scalar code. 3046 Result = LegalizeOp(UnrollVectorOp(Op)); 3047 break; 3048 } 3049 case TargetLowering::Promote: { 3050 switch (Node->getOpcode()) { 3051 default: assert(0 && "Do not know how to promote this BinOp!"); 3052 case ISD::AND: 3053 case ISD::OR: 3054 case ISD::XOR: { 3055 MVT OVT = Node->getValueType(0); 3056 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3057 assert(OVT.isVector() && "Cannot promote this BinOp!"); 3058 // Bit convert each of the values to the new type. 3059 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3060 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3061 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3062 // Bit convert the result back the original type. 3063 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3064 break; 3065 } 3066 } 3067 } 3068 } 3069 break; 3070 3071 case ISD::SMUL_LOHI: 3072 case ISD::UMUL_LOHI: 3073 case ISD::SDIVREM: 3074 case ISD::UDIVREM: 3075 // These nodes will only be produced by target-specific lowering, so 3076 // they shouldn't be here if they aren't legal. 3077 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3078 "This must be legal!"); 3079 3080 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3081 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3082 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3083 break; 3084 3085 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3086 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3087 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3088 case Expand: assert(0 && "Not possible"); 3089 case Legal: 3090 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3091 break; 3092 case Promote: 3093 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3094 break; 3095 } 3096 3097 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3098 3099 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3100 default: assert(0 && "Operation not supported"); 3101 case TargetLowering::Custom: 3102 Tmp1 = TLI.LowerOperation(Result, DAG); 3103 if (Tmp1.Val) Result = Tmp1; 3104 break; 3105 case TargetLowering::Legal: break; 3106 case TargetLowering::Expand: { 3107 // If this target supports fabs/fneg natively and select is cheap, 3108 // do this efficiently. 3109 if (!TLI.isSelectExpensive() && 3110 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3111 TargetLowering::Legal && 3112 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3113 TargetLowering::Legal) { 3114 // Get the sign bit of the RHS. 3115 MVT IVT = 3116 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3117 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3118 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), 3119 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3120 // Get the absolute value of the result. 3121 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3122 // Select between the nabs and abs value based on the sign bit of 3123 // the input. 3124 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3125 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3126 AbsVal), 3127 AbsVal); 3128 Result = LegalizeOp(Result); 3129 break; 3130 } 3131 3132 // Otherwise, do bitwise ops! 3133 MVT NVT = 3134 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3135 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3136 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3137 Result = LegalizeOp(Result); 3138 break; 3139 } 3140 } 3141 break; 3142 3143 case ISD::ADDC: 3144 case ISD::SUBC: 3145 Tmp1 = LegalizeOp(Node->getOperand(0)); 3146 Tmp2 = LegalizeOp(Node->getOperand(1)); 3147 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3148 // Since this produces two values, make sure to remember that we legalized 3149 // both of them. 3150 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3151 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3152 return Result; 3153 3154 case ISD::ADDE: 3155 case ISD::SUBE: 3156 Tmp1 = LegalizeOp(Node->getOperand(0)); 3157 Tmp2 = LegalizeOp(Node->getOperand(1)); 3158 Tmp3 = LegalizeOp(Node->getOperand(2)); 3159 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3160 // Since this produces two values, make sure to remember that we legalized 3161 // both of them. 3162 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3163 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3164 return Result; 3165 3166 case ISD::BUILD_PAIR: { 3167 MVT PairTy = Node->getValueType(0); 3168 // TODO: handle the case where the Lo and Hi operands are not of legal type 3169 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3170 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3171 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3172 case TargetLowering::Promote: 3173 case TargetLowering::Custom: 3174 assert(0 && "Cannot promote/custom this yet!"); 3175 case TargetLowering::Legal: 3176 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3177 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3178 break; 3179 case TargetLowering::Expand: 3180 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3181 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3182 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3183 DAG.getConstant(PairTy.getSizeInBits()/2, 3184 TLI.getShiftAmountTy())); 3185 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3186 break; 3187 } 3188 break; 3189 } 3190 3191 case ISD::UREM: 3192 case ISD::SREM: 3193 case ISD::FREM: 3194 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3195 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3196 3197 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3198 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3199 case TargetLowering::Custom: 3200 isCustom = true; 3201 // FALLTHROUGH 3202 case TargetLowering::Legal: 3203 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3204 if (isCustom) { 3205 Tmp1 = TLI.LowerOperation(Result, DAG); 3206 if (Tmp1.Val) Result = Tmp1; 3207 } 3208 break; 3209 case TargetLowering::Expand: { 3210 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3211 bool isSigned = DivOpc == ISD::SDIV; 3212 MVT VT = Node->getValueType(0); 3213 3214 // See if remainder can be lowered using two-result operations. 3215 SDVTList VTs = DAG.getVTList(VT, VT); 3216 if (Node->getOpcode() == ISD::SREM && 3217 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3218 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3219 break; 3220 } 3221 if (Node->getOpcode() == ISD::UREM && 3222 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3223 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3224 break; 3225 } 3226 3227 if (VT.isInteger()) { 3228 if (TLI.getOperationAction(DivOpc, VT) == 3229 TargetLowering::Legal) { 3230 // X % Y -> X-X/Y*Y 3231 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3232 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3233 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3234 } else if (VT.isVector()) { 3235 Result = LegalizeOp(UnrollVectorOp(Op)); 3236 } else { 3237 assert(VT == MVT::i32 && 3238 "Cannot expand this binary operator!"); 3239 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3240 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3241 SDOperand Dummy; 3242 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3243 } 3244 } else { 3245 assert(VT.isFloatingPoint() && 3246 "remainder op must have integer or floating-point type"); 3247 if (VT.isVector()) { 3248 Result = LegalizeOp(UnrollVectorOp(Op)); 3249 } else { 3250 // Floating point mod -> fmod libcall. 3251 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3252 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3253 SDOperand Dummy; 3254 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3255 } 3256 } 3257 break; 3258 } 3259 } 3260 break; 3261 case ISD::VAARG: { 3262 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3263 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3264 3265 MVT VT = Node->getValueType(0); 3266 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3267 default: assert(0 && "This action is not supported yet!"); 3268 case TargetLowering::Custom: 3269 isCustom = true; 3270 // FALLTHROUGH 3271 case TargetLowering::Legal: 3272 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3273 Result = Result.getValue(0); 3274 Tmp1 = Result.getValue(1); 3275 3276 if (isCustom) { 3277 Tmp2 = TLI.LowerOperation(Result, DAG); 3278 if (Tmp2.Val) { 3279 Result = LegalizeOp(Tmp2); 3280 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3281 } 3282 } 3283 break; 3284 case TargetLowering::Expand: { 3285 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3286 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3287 // Increment the pointer, VAList, to the next vaarg 3288 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3289 DAG.getConstant(VT.getSizeInBits()/8, 3290 TLI.getPointerTy())); 3291 // Store the incremented VAList to the legalized pointer 3292 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3293 // Load the actual argument out of the pointer VAList 3294 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3295 Tmp1 = LegalizeOp(Result.getValue(1)); 3296 Result = LegalizeOp(Result); 3297 break; 3298 } 3299 } 3300 // Since VAARG produces two values, make sure to remember that we 3301 // legalized both of them. 3302 AddLegalizedOperand(SDOperand(Node, 0), Result); 3303 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3304 return Op.ResNo ? Tmp1 : Result; 3305 } 3306 3307 case ISD::VACOPY: 3308 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3309 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3310 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3311 3312 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3313 default: assert(0 && "This action is not supported yet!"); 3314 case TargetLowering::Custom: 3315 isCustom = true; 3316 // FALLTHROUGH 3317 case TargetLowering::Legal: 3318 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3319 Node->getOperand(3), Node->getOperand(4)); 3320 if (isCustom) { 3321 Tmp1 = TLI.LowerOperation(Result, DAG); 3322 if (Tmp1.Val) Result = Tmp1; 3323 } 3324 break; 3325 case TargetLowering::Expand: 3326 // This defaults to loading a pointer from the input and storing it to the 3327 // output, returning the chain. 3328 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3329 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3330 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0); 3331 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0); 3332 break; 3333 } 3334 break; 3335 3336 case ISD::VAEND: 3337 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3338 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3339 3340 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3341 default: assert(0 && "This action is not supported yet!"); 3342 case TargetLowering::Custom: 3343 isCustom = true; 3344 // FALLTHROUGH 3345 case TargetLowering::Legal: 3346 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3347 if (isCustom) { 3348 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3349 if (Tmp1.Val) Result = Tmp1; 3350 } 3351 break; 3352 case TargetLowering::Expand: 3353 Result = Tmp1; // Default to a no-op, return the chain 3354 break; 3355 } 3356 break; 3357 3358 case ISD::VASTART: 3359 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3360 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3361 3362 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3363 3364 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3365 default: assert(0 && "This action is not supported yet!"); 3366 case TargetLowering::Legal: break; 3367 case TargetLowering::Custom: 3368 Tmp1 = TLI.LowerOperation(Result, DAG); 3369 if (Tmp1.Val) Result = Tmp1; 3370 break; 3371 } 3372 break; 3373 3374 case ISD::ROTL: 3375 case ISD::ROTR: 3376 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3377 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3378 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3379 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3380 default: 3381 assert(0 && "ROTL/ROTR legalize operation not supported"); 3382 break; 3383 case TargetLowering::Legal: 3384 break; 3385 case TargetLowering::Custom: 3386 Tmp1 = TLI.LowerOperation(Result, DAG); 3387 if (Tmp1.Val) Result = Tmp1; 3388 break; 3389 case TargetLowering::Promote: 3390 assert(0 && "Do not know how to promote ROTL/ROTR"); 3391 break; 3392 case TargetLowering::Expand: 3393 assert(0 && "Do not know how to expand ROTL/ROTR"); 3394 break; 3395 } 3396 break; 3397 3398 case ISD::BSWAP: 3399 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3400 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3401 case TargetLowering::Custom: 3402 assert(0 && "Cannot custom legalize this yet!"); 3403 case TargetLowering::Legal: 3404 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3405 break; 3406 case TargetLowering::Promote: { 3407 MVT OVT = Tmp1.getValueType(); 3408 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3409 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3410 3411 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3412 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3413 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3414 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3415 break; 3416 } 3417 case TargetLowering::Expand: 3418 Result = ExpandBSWAP(Tmp1); 3419 break; 3420 } 3421 break; 3422 3423 case ISD::CTPOP: 3424 case ISD::CTTZ: 3425 case ISD::CTLZ: 3426 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3427 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3428 case TargetLowering::Custom: 3429 case TargetLowering::Legal: 3430 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3431 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3432 TargetLowering::Custom) { 3433 Tmp1 = TLI.LowerOperation(Result, DAG); 3434 if (Tmp1.Val) { 3435 Result = Tmp1; 3436 } 3437 } 3438 break; 3439 case TargetLowering::Promote: { 3440 MVT OVT = Tmp1.getValueType(); 3441 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3442 3443 // Zero extend the argument. 3444 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3445 // Perform the larger operation, then subtract if needed. 3446 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3447 switch (Node->getOpcode()) { 3448 case ISD::CTPOP: 3449 Result = Tmp1; 3450 break; 3451 case ISD::CTTZ: 3452 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3453 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 3454 DAG.getConstant(NVT.getSizeInBits(), NVT), 3455 ISD::SETEQ); 3456 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3457 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3458 break; 3459 case ISD::CTLZ: 3460 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3461 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3462 DAG.getConstant(NVT.getSizeInBits() - 3463 OVT.getSizeInBits(), NVT)); 3464 break; 3465 } 3466 break; 3467 } 3468 case TargetLowering::Expand: 3469 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3470 break; 3471 } 3472 break; 3473 3474 // Unary operators 3475 case ISD::FABS: 3476 case ISD::FNEG: 3477 case ISD::FSQRT: 3478 case ISD::FSIN: 3479 case ISD::FCOS: 3480 Tmp1 = LegalizeOp(Node->getOperand(0)); 3481 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3482 case TargetLowering::Promote: 3483 case TargetLowering::Custom: 3484 isCustom = true; 3485 // FALLTHROUGH 3486 case TargetLowering::Legal: 3487 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3488 if (isCustom) { 3489 Tmp1 = TLI.LowerOperation(Result, DAG); 3490 if (Tmp1.Val) Result = Tmp1; 3491 } 3492 break; 3493 case TargetLowering::Expand: 3494 switch (Node->getOpcode()) { 3495 default: assert(0 && "Unreachable!"); 3496 case ISD::FNEG: 3497 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3498 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3499 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3500 break; 3501 case ISD::FABS: { 3502 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3503 MVT VT = Node->getValueType(0); 3504 Tmp2 = DAG.getConstantFP(0.0, VT); 3505 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 3506 ISD::SETUGT); 3507 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3508 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3509 break; 3510 } 3511 case ISD::FSQRT: 3512 case ISD::FSIN: 3513 case ISD::FCOS: { 3514 MVT VT = Node->getValueType(0); 3515 3516 // Expand unsupported unary vector operators by unrolling them. 3517 if (VT.isVector()) { 3518 Result = LegalizeOp(UnrollVectorOp(Op)); 3519 break; 3520 } 3521 3522 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3523 switch(Node->getOpcode()) { 3524 case ISD::FSQRT: 3525 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3526 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3527 break; 3528 case ISD::FSIN: 3529 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3530 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3531 break; 3532 case ISD::FCOS: 3533 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3534 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3535 break; 3536 default: assert(0 && "Unreachable!"); 3537 } 3538 SDOperand Dummy; 3539 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3540 break; 3541 } 3542 } 3543 break; 3544 } 3545 break; 3546 case ISD::FPOWI: { 3547 MVT VT = Node->getValueType(0); 3548 3549 // Expand unsupported unary vector operators by unrolling them. 3550 if (VT.isVector()) { 3551 Result = LegalizeOp(UnrollVectorOp(Op)); 3552 break; 3553 } 3554 3555 // We always lower FPOWI into a libcall. No target support for it yet. 3556 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3557 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3558 SDOperand Dummy; 3559 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3560 break; 3561 } 3562 case ISD::BIT_CONVERT: 3563 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3564 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3565 Node->getValueType(0)); 3566 } else if (Op.getOperand(0).getValueType().isVector()) { 3567 // The input has to be a vector type, we have to either scalarize it, pack 3568 // it, or convert it based on whether the input vector type is legal. 3569 SDNode *InVal = Node->getOperand(0).Val; 3570 int InIx = Node->getOperand(0).ResNo; 3571 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 3572 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 3573 3574 // Figure out if there is a simple type corresponding to this Vector 3575 // type. If so, convert to the vector type. 3576 MVT TVT = MVT::getVectorVT(EVT, NumElems); 3577 if (TLI.isTypeLegal(TVT)) { 3578 // Turn this into a bit convert of the vector input. 3579 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3580 LegalizeOp(Node->getOperand(0))); 3581 break; 3582 } else if (NumElems == 1) { 3583 // Turn this into a bit convert of the scalar input. 3584 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3585 ScalarizeVectorOp(Node->getOperand(0))); 3586 break; 3587 } else { 3588 // FIXME: UNIMP! Store then reload 3589 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3590 } 3591 } else { 3592 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3593 Node->getOperand(0).getValueType())) { 3594 default: assert(0 && "Unknown operation action!"); 3595 case TargetLowering::Expand: 3596 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3597 Node->getValueType(0)); 3598 break; 3599 case TargetLowering::Legal: 3600 Tmp1 = LegalizeOp(Node->getOperand(0)); 3601 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3602 break; 3603 } 3604 } 3605 break; 3606 3607 // Conversion operators. The source and destination have different types. 3608 case ISD::SINT_TO_FP: 3609 case ISD::UINT_TO_FP: { 3610 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3611 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3612 case Legal: 3613 switch (TLI.getOperationAction(Node->getOpcode(), 3614 Node->getOperand(0).getValueType())) { 3615 default: assert(0 && "Unknown operation action!"); 3616 case TargetLowering::Custom: 3617 isCustom = true; 3618 // FALLTHROUGH 3619 case TargetLowering::Legal: 3620 Tmp1 = LegalizeOp(Node->getOperand(0)); 3621 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3622 if (isCustom) { 3623 Tmp1 = TLI.LowerOperation(Result, DAG); 3624 if (Tmp1.Val) Result = Tmp1; 3625 } 3626 break; 3627 case TargetLowering::Expand: 3628 Result = ExpandLegalINT_TO_FP(isSigned, 3629 LegalizeOp(Node->getOperand(0)), 3630 Node->getValueType(0)); 3631 break; 3632 case TargetLowering::Promote: 3633 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3634 Node->getValueType(0), 3635 isSigned); 3636 break; 3637 } 3638 break; 3639 case Expand: 3640 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3641 Node->getValueType(0), Node->getOperand(0)); 3642 break; 3643 case Promote: 3644 Tmp1 = PromoteOp(Node->getOperand(0)); 3645 if (isSigned) { 3646 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3647 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3648 } else { 3649 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3650 Node->getOperand(0).getValueType()); 3651 } 3652 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3653 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3654 break; 3655 } 3656 break; 3657 } 3658 case ISD::TRUNCATE: 3659 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3660 case Legal: 3661 Tmp1 = LegalizeOp(Node->getOperand(0)); 3662 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3663 break; 3664 case Expand: 3665 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3666 3667 // Since the result is legal, we should just be able to truncate the low 3668 // part of the source. 3669 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3670 break; 3671 case Promote: 3672 Result = PromoteOp(Node->getOperand(0)); 3673 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3674 break; 3675 } 3676 break; 3677 3678 case ISD::FP_TO_SINT: 3679 case ISD::FP_TO_UINT: 3680 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3681 case Legal: 3682 Tmp1 = LegalizeOp(Node->getOperand(0)); 3683 3684 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3685 default: assert(0 && "Unknown operation action!"); 3686 case TargetLowering::Custom: 3687 isCustom = true; 3688 // FALLTHROUGH 3689 case TargetLowering::Legal: 3690 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3691 if (isCustom) { 3692 Tmp1 = TLI.LowerOperation(Result, DAG); 3693 if (Tmp1.Val) Result = Tmp1; 3694 } 3695 break; 3696 case TargetLowering::Promote: 3697 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3698 Node->getOpcode() == ISD::FP_TO_SINT); 3699 break; 3700 case TargetLowering::Expand: 3701 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3702 SDOperand True, False; 3703 MVT VT = Node->getOperand(0).getValueType(); 3704 MVT NVT = Node->getValueType(0); 3705 const uint64_t zero[] = {0, 0}; 3706 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 3707 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 3708 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 3709 Tmp2 = DAG.getConstantFP(apf, VT); 3710 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), 3711 Node->getOperand(0), Tmp2, ISD::SETLT); 3712 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3713 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3714 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3715 Tmp2)); 3716 False = DAG.getNode(ISD::XOR, NVT, False, 3717 DAG.getConstant(x, NVT)); 3718 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3719 break; 3720 } else { 3721 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3722 } 3723 break; 3724 } 3725 break; 3726 case Expand: { 3727 MVT VT = Op.getValueType(); 3728 MVT OVT = Node->getOperand(0).getValueType(); 3729 // Convert ppcf128 to i32 3730 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3731 if (Node->getOpcode() == ISD::FP_TO_SINT) { 3732 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 3733 Node->getOperand(0), DAG.getValueType(MVT::f64)); 3734 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 3735 DAG.getIntPtrConstant(1)); 3736 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 3737 } else { 3738 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3739 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3740 Tmp2 = DAG.getConstantFP(apf, OVT); 3741 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3742 // FIXME: generated code sucks. 3743 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3744 DAG.getNode(ISD::ADD, MVT::i32, 3745 DAG.getNode(ISD::FP_TO_SINT, VT, 3746 DAG.getNode(ISD::FSUB, OVT, 3747 Node->getOperand(0), Tmp2)), 3748 DAG.getConstant(0x80000000, MVT::i32)), 3749 DAG.getNode(ISD::FP_TO_SINT, VT, 3750 Node->getOperand(0)), 3751 DAG.getCondCode(ISD::SETGE)); 3752 } 3753 break; 3754 } 3755 // Convert f32 / f64 to i32 / i64 / i128. 3756 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3757 switch (Node->getOpcode()) { 3758 case ISD::FP_TO_SINT: { 3759 if (VT == MVT::i32) { 3760 if (OVT == MVT::f32) 3761 LC = RTLIB::FPTOSINT_F32_I32; 3762 else if (OVT == MVT::f64) 3763 LC = RTLIB::FPTOSINT_F64_I32; 3764 else 3765 assert(0 && "Unexpected i32-to-fp conversion!"); 3766 } else if (VT == MVT::i64) { 3767 if (OVT == MVT::f32) 3768 LC = RTLIB::FPTOSINT_F32_I64; 3769 else if (OVT == MVT::f64) 3770 LC = RTLIB::FPTOSINT_F64_I64; 3771 else if (OVT == MVT::f80) 3772 LC = RTLIB::FPTOSINT_F80_I64; 3773 else if (OVT == MVT::ppcf128) 3774 LC = RTLIB::FPTOSINT_PPCF128_I64; 3775 else 3776 assert(0 && "Unexpected i64-to-fp conversion!"); 3777 } else if (VT == MVT::i128) { 3778 if (OVT == MVT::f32) 3779 LC = RTLIB::FPTOSINT_F32_I128; 3780 else if (OVT == MVT::f64) 3781 LC = RTLIB::FPTOSINT_F64_I128; 3782 else if (OVT == MVT::f80) 3783 LC = RTLIB::FPTOSINT_F80_I128; 3784 else if (OVT == MVT::ppcf128) 3785 LC = RTLIB::FPTOSINT_PPCF128_I128; 3786 else 3787 assert(0 && "Unexpected i128-to-fp conversion!"); 3788 } else { 3789 assert(0 && "Unexpectd int-to-fp conversion!"); 3790 } 3791 break; 3792 } 3793 case ISD::FP_TO_UINT: { 3794 if (VT == MVT::i32) { 3795 if (OVT == MVT::f32) 3796 LC = RTLIB::FPTOUINT_F32_I32; 3797 else if (OVT == MVT::f64) 3798 LC = RTLIB::FPTOUINT_F64_I32; 3799 else if (OVT == MVT::f80) 3800 LC = RTLIB::FPTOUINT_F80_I32; 3801 else 3802 assert(0 && "Unexpected i32-to-fp conversion!"); 3803 } else if (VT == MVT::i64) { 3804 if (OVT == MVT::f32) 3805 LC = RTLIB::FPTOUINT_F32_I64; 3806 else if (OVT == MVT::f64) 3807 LC = RTLIB::FPTOUINT_F64_I64; 3808 else if (OVT == MVT::f80) 3809 LC = RTLIB::FPTOUINT_F80_I64; 3810 else if (OVT == MVT::ppcf128) 3811 LC = RTLIB::FPTOUINT_PPCF128_I64; 3812 else 3813 assert(0 && "Unexpected i64-to-fp conversion!"); 3814 } else if (VT == MVT::i128) { 3815 if (OVT == MVT::f32) 3816 LC = RTLIB::FPTOUINT_F32_I128; 3817 else if (OVT == MVT::f64) 3818 LC = RTLIB::FPTOUINT_F64_I128; 3819 else if (OVT == MVT::f80) 3820 LC = RTLIB::FPTOUINT_F80_I128; 3821 else if (OVT == MVT::ppcf128) 3822 LC = RTLIB::FPTOUINT_PPCF128_I128; 3823 else 3824 assert(0 && "Unexpected i128-to-fp conversion!"); 3825 } else { 3826 assert(0 && "Unexpectd int-to-fp conversion!"); 3827 } 3828 break; 3829 } 3830 default: assert(0 && "Unreachable!"); 3831 } 3832 SDOperand Dummy; 3833 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3834 break; 3835 } 3836 case Promote: 3837 Tmp1 = PromoteOp(Node->getOperand(0)); 3838 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3839 Result = LegalizeOp(Result); 3840 break; 3841 } 3842 break; 3843 3844 case ISD::FP_EXTEND: { 3845 MVT DstVT = Op.getValueType(); 3846 MVT SrcVT = Op.getOperand(0).getValueType(); 3847 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3848 // The only other way we can lower this is to turn it into a STORE, 3849 // LOAD pair, targetting a temporary location (a stack slot). 3850 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 3851 break; 3852 } 3853 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3854 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3855 case Legal: 3856 Tmp1 = LegalizeOp(Node->getOperand(0)); 3857 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3858 break; 3859 case Promote: 3860 Tmp1 = PromoteOp(Node->getOperand(0)); 3861 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3862 break; 3863 } 3864 break; 3865 } 3866 case ISD::FP_ROUND: { 3867 MVT DstVT = Op.getValueType(); 3868 MVT SrcVT = Op.getOperand(0).getValueType(); 3869 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3870 if (SrcVT == MVT::ppcf128) { 3871 SDOperand Lo; 3872 ExpandOp(Node->getOperand(0), Lo, Result); 3873 // Round it the rest of the way (e.g. to f32) if needed. 3874 if (DstVT!=MVT::f64) 3875 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 3876 break; 3877 } 3878 // The only other way we can lower this is to turn it into a STORE, 3879 // LOAD pair, targetting a temporary location (a stack slot). 3880 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 3881 break; 3882 } 3883 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3884 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3885 case Legal: 3886 Tmp1 = LegalizeOp(Node->getOperand(0)); 3887 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3888 break; 3889 case Promote: 3890 Tmp1 = PromoteOp(Node->getOperand(0)); 3891 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 3892 Node->getOperand(1)); 3893 break; 3894 } 3895 break; 3896 } 3897 case ISD::ANY_EXTEND: 3898 case ISD::ZERO_EXTEND: 3899 case ISD::SIGN_EXTEND: 3900 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3901 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3902 case Legal: 3903 Tmp1 = LegalizeOp(Node->getOperand(0)); 3904 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3905 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3906 TargetLowering::Custom) { 3907 Tmp1 = TLI.LowerOperation(Result, DAG); 3908 if (Tmp1.Val) Result = Tmp1; 3909 } 3910 break; 3911 case Promote: 3912 switch (Node->getOpcode()) { 3913 case ISD::ANY_EXTEND: 3914 Tmp1 = PromoteOp(Node->getOperand(0)); 3915 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3916 break; 3917 case ISD::ZERO_EXTEND: 3918 Result = PromoteOp(Node->getOperand(0)); 3919 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3920 Result = DAG.getZeroExtendInReg(Result, 3921 Node->getOperand(0).getValueType()); 3922 break; 3923 case ISD::SIGN_EXTEND: 3924 Result = PromoteOp(Node->getOperand(0)); 3925 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3926 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3927 Result, 3928 DAG.getValueType(Node->getOperand(0).getValueType())); 3929 break; 3930 } 3931 } 3932 break; 3933 case ISD::FP_ROUND_INREG: 3934 case ISD::SIGN_EXTEND_INREG: { 3935 Tmp1 = LegalizeOp(Node->getOperand(0)); 3936 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3937 3938 // If this operation is not supported, convert it to a shl/shr or load/store 3939 // pair. 3940 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3941 default: assert(0 && "This action not supported for this op yet!"); 3942 case TargetLowering::Legal: 3943 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3944 break; 3945 case TargetLowering::Expand: 3946 // If this is an integer extend and shifts are supported, do that. 3947 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3948 // NOTE: we could fall back on load/store here too for targets without 3949 // SAR. However, it is doubtful that any exist. 3950 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 3951 ExtraVT.getSizeInBits(); 3952 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3953 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3954 Node->getOperand(0), ShiftCst); 3955 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3956 Result, ShiftCst); 3957 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3958 // The only way we can lower this is to turn it into a TRUNCSTORE, 3959 // EXTLOAD pair, targetting a temporary location (a stack slot). 3960 3961 // NOTE: there is a choice here between constantly creating new stack 3962 // slots and always reusing the same one. We currently always create 3963 // new ones, as reuse may inhibit scheduling. 3964 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 3965 Node->getValueType(0)); 3966 } else { 3967 assert(0 && "Unknown op"); 3968 } 3969 break; 3970 } 3971 break; 3972 } 3973 case ISD::TRAMPOLINE: { 3974 SDOperand Ops[6]; 3975 for (unsigned i = 0; i != 6; ++i) 3976 Ops[i] = LegalizeOp(Node->getOperand(i)); 3977 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3978 // The only option for this node is to custom lower it. 3979 Result = TLI.LowerOperation(Result, DAG); 3980 assert(Result.Val && "Should always custom lower!"); 3981 3982 // Since trampoline produces two values, make sure to remember that we 3983 // legalized both of them. 3984 Tmp1 = LegalizeOp(Result.getValue(1)); 3985 Result = LegalizeOp(Result); 3986 AddLegalizedOperand(SDOperand(Node, 0), Result); 3987 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3988 return Op.ResNo ? Tmp1 : Result; 3989 } 3990 case ISD::FLT_ROUNDS_: { 3991 MVT VT = Node->getValueType(0); 3992 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3993 default: assert(0 && "This action not supported for this op yet!"); 3994 case TargetLowering::Custom: 3995 Result = TLI.LowerOperation(Op, DAG); 3996 if (Result.Val) break; 3997 // Fall Thru 3998 case TargetLowering::Legal: 3999 // If this operation is not supported, lower it to constant 1 4000 Result = DAG.getConstant(1, VT); 4001 break; 4002 } 4003 break; 4004 } 4005 case ISD::TRAP: { 4006 MVT VT = Node->getValueType(0); 4007 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4008 default: assert(0 && "This action not supported for this op yet!"); 4009 case TargetLowering::Legal: 4010 Tmp1 = LegalizeOp(Node->getOperand(0)); 4011 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4012 break; 4013 case TargetLowering::Custom: 4014 Result = TLI.LowerOperation(Op, DAG); 4015 if (Result.Val) break; 4016 // Fall Thru 4017 case TargetLowering::Expand: 4018 // If this operation is not supported, lower it to 'abort()' call 4019 Tmp1 = LegalizeOp(Node->getOperand(0)); 4020 TargetLowering::ArgListTy Args; 4021 std::pair<SDOperand,SDOperand> CallResult = 4022 TLI.LowerCallTo(Tmp1, Type::VoidTy, 4023 false, false, false, CallingConv::C, false, 4024 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 4025 Args, DAG); 4026 Result = CallResult.second; 4027 break; 4028 } 4029 break; 4030 } 4031 } 4032 4033 assert(Result.getValueType() == Op.getValueType() && 4034 "Bad legalization!"); 4035 4036 // Make sure that the generated code is itself legal. 4037 if (Result != Op) 4038 Result = LegalizeOp(Result); 4039 4040 // Note that LegalizeOp may be reentered even from single-use nodes, which 4041 // means that we always must cache transformed nodes. 4042 AddLegalizedOperand(Op, Result); 4043 return Result; 4044} 4045 4046/// PromoteOp - Given an operation that produces a value in an invalid type, 4047/// promote it to compute the value into a larger type. The produced value will 4048/// have the correct bits for the low portion of the register, but no guarantee 4049/// is made about the top bits: it may be zero, sign-extended, or garbage. 4050SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 4051 MVT VT = Op.getValueType(); 4052 MVT NVT = TLI.getTypeToTransformTo(VT); 4053 assert(getTypeAction(VT) == Promote && 4054 "Caller should expand or legalize operands that are not promotable!"); 4055 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() && 4056 "Cannot promote to smaller type!"); 4057 4058 SDOperand Tmp1, Tmp2, Tmp3; 4059 SDOperand Result; 4060 SDNode *Node = Op.Val; 4061 4062 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 4063 if (I != PromotedNodes.end()) return I->second; 4064 4065 switch (Node->getOpcode()) { 4066 case ISD::CopyFromReg: 4067 assert(0 && "CopyFromReg must be legal!"); 4068 default: 4069#ifndef NDEBUG 4070 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4071#endif 4072 assert(0 && "Do not know how to promote this operator!"); 4073 abort(); 4074 case ISD::UNDEF: 4075 Result = DAG.getNode(ISD::UNDEF, NVT); 4076 break; 4077 case ISD::Constant: 4078 if (VT != MVT::i1) 4079 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4080 else 4081 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4082 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4083 break; 4084 case ISD::ConstantFP: 4085 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4086 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4087 break; 4088 4089 case ISD::SETCC: 4090 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0))) 4091 && "SetCC type is not legal??"); 4092 Result = DAG.getNode(ISD::SETCC, 4093 TLI.getSetCCResultType(Node->getOperand(0)), 4094 Node->getOperand(0), Node->getOperand(1), 4095 Node->getOperand(2)); 4096 break; 4097 4098 case ISD::TRUNCATE: 4099 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4100 case Legal: 4101 Result = LegalizeOp(Node->getOperand(0)); 4102 assert(Result.getValueType().bitsGE(NVT) && 4103 "This truncation doesn't make sense!"); 4104 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT 4105 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4106 break; 4107 case Promote: 4108 // The truncation is not required, because we don't guarantee anything 4109 // about high bits anyway. 4110 Result = PromoteOp(Node->getOperand(0)); 4111 break; 4112 case Expand: 4113 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4114 // Truncate the low part of the expanded value to the result type 4115 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4116 } 4117 break; 4118 case ISD::SIGN_EXTEND: 4119 case ISD::ZERO_EXTEND: 4120 case ISD::ANY_EXTEND: 4121 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4122 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4123 case Legal: 4124 // Input is legal? Just do extend all the way to the larger type. 4125 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4126 break; 4127 case Promote: 4128 // Promote the reg if it's smaller. 4129 Result = PromoteOp(Node->getOperand(0)); 4130 // The high bits are not guaranteed to be anything. Insert an extend. 4131 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4132 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4133 DAG.getValueType(Node->getOperand(0).getValueType())); 4134 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4135 Result = DAG.getZeroExtendInReg(Result, 4136 Node->getOperand(0).getValueType()); 4137 break; 4138 } 4139 break; 4140 case ISD::BIT_CONVERT: 4141 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4142 Node->getValueType(0)); 4143 Result = PromoteOp(Result); 4144 break; 4145 4146 case ISD::FP_EXTEND: 4147 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4148 case ISD::FP_ROUND: 4149 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4150 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4151 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4152 case Legal: 4153 if (Node->getConstantOperandVal(1) == 0) { 4154 // Input is legal? Do an FP_ROUND_INREG. 4155 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4156 DAG.getValueType(VT)); 4157 } else { 4158 // Just remove the truncate, it isn't affecting the value. 4159 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4160 Node->getOperand(1)); 4161 } 4162 break; 4163 } 4164 break; 4165 case ISD::SINT_TO_FP: 4166 case ISD::UINT_TO_FP: 4167 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4168 case Legal: 4169 // No extra round required here. 4170 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4171 break; 4172 4173 case Promote: 4174 Result = PromoteOp(Node->getOperand(0)); 4175 if (Node->getOpcode() == ISD::SINT_TO_FP) 4176 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4177 Result, 4178 DAG.getValueType(Node->getOperand(0).getValueType())); 4179 else 4180 Result = DAG.getZeroExtendInReg(Result, 4181 Node->getOperand(0).getValueType()); 4182 // No extra round required here. 4183 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4184 break; 4185 case Expand: 4186 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4187 Node->getOperand(0)); 4188 // Round if we cannot tolerate excess precision. 4189 if (NoExcessFPPrecision) 4190 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4191 DAG.getValueType(VT)); 4192 break; 4193 } 4194 break; 4195 4196 case ISD::SIGN_EXTEND_INREG: 4197 Result = PromoteOp(Node->getOperand(0)); 4198 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4199 Node->getOperand(1)); 4200 break; 4201 case ISD::FP_TO_SINT: 4202 case ISD::FP_TO_UINT: 4203 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4204 case Legal: 4205 case Expand: 4206 Tmp1 = Node->getOperand(0); 4207 break; 4208 case Promote: 4209 // The input result is prerounded, so we don't have to do anything 4210 // special. 4211 Tmp1 = PromoteOp(Node->getOperand(0)); 4212 break; 4213 } 4214 // If we're promoting a UINT to a larger size, check to see if the new node 4215 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4216 // we can use that instead. This allows us to generate better code for 4217 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4218 // legal, such as PowerPC. 4219 if (Node->getOpcode() == ISD::FP_TO_UINT && 4220 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 4221 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 4222 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4223 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4224 } else { 4225 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4226 } 4227 break; 4228 4229 case ISD::FABS: 4230 case ISD::FNEG: 4231 Tmp1 = PromoteOp(Node->getOperand(0)); 4232 assert(Tmp1.getValueType() == NVT); 4233 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4234 // NOTE: we do not have to do any extra rounding here for 4235 // NoExcessFPPrecision, because we know the input will have the appropriate 4236 // precision, and these operations don't modify precision at all. 4237 break; 4238 4239 case ISD::FSQRT: 4240 case ISD::FSIN: 4241 case ISD::FCOS: 4242 Tmp1 = PromoteOp(Node->getOperand(0)); 4243 assert(Tmp1.getValueType() == NVT); 4244 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4245 if (NoExcessFPPrecision) 4246 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4247 DAG.getValueType(VT)); 4248 break; 4249 4250 case ISD::FPOWI: { 4251 // Promote f32 powi to f64 powi. Note that this could insert a libcall 4252 // directly as well, which may be better. 4253 Tmp1 = PromoteOp(Node->getOperand(0)); 4254 assert(Tmp1.getValueType() == NVT); 4255 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 4256 if (NoExcessFPPrecision) 4257 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4258 DAG.getValueType(VT)); 4259 break; 4260 } 4261 4262 case ISD::ATOMIC_CMP_SWAP: { 4263 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4264 Tmp2 = PromoteOp(Node->getOperand(2)); 4265 Tmp3 = PromoteOp(Node->getOperand(3)); 4266 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 4267 AtomNode->getBasePtr(), Tmp2, Tmp3, 4268 AtomNode->getSrcValue(), 4269 AtomNode->getAlignment()); 4270 // Remember that we legalized the chain. 4271 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4272 break; 4273 } 4274 case ISD::ATOMIC_LOAD_ADD: 4275 case ISD::ATOMIC_LOAD_SUB: 4276 case ISD::ATOMIC_LOAD_AND: 4277 case ISD::ATOMIC_LOAD_OR: 4278 case ISD::ATOMIC_LOAD_XOR: 4279 case ISD::ATOMIC_LOAD_NAND: 4280 case ISD::ATOMIC_LOAD_MIN: 4281 case ISD::ATOMIC_LOAD_MAX: 4282 case ISD::ATOMIC_LOAD_UMIN: 4283 case ISD::ATOMIC_LOAD_UMAX: 4284 case ISD::ATOMIC_SWAP: { 4285 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4286 Tmp2 = PromoteOp(Node->getOperand(2)); 4287 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 4288 AtomNode->getBasePtr(), Tmp2, 4289 AtomNode->getSrcValue(), 4290 AtomNode->getAlignment()); 4291 // Remember that we legalized the chain. 4292 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4293 break; 4294 } 4295 4296 case ISD::AND: 4297 case ISD::OR: 4298 case ISD::XOR: 4299 case ISD::ADD: 4300 case ISD::SUB: 4301 case ISD::MUL: 4302 // The input may have strange things in the top bits of the registers, but 4303 // these operations don't care. They may have weird bits going out, but 4304 // that too is okay if they are integer operations. 4305 Tmp1 = PromoteOp(Node->getOperand(0)); 4306 Tmp2 = PromoteOp(Node->getOperand(1)); 4307 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4308 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4309 break; 4310 case ISD::FADD: 4311 case ISD::FSUB: 4312 case ISD::FMUL: 4313 Tmp1 = PromoteOp(Node->getOperand(0)); 4314 Tmp2 = PromoteOp(Node->getOperand(1)); 4315 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4316 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4317 4318 // Floating point operations will give excess precision that we may not be 4319 // able to tolerate. If we DO allow excess precision, just leave it, 4320 // otherwise excise it. 4321 // FIXME: Why would we need to round FP ops more than integer ones? 4322 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4323 if (NoExcessFPPrecision) 4324 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4325 DAG.getValueType(VT)); 4326 break; 4327 4328 case ISD::SDIV: 4329 case ISD::SREM: 4330 // These operators require that their input be sign extended. 4331 Tmp1 = PromoteOp(Node->getOperand(0)); 4332 Tmp2 = PromoteOp(Node->getOperand(1)); 4333 if (NVT.isInteger()) { 4334 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4335 DAG.getValueType(VT)); 4336 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4337 DAG.getValueType(VT)); 4338 } 4339 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4340 4341 // Perform FP_ROUND: this is probably overly pessimistic. 4342 if (NVT.isFloatingPoint() && NoExcessFPPrecision) 4343 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4344 DAG.getValueType(VT)); 4345 break; 4346 case ISD::FDIV: 4347 case ISD::FREM: 4348 case ISD::FCOPYSIGN: 4349 // These operators require that their input be fp extended. 4350 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4351 case Expand: assert(0 && "not implemented"); 4352 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4353 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4354 } 4355 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4356 case Expand: assert(0 && "not implemented"); 4357 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4358 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4359 } 4360 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4361 4362 // Perform FP_ROUND: this is probably overly pessimistic. 4363 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4364 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4365 DAG.getValueType(VT)); 4366 break; 4367 4368 case ISD::UDIV: 4369 case ISD::UREM: 4370 // These operators require that their input be zero extended. 4371 Tmp1 = PromoteOp(Node->getOperand(0)); 4372 Tmp2 = PromoteOp(Node->getOperand(1)); 4373 assert(NVT.isInteger() && "Operators don't apply to FP!"); 4374 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4375 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4376 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4377 break; 4378 4379 case ISD::SHL: 4380 Tmp1 = PromoteOp(Node->getOperand(0)); 4381 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4382 break; 4383 case ISD::SRA: 4384 // The input value must be properly sign extended. 4385 Tmp1 = PromoteOp(Node->getOperand(0)); 4386 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4387 DAG.getValueType(VT)); 4388 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4389 break; 4390 case ISD::SRL: 4391 // The input value must be properly zero extended. 4392 Tmp1 = PromoteOp(Node->getOperand(0)); 4393 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4394 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4395 break; 4396 4397 case ISD::VAARG: 4398 Tmp1 = Node->getOperand(0); // Get the chain. 4399 Tmp2 = Node->getOperand(1); // Get the pointer. 4400 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4401 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4402 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 4403 } else { 4404 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4405 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4406 // Increment the pointer, VAList, to the next vaarg 4407 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4408 DAG.getConstant(VT.getSizeInBits()/8, 4409 TLI.getPointerTy())); 4410 // Store the incremented VAList to the legalized pointer 4411 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4412 // Load the actual argument out of the pointer VAList 4413 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4414 } 4415 // Remember that we legalized the chain. 4416 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4417 break; 4418 4419 case ISD::LOAD: { 4420 LoadSDNode *LD = cast<LoadSDNode>(Node); 4421 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4422 ? ISD::EXTLOAD : LD->getExtensionType(); 4423 Result = DAG.getExtLoad(ExtType, NVT, 4424 LD->getChain(), LD->getBasePtr(), 4425 LD->getSrcValue(), LD->getSrcValueOffset(), 4426 LD->getMemoryVT(), 4427 LD->isVolatile(), 4428 LD->getAlignment()); 4429 // Remember that we legalized the chain. 4430 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4431 break; 4432 } 4433 case ISD::SELECT: { 4434 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4435 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4436 4437 MVT VT2 = Tmp2.getValueType(); 4438 assert(VT2 == Tmp3.getValueType() 4439 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); 4440 // Ensure that the resulting node is at least the same size as the operands' 4441 // value types, because we cannot assume that TLI.getSetCCValueType() is 4442 // constant. 4443 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3); 4444 break; 4445 } 4446 case ISD::SELECT_CC: 4447 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4448 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4449 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4450 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4451 break; 4452 case ISD::BSWAP: 4453 Tmp1 = Node->getOperand(0); 4454 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4455 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4456 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4457 DAG.getConstant(NVT.getSizeInBits() - 4458 VT.getSizeInBits(), 4459 TLI.getShiftAmountTy())); 4460 break; 4461 case ISD::CTPOP: 4462 case ISD::CTTZ: 4463 case ISD::CTLZ: 4464 // Zero extend the argument 4465 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4466 // Perform the larger operation, then subtract if needed. 4467 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4468 switch(Node->getOpcode()) { 4469 case ISD::CTPOP: 4470 Result = Tmp1; 4471 break; 4472 case ISD::CTTZ: 4473 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4474 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 4475 DAG.getConstant(NVT.getSizeInBits(), NVT), 4476 ISD::SETEQ); 4477 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4478 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); 4479 break; 4480 case ISD::CTLZ: 4481 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4482 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4483 DAG.getConstant(NVT.getSizeInBits() - 4484 VT.getSizeInBits(), NVT)); 4485 break; 4486 } 4487 break; 4488 case ISD::EXTRACT_SUBVECTOR: 4489 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4490 break; 4491 case ISD::EXTRACT_VECTOR_ELT: 4492 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4493 break; 4494 } 4495 4496 assert(Result.Val && "Didn't set a result!"); 4497 4498 // Make sure the result is itself legal. 4499 Result = LegalizeOp(Result); 4500 4501 // Remember that we promoted this! 4502 AddPromotedOperand(Op, Result); 4503 return Result; 4504} 4505 4506/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4507/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4508/// based on the vector type. The return type of this matches the element type 4509/// of the vector, which may not be legal for the target. 4510SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4511 // We know that operand #0 is the Vec vector. If the index is a constant 4512 // or if the invec is a supported hardware type, we can use it. Otherwise, 4513 // lower to a store then an indexed load. 4514 SDOperand Vec = Op.getOperand(0); 4515 SDOperand Idx = Op.getOperand(1); 4516 4517 MVT TVT = Vec.getValueType(); 4518 unsigned NumElems = TVT.getVectorNumElements(); 4519 4520 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4521 default: assert(0 && "This action is not supported yet!"); 4522 case TargetLowering::Custom: { 4523 Vec = LegalizeOp(Vec); 4524 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4525 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4526 if (Tmp3.Val) 4527 return Tmp3; 4528 break; 4529 } 4530 case TargetLowering::Legal: 4531 if (isTypeLegal(TVT)) { 4532 Vec = LegalizeOp(Vec); 4533 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4534 return Op; 4535 } 4536 break; 4537 case TargetLowering::Expand: 4538 break; 4539 } 4540 4541 if (NumElems == 1) { 4542 // This must be an access of the only element. Return it. 4543 Op = ScalarizeVectorOp(Vec); 4544 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4545 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 4546 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4547 SDOperand Lo, Hi; 4548 SplitVectorOp(Vec, Lo, Hi); 4549 if (CIdx->getValue() < NumLoElts) { 4550 Vec = Lo; 4551 } else { 4552 Vec = Hi; 4553 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts, 4554 Idx.getValueType()); 4555 } 4556 4557 // It's now an extract from the appropriate high or low part. Recurse. 4558 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4559 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4560 } else { 4561 // Store the value to a temporary stack slot, then LOAD the scalar 4562 // element back out. 4563 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4564 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4565 4566 // Add the offset to the index. 4567 unsigned EltSize = Op.getValueType().getSizeInBits()/8; 4568 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4569 DAG.getConstant(EltSize, Idx.getValueType())); 4570 4571 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 4572 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4573 else 4574 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4575 4576 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4577 4578 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4579 } 4580 return Op; 4581} 4582 4583/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4584/// we assume the operation can be split if it is not already legal. 4585SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4586 // We know that operand #0 is the Vec vector. For now we assume the index 4587 // is a constant and that the extracted result is a supported hardware type. 4588 SDOperand Vec = Op.getOperand(0); 4589 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4590 4591 unsigned NumElems = Vec.getValueType().getVectorNumElements(); 4592 4593 if (NumElems == Op.getValueType().getVectorNumElements()) { 4594 // This must be an access of the desired vector length. Return it. 4595 return Vec; 4596 } 4597 4598 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4599 SDOperand Lo, Hi; 4600 SplitVectorOp(Vec, Lo, Hi); 4601 if (CIdx->getValue() < NumElems/2) { 4602 Vec = Lo; 4603 } else { 4604 Vec = Hi; 4605 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4606 } 4607 4608 // It's now an extract from the appropriate high or low part. Recurse. 4609 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4610 return ExpandEXTRACT_SUBVECTOR(Op); 4611} 4612 4613/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4614/// with condition CC on the current target. This usually involves legalizing 4615/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4616/// there may be no choice but to create a new SetCC node to represent the 4617/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4618/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4619void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4620 SDOperand &RHS, 4621 SDOperand &CC) { 4622 SDOperand Tmp1, Tmp2, Tmp3, Result; 4623 4624 switch (getTypeAction(LHS.getValueType())) { 4625 case Legal: 4626 Tmp1 = LegalizeOp(LHS); // LHS 4627 Tmp2 = LegalizeOp(RHS); // RHS 4628 break; 4629 case Promote: 4630 Tmp1 = PromoteOp(LHS); // LHS 4631 Tmp2 = PromoteOp(RHS); // RHS 4632 4633 // If this is an FP compare, the operands have already been extended. 4634 if (LHS.getValueType().isInteger()) { 4635 MVT VT = LHS.getValueType(); 4636 MVT NVT = TLI.getTypeToTransformTo(VT); 4637 4638 // Otherwise, we have to insert explicit sign or zero extends. Note 4639 // that we could insert sign extends for ALL conditions, but zero extend 4640 // is cheaper on many machines (an AND instead of two shifts), so prefer 4641 // it. 4642 switch (cast<CondCodeSDNode>(CC)->get()) { 4643 default: assert(0 && "Unknown integer comparison!"); 4644 case ISD::SETEQ: 4645 case ISD::SETNE: 4646 case ISD::SETUGE: 4647 case ISD::SETUGT: 4648 case ISD::SETULE: 4649 case ISD::SETULT: 4650 // ALL of these operations will work if we either sign or zero extend 4651 // the operands (including the unsigned comparisons!). Zero extend is 4652 // usually a simpler/cheaper operation, so prefer it. 4653 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4654 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4655 break; 4656 case ISD::SETGE: 4657 case ISD::SETGT: 4658 case ISD::SETLT: 4659 case ISD::SETLE: 4660 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4661 DAG.getValueType(VT)); 4662 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4663 DAG.getValueType(VT)); 4664 break; 4665 } 4666 } 4667 break; 4668 case Expand: { 4669 MVT VT = LHS.getValueType(); 4670 if (VT == MVT::f32 || VT == MVT::f64) { 4671 // Expand into one or more soft-fp libcall(s). 4672 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; 4673 switch (cast<CondCodeSDNode>(CC)->get()) { 4674 case ISD::SETEQ: 4675 case ISD::SETOEQ: 4676 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4677 break; 4678 case ISD::SETNE: 4679 case ISD::SETUNE: 4680 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4681 break; 4682 case ISD::SETGE: 4683 case ISD::SETOGE: 4684 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4685 break; 4686 case ISD::SETLT: 4687 case ISD::SETOLT: 4688 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4689 break; 4690 case ISD::SETLE: 4691 case ISD::SETOLE: 4692 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4693 break; 4694 case ISD::SETGT: 4695 case ISD::SETOGT: 4696 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4697 break; 4698 case ISD::SETUO: 4699 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4700 break; 4701 case ISD::SETO: 4702 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4703 break; 4704 default: 4705 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4706 switch (cast<CondCodeSDNode>(CC)->get()) { 4707 case ISD::SETONE: 4708 // SETONE = SETOLT | SETOGT 4709 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4710 // Fallthrough 4711 case ISD::SETUGT: 4712 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4713 break; 4714 case ISD::SETUGE: 4715 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4716 break; 4717 case ISD::SETULT: 4718 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4719 break; 4720 case ISD::SETULE: 4721 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4722 break; 4723 case ISD::SETUEQ: 4724 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4725 break; 4726 default: assert(0 && "Unsupported FP setcc!"); 4727 } 4728 } 4729 4730 SDOperand Dummy; 4731 Tmp1 = ExpandLibCall(LC1, 4732 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4733 false /*sign irrelevant*/, Dummy); 4734 Tmp2 = DAG.getConstant(0, MVT::i32); 4735 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4736 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4737 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 4738 CC); 4739 LHS = ExpandLibCall(LC2, 4740 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4741 false /*sign irrelevant*/, Dummy); 4742 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, 4743 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4744 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4745 Tmp2 = SDOperand(); 4746 } 4747 LHS = Tmp1; 4748 RHS = Tmp2; 4749 return; 4750 } 4751 4752 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4753 ExpandOp(LHS, LHSLo, LHSHi); 4754 ExpandOp(RHS, RHSLo, RHSHi); 4755 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4756 4757 if (VT==MVT::ppcf128) { 4758 // FIXME: This generated code sucks. We want to generate 4759 // FCMP crN, hi1, hi2 4760 // BNE crN, L: 4761 // FCMP crN, lo1, lo2 4762 // The following can be improved, but not that much. 4763 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ); 4764 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode); 4765 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4766 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE); 4767 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode); 4768 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4769 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4770 Tmp2 = SDOperand(); 4771 break; 4772 } 4773 4774 switch (CCCode) { 4775 case ISD::SETEQ: 4776 case ISD::SETNE: 4777 if (RHSLo == RHSHi) 4778 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4779 if (RHSCST->isAllOnesValue()) { 4780 // Comparison to -1. 4781 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4782 Tmp2 = RHSLo; 4783 break; 4784 } 4785 4786 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4787 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4788 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4789 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4790 break; 4791 default: 4792 // If this is a comparison of the sign bit, just look at the top part. 4793 // X > -1, x < 0 4794 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4795 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4796 CST->isNullValue()) || // X < 0 4797 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4798 CST->isAllOnesValue())) { // X > -1 4799 Tmp1 = LHSHi; 4800 Tmp2 = RHSHi; 4801 break; 4802 } 4803 4804 // FIXME: This generated code sucks. 4805 ISD::CondCode LowCC; 4806 switch (CCCode) { 4807 default: assert(0 && "Unknown integer setcc!"); 4808 case ISD::SETLT: 4809 case ISD::SETULT: LowCC = ISD::SETULT; break; 4810 case ISD::SETGT: 4811 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4812 case ISD::SETLE: 4813 case ISD::SETULE: LowCC = ISD::SETULE; break; 4814 case ISD::SETGE: 4815 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4816 } 4817 4818 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4819 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4820 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4821 4822 // NOTE: on targets without efficient SELECT of bools, we can always use 4823 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4824 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4825 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, 4826 LowCC, false, DagCombineInfo); 4827 if (!Tmp1.Val) 4828 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 4829 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4830 CCCode, false, DagCombineInfo); 4831 if (!Tmp2.Val) 4832 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, 4833 RHSHi,CC); 4834 4835 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4836 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4837 if ((Tmp1C && Tmp1C->isNullValue()) || 4838 (Tmp2C && Tmp2C->isNullValue() && 4839 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4840 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4841 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 4842 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4843 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4844 // low part is known false, returns high part. 4845 // For LE / GE, if high part is known false, ignore the low part. 4846 // For LT / GT, if high part is known true, ignore the low part. 4847 Tmp1 = Tmp2; 4848 Tmp2 = SDOperand(); 4849 } else { 4850 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4851 ISD::SETEQ, false, DagCombineInfo); 4852 if (!Result.Val) 4853 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4854 ISD::SETEQ); 4855 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4856 Result, Tmp1, Tmp2)); 4857 Tmp1 = Result; 4858 Tmp2 = SDOperand(); 4859 } 4860 } 4861 } 4862 } 4863 LHS = Tmp1; 4864 RHS = Tmp2; 4865} 4866 4867/// EmitStackConvert - Emit a store/load combination to the stack. This stores 4868/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 4869/// a load from the stack slot to DestVT, extending it if needed. 4870/// The resultant code need not be legal. 4871SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, 4872 MVT SlotVT, 4873 MVT DestVT) { 4874 // Create the stack frame object. 4875 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment( 4876 SrcOp.getValueType().getTypeForMVT()); 4877 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 4878 4879 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 4880 int SPFI = StackPtrFI->getIndex(); 4881 4882 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 4883 unsigned SlotSize = SlotVT.getSizeInBits(); 4884 unsigned DestSize = DestVT.getSizeInBits(); 4885 const Type* SlotTy = SlotVT.getTypeForMVT(); 4886 unsigned SlotAlign = TLI.getTargetData()->getPrefTypeAlignment(SlotTy); 4887 4888 // Emit a store to the stack slot. Use a truncstore if the input value is 4889 // later than DestVT. 4890 SDOperand Store; 4891 4892 if (SrcSize > SlotSize) 4893 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 4894 PseudoSourceValue::getFixedStack(), SPFI, SlotVT, 4895 false, SlotAlign); 4896 else { 4897 assert(SrcSize == SlotSize && "Invalid store"); 4898 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 4899 PseudoSourceValue::getFixedStack(), SPFI, 4900 false, SlotAlign); 4901 } 4902 4903 // Result is a load from the stack slot. 4904 if (SlotSize == DestSize) 4905 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, SlotAlign); 4906 4907 assert(SlotSize < DestSize && "Unknown extension!"); 4908 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT, 4909 false, SlotAlign); 4910} 4911 4912SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4913 // Create a vector sized/aligned stack slot, store the value to element #0, 4914 // then load the whole vector back out. 4915 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4916 4917 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 4918 int SPFI = StackPtrFI->getIndex(); 4919 4920 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4921 PseudoSourceValue::getFixedStack(), SPFI); 4922 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 4923 PseudoSourceValue::getFixedStack(), SPFI); 4924} 4925 4926 4927/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4928/// support the operation, but do support the resultant vector type. 4929SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4930 4931 // If the only non-undef value is the low element, turn this into a 4932 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4933 unsigned NumElems = Node->getNumOperands(); 4934 bool isOnlyLowElement = true; 4935 SDOperand SplatValue = Node->getOperand(0); 4936 4937 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t> 4938 // and use a bitmask instead of a list of elements. 4939 std::map<SDOperand, std::vector<unsigned> > Values; 4940 Values[SplatValue].push_back(0); 4941 bool isConstant = true; 4942 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4943 SplatValue.getOpcode() != ISD::UNDEF) 4944 isConstant = false; 4945 4946 for (unsigned i = 1; i < NumElems; ++i) { 4947 SDOperand V = Node->getOperand(i); 4948 Values[V].push_back(i); 4949 if (V.getOpcode() != ISD::UNDEF) 4950 isOnlyLowElement = false; 4951 if (SplatValue != V) 4952 SplatValue = SDOperand(0,0); 4953 4954 // If this isn't a constant element or an undef, we can't use a constant 4955 // pool load. 4956 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4957 V.getOpcode() != ISD::UNDEF) 4958 isConstant = false; 4959 } 4960 4961 if (isOnlyLowElement) { 4962 // If the low element is an undef too, then this whole things is an undef. 4963 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4964 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4965 // Otherwise, turn this into a scalar_to_vector node. 4966 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4967 Node->getOperand(0)); 4968 } 4969 4970 // If all elements are constants, create a load from the constant pool. 4971 if (isConstant) { 4972 MVT VT = Node->getValueType(0); 4973 std::vector<Constant*> CV; 4974 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4975 if (ConstantFPSDNode *V = 4976 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4977 CV.push_back(ConstantFP::get(V->getValueAPF())); 4978 } else if (ConstantSDNode *V = 4979 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4980 CV.push_back(ConstantInt::get(V->getAPIntValue())); 4981 } else { 4982 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4983 const Type *OpNTy = 4984 Node->getOperand(0).getValueType().getTypeForMVT(); 4985 CV.push_back(UndefValue::get(OpNTy)); 4986 } 4987 } 4988 Constant *CP = ConstantVector::get(CV); 4989 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4990 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4991 PseudoSourceValue::getConstantPool(), 0); 4992 } 4993 4994 if (SplatValue.Val) { // Splat of one value? 4995 // Build the shuffle constant vector: <0, 0, 0, 0> 4996 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 4997 SDOperand Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); 4998 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4999 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5000 &ZeroVec[0], ZeroVec.size()); 5001 5002 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 5003 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 5004 // Get the splatted value into the low element of a vector register. 5005 SDOperand LowValVec = 5006 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 5007 5008 // Return shuffle(LowValVec, undef, <0,0,0,0>) 5009 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 5010 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 5011 SplatMask); 5012 } 5013 } 5014 5015 // If there are only two unique elements, we may be able to turn this into a 5016 // vector shuffle. 5017 if (Values.size() == 2) { 5018 // Get the two values in deterministic order. 5019 SDOperand Val1 = Node->getOperand(1); 5020 SDOperand Val2; 5021 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin(); 5022 if (MI->first != Val1) 5023 Val2 = MI->first; 5024 else 5025 Val2 = (++MI)->first; 5026 5027 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 5028 // vector shuffle has the undef vector on the RHS. 5029 if (Val1.getOpcode() == ISD::UNDEF) 5030 std::swap(Val1, Val2); 5031 5032 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 5033 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5034 MVT MaskEltVT = MaskVT.getVectorElementType(); 5035 std::vector<SDOperand> MaskVec(NumElems); 5036 5037 // Set elements of the shuffle mask for Val1. 5038 std::vector<unsigned> &Val1Elts = Values[Val1]; 5039 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 5040 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 5041 5042 // Set elements of the shuffle mask for Val2. 5043 std::vector<unsigned> &Val2Elts = Values[Val2]; 5044 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 5045 if (Val2.getOpcode() != ISD::UNDEF) 5046 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 5047 else 5048 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); 5049 5050 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5051 &MaskVec[0], MaskVec.size()); 5052 5053 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 5054 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 5055 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 5056 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); 5057 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); 5058 SDOperand Ops[] = { Val1, Val2, ShuffleMask }; 5059 5060 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 5061 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); 5062 } 5063 } 5064 5065 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5066 // aligned object on the stack, store each element into it, then load 5067 // the result as a vector. 5068 MVT VT = Node->getValueType(0); 5069 // Create the stack frame object. 5070 SDOperand FIPtr = DAG.CreateStackTemporary(VT); 5071 5072 // Emit a store of each element to the stack slot. 5073 SmallVector<SDOperand, 8> Stores; 5074 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8; 5075 // Store (in the right endianness) the elements to memory. 5076 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5077 // Ignore undef elements. 5078 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5079 5080 unsigned Offset = TypeByteSize*i; 5081 5082 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5083 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 5084 5085 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 5086 NULL, 0)); 5087 } 5088 5089 SDOperand StoreChain; 5090 if (!Stores.empty()) // Not all undef elements? 5091 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5092 &Stores[0], Stores.size()); 5093 else 5094 StoreChain = DAG.getEntryNode(); 5095 5096 // Result is a load from the stack slot. 5097 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 5098} 5099 5100void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5101 SDOperand Op, SDOperand Amt, 5102 SDOperand &Lo, SDOperand &Hi) { 5103 // Expand the subcomponents. 5104 SDOperand LHSL, LHSH; 5105 ExpandOp(Op, LHSL, LHSH); 5106 5107 SDOperand Ops[] = { LHSL, LHSH, Amt }; 5108 MVT VT = LHSL.getValueType(); 5109 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5110 Hi = Lo.getValue(1); 5111} 5112 5113 5114/// ExpandShift - Try to find a clever way to expand this shift operation out to 5115/// smaller elements. If we can't find a way that is more efficient than a 5116/// libcall on this target, return false. Otherwise, return true with the 5117/// low-parts expanded into Lo and Hi. 5118bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 5119 SDOperand &Lo, SDOperand &Hi) { 5120 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5121 "This is not a shift!"); 5122 5123 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5124 SDOperand ShAmt = LegalizeOp(Amt); 5125 MVT ShTy = ShAmt.getValueType(); 5126 unsigned ShBits = ShTy.getSizeInBits(); 5127 unsigned VTBits = Op.getValueType().getSizeInBits(); 5128 unsigned NVTBits = NVT.getSizeInBits(); 5129 5130 // Handle the case when Amt is an immediate. 5131 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 5132 unsigned Cst = CN->getValue(); 5133 // Expand the incoming operand to be shifted, so that we have its parts 5134 SDOperand InL, InH; 5135 ExpandOp(Op, InL, InH); 5136 switch(Opc) { 5137 case ISD::SHL: 5138 if (Cst > VTBits) { 5139 Lo = DAG.getConstant(0, NVT); 5140 Hi = DAG.getConstant(0, NVT); 5141 } else if (Cst > NVTBits) { 5142 Lo = DAG.getConstant(0, NVT); 5143 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5144 } else if (Cst == NVTBits) { 5145 Lo = DAG.getConstant(0, NVT); 5146 Hi = InL; 5147 } else { 5148 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5149 Hi = DAG.getNode(ISD::OR, NVT, 5150 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5151 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5152 } 5153 return true; 5154 case ISD::SRL: 5155 if (Cst > VTBits) { 5156 Lo = DAG.getConstant(0, NVT); 5157 Hi = DAG.getConstant(0, NVT); 5158 } else if (Cst > NVTBits) { 5159 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5160 Hi = DAG.getConstant(0, NVT); 5161 } else if (Cst == NVTBits) { 5162 Lo = InH; 5163 Hi = DAG.getConstant(0, NVT); 5164 } else { 5165 Lo = DAG.getNode(ISD::OR, NVT, 5166 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5167 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5168 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5169 } 5170 return true; 5171 case ISD::SRA: 5172 if (Cst > VTBits) { 5173 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5174 DAG.getConstant(NVTBits-1, ShTy)); 5175 } else if (Cst > NVTBits) { 5176 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5177 DAG.getConstant(Cst-NVTBits, ShTy)); 5178 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5179 DAG.getConstant(NVTBits-1, ShTy)); 5180 } else if (Cst == NVTBits) { 5181 Lo = InH; 5182 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5183 DAG.getConstant(NVTBits-1, ShTy)); 5184 } else { 5185 Lo = DAG.getNode(ISD::OR, NVT, 5186 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5187 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5188 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5189 } 5190 return true; 5191 } 5192 } 5193 5194 // Okay, the shift amount isn't constant. However, if we can tell that it is 5195 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5196 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5197 APInt KnownZero, KnownOne; 5198 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5199 5200 // If we know that if any of the high bits of the shift amount are one, then 5201 // we can do this as a couple of simple shifts. 5202 if (KnownOne.intersects(Mask)) { 5203 // Mask out the high bit, which we know is set. 5204 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5205 DAG.getConstant(~Mask, Amt.getValueType())); 5206 5207 // Expand the incoming operand to be shifted, so that we have its parts 5208 SDOperand InL, InH; 5209 ExpandOp(Op, InL, InH); 5210 switch(Opc) { 5211 case ISD::SHL: 5212 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5213 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5214 return true; 5215 case ISD::SRL: 5216 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5217 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5218 return true; 5219 case ISD::SRA: 5220 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5221 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5222 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5223 return true; 5224 } 5225 } 5226 5227 // If we know that the high bits of the shift amount are all zero, then we can 5228 // do this as a couple of simple shifts. 5229 if ((KnownZero & Mask) == Mask) { 5230 // Compute 32-amt. 5231 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5232 DAG.getConstant(NVTBits, Amt.getValueType()), 5233 Amt); 5234 5235 // Expand the incoming operand to be shifted, so that we have its parts 5236 SDOperand InL, InH; 5237 ExpandOp(Op, InL, InH); 5238 switch(Opc) { 5239 case ISD::SHL: 5240 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5241 Hi = DAG.getNode(ISD::OR, NVT, 5242 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5243 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5244 return true; 5245 case ISD::SRL: 5246 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5247 Lo = DAG.getNode(ISD::OR, NVT, 5248 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5249 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5250 return true; 5251 case ISD::SRA: 5252 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5253 Lo = DAG.getNode(ISD::OR, NVT, 5254 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5255 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5256 return true; 5257 } 5258 } 5259 5260 return false; 5261} 5262 5263 5264// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5265// does not fit into a register, return the lo part and set the hi part to the 5266// by-reg argument. If it does fit into a single register, return the result 5267// and leave the Hi part unset. 5268SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5269 bool isSigned, SDOperand &Hi) { 5270 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5271 // The input chain to this libcall is the entry node of the function. 5272 // Legalizing the call will automatically add the previous call to the 5273 // dependence. 5274 SDOperand InChain = DAG.getEntryNode(); 5275 5276 TargetLowering::ArgListTy Args; 5277 TargetLowering::ArgListEntry Entry; 5278 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5279 MVT ArgVT = Node->getOperand(i).getValueType(); 5280 const Type *ArgTy = ArgVT.getTypeForMVT(); 5281 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5282 Entry.isSExt = isSigned; 5283 Entry.isZExt = !isSigned; 5284 Args.push_back(Entry); 5285 } 5286 SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5287 TLI.getPointerTy()); 5288 5289 // Splice the libcall in wherever FindInputOutputChains tells us to. 5290 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 5291 std::pair<SDOperand,SDOperand> CallInfo = 5292 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C, 5293 false, Callee, Args, DAG); 5294 5295 // Legalize the call sequence, starting with the chain. This will advance 5296 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5297 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5298 LegalizeOp(CallInfo.second); 5299 SDOperand Result; 5300 switch (getTypeAction(CallInfo.first.getValueType())) { 5301 default: assert(0 && "Unknown thing"); 5302 case Legal: 5303 Result = CallInfo.first; 5304 break; 5305 case Expand: 5306 ExpandOp(CallInfo.first, Result, Hi); 5307 break; 5308 } 5309 return Result; 5310} 5311 5312 5313/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5314/// 5315SDOperand SelectionDAGLegalize:: 5316ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source) { 5317 MVT SourceVT = Source.getValueType(); 5318 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5319 5320 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5321 if (!isSigned && SourceVT != MVT::i32) { 5322 // The integer value loaded will be incorrectly if the 'sign bit' of the 5323 // incoming integer is set. To handle this, we dynamically test to see if 5324 // it is set, and, if so, add a fudge factor. 5325 SDOperand Hi; 5326 if (ExpandSource) { 5327 SDOperand Lo; 5328 ExpandOp(Source, Lo, Hi); 5329 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); 5330 } else { 5331 // The comparison for the sign bit will use the entire operand. 5332 Hi = Source; 5333 } 5334 5335 // If this is unsigned, and not supported, first perform the conversion to 5336 // signed, then adjust the result if the sign bit is set. 5337 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source); 5338 5339 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 5340 DAG.getConstant(0, Hi.getValueType()), 5341 ISD::SETLT); 5342 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5343 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5344 SignSet, Four, Zero); 5345 uint64_t FF = 0x5f800000ULL; 5346 if (TLI.isLittleEndian()) FF <<= 32; 5347 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5348 5349 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5350 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5351 SDOperand FudgeInReg; 5352 if (DestTy == MVT::f32) 5353 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5354 PseudoSourceValue::getConstantPool(), 0); 5355 else if (DestTy.bitsGT(MVT::f32)) 5356 // FIXME: Avoid the extend by construction the right constantpool? 5357 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5358 CPIdx, 5359 PseudoSourceValue::getConstantPool(), 0, 5360 MVT::f32); 5361 else 5362 assert(0 && "Unexpected conversion"); 5363 5364 MVT SCVT = SignedConv.getValueType(); 5365 if (SCVT != DestTy) { 5366 // Destination type needs to be expanded as well. The FADD now we are 5367 // constructing will be expanded into a libcall. 5368 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { 5369 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); 5370 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, 5371 SignedConv, SignedConv.getValue(1)); 5372 } 5373 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5374 } 5375 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5376 } 5377 5378 // Check to see if the target has a custom way to lower this. If so, use it. 5379 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 5380 default: assert(0 && "This action not implemented for this operation!"); 5381 case TargetLowering::Legal: 5382 case TargetLowering::Expand: 5383 break; // This case is handled below. 5384 case TargetLowering::Custom: { 5385 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5386 Source), DAG); 5387 if (NV.Val) 5388 return LegalizeOp(NV); 5389 break; // The target decided this was legal after all 5390 } 5391 } 5392 5393 // Expand the source, then glue it back together for the call. We must expand 5394 // the source in case it is shared (this pass of legalize must traverse it). 5395 if (ExpandSource) { 5396 SDOperand SrcLo, SrcHi; 5397 ExpandOp(Source, SrcLo, SrcHi); 5398 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); 5399 } 5400 5401 RTLIB::Libcall LC; 5402 if (SourceVT == MVT::i32) { 5403 if (DestTy == MVT::f32) 5404 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 5405 else { 5406 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 5407 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 5408 } 5409 } else if (SourceVT == MVT::i64) { 5410 if (DestTy == MVT::f32) 5411 LC = RTLIB::SINTTOFP_I64_F32; 5412 else if (DestTy == MVT::f64) 5413 LC = RTLIB::SINTTOFP_I64_F64; 5414 else if (DestTy == MVT::f80) 5415 LC = RTLIB::SINTTOFP_I64_F80; 5416 else { 5417 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 5418 LC = RTLIB::SINTTOFP_I64_PPCF128; 5419 } 5420 } else if (SourceVT == MVT::i128) { 5421 if (DestTy == MVT::f32) 5422 LC = RTLIB::SINTTOFP_I128_F32; 5423 else if (DestTy == MVT::f64) 5424 LC = RTLIB::SINTTOFP_I128_F64; 5425 else if (DestTy == MVT::f80) 5426 LC = RTLIB::SINTTOFP_I128_F80; 5427 else { 5428 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 5429 LC = RTLIB::SINTTOFP_I128_PPCF128; 5430 } 5431 } else { 5432 assert(0 && "Unknown int value type"); 5433 } 5434 5435 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 5436 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5437 SDOperand HiPart; 5438 SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart); 5439 if (Result.getValueType() != DestTy && HiPart.Val) 5440 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); 5441 return Result; 5442} 5443 5444/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5445/// INT_TO_FP operation of the specified operand when the target requests that 5446/// we expand it. At this point, we know that the result and operand types are 5447/// legal for the target. 5448SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5449 SDOperand Op0, 5450 MVT DestVT) { 5451 if (Op0.getValueType() == MVT::i32) { 5452 // simple 32-bit [signed|unsigned] integer to float/double expansion 5453 5454 // Get the stack frame index of a 8 byte buffer. 5455 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64); 5456 5457 // word offset constant for Hi/Lo address computation 5458 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5459 // set up Hi and Lo (into buffer) address based on endian 5460 SDOperand Hi = StackSlot; 5461 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5462 if (TLI.isLittleEndian()) 5463 std::swap(Hi, Lo); 5464 5465 // if signed map to unsigned space 5466 SDOperand Op0Mapped; 5467 if (isSigned) { 5468 // constant used to invert sign bit (signed to unsigned mapping) 5469 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5470 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5471 } else { 5472 Op0Mapped = Op0; 5473 } 5474 // store the lo of the constructed double - based on integer input 5475 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 5476 Op0Mapped, Lo, NULL, 0); 5477 // initial hi portion of constructed double 5478 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5479 // store the hi of the constructed double - biased exponent 5480 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5481 // load the constructed double 5482 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5483 // FP constant to bias correct the final result 5484 SDOperand Bias = DAG.getConstantFP(isSigned ? 5485 BitsToDouble(0x4330000080000000ULL) 5486 : BitsToDouble(0x4330000000000000ULL), 5487 MVT::f64); 5488 // subtract the bias 5489 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5490 // final result 5491 SDOperand Result; 5492 // handle final rounding 5493 if (DestVT == MVT::f64) { 5494 // do nothing 5495 Result = Sub; 5496 } else if (DestVT.bitsLT(MVT::f64)) { 5497 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 5498 DAG.getIntPtrConstant(0)); 5499 } else if (DestVT.bitsGT(MVT::f64)) { 5500 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5501 } 5502 return Result; 5503 } 5504 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5505 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5506 5507 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0, 5508 DAG.getConstant(0, Op0.getValueType()), 5509 ISD::SETLT); 5510 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5511 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5512 SignSet, Four, Zero); 5513 5514 // If the sign bit of the integer is set, the large number will be treated 5515 // as a negative number. To counteract this, the dynamic code adds an 5516 // offset depending on the data type. 5517 uint64_t FF; 5518 switch (Op0.getValueType().getSimpleVT()) { 5519 default: assert(0 && "Unsupported integer type!"); 5520 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5521 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5522 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5523 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5524 } 5525 if (TLI.isLittleEndian()) FF <<= 32; 5526 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5527 5528 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5529 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5530 SDOperand FudgeInReg; 5531 if (DestVT == MVT::f32) 5532 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5533 PseudoSourceValue::getConstantPool(), 0); 5534 else { 5535 FudgeInReg = 5536 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5537 DAG.getEntryNode(), CPIdx, 5538 PseudoSourceValue::getConstantPool(), 0, 5539 MVT::f32)); 5540 } 5541 5542 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5543} 5544 5545/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5546/// *INT_TO_FP operation of the specified operand when the target requests that 5547/// we promote it. At this point, we know that the result and operand types are 5548/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5549/// operation that takes a larger input. 5550SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5551 MVT DestVT, 5552 bool isSigned) { 5553 // First step, figure out the appropriate *INT_TO_FP operation to use. 5554 MVT NewInTy = LegalOp.getValueType(); 5555 5556 unsigned OpToUse = 0; 5557 5558 // Scan for the appropriate larger type to use. 5559 while (1) { 5560 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 5561 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 5562 5563 // If the target supports SINT_TO_FP of this type, use it. 5564 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5565 default: break; 5566 case TargetLowering::Legal: 5567 if (!TLI.isTypeLegal(NewInTy)) 5568 break; // Can't use this datatype. 5569 // FALL THROUGH. 5570 case TargetLowering::Custom: 5571 OpToUse = ISD::SINT_TO_FP; 5572 break; 5573 } 5574 if (OpToUse) break; 5575 if (isSigned) continue; 5576 5577 // If the target supports UINT_TO_FP of this type, use it. 5578 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5579 default: break; 5580 case TargetLowering::Legal: 5581 if (!TLI.isTypeLegal(NewInTy)) 5582 break; // Can't use this datatype. 5583 // FALL THROUGH. 5584 case TargetLowering::Custom: 5585 OpToUse = ISD::UINT_TO_FP; 5586 break; 5587 } 5588 if (OpToUse) break; 5589 5590 // Otherwise, try a larger type. 5591 } 5592 5593 // Okay, we found the operation and type to use. Zero extend our input to the 5594 // desired type then run the operation on it. 5595 return DAG.getNode(OpToUse, DestVT, 5596 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5597 NewInTy, LegalOp)); 5598} 5599 5600/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5601/// FP_TO_*INT operation of the specified operand when the target requests that 5602/// we promote it. At this point, we know that the result and operand types are 5603/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5604/// operation that returns a larger result. 5605SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5606 MVT DestVT, 5607 bool isSigned) { 5608 // First step, figure out the appropriate FP_TO*INT operation to use. 5609 MVT NewOutTy = DestVT; 5610 5611 unsigned OpToUse = 0; 5612 5613 // Scan for the appropriate larger type to use. 5614 while (1) { 5615 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 5616 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 5617 5618 // If the target supports FP_TO_SINT returning this type, use it. 5619 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5620 default: break; 5621 case TargetLowering::Legal: 5622 if (!TLI.isTypeLegal(NewOutTy)) 5623 break; // Can't use this datatype. 5624 // FALL THROUGH. 5625 case TargetLowering::Custom: 5626 OpToUse = ISD::FP_TO_SINT; 5627 break; 5628 } 5629 if (OpToUse) break; 5630 5631 // If the target supports FP_TO_UINT of this type, use it. 5632 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5633 default: break; 5634 case TargetLowering::Legal: 5635 if (!TLI.isTypeLegal(NewOutTy)) 5636 break; // Can't use this datatype. 5637 // FALL THROUGH. 5638 case TargetLowering::Custom: 5639 OpToUse = ISD::FP_TO_UINT; 5640 break; 5641 } 5642 if (OpToUse) break; 5643 5644 // Otherwise, try a larger type. 5645 } 5646 5647 5648 // Okay, we found the operation and type to use. 5649 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5650 5651 // If the operation produces an invalid type, it must be custom lowered. Use 5652 // the target lowering hooks to expand it. Just keep the low part of the 5653 // expanded operation, we know that we're truncating anyway. 5654 if (getTypeAction(NewOutTy) == Expand) { 5655 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0); 5656 assert(Operation.Val && "Didn't return anything"); 5657 } 5658 5659 // Truncate the result of the extended FP_TO_*INT operation to the desired 5660 // size. 5661 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5662} 5663 5664/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5665/// 5666SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5667 MVT VT = Op.getValueType(); 5668 MVT SHVT = TLI.getShiftAmountTy(); 5669 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5670 switch (VT.getSimpleVT()) { 5671 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5672 case MVT::i16: 5673 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5674 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5675 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5676 case MVT::i32: 5677 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5678 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5679 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5680 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5681 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5682 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5683 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5684 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5685 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5686 case MVT::i64: 5687 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5688 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5689 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5690 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5691 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5692 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5693 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5694 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5695 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5696 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5697 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5698 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5699 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5700 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5701 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5702 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5703 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5704 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5705 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5706 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5707 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5708 } 5709} 5710 5711/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5712/// 5713SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5714 switch (Opc) { 5715 default: assert(0 && "Cannot expand this yet!"); 5716 case ISD::CTPOP: { 5717 static const uint64_t mask[6] = { 5718 0x5555555555555555ULL, 0x3333333333333333ULL, 5719 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5720 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5721 }; 5722 MVT VT = Op.getValueType(); 5723 MVT ShVT = TLI.getShiftAmountTy(); 5724 unsigned len = VT.getSizeInBits(); 5725 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5726 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5727 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5728 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5729 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5730 DAG.getNode(ISD::AND, VT, 5731 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5732 } 5733 return Op; 5734 } 5735 case ISD::CTLZ: { 5736 // for now, we do this: 5737 // x = x | (x >> 1); 5738 // x = x | (x >> 2); 5739 // ... 5740 // x = x | (x >>16); 5741 // x = x | (x >>32); // for 64-bit input 5742 // return popcount(~x); 5743 // 5744 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5745 MVT VT = Op.getValueType(); 5746 MVT ShVT = TLI.getShiftAmountTy(); 5747 unsigned len = VT.getSizeInBits(); 5748 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5749 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5750 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5751 } 5752 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5753 return DAG.getNode(ISD::CTPOP, VT, Op); 5754 } 5755 case ISD::CTTZ: { 5756 // for now, we use: { return popcount(~x & (x - 1)); } 5757 // unless the target has ctlz but not ctpop, in which case we use: 5758 // { return 32 - nlz(~x & (x-1)); } 5759 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5760 MVT VT = Op.getValueType(); 5761 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5762 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5763 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5764 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5765 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5766 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5767 TLI.isOperationLegal(ISD::CTLZ, VT)) 5768 return DAG.getNode(ISD::SUB, VT, 5769 DAG.getConstant(VT.getSizeInBits(), VT), 5770 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5771 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5772 } 5773 } 5774} 5775 5776/// ExpandOp - Expand the specified SDOperand into its two component pieces 5777/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5778/// LegalizeNodes map is filled in for any results that are not expanded, the 5779/// ExpandedNodes map is filled in for any results that are expanded, and the 5780/// Lo/Hi values are returned. 5781void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5782 MVT VT = Op.getValueType(); 5783 MVT NVT = TLI.getTypeToTransformTo(VT); 5784 SDNode *Node = Op.Val; 5785 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5786 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || 5787 VT.isVector()) && "Cannot expand to FP value or to larger int value!"); 5788 5789 // See if we already expanded it. 5790 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5791 = ExpandedNodes.find(Op); 5792 if (I != ExpandedNodes.end()) { 5793 Lo = I->second.first; 5794 Hi = I->second.second; 5795 return; 5796 } 5797 5798 switch (Node->getOpcode()) { 5799 case ISD::CopyFromReg: 5800 assert(0 && "CopyFromReg must be legal!"); 5801 case ISD::FP_ROUND_INREG: 5802 if (VT == MVT::ppcf128 && 5803 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5804 TargetLowering::Custom) { 5805 SDOperand SrcLo, SrcHi, Src; 5806 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5807 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5808 SDOperand Result = TLI.LowerOperation( 5809 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5810 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5811 Lo = Result.Val->getOperand(0); 5812 Hi = Result.Val->getOperand(1); 5813 break; 5814 } 5815 // fall through 5816 default: 5817#ifndef NDEBUG 5818 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5819#endif 5820 assert(0 && "Do not know how to expand this operator!"); 5821 abort(); 5822 case ISD::EXTRACT_ELEMENT: 5823 ExpandOp(Node->getOperand(0), Lo, Hi); 5824 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 5825 return ExpandOp(Hi, Lo, Hi); 5826 return ExpandOp(Lo, Lo, Hi); 5827 case ISD::EXTRACT_VECTOR_ELT: 5828 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5829 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5830 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5831 return ExpandOp(Lo, Lo, Hi); 5832 case ISD::UNDEF: 5833 Lo = DAG.getNode(ISD::UNDEF, NVT); 5834 Hi = DAG.getNode(ISD::UNDEF, NVT); 5835 break; 5836 case ISD::Constant: { 5837 unsigned NVTBits = NVT.getSizeInBits(); 5838 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 5839 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 5840 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 5841 break; 5842 } 5843 case ISD::ConstantFP: { 5844 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5845 if (CFP->getValueType(0) == MVT::ppcf128) { 5846 APInt api = CFP->getValueAPF().convertToAPInt(); 5847 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5848 MVT::f64); 5849 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5850 MVT::f64); 5851 break; 5852 } 5853 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5854 if (getTypeAction(Lo.getValueType()) == Expand) 5855 ExpandOp(Lo, Lo, Hi); 5856 break; 5857 } 5858 case ISD::BUILD_PAIR: 5859 // Return the operands. 5860 Lo = Node->getOperand(0); 5861 Hi = Node->getOperand(1); 5862 break; 5863 5864 case ISD::MERGE_VALUES: 5865 if (Node->getNumValues() == 1) { 5866 ExpandOp(Op.getOperand(0), Lo, Hi); 5867 break; 5868 } 5869 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5870 assert(Op.ResNo == 0 && Node->getNumValues() == 2 && 5871 Op.getValue(1).getValueType() == MVT::Other && 5872 "unhandled MERGE_VALUES"); 5873 ExpandOp(Op.getOperand(0), Lo, Hi); 5874 // Remember that we legalized the chain. 5875 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5876 break; 5877 5878 case ISD::SIGN_EXTEND_INREG: 5879 ExpandOp(Node->getOperand(0), Lo, Hi); 5880 // sext_inreg the low part if needed. 5881 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5882 5883 // The high part gets the sign extension from the lo-part. This handles 5884 // things like sextinreg V:i64 from i8. 5885 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5886 DAG.getConstant(NVT.getSizeInBits()-1, 5887 TLI.getShiftAmountTy())); 5888 break; 5889 5890 case ISD::BSWAP: { 5891 ExpandOp(Node->getOperand(0), Lo, Hi); 5892 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5893 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5894 Lo = TempLo; 5895 break; 5896 } 5897 5898 case ISD::CTPOP: 5899 ExpandOp(Node->getOperand(0), Lo, Hi); 5900 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5901 DAG.getNode(ISD::CTPOP, NVT, Lo), 5902 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5903 Hi = DAG.getConstant(0, NVT); 5904 break; 5905 5906 case ISD::CTLZ: { 5907 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5908 ExpandOp(Node->getOperand(0), Lo, Hi); 5909 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 5910 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5911 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, 5912 ISD::SETNE); 5913 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5914 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5915 5916 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5917 Hi = DAG.getConstant(0, NVT); 5918 break; 5919 } 5920 5921 case ISD::CTTZ: { 5922 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5923 ExpandOp(Node->getOperand(0), Lo, Hi); 5924 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 5925 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5926 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, 5927 ISD::SETNE); 5928 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5929 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5930 5931 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5932 Hi = DAG.getConstant(0, NVT); 5933 break; 5934 } 5935 5936 case ISD::VAARG: { 5937 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5938 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5939 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5940 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5941 5942 // Remember that we legalized the chain. 5943 Hi = LegalizeOp(Hi); 5944 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5945 if (TLI.isBigEndian()) 5946 std::swap(Lo, Hi); 5947 break; 5948 } 5949 5950 case ISD::LOAD: { 5951 LoadSDNode *LD = cast<LoadSDNode>(Node); 5952 SDOperand Ch = LD->getChain(); // Legalize the chain. 5953 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5954 ISD::LoadExtType ExtType = LD->getExtensionType(); 5955 int SVOffset = LD->getSrcValueOffset(); 5956 unsigned Alignment = LD->getAlignment(); 5957 bool isVolatile = LD->isVolatile(); 5958 5959 if (ExtType == ISD::NON_EXTLOAD) { 5960 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5961 isVolatile, Alignment); 5962 if (VT == MVT::f32 || VT == MVT::f64) { 5963 // f32->i32 or f64->i64 one to one expansion. 5964 // Remember that we legalized the chain. 5965 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5966 // Recursively expand the new load. 5967 if (getTypeAction(NVT) == Expand) 5968 ExpandOp(Lo, Lo, Hi); 5969 break; 5970 } 5971 5972 // Increment the pointer to the other half. 5973 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 5974 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5975 DAG.getIntPtrConstant(IncrementSize)); 5976 SVOffset += IncrementSize; 5977 Alignment = MinAlign(Alignment, IncrementSize); 5978 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5979 isVolatile, Alignment); 5980 5981 // Build a factor node to remember that this load is independent of the 5982 // other one. 5983 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5984 Hi.getValue(1)); 5985 5986 // Remember that we legalized the chain. 5987 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5988 if (TLI.isBigEndian()) 5989 std::swap(Lo, Hi); 5990 } else { 5991 MVT EVT = LD->getMemoryVT(); 5992 5993 if ((VT == MVT::f64 && EVT == MVT::f32) || 5994 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 5995 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5996 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5997 SVOffset, isVolatile, Alignment); 5998 // Remember that we legalized the chain. 5999 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 6000 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 6001 break; 6002 } 6003 6004 if (EVT == NVT) 6005 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 6006 SVOffset, isVolatile, Alignment); 6007 else 6008 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 6009 SVOffset, EVT, isVolatile, 6010 Alignment); 6011 6012 // Remember that we legalized the chain. 6013 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 6014 6015 if (ExtType == ISD::SEXTLOAD) { 6016 // The high part is obtained by SRA'ing all but one of the bits of the 6017 // lo part. 6018 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6019 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6020 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6021 } else if (ExtType == ISD::ZEXTLOAD) { 6022 // The high part is just a zero. 6023 Hi = DAG.getConstant(0, NVT); 6024 } else /* if (ExtType == ISD::EXTLOAD) */ { 6025 // The high part is undefined. 6026 Hi = DAG.getNode(ISD::UNDEF, NVT); 6027 } 6028 } 6029 break; 6030 } 6031 case ISD::AND: 6032 case ISD::OR: 6033 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6034 SDOperand LL, LH, RL, RH; 6035 ExpandOp(Node->getOperand(0), LL, LH); 6036 ExpandOp(Node->getOperand(1), RL, RH); 6037 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 6038 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 6039 break; 6040 } 6041 case ISD::SELECT: { 6042 SDOperand LL, LH, RL, RH; 6043 ExpandOp(Node->getOperand(1), LL, LH); 6044 ExpandOp(Node->getOperand(2), RL, RH); 6045 if (getTypeAction(NVT) == Expand) 6046 NVT = TLI.getTypeToExpandTo(NVT); 6047 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 6048 if (VT != MVT::f32) 6049 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 6050 break; 6051 } 6052 case ISD::SELECT_CC: { 6053 SDOperand TL, TH, FL, FH; 6054 ExpandOp(Node->getOperand(2), TL, TH); 6055 ExpandOp(Node->getOperand(3), FL, FH); 6056 if (getTypeAction(NVT) == Expand) 6057 NVT = TLI.getTypeToExpandTo(NVT); 6058 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6059 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6060 if (VT != MVT::f32) 6061 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6062 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6063 break; 6064 } 6065 case ISD::ANY_EXTEND: 6066 // The low part is any extension of the input (which degenerates to a copy). 6067 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 6068 // The high part is undefined. 6069 Hi = DAG.getNode(ISD::UNDEF, NVT); 6070 break; 6071 case ISD::SIGN_EXTEND: { 6072 // The low part is just a sign extension of the input (which degenerates to 6073 // a copy). 6074 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 6075 6076 // The high part is obtained by SRA'ing all but one of the bits of the lo 6077 // part. 6078 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6079 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6080 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6081 break; 6082 } 6083 case ISD::ZERO_EXTEND: 6084 // The low part is just a zero extension of the input (which degenerates to 6085 // a copy). 6086 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 6087 6088 // The high part is just a zero. 6089 Hi = DAG.getConstant(0, NVT); 6090 break; 6091 6092 case ISD::TRUNCATE: { 6093 // The input value must be larger than this value. Expand *it*. 6094 SDOperand NewLo; 6095 ExpandOp(Node->getOperand(0), NewLo, Hi); 6096 6097 // The low part is now either the right size, or it is closer. If not the 6098 // right size, make an illegal truncate so we recursively expand it. 6099 if (NewLo.getValueType() != Node->getValueType(0)) 6100 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 6101 ExpandOp(NewLo, Lo, Hi); 6102 break; 6103 } 6104 6105 case ISD::BIT_CONVERT: { 6106 SDOperand Tmp; 6107 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6108 // If the target wants to, allow it to lower this itself. 6109 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6110 case Expand: assert(0 && "cannot expand FP!"); 6111 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6112 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6113 } 6114 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 6115 } 6116 6117 // f32 / f64 must be expanded to i32 / i64. 6118 if (VT == MVT::f32 || VT == MVT::f64) { 6119 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6120 if (getTypeAction(NVT) == Expand) 6121 ExpandOp(Lo, Lo, Hi); 6122 break; 6123 } 6124 6125 // If source operand will be expanded to the same type as VT, i.e. 6126 // i64 <- f64, i32 <- f32, expand the source operand instead. 6127 MVT VT0 = Node->getOperand(0).getValueType(); 6128 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6129 ExpandOp(Node->getOperand(0), Lo, Hi); 6130 break; 6131 } 6132 6133 // Turn this into a load/store pair by default. 6134 if (Tmp.Val == 0) 6135 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 6136 6137 ExpandOp(Tmp, Lo, Hi); 6138 break; 6139 } 6140 6141 case ISD::READCYCLECOUNTER: { 6142 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6143 TargetLowering::Custom && 6144 "Must custom expand ReadCycleCounter"); 6145 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 6146 assert(Tmp.Val && "Node must be custom expanded!"); 6147 ExpandOp(Tmp.getValue(0), Lo, Hi); 6148 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6149 LegalizeOp(Tmp.getValue(1))); 6150 break; 6151 } 6152 6153 case ISD::ATOMIC_CMP_SWAP: { 6154 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 6155 assert(Tmp.Val && "Node must be custom expanded!"); 6156 ExpandOp(Tmp.getValue(0), Lo, Hi); 6157 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6158 LegalizeOp(Tmp.getValue(1))); 6159 break; 6160 } 6161 6162 6163 6164 // These operators cannot be expanded directly, emit them as calls to 6165 // library functions. 6166 case ISD::FP_TO_SINT: { 6167 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6168 SDOperand Op; 6169 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6170 case Expand: assert(0 && "cannot expand FP!"); 6171 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6172 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6173 } 6174 6175 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6176 6177 // Now that the custom expander is done, expand the result, which is still 6178 // VT. 6179 if (Op.Val) { 6180 ExpandOp(Op, Lo, Hi); 6181 break; 6182 } 6183 } 6184 6185 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6186 if (VT == MVT::i64) { 6187 if (Node->getOperand(0).getValueType() == MVT::f32) 6188 LC = RTLIB::FPTOSINT_F32_I64; 6189 else if (Node->getOperand(0).getValueType() == MVT::f64) 6190 LC = RTLIB::FPTOSINT_F64_I64; 6191 else if (Node->getOperand(0).getValueType() == MVT::f80) 6192 LC = RTLIB::FPTOSINT_F80_I64; 6193 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6194 LC = RTLIB::FPTOSINT_PPCF128_I64; 6195 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6196 } else if (VT == MVT::i128) { 6197 if (Node->getOperand(0).getValueType() == MVT::f32) 6198 LC = RTLIB::FPTOSINT_F32_I128; 6199 else if (Node->getOperand(0).getValueType() == MVT::f64) 6200 LC = RTLIB::FPTOSINT_F64_I128; 6201 else if (Node->getOperand(0).getValueType() == MVT::f80) 6202 LC = RTLIB::FPTOSINT_F80_I128; 6203 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6204 LC = RTLIB::FPTOSINT_PPCF128_I128; 6205 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6206 } else { 6207 assert(0 && "Unexpected uint-to-fp conversion!"); 6208 } 6209 break; 6210 } 6211 6212 case ISD::FP_TO_UINT: { 6213 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6214 SDOperand Op; 6215 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6216 case Expand: assert(0 && "cannot expand FP!"); 6217 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6218 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6219 } 6220 6221 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6222 6223 // Now that the custom expander is done, expand the result. 6224 if (Op.Val) { 6225 ExpandOp(Op, Lo, Hi); 6226 break; 6227 } 6228 } 6229 6230 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6231 if (VT == MVT::i64) { 6232 if (Node->getOperand(0).getValueType() == MVT::f32) 6233 LC = RTLIB::FPTOUINT_F32_I64; 6234 else if (Node->getOperand(0).getValueType() == MVT::f64) 6235 LC = RTLIB::FPTOUINT_F64_I64; 6236 else if (Node->getOperand(0).getValueType() == MVT::f80) 6237 LC = RTLIB::FPTOUINT_F80_I64; 6238 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6239 LC = RTLIB::FPTOUINT_PPCF128_I64; 6240 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6241 } else if (VT == MVT::i128) { 6242 if (Node->getOperand(0).getValueType() == MVT::f32) 6243 LC = RTLIB::FPTOUINT_F32_I128; 6244 else if (Node->getOperand(0).getValueType() == MVT::f64) 6245 LC = RTLIB::FPTOUINT_F64_I128; 6246 else if (Node->getOperand(0).getValueType() == MVT::f80) 6247 LC = RTLIB::FPTOUINT_F80_I128; 6248 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6249 LC = RTLIB::FPTOUINT_PPCF128_I128; 6250 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6251 } else { 6252 assert(0 && "Unexpected uint-to-fp conversion!"); 6253 } 6254 break; 6255 } 6256 6257 case ISD::SHL: { 6258 // If the target wants custom lowering, do so. 6259 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6260 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6261 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6262 Op = TLI.LowerOperation(Op, DAG); 6263 if (Op.Val) { 6264 // Now that the custom expander is done, expand the result, which is 6265 // still VT. 6266 ExpandOp(Op, Lo, Hi); 6267 break; 6268 } 6269 } 6270 6271 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6272 // this X << 1 as X+X. 6273 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6274 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 6275 TLI.isOperationLegal(ISD::ADDE, NVT)) { 6276 SDOperand LoOps[2], HiOps[3]; 6277 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6278 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6279 LoOps[1] = LoOps[0]; 6280 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6281 6282 HiOps[1] = HiOps[0]; 6283 HiOps[2] = Lo.getValue(1); 6284 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6285 break; 6286 } 6287 } 6288 6289 // If we can emit an efficient shift operation, do so now. 6290 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6291 break; 6292 6293 // If this target supports SHL_PARTS, use it. 6294 TargetLowering::LegalizeAction Action = 6295 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6296 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6297 Action == TargetLowering::Custom) { 6298 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6299 break; 6300 } 6301 6302 // Otherwise, emit a libcall. 6303 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6304 break; 6305 } 6306 6307 case ISD::SRA: { 6308 // If the target wants custom lowering, do so. 6309 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6310 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6311 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6312 Op = TLI.LowerOperation(Op, DAG); 6313 if (Op.Val) { 6314 // Now that the custom expander is done, expand the result, which is 6315 // still VT. 6316 ExpandOp(Op, Lo, Hi); 6317 break; 6318 } 6319 } 6320 6321 // If we can emit an efficient shift operation, do so now. 6322 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6323 break; 6324 6325 // If this target supports SRA_PARTS, use it. 6326 TargetLowering::LegalizeAction Action = 6327 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6328 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6329 Action == TargetLowering::Custom) { 6330 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6331 break; 6332 } 6333 6334 // Otherwise, emit a libcall. 6335 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6336 break; 6337 } 6338 6339 case ISD::SRL: { 6340 // If the target wants custom lowering, do so. 6341 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6342 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6343 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6344 Op = TLI.LowerOperation(Op, DAG); 6345 if (Op.Val) { 6346 // Now that the custom expander is done, expand the result, which is 6347 // still VT. 6348 ExpandOp(Op, Lo, Hi); 6349 break; 6350 } 6351 } 6352 6353 // If we can emit an efficient shift operation, do so now. 6354 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6355 break; 6356 6357 // If this target supports SRL_PARTS, use it. 6358 TargetLowering::LegalizeAction Action = 6359 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6360 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6361 Action == TargetLowering::Custom) { 6362 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6363 break; 6364 } 6365 6366 // Otherwise, emit a libcall. 6367 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6368 break; 6369 } 6370 6371 case ISD::ADD: 6372 case ISD::SUB: { 6373 // If the target wants to custom expand this, let them. 6374 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6375 TargetLowering::Custom) { 6376 SDOperand Result = TLI.LowerOperation(Op, DAG); 6377 if (Result.Val) { 6378 ExpandOp(Result, Lo, Hi); 6379 break; 6380 } 6381 } 6382 6383 // Expand the subcomponents. 6384 SDOperand LHSL, LHSH, RHSL, RHSH; 6385 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6386 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6387 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6388 SDOperand LoOps[2], HiOps[3]; 6389 LoOps[0] = LHSL; 6390 LoOps[1] = RHSL; 6391 HiOps[0] = LHSH; 6392 HiOps[1] = RHSH; 6393 if (Node->getOpcode() == ISD::ADD) { 6394 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6395 HiOps[2] = Lo.getValue(1); 6396 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6397 } else { 6398 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6399 HiOps[2] = Lo.getValue(1); 6400 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6401 } 6402 break; 6403 } 6404 6405 case ISD::ADDC: 6406 case ISD::SUBC: { 6407 // Expand the subcomponents. 6408 SDOperand LHSL, LHSH, RHSL, RHSH; 6409 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6410 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6411 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6412 SDOperand LoOps[2] = { LHSL, RHSL }; 6413 SDOperand HiOps[3] = { LHSH, RHSH }; 6414 6415 if (Node->getOpcode() == ISD::ADDC) { 6416 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6417 HiOps[2] = Lo.getValue(1); 6418 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6419 } else { 6420 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6421 HiOps[2] = Lo.getValue(1); 6422 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6423 } 6424 // Remember that we legalized the flag. 6425 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6426 break; 6427 } 6428 case ISD::ADDE: 6429 case ISD::SUBE: { 6430 // Expand the subcomponents. 6431 SDOperand LHSL, LHSH, RHSL, RHSH; 6432 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6433 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6434 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6435 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 6436 SDOperand HiOps[3] = { LHSH, RHSH }; 6437 6438 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6439 HiOps[2] = Lo.getValue(1); 6440 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6441 6442 // Remember that we legalized the flag. 6443 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6444 break; 6445 } 6446 case ISD::MUL: { 6447 // If the target wants to custom expand this, let them. 6448 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6449 SDOperand New = TLI.LowerOperation(Op, DAG); 6450 if (New.Val) { 6451 ExpandOp(New, Lo, Hi); 6452 break; 6453 } 6454 } 6455 6456 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6457 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6458 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6459 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6460 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6461 SDOperand LL, LH, RL, RH; 6462 ExpandOp(Node->getOperand(0), LL, LH); 6463 ExpandOp(Node->getOperand(1), RL, RH); 6464 unsigned OuterBitSize = Op.getValueSizeInBits(); 6465 unsigned InnerBitSize = RH.getValueSizeInBits(); 6466 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6467 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6468 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 6469 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 6470 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 6471 // The inputs are both zero-extended. 6472 if (HasUMUL_LOHI) { 6473 // We can emit a umul_lohi. 6474 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6475 Hi = SDOperand(Lo.Val, 1); 6476 break; 6477 } 6478 if (HasMULHU) { 6479 // We can emit a mulhu+mul. 6480 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6481 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6482 break; 6483 } 6484 } 6485 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 6486 // The input values are both sign-extended. 6487 if (HasSMUL_LOHI) { 6488 // We can emit a smul_lohi. 6489 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6490 Hi = SDOperand(Lo.Val, 1); 6491 break; 6492 } 6493 if (HasMULHS) { 6494 // We can emit a mulhs+mul. 6495 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6496 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6497 break; 6498 } 6499 } 6500 if (HasUMUL_LOHI) { 6501 // Lo,Hi = umul LHS, RHS. 6502 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6503 DAG.getVTList(NVT, NVT), LL, RL); 6504 Lo = UMulLOHI; 6505 Hi = UMulLOHI.getValue(1); 6506 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6507 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6508 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6509 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6510 break; 6511 } 6512 if (HasMULHU) { 6513 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6514 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6515 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6516 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6517 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6518 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6519 break; 6520 } 6521 } 6522 6523 // If nothing else, we can make a libcall. 6524 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 6525 break; 6526 } 6527 case ISD::SDIV: 6528 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 6529 break; 6530 case ISD::UDIV: 6531 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 6532 break; 6533 case ISD::SREM: 6534 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 6535 break; 6536 case ISD::UREM: 6537 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 6538 break; 6539 6540 case ISD::FADD: 6541 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 6542 RTLIB::ADD_F64, 6543 RTLIB::ADD_F80, 6544 RTLIB::ADD_PPCF128), 6545 Node, false, Hi); 6546 break; 6547 case ISD::FSUB: 6548 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 6549 RTLIB::SUB_F64, 6550 RTLIB::SUB_F80, 6551 RTLIB::SUB_PPCF128), 6552 Node, false, Hi); 6553 break; 6554 case ISD::FMUL: 6555 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 6556 RTLIB::MUL_F64, 6557 RTLIB::MUL_F80, 6558 RTLIB::MUL_PPCF128), 6559 Node, false, Hi); 6560 break; 6561 case ISD::FDIV: 6562 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 6563 RTLIB::DIV_F64, 6564 RTLIB::DIV_F80, 6565 RTLIB::DIV_PPCF128), 6566 Node, false, Hi); 6567 break; 6568 case ISD::FP_EXTEND: 6569 if (VT == MVT::ppcf128) { 6570 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6571 Node->getOperand(0).getValueType()==MVT::f64); 6572 const uint64_t zero = 0; 6573 if (Node->getOperand(0).getValueType()==MVT::f32) 6574 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6575 else 6576 Hi = Node->getOperand(0); 6577 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6578 break; 6579 } 6580 Lo = ExpandLibCall(RTLIB::FPEXT_F32_F64, Node, true, Hi); 6581 break; 6582 case ISD::FP_ROUND: 6583 Lo = ExpandLibCall(RTLIB::FPROUND_F64_F32, Node, true, Hi); 6584 break; 6585 case ISD::FPOWI: 6586 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32, 6587 RTLIB::POWI_F64, 6588 RTLIB::POWI_F80, 6589 RTLIB::POWI_PPCF128), 6590 Node, false, Hi); 6591 break; 6592 case ISD::FSQRT: 6593 case ISD::FSIN: 6594 case ISD::FCOS: { 6595 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6596 switch(Node->getOpcode()) { 6597 case ISD::FSQRT: 6598 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6599 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6600 break; 6601 case ISD::FSIN: 6602 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6603 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6604 break; 6605 case ISD::FCOS: 6606 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6607 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6608 break; 6609 default: assert(0 && "Unreachable!"); 6610 } 6611 Lo = ExpandLibCall(LC, Node, false, Hi); 6612 break; 6613 } 6614 case ISD::FABS: { 6615 if (VT == MVT::ppcf128) { 6616 SDOperand Tmp; 6617 ExpandOp(Node->getOperand(0), Lo, Tmp); 6618 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6619 // lo = hi==fabs(hi) ? lo : -lo; 6620 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6621 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6622 DAG.getCondCode(ISD::SETEQ)); 6623 break; 6624 } 6625 SDOperand Mask = (VT == MVT::f64) 6626 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6627 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6628 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6629 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6630 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6631 if (getTypeAction(NVT) == Expand) 6632 ExpandOp(Lo, Lo, Hi); 6633 break; 6634 } 6635 case ISD::FNEG: { 6636 if (VT == MVT::ppcf128) { 6637 ExpandOp(Node->getOperand(0), Lo, Hi); 6638 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6639 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6640 break; 6641 } 6642 SDOperand Mask = (VT == MVT::f64) 6643 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6644 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6645 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6646 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6647 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6648 if (getTypeAction(NVT) == Expand) 6649 ExpandOp(Lo, Lo, Hi); 6650 break; 6651 } 6652 case ISD::FCOPYSIGN: { 6653 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6654 if (getTypeAction(NVT) == Expand) 6655 ExpandOp(Lo, Lo, Hi); 6656 break; 6657 } 6658 case ISD::SINT_TO_FP: 6659 case ISD::UINT_TO_FP: { 6660 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6661 MVT SrcVT = Node->getOperand(0).getValueType(); 6662 6663 // Promote the operand if needed. Do this before checking for 6664 // ppcf128 so conversions of i16 and i8 work. 6665 if (getTypeAction(SrcVT) == Promote) { 6666 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6667 Tmp = isSigned 6668 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6669 DAG.getValueType(SrcVT)) 6670 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6671 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6672 SrcVT = Node->getOperand(0).getValueType(); 6673 } 6674 6675 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 6676 static const uint64_t zero = 0; 6677 if (isSigned) { 6678 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6679 Node->getOperand(0))); 6680 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6681 } else { 6682 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6683 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6684 Node->getOperand(0))); 6685 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6686 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6687 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6688 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6689 DAG.getConstant(0, MVT::i32), 6690 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6691 DAG.getConstantFP( 6692 APFloat(APInt(128, 2, TwoE32)), 6693 MVT::ppcf128)), 6694 Hi, 6695 DAG.getCondCode(ISD::SETLT)), 6696 Lo, Hi); 6697 } 6698 break; 6699 } 6700 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6701 // si64->ppcf128 done by libcall, below 6702 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6703 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6704 Lo, Hi); 6705 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6706 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6707 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6708 DAG.getConstant(0, MVT::i64), 6709 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6710 DAG.getConstantFP( 6711 APFloat(APInt(128, 2, TwoE64)), 6712 MVT::ppcf128)), 6713 Hi, 6714 DAG.getCondCode(ISD::SETLT)), 6715 Lo, Hi); 6716 break; 6717 } 6718 6719 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6720 Node->getOperand(0)); 6721 if (getTypeAction(Lo.getValueType()) == Expand) 6722 // float to i32 etc. can be 'expanded' to a single node. 6723 ExpandOp(Lo, Lo, Hi); 6724 break; 6725 } 6726 } 6727 6728 // Make sure the resultant values have been legalized themselves, unless this 6729 // is a type that requires multi-step expansion. 6730 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6731 Lo = LegalizeOp(Lo); 6732 if (Hi.Val) 6733 // Don't legalize the high part if it is expanded to a single node. 6734 Hi = LegalizeOp(Hi); 6735 } 6736 6737 // Remember in a map if the values will be reused later. 6738 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6739 assert(isNew && "Value already expanded?!?"); 6740} 6741 6742/// SplitVectorOp - Given an operand of vector type, break it down into 6743/// two smaller values, still of vector type. 6744void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6745 SDOperand &Hi) { 6746 assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); 6747 SDNode *Node = Op.Val; 6748 unsigned NumElements = Op.getValueType().getVectorNumElements(); 6749 assert(NumElements > 1 && "Cannot split a single element vector!"); 6750 6751 MVT NewEltVT = Op.getValueType().getVectorElementType(); 6752 6753 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6754 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6755 6756 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); 6757 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); 6758 6759 // See if we already split it. 6760 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6761 = SplitNodes.find(Op); 6762 if (I != SplitNodes.end()) { 6763 Lo = I->second.first; 6764 Hi = I->second.second; 6765 return; 6766 } 6767 6768 switch (Node->getOpcode()) { 6769 default: 6770#ifndef NDEBUG 6771 Node->dump(&DAG); 6772#endif 6773 assert(0 && "Unhandled operation in SplitVectorOp!"); 6774 case ISD::UNDEF: 6775 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6776 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6777 break; 6778 case ISD::BUILD_PAIR: 6779 Lo = Node->getOperand(0); 6780 Hi = Node->getOperand(1); 6781 break; 6782 case ISD::INSERT_VECTOR_ELT: { 6783 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 6784 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6785 unsigned Index = Idx->getValue(); 6786 SDOperand ScalarOp = Node->getOperand(1); 6787 if (Index < NewNumElts_Lo) 6788 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6789 DAG.getIntPtrConstant(Index)); 6790 else 6791 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6792 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 6793 break; 6794 } 6795 SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 6796 Node->getOperand(1), 6797 Node->getOperand(2)); 6798 SplitVectorOp(Tmp, Lo, Hi); 6799 break; 6800 } 6801 case ISD::VECTOR_SHUFFLE: { 6802 // Build the low part. 6803 SDOperand Mask = Node->getOperand(2); 6804 SmallVector<SDOperand, 8> Ops; 6805 MVT PtrVT = TLI.getPointerTy(); 6806 6807 // Insert all of the elements from the input that are needed. We use 6808 // buildvector of extractelement here because the input vectors will have 6809 // to be legalized, so this makes the code simpler. 6810 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6811 SDOperand IdxNode = Mask.getOperand(i); 6812 if (IdxNode.getOpcode() == ISD::UNDEF) { 6813 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6814 continue; 6815 } 6816 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6817 SDOperand InVec = Node->getOperand(0); 6818 if (Idx >= NumElements) { 6819 InVec = Node->getOperand(1); 6820 Idx -= NumElements; 6821 } 6822 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6823 DAG.getConstant(Idx, PtrVT))); 6824 } 6825 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6826 Ops.clear(); 6827 6828 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6829 SDOperand IdxNode = Mask.getOperand(i); 6830 if (IdxNode.getOpcode() == ISD::UNDEF) { 6831 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6832 continue; 6833 } 6834 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6835 SDOperand InVec = Node->getOperand(0); 6836 if (Idx >= NumElements) { 6837 InVec = Node->getOperand(1); 6838 Idx -= NumElements; 6839 } 6840 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6841 DAG.getConstant(Idx, PtrVT))); 6842 } 6843 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6844 break; 6845 } 6846 case ISD::BUILD_VECTOR: { 6847 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6848 Node->op_begin()+NewNumElts_Lo); 6849 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6850 6851 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6852 Node->op_end()); 6853 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6854 break; 6855 } 6856 case ISD::CONCAT_VECTORS: { 6857 // FIXME: Handle non-power-of-two vectors? 6858 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6859 if (NewNumSubvectors == 1) { 6860 Lo = Node->getOperand(0); 6861 Hi = Node->getOperand(1); 6862 } else { 6863 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6864 Node->op_begin()+NewNumSubvectors); 6865 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6866 6867 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6868 Node->op_end()); 6869 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6870 } 6871 break; 6872 } 6873 case ISD::SELECT: { 6874 SDOperand Cond = Node->getOperand(0); 6875 6876 SDOperand LL, LH, RL, RH; 6877 SplitVectorOp(Node->getOperand(1), LL, LH); 6878 SplitVectorOp(Node->getOperand(2), RL, RH); 6879 6880 if (Cond.getValueType().isVector()) { 6881 // Handle a vector merge. 6882 SDOperand CL, CH; 6883 SplitVectorOp(Cond, CL, CH); 6884 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6885 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6886 } else { 6887 // Handle a simple select with vector operands. 6888 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6889 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6890 } 6891 break; 6892 } 6893 case ISD::SELECT_CC: { 6894 SDOperand CondLHS = Node->getOperand(0); 6895 SDOperand CondRHS = Node->getOperand(1); 6896 SDOperand CondCode = Node->getOperand(4); 6897 6898 SDOperand LL, LH, RL, RH; 6899 SplitVectorOp(Node->getOperand(2), LL, LH); 6900 SplitVectorOp(Node->getOperand(3), RL, RH); 6901 6902 // Handle a simple select with vector operands. 6903 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS, 6904 LL, RL, CondCode); 6905 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS, 6906 LH, RH, CondCode); 6907 break; 6908 } 6909 case ISD::VSETCC: { 6910 SDOperand LL, LH, RL, RH; 6911 SplitVectorOp(Node->getOperand(0), LL, LH); 6912 SplitVectorOp(Node->getOperand(1), RL, RH); 6913 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2)); 6914 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2)); 6915 break; 6916 } 6917 case ISD::ADD: 6918 case ISD::SUB: 6919 case ISD::MUL: 6920 case ISD::FADD: 6921 case ISD::FSUB: 6922 case ISD::FMUL: 6923 case ISD::SDIV: 6924 case ISD::UDIV: 6925 case ISD::FDIV: 6926 case ISD::FPOW: 6927 case ISD::AND: 6928 case ISD::OR: 6929 case ISD::XOR: 6930 case ISD::UREM: 6931 case ISD::SREM: 6932 case ISD::FREM: { 6933 SDOperand LL, LH, RL, RH; 6934 SplitVectorOp(Node->getOperand(0), LL, LH); 6935 SplitVectorOp(Node->getOperand(1), RL, RH); 6936 6937 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 6938 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 6939 break; 6940 } 6941 case ISD::FPOWI: { 6942 SDOperand L, H; 6943 SplitVectorOp(Node->getOperand(0), L, H); 6944 6945 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 6946 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 6947 break; 6948 } 6949 case ISD::CTTZ: 6950 case ISD::CTLZ: 6951 case ISD::CTPOP: 6952 case ISD::FNEG: 6953 case ISD::FABS: 6954 case ISD::FSQRT: 6955 case ISD::FSIN: 6956 case ISD::FCOS: 6957 case ISD::FP_TO_SINT: 6958 case ISD::FP_TO_UINT: 6959 case ISD::SINT_TO_FP: 6960 case ISD::UINT_TO_FP: { 6961 SDOperand L, H; 6962 SplitVectorOp(Node->getOperand(0), L, H); 6963 6964 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 6965 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 6966 break; 6967 } 6968 case ISD::LOAD: { 6969 LoadSDNode *LD = cast<LoadSDNode>(Node); 6970 SDOperand Ch = LD->getChain(); 6971 SDOperand Ptr = LD->getBasePtr(); 6972 const Value *SV = LD->getSrcValue(); 6973 int SVOffset = LD->getSrcValueOffset(); 6974 unsigned Alignment = LD->getAlignment(); 6975 bool isVolatile = LD->isVolatile(); 6976 6977 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6978 unsigned IncrementSize = NewNumElts_Lo * NewEltVT.getSizeInBits()/8; 6979 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6980 DAG.getIntPtrConstant(IncrementSize)); 6981 SVOffset += IncrementSize; 6982 Alignment = MinAlign(Alignment, IncrementSize); 6983 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6984 6985 // Build a factor node to remember that this load is independent of the 6986 // other one. 6987 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6988 Hi.getValue(1)); 6989 6990 // Remember that we legalized the chain. 6991 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6992 break; 6993 } 6994 case ISD::BIT_CONVERT: { 6995 // We know the result is a vector. The input may be either a vector or a 6996 // scalar value. 6997 SDOperand InOp = Node->getOperand(0); 6998 if (!InOp.getValueType().isVector() || 6999 InOp.getValueType().getVectorNumElements() == 1) { 7000 // The input is a scalar or single-element vector. 7001 // Lower to a store/load so that it can be split. 7002 // FIXME: this could be improved probably. 7003 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); 7004 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val); 7005 7006 SDOperand St = DAG.getStore(DAG.getEntryNode(), 7007 InOp, Ptr, 7008 PseudoSourceValue::getFixedStack(), 7009 FI->getIndex()); 7010 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 7011 PseudoSourceValue::getFixedStack(), 7012 FI->getIndex()); 7013 } 7014 // Split the vector and convert each of the pieces now. 7015 SplitVectorOp(InOp, Lo, Hi); 7016 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 7017 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 7018 break; 7019 } 7020 } 7021 7022 // Remember in a map if the values will be reused later. 7023 bool isNew = 7024 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7025 assert(isNew && "Value already split?!?"); 7026} 7027 7028 7029/// ScalarizeVectorOp - Given an operand of single-element vector type 7030/// (e.g. v1f32), convert it into the equivalent operation that returns a 7031/// scalar (e.g. f32) value. 7032SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 7033 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); 7034 SDNode *Node = Op.Val; 7035 MVT NewVT = Op.getValueType().getVectorElementType(); 7036 assert(Op.getValueType().getVectorNumElements() == 1); 7037 7038 // See if we already scalarized it. 7039 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 7040 if (I != ScalarizedNodes.end()) return I->second; 7041 7042 SDOperand Result; 7043 switch (Node->getOpcode()) { 7044 default: 7045#ifndef NDEBUG 7046 Node->dump(&DAG); cerr << "\n"; 7047#endif 7048 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7049 case ISD::ADD: 7050 case ISD::FADD: 7051 case ISD::SUB: 7052 case ISD::FSUB: 7053 case ISD::MUL: 7054 case ISD::FMUL: 7055 case ISD::SDIV: 7056 case ISD::UDIV: 7057 case ISD::FDIV: 7058 case ISD::SREM: 7059 case ISD::UREM: 7060 case ISD::FREM: 7061 case ISD::FPOW: 7062 case ISD::AND: 7063 case ISD::OR: 7064 case ISD::XOR: 7065 Result = DAG.getNode(Node->getOpcode(), 7066 NewVT, 7067 ScalarizeVectorOp(Node->getOperand(0)), 7068 ScalarizeVectorOp(Node->getOperand(1))); 7069 break; 7070 case ISD::FNEG: 7071 case ISD::FABS: 7072 case ISD::FSQRT: 7073 case ISD::FSIN: 7074 case ISD::FCOS: 7075 Result = DAG.getNode(Node->getOpcode(), 7076 NewVT, 7077 ScalarizeVectorOp(Node->getOperand(0))); 7078 break; 7079 case ISD::FPOWI: 7080 Result = DAG.getNode(Node->getOpcode(), 7081 NewVT, 7082 ScalarizeVectorOp(Node->getOperand(0)), 7083 Node->getOperand(1)); 7084 break; 7085 case ISD::LOAD: { 7086 LoadSDNode *LD = cast<LoadSDNode>(Node); 7087 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7088 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7089 7090 const Value *SV = LD->getSrcValue(); 7091 int SVOffset = LD->getSrcValueOffset(); 7092 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 7093 LD->isVolatile(), LD->getAlignment()); 7094 7095 // Remember that we legalized the chain. 7096 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7097 break; 7098 } 7099 case ISD::BUILD_VECTOR: 7100 Result = Node->getOperand(0); 7101 break; 7102 case ISD::INSERT_VECTOR_ELT: 7103 // Returning the inserted scalar element. 7104 Result = Node->getOperand(1); 7105 break; 7106 case ISD::CONCAT_VECTORS: 7107 assert(Node->getOperand(0).getValueType() == NewVT && 7108 "Concat of non-legal vectors not yet supported!"); 7109 Result = Node->getOperand(0); 7110 break; 7111 case ISD::VECTOR_SHUFFLE: { 7112 // Figure out if the scalar is the LHS or RHS and return it. 7113 SDOperand EltNum = Node->getOperand(2).getOperand(0); 7114 if (cast<ConstantSDNode>(EltNum)->getValue()) 7115 Result = ScalarizeVectorOp(Node->getOperand(1)); 7116 else 7117 Result = ScalarizeVectorOp(Node->getOperand(0)); 7118 break; 7119 } 7120 case ISD::EXTRACT_SUBVECTOR: 7121 Result = Node->getOperand(0); 7122 assert(Result.getValueType() == NewVT); 7123 break; 7124 case ISD::BIT_CONVERT: { 7125 SDOperand Op0 = Op.getOperand(0); 7126 if (Op0.getValueType().getVectorNumElements() == 1) 7127 Op0 = ScalarizeVectorOp(Op0); 7128 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); 7129 break; 7130 } 7131 case ISD::SELECT: 7132 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 7133 ScalarizeVectorOp(Op.getOperand(1)), 7134 ScalarizeVectorOp(Op.getOperand(2))); 7135 break; 7136 case ISD::SELECT_CC: 7137 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0), 7138 Node->getOperand(1), 7139 ScalarizeVectorOp(Op.getOperand(2)), 7140 ScalarizeVectorOp(Op.getOperand(3)), 7141 Node->getOperand(4)); 7142 break; 7143 case ISD::VSETCC: { 7144 SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0)); 7145 SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1)); 7146 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1, 7147 Op.getOperand(2)); 7148 Result = DAG.getNode(ISD::SELECT, NewVT, Result, 7149 DAG.getConstant(-1ULL, NewVT), 7150 DAG.getConstant(0ULL, NewVT)); 7151 break; 7152 } 7153 } 7154 7155 if (TLI.isTypeLegal(NewVT)) 7156 Result = LegalizeOp(Result); 7157 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7158 assert(isNew && "Value already scalarized?"); 7159 return Result; 7160} 7161 7162 7163// SelectionDAG::Legalize - This is the entry point for the file. 7164// 7165void SelectionDAG::Legalize() { 7166 if (ViewLegalizeDAGs) viewGraph(); 7167 7168 /// run - This is the main entry point to this class. 7169 /// 7170 SelectionDAGLegalize(*this).LegalizeDAG(); 7171} 7172 7173