LegalizeDAG.cpp revision c761f639f56add3f00ac84e2379d30d648a8bb81
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/DwarfWriter.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/CodeGen/PseudoSourceValue.h" 22#include "llvm/Target/TargetFrameInfo.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetData.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Target/TargetSubtarget.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/DerivedTypes.h" 31#include "llvm/Function.h" 32#include "llvm/GlobalVariable.h" 33#include "llvm/LLVMContext.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include "llvm/ADT/DenseMap.h" 40#include "llvm/ADT/SmallVector.h" 41#include "llvm/ADT/SmallPtrSet.h" 42#include <map> 43using namespace llvm; 44 45//===----------------------------------------------------------------------===// 46/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 47/// hacks on it until the target machine can handle it. This involves 48/// eliminating value sizes the machine cannot handle (promoting small sizes to 49/// large sizes or splitting up large values into small values) as well as 50/// eliminating operations the machine cannot handle. 51/// 52/// This code also does a small amount of optimization and recognition of idioms 53/// as part of its processing. For example, if a target does not support a 54/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 55/// will attempt merge setcc and brc instructions into brcc's. 56/// 57namespace { 58class SelectionDAGLegalize { 59 TargetLowering &TLI; 60 SelectionDAG &DAG; 61 CodeGenOpt::Level OptLevel; 62 63 // Libcall insertion helpers. 64 65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 66 /// legalized. We use this to ensure that calls are properly serialized 67 /// against each other, including inserted libcalls. 68 SDValue LastCALLSEQ_END; 69 70 /// IsLegalizingCall - This member is used *only* for purposes of providing 71 /// helpful assertions that a libcall isn't created while another call is 72 /// being legalized (which could lead to non-serialized call sequences). 73 bool IsLegalizingCall; 74 75 enum LegalizeAction { 76 Legal, // The target natively supports this operation. 77 Promote, // This operation should be executed in a larger type. 78 Expand // Try to expand this to other ops, otherwise use a libcall. 79 }; 80 81 /// ValueTypeActions - This is a bitvector that contains two bits for each 82 /// value type, where the two bits correspond to the LegalizeAction enum. 83 /// This can be queried with "getTypeAction(VT)". 84 TargetLowering::ValueTypeActionImpl ValueTypeActions; 85 86 /// LegalizedNodes - For nodes that are of legal width, and that have more 87 /// than one use, this map indicates what regularized operand to use. This 88 /// allows us to avoid legalizing the same thing more than once. 89 DenseMap<SDValue, SDValue> LegalizedNodes; 90 91 void AddLegalizedOperand(SDValue From, SDValue To) { 92 LegalizedNodes.insert(std::make_pair(From, To)); 93 // If someone requests legalization of the new node, return itself. 94 if (From != To) 95 LegalizedNodes.insert(std::make_pair(To, To)); 96 } 97 98public: 99 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 100 101 /// getTypeAction - Return how we should legalize values of this type, either 102 /// it is already legal or we need to expand it into multiple registers of 103 /// smaller integer type, or we need to promote it to a larger type. 104 LegalizeAction getTypeAction(EVT VT) const { 105 return 106 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT); 107 } 108 109 /// isTypeLegal - Return true if this type is legal on this target. 110 /// 111 bool isTypeLegal(EVT VT) const { 112 return getTypeAction(VT) == Legal; 113 } 114 115 void LegalizeDAG(); 116 117private: 118 /// LegalizeOp - We know that the specified value has a legal type. 119 /// Recursively ensure that the operands have legal types, then return the 120 /// result. 121 SDValue LegalizeOp(SDValue O); 122 123 SDValue OptimizeFloatStore(StoreSDNode *ST); 124 125 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 126 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 127 /// is necessary to spill the vector being inserted into to memory, perform 128 /// the insert there, and then read the result back. 129 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 130 SDValue Idx, DebugLoc dl); 131 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 132 SDValue Idx, DebugLoc dl); 133 134 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 135 /// performs the same shuffe in terms of order or result bytes, but on a type 136 /// whose vector element type is narrower than the original shuffle type. 137 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 138 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 139 SDValue N1, SDValue N2, 140 SmallVectorImpl<int> &Mask) const; 141 142 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 143 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 144 145 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 146 DebugLoc dl); 147 148 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 149 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 150 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 151 RTLIB::Libcall Call_PPCF128); 152 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 153 RTLIB::Libcall Call_I8, 154 RTLIB::Libcall Call_I16, 155 RTLIB::Libcall Call_I32, 156 RTLIB::Libcall Call_I64, 157 RTLIB::Libcall Call_I128); 158 159 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 160 SDValue ExpandBUILD_VECTOR(SDNode *Node); 161 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 162 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 163 SmallVectorImpl<SDValue> &Results); 164 SDValue ExpandFCOPYSIGN(SDNode *Node); 165 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 166 DebugLoc dl); 167 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 168 DebugLoc dl); 169 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 170 DebugLoc dl); 171 172 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 173 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 174 175 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 176 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 177 178 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 179 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 180}; 181} 182 183/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 184/// performs the same shuffe in terms of order or result bytes, but on a type 185/// whose vector element type is narrower than the original shuffle type. 186/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 187SDValue 188SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 189 SDValue N1, SDValue N2, 190 SmallVectorImpl<int> &Mask) const { 191 unsigned NumMaskElts = VT.getVectorNumElements(); 192 unsigned NumDestElts = NVT.getVectorNumElements(); 193 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 194 195 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 196 197 if (NumEltsGrowth == 1) 198 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 199 200 SmallVector<int, 8> NewMask; 201 for (unsigned i = 0; i != NumMaskElts; ++i) { 202 int Idx = Mask[i]; 203 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 204 if (Idx < 0) 205 NewMask.push_back(-1); 206 else 207 NewMask.push_back(Idx * NumEltsGrowth + j); 208 } 209 } 210 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 211 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 213} 214 215SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 216 CodeGenOpt::Level ol) 217 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), 218 ValueTypeActions(TLI.getValueTypeActions()) { 219 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 220 "Too many value types for ValueTypeActions to hold!"); 221} 222 223void SelectionDAGLegalize::LegalizeDAG() { 224 LastCALLSEQ_END = DAG.getEntryNode(); 225 IsLegalizingCall = false; 226 227 // The legalize process is inherently a bottom-up recursive process (users 228 // legalize their uses before themselves). Given infinite stack space, we 229 // could just start legalizing on the root and traverse the whole graph. In 230 // practice however, this causes us to run out of stack space on large basic 231 // blocks. To avoid this problem, compute an ordering of the nodes where each 232 // node is only legalized after all of its operands are legalized. 233 DAG.AssignTopologicalOrder(); 234 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 235 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 236 LegalizeOp(SDValue(I, 0)); 237 238 // Finally, it's possible the root changed. Get the new root. 239 SDValue OldRoot = DAG.getRoot(); 240 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 241 DAG.setRoot(LegalizedNodes[OldRoot]); 242 243 LegalizedNodes.clear(); 244 245 // Remove dead nodes now. 246 DAG.RemoveDeadNodes(); 247} 248 249 250/// FindCallEndFromCallStart - Given a chained node that is part of a call 251/// sequence, find the CALLSEQ_END node that terminates the call sequence. 252static SDNode *FindCallEndFromCallStart(SDNode *Node) { 253 if (Node->getOpcode() == ISD::CALLSEQ_END) 254 return Node; 255 if (Node->use_empty()) 256 return 0; // No CallSeqEnd 257 258 // The chain is usually at the end. 259 SDValue TheChain(Node, Node->getNumValues()-1); 260 if (TheChain.getValueType() != MVT::Other) { 261 // Sometimes it's at the beginning. 262 TheChain = SDValue(Node, 0); 263 if (TheChain.getValueType() != MVT::Other) { 264 // Otherwise, hunt for it. 265 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 266 if (Node->getValueType(i) == MVT::Other) { 267 TheChain = SDValue(Node, i); 268 break; 269 } 270 271 // Otherwise, we walked into a node without a chain. 272 if (TheChain.getValueType() != MVT::Other) 273 return 0; 274 } 275 } 276 277 for (SDNode::use_iterator UI = Node->use_begin(), 278 E = Node->use_end(); UI != E; ++UI) { 279 280 // Make sure to only follow users of our token chain. 281 SDNode *User = *UI; 282 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 283 if (User->getOperand(i) == TheChain) 284 if (SDNode *Result = FindCallEndFromCallStart(User)) 285 return Result; 286 } 287 return 0; 288} 289 290/// FindCallStartFromCallEnd - Given a chained node that is part of a call 291/// sequence, find the CALLSEQ_START node that initiates the call sequence. 292static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 293 assert(Node && "Didn't find callseq_start for a call??"); 294 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 295 296 assert(Node->getOperand(0).getValueType() == MVT::Other && 297 "Node doesn't have a token chain argument!"); 298 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 299} 300 301/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 302/// see if any uses can reach Dest. If no dest operands can get to dest, 303/// legalize them, legalize ourself, and return false, otherwise, return true. 304/// 305/// Keep track of the nodes we fine that actually do lead to Dest in 306/// NodesLeadingTo. This avoids retraversing them exponential number of times. 307/// 308bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 309 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 310 if (N == Dest) return true; // N certainly leads to Dest :) 311 312 // If we've already processed this node and it does lead to Dest, there is no 313 // need to reprocess it. 314 if (NodesLeadingTo.count(N)) return true; 315 316 // If the first result of this node has been already legalized, then it cannot 317 // reach N. 318 if (LegalizedNodes.count(SDValue(N, 0))) return false; 319 320 // Okay, this node has not already been legalized. Check and legalize all 321 // operands. If none lead to Dest, then we can legalize this node. 322 bool OperandsLeadToDest = false; 323 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 324 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 325 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 326 327 if (OperandsLeadToDest) { 328 NodesLeadingTo.insert(N); 329 return true; 330 } 331 332 // Okay, this node looks safe, legalize it and return false. 333 LegalizeOp(SDValue(N, 0)); 334 return false; 335} 336 337/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 338/// a load from the constant pool. 339static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 340 SelectionDAG &DAG, const TargetLowering &TLI) { 341 bool Extend = false; 342 DebugLoc dl = CFP->getDebugLoc(); 343 344 // If a FP immediate is precise when represented as a float and if the 345 // target can do an extending load from float to double, we put it into 346 // the constant pool as a float, even if it's is statically typed as a 347 // double. This shrinks FP constants and canonicalizes them for targets where 348 // an FP extending load is the same cost as a normal load (such as on the x87 349 // fp stack or PPC FP unit). 350 EVT VT = CFP->getValueType(0); 351 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 352 if (!UseCP) { 353 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 354 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 355 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 356 } 357 358 EVT OrigVT = VT; 359 EVT SVT = VT; 360 while (SVT != MVT::f32) { 361 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 362 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 363 // Only do this if the target has a native EXTLOAD instruction from 364 // smaller type. 365 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 366 TLI.ShouldShrinkFPConstant(OrigVT)) { 367 const Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 368 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 369 VT = SVT; 370 Extend = true; 371 } 372 } 373 374 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 375 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 376 if (Extend) 377 return DAG.getExtLoad(ISD::EXTLOAD, dl, 378 OrigVT, DAG.getEntryNode(), 379 CPIdx, PseudoSourceValue::getConstantPool(), 380 0, VT, false, false, Alignment); 381 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 382 PseudoSourceValue::getConstantPool(), 0, false, false, 383 Alignment); 384} 385 386/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 387static 388SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 389 const TargetLowering &TLI) { 390 SDValue Chain = ST->getChain(); 391 SDValue Ptr = ST->getBasePtr(); 392 SDValue Val = ST->getValue(); 393 EVT VT = Val.getValueType(); 394 int Alignment = ST->getAlignment(); 395 int SVOffset = ST->getSrcValueOffset(); 396 DebugLoc dl = ST->getDebugLoc(); 397 if (ST->getMemoryVT().isFloatingPoint() || 398 ST->getMemoryVT().isVector()) { 399 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 400 if (TLI.isTypeLegal(intVT)) { 401 // Expand to a bitconvert of the value to the integer type of the 402 // same size, then a (misaligned) int store. 403 // FIXME: Does not handle truncating floating point stores! 404 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 405 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 406 SVOffset, ST->isVolatile(), ST->isNonTemporal(), 407 Alignment); 408 } else { 409 // Do a (aligned) store to a stack slot, then copy from the stack slot 410 // to the final destination using (unaligned) integer loads and stores. 411 EVT StoredVT = ST->getMemoryVT(); 412 EVT RegVT = 413 TLI.getRegisterType(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), StoredVT.getSizeInBits())); 414 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 415 unsigned RegBytes = RegVT.getSizeInBits() / 8; 416 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 417 418 // Make sure the stack slot is also aligned for the register type. 419 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 420 421 // Perform the original store, only redirected to the stack slot. 422 SDValue Store = DAG.getTruncStore(Chain, dl, 423 Val, StackPtr, NULL, 0, StoredVT, 424 false, false, 0); 425 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 426 SmallVector<SDValue, 8> Stores; 427 unsigned Offset = 0; 428 429 // Do all but one copies using the full register width. 430 for (unsigned i = 1; i < NumRegs; i++) { 431 // Load one integer register's worth from the stack slot. 432 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0, 433 false, false, 0); 434 // Store it to the final location. Remember the store. 435 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 436 ST->getSrcValue(), SVOffset + Offset, 437 ST->isVolatile(), ST->isNonTemporal(), 438 MinAlign(ST->getAlignment(), Offset))); 439 // Increment the pointers. 440 Offset += RegBytes; 441 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 442 Increment); 443 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 444 } 445 446 // The last store may be partial. Do a truncating store. On big-endian 447 // machines this requires an extending load from the stack slot to ensure 448 // that the bits are in the right place. 449 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset)); 450 451 // Load from the stack slot. 452 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 453 NULL, 0, MemVT, false, false, 0); 454 455 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 456 ST->getSrcValue(), SVOffset + Offset, 457 MemVT, ST->isVolatile(), 458 ST->isNonTemporal(), 459 MinAlign(ST->getAlignment(), Offset))); 460 // The order of the stores doesn't matter - say it with a TokenFactor. 461 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 462 Stores.size()); 463 } 464 } 465 assert(ST->getMemoryVT().isInteger() && 466 !ST->getMemoryVT().isVector() && 467 "Unaligned store of unknown type."); 468 // Get the half-size VT 469 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 470 int NumBits = NewStoredVT.getSizeInBits(); 471 int IncrementSize = NumBits / 8; 472 473 // Divide the stored value in two parts. 474 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 475 SDValue Lo = Val; 476 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 477 478 // Store the two parts 479 SDValue Store1, Store2; 480 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 481 ST->getSrcValue(), SVOffset, NewStoredVT, 482 ST->isVolatile(), ST->isNonTemporal(), Alignment); 483 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 484 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 485 Alignment = MinAlign(Alignment, IncrementSize); 486 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 487 ST->getSrcValue(), SVOffset + IncrementSize, 488 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 489 Alignment); 490 491 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 492} 493 494/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 495static 496SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 497 const TargetLowering &TLI) { 498 int SVOffset = LD->getSrcValueOffset(); 499 SDValue Chain = LD->getChain(); 500 SDValue Ptr = LD->getBasePtr(); 501 EVT VT = LD->getValueType(0); 502 EVT LoadedVT = LD->getMemoryVT(); 503 DebugLoc dl = LD->getDebugLoc(); 504 if (VT.isFloatingPoint() || VT.isVector()) { 505 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 506 if (TLI.isTypeLegal(intVT)) { 507 // Expand to a (misaligned) integer load of the same size, 508 // then bitconvert to floating point or vector. 509 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 510 SVOffset, LD->isVolatile(), 511 LD->isNonTemporal(), LD->getAlignment()); 512 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 513 if (VT.isFloatingPoint() && LoadedVT != VT) 514 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 515 516 SDValue Ops[] = { Result, Chain }; 517 return DAG.getMergeValues(Ops, 2, dl); 518 } else { 519 // Copy the value to a (aligned) stack slot using (unaligned) integer 520 // loads and stores, then do a (aligned) load from the stack slot. 521 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 522 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 523 unsigned RegBytes = RegVT.getSizeInBits() / 8; 524 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 525 526 // Make sure the stack slot is also aligned for the register type. 527 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 528 529 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 530 SmallVector<SDValue, 8> Stores; 531 SDValue StackPtr = StackBase; 532 unsigned Offset = 0; 533 534 // Do all but one copies using the full register width. 535 for (unsigned i = 1; i < NumRegs; i++) { 536 // Load one integer register's worth from the original location. 537 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 538 SVOffset + Offset, LD->isVolatile(), 539 LD->isNonTemporal(), 540 MinAlign(LD->getAlignment(), Offset)); 541 // Follow the load with a store to the stack slot. Remember the store. 542 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 543 NULL, 0, false, false, 0)); 544 // Increment the pointers. 545 Offset += RegBytes; 546 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 547 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 548 Increment); 549 } 550 551 // The last copy may be partial. Do an extending load. 552 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (LoadedBytes - Offset)); 553 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 554 LD->getSrcValue(), SVOffset + Offset, 555 MemVT, LD->isVolatile(), 556 LD->isNonTemporal(), 557 MinAlign(LD->getAlignment(), Offset)); 558 // Follow the load with a store to the stack slot. Remember the store. 559 // On big-endian machines this requires a truncating store to ensure 560 // that the bits end up in the right place. 561 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 562 NULL, 0, MemVT, false, false, 0)); 563 564 // The order of the stores doesn't matter - say it with a TokenFactor. 565 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 566 Stores.size()); 567 568 // Finally, perform the original load only redirected to the stack slot. 569 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 570 NULL, 0, LoadedVT, false, false, 0); 571 572 // Callers expect a MERGE_VALUES node. 573 SDValue Ops[] = { Load, TF }; 574 return DAG.getMergeValues(Ops, 2, dl); 575 } 576 } 577 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 578 "Unaligned load of unsupported type."); 579 580 // Compute the new VT that is half the size of the old one. This is an 581 // integer MVT. 582 unsigned NumBits = LoadedVT.getSizeInBits(); 583 EVT NewLoadedVT; 584 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 585 NumBits >>= 1; 586 587 unsigned Alignment = LD->getAlignment(); 588 unsigned IncrementSize = NumBits / 8; 589 ISD::LoadExtType HiExtType = LD->getExtensionType(); 590 591 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 592 if (HiExtType == ISD::NON_EXTLOAD) 593 HiExtType = ISD::ZEXTLOAD; 594 595 // Load the value in two parts 596 SDValue Lo, Hi; 597 if (TLI.isLittleEndian()) { 598 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 599 SVOffset, NewLoadedVT, LD->isVolatile(), 600 LD->isNonTemporal(), Alignment); 601 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 602 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 603 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 604 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 605 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize)); 606 } else { 607 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 608 SVOffset, NewLoadedVT, LD->isVolatile(), 609 LD->isNonTemporal(), Alignment); 610 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 611 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 612 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 613 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 614 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize)); 615 } 616 617 // aggregate the two parts 618 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 619 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 620 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 621 622 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 623 Hi.getValue(1)); 624 625 SDValue Ops[] = { Result, TF }; 626 return DAG.getMergeValues(Ops, 2, dl); 627} 628 629/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 630/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 631/// is necessary to spill the vector being inserted into to memory, perform 632/// the insert there, and then read the result back. 633SDValue SelectionDAGLegalize:: 634PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 635 DebugLoc dl) { 636 SDValue Tmp1 = Vec; 637 SDValue Tmp2 = Val; 638 SDValue Tmp3 = Idx; 639 640 // If the target doesn't support this, we have to spill the input vector 641 // to a temporary stack slot, update the element, then reload it. This is 642 // badness. We could also load the value into a vector register (either 643 // with a "move to register" or "extload into register" instruction, then 644 // permute it into place, if the idx is a constant and if the idx is 645 // supported by the target. 646 EVT VT = Tmp1.getValueType(); 647 EVT EltVT = VT.getVectorElementType(); 648 EVT IdxVT = Tmp3.getValueType(); 649 EVT PtrVT = TLI.getPointerTy(); 650 SDValue StackPtr = DAG.CreateStackTemporary(VT); 651 652 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 653 654 // Store the vector. 655 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 656 PseudoSourceValue::getFixedStack(SPFI), 0, 657 false, false, 0); 658 659 // Truncate or zero extend offset to target pointer type. 660 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 661 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 662 // Add the offset to the index. 663 unsigned EltSize = EltVT.getSizeInBits()/8; 664 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 665 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 666 // Store the scalar value. 667 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 668 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT, 669 false, false, 0); 670 // Load the updated vector. 671 return DAG.getLoad(VT, dl, Ch, StackPtr, 672 PseudoSourceValue::getFixedStack(SPFI), 0, 673 false, false, 0); 674} 675 676 677SDValue SelectionDAGLegalize:: 678ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 679 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 680 // SCALAR_TO_VECTOR requires that the type of the value being inserted 681 // match the element type of the vector being created, except for 682 // integers in which case the inserted value can be over width. 683 EVT EltVT = Vec.getValueType().getVectorElementType(); 684 if (Val.getValueType() == EltVT || 685 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 686 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 687 Vec.getValueType(), Val); 688 689 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 690 // We generate a shuffle of InVec and ScVec, so the shuffle mask 691 // should be 0,1,2,3,4,5... with the appropriate element replaced with 692 // elt 0 of the RHS. 693 SmallVector<int, 8> ShufOps; 694 for (unsigned i = 0; i != NumElts; ++i) 695 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 696 697 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 698 &ShufOps[0]); 699 } 700 } 701 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 702} 703 704SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 705 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 706 // FIXME: We shouldn't do this for TargetConstantFP's. 707 // FIXME: move this to the DAG Combiner! Note that we can't regress due 708 // to phase ordering between legalized code and the dag combiner. This 709 // probably means that we need to integrate dag combiner and legalizer 710 // together. 711 // We generally can't do this one for long doubles. 712 SDValue Tmp1 = ST->getChain(); 713 SDValue Tmp2 = ST->getBasePtr(); 714 SDValue Tmp3; 715 int SVOffset = ST->getSrcValueOffset(); 716 unsigned Alignment = ST->getAlignment(); 717 bool isVolatile = ST->isVolatile(); 718 bool isNonTemporal = ST->isNonTemporal(); 719 DebugLoc dl = ST->getDebugLoc(); 720 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 721 if (CFP->getValueType(0) == MVT::f32 && 722 getTypeAction(MVT::i32) == Legal) { 723 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 724 bitcastToAPInt().zextOrTrunc(32), 725 MVT::i32); 726 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 727 SVOffset, isVolatile, isNonTemporal, Alignment); 728 } else if (CFP->getValueType(0) == MVT::f64) { 729 // If this target supports 64-bit registers, do a single 64-bit store. 730 if (getTypeAction(MVT::i64) == Legal) { 731 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 732 zextOrTrunc(64), MVT::i64); 733 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 734 SVOffset, isVolatile, isNonTemporal, Alignment); 735 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 736 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 737 // stores. If the target supports neither 32- nor 64-bits, this 738 // xform is certainly not worth it. 739 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 740 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 741 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 742 if (TLI.isBigEndian()) std::swap(Lo, Hi); 743 744 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 745 SVOffset, isVolatile, isNonTemporal, Alignment); 746 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 747 DAG.getIntPtrConstant(4)); 748 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 749 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 750 751 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 752 } 753 } 754 } 755 return SDValue(); 756} 757 758/// LegalizeOp - We know that the specified value has a legal type, and 759/// that its operands are legal. Now ensure that the operation itself 760/// is legal, recursively ensuring that the operands' operations remain 761/// legal. 762SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 763 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 764 return Op; 765 766 SDNode *Node = Op.getNode(); 767 DebugLoc dl = Node->getDebugLoc(); 768 769 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 770 assert(getTypeAction(Node->getValueType(i)) == Legal && 771 "Unexpected illegal type!"); 772 773 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 774 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 775 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 776 "Unexpected illegal type!"); 777 778 // Note that LegalizeOp may be reentered even from single-use nodes, which 779 // means that we always must cache transformed nodes. 780 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 781 if (I != LegalizedNodes.end()) return I->second; 782 783 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 784 SDValue Result = Op; 785 bool isCustom = false; 786 787 // Figure out the correct action; the way to query this varies by opcode 788 TargetLowering::LegalizeAction Action; 789 bool SimpleFinishLegalizing = true; 790 switch (Node->getOpcode()) { 791 case ISD::INTRINSIC_W_CHAIN: 792 case ISD::INTRINSIC_WO_CHAIN: 793 case ISD::INTRINSIC_VOID: 794 case ISD::VAARG: 795 case ISD::STACKSAVE: 796 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 797 break; 798 case ISD::SINT_TO_FP: 799 case ISD::UINT_TO_FP: 800 case ISD::EXTRACT_VECTOR_ELT: 801 Action = TLI.getOperationAction(Node->getOpcode(), 802 Node->getOperand(0).getValueType()); 803 break; 804 case ISD::FP_ROUND_INREG: 805 case ISD::SIGN_EXTEND_INREG: { 806 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 807 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 808 break; 809 } 810 case ISD::SELECT_CC: 811 case ISD::SETCC: 812 case ISD::BR_CC: { 813 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 814 Node->getOpcode() == ISD::SETCC ? 2 : 1; 815 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 816 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 817 ISD::CondCode CCCode = 818 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 819 Action = TLI.getCondCodeAction(CCCode, OpVT); 820 if (Action == TargetLowering::Legal) { 821 if (Node->getOpcode() == ISD::SELECT_CC) 822 Action = TLI.getOperationAction(Node->getOpcode(), 823 Node->getValueType(0)); 824 else 825 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 826 } 827 break; 828 } 829 case ISD::LOAD: 830 case ISD::STORE: 831 // FIXME: Model these properly. LOAD and STORE are complicated, and 832 // STORE expects the unlegalized operand in some cases. 833 SimpleFinishLegalizing = false; 834 break; 835 case ISD::CALLSEQ_START: 836 case ISD::CALLSEQ_END: 837 // FIXME: This shouldn't be necessary. These nodes have special properties 838 // dealing with the recursive nature of legalization. Removing this 839 // special case should be done as part of making LegalizeDAG non-recursive. 840 SimpleFinishLegalizing = false; 841 break; 842 case ISD::EXTRACT_ELEMENT: 843 case ISD::FLT_ROUNDS_: 844 case ISD::SADDO: 845 case ISD::SSUBO: 846 case ISD::UADDO: 847 case ISD::USUBO: 848 case ISD::SMULO: 849 case ISD::UMULO: 850 case ISD::FPOWI: 851 case ISD::MERGE_VALUES: 852 case ISD::EH_RETURN: 853 case ISD::FRAME_TO_ARGS_OFFSET: 854 // These operations lie about being legal: when they claim to be legal, 855 // they should actually be expanded. 856 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 857 if (Action == TargetLowering::Legal) 858 Action = TargetLowering::Expand; 859 break; 860 case ISD::TRAMPOLINE: 861 case ISD::FRAMEADDR: 862 case ISD::RETURNADDR: 863 // These operations lie about being legal: when they claim to be legal, 864 // they should actually be custom-lowered. 865 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 866 if (Action == TargetLowering::Legal) 867 Action = TargetLowering::Custom; 868 break; 869 case ISD::BUILD_VECTOR: 870 // A weird case: legalization for BUILD_VECTOR never legalizes the 871 // operands! 872 // FIXME: This really sucks... changing it isn't semantically incorrect, 873 // but it massively pessimizes the code for floating-point BUILD_VECTORs 874 // because ConstantFP operands get legalized into constant pool loads 875 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 876 // though, because BUILD_VECTORS usually get lowered into other nodes 877 // which get legalized properly. 878 SimpleFinishLegalizing = false; 879 break; 880 default: 881 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 882 Action = TargetLowering::Legal; 883 } else { 884 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 885 } 886 break; 887 } 888 889 if (SimpleFinishLegalizing) { 890 SmallVector<SDValue, 8> Ops, ResultVals; 891 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 892 Ops.push_back(LegalizeOp(Node->getOperand(i))); 893 switch (Node->getOpcode()) { 894 default: break; 895 case ISD::BR: 896 case ISD::BRIND: 897 case ISD::BR_JT: 898 case ISD::BR_CC: 899 case ISD::BRCOND: 900 // Branches tweak the chain to include LastCALLSEQ_END 901 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 902 LastCALLSEQ_END); 903 Ops[0] = LegalizeOp(Ops[0]); 904 LastCALLSEQ_END = DAG.getEntryNode(); 905 break; 906 case ISD::SHL: 907 case ISD::SRL: 908 case ISD::SRA: 909 case ISD::ROTL: 910 case ISD::ROTR: 911 // Legalizing shifts/rotates requires adjusting the shift amount 912 // to the appropriate width. 913 if (!Ops[1].getValueType().isVector()) 914 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 915 break; 916 case ISD::SRL_PARTS: 917 case ISD::SRA_PARTS: 918 case ISD::SHL_PARTS: 919 // Legalizing shifts/rotates requires adjusting the shift amount 920 // to the appropriate width. 921 if (!Ops[2].getValueType().isVector()) 922 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2])); 923 break; 924 } 925 926 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(), 927 Ops.size()); 928 switch (Action) { 929 case TargetLowering::Legal: 930 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 931 ResultVals.push_back(Result.getValue(i)); 932 break; 933 case TargetLowering::Custom: 934 // FIXME: The handling for custom lowering with multiple results is 935 // a complete mess. 936 Tmp1 = TLI.LowerOperation(Result, DAG); 937 if (Tmp1.getNode()) { 938 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 939 if (e == 1) 940 ResultVals.push_back(Tmp1); 941 else 942 ResultVals.push_back(Tmp1.getValue(i)); 943 } 944 break; 945 } 946 947 // FALL THROUGH 948 case TargetLowering::Expand: 949 ExpandNode(Result.getNode(), ResultVals); 950 break; 951 case TargetLowering::Promote: 952 PromoteNode(Result.getNode(), ResultVals); 953 break; 954 } 955 if (!ResultVals.empty()) { 956 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 957 if (ResultVals[i] != SDValue(Node, i)) 958 ResultVals[i] = LegalizeOp(ResultVals[i]); 959 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 960 } 961 return ResultVals[Op.getResNo()]; 962 } 963 } 964 965 switch (Node->getOpcode()) { 966 default: 967#ifndef NDEBUG 968 dbgs() << "NODE: "; 969 Node->dump( &DAG); 970 dbgs() << "\n"; 971#endif 972 llvm_unreachable("Do not know how to legalize this operator!"); 973 974 case ISD::BUILD_VECTOR: 975 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 976 default: llvm_unreachable("This action is not supported yet!"); 977 case TargetLowering::Custom: 978 Tmp3 = TLI.LowerOperation(Result, DAG); 979 if (Tmp3.getNode()) { 980 Result = Tmp3; 981 break; 982 } 983 // FALLTHROUGH 984 case TargetLowering::Expand: 985 Result = ExpandBUILD_VECTOR(Result.getNode()); 986 break; 987 } 988 break; 989 case ISD::CALLSEQ_START: { 990 SDNode *CallEnd = FindCallEndFromCallStart(Node); 991 992 // Recursively Legalize all of the inputs of the call end that do not lead 993 // to this call start. This ensures that any libcalls that need be inserted 994 // are inserted *before* the CALLSEQ_START. 995 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 996 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 997 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 998 NodesLeadingTo); 999 } 1000 1001 // Now that we legalized all of the inputs (which may have inserted 1002 // libcalls) create the new CALLSEQ_START node. 1003 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1004 1005 // Merge in the last call, to ensure that this call start after the last 1006 // call ended. 1007 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1008 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1009 Tmp1, LastCALLSEQ_END); 1010 Tmp1 = LegalizeOp(Tmp1); 1011 } 1012 1013 // Do not try to legalize the target-specific arguments (#1+). 1014 if (Tmp1 != Node->getOperand(0)) { 1015 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1016 Ops[0] = Tmp1; 1017 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1018 } 1019 1020 // Remember that the CALLSEQ_START is legalized. 1021 AddLegalizedOperand(Op.getValue(0), Result); 1022 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1023 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1024 1025 // Now that the callseq_start and all of the non-call nodes above this call 1026 // sequence have been legalized, legalize the call itself. During this 1027 // process, no libcalls can/will be inserted, guaranteeing that no calls 1028 // can overlap. 1029 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1030 // Note that we are selecting this call! 1031 LastCALLSEQ_END = SDValue(CallEnd, 0); 1032 IsLegalizingCall = true; 1033 1034 // Legalize the call, starting from the CALLSEQ_END. 1035 LegalizeOp(LastCALLSEQ_END); 1036 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1037 return Result; 1038 } 1039 case ISD::CALLSEQ_END: 1040 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1041 // will cause this node to be legalized as well as handling libcalls right. 1042 if (LastCALLSEQ_END.getNode() != Node) { 1043 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1044 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1045 assert(I != LegalizedNodes.end() && 1046 "Legalizing the call start should have legalized this node!"); 1047 return I->second; 1048 } 1049 1050 // Otherwise, the call start has been legalized and everything is going 1051 // according to plan. Just legalize ourselves normally here. 1052 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1053 // Do not try to legalize the target-specific arguments (#1+), except for 1054 // an optional flag input. 1055 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1056 if (Tmp1 != Node->getOperand(0)) { 1057 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1058 Ops[0] = Tmp1; 1059 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1060 } 1061 } else { 1062 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1063 if (Tmp1 != Node->getOperand(0) || 1064 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1065 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1066 Ops[0] = Tmp1; 1067 Ops.back() = Tmp2; 1068 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1069 } 1070 } 1071 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1072 // This finishes up call legalization. 1073 IsLegalizingCall = false; 1074 1075 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1076 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1077 if (Node->getNumValues() == 2) 1078 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1079 return Result.getValue(Op.getResNo()); 1080 case ISD::LOAD: { 1081 LoadSDNode *LD = cast<LoadSDNode>(Node); 1082 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1083 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1084 1085 ISD::LoadExtType ExtType = LD->getExtensionType(); 1086 if (ExtType == ISD::NON_EXTLOAD) { 1087 EVT VT = Node->getValueType(0); 1088 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1089 Tmp3 = Result.getValue(0); 1090 Tmp4 = Result.getValue(1); 1091 1092 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1093 default: llvm_unreachable("This action is not supported yet!"); 1094 case TargetLowering::Legal: 1095 // If this is an unaligned load and the target doesn't support it, 1096 // expand it. 1097 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1098 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1099 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1100 if (LD->getAlignment() < ABIAlignment){ 1101 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1102 DAG, TLI); 1103 Tmp3 = Result.getOperand(0); 1104 Tmp4 = Result.getOperand(1); 1105 Tmp3 = LegalizeOp(Tmp3); 1106 Tmp4 = LegalizeOp(Tmp4); 1107 } 1108 } 1109 break; 1110 case TargetLowering::Custom: 1111 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1112 if (Tmp1.getNode()) { 1113 Tmp3 = LegalizeOp(Tmp1); 1114 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1115 } 1116 break; 1117 case TargetLowering::Promote: { 1118 // Only promote a load of vector type to another. 1119 assert(VT.isVector() && "Cannot promote this load!"); 1120 // Change base type to a different vector type. 1121 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1122 1123 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1124 LD->getSrcValueOffset(), 1125 LD->isVolatile(), LD->isNonTemporal(), 1126 LD->getAlignment()); 1127 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1128 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1129 break; 1130 } 1131 } 1132 // Since loads produce two values, make sure to remember that we 1133 // legalized both of them. 1134 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1135 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1136 return Op.getResNo() ? Tmp4 : Tmp3; 1137 } else { 1138 EVT SrcVT = LD->getMemoryVT(); 1139 unsigned SrcWidth = SrcVT.getSizeInBits(); 1140 int SVOffset = LD->getSrcValueOffset(); 1141 unsigned Alignment = LD->getAlignment(); 1142 bool isVolatile = LD->isVolatile(); 1143 bool isNonTemporal = LD->isNonTemporal(); 1144 1145 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1146 // Some targets pretend to have an i1 loading operation, and actually 1147 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1148 // bits are guaranteed to be zero; it helps the optimizers understand 1149 // that these bits are zero. It is also useful for EXTLOAD, since it 1150 // tells the optimizers that those bits are undefined. It would be 1151 // nice to have an effective generic way of getting these benefits... 1152 // Until such a way is found, don't insist on promoting i1 here. 1153 (SrcVT != MVT::i1 || 1154 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1155 // Promote to a byte-sized load if not loading an integral number of 1156 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1157 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1158 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 1159 SDValue Ch; 1160 1161 // The extra bits are guaranteed to be zero, since we stored them that 1162 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1163 1164 ISD::LoadExtType NewExtType = 1165 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1166 1167 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 1168 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1169 NVT, isVolatile, isNonTemporal, Alignment); 1170 1171 Ch = Result.getValue(1); // The chain. 1172 1173 if (ExtType == ISD::SEXTLOAD) 1174 // Having the top bits zero doesn't help when sign extending. 1175 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1176 Result.getValueType(), 1177 Result, DAG.getValueType(SrcVT)); 1178 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1179 // All the top bits are guaranteed to be zero - inform the optimizers. 1180 Result = DAG.getNode(ISD::AssertZext, dl, 1181 Result.getValueType(), Result, 1182 DAG.getValueType(SrcVT)); 1183 1184 Tmp1 = LegalizeOp(Result); 1185 Tmp2 = LegalizeOp(Ch); 1186 } else if (SrcWidth & (SrcWidth - 1)) { 1187 // If not loading a power-of-2 number of bits, expand as two loads. 1188 assert(!SrcVT.isVector() && "Unsupported extload!"); 1189 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1190 assert(RoundWidth < SrcWidth); 1191 unsigned ExtraWidth = SrcWidth - RoundWidth; 1192 assert(ExtraWidth < RoundWidth); 1193 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1194 "Load size not an integral number of bytes!"); 1195 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1196 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1197 SDValue Lo, Hi, Ch; 1198 unsigned IncrementSize; 1199 1200 if (TLI.isLittleEndian()) { 1201 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1202 // Load the bottom RoundWidth bits. 1203 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1204 Node->getValueType(0), Tmp1, Tmp2, 1205 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1206 isNonTemporal, Alignment); 1207 1208 // Load the remaining ExtraWidth bits. 1209 IncrementSize = RoundWidth / 8; 1210 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1211 DAG.getIntPtrConstant(IncrementSize)); 1212 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1213 LD->getSrcValue(), SVOffset + IncrementSize, 1214 ExtraVT, isVolatile, isNonTemporal, 1215 MinAlign(Alignment, IncrementSize)); 1216 1217 // Build a factor node to remember that this load is independent of the 1218 // other one. 1219 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1220 Hi.getValue(1)); 1221 1222 // Move the top bits to the right place. 1223 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1224 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1225 1226 // Join the hi and lo parts. 1227 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1228 } else { 1229 // Big endian - avoid unaligned loads. 1230 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1231 // Load the top RoundWidth bits. 1232 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1233 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1234 isNonTemporal, Alignment); 1235 1236 // Load the remaining ExtraWidth bits. 1237 IncrementSize = RoundWidth / 8; 1238 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1239 DAG.getIntPtrConstant(IncrementSize)); 1240 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1241 Node->getValueType(0), Tmp1, Tmp2, 1242 LD->getSrcValue(), SVOffset + IncrementSize, 1243 ExtraVT, isVolatile, isNonTemporal, 1244 MinAlign(Alignment, IncrementSize)); 1245 1246 // Build a factor node to remember that this load is independent of the 1247 // other one. 1248 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1249 Hi.getValue(1)); 1250 1251 // Move the top bits to the right place. 1252 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1253 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1254 1255 // Join the hi and lo parts. 1256 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1257 } 1258 1259 Tmp1 = LegalizeOp(Result); 1260 Tmp2 = LegalizeOp(Ch); 1261 } else { 1262 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1263 default: llvm_unreachable("This action is not supported yet!"); 1264 case TargetLowering::Custom: 1265 isCustom = true; 1266 // FALLTHROUGH 1267 case TargetLowering::Legal: 1268 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1269 Tmp1 = Result.getValue(0); 1270 Tmp2 = Result.getValue(1); 1271 1272 if (isCustom) { 1273 Tmp3 = TLI.LowerOperation(Result, DAG); 1274 if (Tmp3.getNode()) { 1275 Tmp1 = LegalizeOp(Tmp3); 1276 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1277 } 1278 } else { 1279 // If this is an unaligned load and the target doesn't support it, 1280 // expand it. 1281 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1282 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1283 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1284 if (LD->getAlignment() < ABIAlignment){ 1285 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1286 DAG, TLI); 1287 Tmp1 = Result.getOperand(0); 1288 Tmp2 = Result.getOperand(1); 1289 Tmp1 = LegalizeOp(Tmp1); 1290 Tmp2 = LegalizeOp(Tmp2); 1291 } 1292 } 1293 } 1294 break; 1295 case TargetLowering::Expand: 1296 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1297 // f128 = EXTLOAD {f32,f64} too 1298 if ((SrcVT == MVT::f32 && (Node->getValueType(0) == MVT::f64 || 1299 Node->getValueType(0) == MVT::f128)) || 1300 (SrcVT == MVT::f64 && Node->getValueType(0) == MVT::f128)) { 1301 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1302 LD->getSrcValueOffset(), 1303 LD->isVolatile(), LD->isNonTemporal(), 1304 LD->getAlignment()); 1305 Result = DAG.getNode(ISD::FP_EXTEND, dl, 1306 Node->getValueType(0), Load); 1307 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1308 Tmp2 = LegalizeOp(Load.getValue(1)); 1309 break; 1310 } 1311 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1312 // Turn the unsupported load into an EXTLOAD followed by an explicit 1313 // zero/sign extend inreg. 1314 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1315 Tmp1, Tmp2, LD->getSrcValue(), 1316 LD->getSrcValueOffset(), SrcVT, 1317 LD->isVolatile(), LD->isNonTemporal(), 1318 LD->getAlignment()); 1319 SDValue ValRes; 1320 if (ExtType == ISD::SEXTLOAD) 1321 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1322 Result.getValueType(), 1323 Result, DAG.getValueType(SrcVT)); 1324 else 1325 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1326 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1327 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1328 break; 1329 } 1330 } 1331 1332 // Since loads produce two values, make sure to remember that we legalized 1333 // both of them. 1334 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1335 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1336 return Op.getResNo() ? Tmp2 : Tmp1; 1337 } 1338 } 1339 case ISD::STORE: { 1340 StoreSDNode *ST = cast<StoreSDNode>(Node); 1341 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1342 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1343 int SVOffset = ST->getSrcValueOffset(); 1344 unsigned Alignment = ST->getAlignment(); 1345 bool isVolatile = ST->isVolatile(); 1346 bool isNonTemporal = ST->isNonTemporal(); 1347 1348 if (!ST->isTruncatingStore()) { 1349 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1350 Result = SDValue(OptStore, 0); 1351 break; 1352 } 1353 1354 { 1355 Tmp3 = LegalizeOp(ST->getValue()); 1356 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1357 ST->getOffset()); 1358 1359 EVT VT = Tmp3.getValueType(); 1360 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1361 default: llvm_unreachable("This action is not supported yet!"); 1362 case TargetLowering::Legal: 1363 // If this is an unaligned store and the target doesn't support it, 1364 // expand it. 1365 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1366 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1367 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1368 if (ST->getAlignment() < ABIAlignment) 1369 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1370 DAG, TLI); 1371 } 1372 break; 1373 case TargetLowering::Custom: 1374 Tmp1 = TLI.LowerOperation(Result, DAG); 1375 if (Tmp1.getNode()) Result = Tmp1; 1376 break; 1377 case TargetLowering::Promote: 1378 assert(VT.isVector() && "Unknown legal promote case!"); 1379 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1380 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1381 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1382 ST->getSrcValue(), SVOffset, isVolatile, 1383 isNonTemporal, Alignment); 1384 break; 1385 } 1386 break; 1387 } 1388 } else { 1389 Tmp3 = LegalizeOp(ST->getValue()); 1390 1391 EVT StVT = ST->getMemoryVT(); 1392 unsigned StWidth = StVT.getSizeInBits(); 1393 1394 if (StWidth != StVT.getStoreSizeInBits()) { 1395 // Promote to a byte-sized store with upper bits zero if not 1396 // storing an integral number of bytes. For example, promote 1397 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1398 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StVT.getStoreSizeInBits()); 1399 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1400 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1401 SVOffset, NVT, isVolatile, isNonTemporal, 1402 Alignment); 1403 } else if (StWidth & (StWidth - 1)) { 1404 // If not storing a power-of-2 number of bits, expand as two stores. 1405 assert(!StVT.isVector() && "Unsupported truncstore!"); 1406 unsigned RoundWidth = 1 << Log2_32(StWidth); 1407 assert(RoundWidth < StWidth); 1408 unsigned ExtraWidth = StWidth - RoundWidth; 1409 assert(ExtraWidth < RoundWidth); 1410 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1411 "Store size not an integral number of bytes!"); 1412 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1413 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1414 SDValue Lo, Hi; 1415 unsigned IncrementSize; 1416 1417 if (TLI.isLittleEndian()) { 1418 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1419 // Store the bottom RoundWidth bits. 1420 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1421 SVOffset, RoundVT, 1422 isVolatile, isNonTemporal, Alignment); 1423 1424 // Store the remaining ExtraWidth bits. 1425 IncrementSize = RoundWidth / 8; 1426 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1427 DAG.getIntPtrConstant(IncrementSize)); 1428 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1429 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1430 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1431 SVOffset + IncrementSize, ExtraVT, isVolatile, 1432 isNonTemporal, 1433 MinAlign(Alignment, IncrementSize)); 1434 } else { 1435 // Big endian - avoid unaligned stores. 1436 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1437 // Store the top RoundWidth bits. 1438 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1439 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1440 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1441 SVOffset, RoundVT, isVolatile, isNonTemporal, 1442 Alignment); 1443 1444 // Store the remaining ExtraWidth bits. 1445 IncrementSize = RoundWidth / 8; 1446 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1447 DAG.getIntPtrConstant(IncrementSize)); 1448 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1449 SVOffset + IncrementSize, ExtraVT, isVolatile, 1450 isNonTemporal, 1451 MinAlign(Alignment, IncrementSize)); 1452 } 1453 1454 // The order of the stores doesn't matter. 1455 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1456 } else { 1457 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1458 Tmp2 != ST->getBasePtr()) 1459 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1460 ST->getOffset()); 1461 1462 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1463 default: llvm_unreachable("This action is not supported yet!"); 1464 case TargetLowering::Legal: 1465 // If this is an unaligned store and the target doesn't support it, 1466 // expand it. 1467 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1468 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1469 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1470 if (ST->getAlignment() < ABIAlignment) 1471 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1472 DAG, TLI); 1473 } 1474 break; 1475 case TargetLowering::Custom: 1476 Result = TLI.LowerOperation(Result, DAG); 1477 break; 1478 case Expand: 1479 // TRUNCSTORE:i16 i32 -> STORE i16 1480 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1481 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1482 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1483 SVOffset, isVolatile, isNonTemporal, 1484 Alignment); 1485 break; 1486 } 1487 } 1488 } 1489 break; 1490 } 1491 } 1492 assert(Result.getValueType() == Op.getValueType() && 1493 "Bad legalization!"); 1494 1495 // Make sure that the generated code is itself legal. 1496 if (Result != Op) 1497 Result = LegalizeOp(Result); 1498 1499 // Note that LegalizeOp may be reentered even from single-use nodes, which 1500 // means that we always must cache transformed nodes. 1501 AddLegalizedOperand(Op, Result); 1502 return Result; 1503} 1504 1505SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1506 SDValue Vec = Op.getOperand(0); 1507 SDValue Idx = Op.getOperand(1); 1508 DebugLoc dl = Op.getDebugLoc(); 1509 // Store the value to a temporary stack slot, then LOAD the returned part. 1510 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1511 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0, 1512 false, false, 0); 1513 1514 // Add the offset to the index. 1515 unsigned EltSize = 1516 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1517 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1518 DAG.getConstant(EltSize, Idx.getValueType())); 1519 1520 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1521 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1522 else 1523 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1524 1525 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1526 1527 if (Op.getValueType().isVector()) 1528 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0, 1529 false, false, 0); 1530 else 1531 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1532 NULL, 0, Vec.getValueType().getVectorElementType(), 1533 false, false, 0); 1534} 1535 1536SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1537 // We can't handle this case efficiently. Allocate a sufficiently 1538 // aligned object on the stack, store each element into it, then load 1539 // the result as a vector. 1540 // Create the stack frame object. 1541 EVT VT = Node->getValueType(0); 1542 EVT EltVT = VT.getVectorElementType(); 1543 DebugLoc dl = Node->getDebugLoc(); 1544 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1545 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1546 const Value *SV = PseudoSourceValue::getFixedStack(FI); 1547 1548 // Emit a store of each element to the stack slot. 1549 SmallVector<SDValue, 8> Stores; 1550 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1551 // Store (in the right endianness) the elements to memory. 1552 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1553 // Ignore undef elements. 1554 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1555 1556 unsigned Offset = TypeByteSize*i; 1557 1558 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1559 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1560 1561 // If the destination vector element type is narrower than the source 1562 // element type, only store the bits necessary. 1563 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1564 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1565 Node->getOperand(i), Idx, SV, Offset, 1566 EltVT, false, false, 0)); 1567 } else 1568 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1569 Node->getOperand(i), Idx, SV, Offset, 1570 false, false, 0)); 1571 } 1572 1573 SDValue StoreChain; 1574 if (!Stores.empty()) // Not all undef elements? 1575 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1576 &Stores[0], Stores.size()); 1577 else 1578 StoreChain = DAG.getEntryNode(); 1579 1580 // Result is a load from the stack slot. 1581 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0, false, false, 0); 1582} 1583 1584SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1585 DebugLoc dl = Node->getDebugLoc(); 1586 SDValue Tmp1 = Node->getOperand(0); 1587 SDValue Tmp2 = Node->getOperand(1); 1588 1589 // Get the sign bit of the RHS. First obtain a value that has the same 1590 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1591 SDValue SignBit; 1592 EVT FloatVT = Tmp2.getValueType(); 1593 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1594 if (isTypeLegal(IVT)) { 1595 // Convert to an integer with the same sign bit. 1596 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1597 } else { 1598 // Store the float to memory, then load the sign part out as an integer. 1599 MVT LoadTy = TLI.getPointerTy(); 1600 // First create a temporary that is aligned for both the load and store. 1601 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1602 // Then store the float to it. 1603 SDValue Ch = 1604 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL, 0, 1605 false, false, 0); 1606 if (TLI.isBigEndian()) { 1607 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1608 // Load out a legal integer with the same sign bit as the float. 1609 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, NULL, 0, false, false, 0); 1610 } else { // Little endian 1611 SDValue LoadPtr = StackPtr; 1612 // The float may be wider than the integer we are going to load. Advance 1613 // the pointer so that the loaded integer will contain the sign bit. 1614 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1615 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1616 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1617 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1618 // Load a legal integer containing the sign bit. 1619 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, NULL, 0, false, false, 0); 1620 // Move the sign bit to the top bit of the loaded integer. 1621 unsigned BitShift = LoadTy.getSizeInBits() - 1622 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1623 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1624 if (BitShift) 1625 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1626 DAG.getConstant(BitShift,TLI.getShiftAmountTy())); 1627 } 1628 } 1629 // Now get the sign bit proper, by seeing whether the value is negative. 1630 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1631 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1632 ISD::SETLT); 1633 // Get the absolute value of the result. 1634 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1635 // Select between the nabs and abs value based on the sign bit of 1636 // the input. 1637 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1638 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1639 AbsVal); 1640} 1641 1642void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1643 SmallVectorImpl<SDValue> &Results) { 1644 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1645 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1646 " not tell us which reg is the stack pointer!"); 1647 DebugLoc dl = Node->getDebugLoc(); 1648 EVT VT = Node->getValueType(0); 1649 SDValue Tmp1 = SDValue(Node, 0); 1650 SDValue Tmp2 = SDValue(Node, 1); 1651 SDValue Tmp3 = Node->getOperand(2); 1652 SDValue Chain = Tmp1.getOperand(0); 1653 1654 // Chain the dynamic stack allocation so that it doesn't modify the stack 1655 // pointer when other instructions are using the stack. 1656 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1657 1658 SDValue Size = Tmp2.getOperand(1); 1659 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1660 Chain = SP.getValue(1); 1661 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1662 unsigned StackAlign = 1663 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1664 if (Align > StackAlign) 1665 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1666 DAG.getConstant(-(uint64_t)Align, VT)); 1667 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1668 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1669 1670 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1671 DAG.getIntPtrConstant(0, true), SDValue()); 1672 1673 Results.push_back(Tmp1); 1674 Results.push_back(Tmp2); 1675} 1676 1677/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1678/// condition code CC on the current target. This routine expands SETCC with 1679/// illegal condition code into AND / OR of multiple SETCC values. 1680void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1681 SDValue &LHS, SDValue &RHS, 1682 SDValue &CC, 1683 DebugLoc dl) { 1684 EVT OpVT = LHS.getValueType(); 1685 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1686 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1687 default: llvm_unreachable("Unknown condition code action!"); 1688 case TargetLowering::Legal: 1689 // Nothing to do. 1690 break; 1691 case TargetLowering::Expand: { 1692 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1693 unsigned Opc = 0; 1694 switch (CCCode) { 1695 default: llvm_unreachable("Don't know how to expand this condition!"); 1696 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1697 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1698 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1699 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1700 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1701 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1702 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1703 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1704 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1705 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1706 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1707 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1708 // FIXME: Implement more expansions. 1709 } 1710 1711 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1712 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1713 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1714 RHS = SDValue(); 1715 CC = SDValue(); 1716 break; 1717 } 1718 } 1719} 1720 1721/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1722/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1723/// a load from the stack slot to DestVT, extending it if needed. 1724/// The resultant code need not be legal. 1725SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1726 EVT SlotVT, 1727 EVT DestVT, 1728 DebugLoc dl) { 1729 // Create the stack frame object. 1730 unsigned SrcAlign = 1731 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1732 getTypeForEVT(*DAG.getContext())); 1733 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1734 1735 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1736 int SPFI = StackPtrFI->getIndex(); 1737 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1738 1739 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1740 unsigned SlotSize = SlotVT.getSizeInBits(); 1741 unsigned DestSize = DestVT.getSizeInBits(); 1742 unsigned DestAlign = 1743 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT(*DAG.getContext())); 1744 1745 // Emit a store to the stack slot. Use a truncstore if the input value is 1746 // later than DestVT. 1747 SDValue Store; 1748 1749 if (SrcSize > SlotSize) 1750 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1751 SV, 0, SlotVT, false, false, SrcAlign); 1752 else { 1753 assert(SrcSize == SlotSize && "Invalid store"); 1754 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1755 SV, 0, false, false, SrcAlign); 1756 } 1757 1758 // Result is a load from the stack slot. 1759 if (SlotSize == DestSize) 1760 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, false, 1761 DestAlign); 1762 1763 assert(SlotSize < DestSize && "Unknown extension!"); 1764 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, 1765 false, false, DestAlign); 1766} 1767 1768SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1769 DebugLoc dl = Node->getDebugLoc(); 1770 // Create a vector sized/aligned stack slot, store the value to element #0, 1771 // then load the whole vector back out. 1772 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1773 1774 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1775 int SPFI = StackPtrFI->getIndex(); 1776 1777 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1778 StackPtr, 1779 PseudoSourceValue::getFixedStack(SPFI), 0, 1780 Node->getValueType(0).getVectorElementType(), 1781 false, false, 0); 1782 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1783 PseudoSourceValue::getFixedStack(SPFI), 0, 1784 false, false, 0); 1785} 1786 1787 1788/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1789/// support the operation, but do support the resultant vector type. 1790SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1791 unsigned NumElems = Node->getNumOperands(); 1792 SDValue Value1, Value2; 1793 DebugLoc dl = Node->getDebugLoc(); 1794 EVT VT = Node->getValueType(0); 1795 EVT OpVT = Node->getOperand(0).getValueType(); 1796 EVT EltVT = VT.getVectorElementType(); 1797 1798 // If the only non-undef value is the low element, turn this into a 1799 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1800 bool isOnlyLowElement = true; 1801 bool MoreThanTwoValues = false; 1802 bool isConstant = true; 1803 for (unsigned i = 0; i < NumElems; ++i) { 1804 SDValue V = Node->getOperand(i); 1805 if (V.getOpcode() == ISD::UNDEF) 1806 continue; 1807 if (i > 0) 1808 isOnlyLowElement = false; 1809 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1810 isConstant = false; 1811 1812 if (!Value1.getNode()) { 1813 Value1 = V; 1814 } else if (!Value2.getNode()) { 1815 if (V != Value1) 1816 Value2 = V; 1817 } else if (V != Value1 && V != Value2) { 1818 MoreThanTwoValues = true; 1819 } 1820 } 1821 1822 if (!Value1.getNode()) 1823 return DAG.getUNDEF(VT); 1824 1825 if (isOnlyLowElement) 1826 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1827 1828 // If all elements are constants, create a load from the constant pool. 1829 if (isConstant) { 1830 std::vector<Constant*> CV; 1831 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1832 if (ConstantFPSDNode *V = 1833 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1834 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1835 } else if (ConstantSDNode *V = 1836 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1837 if (OpVT==EltVT) 1838 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1839 else { 1840 // If OpVT and EltVT don't match, EltVT is not legal and the 1841 // element values have been promoted/truncated earlier. Undo this; 1842 // we don't want a v16i8 to become a v16i32 for example. 1843 const ConstantInt *CI = V->getConstantIntValue(); 1844 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1845 CI->getZExtValue())); 1846 } 1847 } else { 1848 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1849 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1850 CV.push_back(UndefValue::get(OpNTy)); 1851 } 1852 } 1853 Constant *CP = ConstantVector::get(CV); 1854 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1855 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1856 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1857 PseudoSourceValue::getConstantPool(), 0, 1858 false, false, Alignment); 1859 } 1860 1861 if (!MoreThanTwoValues) { 1862 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1863 for (unsigned i = 0; i < NumElems; ++i) { 1864 SDValue V = Node->getOperand(i); 1865 if (V.getOpcode() == ISD::UNDEF) 1866 continue; 1867 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1868 } 1869 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1870 // Get the splatted value into the low element of a vector register. 1871 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1872 SDValue Vec2; 1873 if (Value2.getNode()) 1874 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1875 else 1876 Vec2 = DAG.getUNDEF(VT); 1877 1878 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1879 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1880 } 1881 } 1882 1883 // Otherwise, we can't handle this case efficiently. 1884 return ExpandVectorBuildThroughStack(Node); 1885} 1886 1887// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1888// does not fit into a register, return the lo part and set the hi part to the 1889// by-reg argument. If it does fit into a single register, return the result 1890// and leave the Hi part unset. 1891SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1892 bool isSigned) { 1893 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1894 // The input chain to this libcall is the entry node of the function. 1895 // Legalizing the call will automatically add the previous call to the 1896 // dependence. 1897 SDValue InChain = DAG.getEntryNode(); 1898 1899 TargetLowering::ArgListTy Args; 1900 TargetLowering::ArgListEntry Entry; 1901 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1902 EVT ArgVT = Node->getOperand(i).getValueType(); 1903 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1904 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1905 Entry.isSExt = isSigned; 1906 Entry.isZExt = !isSigned; 1907 Args.push_back(Entry); 1908 } 1909 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1910 TLI.getPointerTy()); 1911 1912 // Splice the libcall in wherever FindInputOutputChains tells us to. 1913 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1914 std::pair<SDValue, SDValue> CallInfo = 1915 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1916 0, TLI.getLibcallCallingConv(LC), false, 1917 /*isReturnValueUsed=*/true, 1918 Callee, Args, DAG, Node->getDebugLoc()); 1919 1920 // Legalize the call sequence, starting with the chain. This will advance 1921 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1922 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1923 LegalizeOp(CallInfo.second); 1924 return CallInfo.first; 1925} 1926 1927SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1928 RTLIB::Libcall Call_F32, 1929 RTLIB::Libcall Call_F64, 1930 RTLIB::Libcall Call_F80, 1931 RTLIB::Libcall Call_PPCF128) { 1932 RTLIB::Libcall LC; 1933 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1934 default: llvm_unreachable("Unexpected request for libcall!"); 1935 case MVT::f32: LC = Call_F32; break; 1936 case MVT::f64: LC = Call_F64; break; 1937 case MVT::f80: LC = Call_F80; break; 1938 case MVT::ppcf128: LC = Call_PPCF128; break; 1939 } 1940 return ExpandLibCall(LC, Node, false); 1941} 1942 1943SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 1944 RTLIB::Libcall Call_I8, 1945 RTLIB::Libcall Call_I16, 1946 RTLIB::Libcall Call_I32, 1947 RTLIB::Libcall Call_I64, 1948 RTLIB::Libcall Call_I128) { 1949 RTLIB::Libcall LC; 1950 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1951 default: llvm_unreachable("Unexpected request for libcall!"); 1952 case MVT::i8: LC = Call_I8; break; 1953 case MVT::i16: LC = Call_I16; break; 1954 case MVT::i32: LC = Call_I32; break; 1955 case MVT::i64: LC = Call_I64; break; 1956 case MVT::i128: LC = Call_I128; break; 1957 } 1958 return ExpandLibCall(LC, Node, isSigned); 1959} 1960 1961/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 1962/// INT_TO_FP operation of the specified operand when the target requests that 1963/// we expand it. At this point, we know that the result and operand types are 1964/// legal for the target. 1965SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 1966 SDValue Op0, 1967 EVT DestVT, 1968 DebugLoc dl) { 1969 if (Op0.getValueType() == MVT::i32) { 1970 // simple 32-bit [signed|unsigned] integer to float/double expansion 1971 1972 // Get the stack frame index of a 8 byte buffer. 1973 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 1974 1975 // word offset constant for Hi/Lo address computation 1976 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 1977 // set up Hi and Lo (into buffer) address based on endian 1978 SDValue Hi = StackSlot; 1979 SDValue Lo = DAG.getNode(ISD::ADD, dl, 1980 TLI.getPointerTy(), StackSlot, WordOff); 1981 if (TLI.isLittleEndian()) 1982 std::swap(Hi, Lo); 1983 1984 // if signed map to unsigned space 1985 SDValue Op0Mapped; 1986 if (isSigned) { 1987 // constant used to invert sign bit (signed to unsigned mapping) 1988 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 1989 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 1990 } else { 1991 Op0Mapped = Op0; 1992 } 1993 // store the lo of the constructed double - based on integer input 1994 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 1995 Op0Mapped, Lo, NULL, 0, 1996 false, false, 0); 1997 // initial hi portion of constructed double 1998 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 1999 // store the hi of the constructed double - biased exponent 2000 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0, 2001 false, false, 0); 2002 // load the constructed double 2003 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0, 2004 false, false, 0); 2005 // FP constant to bias correct the final result 2006 SDValue Bias = DAG.getConstantFP(isSigned ? 2007 BitsToDouble(0x4330000080000000ULL) : 2008 BitsToDouble(0x4330000000000000ULL), 2009 MVT::f64); 2010 // subtract the bias 2011 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2012 // final result 2013 SDValue Result; 2014 // handle final rounding 2015 if (DestVT == MVT::f64) { 2016 // do nothing 2017 Result = Sub; 2018 } else if (DestVT.bitsLT(MVT::f64)) { 2019 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2020 DAG.getIntPtrConstant(0)); 2021 } else if (DestVT.bitsGT(MVT::f64)) { 2022 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2023 } 2024 return Result; 2025 } 2026 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2027 2028 // Implementation of unsigned i64 to f64 following the algorithm in 2029 // __floatundidf in compiler_rt. This implementation has the advantage 2030 // of performing rounding correctly, both in the default rounding mode 2031 // and in all alternate rounding modes. 2032 // TODO: Generalize this for use with other types. 2033 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2034 SDValue TwoP52 = 2035 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2036 SDValue TwoP84PlusTwoP52 = 2037 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2038 SDValue TwoP84 = 2039 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2040 2041 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2042 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2043 DAG.getConstant(32, MVT::i64)); 2044 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2045 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2046 SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr); 2047 SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr); 2048 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, TwoP84PlusTwoP52); 2049 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2050 } 2051 2052 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2053 2054 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2055 Op0, DAG.getConstant(0, Op0.getValueType()), 2056 ISD::SETLT); 2057 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2058 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2059 SignSet, Four, Zero); 2060 2061 // If the sign bit of the integer is set, the large number will be treated 2062 // as a negative number. To counteract this, the dynamic code adds an 2063 // offset depending on the data type. 2064 uint64_t FF; 2065 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2066 default: llvm_unreachable("Unsupported integer type!"); 2067 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2068 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2069 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2070 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2071 } 2072 if (TLI.isLittleEndian()) FF <<= 32; 2073 Constant *FudgeFactor = ConstantInt::get( 2074 Type::getInt64Ty(*DAG.getContext()), FF); 2075 2076 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2077 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2078 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2079 Alignment = std::min(Alignment, 4u); 2080 SDValue FudgeInReg; 2081 if (DestVT == MVT::f32) 2082 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2083 PseudoSourceValue::getConstantPool(), 0, 2084 false, false, Alignment); 2085 else { 2086 FudgeInReg = 2087 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2088 DAG.getEntryNode(), CPIdx, 2089 PseudoSourceValue::getConstantPool(), 0, 2090 MVT::f32, false, false, Alignment)); 2091 } 2092 2093 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2094} 2095 2096/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2097/// *INT_TO_FP operation of the specified operand when the target requests that 2098/// we promote it. At this point, we know that the result and operand types are 2099/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2100/// operation that takes a larger input. 2101SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2102 EVT DestVT, 2103 bool isSigned, 2104 DebugLoc dl) { 2105 // First step, figure out the appropriate *INT_TO_FP operation to use. 2106 EVT NewInTy = LegalOp.getValueType(); 2107 2108 unsigned OpToUse = 0; 2109 2110 // Scan for the appropriate larger type to use. 2111 while (1) { 2112 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2113 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2114 2115 // If the target supports SINT_TO_FP of this type, use it. 2116 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2117 OpToUse = ISD::SINT_TO_FP; 2118 break; 2119 } 2120 if (isSigned) continue; 2121 2122 // If the target supports UINT_TO_FP of this type, use it. 2123 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2124 OpToUse = ISD::UINT_TO_FP; 2125 break; 2126 } 2127 2128 // Otherwise, try a larger type. 2129 } 2130 2131 // Okay, we found the operation and type to use. Zero extend our input to the 2132 // desired type then run the operation on it. 2133 return DAG.getNode(OpToUse, dl, DestVT, 2134 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2135 dl, NewInTy, LegalOp)); 2136} 2137 2138/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2139/// FP_TO_*INT operation of the specified operand when the target requests that 2140/// we promote it. At this point, we know that the result and operand types are 2141/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2142/// operation that returns a larger result. 2143SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2144 EVT DestVT, 2145 bool isSigned, 2146 DebugLoc dl) { 2147 // First step, figure out the appropriate FP_TO*INT operation to use. 2148 EVT NewOutTy = DestVT; 2149 2150 unsigned OpToUse = 0; 2151 2152 // Scan for the appropriate larger type to use. 2153 while (1) { 2154 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2155 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2156 2157 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2158 OpToUse = ISD::FP_TO_SINT; 2159 break; 2160 } 2161 2162 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2163 OpToUse = ISD::FP_TO_UINT; 2164 break; 2165 } 2166 2167 // Otherwise, try a larger type. 2168 } 2169 2170 2171 // Okay, we found the operation and type to use. 2172 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2173 2174 // Truncate the result of the extended FP_TO_*INT operation to the desired 2175 // size. 2176 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2177} 2178 2179/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2180/// 2181SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2182 EVT VT = Op.getValueType(); 2183 EVT SHVT = TLI.getShiftAmountTy(); 2184 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2185 switch (VT.getSimpleVT().SimpleTy) { 2186 default: llvm_unreachable("Unhandled Expand type in BSWAP!"); 2187 case MVT::i16: 2188 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2189 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2190 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2191 case MVT::i32: 2192 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2193 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2194 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2195 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2196 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2197 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2198 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2199 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2200 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2201 case MVT::i64: 2202 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2203 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2204 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2205 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2206 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2207 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2208 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2209 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2210 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2211 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2212 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2213 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2214 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2215 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2216 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2217 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2218 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2219 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2220 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2221 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2222 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2223 } 2224} 2225 2226/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2227/// 2228SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2229 DebugLoc dl) { 2230 switch (Opc) { 2231 default: llvm_unreachable("Cannot expand this yet!"); 2232 case ISD::CTPOP: { 2233 static const uint64_t mask[6] = { 2234 0x5555555555555555ULL, 0x3333333333333333ULL, 2235 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2236 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2237 }; 2238 EVT VT = Op.getValueType(); 2239 EVT ShVT = TLI.getShiftAmountTy(); 2240 unsigned len = VT.getSizeInBits(); 2241 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2242 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2243 unsigned EltSize = VT.isVector() ? 2244 VT.getVectorElementType().getSizeInBits() : len; 2245 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2246 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2247 Op = DAG.getNode(ISD::ADD, dl, VT, 2248 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2249 DAG.getNode(ISD::AND, dl, VT, 2250 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2251 Tmp2)); 2252 } 2253 return Op; 2254 } 2255 case ISD::CTLZ: { 2256 // for now, we do this: 2257 // x = x | (x >> 1); 2258 // x = x | (x >> 2); 2259 // ... 2260 // x = x | (x >>16); 2261 // x = x | (x >>32); // for 64-bit input 2262 // return popcount(~x); 2263 // 2264 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2265 EVT VT = Op.getValueType(); 2266 EVT ShVT = TLI.getShiftAmountTy(); 2267 unsigned len = VT.getSizeInBits(); 2268 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2269 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2270 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2271 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2272 } 2273 Op = DAG.getNOT(dl, Op, VT); 2274 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2275 } 2276 case ISD::CTTZ: { 2277 // for now, we use: { return popcount(~x & (x - 1)); } 2278 // unless the target has ctlz but not ctpop, in which case we use: 2279 // { return 32 - nlz(~x & (x-1)); } 2280 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2281 EVT VT = Op.getValueType(); 2282 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2283 DAG.getNOT(dl, Op, VT), 2284 DAG.getNode(ISD::SUB, dl, VT, Op, 2285 DAG.getConstant(1, VT))); 2286 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2287 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2288 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2289 return DAG.getNode(ISD::SUB, dl, VT, 2290 DAG.getConstant(VT.getSizeInBits(), VT), 2291 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2292 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2293 } 2294 } 2295} 2296 2297void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2298 SmallVectorImpl<SDValue> &Results) { 2299 DebugLoc dl = Node->getDebugLoc(); 2300 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2301 switch (Node->getOpcode()) { 2302 case ISD::CTPOP: 2303 case ISD::CTLZ: 2304 case ISD::CTTZ: 2305 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2306 Results.push_back(Tmp1); 2307 break; 2308 case ISD::BSWAP: 2309 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2310 break; 2311 case ISD::FRAMEADDR: 2312 case ISD::RETURNADDR: 2313 case ISD::FRAME_TO_ARGS_OFFSET: 2314 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2315 break; 2316 case ISD::FLT_ROUNDS_: 2317 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2318 break; 2319 case ISD::EH_RETURN: 2320 case ISD::EH_LABEL: 2321 case ISD::PREFETCH: 2322 case ISD::MEMBARRIER: 2323 case ISD::VAEND: 2324 Results.push_back(Node->getOperand(0)); 2325 break; 2326 case ISD::DYNAMIC_STACKALLOC: 2327 ExpandDYNAMIC_STACKALLOC(Node, Results); 2328 break; 2329 case ISD::MERGE_VALUES: 2330 for (unsigned i = 0; i < Node->getNumValues(); i++) 2331 Results.push_back(Node->getOperand(i)); 2332 break; 2333 case ISD::UNDEF: { 2334 EVT VT = Node->getValueType(0); 2335 if (VT.isInteger()) 2336 Results.push_back(DAG.getConstant(0, VT)); 2337 else if (VT.isFloatingPoint()) 2338 Results.push_back(DAG.getConstantFP(0, VT)); 2339 else 2340 llvm_unreachable("Unknown value type!"); 2341 break; 2342 } 2343 case ISD::TRAP: { 2344 // If this operation is not supported, lower it to 'abort()' call 2345 TargetLowering::ArgListTy Args; 2346 std::pair<SDValue, SDValue> CallResult = 2347 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2348 false, false, false, false, 0, CallingConv::C, false, 2349 /*isReturnValueUsed=*/true, 2350 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2351 Args, DAG, dl); 2352 Results.push_back(CallResult.second); 2353 break; 2354 } 2355 case ISD::FP_ROUND: 2356 case ISD::BIT_CONVERT: 2357 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2358 Node->getValueType(0), dl); 2359 Results.push_back(Tmp1); 2360 break; 2361 case ISD::FP_EXTEND: 2362 Tmp1 = EmitStackConvert(Node->getOperand(0), 2363 Node->getOperand(0).getValueType(), 2364 Node->getValueType(0), dl); 2365 Results.push_back(Tmp1); 2366 break; 2367 case ISD::SIGN_EXTEND_INREG: { 2368 // NOTE: we could fall back on load/store here too for targets without 2369 // SAR. However, it is doubtful that any exist. 2370 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2371 EVT VT = Node->getValueType(0); 2372 EVT ShiftAmountTy = TLI.getShiftAmountTy(); 2373 if (VT.isVector()) 2374 ShiftAmountTy = VT; 2375 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2376 ExtraVT.getScalarType().getSizeInBits(); 2377 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2378 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2379 Node->getOperand(0), ShiftCst); 2380 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2381 Results.push_back(Tmp1); 2382 break; 2383 } 2384 case ISD::FP_ROUND_INREG: { 2385 // The only way we can lower this is to turn it into a TRUNCSTORE, 2386 // EXTLOAD pair, targetting a temporary location (a stack slot). 2387 2388 // NOTE: there is a choice here between constantly creating new stack 2389 // slots and always reusing the same one. We currently always create 2390 // new ones, as reuse may inhibit scheduling. 2391 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2392 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2393 Node->getValueType(0), dl); 2394 Results.push_back(Tmp1); 2395 break; 2396 } 2397 case ISD::SINT_TO_FP: 2398 case ISD::UINT_TO_FP: 2399 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2400 Node->getOperand(0), Node->getValueType(0), dl); 2401 Results.push_back(Tmp1); 2402 break; 2403 case ISD::FP_TO_UINT: { 2404 SDValue True, False; 2405 EVT VT = Node->getOperand(0).getValueType(); 2406 EVT NVT = Node->getValueType(0); 2407 const uint64_t zero[] = {0, 0}; 2408 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2409 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2410 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2411 Tmp1 = DAG.getConstantFP(apf, VT); 2412 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2413 Node->getOperand(0), 2414 Tmp1, ISD::SETLT); 2415 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2416 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2417 DAG.getNode(ISD::FSUB, dl, VT, 2418 Node->getOperand(0), Tmp1)); 2419 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2420 DAG.getConstant(x, NVT)); 2421 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2422 Results.push_back(Tmp1); 2423 break; 2424 } 2425 case ISD::VAARG: { 2426 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2427 EVT VT = Node->getValueType(0); 2428 Tmp1 = Node->getOperand(0); 2429 Tmp2 = Node->getOperand(1); 2430 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0, 2431 false, false, 0); 2432 // Increment the pointer, VAList, to the next vaarg 2433 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2434 DAG.getConstant(TLI.getTargetData()-> 2435 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2436 TLI.getPointerTy())); 2437 // Store the incremented VAList to the legalized pointer 2438 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0, 2439 false, false, 0); 2440 // Load the actual argument out of the pointer VAList 2441 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0, 2442 false, false, 0)); 2443 Results.push_back(Results[0].getValue(1)); 2444 break; 2445 } 2446 case ISD::VACOPY: { 2447 // This defaults to loading a pointer from the input and storing it to the 2448 // output, returning the chain. 2449 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2450 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2451 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2452 Node->getOperand(2), VS, 0, false, false, 0); 2453 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0, 2454 false, false, 0); 2455 Results.push_back(Tmp1); 2456 break; 2457 } 2458 case ISD::EXTRACT_VECTOR_ELT: 2459 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2460 // This must be an access of the only element. Return it. 2461 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2462 Node->getOperand(0)); 2463 else 2464 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2465 Results.push_back(Tmp1); 2466 break; 2467 case ISD::EXTRACT_SUBVECTOR: 2468 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2469 break; 2470 case ISD::CONCAT_VECTORS: { 2471 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2472 break; 2473 } 2474 case ISD::SCALAR_TO_VECTOR: 2475 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2476 break; 2477 case ISD::INSERT_VECTOR_ELT: 2478 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2479 Node->getOperand(1), 2480 Node->getOperand(2), dl)); 2481 break; 2482 case ISD::VECTOR_SHUFFLE: { 2483 SmallVector<int, 8> Mask; 2484 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2485 2486 EVT VT = Node->getValueType(0); 2487 EVT EltVT = VT.getVectorElementType(); 2488 unsigned NumElems = VT.getVectorNumElements(); 2489 SmallVector<SDValue, 8> Ops; 2490 for (unsigned i = 0; i != NumElems; ++i) { 2491 if (Mask[i] < 0) { 2492 Ops.push_back(DAG.getUNDEF(EltVT)); 2493 continue; 2494 } 2495 unsigned Idx = Mask[i]; 2496 if (Idx < NumElems) 2497 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2498 Node->getOperand(0), 2499 DAG.getIntPtrConstant(Idx))); 2500 else 2501 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2502 Node->getOperand(1), 2503 DAG.getIntPtrConstant(Idx - NumElems))); 2504 } 2505 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2506 Results.push_back(Tmp1); 2507 break; 2508 } 2509 case ISD::EXTRACT_ELEMENT: { 2510 EVT OpTy = Node->getOperand(0).getValueType(); 2511 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2512 // 1 -> Hi 2513 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2514 DAG.getConstant(OpTy.getSizeInBits()/2, 2515 TLI.getShiftAmountTy())); 2516 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2517 } else { 2518 // 0 -> Lo 2519 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2520 Node->getOperand(0)); 2521 } 2522 Results.push_back(Tmp1); 2523 break; 2524 } 2525 case ISD::STACKSAVE: 2526 // Expand to CopyFromReg if the target set 2527 // StackPointerRegisterToSaveRestore. 2528 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2529 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2530 Node->getValueType(0))); 2531 Results.push_back(Results[0].getValue(1)); 2532 } else { 2533 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2534 Results.push_back(Node->getOperand(0)); 2535 } 2536 break; 2537 case ISD::STACKRESTORE: 2538 // Expand to CopyToReg if the target set 2539 // StackPointerRegisterToSaveRestore. 2540 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2541 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2542 Node->getOperand(1))); 2543 } else { 2544 Results.push_back(Node->getOperand(0)); 2545 } 2546 break; 2547 case ISD::FCOPYSIGN: 2548 Results.push_back(ExpandFCOPYSIGN(Node)); 2549 break; 2550 case ISD::FNEG: 2551 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2552 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2553 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2554 Node->getOperand(0)); 2555 Results.push_back(Tmp1); 2556 break; 2557 case ISD::FABS: { 2558 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2559 EVT VT = Node->getValueType(0); 2560 Tmp1 = Node->getOperand(0); 2561 Tmp2 = DAG.getConstantFP(0.0, VT); 2562 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2563 Tmp1, Tmp2, ISD::SETUGT); 2564 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2565 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2566 Results.push_back(Tmp1); 2567 break; 2568 } 2569 case ISD::FSQRT: 2570 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2571 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2572 break; 2573 case ISD::FSIN: 2574 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2575 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2576 break; 2577 case ISD::FCOS: 2578 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2579 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2580 break; 2581 case ISD::FLOG: 2582 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2583 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2584 break; 2585 case ISD::FLOG2: 2586 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2587 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2588 break; 2589 case ISD::FLOG10: 2590 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2591 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2592 break; 2593 case ISD::FEXP: 2594 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2595 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2596 break; 2597 case ISD::FEXP2: 2598 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2599 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2600 break; 2601 case ISD::FTRUNC: 2602 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2603 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2604 break; 2605 case ISD::FFLOOR: 2606 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2607 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2608 break; 2609 case ISD::FCEIL: 2610 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2611 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2612 break; 2613 case ISD::FRINT: 2614 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2615 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2616 break; 2617 case ISD::FNEARBYINT: 2618 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2619 RTLIB::NEARBYINT_F64, 2620 RTLIB::NEARBYINT_F80, 2621 RTLIB::NEARBYINT_PPCF128)); 2622 break; 2623 case ISD::FPOWI: 2624 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2625 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2626 break; 2627 case ISD::FPOW: 2628 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2629 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2630 break; 2631 case ISD::FDIV: 2632 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2633 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2634 break; 2635 case ISD::FREM: 2636 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2637 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2638 break; 2639 case ISD::FP16_TO_FP32: 2640 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 2641 break; 2642 case ISD::FP32_TO_FP16: 2643 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 2644 break; 2645 case ISD::ConstantFP: { 2646 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2647 // Check to see if this FP immediate is already legal. 2648 // If this is a legal constant, turn it into a TargetConstantFP node. 2649 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 2650 Results.push_back(SDValue(Node, 0)); 2651 else 2652 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2653 break; 2654 } 2655 case ISD::EHSELECTION: { 2656 unsigned Reg = TLI.getExceptionSelectorRegister(); 2657 assert(Reg && "Can't expand to unknown register!"); 2658 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2659 Node->getValueType(0))); 2660 Results.push_back(Results[0].getValue(1)); 2661 break; 2662 } 2663 case ISD::EXCEPTIONADDR: { 2664 unsigned Reg = TLI.getExceptionAddressRegister(); 2665 assert(Reg && "Can't expand to unknown register!"); 2666 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2667 Node->getValueType(0))); 2668 Results.push_back(Results[0].getValue(1)); 2669 break; 2670 } 2671 case ISD::SUB: { 2672 EVT VT = Node->getValueType(0); 2673 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2674 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2675 "Don't know how to expand this subtraction!"); 2676 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2677 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2678 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2679 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2680 break; 2681 } 2682 case ISD::UREM: 2683 case ISD::SREM: { 2684 EVT VT = Node->getValueType(0); 2685 SDVTList VTs = DAG.getVTList(VT, VT); 2686 bool isSigned = Node->getOpcode() == ISD::SREM; 2687 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2688 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2689 Tmp2 = Node->getOperand(0); 2690 Tmp3 = Node->getOperand(1); 2691 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2692 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2693 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2694 // X % Y -> X-X/Y*Y 2695 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2696 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2697 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2698 } else if (isSigned) { 2699 Tmp1 = ExpandIntLibCall(Node, true, 2700 RTLIB::SREM_I8, 2701 RTLIB::SREM_I16, RTLIB::SREM_I32, 2702 RTLIB::SREM_I64, RTLIB::SREM_I128); 2703 } else { 2704 Tmp1 = ExpandIntLibCall(Node, false, 2705 RTLIB::UREM_I8, 2706 RTLIB::UREM_I16, RTLIB::UREM_I32, 2707 RTLIB::UREM_I64, RTLIB::UREM_I128); 2708 } 2709 Results.push_back(Tmp1); 2710 break; 2711 } 2712 case ISD::UDIV: 2713 case ISD::SDIV: { 2714 bool isSigned = Node->getOpcode() == ISD::SDIV; 2715 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2716 EVT VT = Node->getValueType(0); 2717 SDVTList VTs = DAG.getVTList(VT, VT); 2718 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2719 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2720 Node->getOperand(1)); 2721 else if (isSigned) 2722 Tmp1 = ExpandIntLibCall(Node, true, 2723 RTLIB::SDIV_I8, 2724 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2725 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2726 else 2727 Tmp1 = ExpandIntLibCall(Node, false, 2728 RTLIB::UDIV_I8, 2729 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2730 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2731 Results.push_back(Tmp1); 2732 break; 2733 } 2734 case ISD::MULHU: 2735 case ISD::MULHS: { 2736 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2737 ISD::SMUL_LOHI; 2738 EVT VT = Node->getValueType(0); 2739 SDVTList VTs = DAG.getVTList(VT, VT); 2740 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2741 "If this wasn't legal, it shouldn't have been created!"); 2742 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 2743 Node->getOperand(1)); 2744 Results.push_back(Tmp1.getValue(1)); 2745 break; 2746 } 2747 case ISD::MUL: { 2748 EVT VT = Node->getValueType(0); 2749 SDVTList VTs = DAG.getVTList(VT, VT); 2750 // See if multiply or divide can be lowered using two-result operations. 2751 // We just need the low half of the multiply; try both the signed 2752 // and unsigned forms. If the target supports both SMUL_LOHI and 2753 // UMUL_LOHI, form a preference by checking which forms of plain 2754 // MULH it supports. 2755 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 2756 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 2757 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 2758 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 2759 unsigned OpToUse = 0; 2760 if (HasSMUL_LOHI && !HasMULHS) { 2761 OpToUse = ISD::SMUL_LOHI; 2762 } else if (HasUMUL_LOHI && !HasMULHU) { 2763 OpToUse = ISD::UMUL_LOHI; 2764 } else if (HasSMUL_LOHI) { 2765 OpToUse = ISD::SMUL_LOHI; 2766 } else if (HasUMUL_LOHI) { 2767 OpToUse = ISD::UMUL_LOHI; 2768 } 2769 if (OpToUse) { 2770 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 2771 Node->getOperand(1))); 2772 break; 2773 } 2774 Tmp1 = ExpandIntLibCall(Node, false, 2775 RTLIB::MUL_I8, 2776 RTLIB::MUL_I16, RTLIB::MUL_I32, 2777 RTLIB::MUL_I64, RTLIB::MUL_I128); 2778 Results.push_back(Tmp1); 2779 break; 2780 } 2781 case ISD::SADDO: 2782 case ISD::SSUBO: { 2783 SDValue LHS = Node->getOperand(0); 2784 SDValue RHS = Node->getOperand(1); 2785 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 2786 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2787 LHS, RHS); 2788 Results.push_back(Sum); 2789 EVT OType = Node->getValueType(1); 2790 2791 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 2792 2793 // LHSSign -> LHS >= 0 2794 // RHSSign -> RHS >= 0 2795 // SumSign -> Sum >= 0 2796 // 2797 // Add: 2798 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 2799 // Sub: 2800 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 2801 // 2802 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 2803 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 2804 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 2805 Node->getOpcode() == ISD::SADDO ? 2806 ISD::SETEQ : ISD::SETNE); 2807 2808 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 2809 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 2810 2811 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 2812 Results.push_back(Cmp); 2813 break; 2814 } 2815 case ISD::UADDO: 2816 case ISD::USUBO: { 2817 SDValue LHS = Node->getOperand(0); 2818 SDValue RHS = Node->getOperand(1); 2819 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 2820 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2821 LHS, RHS); 2822 Results.push_back(Sum); 2823 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 2824 Node->getOpcode () == ISD::UADDO ? 2825 ISD::SETULT : ISD::SETUGT)); 2826 break; 2827 } 2828 case ISD::UMULO: 2829 case ISD::SMULO: { 2830 EVT VT = Node->getValueType(0); 2831 SDValue LHS = Node->getOperand(0); 2832 SDValue RHS = Node->getOperand(1); 2833 SDValue BottomHalf; 2834 SDValue TopHalf; 2835 static const unsigned Ops[2][3] = 2836 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 2837 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 2838 bool isSigned = Node->getOpcode() == ISD::SMULO; 2839 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 2840 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 2841 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 2842 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 2843 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 2844 RHS); 2845 TopHalf = BottomHalf.getValue(1); 2846 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2))) { 2847 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 2848 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 2849 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 2850 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 2851 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2852 DAG.getIntPtrConstant(0)); 2853 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2854 DAG.getIntPtrConstant(1)); 2855 } else { 2856 // FIXME: We should be able to fall back to a libcall with an illegal 2857 // type in some cases. 2858 // Also, we can fall back to a division in some cases, but that's a big 2859 // performance hit in the general case. 2860 llvm_unreachable("Don't know how to expand this operation yet!"); 2861 } 2862 if (isSigned) { 2863 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); 2864 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 2865 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 2866 ISD::SETNE); 2867 } else { 2868 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 2869 DAG.getConstant(0, VT), ISD::SETNE); 2870 } 2871 Results.push_back(BottomHalf); 2872 Results.push_back(TopHalf); 2873 break; 2874 } 2875 case ISD::BUILD_PAIR: { 2876 EVT PairTy = Node->getValueType(0); 2877 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 2878 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 2879 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 2880 DAG.getConstant(PairTy.getSizeInBits()/2, 2881 TLI.getShiftAmountTy())); 2882 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 2883 break; 2884 } 2885 case ISD::SELECT: 2886 Tmp1 = Node->getOperand(0); 2887 Tmp2 = Node->getOperand(1); 2888 Tmp3 = Node->getOperand(2); 2889 if (Tmp1.getOpcode() == ISD::SETCC) { 2890 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 2891 Tmp2, Tmp3, 2892 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2893 } else { 2894 Tmp1 = DAG.getSelectCC(dl, Tmp1, 2895 DAG.getConstant(0, Tmp1.getValueType()), 2896 Tmp2, Tmp3, ISD::SETNE); 2897 } 2898 Results.push_back(Tmp1); 2899 break; 2900 case ISD::BR_JT: { 2901 SDValue Chain = Node->getOperand(0); 2902 SDValue Table = Node->getOperand(1); 2903 SDValue Index = Node->getOperand(2); 2904 2905 EVT PTy = TLI.getPointerTy(); 2906 2907 const TargetData &TD = *TLI.getTargetData(); 2908 unsigned EntrySize = 2909 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 2910 2911 Index = DAG.getNode(ISD::MUL, dl, PTy, 2912 Index, DAG.getConstant(EntrySize, PTy)); 2913 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2914 2915 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 2916 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 2917 PseudoSourceValue::getJumpTable(), 0, MemVT, 2918 false, false, 0); 2919 Addr = LD; 2920 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2921 // For PIC, the sequence is: 2922 // BRIND(load(Jumptable + index) + RelocBase) 2923 // RelocBase can be JumpTable, GOT or some sort of global base. 2924 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 2925 TLI.getPICJumpTableRelocBase(Table, DAG)); 2926 } 2927 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 2928 Results.push_back(Tmp1); 2929 break; 2930 } 2931 case ISD::BRCOND: 2932 // Expand brcond's setcc into its constituent parts and create a BR_CC 2933 // Node. 2934 Tmp1 = Node->getOperand(0); 2935 Tmp2 = Node->getOperand(1); 2936 if (Tmp2.getOpcode() == ISD::SETCC) { 2937 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 2938 Tmp1, Tmp2.getOperand(2), 2939 Tmp2.getOperand(0), Tmp2.getOperand(1), 2940 Node->getOperand(2)); 2941 } else { 2942 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 2943 DAG.getCondCode(ISD::SETNE), Tmp2, 2944 DAG.getConstant(0, Tmp2.getValueType()), 2945 Node->getOperand(2)); 2946 } 2947 Results.push_back(Tmp1); 2948 break; 2949 case ISD::SETCC: { 2950 Tmp1 = Node->getOperand(0); 2951 Tmp2 = Node->getOperand(1); 2952 Tmp3 = Node->getOperand(2); 2953 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 2954 2955 // If we expanded the SETCC into an AND/OR, return the new node 2956 if (Tmp2.getNode() == 0) { 2957 Results.push_back(Tmp1); 2958 break; 2959 } 2960 2961 // Otherwise, SETCC for the given comparison type must be completely 2962 // illegal; expand it into a SELECT_CC. 2963 EVT VT = Node->getValueType(0); 2964 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 2965 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 2966 Results.push_back(Tmp1); 2967 break; 2968 } 2969 case ISD::SELECT_CC: { 2970 Tmp1 = Node->getOperand(0); // LHS 2971 Tmp2 = Node->getOperand(1); // RHS 2972 Tmp3 = Node->getOperand(2); // True 2973 Tmp4 = Node->getOperand(3); // False 2974 SDValue CC = Node->getOperand(4); 2975 2976 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 2977 Tmp1, Tmp2, CC, dl); 2978 2979 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 2980 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2981 CC = DAG.getCondCode(ISD::SETNE); 2982 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 2983 Tmp3, Tmp4, CC); 2984 Results.push_back(Tmp1); 2985 break; 2986 } 2987 case ISD::BR_CC: { 2988 Tmp1 = Node->getOperand(0); // Chain 2989 Tmp2 = Node->getOperand(2); // LHS 2990 Tmp3 = Node->getOperand(3); // RHS 2991 Tmp4 = Node->getOperand(1); // CC 2992 2993 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 2994 Tmp2, Tmp3, Tmp4, dl); 2995 LastCALLSEQ_END = DAG.getEntryNode(); 2996 2997 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 2998 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 2999 Tmp4 = DAG.getCondCode(ISD::SETNE); 3000 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3001 Tmp3, Node->getOperand(4)); 3002 Results.push_back(Tmp1); 3003 break; 3004 } 3005 case ISD::GLOBAL_OFFSET_TABLE: 3006 case ISD::GlobalAddress: 3007 case ISD::GlobalTLSAddress: 3008 case ISD::ExternalSymbol: 3009 case ISD::ConstantPool: 3010 case ISD::JumpTable: 3011 case ISD::INTRINSIC_W_CHAIN: 3012 case ISD::INTRINSIC_WO_CHAIN: 3013 case ISD::INTRINSIC_VOID: 3014 // FIXME: Custom lowering for these operations shouldn't return null! 3015 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3016 Results.push_back(SDValue(Node, i)); 3017 break; 3018 } 3019} 3020void SelectionDAGLegalize::PromoteNode(SDNode *Node, 3021 SmallVectorImpl<SDValue> &Results) { 3022 EVT OVT = Node->getValueType(0); 3023 if (Node->getOpcode() == ISD::UINT_TO_FP || 3024 Node->getOpcode() == ISD::SINT_TO_FP || 3025 Node->getOpcode() == ISD::SETCC) { 3026 OVT = Node->getOperand(0).getValueType(); 3027 } 3028 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3029 DebugLoc dl = Node->getDebugLoc(); 3030 SDValue Tmp1, Tmp2, Tmp3; 3031 switch (Node->getOpcode()) { 3032 case ISD::CTTZ: 3033 case ISD::CTLZ: 3034 case ISD::CTPOP: 3035 // Zero extend the argument. 3036 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3037 // Perform the larger operation. 3038 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3039 if (Node->getOpcode() == ISD::CTTZ) { 3040 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3041 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3042 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3043 ISD::SETEQ); 3044 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3045 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3046 } else if (Node->getOpcode() == ISD::CTLZ) { 3047 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3048 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3049 DAG.getConstant(NVT.getSizeInBits() - 3050 OVT.getSizeInBits(), NVT)); 3051 } 3052 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3053 break; 3054 case ISD::BSWAP: { 3055 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3056 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3057 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3058 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3059 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3060 Results.push_back(Tmp1); 3061 break; 3062 } 3063 case ISD::FP_TO_UINT: 3064 case ISD::FP_TO_SINT: 3065 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3066 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3067 Results.push_back(Tmp1); 3068 break; 3069 case ISD::UINT_TO_FP: 3070 case ISD::SINT_TO_FP: 3071 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3072 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3073 Results.push_back(Tmp1); 3074 break; 3075 case ISD::AND: 3076 case ISD::OR: 3077 case ISD::XOR: { 3078 unsigned ExtOp, TruncOp; 3079 if (OVT.isVector()) { 3080 ExtOp = ISD::BIT_CONVERT; 3081 TruncOp = ISD::BIT_CONVERT; 3082 } else if (OVT.isInteger()) { 3083 ExtOp = ISD::ANY_EXTEND; 3084 TruncOp = ISD::TRUNCATE; 3085 } else { 3086 llvm_report_error("Cannot promote logic operation"); 3087 } 3088 // Promote each of the values to the new type. 3089 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3090 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3091 // Perform the larger operation, then convert back 3092 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3093 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3094 break; 3095 } 3096 case ISD::SELECT: { 3097 unsigned ExtOp, TruncOp; 3098 if (Node->getValueType(0).isVector()) { 3099 ExtOp = ISD::BIT_CONVERT; 3100 TruncOp = ISD::BIT_CONVERT; 3101 } else if (Node->getValueType(0).isInteger()) { 3102 ExtOp = ISD::ANY_EXTEND; 3103 TruncOp = ISD::TRUNCATE; 3104 } else { 3105 ExtOp = ISD::FP_EXTEND; 3106 TruncOp = ISD::FP_ROUND; 3107 } 3108 Tmp1 = Node->getOperand(0); 3109 // Promote each of the values to the new type. 3110 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3111 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3112 // Perform the larger operation, then round down. 3113 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3114 if (TruncOp != ISD::FP_ROUND) 3115 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3116 else 3117 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3118 DAG.getIntPtrConstant(0)); 3119 Results.push_back(Tmp1); 3120 break; 3121 } 3122 case ISD::VECTOR_SHUFFLE: { 3123 SmallVector<int, 8> Mask; 3124 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3125 3126 // Cast the two input vectors. 3127 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3128 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3129 3130 // Convert the shuffle mask to the right # elements. 3131 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3132 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3133 Results.push_back(Tmp1); 3134 break; 3135 } 3136 case ISD::SETCC: { 3137 unsigned ExtOp = ISD::FP_EXTEND; 3138 if (NVT.isInteger()) { 3139 ISD::CondCode CCCode = 3140 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3141 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3142 } 3143 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3144 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3145 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3146 Tmp1, Tmp2, Node->getOperand(2))); 3147 break; 3148 } 3149 } 3150} 3151 3152// SelectionDAG::Legalize - This is the entry point for the file. 3153// 3154void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) { 3155 /// run - This is the main entry point to this class. 3156 /// 3157 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3158} 3159 3160