LegalizeDAG.cpp revision c7f7d5e7c86e86b9fa99735f4bac646e74764810
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/Target/TargetFrameInfo.h" 20#include "llvm/Target/TargetLowering.h" 21#include "llvm/Target/TargetData.h" 22#include "llvm/Target/TargetMachine.h" 23#include "llvm/Target/TargetOptions.h" 24#include "llvm/CallingConv.h" 25#include "llvm/Constants.h" 26#include "llvm/DerivedTypes.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Compiler.h" 29#include "llvm/Support/MathExtras.h" 30#include "llvm/ADT/DenseMap.h" 31#include "llvm/ADT/SmallVector.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include <map> 34using namespace llvm; 35 36#ifndef NDEBUG 37static cl::opt<bool> 38ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 39 cl::desc("Pop up a window to show dags before legalize")); 40#else 41static const bool ViewLegalizeDAGs = 0; 42#endif 43 44//===----------------------------------------------------------------------===// 45/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 46/// hacks on it until the target machine can handle it. This involves 47/// eliminating value sizes the machine cannot handle (promoting small sizes to 48/// large sizes or splitting up large values into small values) as well as 49/// eliminating operations the machine cannot handle. 50/// 51/// This code also does a small amount of optimization and recognition of idioms 52/// as part of its processing. For example, if a target does not support a 53/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 54/// will attempt merge setcc and brc instructions into brcc's. 55/// 56namespace { 57class VISIBILITY_HIDDEN SelectionDAGLegalize { 58 TargetLowering &TLI; 59 SelectionDAG &DAG; 60 61 // Libcall insertion helpers. 62 63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 64 /// legalized. We use this to ensure that calls are properly serialized 65 /// against each other, including inserted libcalls. 66 SDOperand LastCALLSEQ_END; 67 68 /// IsLegalizingCall - This member is used *only* for purposes of providing 69 /// helpful assertions that a libcall isn't created while another call is 70 /// being legalized (which could lead to non-serialized call sequences). 71 bool IsLegalizingCall; 72 73 enum LegalizeAction { 74 Legal, // The target natively supports this operation. 75 Promote, // This operation should be executed in a larger type. 76 Expand // Try to expand this to other ops, otherwise use a libcall. 77 }; 78 79 /// ValueTypeActions - This is a bitvector that contains two bits for each 80 /// value type, where the two bits correspond to the LegalizeAction enum. 81 /// This can be queried with "getTypeAction(VT)". 82 TargetLowering::ValueTypeActionImpl ValueTypeActions; 83 84 /// LegalizedNodes - For nodes that are of legal width, and that have more 85 /// than one use, this map indicates what regularized operand to use. This 86 /// allows us to avoid legalizing the same thing more than once. 87 DenseMap<SDOperand, SDOperand> LegalizedNodes; 88 89 /// PromotedNodes - For nodes that are below legal width, and that have more 90 /// than one use, this map indicates what promoted value to use. This allows 91 /// us to avoid promoting the same thing more than once. 92 DenseMap<SDOperand, SDOperand> PromotedNodes; 93 94 /// ExpandedNodes - For nodes that need to be expanded this map indicates 95 /// which which operands are the expanded version of the input. This allows 96 /// us to avoid expanding the same node more than once. 97 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 98 99 /// SplitNodes - For vector nodes that need to be split, this map indicates 100 /// which which operands are the split version of the input. This allows us 101 /// to avoid splitting the same node more than once. 102 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 103 104 /// ScalarizedNodes - For nodes that need to be converted from vector types to 105 /// scalar types, this contains the mapping of ones we have already 106 /// processed to the result. 107 std::map<SDOperand, SDOperand> ScalarizedNodes; 108 109 void AddLegalizedOperand(SDOperand From, SDOperand To) { 110 LegalizedNodes.insert(std::make_pair(From, To)); 111 // If someone requests legalization of the new node, return itself. 112 if (From != To) 113 LegalizedNodes.insert(std::make_pair(To, To)); 114 } 115 void AddPromotedOperand(SDOperand From, SDOperand To) { 116 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 117 assert(isNew && "Got into the map somehow?"); 118 // If someone requests legalization of the new node, return itself. 119 LegalizedNodes.insert(std::make_pair(To, To)); 120 } 121 122public: 123 124 SelectionDAGLegalize(SelectionDAG &DAG); 125 126 /// getTypeAction - Return how we should legalize values of this type, either 127 /// it is already legal or we need to expand it into multiple registers of 128 /// smaller integer type, or we need to promote it to a larger type. 129 LegalizeAction getTypeAction(MVT::ValueType VT) const { 130 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 131 } 132 133 /// isTypeLegal - Return true if this type is legal on this target. 134 /// 135 bool isTypeLegal(MVT::ValueType VT) const { 136 return getTypeAction(VT) == Legal; 137 } 138 139 void LegalizeDAG(); 140 141private: 142 /// HandleOp - Legalize, Promote, or Expand the specified operand as 143 /// appropriate for its type. 144 void HandleOp(SDOperand Op); 145 146 /// LegalizeOp - We know that the specified value has a legal type. 147 /// Recursively ensure that the operands have legal types, then return the 148 /// result. 149 SDOperand LegalizeOp(SDOperand O); 150 151 /// UnrollVectorOp - We know that the given vector has a legal type, however 152 /// the operation it performs is not legal and is an operation that we have 153 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 154 /// operating on each element individually. 155 SDOperand UnrollVectorOp(SDOperand O); 156 157 /// PromoteOp - Given an operation that produces a value in an invalid type, 158 /// promote it to compute the value into a larger type. The produced value 159 /// will have the correct bits for the low portion of the register, but no 160 /// guarantee is made about the top bits: it may be zero, sign-extended, or 161 /// garbage. 162 SDOperand PromoteOp(SDOperand O); 163 164 /// ExpandOp - Expand the specified SDOperand into its two component pieces 165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 166 /// the LegalizeNodes map is filled in for any results that are not expanded, 167 /// the ExpandedNodes map is filled in for any results that are expanded, and 168 /// the Lo/Hi values are returned. This applies to integer types and Vector 169 /// types. 170 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 171 172 /// SplitVectorOp - Given an operand of vector type, break it down into 173 /// two smaller values. 174 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 175 176 /// ScalarizeVectorOp - Given an operand of single-element vector type 177 /// (e.g. v1f32), convert it into the equivalent operation that returns a 178 /// scalar (e.g. f32) value. 179 SDOperand ScalarizeVectorOp(SDOperand O); 180 181 /// isShuffleLegal - Return true if a vector shuffle is legal with the 182 /// specified mask and type. Targets can specify exactly which masks they 183 /// support and the code generator is tasked with not creating illegal masks. 184 /// 185 /// Note that this will also return true for shuffles that are promoted to a 186 /// different type. 187 /// 188 /// If this is a legal shuffle, this method returns the (possibly promoted) 189 /// build_vector Mask. If it's not a legal shuffle, it returns null. 190 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 191 192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 194 195 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 196 197 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 198 SDOperand &Hi); 199 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 200 SDOperand Source); 201 202 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 203 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 204 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 205 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 206 SDOperand LegalOp, 207 MVT::ValueType DestVT); 208 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 209 bool isSigned); 210 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 211 bool isSigned); 212 213 SDOperand ExpandBSWAP(SDOperand Op); 214 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 215 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 216 SDOperand &Lo, SDOperand &Hi); 217 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 218 SDOperand &Lo, SDOperand &Hi); 219 220 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 221 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 222 223 SDOperand getIntPtrConstant(uint64_t Val) { 224 return DAG.getConstant(Val, TLI.getPointerTy()); 225 } 226}; 227} 228 229/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 230/// specified mask and type. Targets can specify exactly which masks they 231/// support and the code generator is tasked with not creating illegal masks. 232/// 233/// Note that this will also return true for shuffles that are promoted to a 234/// different type. 235SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 236 SDOperand Mask) const { 237 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 238 default: return 0; 239 case TargetLowering::Legal: 240 case TargetLowering::Custom: 241 break; 242 case TargetLowering::Promote: { 243 // If this is promoted to a different type, convert the shuffle mask and 244 // ask if it is legal in the promoted type! 245 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 246 247 // If we changed # elements, change the shuffle mask. 248 unsigned NumEltsGrowth = 249 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 250 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 251 if (NumEltsGrowth > 1) { 252 // Renumber the elements. 253 SmallVector<SDOperand, 8> Ops; 254 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 255 SDOperand InOp = Mask.getOperand(i); 256 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 257 if (InOp.getOpcode() == ISD::UNDEF) 258 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 259 else { 260 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 261 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 262 } 263 } 264 } 265 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 266 } 267 VT = NVT; 268 break; 269 } 270 } 271 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 272} 273 274SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 275 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 276 ValueTypeActions(TLI.getValueTypeActions()) { 277 assert(MVT::LAST_VALUETYPE <= 32 && 278 "Too many value types for ValueTypeActions to hold!"); 279} 280 281/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 282/// contains all of a nodes operands before it contains the node. 283static void ComputeTopDownOrdering(SelectionDAG &DAG, 284 SmallVector<SDNode*, 64> &Order) { 285 286 DenseMap<SDNode*, unsigned> Visited; 287 std::vector<SDNode*> Worklist; 288 Worklist.reserve(128); 289 290 // Compute ordering from all of the leaves in the graphs, those (like the 291 // entry node) that have no operands. 292 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 293 E = DAG.allnodes_end(); I != E; ++I) { 294 if (I->getNumOperands() == 0) { 295 Visited[I] = 0 - 1U; 296 Worklist.push_back(I); 297 } 298 } 299 300 while (!Worklist.empty()) { 301 SDNode *N = Worklist.back(); 302 Worklist.pop_back(); 303 304 if (++Visited[N] != N->getNumOperands()) 305 continue; // Haven't visited all operands yet 306 307 Order.push_back(N); 308 309 // Now that we have N in, add anything that uses it if all of their operands 310 // are now done. 311 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 312 UI != E; ++UI) 313 Worklist.push_back(*UI); 314 } 315 316 assert(Order.size() == Visited.size() && 317 Order.size() == 318 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 319 "Error: DAG is cyclic!"); 320} 321 322 323void SelectionDAGLegalize::LegalizeDAG() { 324 LastCALLSEQ_END = DAG.getEntryNode(); 325 IsLegalizingCall = false; 326 327 // The legalize process is inherently a bottom-up recursive process (users 328 // legalize their uses before themselves). Given infinite stack space, we 329 // could just start legalizing on the root and traverse the whole graph. In 330 // practice however, this causes us to run out of stack space on large basic 331 // blocks. To avoid this problem, compute an ordering of the nodes where each 332 // node is only legalized after all of its operands are legalized. 333 SmallVector<SDNode*, 64> Order; 334 ComputeTopDownOrdering(DAG, Order); 335 336 for (unsigned i = 0, e = Order.size(); i != e; ++i) 337 HandleOp(SDOperand(Order[i], 0)); 338 339 // Finally, it's possible the root changed. Get the new root. 340 SDOperand OldRoot = DAG.getRoot(); 341 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 342 DAG.setRoot(LegalizedNodes[OldRoot]); 343 344 ExpandedNodes.clear(); 345 LegalizedNodes.clear(); 346 PromotedNodes.clear(); 347 SplitNodes.clear(); 348 ScalarizedNodes.clear(); 349 350 // Remove dead nodes now. 351 DAG.RemoveDeadNodes(); 352} 353 354 355/// FindCallEndFromCallStart - Given a chained node that is part of a call 356/// sequence, find the CALLSEQ_END node that terminates the call sequence. 357static SDNode *FindCallEndFromCallStart(SDNode *Node) { 358 if (Node->getOpcode() == ISD::CALLSEQ_END) 359 return Node; 360 if (Node->use_empty()) 361 return 0; // No CallSeqEnd 362 363 // The chain is usually at the end. 364 SDOperand TheChain(Node, Node->getNumValues()-1); 365 if (TheChain.getValueType() != MVT::Other) { 366 // Sometimes it's at the beginning. 367 TheChain = SDOperand(Node, 0); 368 if (TheChain.getValueType() != MVT::Other) { 369 // Otherwise, hunt for it. 370 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 371 if (Node->getValueType(i) == MVT::Other) { 372 TheChain = SDOperand(Node, i); 373 break; 374 } 375 376 // Otherwise, we walked into a node without a chain. 377 if (TheChain.getValueType() != MVT::Other) 378 return 0; 379 } 380 } 381 382 for (SDNode::use_iterator UI = Node->use_begin(), 383 E = Node->use_end(); UI != E; ++UI) { 384 385 // Make sure to only follow users of our token chain. 386 SDNode *User = *UI; 387 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 388 if (User->getOperand(i) == TheChain) 389 if (SDNode *Result = FindCallEndFromCallStart(User)) 390 return Result; 391 } 392 return 0; 393} 394 395/// FindCallStartFromCallEnd - Given a chained node that is part of a call 396/// sequence, find the CALLSEQ_START node that initiates the call sequence. 397static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 398 assert(Node && "Didn't find callseq_start for a call??"); 399 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 400 401 assert(Node->getOperand(0).getValueType() == MVT::Other && 402 "Node doesn't have a token chain argument!"); 403 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 404} 405 406/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 407/// see if any uses can reach Dest. If no dest operands can get to dest, 408/// legalize them, legalize ourself, and return false, otherwise, return true. 409/// 410/// Keep track of the nodes we fine that actually do lead to Dest in 411/// NodesLeadingTo. This avoids retraversing them exponential number of times. 412/// 413bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 414 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 415 if (N == Dest) return true; // N certainly leads to Dest :) 416 417 // If we've already processed this node and it does lead to Dest, there is no 418 // need to reprocess it. 419 if (NodesLeadingTo.count(N)) return true; 420 421 // If the first result of this node has been already legalized, then it cannot 422 // reach N. 423 switch (getTypeAction(N->getValueType(0))) { 424 case Legal: 425 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 426 break; 427 case Promote: 428 if (PromotedNodes.count(SDOperand(N, 0))) return false; 429 break; 430 case Expand: 431 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 432 break; 433 } 434 435 // Okay, this node has not already been legalized. Check and legalize all 436 // operands. If none lead to Dest, then we can legalize this node. 437 bool OperandsLeadToDest = false; 438 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 439 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 440 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 441 442 if (OperandsLeadToDest) { 443 NodesLeadingTo.insert(N); 444 return true; 445 } 446 447 // Okay, this node looks safe, legalize it and return false. 448 HandleOp(SDOperand(N, 0)); 449 return false; 450} 451 452/// HandleOp - Legalize, Promote, or Expand the specified operand as 453/// appropriate for its type. 454void SelectionDAGLegalize::HandleOp(SDOperand Op) { 455 MVT::ValueType VT = Op.getValueType(); 456 switch (getTypeAction(VT)) { 457 default: assert(0 && "Bad type action!"); 458 case Legal: (void)LegalizeOp(Op); break; 459 case Promote: (void)PromoteOp(Op); break; 460 case Expand: 461 if (!MVT::isVector(VT)) { 462 // If this is an illegal scalar, expand it into its two component 463 // pieces. 464 SDOperand X, Y; 465 if (Op.getOpcode() == ISD::TargetConstant) 466 break; // Allow illegal target nodes. 467 ExpandOp(Op, X, Y); 468 } else if (MVT::getVectorNumElements(VT) == 1) { 469 // If this is an illegal single element vector, convert it to a 470 // scalar operation. 471 (void)ScalarizeVectorOp(Op); 472 } else { 473 // Otherwise, this is an illegal multiple element vector. 474 // Split it in half and legalize both parts. 475 SDOperand X, Y; 476 SplitVectorOp(Op, X, Y); 477 } 478 break; 479 } 480} 481 482/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 483/// a load from the constant pool. 484static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 485 SelectionDAG &DAG, TargetLowering &TLI) { 486 bool Extend = false; 487 488 // If a FP immediate is precise when represented as a float and if the 489 // target can do an extending load from float to double, we put it into 490 // the constant pool as a float, even if it's is statically typed as a 491 // double. 492 MVT::ValueType VT = CFP->getValueType(0); 493 bool isDouble = VT == MVT::f64; 494 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT), 495 CFP->getValueAPF()); 496 if (!UseCP) { 497 if (VT!=MVT::f64 && VT!=MVT::f32) 498 assert(0 && "Invalid type expansion"); 499 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(), 500 isDouble ? MVT::i64 : MVT::i32); 501 } 502 503 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) && 504 // Only do this if the target has a native EXTLOAD instruction from f32. 505 // Do not try to be clever about long doubles (so far) 506 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 507 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 508 VT = MVT::f32; 509 Extend = true; 510 } 511 512 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 513 if (Extend) { 514 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 515 CPIdx, NULL, 0, MVT::f32); 516 } else { 517 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 518 } 519} 520 521 522/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 523/// operations. 524static 525SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 526 SelectionDAG &DAG, TargetLowering &TLI) { 527 MVT::ValueType VT = Node->getValueType(0); 528 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 529 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 530 "fcopysign expansion only supported for f32 and f64"); 531 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 532 533 // First get the sign bit of second operand. 534 SDOperand Mask1 = (SrcVT == MVT::f64) 535 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 536 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 537 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 538 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 539 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 540 // Shift right or sign-extend it if the two operands have different types. 541 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 542 if (SizeDiff > 0) { 543 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 544 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 545 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 546 } else if (SizeDiff < 0) 547 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 548 549 // Clear the sign bit of first operand. 550 SDOperand Mask2 = (VT == MVT::f64) 551 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 552 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 553 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 554 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 555 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 556 557 // Or the value with the sign bit. 558 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 559 return Result; 560} 561 562/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 563static 564SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 565 TargetLowering &TLI) { 566 SDOperand Chain = ST->getChain(); 567 SDOperand Ptr = ST->getBasePtr(); 568 SDOperand Val = ST->getValue(); 569 MVT::ValueType VT = Val.getValueType(); 570 int Alignment = ST->getAlignment(); 571 int SVOffset = ST->getSrcValueOffset(); 572 if (MVT::isFloatingPoint(ST->getStoredVT())) { 573 // Expand to a bitconvert of the value to the integer type of the 574 // same size, then a (misaligned) int store. 575 MVT::ValueType intVT; 576 if (VT==MVT::f64) 577 intVT = MVT::i64; 578 else if (VT==MVT::f32) 579 intVT = MVT::i32; 580 else 581 assert(0 && "Unaligned load of unsupported floating point type"); 582 583 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 584 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 585 SVOffset, ST->isVolatile(), Alignment); 586 } 587 assert(MVT::isInteger(ST->getStoredVT()) && 588 "Unaligned store of unknown type."); 589 // Get the half-size VT 590 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1; 591 int NumBits = MVT::getSizeInBits(NewStoredVT); 592 int IncrementSize = NumBits / 8; 593 594 // Divide the stored value in two parts. 595 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 596 SDOperand Lo = Val; 597 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 598 599 // Store the two parts 600 SDOperand Store1, Store2; 601 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 602 ST->getSrcValue(), SVOffset, NewStoredVT, 603 ST->isVolatile(), Alignment); 604 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 605 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 606 Alignment = MinAlign(Alignment, IncrementSize); 607 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 608 ST->getSrcValue(), SVOffset + IncrementSize, 609 NewStoredVT, ST->isVolatile(), Alignment); 610 611 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 612} 613 614/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 615static 616SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 617 TargetLowering &TLI) { 618 int SVOffset = LD->getSrcValueOffset(); 619 SDOperand Chain = LD->getChain(); 620 SDOperand Ptr = LD->getBasePtr(); 621 MVT::ValueType VT = LD->getValueType(0); 622 MVT::ValueType LoadedVT = LD->getLoadedVT(); 623 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) { 624 // Expand to a (misaligned) integer load of the same size, 625 // then bitconvert to floating point. 626 MVT::ValueType intVT; 627 if (LoadedVT == MVT::f64) 628 intVT = MVT::i64; 629 else if (LoadedVT == MVT::f32) 630 intVT = MVT::i32; 631 else 632 assert(0 && "Unaligned load of unsupported floating point type"); 633 634 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 635 SVOffset, LD->isVolatile(), 636 LD->getAlignment()); 637 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 638 if (LoadedVT != VT) 639 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 640 641 SDOperand Ops[] = { Result, Chain }; 642 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 643 Ops, 2); 644 } 645 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) && 646 "Unaligned load of unsupported type."); 647 648 // Compute the new VT that is half the size of the old one. We either have an 649 // integer MVT or we have a vector MVT. 650 unsigned NumBits = MVT::getSizeInBits(LoadedVT); 651 MVT::ValueType NewLoadedVT; 652 if (!MVT::isVector(LoadedVT)) { 653 NewLoadedVT = MVT::getIntegerType(NumBits/2); 654 } else { 655 // FIXME: This is not right for <1 x anything> it is also not right for 656 // non-power-of-two vectors. 657 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT), 658 MVT::getVectorNumElements(LoadedVT)/2); 659 } 660 NumBits >>= 1; 661 662 unsigned Alignment = LD->getAlignment(); 663 unsigned IncrementSize = NumBits / 8; 664 ISD::LoadExtType HiExtType = LD->getExtensionType(); 665 666 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 667 if (HiExtType == ISD::NON_EXTLOAD) 668 HiExtType = ISD::ZEXTLOAD; 669 670 // Load the value in two parts 671 SDOperand Lo, Hi; 672 if (TLI.isLittleEndian()) { 673 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 674 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 675 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 676 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 677 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 678 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 679 MinAlign(Alignment, IncrementSize)); 680 } else { 681 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 682 NewLoadedVT,LD->isVolatile(), Alignment); 683 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 684 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 685 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 686 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 687 MinAlign(Alignment, IncrementSize)); 688 } 689 690 // aggregate the two parts 691 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 692 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 693 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 694 695 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 696 Hi.getValue(1)); 697 698 SDOperand Ops[] = { Result, TF }; 699 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 700} 701 702/// UnrollVectorOp - We know that the given vector has a legal type, however 703/// the operation it performs is not legal and is an operation that we have 704/// no way of lowering. "Unroll" the vector, splitting out the scalars and 705/// operating on each element individually. 706SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 707 MVT::ValueType VT = Op.getValueType(); 708 assert(isTypeLegal(VT) && 709 "Caller should expand or promote operands that are not legal!"); 710 assert(Op.Val->getNumValues() == 1 && 711 "Can't unroll a vector with multiple results!"); 712 unsigned NE = MVT::getVectorNumElements(VT); 713 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 714 715 SmallVector<SDOperand, 8> Scalars; 716 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 717 for (unsigned i = 0; i != NE; ++i) { 718 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 719 SDOperand Operand = Op.getOperand(j); 720 MVT::ValueType OperandVT = Operand.getValueType(); 721 if (MVT::isVector(OperandVT)) { 722 // A vector operand; extract a single element. 723 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT); 724 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 725 OperandEltVT, 726 Operand, 727 DAG.getConstant(i, MVT::i32)); 728 } else { 729 // A scalar operand; just use it as is. 730 Operands[j] = Operand; 731 } 732 } 733 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 734 &Operands[0], Operands.size())); 735 } 736 737 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 738} 739 740/// LegalizeOp - We know that the specified value has a legal type, and 741/// that its operands are legal. Now ensure that the operation itself 742/// is legal, recursively ensuring that the operands' operations remain 743/// legal. 744SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 745 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 746 return Op; 747 748 assert(isTypeLegal(Op.getValueType()) && 749 "Caller should expand or promote operands that are not legal!"); 750 SDNode *Node = Op.Val; 751 752 // If this operation defines any values that cannot be represented in a 753 // register on this target, make sure to expand or promote them. 754 if (Node->getNumValues() > 1) { 755 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 756 if (getTypeAction(Node->getValueType(i)) != Legal) { 757 HandleOp(Op.getValue(i)); 758 assert(LegalizedNodes.count(Op) && 759 "Handling didn't add legal operands!"); 760 return LegalizedNodes[Op]; 761 } 762 } 763 764 // Note that LegalizeOp may be reentered even from single-use nodes, which 765 // means that we always must cache transformed nodes. 766 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 767 if (I != LegalizedNodes.end()) return I->second; 768 769 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 770 SDOperand Result = Op; 771 bool isCustom = false; 772 773 switch (Node->getOpcode()) { 774 case ISD::FrameIndex: 775 case ISD::EntryToken: 776 case ISD::Register: 777 case ISD::BasicBlock: 778 case ISD::TargetFrameIndex: 779 case ISD::TargetJumpTable: 780 case ISD::TargetConstant: 781 case ISD::TargetConstantFP: 782 case ISD::TargetConstantPool: 783 case ISD::TargetGlobalAddress: 784 case ISD::TargetGlobalTLSAddress: 785 case ISD::TargetExternalSymbol: 786 case ISD::VALUETYPE: 787 case ISD::SRCVALUE: 788 case ISD::STRING: 789 case ISD::CONDCODE: 790 // Primitives must all be legal. 791 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 792 "This must be legal!"); 793 break; 794 default: 795 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 796 // If this is a target node, legalize it by legalizing the operands then 797 // passing it through. 798 SmallVector<SDOperand, 8> Ops; 799 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 800 Ops.push_back(LegalizeOp(Node->getOperand(i))); 801 802 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 803 804 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 805 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 806 return Result.getValue(Op.ResNo); 807 } 808 // Otherwise this is an unhandled builtin node. splat. 809#ifndef NDEBUG 810 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 811#endif 812 assert(0 && "Do not know how to legalize this operator!"); 813 abort(); 814 case ISD::GLOBAL_OFFSET_TABLE: 815 case ISD::GlobalAddress: 816 case ISD::GlobalTLSAddress: 817 case ISD::ExternalSymbol: 818 case ISD::ConstantPool: 819 case ISD::JumpTable: // Nothing to do. 820 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 821 default: assert(0 && "This action is not supported yet!"); 822 case TargetLowering::Custom: 823 Tmp1 = TLI.LowerOperation(Op, DAG); 824 if (Tmp1.Val) Result = Tmp1; 825 // FALLTHROUGH if the target doesn't want to lower this op after all. 826 case TargetLowering::Legal: 827 break; 828 } 829 break; 830 case ISD::FRAMEADDR: 831 case ISD::RETURNADDR: 832 // The only option for these nodes is to custom lower them. If the target 833 // does not custom lower them, then return zero. 834 Tmp1 = TLI.LowerOperation(Op, DAG); 835 if (Tmp1.Val) 836 Result = Tmp1; 837 else 838 Result = DAG.getConstant(0, TLI.getPointerTy()); 839 break; 840 case ISD::FRAME_TO_ARGS_OFFSET: { 841 MVT::ValueType VT = Node->getValueType(0); 842 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 843 default: assert(0 && "This action is not supported yet!"); 844 case TargetLowering::Custom: 845 Result = TLI.LowerOperation(Op, DAG); 846 if (Result.Val) break; 847 // Fall Thru 848 case TargetLowering::Legal: 849 Result = DAG.getConstant(0, VT); 850 break; 851 } 852 } 853 break; 854 case ISD::EXCEPTIONADDR: { 855 Tmp1 = LegalizeOp(Node->getOperand(0)); 856 MVT::ValueType VT = Node->getValueType(0); 857 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 858 default: assert(0 && "This action is not supported yet!"); 859 case TargetLowering::Expand: { 860 unsigned Reg = TLI.getExceptionAddressRegister(); 861 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 862 } 863 break; 864 case TargetLowering::Custom: 865 Result = TLI.LowerOperation(Op, DAG); 866 if (Result.Val) break; 867 // Fall Thru 868 case TargetLowering::Legal: { 869 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 870 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 871 Ops, 2); 872 break; 873 } 874 } 875 } 876 if (Result.Val->getNumValues() == 1) break; 877 878 assert(Result.Val->getNumValues() == 2 && 879 "Cannot return more than two values!"); 880 881 // Since we produced two values, make sure to remember that we 882 // legalized both of them. 883 Tmp1 = LegalizeOp(Result); 884 Tmp2 = LegalizeOp(Result.getValue(1)); 885 AddLegalizedOperand(Op.getValue(0), Tmp1); 886 AddLegalizedOperand(Op.getValue(1), Tmp2); 887 return Op.ResNo ? Tmp2 : Tmp1; 888 case ISD::EHSELECTION: { 889 Tmp1 = LegalizeOp(Node->getOperand(0)); 890 Tmp2 = LegalizeOp(Node->getOperand(1)); 891 MVT::ValueType VT = Node->getValueType(0); 892 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 893 default: assert(0 && "This action is not supported yet!"); 894 case TargetLowering::Expand: { 895 unsigned Reg = TLI.getExceptionSelectorRegister(); 896 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 897 } 898 break; 899 case TargetLowering::Custom: 900 Result = TLI.LowerOperation(Op, DAG); 901 if (Result.Val) break; 902 // Fall Thru 903 case TargetLowering::Legal: { 904 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 905 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 906 Ops, 2); 907 break; 908 } 909 } 910 } 911 if (Result.Val->getNumValues() == 1) break; 912 913 assert(Result.Val->getNumValues() == 2 && 914 "Cannot return more than two values!"); 915 916 // Since we produced two values, make sure to remember that we 917 // legalized both of them. 918 Tmp1 = LegalizeOp(Result); 919 Tmp2 = LegalizeOp(Result.getValue(1)); 920 AddLegalizedOperand(Op.getValue(0), Tmp1); 921 AddLegalizedOperand(Op.getValue(1), Tmp2); 922 return Op.ResNo ? Tmp2 : Tmp1; 923 case ISD::EH_RETURN: { 924 MVT::ValueType VT = Node->getValueType(0); 925 // The only "good" option for this node is to custom lower it. 926 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 927 default: assert(0 && "This action is not supported at all!"); 928 case TargetLowering::Custom: 929 Result = TLI.LowerOperation(Op, DAG); 930 if (Result.Val) break; 931 // Fall Thru 932 case TargetLowering::Legal: 933 // Target does not know, how to lower this, lower to noop 934 Result = LegalizeOp(Node->getOperand(0)); 935 break; 936 } 937 } 938 break; 939 case ISD::AssertSext: 940 case ISD::AssertZext: 941 Tmp1 = LegalizeOp(Node->getOperand(0)); 942 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 943 break; 944 case ISD::MERGE_VALUES: 945 // Legalize eliminates MERGE_VALUES nodes. 946 Result = Node->getOperand(Op.ResNo); 947 break; 948 case ISD::CopyFromReg: 949 Tmp1 = LegalizeOp(Node->getOperand(0)); 950 Result = Op.getValue(0); 951 if (Node->getNumValues() == 2) { 952 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 953 } else { 954 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 955 if (Node->getNumOperands() == 3) { 956 Tmp2 = LegalizeOp(Node->getOperand(2)); 957 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 958 } else { 959 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 960 } 961 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 962 } 963 // Since CopyFromReg produces two values, make sure to remember that we 964 // legalized both of them. 965 AddLegalizedOperand(Op.getValue(0), Result); 966 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 967 return Result.getValue(Op.ResNo); 968 case ISD::UNDEF: { 969 MVT::ValueType VT = Op.getValueType(); 970 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 971 default: assert(0 && "This action is not supported yet!"); 972 case TargetLowering::Expand: 973 if (MVT::isInteger(VT)) 974 Result = DAG.getConstant(0, VT); 975 else if (MVT::isFloatingPoint(VT)) 976 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)), 977 VT); 978 else 979 assert(0 && "Unknown value type!"); 980 break; 981 case TargetLowering::Legal: 982 break; 983 } 984 break; 985 } 986 987 case ISD::INTRINSIC_W_CHAIN: 988 case ISD::INTRINSIC_WO_CHAIN: 989 case ISD::INTRINSIC_VOID: { 990 SmallVector<SDOperand, 8> Ops; 991 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 992 Ops.push_back(LegalizeOp(Node->getOperand(i))); 993 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 994 995 // Allow the target to custom lower its intrinsics if it wants to. 996 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 997 TargetLowering::Custom) { 998 Tmp3 = TLI.LowerOperation(Result, DAG); 999 if (Tmp3.Val) Result = Tmp3; 1000 } 1001 1002 if (Result.Val->getNumValues() == 1) break; 1003 1004 // Must have return value and chain result. 1005 assert(Result.Val->getNumValues() == 2 && 1006 "Cannot return more than two values!"); 1007 1008 // Since loads produce two values, make sure to remember that we 1009 // legalized both of them. 1010 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1011 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1012 return Result.getValue(Op.ResNo); 1013 } 1014 1015 case ISD::LOCATION: 1016 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 1017 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1018 1019 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 1020 case TargetLowering::Promote: 1021 default: assert(0 && "This action is not supported yet!"); 1022 case TargetLowering::Expand: { 1023 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1024 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1025 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 1026 1027 if (MMI && (useDEBUG_LOC || useLABEL)) { 1028 const std::string &FName = 1029 cast<StringSDNode>(Node->getOperand(3))->getValue(); 1030 const std::string &DirName = 1031 cast<StringSDNode>(Node->getOperand(4))->getValue(); 1032 unsigned SrcFile = MMI->RecordSource(DirName, FName); 1033 1034 SmallVector<SDOperand, 8> Ops; 1035 Ops.push_back(Tmp1); // chain 1036 SDOperand LineOp = Node->getOperand(1); 1037 SDOperand ColOp = Node->getOperand(2); 1038 1039 if (useDEBUG_LOC) { 1040 Ops.push_back(LineOp); // line # 1041 Ops.push_back(ColOp); // col # 1042 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1043 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1044 } else { 1045 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 1046 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 1047 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile); 1048 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 1049 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size()); 1050 } 1051 } else { 1052 Result = Tmp1; // chain 1053 } 1054 break; 1055 } 1056 case TargetLowering::Legal: 1057 if (Tmp1 != Node->getOperand(0) || 1058 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1059 SmallVector<SDOperand, 8> Ops; 1060 Ops.push_back(Tmp1); 1061 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1062 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1063 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1064 } else { 1065 // Otherwise promote them. 1066 Ops.push_back(PromoteOp(Node->getOperand(1))); 1067 Ops.push_back(PromoteOp(Node->getOperand(2))); 1068 } 1069 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1070 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1071 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1072 } 1073 break; 1074 } 1075 break; 1076 1077 case ISD::DEBUG_LOC: 1078 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1079 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1080 default: assert(0 && "This action is not supported yet!"); 1081 case TargetLowering::Legal: 1082 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1083 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1084 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1085 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1086 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1087 break; 1088 } 1089 break; 1090 1091 case ISD::LABEL: 1092 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!"); 1093 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1094 default: assert(0 && "This action is not supported yet!"); 1095 case TargetLowering::Legal: 1096 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1097 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1098 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1099 break; 1100 case TargetLowering::Expand: 1101 Result = LegalizeOp(Node->getOperand(0)); 1102 break; 1103 } 1104 break; 1105 1106 case ISD::Constant: { 1107 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1108 unsigned opAction = 1109 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1110 1111 // We know we don't need to expand constants here, constants only have one 1112 // value and we check that it is fine above. 1113 1114 if (opAction == TargetLowering::Custom) { 1115 Tmp1 = TLI.LowerOperation(Result, DAG); 1116 if (Tmp1.Val) 1117 Result = Tmp1; 1118 } 1119 break; 1120 } 1121 case ISD::ConstantFP: { 1122 // Spill FP immediates to the constant pool if the target cannot directly 1123 // codegen them. Targets often have some immediate values that can be 1124 // efficiently generated into an FP register without a load. We explicitly 1125 // leave these constants as ConstantFP nodes for the target to deal with. 1126 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1127 1128 // Check to see if this FP immediate is already legal. 1129 bool isLegal = false; 1130 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1131 E = TLI.legal_fpimm_end(); I != E; ++I) 1132 if (CFP->isExactlyValue(*I)) { 1133 isLegal = true; 1134 break; 1135 } 1136 1137 // If this is a legal constant, turn it into a TargetConstantFP node. 1138 if (isLegal) { 1139 Result = DAG.getTargetConstantFP(CFP->getValueAPF(), 1140 CFP->getValueType(0)); 1141 break; 1142 } 1143 1144 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1145 default: assert(0 && "This action is not supported yet!"); 1146 case TargetLowering::Custom: 1147 Tmp3 = TLI.LowerOperation(Result, DAG); 1148 if (Tmp3.Val) { 1149 Result = Tmp3; 1150 break; 1151 } 1152 // FALLTHROUGH 1153 case TargetLowering::Expand: 1154 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1155 } 1156 break; 1157 } 1158 case ISD::TokenFactor: 1159 if (Node->getNumOperands() == 2) { 1160 Tmp1 = LegalizeOp(Node->getOperand(0)); 1161 Tmp2 = LegalizeOp(Node->getOperand(1)); 1162 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1163 } else if (Node->getNumOperands() == 3) { 1164 Tmp1 = LegalizeOp(Node->getOperand(0)); 1165 Tmp2 = LegalizeOp(Node->getOperand(1)); 1166 Tmp3 = LegalizeOp(Node->getOperand(2)); 1167 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1168 } else { 1169 SmallVector<SDOperand, 8> Ops; 1170 // Legalize the operands. 1171 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1172 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1173 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1174 } 1175 break; 1176 1177 case ISD::FORMAL_ARGUMENTS: 1178 case ISD::CALL: 1179 // The only option for this is to custom lower it. 1180 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1181 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1182 1183 // The number of incoming and outgoing values should match; unless the final 1184 // outgoing value is a flag. 1185 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1186 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1187 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1188 MVT::Flag)) && 1189 "Lowering call/formal_arguments produced unexpected # results!"); 1190 1191 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1192 // remember that we legalized all of them, so it doesn't get relegalized. 1193 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1194 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1195 continue; 1196 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1197 if (Op.ResNo == i) 1198 Tmp2 = Tmp1; 1199 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1200 } 1201 return Tmp2; 1202 case ISD::EXTRACT_SUBREG: { 1203 Tmp1 = LegalizeOp(Node->getOperand(0)); 1204 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1205 assert(idx && "Operand must be a constant"); 1206 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1207 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1208 } 1209 break; 1210 case ISD::INSERT_SUBREG: { 1211 Tmp1 = LegalizeOp(Node->getOperand(0)); 1212 Tmp2 = LegalizeOp(Node->getOperand(1)); 1213 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1214 assert(idx && "Operand must be a constant"); 1215 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1216 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1217 } 1218 break; 1219 case ISD::BUILD_VECTOR: 1220 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1221 default: assert(0 && "This action is not supported yet!"); 1222 case TargetLowering::Custom: 1223 Tmp3 = TLI.LowerOperation(Result, DAG); 1224 if (Tmp3.Val) { 1225 Result = Tmp3; 1226 break; 1227 } 1228 // FALLTHROUGH 1229 case TargetLowering::Expand: 1230 Result = ExpandBUILD_VECTOR(Result.Val); 1231 break; 1232 } 1233 break; 1234 case ISD::INSERT_VECTOR_ELT: 1235 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1236 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 1237 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1238 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1239 1240 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1241 Node->getValueType(0))) { 1242 default: assert(0 && "This action is not supported yet!"); 1243 case TargetLowering::Legal: 1244 break; 1245 case TargetLowering::Custom: 1246 Tmp3 = TLI.LowerOperation(Result, DAG); 1247 if (Tmp3.Val) { 1248 Result = Tmp3; 1249 break; 1250 } 1251 // FALLTHROUGH 1252 case TargetLowering::Expand: { 1253 // If the insert index is a constant, codegen this as a scalar_to_vector, 1254 // then a shuffle that inserts it into the right position in the vector. 1255 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1256 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1257 Tmp1.getValueType(), Tmp2); 1258 1259 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1260 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1261 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1262 1263 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 1264 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 1265 // the RHS. 1266 SmallVector<SDOperand, 8> ShufOps; 1267 for (unsigned i = 0; i != NumElts; ++i) { 1268 if (i != InsertPos->getValue()) 1269 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1270 else 1271 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1272 } 1273 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1274 &ShufOps[0], ShufOps.size()); 1275 1276 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1277 Tmp1, ScVec, ShufMask); 1278 Result = LegalizeOp(Result); 1279 break; 1280 } 1281 1282 // If the target doesn't support this, we have to spill the input vector 1283 // to a temporary stack slot, update the element, then reload it. This is 1284 // badness. We could also load the value into a vector register (either 1285 // with a "move to register" or "extload into register" instruction, then 1286 // permute it into place, if the idx is a constant and if the idx is 1287 // supported by the target. 1288 MVT::ValueType VT = Tmp1.getValueType(); 1289 MVT::ValueType EltVT = Tmp2.getValueType(); 1290 MVT::ValueType IdxVT = Tmp3.getValueType(); 1291 MVT::ValueType PtrVT = TLI.getPointerTy(); 1292 SDOperand StackPtr = DAG.CreateStackTemporary(VT); 1293 // Store the vector. 1294 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); 1295 1296 // Truncate or zero extend offset to target pointer type. 1297 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1298 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1299 // Add the offset to the index. 1300 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1301 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1302 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1303 // Store the scalar value. 1304 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); 1305 // Load the updated vector. 1306 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 1307 break; 1308 } 1309 } 1310 break; 1311 case ISD::SCALAR_TO_VECTOR: 1312 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1313 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1314 break; 1315 } 1316 1317 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1318 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1319 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1320 Node->getValueType(0))) { 1321 default: assert(0 && "This action is not supported yet!"); 1322 case TargetLowering::Legal: 1323 break; 1324 case TargetLowering::Custom: 1325 Tmp3 = TLI.LowerOperation(Result, DAG); 1326 if (Tmp3.Val) { 1327 Result = Tmp3; 1328 break; 1329 } 1330 // FALLTHROUGH 1331 case TargetLowering::Expand: 1332 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1333 break; 1334 } 1335 break; 1336 case ISD::VECTOR_SHUFFLE: 1337 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1338 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1339 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1340 1341 // Allow targets to custom lower the SHUFFLEs they support. 1342 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1343 default: assert(0 && "Unknown operation action!"); 1344 case TargetLowering::Legal: 1345 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1346 "vector shuffle should not be created if not legal!"); 1347 break; 1348 case TargetLowering::Custom: 1349 Tmp3 = TLI.LowerOperation(Result, DAG); 1350 if (Tmp3.Val) { 1351 Result = Tmp3; 1352 break; 1353 } 1354 // FALLTHROUGH 1355 case TargetLowering::Expand: { 1356 MVT::ValueType VT = Node->getValueType(0); 1357 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1358 MVT::ValueType PtrVT = TLI.getPointerTy(); 1359 SDOperand Mask = Node->getOperand(2); 1360 unsigned NumElems = Mask.getNumOperands(); 1361 SmallVector<SDOperand,8> Ops; 1362 for (unsigned i = 0; i != NumElems; ++i) { 1363 SDOperand Arg = Mask.getOperand(i); 1364 if (Arg.getOpcode() == ISD::UNDEF) { 1365 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1366 } else { 1367 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1368 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1369 if (Idx < NumElems) 1370 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1371 DAG.getConstant(Idx, PtrVT))); 1372 else 1373 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1374 DAG.getConstant(Idx - NumElems, PtrVT))); 1375 } 1376 } 1377 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1378 break; 1379 } 1380 case TargetLowering::Promote: { 1381 // Change base type to a different vector type. 1382 MVT::ValueType OVT = Node->getValueType(0); 1383 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1384 1385 // Cast the two input vectors. 1386 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1387 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1388 1389 // Convert the shuffle mask to the right # elements. 1390 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1391 assert(Tmp3.Val && "Shuffle not legal?"); 1392 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1393 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1394 break; 1395 } 1396 } 1397 break; 1398 1399 case ISD::EXTRACT_VECTOR_ELT: 1400 Tmp1 = Node->getOperand(0); 1401 Tmp2 = LegalizeOp(Node->getOperand(1)); 1402 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1403 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1404 break; 1405 1406 case ISD::EXTRACT_SUBVECTOR: 1407 Tmp1 = Node->getOperand(0); 1408 Tmp2 = LegalizeOp(Node->getOperand(1)); 1409 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1410 Result = ExpandEXTRACT_SUBVECTOR(Result); 1411 break; 1412 1413 case ISD::CALLSEQ_START: { 1414 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1415 1416 // Recursively Legalize all of the inputs of the call end that do not lead 1417 // to this call start. This ensures that any libcalls that need be inserted 1418 // are inserted *before* the CALLSEQ_START. 1419 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1420 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1421 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1422 NodesLeadingTo); 1423 } 1424 1425 // Now that we legalized all of the inputs (which may have inserted 1426 // libcalls) create the new CALLSEQ_START node. 1427 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1428 1429 // Merge in the last call, to ensure that this call start after the last 1430 // call ended. 1431 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1432 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1433 Tmp1 = LegalizeOp(Tmp1); 1434 } 1435 1436 // Do not try to legalize the target-specific arguments (#1+). 1437 if (Tmp1 != Node->getOperand(0)) { 1438 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1439 Ops[0] = Tmp1; 1440 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1441 } 1442 1443 // Remember that the CALLSEQ_START is legalized. 1444 AddLegalizedOperand(Op.getValue(0), Result); 1445 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1446 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1447 1448 // Now that the callseq_start and all of the non-call nodes above this call 1449 // sequence have been legalized, legalize the call itself. During this 1450 // process, no libcalls can/will be inserted, guaranteeing that no calls 1451 // can overlap. 1452 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1453 SDOperand InCallSEQ = LastCALLSEQ_END; 1454 // Note that we are selecting this call! 1455 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1456 IsLegalizingCall = true; 1457 1458 // Legalize the call, starting from the CALLSEQ_END. 1459 LegalizeOp(LastCALLSEQ_END); 1460 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1461 return Result; 1462 } 1463 case ISD::CALLSEQ_END: 1464 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1465 // will cause this node to be legalized as well as handling libcalls right. 1466 if (LastCALLSEQ_END.Val != Node) { 1467 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1468 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1469 assert(I != LegalizedNodes.end() && 1470 "Legalizing the call start should have legalized this node!"); 1471 return I->second; 1472 } 1473 1474 // Otherwise, the call start has been legalized and everything is going 1475 // according to plan. Just legalize ourselves normally here. 1476 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1477 // Do not try to legalize the target-specific arguments (#1+), except for 1478 // an optional flag input. 1479 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1480 if (Tmp1 != Node->getOperand(0)) { 1481 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1482 Ops[0] = Tmp1; 1483 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1484 } 1485 } else { 1486 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1487 if (Tmp1 != Node->getOperand(0) || 1488 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1489 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1490 Ops[0] = Tmp1; 1491 Ops.back() = Tmp2; 1492 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1493 } 1494 } 1495 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1496 // This finishes up call legalization. 1497 IsLegalizingCall = false; 1498 1499 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1500 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1501 if (Node->getNumValues() == 2) 1502 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1503 return Result.getValue(Op.ResNo); 1504 case ISD::DYNAMIC_STACKALLOC: { 1505 MVT::ValueType VT = Node->getValueType(0); 1506 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1507 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1508 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1509 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1510 1511 Tmp1 = Result.getValue(0); 1512 Tmp2 = Result.getValue(1); 1513 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1514 default: assert(0 && "This action is not supported yet!"); 1515 case TargetLowering::Expand: { 1516 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1517 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1518 " not tell us which reg is the stack pointer!"); 1519 SDOperand Chain = Tmp1.getOperand(0); 1520 1521 // Chain the dynamic stack allocation so that it doesn't modify the stack 1522 // pointer when other instructions are using the stack. 1523 Chain = DAG.getCALLSEQ_START(Chain, 1524 DAG.getConstant(0, TLI.getPointerTy())); 1525 1526 SDOperand Size = Tmp2.getOperand(1); 1527 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1528 Chain = SP.getValue(1); 1529 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1530 unsigned StackAlign = 1531 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1532 if (Align > StackAlign) 1533 SP = DAG.getNode(ISD::AND, VT, SP, 1534 DAG.getConstant(-(uint64_t)Align, VT)); 1535 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1536 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1537 1538 Tmp2 = 1539 DAG.getCALLSEQ_END(Chain, 1540 DAG.getConstant(0, TLI.getPointerTy()), 1541 DAG.getConstant(0, TLI.getPointerTy()), 1542 SDOperand()); 1543 1544 Tmp1 = LegalizeOp(Tmp1); 1545 Tmp2 = LegalizeOp(Tmp2); 1546 break; 1547 } 1548 case TargetLowering::Custom: 1549 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1550 if (Tmp3.Val) { 1551 Tmp1 = LegalizeOp(Tmp3); 1552 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1553 } 1554 break; 1555 case TargetLowering::Legal: 1556 break; 1557 } 1558 // Since this op produce two values, make sure to remember that we 1559 // legalized both of them. 1560 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1561 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1562 return Op.ResNo ? Tmp2 : Tmp1; 1563 } 1564 case ISD::INLINEASM: { 1565 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1566 bool Changed = false; 1567 // Legalize all of the operands of the inline asm, in case they are nodes 1568 // that need to be expanded or something. Note we skip the asm string and 1569 // all of the TargetConstant flags. 1570 SDOperand Op = LegalizeOp(Ops[0]); 1571 Changed = Op != Ops[0]; 1572 Ops[0] = Op; 1573 1574 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1575 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1576 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1577 for (++i; NumVals; ++i, --NumVals) { 1578 SDOperand Op = LegalizeOp(Ops[i]); 1579 if (Op != Ops[i]) { 1580 Changed = true; 1581 Ops[i] = Op; 1582 } 1583 } 1584 } 1585 1586 if (HasInFlag) { 1587 Op = LegalizeOp(Ops.back()); 1588 Changed |= Op != Ops.back(); 1589 Ops.back() = Op; 1590 } 1591 1592 if (Changed) 1593 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1594 1595 // INLINE asm returns a chain and flag, make sure to add both to the map. 1596 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1597 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1598 return Result.getValue(Op.ResNo); 1599 } 1600 case ISD::BR: 1601 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1602 // Ensure that libcalls are emitted before a branch. 1603 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1604 Tmp1 = LegalizeOp(Tmp1); 1605 LastCALLSEQ_END = DAG.getEntryNode(); 1606 1607 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1608 break; 1609 case ISD::BRIND: 1610 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1611 // Ensure that libcalls are emitted before a branch. 1612 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1613 Tmp1 = LegalizeOp(Tmp1); 1614 LastCALLSEQ_END = DAG.getEntryNode(); 1615 1616 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1617 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1618 case Legal: 1619 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1620 break; 1621 } 1622 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1623 break; 1624 case ISD::BR_JT: 1625 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1626 // Ensure that libcalls are emitted before a branch. 1627 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1628 Tmp1 = LegalizeOp(Tmp1); 1629 LastCALLSEQ_END = DAG.getEntryNode(); 1630 1631 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1632 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1633 1634 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1635 default: assert(0 && "This action is not supported yet!"); 1636 case TargetLowering::Legal: break; 1637 case TargetLowering::Custom: 1638 Tmp1 = TLI.LowerOperation(Result, DAG); 1639 if (Tmp1.Val) Result = Tmp1; 1640 break; 1641 case TargetLowering::Expand: { 1642 SDOperand Chain = Result.getOperand(0); 1643 SDOperand Table = Result.getOperand(1); 1644 SDOperand Index = Result.getOperand(2); 1645 1646 MVT::ValueType PTy = TLI.getPointerTy(); 1647 MachineFunction &MF = DAG.getMachineFunction(); 1648 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1649 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1650 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1651 1652 SDOperand LD; 1653 switch (EntrySize) { 1654 default: assert(0 && "Size of jump table not supported yet."); break; 1655 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; 1656 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; 1657 } 1658 1659 Addr = LD; 1660 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1661 // For PIC, the sequence is: 1662 // BRIND(load(Jumptable + index) + RelocBase) 1663 // RelocBase can be JumpTable, GOT or some sort of global base. 1664 if (PTy != MVT::i32) 1665 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1666 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1667 TLI.getPICJumpTableRelocBase(Table, DAG)); 1668 } 1669 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1670 } 1671 } 1672 break; 1673 case ISD::BRCOND: 1674 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1675 // Ensure that libcalls are emitted before a return. 1676 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1677 Tmp1 = LegalizeOp(Tmp1); 1678 LastCALLSEQ_END = DAG.getEntryNode(); 1679 1680 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1681 case Expand: assert(0 && "It's impossible to expand bools"); 1682 case Legal: 1683 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1684 break; 1685 case Promote: 1686 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1687 1688 // The top bits of the promoted condition are not necessarily zero, ensure 1689 // that the value is properly zero extended. 1690 if (!DAG.MaskedValueIsZero(Tmp2, 1691 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1692 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1693 break; 1694 } 1695 1696 // Basic block destination (Op#2) is always legal. 1697 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1698 1699 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1700 default: assert(0 && "This action is not supported yet!"); 1701 case TargetLowering::Legal: break; 1702 case TargetLowering::Custom: 1703 Tmp1 = TLI.LowerOperation(Result, DAG); 1704 if (Tmp1.Val) Result = Tmp1; 1705 break; 1706 case TargetLowering::Expand: 1707 // Expand brcond's setcc into its constituent parts and create a BR_CC 1708 // Node. 1709 if (Tmp2.getOpcode() == ISD::SETCC) { 1710 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1711 Tmp2.getOperand(0), Tmp2.getOperand(1), 1712 Node->getOperand(2)); 1713 } else { 1714 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1715 DAG.getCondCode(ISD::SETNE), Tmp2, 1716 DAG.getConstant(0, Tmp2.getValueType()), 1717 Node->getOperand(2)); 1718 } 1719 break; 1720 } 1721 break; 1722 case ISD::BR_CC: 1723 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1724 // Ensure that libcalls are emitted before a branch. 1725 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1726 Tmp1 = LegalizeOp(Tmp1); 1727 Tmp2 = Node->getOperand(2); // LHS 1728 Tmp3 = Node->getOperand(3); // RHS 1729 Tmp4 = Node->getOperand(1); // CC 1730 1731 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1732 LastCALLSEQ_END = DAG.getEntryNode(); 1733 1734 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1735 // the LHS is a legal SETCC itself. In this case, we need to compare 1736 // the result against zero to select between true and false values. 1737 if (Tmp3.Val == 0) { 1738 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1739 Tmp4 = DAG.getCondCode(ISD::SETNE); 1740 } 1741 1742 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1743 Node->getOperand(4)); 1744 1745 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1746 default: assert(0 && "Unexpected action for BR_CC!"); 1747 case TargetLowering::Legal: break; 1748 case TargetLowering::Custom: 1749 Tmp4 = TLI.LowerOperation(Result, DAG); 1750 if (Tmp4.Val) Result = Tmp4; 1751 break; 1752 } 1753 break; 1754 case ISD::LOAD: { 1755 LoadSDNode *LD = cast<LoadSDNode>(Node); 1756 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1757 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1758 1759 ISD::LoadExtType ExtType = LD->getExtensionType(); 1760 if (ExtType == ISD::NON_EXTLOAD) { 1761 MVT::ValueType VT = Node->getValueType(0); 1762 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1763 Tmp3 = Result.getValue(0); 1764 Tmp4 = Result.getValue(1); 1765 1766 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1767 default: assert(0 && "This action is not supported yet!"); 1768 case TargetLowering::Legal: 1769 // If this is an unaligned load and the target doesn't support it, 1770 // expand it. 1771 if (!TLI.allowsUnalignedMemoryAccesses()) { 1772 unsigned ABIAlignment = TLI.getTargetData()-> 1773 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1774 if (LD->getAlignment() < ABIAlignment){ 1775 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1776 TLI); 1777 Tmp3 = Result.getOperand(0); 1778 Tmp4 = Result.getOperand(1); 1779 Tmp3 = LegalizeOp(Tmp3); 1780 Tmp4 = LegalizeOp(Tmp4); 1781 } 1782 } 1783 break; 1784 case TargetLowering::Custom: 1785 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1786 if (Tmp1.Val) { 1787 Tmp3 = LegalizeOp(Tmp1); 1788 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1789 } 1790 break; 1791 case TargetLowering::Promote: { 1792 // Only promote a load of vector type to another. 1793 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1794 // Change base type to a different vector type. 1795 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1796 1797 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1798 LD->getSrcValueOffset(), 1799 LD->isVolatile(), LD->getAlignment()); 1800 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1801 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1802 break; 1803 } 1804 } 1805 // Since loads produce two values, make sure to remember that we 1806 // legalized both of them. 1807 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1808 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1809 return Op.ResNo ? Tmp4 : Tmp3; 1810 } else { 1811 MVT::ValueType SrcVT = LD->getLoadedVT(); 1812 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1813 default: assert(0 && "This action is not supported yet!"); 1814 case TargetLowering::Promote: 1815 assert(SrcVT == MVT::i1 && 1816 "Can only promote extending LOAD from i1 -> i8!"); 1817 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1818 LD->getSrcValue(), LD->getSrcValueOffset(), 1819 MVT::i8, LD->isVolatile(), LD->getAlignment()); 1820 Tmp1 = Result.getValue(0); 1821 Tmp2 = Result.getValue(1); 1822 break; 1823 case TargetLowering::Custom: 1824 isCustom = true; 1825 // FALLTHROUGH 1826 case TargetLowering::Legal: 1827 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1828 Tmp1 = Result.getValue(0); 1829 Tmp2 = Result.getValue(1); 1830 1831 if (isCustom) { 1832 Tmp3 = TLI.LowerOperation(Result, DAG); 1833 if (Tmp3.Val) { 1834 Tmp1 = LegalizeOp(Tmp3); 1835 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1836 } 1837 } else { 1838 // If this is an unaligned load and the target doesn't support it, 1839 // expand it. 1840 if (!TLI.allowsUnalignedMemoryAccesses()) { 1841 unsigned ABIAlignment = TLI.getTargetData()-> 1842 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1843 if (LD->getAlignment() < ABIAlignment){ 1844 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1845 TLI); 1846 Tmp1 = Result.getOperand(0); 1847 Tmp2 = Result.getOperand(1); 1848 Tmp1 = LegalizeOp(Tmp1); 1849 Tmp2 = LegalizeOp(Tmp2); 1850 } 1851 } 1852 } 1853 break; 1854 case TargetLowering::Expand: 1855 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1856 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1857 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1858 LD->getSrcValueOffset(), 1859 LD->isVolatile(), LD->getAlignment()); 1860 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1861 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1862 Tmp2 = LegalizeOp(Load.getValue(1)); 1863 break; 1864 } 1865 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1866 // Turn the unsupported load into an EXTLOAD followed by an explicit 1867 // zero/sign extend inreg. 1868 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1869 Tmp1, Tmp2, LD->getSrcValue(), 1870 LD->getSrcValueOffset(), SrcVT, 1871 LD->isVolatile(), LD->getAlignment()); 1872 SDOperand ValRes; 1873 if (ExtType == ISD::SEXTLOAD) 1874 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1875 Result, DAG.getValueType(SrcVT)); 1876 else 1877 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1878 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1879 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1880 break; 1881 } 1882 // Since loads produce two values, make sure to remember that we legalized 1883 // both of them. 1884 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1885 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1886 return Op.ResNo ? Tmp2 : Tmp1; 1887 } 1888 } 1889 case ISD::EXTRACT_ELEMENT: { 1890 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1891 switch (getTypeAction(OpTy)) { 1892 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1893 case Legal: 1894 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1895 // 1 -> Hi 1896 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1897 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1898 TLI.getShiftAmountTy())); 1899 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1900 } else { 1901 // 0 -> Lo 1902 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1903 Node->getOperand(0)); 1904 } 1905 break; 1906 case Expand: 1907 // Get both the low and high parts. 1908 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1909 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1910 Result = Tmp2; // 1 -> Hi 1911 else 1912 Result = Tmp1; // 0 -> Lo 1913 break; 1914 } 1915 break; 1916 } 1917 1918 case ISD::CopyToReg: 1919 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1920 1921 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1922 "Register type must be legal!"); 1923 // Legalize the incoming value (must be a legal type). 1924 Tmp2 = LegalizeOp(Node->getOperand(2)); 1925 if (Node->getNumValues() == 1) { 1926 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1927 } else { 1928 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1929 if (Node->getNumOperands() == 4) { 1930 Tmp3 = LegalizeOp(Node->getOperand(3)); 1931 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1932 Tmp3); 1933 } else { 1934 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1935 } 1936 1937 // Since this produces two values, make sure to remember that we legalized 1938 // both of them. 1939 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1940 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1941 return Result; 1942 } 1943 break; 1944 1945 case ISD::RET: 1946 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1947 1948 // Ensure that libcalls are emitted before a return. 1949 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1950 Tmp1 = LegalizeOp(Tmp1); 1951 LastCALLSEQ_END = DAG.getEntryNode(); 1952 1953 switch (Node->getNumOperands()) { 1954 case 3: // ret val 1955 Tmp2 = Node->getOperand(1); 1956 Tmp3 = Node->getOperand(2); // Signness 1957 switch (getTypeAction(Tmp2.getValueType())) { 1958 case Legal: 1959 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1960 break; 1961 case Expand: 1962 if (!MVT::isVector(Tmp2.getValueType())) { 1963 SDOperand Lo, Hi; 1964 ExpandOp(Tmp2, Lo, Hi); 1965 1966 // Big endian systems want the hi reg first. 1967 if (!TLI.isLittleEndian()) 1968 std::swap(Lo, Hi); 1969 1970 if (Hi.Val) 1971 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1972 else 1973 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 1974 Result = LegalizeOp(Result); 1975 } else { 1976 SDNode *InVal = Tmp2.Val; 1977 int InIx = Tmp2.ResNo; 1978 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 1979 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 1980 1981 // Figure out if there is a simple type corresponding to this Vector 1982 // type. If so, convert to the vector type. 1983 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1984 if (TLI.isTypeLegal(TVT)) { 1985 // Turn this into a return of the vector type. 1986 Tmp2 = LegalizeOp(Tmp2); 1987 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1988 } else if (NumElems == 1) { 1989 // Turn this into a return of the scalar type. 1990 Tmp2 = ScalarizeVectorOp(Tmp2); 1991 Tmp2 = LegalizeOp(Tmp2); 1992 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1993 1994 // FIXME: Returns of gcc generic vectors smaller than a legal type 1995 // should be returned in integer registers! 1996 1997 // The scalarized value type may not be legal, e.g. it might require 1998 // promotion or expansion. Relegalize the return. 1999 Result = LegalizeOp(Result); 2000 } else { 2001 // FIXME: Returns of gcc generic vectors larger than a legal vector 2002 // type should be returned by reference! 2003 SDOperand Lo, Hi; 2004 SplitVectorOp(Tmp2, Lo, Hi); 2005 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2006 Result = LegalizeOp(Result); 2007 } 2008 } 2009 break; 2010 case Promote: 2011 Tmp2 = PromoteOp(Node->getOperand(1)); 2012 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2013 Result = LegalizeOp(Result); 2014 break; 2015 } 2016 break; 2017 case 1: // ret void 2018 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2019 break; 2020 default: { // ret <values> 2021 SmallVector<SDOperand, 8> NewValues; 2022 NewValues.push_back(Tmp1); 2023 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2024 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2025 case Legal: 2026 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2027 NewValues.push_back(Node->getOperand(i+1)); 2028 break; 2029 case Expand: { 2030 SDOperand Lo, Hi; 2031 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && 2032 "FIXME: TODO: implement returning non-legal vector types!"); 2033 ExpandOp(Node->getOperand(i), Lo, Hi); 2034 NewValues.push_back(Lo); 2035 NewValues.push_back(Node->getOperand(i+1)); 2036 if (Hi.Val) { 2037 NewValues.push_back(Hi); 2038 NewValues.push_back(Node->getOperand(i+1)); 2039 } 2040 break; 2041 } 2042 case Promote: 2043 assert(0 && "Can't promote multiple return value yet!"); 2044 } 2045 2046 if (NewValues.size() == Node->getNumOperands()) 2047 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2048 else 2049 Result = DAG.getNode(ISD::RET, MVT::Other, 2050 &NewValues[0], NewValues.size()); 2051 break; 2052 } 2053 } 2054 2055 if (Result.getOpcode() == ISD::RET) { 2056 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2057 default: assert(0 && "This action is not supported yet!"); 2058 case TargetLowering::Legal: break; 2059 case TargetLowering::Custom: 2060 Tmp1 = TLI.LowerOperation(Result, DAG); 2061 if (Tmp1.Val) Result = Tmp1; 2062 break; 2063 } 2064 } 2065 break; 2066 case ISD::STORE: { 2067 StoreSDNode *ST = cast<StoreSDNode>(Node); 2068 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2069 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2070 int SVOffset = ST->getSrcValueOffset(); 2071 unsigned Alignment = ST->getAlignment(); 2072 bool isVolatile = ST->isVolatile(); 2073 2074 if (!ST->isTruncatingStore()) { 2075 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2076 // FIXME: We shouldn't do this for TargetConstantFP's. 2077 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2078 // to phase ordering between legalized code and the dag combiner. This 2079 // probably means that we need to integrate dag combiner and legalizer 2080 // together. 2081 // We generally can't do this one for long doubles. 2082 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2083 if (CFP->getValueType(0) == MVT::f32 && 2084 getTypeAction(MVT::i32) == Legal) { 2085 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF(). 2086 convertToAPInt().getZExtValue(), 2087 MVT::i32); 2088 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2089 SVOffset, isVolatile, Alignment); 2090 break; 2091 } else if (CFP->getValueType(0) == MVT::f64) { 2092 // If this target supports 64-bit registers, do a single 64-bit store. 2093 if (getTypeAction(MVT::i64) == Legal) { 2094 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2095 getZExtValue(), MVT::i64); 2096 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2097 SVOffset, isVolatile, Alignment); 2098 break; 2099 } else if (getTypeAction(MVT::i32) == Legal) { 2100 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2101 // stores. If the target supports neither 32- nor 64-bits, this 2102 // xform is certainly not worth it. 2103 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue(); 2104 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32); 2105 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32); 2106 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 2107 2108 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2109 SVOffset, isVolatile, Alignment); 2110 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2111 getIntPtrConstant(4)); 2112 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2113 isVolatile, MinAlign(Alignment, 4U)); 2114 2115 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2116 break; 2117 } 2118 } 2119 } 2120 2121 switch (getTypeAction(ST->getStoredVT())) { 2122 case Legal: { 2123 Tmp3 = LegalizeOp(ST->getValue()); 2124 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2125 ST->getOffset()); 2126 2127 MVT::ValueType VT = Tmp3.getValueType(); 2128 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2129 default: assert(0 && "This action is not supported yet!"); 2130 case TargetLowering::Legal: 2131 // If this is an unaligned store and the target doesn't support it, 2132 // expand it. 2133 if (!TLI.allowsUnalignedMemoryAccesses()) { 2134 unsigned ABIAlignment = TLI.getTargetData()-> 2135 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2136 if (ST->getAlignment() < ABIAlignment) 2137 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2138 TLI); 2139 } 2140 break; 2141 case TargetLowering::Custom: 2142 Tmp1 = TLI.LowerOperation(Result, DAG); 2143 if (Tmp1.Val) Result = Tmp1; 2144 break; 2145 case TargetLowering::Promote: 2146 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 2147 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2148 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2149 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2150 ST->getSrcValue(), SVOffset, isVolatile, 2151 Alignment); 2152 break; 2153 } 2154 break; 2155 } 2156 case Promote: 2157 // Truncate the value and store the result. 2158 Tmp3 = PromoteOp(ST->getValue()); 2159 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2160 SVOffset, ST->getStoredVT(), 2161 isVolatile, Alignment); 2162 break; 2163 2164 case Expand: 2165 unsigned IncrementSize = 0; 2166 SDOperand Lo, Hi; 2167 2168 // If this is a vector type, then we have to calculate the increment as 2169 // the product of the element size in bytes, and the number of elements 2170 // in the high half of the vector. 2171 if (MVT::isVector(ST->getValue().getValueType())) { 2172 SDNode *InVal = ST->getValue().Val; 2173 int InIx = ST->getValue().ResNo; 2174 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 2175 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 2176 2177 // Figure out if there is a simple type corresponding to this Vector 2178 // type. If so, convert to the vector type. 2179 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2180 if (TLI.isTypeLegal(TVT)) { 2181 // Turn this into a normal store of the vector type. 2182 Tmp3 = LegalizeOp(Node->getOperand(1)); 2183 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2184 SVOffset, isVolatile, Alignment); 2185 Result = LegalizeOp(Result); 2186 break; 2187 } else if (NumElems == 1) { 2188 // Turn this into a normal store of the scalar type. 2189 Tmp3 = ScalarizeVectorOp(Node->getOperand(1)); 2190 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2191 SVOffset, isVolatile, Alignment); 2192 // The scalarized value type may not be legal, e.g. it might require 2193 // promotion or expansion. Relegalize the scalar store. 2194 Result = LegalizeOp(Result); 2195 break; 2196 } else { 2197 SplitVectorOp(Node->getOperand(1), Lo, Hi); 2198 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) * 2199 MVT::getSizeInBits(EVT)/8; 2200 } 2201 } else { 2202 ExpandOp(Node->getOperand(1), Lo, Hi); 2203 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 2204 2205 if (!TLI.isLittleEndian()) 2206 std::swap(Lo, Hi); 2207 } 2208 2209 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2210 SVOffset, isVolatile, Alignment); 2211 2212 if (Hi.Val == NULL) { 2213 // Must be int <-> float one-to-one expansion. 2214 Result = Lo; 2215 break; 2216 } 2217 2218 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2219 getIntPtrConstant(IncrementSize)); 2220 assert(isTypeLegal(Tmp2.getValueType()) && 2221 "Pointers must be legal!"); 2222 SVOffset += IncrementSize; 2223 Alignment = MinAlign(Alignment, IncrementSize); 2224 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2225 SVOffset, isVolatile, Alignment); 2226 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2227 break; 2228 } 2229 } else { 2230 // Truncating store 2231 assert(isTypeLegal(ST->getValue().getValueType()) && 2232 "Cannot handle illegal TRUNCSTORE yet!"); 2233 Tmp3 = LegalizeOp(ST->getValue()); 2234 2235 // The only promote case we handle is TRUNCSTORE:i1 X into 2236 // -> TRUNCSTORE:i8 (and X, 1) 2237 if (ST->getStoredVT() == MVT::i1 && 2238 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) { 2239 // Promote the bool to a mask then store. 2240 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3, 2241 DAG.getConstant(1, Tmp3.getValueType())); 2242 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2243 SVOffset, MVT::i8, 2244 isVolatile, Alignment); 2245 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2246 Tmp2 != ST->getBasePtr()) { 2247 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2248 ST->getOffset()); 2249 } 2250 2251 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT(); 2252 switch (TLI.getStoreXAction(StVT)) { 2253 default: assert(0 && "This action is not supported yet!"); 2254 case TargetLowering::Legal: 2255 // If this is an unaligned store and the target doesn't support it, 2256 // expand it. 2257 if (!TLI.allowsUnalignedMemoryAccesses()) { 2258 unsigned ABIAlignment = TLI.getTargetData()-> 2259 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2260 if (ST->getAlignment() < ABIAlignment) 2261 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2262 TLI); 2263 } 2264 break; 2265 case TargetLowering::Custom: 2266 Tmp1 = TLI.LowerOperation(Result, DAG); 2267 if (Tmp1.Val) Result = Tmp1; 2268 break; 2269 } 2270 } 2271 break; 2272 } 2273 case ISD::PCMARKER: 2274 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2275 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2276 break; 2277 case ISD::STACKSAVE: 2278 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2279 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2280 Tmp1 = Result.getValue(0); 2281 Tmp2 = Result.getValue(1); 2282 2283 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2284 default: assert(0 && "This action is not supported yet!"); 2285 case TargetLowering::Legal: break; 2286 case TargetLowering::Custom: 2287 Tmp3 = TLI.LowerOperation(Result, DAG); 2288 if (Tmp3.Val) { 2289 Tmp1 = LegalizeOp(Tmp3); 2290 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2291 } 2292 break; 2293 case TargetLowering::Expand: 2294 // Expand to CopyFromReg if the target set 2295 // StackPointerRegisterToSaveRestore. 2296 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2297 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2298 Node->getValueType(0)); 2299 Tmp2 = Tmp1.getValue(1); 2300 } else { 2301 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2302 Tmp2 = Node->getOperand(0); 2303 } 2304 break; 2305 } 2306 2307 // Since stacksave produce two values, make sure to remember that we 2308 // legalized both of them. 2309 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2310 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2311 return Op.ResNo ? Tmp2 : Tmp1; 2312 2313 case ISD::STACKRESTORE: 2314 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2315 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2316 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2317 2318 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2319 default: assert(0 && "This action is not supported yet!"); 2320 case TargetLowering::Legal: break; 2321 case TargetLowering::Custom: 2322 Tmp1 = TLI.LowerOperation(Result, DAG); 2323 if (Tmp1.Val) Result = Tmp1; 2324 break; 2325 case TargetLowering::Expand: 2326 // Expand to CopyToReg if the target set 2327 // StackPointerRegisterToSaveRestore. 2328 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2329 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2330 } else { 2331 Result = Tmp1; 2332 } 2333 break; 2334 } 2335 break; 2336 2337 case ISD::READCYCLECOUNTER: 2338 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2339 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2340 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2341 Node->getValueType(0))) { 2342 default: assert(0 && "This action is not supported yet!"); 2343 case TargetLowering::Legal: 2344 Tmp1 = Result.getValue(0); 2345 Tmp2 = Result.getValue(1); 2346 break; 2347 case TargetLowering::Custom: 2348 Result = TLI.LowerOperation(Result, DAG); 2349 Tmp1 = LegalizeOp(Result.getValue(0)); 2350 Tmp2 = LegalizeOp(Result.getValue(1)); 2351 break; 2352 } 2353 2354 // Since rdcc produce two values, make sure to remember that we legalized 2355 // both of them. 2356 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2357 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2358 return Result; 2359 2360 case ISD::SELECT: 2361 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2362 case Expand: assert(0 && "It's impossible to expand bools"); 2363 case Legal: 2364 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2365 break; 2366 case Promote: 2367 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2368 // Make sure the condition is either zero or one. 2369 if (!DAG.MaskedValueIsZero(Tmp1, 2370 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 2371 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2372 break; 2373 } 2374 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2375 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2376 2377 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2378 2379 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2380 default: assert(0 && "This action is not supported yet!"); 2381 case TargetLowering::Legal: break; 2382 case TargetLowering::Custom: { 2383 Tmp1 = TLI.LowerOperation(Result, DAG); 2384 if (Tmp1.Val) Result = Tmp1; 2385 break; 2386 } 2387 case TargetLowering::Expand: 2388 if (Tmp1.getOpcode() == ISD::SETCC) { 2389 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2390 Tmp2, Tmp3, 2391 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2392 } else { 2393 Result = DAG.getSelectCC(Tmp1, 2394 DAG.getConstant(0, Tmp1.getValueType()), 2395 Tmp2, Tmp3, ISD::SETNE); 2396 } 2397 break; 2398 case TargetLowering::Promote: { 2399 MVT::ValueType NVT = 2400 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2401 unsigned ExtOp, TruncOp; 2402 if (MVT::isVector(Tmp2.getValueType())) { 2403 ExtOp = ISD::BIT_CONVERT; 2404 TruncOp = ISD::BIT_CONVERT; 2405 } else if (MVT::isInteger(Tmp2.getValueType())) { 2406 ExtOp = ISD::ANY_EXTEND; 2407 TruncOp = ISD::TRUNCATE; 2408 } else { 2409 ExtOp = ISD::FP_EXTEND; 2410 TruncOp = ISD::FP_ROUND; 2411 } 2412 // Promote each of the values to the new type. 2413 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2414 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2415 // Perform the larger operation, then round down. 2416 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2417 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2418 break; 2419 } 2420 } 2421 break; 2422 case ISD::SELECT_CC: { 2423 Tmp1 = Node->getOperand(0); // LHS 2424 Tmp2 = Node->getOperand(1); // RHS 2425 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2426 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2427 SDOperand CC = Node->getOperand(4); 2428 2429 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2430 2431 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2432 // the LHS is a legal SETCC itself. In this case, we need to compare 2433 // the result against zero to select between true and false values. 2434 if (Tmp2.Val == 0) { 2435 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2436 CC = DAG.getCondCode(ISD::SETNE); 2437 } 2438 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2439 2440 // Everything is legal, see if we should expand this op or something. 2441 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2442 default: assert(0 && "This action is not supported yet!"); 2443 case TargetLowering::Legal: break; 2444 case TargetLowering::Custom: 2445 Tmp1 = TLI.LowerOperation(Result, DAG); 2446 if (Tmp1.Val) Result = Tmp1; 2447 break; 2448 } 2449 break; 2450 } 2451 case ISD::SETCC: 2452 Tmp1 = Node->getOperand(0); 2453 Tmp2 = Node->getOperand(1); 2454 Tmp3 = Node->getOperand(2); 2455 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2456 2457 // If we had to Expand the SetCC operands into a SELECT node, then it may 2458 // not always be possible to return a true LHS & RHS. In this case, just 2459 // return the value we legalized, returned in the LHS 2460 if (Tmp2.Val == 0) { 2461 Result = Tmp1; 2462 break; 2463 } 2464 2465 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2466 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2467 case TargetLowering::Custom: 2468 isCustom = true; 2469 // FALLTHROUGH. 2470 case TargetLowering::Legal: 2471 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2472 if (isCustom) { 2473 Tmp4 = TLI.LowerOperation(Result, DAG); 2474 if (Tmp4.Val) Result = Tmp4; 2475 } 2476 break; 2477 case TargetLowering::Promote: { 2478 // First step, figure out the appropriate operation to use. 2479 // Allow SETCC to not be supported for all legal data types 2480 // Mostly this targets FP 2481 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2482 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2483 2484 // Scan for the appropriate larger type to use. 2485 while (1) { 2486 NewInTy = (MVT::ValueType)(NewInTy+1); 2487 2488 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2489 "Fell off of the edge of the integer world"); 2490 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2491 "Fell off of the edge of the floating point world"); 2492 2493 // If the target supports SETCC of this type, use it. 2494 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2495 break; 2496 } 2497 if (MVT::isInteger(NewInTy)) 2498 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2499 else { 2500 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2501 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2502 } 2503 Tmp1 = LegalizeOp(Tmp1); 2504 Tmp2 = LegalizeOp(Tmp2); 2505 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2506 Result = LegalizeOp(Result); 2507 break; 2508 } 2509 case TargetLowering::Expand: 2510 // Expand a setcc node into a select_cc of the same condition, lhs, and 2511 // rhs that selects between const 1 (true) and const 0 (false). 2512 MVT::ValueType VT = Node->getValueType(0); 2513 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2514 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2515 Tmp3); 2516 break; 2517 } 2518 break; 2519 case ISD::MEMSET: 2520 case ISD::MEMCPY: 2521 case ISD::MEMMOVE: { 2522 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2523 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2524 2525 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2526 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2527 case Expand: assert(0 && "Cannot expand a byte!"); 2528 case Legal: 2529 Tmp3 = LegalizeOp(Node->getOperand(2)); 2530 break; 2531 case Promote: 2532 Tmp3 = PromoteOp(Node->getOperand(2)); 2533 break; 2534 } 2535 } else { 2536 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2537 } 2538 2539 SDOperand Tmp4; 2540 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2541 case Expand: { 2542 // Length is too big, just take the lo-part of the length. 2543 SDOperand HiPart; 2544 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2545 break; 2546 } 2547 case Legal: 2548 Tmp4 = LegalizeOp(Node->getOperand(3)); 2549 break; 2550 case Promote: 2551 Tmp4 = PromoteOp(Node->getOperand(3)); 2552 break; 2553 } 2554 2555 SDOperand Tmp5; 2556 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2557 case Expand: assert(0 && "Cannot expand this yet!"); 2558 case Legal: 2559 Tmp5 = LegalizeOp(Node->getOperand(4)); 2560 break; 2561 case Promote: 2562 Tmp5 = PromoteOp(Node->getOperand(4)); 2563 break; 2564 } 2565 2566 SDOperand Tmp6; 2567 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool 2568 case Expand: assert(0 && "Cannot expand this yet!"); 2569 case Legal: 2570 Tmp6 = LegalizeOp(Node->getOperand(5)); 2571 break; 2572 case Promote: 2573 Tmp6 = PromoteOp(Node->getOperand(5)); 2574 break; 2575 } 2576 2577 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2578 default: assert(0 && "This action not implemented for this operation!"); 2579 case TargetLowering::Custom: 2580 isCustom = true; 2581 // FALLTHROUGH 2582 case TargetLowering::Legal: { 2583 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 }; 2584 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 2585 if (isCustom) { 2586 Tmp1 = TLI.LowerOperation(Result, DAG); 2587 if (Tmp1.Val) Result = Tmp1; 2588 } 2589 break; 2590 } 2591 case TargetLowering::Expand: { 2592 // Otherwise, the target does not support this operation. Lower the 2593 // operation to an explicit libcall as appropriate. 2594 MVT::ValueType IntPtr = TLI.getPointerTy(); 2595 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2596 TargetLowering::ArgListTy Args; 2597 TargetLowering::ArgListEntry Entry; 2598 2599 const char *FnName = 0; 2600 if (Node->getOpcode() == ISD::MEMSET) { 2601 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; 2602 Args.push_back(Entry); 2603 // Extend the (previously legalized) ubyte argument to be an int value 2604 // for the call. 2605 if (Tmp3.getValueType() > MVT::i32) 2606 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2607 else 2608 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2609 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 2610 Args.push_back(Entry); 2611 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false; 2612 Args.push_back(Entry); 2613 2614 FnName = "memset"; 2615 } else if (Node->getOpcode() == ISD::MEMCPY || 2616 Node->getOpcode() == ISD::MEMMOVE) { 2617 Entry.Ty = IntPtrTy; 2618 Entry.Node = Tmp2; Args.push_back(Entry); 2619 Entry.Node = Tmp3; Args.push_back(Entry); 2620 Entry.Node = Tmp4; Args.push_back(Entry); 2621 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2622 } else { 2623 assert(0 && "Unknown op!"); 2624 } 2625 2626 std::pair<SDOperand,SDOperand> CallResult = 2627 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 2628 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2629 Result = CallResult.second; 2630 break; 2631 } 2632 } 2633 break; 2634 } 2635 2636 case ISD::SHL_PARTS: 2637 case ISD::SRA_PARTS: 2638 case ISD::SRL_PARTS: { 2639 SmallVector<SDOperand, 8> Ops; 2640 bool Changed = false; 2641 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2642 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2643 Changed |= Ops.back() != Node->getOperand(i); 2644 } 2645 if (Changed) 2646 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2647 2648 switch (TLI.getOperationAction(Node->getOpcode(), 2649 Node->getValueType(0))) { 2650 default: assert(0 && "This action is not supported yet!"); 2651 case TargetLowering::Legal: break; 2652 case TargetLowering::Custom: 2653 Tmp1 = TLI.LowerOperation(Result, DAG); 2654 if (Tmp1.Val) { 2655 SDOperand Tmp2, RetVal(0, 0); 2656 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2657 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2658 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2659 if (i == Op.ResNo) 2660 RetVal = Tmp2; 2661 } 2662 assert(RetVal.Val && "Illegal result number"); 2663 return RetVal; 2664 } 2665 break; 2666 } 2667 2668 // Since these produce multiple values, make sure to remember that we 2669 // legalized all of them. 2670 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2671 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2672 return Result.getValue(Op.ResNo); 2673 } 2674 2675 // Binary operators 2676 case ISD::ADD: 2677 case ISD::SUB: 2678 case ISD::MUL: 2679 case ISD::MULHS: 2680 case ISD::MULHU: 2681 case ISD::UDIV: 2682 case ISD::SDIV: 2683 case ISD::AND: 2684 case ISD::OR: 2685 case ISD::XOR: 2686 case ISD::SHL: 2687 case ISD::SRL: 2688 case ISD::SRA: 2689 case ISD::FADD: 2690 case ISD::FSUB: 2691 case ISD::FMUL: 2692 case ISD::FDIV: 2693 case ISD::FPOW: 2694 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2695 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2696 case Expand: assert(0 && "Not possible"); 2697 case Legal: 2698 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2699 break; 2700 case Promote: 2701 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2702 break; 2703 } 2704 2705 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2706 2707 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2708 default: assert(0 && "BinOp legalize operation not supported"); 2709 case TargetLowering::Legal: break; 2710 case TargetLowering::Custom: 2711 Tmp1 = TLI.LowerOperation(Result, DAG); 2712 if (Tmp1.Val) Result = Tmp1; 2713 break; 2714 case TargetLowering::Expand: { 2715 MVT::ValueType VT = Op.getValueType(); 2716 2717 // See if multiply or divide can be lowered using two-result operations. 2718 SDVTList VTs = DAG.getVTList(VT, VT); 2719 if (Node->getOpcode() == ISD::MUL) { 2720 // We just need the low half of the multiply; try both the signed 2721 // and unsigned forms. If the target supports both SMUL_LOHI and 2722 // UMUL_LOHI, form a preference by checking which forms of plain 2723 // MULH it supports. 2724 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2725 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2726 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2727 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2728 unsigned OpToUse = 0; 2729 if (HasSMUL_LOHI && !HasMULHS) { 2730 OpToUse = ISD::SMUL_LOHI; 2731 } else if (HasUMUL_LOHI && !HasMULHU) { 2732 OpToUse = ISD::UMUL_LOHI; 2733 } else if (HasSMUL_LOHI) { 2734 OpToUse = ISD::SMUL_LOHI; 2735 } else if (HasUMUL_LOHI) { 2736 OpToUse = ISD::UMUL_LOHI; 2737 } 2738 if (OpToUse) { 2739 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 2740 break; 2741 } 2742 } 2743 if (Node->getOpcode() == ISD::MULHS && 2744 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 2745 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2746 break; 2747 } 2748 if (Node->getOpcode() == ISD::MULHU && 2749 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 2750 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2751 break; 2752 } 2753 if (Node->getOpcode() == ISD::SDIV && 2754 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 2755 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 2756 break; 2757 } 2758 if (Node->getOpcode() == ISD::UDIV && 2759 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 2760 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 2761 break; 2762 } 2763 2764 // Check to see if we have a libcall for this operator. 2765 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2766 bool isSigned = false; 2767 switch (Node->getOpcode()) { 2768 case ISD::UDIV: 2769 case ISD::SDIV: 2770 if (VT == MVT::i32) { 2771 LC = Node->getOpcode() == ISD::UDIV 2772 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 2773 isSigned = Node->getOpcode() == ISD::SDIV; 2774 } 2775 break; 2776 case ISD::FPOW: 2777 LC = VT == MVT::f32 ? RTLIB::POW_F32 : 2778 VT == MVT::f64 ? RTLIB::POW_F64 : 2779 VT == MVT::f80 ? RTLIB::POW_F80 : 2780 VT == MVT::ppcf128 ? RTLIB::POW_PPCF128 : 2781 RTLIB::UNKNOWN_LIBCALL; 2782 break; 2783 default: break; 2784 } 2785 if (LC != RTLIB::UNKNOWN_LIBCALL) { 2786 SDOperand Dummy; 2787 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2788 break; 2789 } 2790 2791 assert(MVT::isVector(Node->getValueType(0)) && 2792 "Cannot expand this binary operator!"); 2793 // Expand the operation into a bunch of nasty scalar code. 2794 Result = LegalizeOp(UnrollVectorOp(Op)); 2795 break; 2796 } 2797 case TargetLowering::Promote: { 2798 switch (Node->getOpcode()) { 2799 default: assert(0 && "Do not know how to promote this BinOp!"); 2800 case ISD::AND: 2801 case ISD::OR: 2802 case ISD::XOR: { 2803 MVT::ValueType OVT = Node->getValueType(0); 2804 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2805 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2806 // Bit convert each of the values to the new type. 2807 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2808 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2809 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2810 // Bit convert the result back the original type. 2811 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2812 break; 2813 } 2814 } 2815 } 2816 } 2817 break; 2818 2819 case ISD::SMUL_LOHI: 2820 case ISD::UMUL_LOHI: 2821 case ISD::SDIVREM: 2822 case ISD::UDIVREM: 2823 // These nodes will only be produced by target-specific lowering, so 2824 // they shouldn't be here if they aren't legal. 2825 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 2826 "This must be legal!"); 2827 2828 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2829 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2830 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2831 break; 2832 2833 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2834 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2835 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2836 case Expand: assert(0 && "Not possible"); 2837 case Legal: 2838 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2839 break; 2840 case Promote: 2841 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2842 break; 2843 } 2844 2845 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2846 2847 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2848 default: assert(0 && "Operation not supported"); 2849 case TargetLowering::Custom: 2850 Tmp1 = TLI.LowerOperation(Result, DAG); 2851 if (Tmp1.Val) Result = Tmp1; 2852 break; 2853 case TargetLowering::Legal: break; 2854 case TargetLowering::Expand: { 2855 // If this target supports fabs/fneg natively and select is cheap, 2856 // do this efficiently. 2857 if (!TLI.isSelectExpensive() && 2858 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 2859 TargetLowering::Legal && 2860 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 2861 TargetLowering::Legal) { 2862 // Get the sign bit of the RHS. 2863 MVT::ValueType IVT = 2864 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2865 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2866 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2867 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2868 // Get the absolute value of the result. 2869 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2870 // Select between the nabs and abs value based on the sign bit of 2871 // the input. 2872 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2873 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2874 AbsVal), 2875 AbsVal); 2876 Result = LegalizeOp(Result); 2877 break; 2878 } 2879 2880 // Otherwise, do bitwise ops! 2881 MVT::ValueType NVT = 2882 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 2883 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 2884 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 2885 Result = LegalizeOp(Result); 2886 break; 2887 } 2888 } 2889 break; 2890 2891 case ISD::ADDC: 2892 case ISD::SUBC: 2893 Tmp1 = LegalizeOp(Node->getOperand(0)); 2894 Tmp2 = LegalizeOp(Node->getOperand(1)); 2895 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2896 // Since this produces two values, make sure to remember that we legalized 2897 // both of them. 2898 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2899 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2900 return Result; 2901 2902 case ISD::ADDE: 2903 case ISD::SUBE: 2904 Tmp1 = LegalizeOp(Node->getOperand(0)); 2905 Tmp2 = LegalizeOp(Node->getOperand(1)); 2906 Tmp3 = LegalizeOp(Node->getOperand(2)); 2907 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2908 // Since this produces two values, make sure to remember that we legalized 2909 // both of them. 2910 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2911 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2912 return Result; 2913 2914 case ISD::BUILD_PAIR: { 2915 MVT::ValueType PairTy = Node->getValueType(0); 2916 // TODO: handle the case where the Lo and Hi operands are not of legal type 2917 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2918 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2919 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2920 case TargetLowering::Promote: 2921 case TargetLowering::Custom: 2922 assert(0 && "Cannot promote/custom this yet!"); 2923 case TargetLowering::Legal: 2924 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2925 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2926 break; 2927 case TargetLowering::Expand: 2928 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2929 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2930 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2931 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2932 TLI.getShiftAmountTy())); 2933 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2934 break; 2935 } 2936 break; 2937 } 2938 2939 case ISD::UREM: 2940 case ISD::SREM: 2941 case ISD::FREM: 2942 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2943 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2944 2945 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2946 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2947 case TargetLowering::Custom: 2948 isCustom = true; 2949 // FALLTHROUGH 2950 case TargetLowering::Legal: 2951 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2952 if (isCustom) { 2953 Tmp1 = TLI.LowerOperation(Result, DAG); 2954 if (Tmp1.Val) Result = Tmp1; 2955 } 2956 break; 2957 case TargetLowering::Expand: { 2958 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2959 bool isSigned = DivOpc == ISD::SDIV; 2960 MVT::ValueType VT = Node->getValueType(0); 2961 2962 // See if remainder can be lowered using two-result operations. 2963 SDVTList VTs = DAG.getVTList(VT, VT); 2964 if (Node->getOpcode() == ISD::SREM && 2965 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 2966 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 2967 break; 2968 } 2969 if (Node->getOpcode() == ISD::UREM && 2970 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 2971 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 2972 break; 2973 } 2974 2975 if (MVT::isInteger(VT)) { 2976 if (TLI.getOperationAction(DivOpc, VT) == 2977 TargetLowering::Legal) { 2978 // X % Y -> X-X/Y*Y 2979 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 2980 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2981 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2982 } else if (MVT::isVector(VT)) { 2983 Result = LegalizeOp(UnrollVectorOp(Op)); 2984 } else { 2985 assert(VT == MVT::i32 && 2986 "Cannot expand this binary operator!"); 2987 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 2988 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 2989 SDOperand Dummy; 2990 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2991 } 2992 } else { 2993 assert(MVT::isFloatingPoint(VT) && 2994 "remainder op must have integer or floating-point type"); 2995 if (MVT::isVector(VT)) { 2996 Result = LegalizeOp(UnrollVectorOp(Op)); 2997 } else { 2998 // Floating point mod -> fmod libcall. 2999 RTLIB::Libcall LC = VT == MVT::f32 3000 ? RTLIB::REM_F32 : RTLIB::REM_F64; 3001 SDOperand Dummy; 3002 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3003 false/*sign irrelevant*/, Dummy); 3004 } 3005 } 3006 break; 3007 } 3008 } 3009 break; 3010 case ISD::VAARG: { 3011 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3012 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3013 3014 MVT::ValueType VT = Node->getValueType(0); 3015 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3016 default: assert(0 && "This action is not supported yet!"); 3017 case TargetLowering::Custom: 3018 isCustom = true; 3019 // FALLTHROUGH 3020 case TargetLowering::Legal: 3021 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3022 Result = Result.getValue(0); 3023 Tmp1 = Result.getValue(1); 3024 3025 if (isCustom) { 3026 Tmp2 = TLI.LowerOperation(Result, DAG); 3027 if (Tmp2.Val) { 3028 Result = LegalizeOp(Tmp2); 3029 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3030 } 3031 } 3032 break; 3033 case TargetLowering::Expand: { 3034 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 3035 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3036 SV->getValue(), SV->getOffset()); 3037 // Increment the pointer, VAList, to the next vaarg 3038 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3039 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3040 TLI.getPointerTy())); 3041 // Store the incremented VAList to the legalized pointer 3042 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 3043 SV->getOffset()); 3044 // Load the actual argument out of the pointer VAList 3045 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3046 Tmp1 = LegalizeOp(Result.getValue(1)); 3047 Result = LegalizeOp(Result); 3048 break; 3049 } 3050 } 3051 // Since VAARG produces two values, make sure to remember that we 3052 // legalized both of them. 3053 AddLegalizedOperand(SDOperand(Node, 0), Result); 3054 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3055 return Op.ResNo ? Tmp1 : Result; 3056 } 3057 3058 case ISD::VACOPY: 3059 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3060 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3061 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3062 3063 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3064 default: assert(0 && "This action is not supported yet!"); 3065 case TargetLowering::Custom: 3066 isCustom = true; 3067 // FALLTHROUGH 3068 case TargetLowering::Legal: 3069 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3070 Node->getOperand(3), Node->getOperand(4)); 3071 if (isCustom) { 3072 Tmp1 = TLI.LowerOperation(Result, DAG); 3073 if (Tmp1.Val) Result = Tmp1; 3074 } 3075 break; 3076 case TargetLowering::Expand: 3077 // This defaults to loading a pointer from the input and storing it to the 3078 // output, returning the chain. 3079 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 3080 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); 3081 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 3082 SVD->getOffset()); 3083 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), 3084 SVS->getOffset()); 3085 break; 3086 } 3087 break; 3088 3089 case ISD::VAEND: 3090 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3091 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3092 3093 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3094 default: assert(0 && "This action is not supported yet!"); 3095 case TargetLowering::Custom: 3096 isCustom = true; 3097 // FALLTHROUGH 3098 case TargetLowering::Legal: 3099 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3100 if (isCustom) { 3101 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3102 if (Tmp1.Val) Result = Tmp1; 3103 } 3104 break; 3105 case TargetLowering::Expand: 3106 Result = Tmp1; // Default to a no-op, return the chain 3107 break; 3108 } 3109 break; 3110 3111 case ISD::VASTART: 3112 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3113 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3114 3115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3116 3117 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3118 default: assert(0 && "This action is not supported yet!"); 3119 case TargetLowering::Legal: break; 3120 case TargetLowering::Custom: 3121 Tmp1 = TLI.LowerOperation(Result, DAG); 3122 if (Tmp1.Val) Result = Tmp1; 3123 break; 3124 } 3125 break; 3126 3127 case ISD::ROTL: 3128 case ISD::ROTR: 3129 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3130 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3131 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3132 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3133 default: 3134 assert(0 && "ROTL/ROTR legalize operation not supported"); 3135 break; 3136 case TargetLowering::Legal: 3137 break; 3138 case TargetLowering::Custom: 3139 Tmp1 = TLI.LowerOperation(Result, DAG); 3140 if (Tmp1.Val) Result = Tmp1; 3141 break; 3142 case TargetLowering::Promote: 3143 assert(0 && "Do not know how to promote ROTL/ROTR"); 3144 break; 3145 case TargetLowering::Expand: 3146 assert(0 && "Do not know how to expand ROTL/ROTR"); 3147 break; 3148 } 3149 break; 3150 3151 case ISD::BSWAP: 3152 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3153 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3154 case TargetLowering::Custom: 3155 assert(0 && "Cannot custom legalize this yet!"); 3156 case TargetLowering::Legal: 3157 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3158 break; 3159 case TargetLowering::Promote: { 3160 MVT::ValueType OVT = Tmp1.getValueType(); 3161 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3162 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 3163 3164 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3165 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3166 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3167 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3168 break; 3169 } 3170 case TargetLowering::Expand: 3171 Result = ExpandBSWAP(Tmp1); 3172 break; 3173 } 3174 break; 3175 3176 case ISD::CTPOP: 3177 case ISD::CTTZ: 3178 case ISD::CTLZ: 3179 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3180 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3181 case TargetLowering::Custom: 3182 case TargetLowering::Legal: 3183 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3184 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3185 TargetLowering::Custom) { 3186 Tmp1 = TLI.LowerOperation(Result, DAG); 3187 if (Tmp1.Val) { 3188 Result = Tmp1; 3189 } 3190 } 3191 break; 3192 case TargetLowering::Promote: { 3193 MVT::ValueType OVT = Tmp1.getValueType(); 3194 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3195 3196 // Zero extend the argument. 3197 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3198 // Perform the larger operation, then subtract if needed. 3199 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3200 switch (Node->getOpcode()) { 3201 case ISD::CTPOP: 3202 Result = Tmp1; 3203 break; 3204 case ISD::CTTZ: 3205 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3206 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3207 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3208 ISD::SETEQ); 3209 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3210 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 3211 break; 3212 case ISD::CTLZ: 3213 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3214 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3215 DAG.getConstant(MVT::getSizeInBits(NVT) - 3216 MVT::getSizeInBits(OVT), NVT)); 3217 break; 3218 } 3219 break; 3220 } 3221 case TargetLowering::Expand: 3222 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3223 break; 3224 } 3225 break; 3226 3227 // Unary operators 3228 case ISD::FABS: 3229 case ISD::FNEG: 3230 case ISD::FSQRT: 3231 case ISD::FSIN: 3232 case ISD::FCOS: 3233 Tmp1 = LegalizeOp(Node->getOperand(0)); 3234 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3235 case TargetLowering::Promote: 3236 case TargetLowering::Custom: 3237 isCustom = true; 3238 // FALLTHROUGH 3239 case TargetLowering::Legal: 3240 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3241 if (isCustom) { 3242 Tmp1 = TLI.LowerOperation(Result, DAG); 3243 if (Tmp1.Val) Result = Tmp1; 3244 } 3245 break; 3246 case TargetLowering::Expand: 3247 switch (Node->getOpcode()) { 3248 default: assert(0 && "Unreachable!"); 3249 case ISD::FNEG: 3250 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3251 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3252 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3253 break; 3254 case ISD::FABS: { 3255 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3256 MVT::ValueType VT = Node->getValueType(0); 3257 Tmp2 = DAG.getConstantFP(0.0, VT); 3258 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 3259 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3260 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3261 break; 3262 } 3263 case ISD::FSQRT: 3264 case ISD::FSIN: 3265 case ISD::FCOS: { 3266 MVT::ValueType VT = Node->getValueType(0); 3267 3268 // Expand unsupported unary vector operators by unrolling them. 3269 if (MVT::isVector(VT)) { 3270 Result = LegalizeOp(UnrollVectorOp(Op)); 3271 break; 3272 } 3273 3274 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3275 switch(Node->getOpcode()) { 3276 case ISD::FSQRT: 3277 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : 3278 VT == MVT::f64 ? RTLIB::SQRT_F64 : 3279 VT == MVT::f80 ? RTLIB::SQRT_F80 : 3280 VT == MVT::ppcf128 ? RTLIB::SQRT_PPCF128 : 3281 RTLIB::UNKNOWN_LIBCALL; 3282 break; 3283 case ISD::FSIN: 3284 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 3285 break; 3286 case ISD::FCOS: 3287 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64; 3288 break; 3289 default: assert(0 && "Unreachable!"); 3290 } 3291 SDOperand Dummy; 3292 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3293 false/*sign irrelevant*/, Dummy); 3294 break; 3295 } 3296 } 3297 break; 3298 } 3299 break; 3300 case ISD::FPOWI: { 3301 MVT::ValueType VT = Node->getValueType(0); 3302 3303 // Expand unsupported unary vector operators by unrolling them. 3304 if (MVT::isVector(VT)) { 3305 Result = LegalizeOp(UnrollVectorOp(Op)); 3306 break; 3307 } 3308 3309 // We always lower FPOWI into a libcall. No target support for it yet. 3310 RTLIB::Libcall LC = 3311 VT == MVT::f32 ? RTLIB::POWI_F32 : 3312 VT == MVT::f64 ? RTLIB::POWI_F64 : 3313 VT == MVT::f80 ? RTLIB::POWI_F80 : 3314 VT == MVT::ppcf128 ? RTLIB::POWI_PPCF128 : 3315 RTLIB::UNKNOWN_LIBCALL; 3316 SDOperand Dummy; 3317 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3318 false/*sign irrelevant*/, Dummy); 3319 break; 3320 } 3321 case ISD::BIT_CONVERT: 3322 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3323 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3324 } else if (MVT::isVector(Op.getOperand(0).getValueType())) { 3325 // The input has to be a vector type, we have to either scalarize it, pack 3326 // it, or convert it based on whether the input vector type is legal. 3327 SDNode *InVal = Node->getOperand(0).Val; 3328 int InIx = Node->getOperand(0).ResNo; 3329 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 3330 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 3331 3332 // Figure out if there is a simple type corresponding to this Vector 3333 // type. If so, convert to the vector type. 3334 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3335 if (TLI.isTypeLegal(TVT)) { 3336 // Turn this into a bit convert of the vector input. 3337 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3338 LegalizeOp(Node->getOperand(0))); 3339 break; 3340 } else if (NumElems == 1) { 3341 // Turn this into a bit convert of the scalar input. 3342 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3343 ScalarizeVectorOp(Node->getOperand(0))); 3344 break; 3345 } else { 3346 // FIXME: UNIMP! Store then reload 3347 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3348 } 3349 } else { 3350 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3351 Node->getOperand(0).getValueType())) { 3352 default: assert(0 && "Unknown operation action!"); 3353 case TargetLowering::Expand: 3354 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3355 break; 3356 case TargetLowering::Legal: 3357 Tmp1 = LegalizeOp(Node->getOperand(0)); 3358 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3359 break; 3360 } 3361 } 3362 break; 3363 3364 // Conversion operators. The source and destination have different types. 3365 case ISD::SINT_TO_FP: 3366 case ISD::UINT_TO_FP: { 3367 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3368 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3369 case Legal: 3370 switch (TLI.getOperationAction(Node->getOpcode(), 3371 Node->getOperand(0).getValueType())) { 3372 default: assert(0 && "Unknown operation action!"); 3373 case TargetLowering::Custom: 3374 isCustom = true; 3375 // FALLTHROUGH 3376 case TargetLowering::Legal: 3377 Tmp1 = LegalizeOp(Node->getOperand(0)); 3378 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3379 if (isCustom) { 3380 Tmp1 = TLI.LowerOperation(Result, DAG); 3381 if (Tmp1.Val) Result = Tmp1; 3382 } 3383 break; 3384 case TargetLowering::Expand: 3385 Result = ExpandLegalINT_TO_FP(isSigned, 3386 LegalizeOp(Node->getOperand(0)), 3387 Node->getValueType(0)); 3388 break; 3389 case TargetLowering::Promote: 3390 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3391 Node->getValueType(0), 3392 isSigned); 3393 break; 3394 } 3395 break; 3396 case Expand: 3397 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3398 Node->getValueType(0), Node->getOperand(0)); 3399 break; 3400 case Promote: 3401 Tmp1 = PromoteOp(Node->getOperand(0)); 3402 if (isSigned) { 3403 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3404 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3405 } else { 3406 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3407 Node->getOperand(0).getValueType()); 3408 } 3409 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3410 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3411 break; 3412 } 3413 break; 3414 } 3415 case ISD::TRUNCATE: 3416 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3417 case Legal: 3418 Tmp1 = LegalizeOp(Node->getOperand(0)); 3419 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3420 break; 3421 case Expand: 3422 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3423 3424 // Since the result is legal, we should just be able to truncate the low 3425 // part of the source. 3426 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3427 break; 3428 case Promote: 3429 Result = PromoteOp(Node->getOperand(0)); 3430 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3431 break; 3432 } 3433 break; 3434 3435 case ISD::FP_TO_SINT: 3436 case ISD::FP_TO_UINT: 3437 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3438 case Legal: 3439 Tmp1 = LegalizeOp(Node->getOperand(0)); 3440 3441 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3442 default: assert(0 && "Unknown operation action!"); 3443 case TargetLowering::Custom: 3444 isCustom = true; 3445 // FALLTHROUGH 3446 case TargetLowering::Legal: 3447 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3448 if (isCustom) { 3449 Tmp1 = TLI.LowerOperation(Result, DAG); 3450 if (Tmp1.Val) Result = Tmp1; 3451 } 3452 break; 3453 case TargetLowering::Promote: 3454 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3455 Node->getOpcode() == ISD::FP_TO_SINT); 3456 break; 3457 case TargetLowering::Expand: 3458 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3459 SDOperand True, False; 3460 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3461 MVT::ValueType NVT = Node->getValueType(0); 3462 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1; 3463 const uint64_t zero[] = {0, 0}; 3464 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero)); 3465 uint64_t x = 1ULL << ShiftAmt; 3466 (void)apf.convertFromZeroExtendedInteger 3467 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven); 3468 Tmp2 = DAG.getConstantFP(apf, VT); 3469 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 3470 Node->getOperand(0), Tmp2, ISD::SETLT); 3471 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3472 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3473 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3474 Tmp2)); 3475 False = DAG.getNode(ISD::XOR, NVT, False, 3476 DAG.getConstant(1ULL << ShiftAmt, NVT)); 3477 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3478 break; 3479 } else { 3480 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3481 } 3482 break; 3483 } 3484 break; 3485 case Expand: { 3486 MVT::ValueType VT = Op.getValueType(); 3487 MVT::ValueType OVT = Node->getOperand(0).getValueType(); 3488 // Convert ppcf128 to i32 3489 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3490 if (Node->getOpcode()==ISD::FP_TO_SINT) 3491 Result = DAG.getNode(ISD::FP_TO_SINT, VT, 3492 DAG.getNode(ISD::FP_ROUND, MVT::f64, 3493 (DAG.getNode(ISD::FP_ROUND_INREG, 3494 MVT::ppcf128, Node->getOperand(0), 3495 DAG.getValueType(MVT::f64))))); 3496 else { 3497 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3498 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3499 Tmp2 = DAG.getConstantFP(apf, OVT); 3500 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3501 // FIXME: generated code sucks. 3502 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3503 DAG.getNode(ISD::ADD, MVT::i32, 3504 DAG.getNode(ISD::FP_TO_SINT, VT, 3505 DAG.getNode(ISD::FSUB, OVT, 3506 Node->getOperand(0), Tmp2)), 3507 DAG.getConstant(0x80000000, MVT::i32)), 3508 DAG.getNode(ISD::FP_TO_SINT, VT, 3509 Node->getOperand(0)), 3510 DAG.getCondCode(ISD::SETGE)); 3511 } 3512 break; 3513 } 3514 // Convert f32 / f64 to i32 / i64. 3515 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3516 switch (Node->getOpcode()) { 3517 case ISD::FP_TO_SINT: { 3518 if (OVT == MVT::f32) 3519 LC = (VT == MVT::i32) 3520 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3521 else if (OVT == MVT::f64) 3522 LC = (VT == MVT::i32) 3523 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3524 else if (OVT == MVT::f80) { 3525 assert(VT == MVT::i64); 3526 LC = RTLIB::FPTOSINT_F80_I64; 3527 } 3528 else if (OVT == MVT::ppcf128) { 3529 assert(VT == MVT::i64); 3530 LC = RTLIB::FPTOSINT_PPCF128_I64; 3531 } 3532 break; 3533 } 3534 case ISD::FP_TO_UINT: { 3535 if (OVT == MVT::f32) 3536 LC = (VT == MVT::i32) 3537 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3538 else if (OVT == MVT::f64) 3539 LC = (VT == MVT::i32) 3540 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3541 else if (OVT == MVT::f80) { 3542 LC = (VT == MVT::i32) 3543 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64; 3544 } 3545 else if (OVT == MVT::ppcf128) { 3546 assert(VT == MVT::i64); 3547 LC = RTLIB::FPTOUINT_PPCF128_I64; 3548 } 3549 break; 3550 } 3551 default: assert(0 && "Unreachable!"); 3552 } 3553 SDOperand Dummy; 3554 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3555 false/*sign irrelevant*/, Dummy); 3556 break; 3557 } 3558 case Promote: 3559 Tmp1 = PromoteOp(Node->getOperand(0)); 3560 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3561 Result = LegalizeOp(Result); 3562 break; 3563 } 3564 break; 3565 3566 case ISD::FP_EXTEND: 3567 case ISD::FP_ROUND: { 3568 MVT::ValueType newVT = Op.getValueType(); 3569 MVT::ValueType oldVT = Op.getOperand(0).getValueType(); 3570 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) { 3571 if (Node->getOpcode() == ISD::FP_ROUND && oldVT == MVT::ppcf128) { 3572 SDOperand Lo, Hi; 3573 ExpandOp(Node->getOperand(0), Lo, Hi); 3574 if (newVT == MVT::f64) 3575 Result = Hi; 3576 else 3577 Result = DAG.getNode(ISD::FP_ROUND, newVT, Hi); 3578 break; 3579 } else { 3580 // The only other way we can lower this is to turn it into a STORE, 3581 // LOAD pair, targetting a temporary location (a stack slot). 3582 3583 // NOTE: there is a choice here between constantly creating new stack 3584 // slots and always reusing the same one. We currently always create 3585 // new ones, as reuse may inhibit scheduling. 3586 MVT::ValueType slotVT = 3587 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT; 3588 const Type *Ty = MVT::getTypeForValueType(slotVT); 3589 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 3590 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3591 MachineFunction &MF = DAG.getMachineFunction(); 3592 int SSFI = 3593 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3594 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3595 if (Node->getOpcode() == ISD::FP_EXTEND) { 3596 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), 3597 StackSlot, NULL, 0); 3598 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT, 3599 Result, StackSlot, NULL, 0, oldVT); 3600 } else { 3601 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3602 StackSlot, NULL, 0, newVT); 3603 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0); 3604 } 3605 break; 3606 } 3607 } 3608 } 3609 // FALL THROUGH 3610 case ISD::ANY_EXTEND: 3611 case ISD::ZERO_EXTEND: 3612 case ISD::SIGN_EXTEND: 3613 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3614 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3615 case Legal: 3616 Tmp1 = LegalizeOp(Node->getOperand(0)); 3617 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3618 break; 3619 case Promote: 3620 switch (Node->getOpcode()) { 3621 case ISD::ANY_EXTEND: 3622 Tmp1 = PromoteOp(Node->getOperand(0)); 3623 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3624 break; 3625 case ISD::ZERO_EXTEND: 3626 Result = PromoteOp(Node->getOperand(0)); 3627 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3628 Result = DAG.getZeroExtendInReg(Result, 3629 Node->getOperand(0).getValueType()); 3630 break; 3631 case ISD::SIGN_EXTEND: 3632 Result = PromoteOp(Node->getOperand(0)); 3633 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3634 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3635 Result, 3636 DAG.getValueType(Node->getOperand(0).getValueType())); 3637 break; 3638 case ISD::FP_EXTEND: 3639 Result = PromoteOp(Node->getOperand(0)); 3640 if (Result.getValueType() != Op.getValueType()) 3641 // Dynamically dead while we have only 2 FP types. 3642 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 3643 break; 3644 case ISD::FP_ROUND: 3645 Result = PromoteOp(Node->getOperand(0)); 3646 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 3647 break; 3648 } 3649 } 3650 break; 3651 case ISD::FP_ROUND_INREG: 3652 case ISD::SIGN_EXTEND_INREG: { 3653 Tmp1 = LegalizeOp(Node->getOperand(0)); 3654 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3655 3656 // If this operation is not supported, convert it to a shl/shr or load/store 3657 // pair. 3658 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3659 default: assert(0 && "This action not supported for this op yet!"); 3660 case TargetLowering::Legal: 3661 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3662 break; 3663 case TargetLowering::Expand: 3664 // If this is an integer extend and shifts are supported, do that. 3665 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3666 // NOTE: we could fall back on load/store here too for targets without 3667 // SAR. However, it is doubtful that any exist. 3668 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3669 MVT::getSizeInBits(ExtraVT); 3670 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3671 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3672 Node->getOperand(0), ShiftCst); 3673 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3674 Result, ShiftCst); 3675 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3676 // The only way we can lower this is to turn it into a TRUNCSTORE, 3677 // EXTLOAD pair, targetting a temporary location (a stack slot). 3678 3679 // NOTE: there is a choice here between constantly creating new stack 3680 // slots and always reusing the same one. We currently always create 3681 // new ones, as reuse may inhibit scheduling. 3682 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 3683 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 3684 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3685 MachineFunction &MF = DAG.getMachineFunction(); 3686 int SSFI = 3687 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3688 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3689 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3690 StackSlot, NULL, 0, ExtraVT); 3691 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 3692 Result, StackSlot, NULL, 0, ExtraVT); 3693 } else { 3694 assert(0 && "Unknown op"); 3695 } 3696 break; 3697 } 3698 break; 3699 } 3700 case ISD::TRAMPOLINE: { 3701 SDOperand Ops[6]; 3702 for (unsigned i = 0; i != 6; ++i) 3703 Ops[i] = LegalizeOp(Node->getOperand(i)); 3704 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3705 // The only option for this node is to custom lower it. 3706 Result = TLI.LowerOperation(Result, DAG); 3707 assert(Result.Val && "Should always custom lower!"); 3708 3709 // Since trampoline produces two values, make sure to remember that we 3710 // legalized both of them. 3711 Tmp1 = LegalizeOp(Result.getValue(1)); 3712 Result = LegalizeOp(Result); 3713 AddLegalizedOperand(SDOperand(Node, 0), Result); 3714 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3715 return Op.ResNo ? Tmp1 : Result; 3716 } 3717 case ISD::FLT_ROUNDS: { 3718 MVT::ValueType VT = Node->getValueType(0); 3719 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3720 default: assert(0 && "This action not supported for this op yet!"); 3721 case TargetLowering::Custom: 3722 Result = TLI.LowerOperation(Op, DAG); 3723 if (Result.Val) break; 3724 // Fall Thru 3725 case TargetLowering::Legal: 3726 // If this operation is not supported, lower it to constant 1 3727 Result = DAG.getConstant(1, VT); 3728 break; 3729 } 3730 } 3731 } 3732 3733 assert(Result.getValueType() == Op.getValueType() && 3734 "Bad legalization!"); 3735 3736 // Make sure that the generated code is itself legal. 3737 if (Result != Op) 3738 Result = LegalizeOp(Result); 3739 3740 // Note that LegalizeOp may be reentered even from single-use nodes, which 3741 // means that we always must cache transformed nodes. 3742 AddLegalizedOperand(Op, Result); 3743 return Result; 3744} 3745 3746/// PromoteOp - Given an operation that produces a value in an invalid type, 3747/// promote it to compute the value into a larger type. The produced value will 3748/// have the correct bits for the low portion of the register, but no guarantee 3749/// is made about the top bits: it may be zero, sign-extended, or garbage. 3750SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 3751 MVT::ValueType VT = Op.getValueType(); 3752 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3753 assert(getTypeAction(VT) == Promote && 3754 "Caller should expand or legalize operands that are not promotable!"); 3755 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 3756 "Cannot promote to smaller type!"); 3757 3758 SDOperand Tmp1, Tmp2, Tmp3; 3759 SDOperand Result; 3760 SDNode *Node = Op.Val; 3761 3762 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 3763 if (I != PromotedNodes.end()) return I->second; 3764 3765 switch (Node->getOpcode()) { 3766 case ISD::CopyFromReg: 3767 assert(0 && "CopyFromReg must be legal!"); 3768 default: 3769#ifndef NDEBUG 3770 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 3771#endif 3772 assert(0 && "Do not know how to promote this operator!"); 3773 abort(); 3774 case ISD::UNDEF: 3775 Result = DAG.getNode(ISD::UNDEF, NVT); 3776 break; 3777 case ISD::Constant: 3778 if (VT != MVT::i1) 3779 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 3780 else 3781 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 3782 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 3783 break; 3784 case ISD::ConstantFP: 3785 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 3786 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 3787 break; 3788 3789 case ISD::SETCC: 3790 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 3791 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 3792 Node->getOperand(1), Node->getOperand(2)); 3793 break; 3794 3795 case ISD::TRUNCATE: 3796 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3797 case Legal: 3798 Result = LegalizeOp(Node->getOperand(0)); 3799 assert(Result.getValueType() >= NVT && 3800 "This truncation doesn't make sense!"); 3801 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 3802 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 3803 break; 3804 case Promote: 3805 // The truncation is not required, because we don't guarantee anything 3806 // about high bits anyway. 3807 Result = PromoteOp(Node->getOperand(0)); 3808 break; 3809 case Expand: 3810 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3811 // Truncate the low part of the expanded value to the result type 3812 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 3813 } 3814 break; 3815 case ISD::SIGN_EXTEND: 3816 case ISD::ZERO_EXTEND: 3817 case ISD::ANY_EXTEND: 3818 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3819 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 3820 case Legal: 3821 // Input is legal? Just do extend all the way to the larger type. 3822 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3823 break; 3824 case Promote: 3825 // Promote the reg if it's smaller. 3826 Result = PromoteOp(Node->getOperand(0)); 3827 // The high bits are not guaranteed to be anything. Insert an extend. 3828 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3829 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3830 DAG.getValueType(Node->getOperand(0).getValueType())); 3831 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3832 Result = DAG.getZeroExtendInReg(Result, 3833 Node->getOperand(0).getValueType()); 3834 break; 3835 } 3836 break; 3837 case ISD::BIT_CONVERT: 3838 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3839 Result = PromoteOp(Result); 3840 break; 3841 3842 case ISD::FP_EXTEND: 3843 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3844 case ISD::FP_ROUND: 3845 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3846 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3847 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3848 case Legal: 3849 // Input is legal? Do an FP_ROUND_INREG. 3850 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 3851 DAG.getValueType(VT)); 3852 break; 3853 } 3854 break; 3855 3856 case ISD::SINT_TO_FP: 3857 case ISD::UINT_TO_FP: 3858 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3859 case Legal: 3860 // No extra round required here. 3861 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3862 break; 3863 3864 case Promote: 3865 Result = PromoteOp(Node->getOperand(0)); 3866 if (Node->getOpcode() == ISD::SINT_TO_FP) 3867 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3868 Result, 3869 DAG.getValueType(Node->getOperand(0).getValueType())); 3870 else 3871 Result = DAG.getZeroExtendInReg(Result, 3872 Node->getOperand(0).getValueType()); 3873 // No extra round required here. 3874 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3875 break; 3876 case Expand: 3877 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3878 Node->getOperand(0)); 3879 // Round if we cannot tolerate excess precision. 3880 if (NoExcessFPPrecision) 3881 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3882 DAG.getValueType(VT)); 3883 break; 3884 } 3885 break; 3886 3887 case ISD::SIGN_EXTEND_INREG: 3888 Result = PromoteOp(Node->getOperand(0)); 3889 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3890 Node->getOperand(1)); 3891 break; 3892 case ISD::FP_TO_SINT: 3893 case ISD::FP_TO_UINT: 3894 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3895 case Legal: 3896 case Expand: 3897 Tmp1 = Node->getOperand(0); 3898 break; 3899 case Promote: 3900 // The input result is prerounded, so we don't have to do anything 3901 // special. 3902 Tmp1 = PromoteOp(Node->getOperand(0)); 3903 break; 3904 } 3905 // If we're promoting a UINT to a larger size, check to see if the new node 3906 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3907 // we can use that instead. This allows us to generate better code for 3908 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3909 // legal, such as PowerPC. 3910 if (Node->getOpcode() == ISD::FP_TO_UINT && 3911 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3912 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3913 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3914 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3915 } else { 3916 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3917 } 3918 break; 3919 3920 case ISD::FABS: 3921 case ISD::FNEG: 3922 Tmp1 = PromoteOp(Node->getOperand(0)); 3923 assert(Tmp1.getValueType() == NVT); 3924 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3925 // NOTE: we do not have to do any extra rounding here for 3926 // NoExcessFPPrecision, because we know the input will have the appropriate 3927 // precision, and these operations don't modify precision at all. 3928 break; 3929 3930 case ISD::FSQRT: 3931 case ISD::FSIN: 3932 case ISD::FCOS: 3933 Tmp1 = PromoteOp(Node->getOperand(0)); 3934 assert(Tmp1.getValueType() == NVT); 3935 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3936 if (NoExcessFPPrecision) 3937 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3938 DAG.getValueType(VT)); 3939 break; 3940 3941 case ISD::FPOWI: { 3942 // Promote f32 powi to f64 powi. Note that this could insert a libcall 3943 // directly as well, which may be better. 3944 Tmp1 = PromoteOp(Node->getOperand(0)); 3945 assert(Tmp1.getValueType() == NVT); 3946 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 3947 if (NoExcessFPPrecision) 3948 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3949 DAG.getValueType(VT)); 3950 break; 3951 } 3952 3953 case ISD::AND: 3954 case ISD::OR: 3955 case ISD::XOR: 3956 case ISD::ADD: 3957 case ISD::SUB: 3958 case ISD::MUL: 3959 // The input may have strange things in the top bits of the registers, but 3960 // these operations don't care. They may have weird bits going out, but 3961 // that too is okay if they are integer operations. 3962 Tmp1 = PromoteOp(Node->getOperand(0)); 3963 Tmp2 = PromoteOp(Node->getOperand(1)); 3964 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3965 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3966 break; 3967 case ISD::FADD: 3968 case ISD::FSUB: 3969 case ISD::FMUL: 3970 Tmp1 = PromoteOp(Node->getOperand(0)); 3971 Tmp2 = PromoteOp(Node->getOperand(1)); 3972 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3973 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3974 3975 // Floating point operations will give excess precision that we may not be 3976 // able to tolerate. If we DO allow excess precision, just leave it, 3977 // otherwise excise it. 3978 // FIXME: Why would we need to round FP ops more than integer ones? 3979 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3980 if (NoExcessFPPrecision) 3981 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3982 DAG.getValueType(VT)); 3983 break; 3984 3985 case ISD::SDIV: 3986 case ISD::SREM: 3987 // These operators require that their input be sign extended. 3988 Tmp1 = PromoteOp(Node->getOperand(0)); 3989 Tmp2 = PromoteOp(Node->getOperand(1)); 3990 if (MVT::isInteger(NVT)) { 3991 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3992 DAG.getValueType(VT)); 3993 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3994 DAG.getValueType(VT)); 3995 } 3996 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3997 3998 // Perform FP_ROUND: this is probably overly pessimistic. 3999 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 4000 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4001 DAG.getValueType(VT)); 4002 break; 4003 case ISD::FDIV: 4004 case ISD::FREM: 4005 case ISD::FCOPYSIGN: 4006 // These operators require that their input be fp extended. 4007 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4008 case Legal: 4009 Tmp1 = LegalizeOp(Node->getOperand(0)); 4010 break; 4011 case Promote: 4012 Tmp1 = PromoteOp(Node->getOperand(0)); 4013 break; 4014 case Expand: 4015 assert(0 && "not implemented"); 4016 } 4017 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4018 case Legal: 4019 Tmp2 = LegalizeOp(Node->getOperand(1)); 4020 break; 4021 case Promote: 4022 Tmp2 = PromoteOp(Node->getOperand(1)); 4023 break; 4024 case Expand: 4025 assert(0 && "not implemented"); 4026 } 4027 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4028 4029 // Perform FP_ROUND: this is probably overly pessimistic. 4030 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4031 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4032 DAG.getValueType(VT)); 4033 break; 4034 4035 case ISD::UDIV: 4036 case ISD::UREM: 4037 // These operators require that their input be zero extended. 4038 Tmp1 = PromoteOp(Node->getOperand(0)); 4039 Tmp2 = PromoteOp(Node->getOperand(1)); 4040 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 4041 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4042 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4043 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4044 break; 4045 4046 case ISD::SHL: 4047 Tmp1 = PromoteOp(Node->getOperand(0)); 4048 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4049 break; 4050 case ISD::SRA: 4051 // The input value must be properly sign extended. 4052 Tmp1 = PromoteOp(Node->getOperand(0)); 4053 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4054 DAG.getValueType(VT)); 4055 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4056 break; 4057 case ISD::SRL: 4058 // The input value must be properly zero extended. 4059 Tmp1 = PromoteOp(Node->getOperand(0)); 4060 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4061 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4062 break; 4063 4064 case ISD::VAARG: 4065 Tmp1 = Node->getOperand(0); // Get the chain. 4066 Tmp2 = Node->getOperand(1); // Get the pointer. 4067 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4068 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4069 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 4070 } else { 4071 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 4072 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 4073 SV->getValue(), SV->getOffset()); 4074 // Increment the pointer, VAList, to the next vaarg 4075 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4076 DAG.getConstant(MVT::getSizeInBits(VT)/8, 4077 TLI.getPointerTy())); 4078 // Store the incremented VAList to the legalized pointer 4079 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 4080 SV->getOffset()); 4081 // Load the actual argument out of the pointer VAList 4082 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4083 } 4084 // Remember that we legalized the chain. 4085 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4086 break; 4087 4088 case ISD::LOAD: { 4089 LoadSDNode *LD = cast<LoadSDNode>(Node); 4090 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4091 ? ISD::EXTLOAD : LD->getExtensionType(); 4092 Result = DAG.getExtLoad(ExtType, NVT, 4093 LD->getChain(), LD->getBasePtr(), 4094 LD->getSrcValue(), LD->getSrcValueOffset(), 4095 LD->getLoadedVT(), 4096 LD->isVolatile(), 4097 LD->getAlignment()); 4098 // Remember that we legalized the chain. 4099 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4100 break; 4101 } 4102 case ISD::SELECT: 4103 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4104 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4105 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 4106 break; 4107 case ISD::SELECT_CC: 4108 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4109 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4110 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4111 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4112 break; 4113 case ISD::BSWAP: 4114 Tmp1 = Node->getOperand(0); 4115 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4116 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4117 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4118 DAG.getConstant(MVT::getSizeInBits(NVT) - 4119 MVT::getSizeInBits(VT), 4120 TLI.getShiftAmountTy())); 4121 break; 4122 case ISD::CTPOP: 4123 case ISD::CTTZ: 4124 case ISD::CTLZ: 4125 // Zero extend the argument 4126 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4127 // Perform the larger operation, then subtract if needed. 4128 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4129 switch(Node->getOpcode()) { 4130 case ISD::CTPOP: 4131 Result = Tmp1; 4132 break; 4133 case ISD::CTTZ: 4134 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4135 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 4136 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 4137 ISD::SETEQ); 4138 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4139 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 4140 break; 4141 case ISD::CTLZ: 4142 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4143 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4144 DAG.getConstant(MVT::getSizeInBits(NVT) - 4145 MVT::getSizeInBits(VT), NVT)); 4146 break; 4147 } 4148 break; 4149 case ISD::EXTRACT_SUBVECTOR: 4150 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4151 break; 4152 case ISD::EXTRACT_VECTOR_ELT: 4153 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4154 break; 4155 } 4156 4157 assert(Result.Val && "Didn't set a result!"); 4158 4159 // Make sure the result is itself legal. 4160 Result = LegalizeOp(Result); 4161 4162 // Remember that we promoted this! 4163 AddPromotedOperand(Op, Result); 4164 return Result; 4165} 4166 4167/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4168/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4169/// based on the vector type. The return type of this matches the element type 4170/// of the vector, which may not be legal for the target. 4171SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4172 // We know that operand #0 is the Vec vector. If the index is a constant 4173 // or if the invec is a supported hardware type, we can use it. Otherwise, 4174 // lower to a store then an indexed load. 4175 SDOperand Vec = Op.getOperand(0); 4176 SDOperand Idx = Op.getOperand(1); 4177 4178 MVT::ValueType TVT = Vec.getValueType(); 4179 unsigned NumElems = MVT::getVectorNumElements(TVT); 4180 4181 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4182 default: assert(0 && "This action is not supported yet!"); 4183 case TargetLowering::Custom: { 4184 Vec = LegalizeOp(Vec); 4185 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4186 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4187 if (Tmp3.Val) 4188 return Tmp3; 4189 break; 4190 } 4191 case TargetLowering::Legal: 4192 if (isTypeLegal(TVT)) { 4193 Vec = LegalizeOp(Vec); 4194 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4195 return Op; 4196 } 4197 break; 4198 case TargetLowering::Expand: 4199 break; 4200 } 4201 4202 if (NumElems == 1) { 4203 // This must be an access of the only element. Return it. 4204 Op = ScalarizeVectorOp(Vec); 4205 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4206 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4207 SDOperand Lo, Hi; 4208 SplitVectorOp(Vec, Lo, Hi); 4209 if (CIdx->getValue() < NumElems/2) { 4210 Vec = Lo; 4211 } else { 4212 Vec = Hi; 4213 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, 4214 Idx.getValueType()); 4215 } 4216 4217 // It's now an extract from the appropriate high or low part. Recurse. 4218 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4219 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4220 } else { 4221 // Store the value to a temporary stack slot, then LOAD the scalar 4222 // element back out. 4223 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4224 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4225 4226 // Add the offset to the index. 4227 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 4228 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4229 DAG.getConstant(EltSize, Idx.getValueType())); 4230 4231 if (MVT::getSizeInBits(Idx.getValueType()) > 4232 MVT::getSizeInBits(TLI.getPointerTy())) 4233 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4234 else 4235 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4236 4237 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4238 4239 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4240 } 4241 return Op; 4242} 4243 4244/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4245/// we assume the operation can be split if it is not already legal. 4246SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4247 // We know that operand #0 is the Vec vector. For now we assume the index 4248 // is a constant and that the extracted result is a supported hardware type. 4249 SDOperand Vec = Op.getOperand(0); 4250 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4251 4252 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); 4253 4254 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 4255 // This must be an access of the desired vector length. Return it. 4256 return Vec; 4257 } 4258 4259 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4260 SDOperand Lo, Hi; 4261 SplitVectorOp(Vec, Lo, Hi); 4262 if (CIdx->getValue() < NumElems/2) { 4263 Vec = Lo; 4264 } else { 4265 Vec = Hi; 4266 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4267 } 4268 4269 // It's now an extract from the appropriate high or low part. Recurse. 4270 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4271 return ExpandEXTRACT_SUBVECTOR(Op); 4272} 4273 4274/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4275/// with condition CC on the current target. This usually involves legalizing 4276/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4277/// there may be no choice but to create a new SetCC node to represent the 4278/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4279/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4280void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4281 SDOperand &RHS, 4282 SDOperand &CC) { 4283 SDOperand Tmp1, Tmp2, Tmp3, Result; 4284 4285 switch (getTypeAction(LHS.getValueType())) { 4286 case Legal: 4287 Tmp1 = LegalizeOp(LHS); // LHS 4288 Tmp2 = LegalizeOp(RHS); // RHS 4289 break; 4290 case Promote: 4291 Tmp1 = PromoteOp(LHS); // LHS 4292 Tmp2 = PromoteOp(RHS); // RHS 4293 4294 // If this is an FP compare, the operands have already been extended. 4295 if (MVT::isInteger(LHS.getValueType())) { 4296 MVT::ValueType VT = LHS.getValueType(); 4297 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4298 4299 // Otherwise, we have to insert explicit sign or zero extends. Note 4300 // that we could insert sign extends for ALL conditions, but zero extend 4301 // is cheaper on many machines (an AND instead of two shifts), so prefer 4302 // it. 4303 switch (cast<CondCodeSDNode>(CC)->get()) { 4304 default: assert(0 && "Unknown integer comparison!"); 4305 case ISD::SETEQ: 4306 case ISD::SETNE: 4307 case ISD::SETUGE: 4308 case ISD::SETUGT: 4309 case ISD::SETULE: 4310 case ISD::SETULT: 4311 // ALL of these operations will work if we either sign or zero extend 4312 // the operands (including the unsigned comparisons!). Zero extend is 4313 // usually a simpler/cheaper operation, so prefer it. 4314 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4315 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4316 break; 4317 case ISD::SETGE: 4318 case ISD::SETGT: 4319 case ISD::SETLT: 4320 case ISD::SETLE: 4321 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4322 DAG.getValueType(VT)); 4323 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4324 DAG.getValueType(VT)); 4325 break; 4326 } 4327 } 4328 break; 4329 case Expand: { 4330 MVT::ValueType VT = LHS.getValueType(); 4331 if (VT == MVT::f32 || VT == MVT::f64) { 4332 // Expand into one or more soft-fp libcall(s). 4333 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4334 switch (cast<CondCodeSDNode>(CC)->get()) { 4335 case ISD::SETEQ: 4336 case ISD::SETOEQ: 4337 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4338 break; 4339 case ISD::SETNE: 4340 case ISD::SETUNE: 4341 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4342 break; 4343 case ISD::SETGE: 4344 case ISD::SETOGE: 4345 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4346 break; 4347 case ISD::SETLT: 4348 case ISD::SETOLT: 4349 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4350 break; 4351 case ISD::SETLE: 4352 case ISD::SETOLE: 4353 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4354 break; 4355 case ISD::SETGT: 4356 case ISD::SETOGT: 4357 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4358 break; 4359 case ISD::SETUO: 4360 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4361 break; 4362 case ISD::SETO: 4363 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4364 break; 4365 default: 4366 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4367 switch (cast<CondCodeSDNode>(CC)->get()) { 4368 case ISD::SETONE: 4369 // SETONE = SETOLT | SETOGT 4370 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4371 // Fallthrough 4372 case ISD::SETUGT: 4373 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4374 break; 4375 case ISD::SETUGE: 4376 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4377 break; 4378 case ISD::SETULT: 4379 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4380 break; 4381 case ISD::SETULE: 4382 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4383 break; 4384 case ISD::SETUEQ: 4385 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4386 break; 4387 default: assert(0 && "Unsupported FP setcc!"); 4388 } 4389 } 4390 4391 SDOperand Dummy; 4392 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 4393 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4394 false /*sign irrelevant*/, Dummy); 4395 Tmp2 = DAG.getConstant(0, MVT::i32); 4396 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4397 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4398 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 4399 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 4400 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4401 false /*sign irrelevant*/, Dummy); 4402 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 4403 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4404 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4405 Tmp2 = SDOperand(); 4406 } 4407 LHS = Tmp1; 4408 RHS = Tmp2; 4409 return; 4410 } 4411 4412 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4413 ExpandOp(LHS, LHSLo, LHSHi); 4414 ExpandOp(RHS, RHSLo, RHSHi); 4415 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4416 4417 if (VT==MVT::ppcf128) { 4418 // FIXME: This generated code sucks. We want to generate 4419 // FCMP crN, hi1, hi2 4420 // BNE crN, L: 4421 // FCMP crN, lo1, lo2 4422 // The following can be improved, but not that much. 4423 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4424 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode); 4425 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4426 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE); 4427 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode); 4428 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4429 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4430 Tmp2 = SDOperand(); 4431 break; 4432 } 4433 4434 switch (CCCode) { 4435 case ISD::SETEQ: 4436 case ISD::SETNE: 4437 if (RHSLo == RHSHi) 4438 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4439 if (RHSCST->isAllOnesValue()) { 4440 // Comparison to -1. 4441 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4442 Tmp2 = RHSLo; 4443 break; 4444 } 4445 4446 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4447 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4448 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4449 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4450 break; 4451 default: 4452 // If this is a comparison of the sign bit, just look at the top part. 4453 // X > -1, x < 0 4454 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4455 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4456 CST->getValue() == 0) || // X < 0 4457 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4458 CST->isAllOnesValue())) { // X > -1 4459 Tmp1 = LHSHi; 4460 Tmp2 = RHSHi; 4461 break; 4462 } 4463 4464 // FIXME: This generated code sucks. 4465 ISD::CondCode LowCC; 4466 switch (CCCode) { 4467 default: assert(0 && "Unknown integer setcc!"); 4468 case ISD::SETLT: 4469 case ISD::SETULT: LowCC = ISD::SETULT; break; 4470 case ISD::SETGT: 4471 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4472 case ISD::SETLE: 4473 case ISD::SETULE: LowCC = ISD::SETULE; break; 4474 case ISD::SETGE: 4475 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4476 } 4477 4478 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4479 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4480 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4481 4482 // NOTE: on targets without efficient SELECT of bools, we can always use 4483 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4484 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4485 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, 4486 false, DagCombineInfo); 4487 if (!Tmp1.Val) 4488 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 4489 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4490 CCCode, false, DagCombineInfo); 4491 if (!Tmp2.Val) 4492 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC); 4493 4494 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4495 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4496 if ((Tmp1C && Tmp1C->getValue() == 0) || 4497 (Tmp2C && Tmp2C->getValue() == 0 && 4498 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4499 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4500 (Tmp2C && Tmp2C->getValue() == 1 && 4501 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4502 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4503 // low part is known false, returns high part. 4504 // For LE / GE, if high part is known false, ignore the low part. 4505 // For LT / GT, if high part is known true, ignore the low part. 4506 Tmp1 = Tmp2; 4507 Tmp2 = SDOperand(); 4508 } else { 4509 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4510 ISD::SETEQ, false, DagCombineInfo); 4511 if (!Result.Val) 4512 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4513 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4514 Result, Tmp1, Tmp2)); 4515 Tmp1 = Result; 4516 Tmp2 = SDOperand(); 4517 } 4518 } 4519 } 4520 } 4521 LHS = Tmp1; 4522 RHS = Tmp2; 4523} 4524 4525/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 4526/// The resultant code need not be legal. Note that SrcOp is the input operand 4527/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 4528SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 4529 SDOperand SrcOp) { 4530 // Create the stack frame object. 4531 SDOperand FIPtr = DAG.CreateStackTemporary(DestVT); 4532 4533 // Emit a store to the stack slot. 4534 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); 4535 // Result is a load from the stack slot. 4536 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4537} 4538 4539SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4540 // Create a vector sized/aligned stack slot, store the value to element #0, 4541 // then load the whole vector back out. 4542 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4543 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4544 NULL, 0); 4545 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 4546} 4547 4548 4549/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4550/// support the operation, but do support the resultant vector type. 4551SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4552 4553 // If the only non-undef value is the low element, turn this into a 4554 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4555 unsigned NumElems = Node->getNumOperands(); 4556 bool isOnlyLowElement = true; 4557 SDOperand SplatValue = Node->getOperand(0); 4558 std::map<SDOperand, std::vector<unsigned> > Values; 4559 Values[SplatValue].push_back(0); 4560 bool isConstant = true; 4561 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4562 SplatValue.getOpcode() != ISD::UNDEF) 4563 isConstant = false; 4564 4565 for (unsigned i = 1; i < NumElems; ++i) { 4566 SDOperand V = Node->getOperand(i); 4567 Values[V].push_back(i); 4568 if (V.getOpcode() != ISD::UNDEF) 4569 isOnlyLowElement = false; 4570 if (SplatValue != V) 4571 SplatValue = SDOperand(0,0); 4572 4573 // If this isn't a constant element or an undef, we can't use a constant 4574 // pool load. 4575 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4576 V.getOpcode() != ISD::UNDEF) 4577 isConstant = false; 4578 } 4579 4580 if (isOnlyLowElement) { 4581 // If the low element is an undef too, then this whole things is an undef. 4582 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4583 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4584 // Otherwise, turn this into a scalar_to_vector node. 4585 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4586 Node->getOperand(0)); 4587 } 4588 4589 // If all elements are constants, create a load from the constant pool. 4590 if (isConstant) { 4591 MVT::ValueType VT = Node->getValueType(0); 4592 const Type *OpNTy = 4593 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 4594 std::vector<Constant*> CV; 4595 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4596 if (ConstantFPSDNode *V = 4597 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4598 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF())); 4599 } else if (ConstantSDNode *V = 4600 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4601 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 4602 } else { 4603 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4604 CV.push_back(UndefValue::get(OpNTy)); 4605 } 4606 } 4607 Constant *CP = ConstantVector::get(CV); 4608 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4609 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 4610 } 4611 4612 if (SplatValue.Val) { // Splat of one value? 4613 // Build the shuffle constant vector: <0, 0, 0, 0> 4614 MVT::ValueType MaskVT = 4615 MVT::getIntVectorWithNumElements(NumElems); 4616 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 4617 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4618 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4619 &ZeroVec[0], ZeroVec.size()); 4620 4621 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4622 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4623 // Get the splatted value into the low element of a vector register. 4624 SDOperand LowValVec = 4625 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4626 4627 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4628 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4629 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4630 SplatMask); 4631 } 4632 } 4633 4634 // If there are only two unique elements, we may be able to turn this into a 4635 // vector shuffle. 4636 if (Values.size() == 2) { 4637 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 4638 MVT::ValueType MaskVT = 4639 MVT::getIntVectorWithNumElements(NumElems); 4640 std::vector<SDOperand> MaskVec(NumElems); 4641 unsigned i = 0; 4642 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4643 E = Values.end(); I != E; ++I) { 4644 for (std::vector<unsigned>::iterator II = I->second.begin(), 4645 EE = I->second.end(); II != EE; ++II) 4646 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT)); 4647 i += NumElems; 4648 } 4649 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4650 &MaskVec[0], MaskVec.size()); 4651 4652 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4653 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 4654 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 4655 SmallVector<SDOperand, 8> Ops; 4656 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4657 E = Values.end(); I != E; ++I) { 4658 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4659 I->first); 4660 Ops.push_back(Op); 4661 } 4662 Ops.push_back(ShuffleMask); 4663 4664 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 4665 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 4666 &Ops[0], Ops.size()); 4667 } 4668 } 4669 4670 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 4671 // aligned object on the stack, store each element into it, then load 4672 // the result as a vector. 4673 MVT::ValueType VT = Node->getValueType(0); 4674 // Create the stack frame object. 4675 SDOperand FIPtr = DAG.CreateStackTemporary(VT); 4676 4677 // Emit a store of each element to the stack slot. 4678 SmallVector<SDOperand, 8> Stores; 4679 unsigned TypeByteSize = 4680 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 4681 // Store (in the right endianness) the elements to memory. 4682 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4683 // Ignore undef elements. 4684 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4685 4686 unsigned Offset = TypeByteSize*i; 4687 4688 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 4689 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 4690 4691 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 4692 NULL, 0)); 4693 } 4694 4695 SDOperand StoreChain; 4696 if (!Stores.empty()) // Not all undef elements? 4697 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4698 &Stores[0], Stores.size()); 4699 else 4700 StoreChain = DAG.getEntryNode(); 4701 4702 // Result is a load from the stack slot. 4703 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 4704} 4705 4706void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 4707 SDOperand Op, SDOperand Amt, 4708 SDOperand &Lo, SDOperand &Hi) { 4709 // Expand the subcomponents. 4710 SDOperand LHSL, LHSH; 4711 ExpandOp(Op, LHSL, LHSH); 4712 4713 SDOperand Ops[] = { LHSL, LHSH, Amt }; 4714 MVT::ValueType VT = LHSL.getValueType(); 4715 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 4716 Hi = Lo.getValue(1); 4717} 4718 4719 4720/// ExpandShift - Try to find a clever way to expand this shift operation out to 4721/// smaller elements. If we can't find a way that is more efficient than a 4722/// libcall on this target, return false. Otherwise, return true with the 4723/// low-parts expanded into Lo and Hi. 4724bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 4725 SDOperand &Lo, SDOperand &Hi) { 4726 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 4727 "This is not a shift!"); 4728 4729 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 4730 SDOperand ShAmt = LegalizeOp(Amt); 4731 MVT::ValueType ShTy = ShAmt.getValueType(); 4732 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 4733 unsigned NVTBits = MVT::getSizeInBits(NVT); 4734 4735 // Handle the case when Amt is an immediate. 4736 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 4737 unsigned Cst = CN->getValue(); 4738 // Expand the incoming operand to be shifted, so that we have its parts 4739 SDOperand InL, InH; 4740 ExpandOp(Op, InL, InH); 4741 switch(Opc) { 4742 case ISD::SHL: 4743 if (Cst > VTBits) { 4744 Lo = DAG.getConstant(0, NVT); 4745 Hi = DAG.getConstant(0, NVT); 4746 } else if (Cst > NVTBits) { 4747 Lo = DAG.getConstant(0, NVT); 4748 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 4749 } else if (Cst == NVTBits) { 4750 Lo = DAG.getConstant(0, NVT); 4751 Hi = InL; 4752 } else { 4753 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 4754 Hi = DAG.getNode(ISD::OR, NVT, 4755 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 4756 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 4757 } 4758 return true; 4759 case ISD::SRL: 4760 if (Cst > VTBits) { 4761 Lo = DAG.getConstant(0, NVT); 4762 Hi = DAG.getConstant(0, NVT); 4763 } else if (Cst > NVTBits) { 4764 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 4765 Hi = DAG.getConstant(0, NVT); 4766 } else if (Cst == NVTBits) { 4767 Lo = InH; 4768 Hi = DAG.getConstant(0, NVT); 4769 } else { 4770 Lo = DAG.getNode(ISD::OR, NVT, 4771 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4772 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4773 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 4774 } 4775 return true; 4776 case ISD::SRA: 4777 if (Cst > VTBits) { 4778 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 4779 DAG.getConstant(NVTBits-1, ShTy)); 4780 } else if (Cst > NVTBits) { 4781 Lo = DAG.getNode(ISD::SRA, NVT, InH, 4782 DAG.getConstant(Cst-NVTBits, ShTy)); 4783 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4784 DAG.getConstant(NVTBits-1, ShTy)); 4785 } else if (Cst == NVTBits) { 4786 Lo = InH; 4787 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4788 DAG.getConstant(NVTBits-1, ShTy)); 4789 } else { 4790 Lo = DAG.getNode(ISD::OR, NVT, 4791 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4792 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4793 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 4794 } 4795 return true; 4796 } 4797 } 4798 4799 // Okay, the shift amount isn't constant. However, if we can tell that it is 4800 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 4801 uint64_t Mask = NVTBits, KnownZero, KnownOne; 4802 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 4803 4804 // If we know that the high bit of the shift amount is one, then we can do 4805 // this as a couple of simple shifts. 4806 if (KnownOne & Mask) { 4807 // Mask out the high bit, which we know is set. 4808 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 4809 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4810 4811 // Expand the incoming operand to be shifted, so that we have its parts 4812 SDOperand InL, InH; 4813 ExpandOp(Op, InL, InH); 4814 switch(Opc) { 4815 case ISD::SHL: 4816 Lo = DAG.getConstant(0, NVT); // Low part is zero. 4817 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 4818 return true; 4819 case ISD::SRL: 4820 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 4821 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 4822 return true; 4823 case ISD::SRA: 4824 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 4825 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4826 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 4827 return true; 4828 } 4829 } 4830 4831 // If we know that the high bit of the shift amount is zero, then we can do 4832 // this as a couple of simple shifts. 4833 if (KnownZero & Mask) { 4834 // Compute 32-amt. 4835 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 4836 DAG.getConstant(NVTBits, Amt.getValueType()), 4837 Amt); 4838 4839 // Expand the incoming operand to be shifted, so that we have its parts 4840 SDOperand InL, InH; 4841 ExpandOp(Op, InL, InH); 4842 switch(Opc) { 4843 case ISD::SHL: 4844 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 4845 Hi = DAG.getNode(ISD::OR, NVT, 4846 DAG.getNode(ISD::SHL, NVT, InH, Amt), 4847 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 4848 return true; 4849 case ISD::SRL: 4850 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 4851 Lo = DAG.getNode(ISD::OR, NVT, 4852 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4853 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4854 return true; 4855 case ISD::SRA: 4856 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 4857 Lo = DAG.getNode(ISD::OR, NVT, 4858 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4859 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4860 return true; 4861 } 4862 } 4863 4864 return false; 4865} 4866 4867 4868// ExpandLibCall - Expand a node into a call to a libcall. If the result value 4869// does not fit into a register, return the lo part and set the hi part to the 4870// by-reg argument. If it does fit into a single register, return the result 4871// and leave the Hi part unset. 4872SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 4873 bool isSigned, SDOperand &Hi) { 4874 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 4875 // The input chain to this libcall is the entry node of the function. 4876 // Legalizing the call will automatically add the previous call to the 4877 // dependence. 4878 SDOperand InChain = DAG.getEntryNode(); 4879 4880 TargetLowering::ArgListTy Args; 4881 TargetLowering::ArgListEntry Entry; 4882 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4883 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 4884 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 4885 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 4886 Entry.isSExt = isSigned; 4887 Args.push_back(Entry); 4888 } 4889 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 4890 4891 // Splice the libcall in wherever FindInputOutputChains tells us to. 4892 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 4893 std::pair<SDOperand,SDOperand> CallInfo = 4894 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false, 4895 Callee, Args, DAG); 4896 4897 // Legalize the call sequence, starting with the chain. This will advance 4898 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 4899 // was added by LowerCallTo (guaranteeing proper serialization of calls). 4900 LegalizeOp(CallInfo.second); 4901 SDOperand Result; 4902 switch (getTypeAction(CallInfo.first.getValueType())) { 4903 default: assert(0 && "Unknown thing"); 4904 case Legal: 4905 Result = CallInfo.first; 4906 break; 4907 case Expand: 4908 ExpandOp(CallInfo.first, Result, Hi); 4909 break; 4910 } 4911 return Result; 4912} 4913 4914 4915/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 4916/// 4917SDOperand SelectionDAGLegalize:: 4918ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 4919 assert(getTypeAction(Source.getValueType()) == Expand && 4920 "This is not an expansion!"); 4921 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 4922 4923 if (!isSigned) { 4924 assert(Source.getValueType() == MVT::i64 && 4925 "This only works for 64-bit -> FP"); 4926 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 4927 // incoming integer is set. To handle this, we dynamically test to see if 4928 // it is set, and, if so, add a fudge factor. 4929 SDOperand Lo, Hi; 4930 ExpandOp(Source, Lo, Hi); 4931 4932 // If this is unsigned, and not supported, first perform the conversion to 4933 // signed, then adjust the result if the sign bit is set. 4934 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 4935 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 4936 4937 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 4938 DAG.getConstant(0, Hi.getValueType()), 4939 ISD::SETLT); 4940 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4941 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4942 SignSet, Four, Zero); 4943 uint64_t FF = 0x5f800000ULL; 4944 if (TLI.isLittleEndian()) FF <<= 32; 4945 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4946 4947 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4948 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4949 SDOperand FudgeInReg; 4950 if (DestTy == MVT::f32) 4951 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4952 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) 4953 // FIXME: Avoid the extend by construction the right constantpool? 4954 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 4955 CPIdx, NULL, 0, MVT::f32); 4956 else 4957 assert(0 && "Unexpected conversion"); 4958 4959 MVT::ValueType SCVT = SignedConv.getValueType(); 4960 if (SCVT != DestTy) { 4961 // Destination type needs to be expanded as well. The FADD now we are 4962 // constructing will be expanded into a libcall. 4963 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 4964 assert(SCVT == MVT::i32 && DestTy == MVT::f64); 4965 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, 4966 SignedConv, SignedConv.getValue(1)); 4967 } 4968 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 4969 } 4970 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 4971 } 4972 4973 // Check to see if the target has a custom way to lower this. If so, use it. 4974 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 4975 default: assert(0 && "This action not implemented for this operation!"); 4976 case TargetLowering::Legal: 4977 case TargetLowering::Expand: 4978 break; // This case is handled below. 4979 case TargetLowering::Custom: { 4980 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 4981 Source), DAG); 4982 if (NV.Val) 4983 return LegalizeOp(NV); 4984 break; // The target decided this was legal after all 4985 } 4986 } 4987 4988 // Expand the source, then glue it back together for the call. We must expand 4989 // the source in case it is shared (this pass of legalize must traverse it). 4990 SDOperand SrcLo, SrcHi; 4991 ExpandOp(Source, SrcLo, SrcHi); 4992 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 4993 4994 RTLIB::Libcall LC; 4995 if (DestTy == MVT::f32) 4996 LC = RTLIB::SINTTOFP_I64_F32; 4997 else { 4998 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 4999 LC = RTLIB::SINTTOFP_I64_F64; 5000 } 5001 5002 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 5003 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5004 SDOperand UnusedHiPart; 5005 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 5006 UnusedHiPart); 5007} 5008 5009/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5010/// INT_TO_FP operation of the specified operand when the target requests that 5011/// we expand it. At this point, we know that the result and operand types are 5012/// legal for the target. 5013SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5014 SDOperand Op0, 5015 MVT::ValueType DestVT) { 5016 if (Op0.getValueType() == MVT::i32) { 5017 // simple 32-bit [signed|unsigned] integer to float/double expansion 5018 5019 // get the stack frame index of a 8 byte buffer, pessimistically aligned 5020 MachineFunction &MF = DAG.getMachineFunction(); 5021 const Type *F64Type = MVT::getTypeForValueType(MVT::f64); 5022 unsigned StackAlign = 5023 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type); 5024 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign); 5025 // get address of 8 byte buffer 5026 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5027 // word offset constant for Hi/Lo address computation 5028 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5029 // set up Hi and Lo (into buffer) address based on endian 5030 SDOperand Hi = StackSlot; 5031 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5032 if (TLI.isLittleEndian()) 5033 std::swap(Hi, Lo); 5034 5035 // if signed map to unsigned space 5036 SDOperand Op0Mapped; 5037 if (isSigned) { 5038 // constant used to invert sign bit (signed to unsigned mapping) 5039 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5040 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5041 } else { 5042 Op0Mapped = Op0; 5043 } 5044 // store the lo of the constructed double - based on integer input 5045 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 5046 Op0Mapped, Lo, NULL, 0); 5047 // initial hi portion of constructed double 5048 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5049 // store the hi of the constructed double - biased exponent 5050 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5051 // load the constructed double 5052 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5053 // FP constant to bias correct the final result 5054 SDOperand Bias = DAG.getConstantFP(isSigned ? 5055 BitsToDouble(0x4330000080000000ULL) 5056 : BitsToDouble(0x4330000000000000ULL), 5057 MVT::f64); 5058 // subtract the bias 5059 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5060 // final result 5061 SDOperand Result; 5062 // handle final rounding 5063 if (DestVT == MVT::f64) { 5064 // do nothing 5065 Result = Sub; 5066 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { 5067 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub); 5068 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { 5069 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5070 } 5071 return Result; 5072 } 5073 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5074 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5075 5076 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 5077 DAG.getConstant(0, Op0.getValueType()), 5078 ISD::SETLT); 5079 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 5080 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5081 SignSet, Four, Zero); 5082 5083 // If the sign bit of the integer is set, the large number will be treated 5084 // as a negative number. To counteract this, the dynamic code adds an 5085 // offset depending on the data type. 5086 uint64_t FF; 5087 switch (Op0.getValueType()) { 5088 default: assert(0 && "Unsupported integer type!"); 5089 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5090 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5091 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5092 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5093 } 5094 if (TLI.isLittleEndian()) FF <<= 32; 5095 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5096 5097 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5098 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5099 SDOperand FudgeInReg; 5100 if (DestVT == MVT::f32) 5101 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 5102 else { 5103 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5104 DAG.getEntryNode(), CPIdx, 5105 NULL, 0, MVT::f32)); 5106 } 5107 5108 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5109} 5110 5111/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5112/// *INT_TO_FP operation of the specified operand when the target requests that 5113/// we promote it. At this point, we know that the result and operand types are 5114/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5115/// operation that takes a larger input. 5116SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5117 MVT::ValueType DestVT, 5118 bool isSigned) { 5119 // First step, figure out the appropriate *INT_TO_FP operation to use. 5120 MVT::ValueType NewInTy = LegalOp.getValueType(); 5121 5122 unsigned OpToUse = 0; 5123 5124 // Scan for the appropriate larger type to use. 5125 while (1) { 5126 NewInTy = (MVT::ValueType)(NewInTy+1); 5127 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 5128 5129 // If the target supports SINT_TO_FP of this type, use it. 5130 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5131 default: break; 5132 case TargetLowering::Legal: 5133 if (!TLI.isTypeLegal(NewInTy)) 5134 break; // Can't use this datatype. 5135 // FALL THROUGH. 5136 case TargetLowering::Custom: 5137 OpToUse = ISD::SINT_TO_FP; 5138 break; 5139 } 5140 if (OpToUse) break; 5141 if (isSigned) continue; 5142 5143 // If the target supports UINT_TO_FP of this type, use it. 5144 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5145 default: break; 5146 case TargetLowering::Legal: 5147 if (!TLI.isTypeLegal(NewInTy)) 5148 break; // Can't use this datatype. 5149 // FALL THROUGH. 5150 case TargetLowering::Custom: 5151 OpToUse = ISD::UINT_TO_FP; 5152 break; 5153 } 5154 if (OpToUse) break; 5155 5156 // Otherwise, try a larger type. 5157 } 5158 5159 // Okay, we found the operation and type to use. Zero extend our input to the 5160 // desired type then run the operation on it. 5161 return DAG.getNode(OpToUse, DestVT, 5162 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5163 NewInTy, LegalOp)); 5164} 5165 5166/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5167/// FP_TO_*INT operation of the specified operand when the target requests that 5168/// we promote it. At this point, we know that the result and operand types are 5169/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5170/// operation that returns a larger result. 5171SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5172 MVT::ValueType DestVT, 5173 bool isSigned) { 5174 // First step, figure out the appropriate FP_TO*INT operation to use. 5175 MVT::ValueType NewOutTy = DestVT; 5176 5177 unsigned OpToUse = 0; 5178 5179 // Scan for the appropriate larger type to use. 5180 while (1) { 5181 NewOutTy = (MVT::ValueType)(NewOutTy+1); 5182 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 5183 5184 // If the target supports FP_TO_SINT returning this type, use it. 5185 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5186 default: break; 5187 case TargetLowering::Legal: 5188 if (!TLI.isTypeLegal(NewOutTy)) 5189 break; // Can't use this datatype. 5190 // FALL THROUGH. 5191 case TargetLowering::Custom: 5192 OpToUse = ISD::FP_TO_SINT; 5193 break; 5194 } 5195 if (OpToUse) break; 5196 5197 // If the target supports FP_TO_UINT of this type, use it. 5198 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5199 default: break; 5200 case TargetLowering::Legal: 5201 if (!TLI.isTypeLegal(NewOutTy)) 5202 break; // Can't use this datatype. 5203 // FALL THROUGH. 5204 case TargetLowering::Custom: 5205 OpToUse = ISD::FP_TO_UINT; 5206 break; 5207 } 5208 if (OpToUse) break; 5209 5210 // Otherwise, try a larger type. 5211 } 5212 5213 5214 // Okay, we found the operation and type to use. 5215 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5216 5217 // If the operation produces an invalid type, it must be custom lowered. Use 5218 // the target lowering hooks to expand it. Just keep the low part of the 5219 // expanded operation, we know that we're truncating anyway. 5220 if (getTypeAction(NewOutTy) == Expand) { 5221 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0); 5222 assert(Operation.Val && "Didn't return anything"); 5223 } 5224 5225 // Truncate the result of the extended FP_TO_*INT operation to the desired 5226 // size. 5227 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5228} 5229 5230/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5231/// 5232SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5233 MVT::ValueType VT = Op.getValueType(); 5234 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 5235 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5236 switch (VT) { 5237 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5238 case MVT::i16: 5239 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5240 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5241 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5242 case MVT::i32: 5243 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5244 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5245 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5246 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5247 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5248 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5249 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5250 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5251 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5252 case MVT::i64: 5253 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5254 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5255 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5256 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5257 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5258 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5259 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5260 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5261 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5262 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5263 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5264 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5265 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5266 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5267 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5268 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5269 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5270 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5271 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5272 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5273 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5274 } 5275} 5276 5277/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5278/// 5279SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5280 switch (Opc) { 5281 default: assert(0 && "Cannot expand this yet!"); 5282 case ISD::CTPOP: { 5283 static const uint64_t mask[6] = { 5284 0x5555555555555555ULL, 0x3333333333333333ULL, 5285 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5286 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5287 }; 5288 MVT::ValueType VT = Op.getValueType(); 5289 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5290 unsigned len = MVT::getSizeInBits(VT); 5291 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5292 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5293 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5294 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5295 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5296 DAG.getNode(ISD::AND, VT, 5297 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5298 } 5299 return Op; 5300 } 5301 case ISD::CTLZ: { 5302 // for now, we do this: 5303 // x = x | (x >> 1); 5304 // x = x | (x >> 2); 5305 // ... 5306 // x = x | (x >>16); 5307 // x = x | (x >>32); // for 64-bit input 5308 // return popcount(~x); 5309 // 5310 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5311 MVT::ValueType VT = Op.getValueType(); 5312 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5313 unsigned len = MVT::getSizeInBits(VT); 5314 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5315 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5316 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5317 } 5318 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5319 return DAG.getNode(ISD::CTPOP, VT, Op); 5320 } 5321 case ISD::CTTZ: { 5322 // for now, we use: { return popcount(~x & (x - 1)); } 5323 // unless the target has ctlz but not ctpop, in which case we use: 5324 // { return 32 - nlz(~x & (x-1)); } 5325 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5326 MVT::ValueType VT = Op.getValueType(); 5327 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5328 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5329 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5330 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5331 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5332 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5333 TLI.isOperationLegal(ISD::CTLZ, VT)) 5334 return DAG.getNode(ISD::SUB, VT, 5335 DAG.getConstant(MVT::getSizeInBits(VT), VT), 5336 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5337 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5338 } 5339 } 5340} 5341 5342/// ExpandOp - Expand the specified SDOperand into its two component pieces 5343/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5344/// LegalizeNodes map is filled in for any results that are not expanded, the 5345/// ExpandedNodes map is filled in for any results that are expanded, and the 5346/// Lo/Hi values are returned. 5347void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5348 MVT::ValueType VT = Op.getValueType(); 5349 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 5350 SDNode *Node = Op.Val; 5351 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5352 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 5353 MVT::isVector(VT)) && 5354 "Cannot expand to FP value or to larger int value!"); 5355 5356 // See if we already expanded it. 5357 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5358 = ExpandedNodes.find(Op); 5359 if (I != ExpandedNodes.end()) { 5360 Lo = I->second.first; 5361 Hi = I->second.second; 5362 return; 5363 } 5364 5365 switch (Node->getOpcode()) { 5366 case ISD::CopyFromReg: 5367 assert(0 && "CopyFromReg must be legal!"); 5368 case ISD::FP_ROUND_INREG: 5369 if (VT == MVT::ppcf128 && 5370 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5371 TargetLowering::Custom) { 5372 SDOperand SrcLo, SrcHi, Src; 5373 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5374 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5375 SDOperand Result = TLI.LowerOperation( 5376 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5377 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5378 Lo = Result.Val->getOperand(0); 5379 Hi = Result.Val->getOperand(1); 5380 break; 5381 } 5382 // fall through 5383 default: 5384#ifndef NDEBUG 5385 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5386#endif 5387 assert(0 && "Do not know how to expand this operator!"); 5388 abort(); 5389 case ISD::EXTRACT_VECTOR_ELT: 5390 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5391 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5392 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5393 return ExpandOp(Lo, Lo, Hi); 5394 case ISD::UNDEF: 5395 NVT = TLI.getTypeToExpandTo(VT); 5396 Lo = DAG.getNode(ISD::UNDEF, NVT); 5397 Hi = DAG.getNode(ISD::UNDEF, NVT); 5398 break; 5399 case ISD::Constant: { 5400 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 5401 Lo = DAG.getConstant(Cst, NVT); 5402 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 5403 break; 5404 } 5405 case ISD::ConstantFP: { 5406 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5407 if (CFP->getValueType(0) == MVT::ppcf128) { 5408 APInt api = CFP->getValueAPF().convertToAPInt(); 5409 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5410 MVT::f64); 5411 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5412 MVT::f64); 5413 break; 5414 } 5415 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5416 if (getTypeAction(Lo.getValueType()) == Expand) 5417 ExpandOp(Lo, Lo, Hi); 5418 break; 5419 } 5420 case ISD::BUILD_PAIR: 5421 // Return the operands. 5422 Lo = Node->getOperand(0); 5423 Hi = Node->getOperand(1); 5424 break; 5425 5426 case ISD::MERGE_VALUES: 5427 if (Node->getNumValues() == 1) { 5428 ExpandOp(Op.getOperand(0), Lo, Hi); 5429 break; 5430 } 5431 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5432 assert(Op.ResNo == 0 && Node->getNumValues() == 2 && 5433 Op.getValue(1).getValueType() == MVT::Other && 5434 "unhandled MERGE_VALUES"); 5435 ExpandOp(Op.getOperand(0), Lo, Hi); 5436 // Remember that we legalized the chain. 5437 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5438 break; 5439 5440 case ISD::SIGN_EXTEND_INREG: 5441 ExpandOp(Node->getOperand(0), Lo, Hi); 5442 // sext_inreg the low part if needed. 5443 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5444 5445 // The high part gets the sign extension from the lo-part. This handles 5446 // things like sextinreg V:i64 from i8. 5447 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5448 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 5449 TLI.getShiftAmountTy())); 5450 break; 5451 5452 case ISD::BSWAP: { 5453 ExpandOp(Node->getOperand(0), Lo, Hi); 5454 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5455 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5456 Lo = TempLo; 5457 break; 5458 } 5459 5460 case ISD::CTPOP: 5461 ExpandOp(Node->getOperand(0), Lo, Hi); 5462 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5463 DAG.getNode(ISD::CTPOP, NVT, Lo), 5464 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5465 Hi = DAG.getConstant(0, NVT); 5466 break; 5467 5468 case ISD::CTLZ: { 5469 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5470 ExpandOp(Node->getOperand(0), Lo, Hi); 5471 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5472 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5473 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 5474 ISD::SETNE); 5475 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5476 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5477 5478 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5479 Hi = DAG.getConstant(0, NVT); 5480 break; 5481 } 5482 5483 case ISD::CTTZ: { 5484 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5485 ExpandOp(Node->getOperand(0), Lo, Hi); 5486 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5487 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5488 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 5489 ISD::SETNE); 5490 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5491 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5492 5493 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5494 Hi = DAG.getConstant(0, NVT); 5495 break; 5496 } 5497 5498 case ISD::VAARG: { 5499 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5500 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5501 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5502 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5503 5504 // Remember that we legalized the chain. 5505 Hi = LegalizeOp(Hi); 5506 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5507 if (!TLI.isLittleEndian()) 5508 std::swap(Lo, Hi); 5509 break; 5510 } 5511 5512 case ISD::LOAD: { 5513 LoadSDNode *LD = cast<LoadSDNode>(Node); 5514 SDOperand Ch = LD->getChain(); // Legalize the chain. 5515 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5516 ISD::LoadExtType ExtType = LD->getExtensionType(); 5517 int SVOffset = LD->getSrcValueOffset(); 5518 unsigned Alignment = LD->getAlignment(); 5519 bool isVolatile = LD->isVolatile(); 5520 5521 if (ExtType == ISD::NON_EXTLOAD) { 5522 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5523 isVolatile, Alignment); 5524 if (VT == MVT::f32 || VT == MVT::f64) { 5525 // f32->i32 or f64->i64 one to one expansion. 5526 // Remember that we legalized the chain. 5527 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5528 // Recursively expand the new load. 5529 if (getTypeAction(NVT) == Expand) 5530 ExpandOp(Lo, Lo, Hi); 5531 break; 5532 } 5533 5534 // Increment the pointer to the other half. 5535 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 5536 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5537 getIntPtrConstant(IncrementSize)); 5538 SVOffset += IncrementSize; 5539 Alignment = MinAlign(Alignment, IncrementSize); 5540 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5541 isVolatile, Alignment); 5542 5543 // Build a factor node to remember that this load is independent of the 5544 // other one. 5545 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5546 Hi.getValue(1)); 5547 5548 // Remember that we legalized the chain. 5549 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5550 if (!TLI.isLittleEndian()) 5551 std::swap(Lo, Hi); 5552 } else { 5553 MVT::ValueType EVT = LD->getLoadedVT(); 5554 5555 if ((VT == MVT::f64 && EVT == MVT::f32) || 5556 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 5557 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5558 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5559 SVOffset, isVolatile, Alignment); 5560 // Remember that we legalized the chain. 5561 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 5562 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 5563 break; 5564 } 5565 5566 if (EVT == NVT) 5567 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 5568 SVOffset, isVolatile, Alignment); 5569 else 5570 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 5571 SVOffset, EVT, isVolatile, 5572 Alignment); 5573 5574 // Remember that we legalized the chain. 5575 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5576 5577 if (ExtType == ISD::SEXTLOAD) { 5578 // The high part is obtained by SRA'ing all but one of the bits of the 5579 // lo part. 5580 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5581 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5582 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5583 } else if (ExtType == ISD::ZEXTLOAD) { 5584 // The high part is just a zero. 5585 Hi = DAG.getConstant(0, NVT); 5586 } else /* if (ExtType == ISD::EXTLOAD) */ { 5587 // The high part is undefined. 5588 Hi = DAG.getNode(ISD::UNDEF, NVT); 5589 } 5590 } 5591 break; 5592 } 5593 case ISD::AND: 5594 case ISD::OR: 5595 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 5596 SDOperand LL, LH, RL, RH; 5597 ExpandOp(Node->getOperand(0), LL, LH); 5598 ExpandOp(Node->getOperand(1), RL, RH); 5599 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 5600 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 5601 break; 5602 } 5603 case ISD::SELECT: { 5604 SDOperand LL, LH, RL, RH; 5605 ExpandOp(Node->getOperand(1), LL, LH); 5606 ExpandOp(Node->getOperand(2), RL, RH); 5607 if (getTypeAction(NVT) == Expand) 5608 NVT = TLI.getTypeToExpandTo(NVT); 5609 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 5610 if (VT != MVT::f32) 5611 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 5612 break; 5613 } 5614 case ISD::SELECT_CC: { 5615 SDOperand TL, TH, FL, FH; 5616 ExpandOp(Node->getOperand(2), TL, TH); 5617 ExpandOp(Node->getOperand(3), FL, FH); 5618 if (getTypeAction(NVT) == Expand) 5619 NVT = TLI.getTypeToExpandTo(NVT); 5620 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5621 Node->getOperand(1), TL, FL, Node->getOperand(4)); 5622 if (VT != MVT::f32) 5623 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5624 Node->getOperand(1), TH, FH, Node->getOperand(4)); 5625 break; 5626 } 5627 case ISD::ANY_EXTEND: 5628 // The low part is any extension of the input (which degenerates to a copy). 5629 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 5630 // The high part is undefined. 5631 Hi = DAG.getNode(ISD::UNDEF, NVT); 5632 break; 5633 case ISD::SIGN_EXTEND: { 5634 // The low part is just a sign extension of the input (which degenerates to 5635 // a copy). 5636 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 5637 5638 // The high part is obtained by SRA'ing all but one of the bits of the lo 5639 // part. 5640 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5641 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5642 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5643 break; 5644 } 5645 case ISD::ZERO_EXTEND: 5646 // The low part is just a zero extension of the input (which degenerates to 5647 // a copy). 5648 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 5649 5650 // The high part is just a zero. 5651 Hi = DAG.getConstant(0, NVT); 5652 break; 5653 5654 case ISD::TRUNCATE: { 5655 // The input value must be larger than this value. Expand *it*. 5656 SDOperand NewLo; 5657 ExpandOp(Node->getOperand(0), NewLo, Hi); 5658 5659 // The low part is now either the right size, or it is closer. If not the 5660 // right size, make an illegal truncate so we recursively expand it. 5661 if (NewLo.getValueType() != Node->getValueType(0)) 5662 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 5663 ExpandOp(NewLo, Lo, Hi); 5664 break; 5665 } 5666 5667 case ISD::BIT_CONVERT: { 5668 SDOperand Tmp; 5669 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 5670 // If the target wants to, allow it to lower this itself. 5671 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5672 case Expand: assert(0 && "cannot expand FP!"); 5673 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 5674 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 5675 } 5676 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 5677 } 5678 5679 // f32 / f64 must be expanded to i32 / i64. 5680 if (VT == MVT::f32 || VT == MVT::f64) { 5681 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5682 if (getTypeAction(NVT) == Expand) 5683 ExpandOp(Lo, Lo, Hi); 5684 break; 5685 } 5686 5687 // If source operand will be expanded to the same type as VT, i.e. 5688 // i64 <- f64, i32 <- f32, expand the source operand instead. 5689 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 5690 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 5691 ExpandOp(Node->getOperand(0), Lo, Hi); 5692 break; 5693 } 5694 5695 // Turn this into a load/store pair by default. 5696 if (Tmp.Val == 0) 5697 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0)); 5698 5699 ExpandOp(Tmp, Lo, Hi); 5700 break; 5701 } 5702 5703 case ISD::READCYCLECOUNTER: { 5704 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 5705 TargetLowering::Custom && 5706 "Must custom expand ReadCycleCounter"); 5707 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 5708 assert(Tmp.Val && "Node must be custom expanded!"); 5709 ExpandOp(Tmp.getValue(0), Lo, Hi); 5710 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 5711 LegalizeOp(Tmp.getValue(1))); 5712 break; 5713 } 5714 5715 // These operators cannot be expanded directly, emit them as calls to 5716 // library functions. 5717 case ISD::FP_TO_SINT: { 5718 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 5719 SDOperand Op; 5720 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5721 case Expand: assert(0 && "cannot expand FP!"); 5722 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5723 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5724 } 5725 5726 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 5727 5728 // Now that the custom expander is done, expand the result, which is still 5729 // VT. 5730 if (Op.Val) { 5731 ExpandOp(Op, Lo, Hi); 5732 break; 5733 } 5734 } 5735 5736 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5737 if (Node->getOperand(0).getValueType() == MVT::f32) 5738 LC = RTLIB::FPTOSINT_F32_I64; 5739 else if (Node->getOperand(0).getValueType() == MVT::f64) 5740 LC = RTLIB::FPTOSINT_F64_I64; 5741 else if (Node->getOperand(0).getValueType() == MVT::f80) 5742 LC = RTLIB::FPTOSINT_F80_I64; 5743 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 5744 LC = RTLIB::FPTOSINT_PPCF128_I64; 5745 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5746 false/*sign irrelevant*/, Hi); 5747 break; 5748 } 5749 5750 case ISD::FP_TO_UINT: { 5751 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 5752 SDOperand Op; 5753 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5754 case Expand: assert(0 && "cannot expand FP!"); 5755 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5756 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5757 } 5758 5759 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 5760 5761 // Now that the custom expander is done, expand the result. 5762 if (Op.Val) { 5763 ExpandOp(Op, Lo, Hi); 5764 break; 5765 } 5766 } 5767 5768 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5769 if (Node->getOperand(0).getValueType() == MVT::f32) 5770 LC = RTLIB::FPTOUINT_F32_I64; 5771 else if (Node->getOperand(0).getValueType() == MVT::f64) 5772 LC = RTLIB::FPTOUINT_F64_I64; 5773 else if (Node->getOperand(0).getValueType() == MVT::f80) 5774 LC = RTLIB::FPTOUINT_F80_I64; 5775 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 5776 LC = RTLIB::FPTOUINT_PPCF128_I64; 5777 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5778 false/*sign irrelevant*/, Hi); 5779 break; 5780 } 5781 5782 case ISD::SHL: { 5783 // If the target wants custom lowering, do so. 5784 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5785 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 5786 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 5787 Op = TLI.LowerOperation(Op, DAG); 5788 if (Op.Val) { 5789 // Now that the custom expander is done, expand the result, which is 5790 // still VT. 5791 ExpandOp(Op, Lo, Hi); 5792 break; 5793 } 5794 } 5795 5796 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 5797 // this X << 1 as X+X. 5798 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 5799 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 5800 TLI.isOperationLegal(ISD::ADDE, NVT)) { 5801 SDOperand LoOps[2], HiOps[3]; 5802 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 5803 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 5804 LoOps[1] = LoOps[0]; 5805 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5806 5807 HiOps[1] = HiOps[0]; 5808 HiOps[2] = Lo.getValue(1); 5809 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5810 break; 5811 } 5812 } 5813 5814 // If we can emit an efficient shift operation, do so now. 5815 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5816 break; 5817 5818 // If this target supports SHL_PARTS, use it. 5819 TargetLowering::LegalizeAction Action = 5820 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 5821 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5822 Action == TargetLowering::Custom) { 5823 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5824 break; 5825 } 5826 5827 // Otherwise, emit a libcall. 5828 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 5829 false/*left shift=unsigned*/, Hi); 5830 break; 5831 } 5832 5833 case ISD::SRA: { 5834 // If the target wants custom lowering, do so. 5835 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5836 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 5837 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 5838 Op = TLI.LowerOperation(Op, DAG); 5839 if (Op.Val) { 5840 // Now that the custom expander is done, expand the result, which is 5841 // still VT. 5842 ExpandOp(Op, Lo, Hi); 5843 break; 5844 } 5845 } 5846 5847 // If we can emit an efficient shift operation, do so now. 5848 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5849 break; 5850 5851 // If this target supports SRA_PARTS, use it. 5852 TargetLowering::LegalizeAction Action = 5853 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 5854 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5855 Action == TargetLowering::Custom) { 5856 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5857 break; 5858 } 5859 5860 // Otherwise, emit a libcall. 5861 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 5862 true/*ashr is signed*/, Hi); 5863 break; 5864 } 5865 5866 case ISD::SRL: { 5867 // If the target wants custom lowering, do so. 5868 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5869 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 5870 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 5871 Op = TLI.LowerOperation(Op, DAG); 5872 if (Op.Val) { 5873 // Now that the custom expander is done, expand the result, which is 5874 // still VT. 5875 ExpandOp(Op, Lo, Hi); 5876 break; 5877 } 5878 } 5879 5880 // If we can emit an efficient shift operation, do so now. 5881 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5882 break; 5883 5884 // If this target supports SRL_PARTS, use it. 5885 TargetLowering::LegalizeAction Action = 5886 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 5887 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5888 Action == TargetLowering::Custom) { 5889 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5890 break; 5891 } 5892 5893 // Otherwise, emit a libcall. 5894 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 5895 false/*lshr is unsigned*/, Hi); 5896 break; 5897 } 5898 5899 case ISD::ADD: 5900 case ISD::SUB: { 5901 // If the target wants to custom expand this, let them. 5902 if (TLI.getOperationAction(Node->getOpcode(), VT) == 5903 TargetLowering::Custom) { 5904 Op = TLI.LowerOperation(Op, DAG); 5905 if (Op.Val) { 5906 ExpandOp(Op, Lo, Hi); 5907 break; 5908 } 5909 } 5910 5911 // Expand the subcomponents. 5912 SDOperand LHSL, LHSH, RHSL, RHSH; 5913 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5914 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5915 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5916 SDOperand LoOps[2], HiOps[3]; 5917 LoOps[0] = LHSL; 5918 LoOps[1] = RHSL; 5919 HiOps[0] = LHSH; 5920 HiOps[1] = RHSH; 5921 if (Node->getOpcode() == ISD::ADD) { 5922 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5923 HiOps[2] = Lo.getValue(1); 5924 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5925 } else { 5926 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5927 HiOps[2] = Lo.getValue(1); 5928 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5929 } 5930 break; 5931 } 5932 5933 case ISD::ADDC: 5934 case ISD::SUBC: { 5935 // Expand the subcomponents. 5936 SDOperand LHSL, LHSH, RHSL, RHSH; 5937 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5938 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5939 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5940 SDOperand LoOps[2] = { LHSL, RHSL }; 5941 SDOperand HiOps[3] = { LHSH, RHSH }; 5942 5943 if (Node->getOpcode() == ISD::ADDC) { 5944 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5945 HiOps[2] = Lo.getValue(1); 5946 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5947 } else { 5948 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5949 HiOps[2] = Lo.getValue(1); 5950 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5951 } 5952 // Remember that we legalized the flag. 5953 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5954 break; 5955 } 5956 case ISD::ADDE: 5957 case ISD::SUBE: { 5958 // Expand the subcomponents. 5959 SDOperand LHSL, LHSH, RHSL, RHSH; 5960 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5961 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5962 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5963 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 5964 SDOperand HiOps[3] = { LHSH, RHSH }; 5965 5966 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 5967 HiOps[2] = Lo.getValue(1); 5968 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 5969 5970 // Remember that we legalized the flag. 5971 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5972 break; 5973 } 5974 case ISD::MUL: { 5975 // If the target wants to custom expand this, let them. 5976 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 5977 SDOperand New = TLI.LowerOperation(Op, DAG); 5978 if (New.Val) { 5979 ExpandOp(New, Lo, Hi); 5980 break; 5981 } 5982 } 5983 5984 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 5985 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 5986 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 5987 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 5988 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 5989 SDOperand LL, LH, RL, RH; 5990 ExpandOp(Node->getOperand(0), LL, LH); 5991 ExpandOp(Node->getOperand(1), RL, RH); 5992 unsigned BitSize = MVT::getSizeInBits(RH.getValueType()); 5993 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 5994 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 5995 // FIXME: generalize this to handle other bit sizes 5996 if (LHSSB == 32 && RHSSB == 32 && 5997 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) && 5998 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) { 5999 // The inputs are both zero-extended. 6000 if (HasUMUL_LOHI) { 6001 // We can emit a umul_lohi. 6002 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6003 Hi = SDOperand(Lo.Val, 1); 6004 break; 6005 } 6006 if (HasMULHU) { 6007 // We can emit a mulhu+mul. 6008 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6009 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6010 break; 6011 } 6012 } 6013 if (LHSSB > BitSize && RHSSB > BitSize) { 6014 // The input values are both sign-extended. 6015 if (HasSMUL_LOHI) { 6016 // We can emit a smul_lohi. 6017 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6018 Hi = SDOperand(Lo.Val, 1); 6019 break; 6020 } 6021 if (HasMULHS) { 6022 // We can emit a mulhs+mul. 6023 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6024 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6025 break; 6026 } 6027 } 6028 if (HasUMUL_LOHI) { 6029 // Lo,Hi = umul LHS, RHS. 6030 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6031 DAG.getVTList(NVT, NVT), LL, RL); 6032 Lo = UMulLOHI; 6033 Hi = UMulLOHI.getValue(1); 6034 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6035 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6036 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6037 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6038 break; 6039 } 6040 if (HasMULHU) { 6041 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6042 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6043 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6044 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6045 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6046 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6047 break; 6048 } 6049 } 6050 6051 // If nothing else, we can make a libcall. 6052 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 6053 false/*sign irrelevant*/, Hi); 6054 break; 6055 } 6056 case ISD::SDIV: 6057 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 6058 break; 6059 case ISD::UDIV: 6060 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 6061 break; 6062 case ISD::SREM: 6063 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 6064 break; 6065 case ISD::UREM: 6066 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 6067 break; 6068 6069 case ISD::FADD: 6070 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::ADD_F32 : 6071 VT == MVT::f64 ? RTLIB::ADD_F64 : 6072 VT == MVT::ppcf128 ? 6073 RTLIB::ADD_PPCF128 : 6074 RTLIB::UNKNOWN_LIBCALL), 6075 Node, false, Hi); 6076 break; 6077 case ISD::FSUB: 6078 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::SUB_F32 : 6079 VT == MVT::f64 ? RTLIB::SUB_F64 : 6080 VT == MVT::ppcf128 ? 6081 RTLIB::SUB_PPCF128 : 6082 RTLIB::UNKNOWN_LIBCALL), 6083 Node, false, Hi); 6084 break; 6085 case ISD::FMUL: 6086 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::MUL_F32 : 6087 VT == MVT::f64 ? RTLIB::MUL_F64 : 6088 VT == MVT::ppcf128 ? 6089 RTLIB::MUL_PPCF128 : 6090 RTLIB::UNKNOWN_LIBCALL), 6091 Node, false, Hi); 6092 break; 6093 case ISD::FDIV: 6094 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::DIV_F32 : 6095 VT == MVT::f64 ? RTLIB::DIV_F64 : 6096 VT == MVT::ppcf128 ? 6097 RTLIB::DIV_PPCF128 : 6098 RTLIB::UNKNOWN_LIBCALL), 6099 Node, false, Hi); 6100 break; 6101 case ISD::FP_EXTEND: 6102 if (VT == MVT::ppcf128) { 6103 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6104 Node->getOperand(0).getValueType()==MVT::f64); 6105 const uint64_t zero = 0; 6106 if (Node->getOperand(0).getValueType()==MVT::f32) 6107 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6108 else 6109 Hi = Node->getOperand(0); 6110 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6111 break; 6112 } 6113 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 6114 break; 6115 case ISD::FP_ROUND: 6116 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 6117 break; 6118 case ISD::FPOWI: 6119 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) ? RTLIB::POWI_F32 : 6120 (VT == MVT::f64) ? RTLIB::POWI_F64 : 6121 (VT == MVT::f80) ? RTLIB::POWI_F80 : 6122 (VT == MVT::ppcf128) ? 6123 RTLIB::POWI_PPCF128 : 6124 RTLIB::UNKNOWN_LIBCALL), 6125 Node, false, Hi); 6126 break; 6127 case ISD::FSQRT: 6128 case ISD::FSIN: 6129 case ISD::FCOS: { 6130 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6131 switch(Node->getOpcode()) { 6132 case ISD::FSQRT: 6133 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : 6134 (VT == MVT::f64) ? RTLIB::SQRT_F64 : 6135 (VT == MVT::f80) ? RTLIB::SQRT_F80 : 6136 (VT == MVT::ppcf128) ? RTLIB::SQRT_PPCF128 : 6137 RTLIB::UNKNOWN_LIBCALL; 6138 break; 6139 case ISD::FSIN: 6140 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 6141 break; 6142 case ISD::FCOS: 6143 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64; 6144 break; 6145 default: assert(0 && "Unreachable!"); 6146 } 6147 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 6148 break; 6149 } 6150 case ISD::FABS: { 6151 if (VT == MVT::ppcf128) { 6152 SDOperand Tmp; 6153 ExpandOp(Node->getOperand(0), Lo, Tmp); 6154 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6155 // lo = hi==fabs(hi) ? lo : -lo; 6156 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6157 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6158 DAG.getCondCode(ISD::SETEQ)); 6159 break; 6160 } 6161 SDOperand Mask = (VT == MVT::f64) 6162 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6163 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6164 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6165 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6166 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6167 if (getTypeAction(NVT) == Expand) 6168 ExpandOp(Lo, Lo, Hi); 6169 break; 6170 } 6171 case ISD::FNEG: { 6172 if (VT == MVT::ppcf128) { 6173 ExpandOp(Node->getOperand(0), Lo, Hi); 6174 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6175 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6176 break; 6177 } 6178 SDOperand Mask = (VT == MVT::f64) 6179 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6180 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6181 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6182 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6183 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6184 if (getTypeAction(NVT) == Expand) 6185 ExpandOp(Lo, Lo, Hi); 6186 break; 6187 } 6188 case ISD::FCOPYSIGN: { 6189 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6190 if (getTypeAction(NVT) == Expand) 6191 ExpandOp(Lo, Lo, Hi); 6192 break; 6193 } 6194 case ISD::SINT_TO_FP: 6195 case ISD::UINT_TO_FP: { 6196 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6197 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 6198 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) { 6199 static uint64_t zero = 0; 6200 if (isSigned) { 6201 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6202 Node->getOperand(0))); 6203 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6204 } else { 6205 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6206 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6207 Node->getOperand(0))); 6208 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6209 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6210 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6211 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6212 DAG.getConstant(0, MVT::i32), 6213 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6214 DAG.getConstantFP( 6215 APFloat(APInt(128, 2, TwoE32)), 6216 MVT::ppcf128)), 6217 Hi, 6218 DAG.getCondCode(ISD::SETLT)), 6219 Lo, Hi); 6220 } 6221 break; 6222 } 6223 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6224 // si64->ppcf128 done by libcall, below 6225 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6226 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6227 Lo, Hi); 6228 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6229 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6230 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6231 DAG.getConstant(0, MVT::i64), 6232 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6233 DAG.getConstantFP( 6234 APFloat(APInt(128, 2, TwoE64)), 6235 MVT::ppcf128)), 6236 Hi, 6237 DAG.getCondCode(ISD::SETLT)), 6238 Lo, Hi); 6239 break; 6240 } 6241 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6242 if (Node->getOperand(0).getValueType() == MVT::i64) { 6243 if (VT == MVT::f32) 6244 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 6245 else if (VT == MVT::f64) 6246 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 6247 else if (VT == MVT::f80) { 6248 assert(isSigned); 6249 LC = RTLIB::SINTTOFP_I64_F80; 6250 } 6251 else if (VT == MVT::ppcf128) { 6252 assert(isSigned); 6253 LC = RTLIB::SINTTOFP_I64_PPCF128; 6254 } 6255 } else { 6256 if (VT == MVT::f32) 6257 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 6258 else 6259 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 6260 } 6261 6262 // Promote the operand if needed. 6263 if (getTypeAction(SrcVT) == Promote) { 6264 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6265 Tmp = isSigned 6266 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6267 DAG.getValueType(SrcVT)) 6268 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6269 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6270 } 6271 6272 const char *LibCall = TLI.getLibcallName(LC); 6273 if (LibCall) 6274 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 6275 else { 6276 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6277 Node->getOperand(0)); 6278 if (getTypeAction(Lo.getValueType()) == Expand) 6279 ExpandOp(Lo, Lo, Hi); 6280 } 6281 break; 6282 } 6283 } 6284 6285 // Make sure the resultant values have been legalized themselves, unless this 6286 // is a type that requires multi-step expansion. 6287 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6288 Lo = LegalizeOp(Lo); 6289 if (Hi.Val) 6290 // Don't legalize the high part if it is expanded to a single node. 6291 Hi = LegalizeOp(Hi); 6292 } 6293 6294 // Remember in a map if the values will be reused later. 6295 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6296 assert(isNew && "Value already expanded?!?"); 6297} 6298 6299/// SplitVectorOp - Given an operand of vector type, break it down into 6300/// two smaller values, still of vector type. 6301void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6302 SDOperand &Hi) { 6303 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); 6304 SDNode *Node = Op.Val; 6305 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType()); 6306 assert(NumElements > 1 && "Cannot split a single element vector!"); 6307 6308 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType()); 6309 6310 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6311 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6312 6313 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo); 6314 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi); 6315 6316 // See if we already split it. 6317 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6318 = SplitNodes.find(Op); 6319 if (I != SplitNodes.end()) { 6320 Lo = I->second.first; 6321 Hi = I->second.second; 6322 return; 6323 } 6324 6325 switch (Node->getOpcode()) { 6326 default: 6327#ifndef NDEBUG 6328 Node->dump(&DAG); 6329#endif 6330 assert(0 && "Unhandled operation in SplitVectorOp!"); 6331 case ISD::UNDEF: 6332 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6333 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6334 break; 6335 case ISD::BUILD_PAIR: 6336 Lo = Node->getOperand(0); 6337 Hi = Node->getOperand(1); 6338 break; 6339 case ISD::INSERT_VECTOR_ELT: { 6340 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6341 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 6342 SDOperand ScalarOp = Node->getOperand(1); 6343 if (Index < NewNumElts_Lo) 6344 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6345 DAG.getConstant(Index, TLI.getPointerTy())); 6346 else 6347 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6348 DAG.getConstant(Index - NewNumElts_Lo, 6349 TLI.getPointerTy())); 6350 break; 6351 } 6352 case ISD::VECTOR_SHUFFLE: { 6353 // Build the low part. 6354 SDOperand Mask = Node->getOperand(2); 6355 SmallVector<SDOperand, 8> Ops; 6356 MVT::ValueType PtrVT = TLI.getPointerTy(); 6357 6358 // Insert all of the elements from the input that are needed. We use 6359 // buildvector of extractelement here because the input vectors will have 6360 // to be legalized, so this makes the code simpler. 6361 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6362 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 6363 SDOperand InVec = Node->getOperand(0); 6364 if (Idx >= NumElements) { 6365 InVec = Node->getOperand(1); 6366 Idx -= NumElements; 6367 } 6368 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6369 DAG.getConstant(Idx, PtrVT))); 6370 } 6371 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6372 Ops.clear(); 6373 6374 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6375 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 6376 SDOperand InVec = Node->getOperand(0); 6377 if (Idx >= NumElements) { 6378 InVec = Node->getOperand(1); 6379 Idx -= NumElements; 6380 } 6381 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6382 DAG.getConstant(Idx, PtrVT))); 6383 } 6384 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6385 break; 6386 } 6387 case ISD::BUILD_VECTOR: { 6388 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6389 Node->op_begin()+NewNumElts_Lo); 6390 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6391 6392 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6393 Node->op_end()); 6394 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6395 break; 6396 } 6397 case ISD::CONCAT_VECTORS: { 6398 // FIXME: Handle non-power-of-two vectors? 6399 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6400 if (NewNumSubvectors == 1) { 6401 Lo = Node->getOperand(0); 6402 Hi = Node->getOperand(1); 6403 } else { 6404 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6405 Node->op_begin()+NewNumSubvectors); 6406 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6407 6408 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6409 Node->op_end()); 6410 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6411 } 6412 break; 6413 } 6414 case ISD::SELECT: { 6415 SDOperand Cond = Node->getOperand(0); 6416 6417 SDOperand LL, LH, RL, RH; 6418 SplitVectorOp(Node->getOperand(1), LL, LH); 6419 SplitVectorOp(Node->getOperand(2), RL, RH); 6420 6421 if (MVT::isVector(Cond.getValueType())) { 6422 // Handle a vector merge. 6423 SDOperand CL, CH; 6424 SplitVectorOp(Cond, CL, CH); 6425 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6426 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6427 } else { 6428 // Handle a simple select with vector operands. 6429 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6430 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6431 } 6432 break; 6433 } 6434 case ISD::ADD: 6435 case ISD::SUB: 6436 case ISD::MUL: 6437 case ISD::FADD: 6438 case ISD::FSUB: 6439 case ISD::FMUL: 6440 case ISD::SDIV: 6441 case ISD::UDIV: 6442 case ISD::FDIV: 6443 case ISD::FPOW: 6444 case ISD::AND: 6445 case ISD::OR: 6446 case ISD::XOR: 6447 case ISD::UREM: 6448 case ISD::SREM: 6449 case ISD::FREM: { 6450 SDOperand LL, LH, RL, RH; 6451 SplitVectorOp(Node->getOperand(0), LL, LH); 6452 SplitVectorOp(Node->getOperand(1), RL, RH); 6453 6454 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 6455 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 6456 break; 6457 } 6458 case ISD::FPOWI: { 6459 SDOperand L, H; 6460 SplitVectorOp(Node->getOperand(0), L, H); 6461 6462 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 6463 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 6464 break; 6465 } 6466 case ISD::CTTZ: 6467 case ISD::CTLZ: 6468 case ISD::CTPOP: 6469 case ISD::FNEG: 6470 case ISD::FABS: 6471 case ISD::FSQRT: 6472 case ISD::FSIN: 6473 case ISD::FCOS: 6474 case ISD::FP_TO_SINT: 6475 case ISD::FP_TO_UINT: 6476 case ISD::SINT_TO_FP: 6477 case ISD::UINT_TO_FP: { 6478 SDOperand L, H; 6479 SplitVectorOp(Node->getOperand(0), L, H); 6480 6481 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 6482 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 6483 break; 6484 } 6485 case ISD::LOAD: { 6486 LoadSDNode *LD = cast<LoadSDNode>(Node); 6487 SDOperand Ch = LD->getChain(); 6488 SDOperand Ptr = LD->getBasePtr(); 6489 const Value *SV = LD->getSrcValue(); 6490 int SVOffset = LD->getSrcValueOffset(); 6491 unsigned Alignment = LD->getAlignment(); 6492 bool isVolatile = LD->isVolatile(); 6493 6494 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6495 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8; 6496 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6497 getIntPtrConstant(IncrementSize)); 6498 SVOffset += IncrementSize; 6499 Alignment = MinAlign(Alignment, IncrementSize); 6500 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6501 6502 // Build a factor node to remember that this load is independent of the 6503 // other one. 6504 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6505 Hi.getValue(1)); 6506 6507 // Remember that we legalized the chain. 6508 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6509 break; 6510 } 6511 case ISD::BIT_CONVERT: { 6512 // We know the result is a vector. The input may be either a vector or a 6513 // scalar value. 6514 SDOperand InOp = Node->getOperand(0); 6515 if (!MVT::isVector(InOp.getValueType()) || 6516 MVT::getVectorNumElements(InOp.getValueType()) == 1) { 6517 // The input is a scalar or single-element vector. 6518 // Lower to a store/load so that it can be split. 6519 // FIXME: this could be improved probably. 6520 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); 6521 6522 SDOperand St = DAG.getStore(DAG.getEntryNode(), 6523 InOp, Ptr, NULL, 0); 6524 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0); 6525 } 6526 // Split the vector and convert each of the pieces now. 6527 SplitVectorOp(InOp, Lo, Hi); 6528 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 6529 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 6530 break; 6531 } 6532 } 6533 6534 // Remember in a map if the values will be reused later. 6535 bool isNew = 6536 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 6537 assert(isNew && "Value already split?!?"); 6538} 6539 6540 6541/// ScalarizeVectorOp - Given an operand of single-element vector type 6542/// (e.g. v1f32), convert it into the equivalent operation that returns a 6543/// scalar (e.g. f32) value. 6544SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 6545 assert(MVT::isVector(Op.getValueType()) && 6546 "Bad ScalarizeVectorOp invocation!"); 6547 SDNode *Node = Op.Val; 6548 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); 6549 assert(MVT::getVectorNumElements(Op.getValueType()) == 1); 6550 6551 // See if we already scalarized it. 6552 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 6553 if (I != ScalarizedNodes.end()) return I->second; 6554 6555 SDOperand Result; 6556 switch (Node->getOpcode()) { 6557 default: 6558#ifndef NDEBUG 6559 Node->dump(&DAG); cerr << "\n"; 6560#endif 6561 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 6562 case ISD::ADD: 6563 case ISD::FADD: 6564 case ISD::SUB: 6565 case ISD::FSUB: 6566 case ISD::MUL: 6567 case ISD::FMUL: 6568 case ISD::SDIV: 6569 case ISD::UDIV: 6570 case ISD::FDIV: 6571 case ISD::SREM: 6572 case ISD::UREM: 6573 case ISD::FREM: 6574 case ISD::FPOW: 6575 case ISD::AND: 6576 case ISD::OR: 6577 case ISD::XOR: 6578 Result = DAG.getNode(Node->getOpcode(), 6579 NewVT, 6580 ScalarizeVectorOp(Node->getOperand(0)), 6581 ScalarizeVectorOp(Node->getOperand(1))); 6582 break; 6583 case ISD::FNEG: 6584 case ISD::FABS: 6585 case ISD::FSQRT: 6586 case ISD::FSIN: 6587 case ISD::FCOS: 6588 Result = DAG.getNode(Node->getOpcode(), 6589 NewVT, 6590 ScalarizeVectorOp(Node->getOperand(0))); 6591 break; 6592 case ISD::FPOWI: 6593 Result = DAG.getNode(Node->getOpcode(), 6594 NewVT, 6595 ScalarizeVectorOp(Node->getOperand(0)), 6596 Node->getOperand(1)); 6597 break; 6598 case ISD::LOAD: { 6599 LoadSDNode *LD = cast<LoadSDNode>(Node); 6600 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 6601 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 6602 6603 const Value *SV = LD->getSrcValue(); 6604 int SVOffset = LD->getSrcValueOffset(); 6605 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 6606 LD->isVolatile(), LD->getAlignment()); 6607 6608 // Remember that we legalized the chain. 6609 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 6610 break; 6611 } 6612 case ISD::BUILD_VECTOR: 6613 Result = Node->getOperand(0); 6614 break; 6615 case ISD::INSERT_VECTOR_ELT: 6616 // Returning the inserted scalar element. 6617 Result = Node->getOperand(1); 6618 break; 6619 case ISD::CONCAT_VECTORS: 6620 assert(Node->getOperand(0).getValueType() == NewVT && 6621 "Concat of non-legal vectors not yet supported!"); 6622 Result = Node->getOperand(0); 6623 break; 6624 case ISD::VECTOR_SHUFFLE: { 6625 // Figure out if the scalar is the LHS or RHS and return it. 6626 SDOperand EltNum = Node->getOperand(2).getOperand(0); 6627 if (cast<ConstantSDNode>(EltNum)->getValue()) 6628 Result = ScalarizeVectorOp(Node->getOperand(1)); 6629 else 6630 Result = ScalarizeVectorOp(Node->getOperand(0)); 6631 break; 6632 } 6633 case ISD::EXTRACT_SUBVECTOR: 6634 Result = Node->getOperand(0); 6635 assert(Result.getValueType() == NewVT); 6636 break; 6637 case ISD::BIT_CONVERT: 6638 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 6639 break; 6640 case ISD::SELECT: 6641 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 6642 ScalarizeVectorOp(Op.getOperand(1)), 6643 ScalarizeVectorOp(Op.getOperand(2))); 6644 break; 6645 } 6646 6647 if (TLI.isTypeLegal(NewVT)) 6648 Result = LegalizeOp(Result); 6649 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 6650 assert(isNew && "Value already scalarized?"); 6651 return Result; 6652} 6653 6654 6655// SelectionDAG::Legalize - This is the entry point for the file. 6656// 6657void SelectionDAG::Legalize() { 6658 if (ViewLegalizeDAGs) viewGraph(); 6659 6660 /// run - This is the main entry point to this class. 6661 /// 6662 SelectionDAGLegalize(*this).LegalizeDAG(); 6663} 6664 6665