LegalizeDAG.cpp revision c9dc11457809b6641de853af2261721a97ad1f26
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetMachine.h" 21#include "llvm/Target/TargetOptions.h" 22#include "llvm/CallingConv.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Support/MathExtras.h" 26#include "llvm/Support/CommandLine.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/ADT/DenseMap.h" 29#include "llvm/ADT/SmallVector.h" 30#include "llvm/ADT/SmallPtrSet.h" 31#include <map> 32using namespace llvm; 33 34#ifndef NDEBUG 35static cl::opt<bool> 36ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 37 cl::desc("Pop up a window to show dags before legalize")); 38#else 39static const bool ViewLegalizeDAGs = 0; 40#endif 41 42namespace llvm { 43template<> 44struct DenseMapKeyInfo<SDOperand> { 45 static inline SDOperand getEmptyKey() { return SDOperand((SDNode*)-1, -1U); } 46 static inline SDOperand getTombstoneKey() { return SDOperand((SDNode*)-1, 0);} 47 static unsigned getHashValue(const SDOperand &Val) { 48 return DenseMapKeyInfo<void*>::getHashValue(Val.Val) + Val.ResNo; 49 } 50 static bool isPod() { return true; } 51}; 52} 53 54//===----------------------------------------------------------------------===// 55/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 56/// hacks on it until the target machine can handle it. This involves 57/// eliminating value sizes the machine cannot handle (promoting small sizes to 58/// large sizes or splitting up large values into small values) as well as 59/// eliminating operations the machine cannot handle. 60/// 61/// This code also does a small amount of optimization and recognition of idioms 62/// as part of its processing. For example, if a target does not support a 63/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 64/// will attempt merge setcc and brc instructions into brcc's. 65/// 66namespace { 67class VISIBILITY_HIDDEN SelectionDAGLegalize { 68 TargetLowering &TLI; 69 SelectionDAG &DAG; 70 71 // Libcall insertion helpers. 72 73 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 74 /// legalized. We use this to ensure that calls are properly serialized 75 /// against each other, including inserted libcalls. 76 SDOperand LastCALLSEQ_END; 77 78 /// IsLegalizingCall - This member is used *only* for purposes of providing 79 /// helpful assertions that a libcall isn't created while another call is 80 /// being legalized (which could lead to non-serialized call sequences). 81 bool IsLegalizingCall; 82 83 enum LegalizeAction { 84 Legal, // The target natively supports this operation. 85 Promote, // This operation should be executed in a larger type. 86 Expand // Try to expand this to other ops, otherwise use a libcall. 87 }; 88 89 /// ValueTypeActions - This is a bitvector that contains two bits for each 90 /// value type, where the two bits correspond to the LegalizeAction enum. 91 /// This can be queried with "getTypeAction(VT)". 92 TargetLowering::ValueTypeActionImpl ValueTypeActions; 93 94 /// LegalizedNodes - For nodes that are of legal width, and that have more 95 /// than one use, this map indicates what regularized operand to use. This 96 /// allows us to avoid legalizing the same thing more than once. 97 DenseMap<SDOperand, SDOperand> LegalizedNodes; 98 99 /// PromotedNodes - For nodes that are below legal width, and that have more 100 /// than one use, this map indicates what promoted value to use. This allows 101 /// us to avoid promoting the same thing more than once. 102 DenseMap<SDOperand, SDOperand> PromotedNodes; 103 104 /// ExpandedNodes - For nodes that need to be expanded this map indicates 105 /// which which operands are the expanded version of the input. This allows 106 /// us to avoid expanding the same node more than once. 107 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 108 109 /// SplitNodes - For vector nodes that need to be split, this map indicates 110 /// which which operands are the split version of the input. This allows us 111 /// to avoid splitting the same node more than once. 112 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 113 114 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to 115 /// concrete vector types, this contains the mapping of ones we have already 116 /// processed to the result. 117 std::map<SDOperand, SDOperand> PackedNodes; 118 119 void AddLegalizedOperand(SDOperand From, SDOperand To) { 120 LegalizedNodes.insert(std::make_pair(From, To)); 121 // If someone requests legalization of the new node, return itself. 122 if (From != To) 123 LegalizedNodes.insert(std::make_pair(To, To)); 124 } 125 void AddPromotedOperand(SDOperand From, SDOperand To) { 126 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 127 assert(isNew && "Got into the map somehow?"); 128 // If someone requests legalization of the new node, return itself. 129 LegalizedNodes.insert(std::make_pair(To, To)); 130 } 131 132public: 133 134 SelectionDAGLegalize(SelectionDAG &DAG); 135 136 /// getTypeAction - Return how we should legalize values of this type, either 137 /// it is already legal or we need to expand it into multiple registers of 138 /// smaller integer type, or we need to promote it to a larger type. 139 LegalizeAction getTypeAction(MVT::ValueType VT) const { 140 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 141 } 142 143 /// isTypeLegal - Return true if this type is legal on this target. 144 /// 145 bool isTypeLegal(MVT::ValueType VT) const { 146 return getTypeAction(VT) == Legal; 147 } 148 149 void LegalizeDAG(); 150 151private: 152 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 153 /// appropriate for its type. 154 void HandleOp(SDOperand Op); 155 156 /// LegalizeOp - We know that the specified value has a legal type. 157 /// Recursively ensure that the operands have legal types, then return the 158 /// result. 159 SDOperand LegalizeOp(SDOperand O); 160 161 /// PromoteOp - Given an operation that produces a value in an invalid type, 162 /// promote it to compute the value into a larger type. The produced value 163 /// will have the correct bits for the low portion of the register, but no 164 /// guarantee is made about the top bits: it may be zero, sign-extended, or 165 /// garbage. 166 SDOperand PromoteOp(SDOperand O); 167 168 /// ExpandOp - Expand the specified SDOperand into its two component pieces 169 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 170 /// the LegalizeNodes map is filled in for any results that are not expanded, 171 /// the ExpandedNodes map is filled in for any results that are expanded, and 172 /// the Lo/Hi values are returned. This applies to integer types and Vector 173 /// types. 174 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 175 176 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 177 /// two smaller values of MVT::Vector type. 178 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 179 180 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 181 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When 182 /// this is called, we know that PackedVT is the right type for the result and 183 /// we know that this type is legal for the target. 184 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT); 185 186 /// isShuffleLegal - Return true if a vector shuffle is legal with the 187 /// specified mask and type. Targets can specify exactly which masks they 188 /// support and the code generator is tasked with not creating illegal masks. 189 /// 190 /// Note that this will also return true for shuffles that are promoted to a 191 /// different type. 192 /// 193 /// If this is a legal shuffle, this method returns the (possibly promoted) 194 /// build_vector Mask. If it's not a legal shuffle, it returns null. 195 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 196 197 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 198 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 199 200 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 201 202 SDOperand CreateStackTemporary(MVT::ValueType VT); 203 204 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 205 SDOperand &Hi); 206 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 207 SDOperand Source); 208 209 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 210 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 211 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 212 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 213 SDOperand LegalOp, 214 MVT::ValueType DestVT); 215 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 216 bool isSigned); 217 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 218 bool isSigned); 219 220 SDOperand ExpandBSWAP(SDOperand Op); 221 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 222 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 223 SDOperand &Lo, SDOperand &Hi); 224 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 225 SDOperand &Lo, SDOperand &Hi); 226 227 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op); 228 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 229 230 SDOperand getIntPtrConstant(uint64_t Val) { 231 return DAG.getConstant(Val, TLI.getPointerTy()); 232 } 233}; 234} 235 236/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 237/// specified mask and type. Targets can specify exactly which masks they 238/// support and the code generator is tasked with not creating illegal masks. 239/// 240/// Note that this will also return true for shuffles that are promoted to a 241/// different type. 242SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 243 SDOperand Mask) const { 244 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 245 default: return 0; 246 case TargetLowering::Legal: 247 case TargetLowering::Custom: 248 break; 249 case TargetLowering::Promote: { 250 // If this is promoted to a different type, convert the shuffle mask and 251 // ask if it is legal in the promoted type! 252 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 253 254 // If we changed # elements, change the shuffle mask. 255 unsigned NumEltsGrowth = 256 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 257 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 258 if (NumEltsGrowth > 1) { 259 // Renumber the elements. 260 SmallVector<SDOperand, 8> Ops; 261 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 262 SDOperand InOp = Mask.getOperand(i); 263 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 264 if (InOp.getOpcode() == ISD::UNDEF) 265 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 266 else { 267 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 268 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 269 } 270 } 271 } 272 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 273 } 274 VT = NVT; 275 break; 276 } 277 } 278 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 279} 280 281/// getScalarizedOpcode - Return the scalar opcode that corresponds to the 282/// specified vector opcode. 283static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 284 switch (VecOp) { 285 default: assert(0 && "Don't know how to scalarize this opcode!"); 286 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 287 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 288 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 289 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV; 290 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV; 291 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0; 292 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0; 293 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0; 294 } 295} 296 297SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 298 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 299 ValueTypeActions(TLI.getValueTypeActions()) { 300 assert(MVT::LAST_VALUETYPE <= 32 && 301 "Too many value types for ValueTypeActions to hold!"); 302} 303 304/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 305/// not been visited yet and if all of its operands have already been visited. 306static void ComputeTopDownOrdering(SDNode *N, SmallVector<SDNode*, 64> &Order, 307 DenseMap<SDNode*, unsigned> &Visited) { 308 if (++Visited[N] != N->getNumOperands()) 309 return; // Haven't visited all operands yet 310 311 Order.push_back(N); 312 313 if (N->hasOneUse()) { // Tail recurse in common case. 314 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 315 return; 316 } 317 318 // Now that we have N in, add anything that uses it if all of their operands 319 // are now done. 320 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 321 ComputeTopDownOrdering(*UI, Order, Visited); 322} 323 324 325void SelectionDAGLegalize::LegalizeDAG() { 326 LastCALLSEQ_END = DAG.getEntryNode(); 327 IsLegalizingCall = false; 328 329 // The legalize process is inherently a bottom-up recursive process (users 330 // legalize their uses before themselves). Given infinite stack space, we 331 // could just start legalizing on the root and traverse the whole graph. In 332 // practice however, this causes us to run out of stack space on large basic 333 // blocks. To avoid this problem, compute an ordering of the nodes where each 334 // node is only legalized after all of its operands are legalized. 335 DenseMap<SDNode*, unsigned> Visited; 336 SmallVector<SDNode*, 64> Order; 337 338 // Compute ordering from all of the leaves in the graphs, those (like the 339 // entry node) that have no operands. 340 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 341 E = DAG.allnodes_end(); I != E; ++I) { 342 if (I->getNumOperands() == 0) { 343 Visited[I] = 0 - 1U; 344 ComputeTopDownOrdering(I, Order, Visited); 345 } 346 } 347 348 assert(Order.size() == Visited.size() && 349 Order.size() == 350 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 351 "Error: DAG is cyclic!"); 352 Visited.clear(); 353 354 for (unsigned i = 0, e = Order.size(); i != e; ++i) 355 HandleOp(SDOperand(Order[i], 0)); 356 357 // Finally, it's possible the root changed. Get the new root. 358 SDOperand OldRoot = DAG.getRoot(); 359 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 360 DAG.setRoot(LegalizedNodes[OldRoot]); 361 362 ExpandedNodes.clear(); 363 LegalizedNodes.clear(); 364 PromotedNodes.clear(); 365 SplitNodes.clear(); 366 PackedNodes.clear(); 367 368 // Remove dead nodes now. 369 DAG.RemoveDeadNodes(); 370} 371 372 373/// FindCallEndFromCallStart - Given a chained node that is part of a call 374/// sequence, find the CALLSEQ_END node that terminates the call sequence. 375static SDNode *FindCallEndFromCallStart(SDNode *Node) { 376 if (Node->getOpcode() == ISD::CALLSEQ_END) 377 return Node; 378 if (Node->use_empty()) 379 return 0; // No CallSeqEnd 380 381 // The chain is usually at the end. 382 SDOperand TheChain(Node, Node->getNumValues()-1); 383 if (TheChain.getValueType() != MVT::Other) { 384 // Sometimes it's at the beginning. 385 TheChain = SDOperand(Node, 0); 386 if (TheChain.getValueType() != MVT::Other) { 387 // Otherwise, hunt for it. 388 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 389 if (Node->getValueType(i) == MVT::Other) { 390 TheChain = SDOperand(Node, i); 391 break; 392 } 393 394 // Otherwise, we walked into a node without a chain. 395 if (TheChain.getValueType() != MVT::Other) 396 return 0; 397 } 398 } 399 400 for (SDNode::use_iterator UI = Node->use_begin(), 401 E = Node->use_end(); UI != E; ++UI) { 402 403 // Make sure to only follow users of our token chain. 404 SDNode *User = *UI; 405 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 406 if (User->getOperand(i) == TheChain) 407 if (SDNode *Result = FindCallEndFromCallStart(User)) 408 return Result; 409 } 410 return 0; 411} 412 413/// FindCallStartFromCallEnd - Given a chained node that is part of a call 414/// sequence, find the CALLSEQ_START node that initiates the call sequence. 415static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 416 assert(Node && "Didn't find callseq_start for a call??"); 417 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 418 419 assert(Node->getOperand(0).getValueType() == MVT::Other && 420 "Node doesn't have a token chain argument!"); 421 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 422} 423 424/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 425/// see if any uses can reach Dest. If no dest operands can get to dest, 426/// legalize them, legalize ourself, and return false, otherwise, return true. 427/// 428/// Keep track of the nodes we fine that actually do lead to Dest in 429/// NodesLeadingTo. This avoids retraversing them exponential number of times. 430/// 431bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 432 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 433 if (N == Dest) return true; // N certainly leads to Dest :) 434 435 // If we've already processed this node and it does lead to Dest, there is no 436 // need to reprocess it. 437 if (NodesLeadingTo.count(N)) return true; 438 439 // If the first result of this node has been already legalized, then it cannot 440 // reach N. 441 switch (getTypeAction(N->getValueType(0))) { 442 case Legal: 443 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 444 break; 445 case Promote: 446 if (PromotedNodes.count(SDOperand(N, 0))) return false; 447 break; 448 case Expand: 449 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 450 break; 451 } 452 453 // Okay, this node has not already been legalized. Check and legalize all 454 // operands. If none lead to Dest, then we can legalize this node. 455 bool OperandsLeadToDest = false; 456 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 457 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 458 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 459 460 if (OperandsLeadToDest) { 461 NodesLeadingTo.insert(N); 462 return true; 463 } 464 465 // Okay, this node looks safe, legalize it and return false. 466 HandleOp(SDOperand(N, 0)); 467 return false; 468} 469 470/// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 471/// appropriate for its type. 472void SelectionDAGLegalize::HandleOp(SDOperand Op) { 473 switch (getTypeAction(Op.getValueType())) { 474 default: assert(0 && "Bad type action!"); 475 case Legal: LegalizeOp(Op); break; 476 case Promote: PromoteOp(Op); break; 477 case Expand: 478 if (Op.getValueType() != MVT::Vector) { 479 SDOperand X, Y; 480 ExpandOp(Op, X, Y); 481 } else { 482 SDNode *N = Op.Val; 483 unsigned NumOps = N->getNumOperands(); 484 unsigned NumElements = 485 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue(); 486 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT(); 487 MVT::ValueType PackedVT = MVT::getVectorType(EVT, NumElements); 488 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) { 489 // In the common case, this is a legal vector type, convert it to the 490 // packed operation and type now. 491 PackVectorOp(Op, PackedVT); 492 } else if (NumElements == 1) { 493 // Otherwise, if this is a single element vector, convert it to a 494 // scalar operation. 495 PackVectorOp(Op, EVT); 496 } else { 497 // Otherwise, this is a multiple element vector that isn't supported. 498 // Split it in half and legalize both parts. 499 SDOperand X, Y; 500 SplitVectorOp(Op, X, Y); 501 } 502 } 503 break; 504 } 505} 506 507/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 508/// a load from the constant pool. 509static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 510 SelectionDAG &DAG, TargetLowering &TLI) { 511 bool Extend = false; 512 513 // If a FP immediate is precise when represented as a float and if the 514 // target can do an extending load from float to double, we put it into 515 // the constant pool as a float, even if it's is statically typed as a 516 // double. 517 MVT::ValueType VT = CFP->getValueType(0); 518 bool isDouble = VT == MVT::f64; 519 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 520 Type::FloatTy, CFP->getValue()); 521 if (!UseCP) { 522 double Val = LLVMC->getValue(); 523 return isDouble 524 ? DAG.getConstant(DoubleToBits(Val), MVT::i64) 525 : DAG.getConstant(FloatToBits(Val), MVT::i32); 526 } 527 528 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 529 // Only do this if the target has a native EXTLOAD instruction from f32. 530 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 531 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 532 VT = MVT::f32; 533 Extend = true; 534 } 535 536 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 537 if (Extend) { 538 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 539 CPIdx, NULL, 0, MVT::f32); 540 } else { 541 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 542 } 543} 544 545 546/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 547/// operations. 548static 549SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 550 SelectionDAG &DAG, TargetLowering &TLI) { 551 MVT::ValueType VT = Node->getValueType(0); 552 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 553 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 554 555 // First get the sign bit of second operand. 556 SDOperand Mask1 = (SrcVT == MVT::f64) 557 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 558 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 559 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 560 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 561 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 562 // Shift right or sign-extend it if the two operands have different types. 563 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 564 if (SizeDiff > 0) { 565 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 566 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 567 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 568 } else if (SizeDiff < 0) 569 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 570 571 // Clear the sign bit of first operand. 572 SDOperand Mask2 = (VT == MVT::f64) 573 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 574 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 575 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 576 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 577 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 578 579 // Or the value with the sign bit. 580 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 581 return Result; 582} 583 584 585/// LegalizeOp - We know that the specified value has a legal type. 586/// Recursively ensure that the operands have legal types, then return the 587/// result. 588SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 589 assert(isTypeLegal(Op.getValueType()) && 590 "Caller should expand or promote operands that are not legal!"); 591 SDNode *Node = Op.Val; 592 593 // If this operation defines any values that cannot be represented in a 594 // register on this target, make sure to expand or promote them. 595 if (Node->getNumValues() > 1) { 596 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 597 if (getTypeAction(Node->getValueType(i)) != Legal) { 598 HandleOp(Op.getValue(i)); 599 assert(LegalizedNodes.count(Op) && 600 "Handling didn't add legal operands!"); 601 return LegalizedNodes[Op]; 602 } 603 } 604 605 // Note that LegalizeOp may be reentered even from single-use nodes, which 606 // means that we always must cache transformed nodes. 607 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 608 if (I != LegalizedNodes.end()) return I->second; 609 610 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 611 SDOperand Result = Op; 612 bool isCustom = false; 613 614 switch (Node->getOpcode()) { 615 case ISD::FrameIndex: 616 case ISD::EntryToken: 617 case ISD::Register: 618 case ISD::BasicBlock: 619 case ISD::TargetFrameIndex: 620 case ISD::TargetJumpTable: 621 case ISD::TargetConstant: 622 case ISD::TargetConstantFP: 623 case ISD::TargetConstantPool: 624 case ISD::TargetGlobalAddress: 625 case ISD::TargetExternalSymbol: 626 case ISD::VALUETYPE: 627 case ISD::SRCVALUE: 628 case ISD::STRING: 629 case ISD::CONDCODE: 630 case ISD::GLOBAL_OFFSET_TABLE: 631 // Primitives must all be legal. 632 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 633 "This must be legal!"); 634 break; 635 default: 636 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 637 // If this is a target node, legalize it by legalizing the operands then 638 // passing it through. 639 SmallVector<SDOperand, 8> Ops; 640 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 641 Ops.push_back(LegalizeOp(Node->getOperand(i))); 642 643 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 644 645 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 646 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 647 return Result.getValue(Op.ResNo); 648 } 649 // Otherwise this is an unhandled builtin node. splat. 650#ifndef NDEBUG 651 cerr << "NODE: "; Node->dump(); cerr << "\n"; 652#endif 653 assert(0 && "Do not know how to legalize this operator!"); 654 abort(); 655 case ISD::GlobalAddress: 656 case ISD::ExternalSymbol: 657 case ISD::ConstantPool: 658 case ISD::JumpTable: // Nothing to do. 659 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 660 default: assert(0 && "This action is not supported yet!"); 661 case TargetLowering::Custom: 662 Tmp1 = TLI.LowerOperation(Op, DAG); 663 if (Tmp1.Val) Result = Tmp1; 664 // FALLTHROUGH if the target doesn't want to lower this op after all. 665 case TargetLowering::Legal: 666 break; 667 } 668 break; 669 case ISD::FRAMEADDR: 670 case ISD::RETURNADDR: 671 // The only option for these nodes is to custom lower them. If the target 672 // does not custom lower them, then return zero. 673 Tmp1 = TLI.LowerOperation(Op, DAG); 674 if (Tmp1.Val) 675 Result = Tmp1; 676 else 677 Result = DAG.getConstant(0, TLI.getPointerTy()); 678 break; 679 case ISD::EXCEPTIONADDR: { 680 Tmp1 = LegalizeOp(Node->getOperand(0)); 681 MVT::ValueType VT = Node->getValueType(0); 682 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 683 default: assert(0 && "This action is not supported yet!"); 684 case TargetLowering::Expand: { 685 unsigned Reg = TLI.getExceptionAddressRegister(); 686 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo); 687 } 688 break; 689 case TargetLowering::Custom: 690 Result = TLI.LowerOperation(Op, DAG); 691 if (Result.Val) break; 692 // Fall Thru 693 case TargetLowering::Legal: 694 Result = DAG.getNode(ISD::MERGE_VALUES, VT, DAG.getConstant(0, VT), Tmp1). 695 getValue(Op.ResNo); 696 break; 697 } 698 } 699 break; 700 case ISD::EHSELECTION: { 701 Tmp1 = LegalizeOp(Node->getOperand(0)); 702 Tmp2 = LegalizeOp(Node->getOperand(1)); 703 MVT::ValueType VT = Node->getValueType(0); 704 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 705 default: assert(0 && "This action is not supported yet!"); 706 case TargetLowering::Expand: { 707 unsigned Reg = TLI.getExceptionSelectorRegister(); 708 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo); 709 } 710 break; 711 case TargetLowering::Custom: 712 Result = TLI.LowerOperation(Op, DAG); 713 if (Result.Val) break; 714 // Fall Thru 715 case TargetLowering::Legal: 716 Result = DAG.getNode(ISD::MERGE_VALUES, VT, DAG.getConstant(0, VT), Tmp2). 717 getValue(Op.ResNo); 718 break; 719 } 720 } 721 break; 722 case ISD::AssertSext: 723 case ISD::AssertZext: 724 Tmp1 = LegalizeOp(Node->getOperand(0)); 725 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 726 break; 727 case ISD::MERGE_VALUES: 728 // Legalize eliminates MERGE_VALUES nodes. 729 Result = Node->getOperand(Op.ResNo); 730 break; 731 case ISD::CopyFromReg: 732 Tmp1 = LegalizeOp(Node->getOperand(0)); 733 Result = Op.getValue(0); 734 if (Node->getNumValues() == 2) { 735 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 736 } else { 737 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 738 if (Node->getNumOperands() == 3) { 739 Tmp2 = LegalizeOp(Node->getOperand(2)); 740 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 741 } else { 742 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 743 } 744 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 745 } 746 // Since CopyFromReg produces two values, make sure to remember that we 747 // legalized both of them. 748 AddLegalizedOperand(Op.getValue(0), Result); 749 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 750 return Result.getValue(Op.ResNo); 751 case ISD::UNDEF: { 752 MVT::ValueType VT = Op.getValueType(); 753 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 754 default: assert(0 && "This action is not supported yet!"); 755 case TargetLowering::Expand: 756 if (MVT::isInteger(VT)) 757 Result = DAG.getConstant(0, VT); 758 else if (MVT::isFloatingPoint(VT)) 759 Result = DAG.getConstantFP(0, VT); 760 else 761 assert(0 && "Unknown value type!"); 762 break; 763 case TargetLowering::Legal: 764 break; 765 } 766 break; 767 } 768 769 case ISD::INTRINSIC_W_CHAIN: 770 case ISD::INTRINSIC_WO_CHAIN: 771 case ISD::INTRINSIC_VOID: { 772 SmallVector<SDOperand, 8> Ops; 773 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 774 Ops.push_back(LegalizeOp(Node->getOperand(i))); 775 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 776 777 // Allow the target to custom lower its intrinsics if it wants to. 778 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 779 TargetLowering::Custom) { 780 Tmp3 = TLI.LowerOperation(Result, DAG); 781 if (Tmp3.Val) Result = Tmp3; 782 } 783 784 if (Result.Val->getNumValues() == 1) break; 785 786 // Must have return value and chain result. 787 assert(Result.Val->getNumValues() == 2 && 788 "Cannot return more than two values!"); 789 790 // Since loads produce two values, make sure to remember that we 791 // legalized both of them. 792 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 793 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 794 return Result.getValue(Op.ResNo); 795 } 796 797 case ISD::LOCATION: 798 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 799 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 800 801 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 802 case TargetLowering::Promote: 803 default: assert(0 && "This action is not supported yet!"); 804 case TargetLowering::Expand: { 805 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 806 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 807 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 808 809 if (MMI && (useDEBUG_LOC || useLABEL)) { 810 const std::string &FName = 811 cast<StringSDNode>(Node->getOperand(3))->getValue(); 812 const std::string &DirName = 813 cast<StringSDNode>(Node->getOperand(4))->getValue(); 814 unsigned SrcFile = MMI->RecordSource(DirName, FName); 815 816 SmallVector<SDOperand, 8> Ops; 817 Ops.push_back(Tmp1); // chain 818 SDOperand LineOp = Node->getOperand(1); 819 SDOperand ColOp = Node->getOperand(2); 820 821 if (useDEBUG_LOC) { 822 Ops.push_back(LineOp); // line # 823 Ops.push_back(ColOp); // col # 824 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 825 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 826 } else { 827 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 828 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 829 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile); 830 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 831 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size()); 832 } 833 } else { 834 Result = Tmp1; // chain 835 } 836 break; 837 } 838 case TargetLowering::Legal: 839 if (Tmp1 != Node->getOperand(0) || 840 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 841 SmallVector<SDOperand, 8> Ops; 842 Ops.push_back(Tmp1); 843 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 844 Ops.push_back(Node->getOperand(1)); // line # must be legal. 845 Ops.push_back(Node->getOperand(2)); // col # must be legal. 846 } else { 847 // Otherwise promote them. 848 Ops.push_back(PromoteOp(Node->getOperand(1))); 849 Ops.push_back(PromoteOp(Node->getOperand(2))); 850 } 851 Ops.push_back(Node->getOperand(3)); // filename must be legal. 852 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 853 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 854 } 855 break; 856 } 857 break; 858 859 case ISD::DEBUG_LOC: 860 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 861 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 862 default: assert(0 && "This action is not supported yet!"); 863 case TargetLowering::Legal: 864 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 865 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 866 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 867 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 868 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 869 break; 870 } 871 break; 872 873 case ISD::LABEL: 874 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!"); 875 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 876 default: assert(0 && "This action is not supported yet!"); 877 case TargetLowering::Legal: 878 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 879 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 880 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 881 break; 882 case TargetLowering::Expand: 883 Result = LegalizeOp(Node->getOperand(0)); 884 break; 885 } 886 break; 887 888 case ISD::Constant: 889 // We know we don't need to expand constants here, constants only have one 890 // value and we check that it is fine above. 891 892 // FIXME: Maybe we should handle things like targets that don't support full 893 // 32-bit immediates? 894 break; 895 case ISD::ConstantFP: { 896 // Spill FP immediates to the constant pool if the target cannot directly 897 // codegen them. Targets often have some immediate values that can be 898 // efficiently generated into an FP register without a load. We explicitly 899 // leave these constants as ConstantFP nodes for the target to deal with. 900 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 901 902 // Check to see if this FP immediate is already legal. 903 bool isLegal = false; 904 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 905 E = TLI.legal_fpimm_end(); I != E; ++I) 906 if (CFP->isExactlyValue(*I)) { 907 isLegal = true; 908 break; 909 } 910 911 // If this is a legal constant, turn it into a TargetConstantFP node. 912 if (isLegal) { 913 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0)); 914 break; 915 } 916 917 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 918 default: assert(0 && "This action is not supported yet!"); 919 case TargetLowering::Custom: 920 Tmp3 = TLI.LowerOperation(Result, DAG); 921 if (Tmp3.Val) { 922 Result = Tmp3; 923 break; 924 } 925 // FALLTHROUGH 926 case TargetLowering::Expand: 927 Result = ExpandConstantFP(CFP, true, DAG, TLI); 928 } 929 break; 930 } 931 case ISD::TokenFactor: 932 if (Node->getNumOperands() == 2) { 933 Tmp1 = LegalizeOp(Node->getOperand(0)); 934 Tmp2 = LegalizeOp(Node->getOperand(1)); 935 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 936 } else if (Node->getNumOperands() == 3) { 937 Tmp1 = LegalizeOp(Node->getOperand(0)); 938 Tmp2 = LegalizeOp(Node->getOperand(1)); 939 Tmp3 = LegalizeOp(Node->getOperand(2)); 940 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 941 } else { 942 SmallVector<SDOperand, 8> Ops; 943 // Legalize the operands. 944 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 945 Ops.push_back(LegalizeOp(Node->getOperand(i))); 946 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 947 } 948 break; 949 950 case ISD::FORMAL_ARGUMENTS: 951 case ISD::CALL: 952 // The only option for this is to custom lower it. 953 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 954 assert(Tmp3.Val && "Target didn't custom lower this node!"); 955 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() && 956 "Lowering call/formal_arguments produced unexpected # results!"); 957 958 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 959 // remember that we legalized all of them, so it doesn't get relegalized. 960 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 961 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 962 if (Op.ResNo == i) 963 Tmp2 = Tmp1; 964 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 965 } 966 return Tmp2; 967 968 case ISD::BUILD_VECTOR: 969 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 970 default: assert(0 && "This action is not supported yet!"); 971 case TargetLowering::Custom: 972 Tmp3 = TLI.LowerOperation(Result, DAG); 973 if (Tmp3.Val) { 974 Result = Tmp3; 975 break; 976 } 977 // FALLTHROUGH 978 case TargetLowering::Expand: 979 Result = ExpandBUILD_VECTOR(Result.Val); 980 break; 981 } 982 break; 983 case ISD::INSERT_VECTOR_ELT: 984 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 985 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 986 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 987 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 988 989 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 990 Node->getValueType(0))) { 991 default: assert(0 && "This action is not supported yet!"); 992 case TargetLowering::Legal: 993 break; 994 case TargetLowering::Custom: 995 Tmp3 = TLI.LowerOperation(Result, DAG); 996 if (Tmp3.Val) { 997 Result = Tmp3; 998 break; 999 } 1000 // FALLTHROUGH 1001 case TargetLowering::Expand: { 1002 // If the insert index is a constant, codegen this as a scalar_to_vector, 1003 // then a shuffle that inserts it into the right position in the vector. 1004 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1005 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1006 Tmp1.getValueType(), Tmp2); 1007 1008 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1009 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1010 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT); 1011 1012 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 1013 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 1014 // the RHS. 1015 SmallVector<SDOperand, 8> ShufOps; 1016 for (unsigned i = 0; i != NumElts; ++i) { 1017 if (i != InsertPos->getValue()) 1018 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1019 else 1020 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1021 } 1022 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1023 &ShufOps[0], ShufOps.size()); 1024 1025 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1026 Tmp1, ScVec, ShufMask); 1027 Result = LegalizeOp(Result); 1028 break; 1029 } 1030 1031 // If the target doesn't support this, we have to spill the input vector 1032 // to a temporary stack slot, update the element, then reload it. This is 1033 // badness. We could also load the value into a vector register (either 1034 // with a "move to register" or "extload into register" instruction, then 1035 // permute it into place, if the idx is a constant and if the idx is 1036 // supported by the target. 1037 MVT::ValueType VT = Tmp1.getValueType(); 1038 MVT::ValueType EltVT = Tmp2.getValueType(); 1039 MVT::ValueType IdxVT = Tmp3.getValueType(); 1040 MVT::ValueType PtrVT = TLI.getPointerTy(); 1041 SDOperand StackPtr = CreateStackTemporary(VT); 1042 // Store the vector. 1043 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); 1044 1045 // Truncate or zero extend offset to target pointer type. 1046 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1047 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1048 // Add the offset to the index. 1049 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1050 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1051 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1052 // Store the scalar value. 1053 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); 1054 // Load the updated vector. 1055 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 1056 break; 1057 } 1058 } 1059 break; 1060 case ISD::SCALAR_TO_VECTOR: 1061 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1062 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1063 break; 1064 } 1065 1066 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1067 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1068 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1069 Node->getValueType(0))) { 1070 default: assert(0 && "This action is not supported yet!"); 1071 case TargetLowering::Legal: 1072 break; 1073 case TargetLowering::Custom: 1074 Tmp3 = TLI.LowerOperation(Result, DAG); 1075 if (Tmp3.Val) { 1076 Result = Tmp3; 1077 break; 1078 } 1079 // FALLTHROUGH 1080 case TargetLowering::Expand: 1081 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1082 break; 1083 } 1084 break; 1085 case ISD::VECTOR_SHUFFLE: 1086 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1087 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1088 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1089 1090 // Allow targets to custom lower the SHUFFLEs they support. 1091 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1092 default: assert(0 && "Unknown operation action!"); 1093 case TargetLowering::Legal: 1094 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1095 "vector shuffle should not be created if not legal!"); 1096 break; 1097 case TargetLowering::Custom: 1098 Tmp3 = TLI.LowerOperation(Result, DAG); 1099 if (Tmp3.Val) { 1100 Result = Tmp3; 1101 break; 1102 } 1103 // FALLTHROUGH 1104 case TargetLowering::Expand: { 1105 MVT::ValueType VT = Node->getValueType(0); 1106 MVT::ValueType EltVT = MVT::getVectorBaseType(VT); 1107 MVT::ValueType PtrVT = TLI.getPointerTy(); 1108 SDOperand Mask = Node->getOperand(2); 1109 unsigned NumElems = Mask.getNumOperands(); 1110 SmallVector<SDOperand,8> Ops; 1111 for (unsigned i = 0; i != NumElems; ++i) { 1112 SDOperand Arg = Mask.getOperand(i); 1113 if (Arg.getOpcode() == ISD::UNDEF) { 1114 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1115 } else { 1116 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1117 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1118 if (Idx < NumElems) 1119 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1120 DAG.getConstant(Idx, PtrVT))); 1121 else 1122 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1123 DAG.getConstant(Idx - NumElems, PtrVT))); 1124 } 1125 } 1126 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1127 break; 1128 } 1129 case TargetLowering::Promote: { 1130 // Change base type to a different vector type. 1131 MVT::ValueType OVT = Node->getValueType(0); 1132 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1133 1134 // Cast the two input vectors. 1135 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1136 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1137 1138 // Convert the shuffle mask to the right # elements. 1139 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1140 assert(Tmp3.Val && "Shuffle not legal?"); 1141 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1142 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1143 break; 1144 } 1145 } 1146 break; 1147 1148 case ISD::EXTRACT_VECTOR_ELT: 1149 Tmp1 = LegalizeOp(Node->getOperand(0)); 1150 Tmp2 = LegalizeOp(Node->getOperand(1)); 1151 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1152 1153 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, 1154 Tmp1.getValueType())) { 1155 default: assert(0 && "This action is not supported yet!"); 1156 case TargetLowering::Legal: 1157 break; 1158 case TargetLowering::Custom: 1159 Tmp3 = TLI.LowerOperation(Result, DAG); 1160 if (Tmp3.Val) { 1161 Result = Tmp3; 1162 break; 1163 } 1164 // FALLTHROUGH 1165 case TargetLowering::Expand: 1166 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1167 break; 1168 } 1169 break; 1170 1171 case ISD::VEXTRACT_VECTOR_ELT: 1172 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op)); 1173 break; 1174 1175 case ISD::CALLSEQ_START: { 1176 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1177 1178 // Recursively Legalize all of the inputs of the call end that do not lead 1179 // to this call start. This ensures that any libcalls that need be inserted 1180 // are inserted *before* the CALLSEQ_START. 1181 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1182 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1183 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1184 NodesLeadingTo); 1185 } 1186 1187 // Now that we legalized all of the inputs (which may have inserted 1188 // libcalls) create the new CALLSEQ_START node. 1189 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1190 1191 // Merge in the last call, to ensure that this call start after the last 1192 // call ended. 1193 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1194 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1195 Tmp1 = LegalizeOp(Tmp1); 1196 } 1197 1198 // Do not try to legalize the target-specific arguments (#1+). 1199 if (Tmp1 != Node->getOperand(0)) { 1200 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1201 Ops[0] = Tmp1; 1202 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1203 } 1204 1205 // Remember that the CALLSEQ_START is legalized. 1206 AddLegalizedOperand(Op.getValue(0), Result); 1207 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1208 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1209 1210 // Now that the callseq_start and all of the non-call nodes above this call 1211 // sequence have been legalized, legalize the call itself. During this 1212 // process, no libcalls can/will be inserted, guaranteeing that no calls 1213 // can overlap. 1214 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1215 SDOperand InCallSEQ = LastCALLSEQ_END; 1216 // Note that we are selecting this call! 1217 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1218 IsLegalizingCall = true; 1219 1220 // Legalize the call, starting from the CALLSEQ_END. 1221 LegalizeOp(LastCALLSEQ_END); 1222 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1223 return Result; 1224 } 1225 case ISD::CALLSEQ_END: 1226 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1227 // will cause this node to be legalized as well as handling libcalls right. 1228 if (LastCALLSEQ_END.Val != Node) { 1229 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1230 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1231 assert(I != LegalizedNodes.end() && 1232 "Legalizing the call start should have legalized this node!"); 1233 return I->second; 1234 } 1235 1236 // Otherwise, the call start has been legalized and everything is going 1237 // according to plan. Just legalize ourselves normally here. 1238 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1239 // Do not try to legalize the target-specific arguments (#1+), except for 1240 // an optional flag input. 1241 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1242 if (Tmp1 != Node->getOperand(0)) { 1243 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1244 Ops[0] = Tmp1; 1245 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1246 } 1247 } else { 1248 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1249 if (Tmp1 != Node->getOperand(0) || 1250 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1251 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1252 Ops[0] = Tmp1; 1253 Ops.back() = Tmp2; 1254 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1255 } 1256 } 1257 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1258 // This finishes up call legalization. 1259 IsLegalizingCall = false; 1260 1261 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1262 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1263 if (Node->getNumValues() == 2) 1264 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1265 return Result.getValue(Op.ResNo); 1266 case ISD::DYNAMIC_STACKALLOC: { 1267 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1268 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1269 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1270 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1271 1272 Tmp1 = Result.getValue(0); 1273 Tmp2 = Result.getValue(1); 1274 switch (TLI.getOperationAction(Node->getOpcode(), 1275 Node->getValueType(0))) { 1276 default: assert(0 && "This action is not supported yet!"); 1277 case TargetLowering::Expand: { 1278 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1279 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1280 " not tell us which reg is the stack pointer!"); 1281 SDOperand Chain = Tmp1.getOperand(0); 1282 SDOperand Size = Tmp2.getOperand(1); 1283 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0)); 1284 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value 1285 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain 1286 Tmp1 = LegalizeOp(Tmp1); 1287 Tmp2 = LegalizeOp(Tmp2); 1288 break; 1289 } 1290 case TargetLowering::Custom: 1291 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1292 if (Tmp3.Val) { 1293 Tmp1 = LegalizeOp(Tmp3); 1294 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1295 } 1296 break; 1297 case TargetLowering::Legal: 1298 break; 1299 } 1300 // Since this op produce two values, make sure to remember that we 1301 // legalized both of them. 1302 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1303 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1304 return Op.ResNo ? Tmp2 : Tmp1; 1305 } 1306 case ISD::INLINEASM: { 1307 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1308 bool Changed = false; 1309 // Legalize all of the operands of the inline asm, in case they are nodes 1310 // that need to be expanded or something. Note we skip the asm string and 1311 // all of the TargetConstant flags. 1312 SDOperand Op = LegalizeOp(Ops[0]); 1313 Changed = Op != Ops[0]; 1314 Ops[0] = Op; 1315 1316 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1317 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1318 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1319 for (++i; NumVals; ++i, --NumVals) { 1320 SDOperand Op = LegalizeOp(Ops[i]); 1321 if (Op != Ops[i]) { 1322 Changed = true; 1323 Ops[i] = Op; 1324 } 1325 } 1326 } 1327 1328 if (HasInFlag) { 1329 Op = LegalizeOp(Ops.back()); 1330 Changed |= Op != Ops.back(); 1331 Ops.back() = Op; 1332 } 1333 1334 if (Changed) 1335 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1336 1337 // INLINE asm returns a chain and flag, make sure to add both to the map. 1338 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1339 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1340 return Result.getValue(Op.ResNo); 1341 } 1342 case ISD::BR: 1343 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1344 // Ensure that libcalls are emitted before a branch. 1345 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1346 Tmp1 = LegalizeOp(Tmp1); 1347 LastCALLSEQ_END = DAG.getEntryNode(); 1348 1349 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1350 break; 1351 case ISD::BRIND: 1352 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1353 // Ensure that libcalls are emitted before a branch. 1354 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1355 Tmp1 = LegalizeOp(Tmp1); 1356 LastCALLSEQ_END = DAG.getEntryNode(); 1357 1358 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1359 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1360 case Legal: 1361 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1362 break; 1363 } 1364 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1365 break; 1366 case ISD::BR_JT: 1367 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1368 // Ensure that libcalls are emitted before a branch. 1369 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1370 Tmp1 = LegalizeOp(Tmp1); 1371 LastCALLSEQ_END = DAG.getEntryNode(); 1372 1373 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1374 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1375 1376 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1377 default: assert(0 && "This action is not supported yet!"); 1378 case TargetLowering::Legal: break; 1379 case TargetLowering::Custom: 1380 Tmp1 = TLI.LowerOperation(Result, DAG); 1381 if (Tmp1.Val) Result = Tmp1; 1382 break; 1383 case TargetLowering::Expand: { 1384 SDOperand Chain = Result.getOperand(0); 1385 SDOperand Table = Result.getOperand(1); 1386 SDOperand Index = Result.getOperand(2); 1387 1388 MVT::ValueType PTy = TLI.getPointerTy(); 1389 MachineFunction &MF = DAG.getMachineFunction(); 1390 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1391 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1392 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1393 1394 SDOperand LD; 1395 switch (EntrySize) { 1396 default: assert(0 && "Size of jump table not supported yet."); break; 1397 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; 1398 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; 1399 } 1400 1401 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1402 // For PIC, the sequence is: 1403 // BRIND(load(Jumptable + index) + RelocBase) 1404 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha 1405 SDOperand Reloc; 1406 if (TLI.usesGlobalOffsetTable()) 1407 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy); 1408 else 1409 Reloc = Table; 1410 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD; 1411 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc); 1412 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1413 } else { 1414 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD); 1415 } 1416 } 1417 } 1418 break; 1419 case ISD::BRCOND: 1420 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1421 // Ensure that libcalls are emitted before a return. 1422 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1423 Tmp1 = LegalizeOp(Tmp1); 1424 LastCALLSEQ_END = DAG.getEntryNode(); 1425 1426 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1427 case Expand: assert(0 && "It's impossible to expand bools"); 1428 case Legal: 1429 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1430 break; 1431 case Promote: 1432 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1433 1434 // The top bits of the promoted condition are not necessarily zero, ensure 1435 // that the value is properly zero extended. 1436 if (!TLI.MaskedValueIsZero(Tmp2, 1437 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1438 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1439 break; 1440 } 1441 1442 // Basic block destination (Op#2) is always legal. 1443 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1444 1445 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1446 default: assert(0 && "This action is not supported yet!"); 1447 case TargetLowering::Legal: break; 1448 case TargetLowering::Custom: 1449 Tmp1 = TLI.LowerOperation(Result, DAG); 1450 if (Tmp1.Val) Result = Tmp1; 1451 break; 1452 case TargetLowering::Expand: 1453 // Expand brcond's setcc into its constituent parts and create a BR_CC 1454 // Node. 1455 if (Tmp2.getOpcode() == ISD::SETCC) { 1456 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1457 Tmp2.getOperand(0), Tmp2.getOperand(1), 1458 Node->getOperand(2)); 1459 } else { 1460 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1461 DAG.getCondCode(ISD::SETNE), Tmp2, 1462 DAG.getConstant(0, Tmp2.getValueType()), 1463 Node->getOperand(2)); 1464 } 1465 break; 1466 } 1467 break; 1468 case ISD::BR_CC: 1469 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1470 // Ensure that libcalls are emitted before a branch. 1471 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1472 Tmp1 = LegalizeOp(Tmp1); 1473 Tmp2 = Node->getOperand(2); // LHS 1474 Tmp3 = Node->getOperand(3); // RHS 1475 Tmp4 = Node->getOperand(1); // CC 1476 1477 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1478 LastCALLSEQ_END = DAG.getEntryNode(); 1479 1480 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1481 // the LHS is a legal SETCC itself. In this case, we need to compare 1482 // the result against zero to select between true and false values. 1483 if (Tmp3.Val == 0) { 1484 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1485 Tmp4 = DAG.getCondCode(ISD::SETNE); 1486 } 1487 1488 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1489 Node->getOperand(4)); 1490 1491 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1492 default: assert(0 && "Unexpected action for BR_CC!"); 1493 case TargetLowering::Legal: break; 1494 case TargetLowering::Custom: 1495 Tmp4 = TLI.LowerOperation(Result, DAG); 1496 if (Tmp4.Val) Result = Tmp4; 1497 break; 1498 } 1499 break; 1500 case ISD::LOAD: { 1501 LoadSDNode *LD = cast<LoadSDNode>(Node); 1502 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1503 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1504 1505 ISD::LoadExtType ExtType = LD->getExtensionType(); 1506 if (ExtType == ISD::NON_EXTLOAD) { 1507 MVT::ValueType VT = Node->getValueType(0); 1508 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1509 Tmp3 = Result.getValue(0); 1510 Tmp4 = Result.getValue(1); 1511 1512 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1513 default: assert(0 && "This action is not supported yet!"); 1514 case TargetLowering::Legal: break; 1515 case TargetLowering::Custom: 1516 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1517 if (Tmp1.Val) { 1518 Tmp3 = LegalizeOp(Tmp1); 1519 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1520 } 1521 break; 1522 case TargetLowering::Promote: { 1523 // Only promote a load of vector type to another. 1524 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1525 // Change base type to a different vector type. 1526 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1527 1528 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1529 LD->getSrcValueOffset()); 1530 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1531 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1532 break; 1533 } 1534 } 1535 // Since loads produce two values, make sure to remember that we 1536 // legalized both of them. 1537 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1538 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1539 return Op.ResNo ? Tmp4 : Tmp3; 1540 } else { 1541 MVT::ValueType SrcVT = LD->getLoadedVT(); 1542 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1543 default: assert(0 && "This action is not supported yet!"); 1544 case TargetLowering::Promote: 1545 assert(SrcVT == MVT::i1 && 1546 "Can only promote extending LOAD from i1 -> i8!"); 1547 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1548 LD->getSrcValue(), LD->getSrcValueOffset(), 1549 MVT::i8); 1550 Tmp1 = Result.getValue(0); 1551 Tmp2 = Result.getValue(1); 1552 break; 1553 case TargetLowering::Custom: 1554 isCustom = true; 1555 // FALLTHROUGH 1556 case TargetLowering::Legal: 1557 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1558 Tmp1 = Result.getValue(0); 1559 Tmp2 = Result.getValue(1); 1560 1561 if (isCustom) { 1562 Tmp3 = TLI.LowerOperation(Result, DAG); 1563 if (Tmp3.Val) { 1564 Tmp1 = LegalizeOp(Tmp3); 1565 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1566 } 1567 } 1568 break; 1569 case TargetLowering::Expand: 1570 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1571 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1572 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1573 LD->getSrcValueOffset()); 1574 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1575 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1576 Tmp2 = LegalizeOp(Load.getValue(1)); 1577 break; 1578 } 1579 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1580 // Turn the unsupported load into an EXTLOAD followed by an explicit 1581 // zero/sign extend inreg. 1582 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1583 Tmp1, Tmp2, LD->getSrcValue(), 1584 LD->getSrcValueOffset(), SrcVT); 1585 SDOperand ValRes; 1586 if (ExtType == ISD::SEXTLOAD) 1587 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1588 Result, DAG.getValueType(SrcVT)); 1589 else 1590 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1591 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1592 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1593 break; 1594 } 1595 // Since loads produce two values, make sure to remember that we legalized 1596 // both of them. 1597 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1598 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1599 return Op.ResNo ? Tmp2 : Tmp1; 1600 } 1601 } 1602 case ISD::EXTRACT_ELEMENT: { 1603 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1604 switch (getTypeAction(OpTy)) { 1605 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1606 case Legal: 1607 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1608 // 1 -> Hi 1609 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1610 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1611 TLI.getShiftAmountTy())); 1612 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1613 } else { 1614 // 0 -> Lo 1615 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1616 Node->getOperand(0)); 1617 } 1618 break; 1619 case Expand: 1620 // Get both the low and high parts. 1621 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1622 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1623 Result = Tmp2; // 1 -> Hi 1624 else 1625 Result = Tmp1; // 0 -> Lo 1626 break; 1627 } 1628 break; 1629 } 1630 1631 case ISD::CopyToReg: 1632 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1633 1634 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1635 "Register type must be legal!"); 1636 // Legalize the incoming value (must be a legal type). 1637 Tmp2 = LegalizeOp(Node->getOperand(2)); 1638 if (Node->getNumValues() == 1) { 1639 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1640 } else { 1641 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1642 if (Node->getNumOperands() == 4) { 1643 Tmp3 = LegalizeOp(Node->getOperand(3)); 1644 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1645 Tmp3); 1646 } else { 1647 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1648 } 1649 1650 // Since this produces two values, make sure to remember that we legalized 1651 // both of them. 1652 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1653 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1654 return Result; 1655 } 1656 break; 1657 1658 case ISD::RET: 1659 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1660 1661 // Ensure that libcalls are emitted before a return. 1662 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1663 Tmp1 = LegalizeOp(Tmp1); 1664 LastCALLSEQ_END = DAG.getEntryNode(); 1665 1666 switch (Node->getNumOperands()) { 1667 case 3: // ret val 1668 Tmp2 = Node->getOperand(1); 1669 Tmp3 = Node->getOperand(2); // Signness 1670 switch (getTypeAction(Tmp2.getValueType())) { 1671 case Legal: 1672 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1673 break; 1674 case Expand: 1675 if (Tmp2.getValueType() != MVT::Vector) { 1676 SDOperand Lo, Hi; 1677 ExpandOp(Tmp2, Lo, Hi); 1678 1679 // Big endian systems want the hi reg first. 1680 if (!TLI.isLittleEndian()) 1681 std::swap(Lo, Hi); 1682 1683 if (Hi.Val) 1684 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1685 else 1686 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 1687 Result = LegalizeOp(Result); 1688 } else { 1689 SDNode *InVal = Tmp2.Val; 1690 unsigned NumElems = 1691 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1692 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1693 1694 // Figure out if there is a Packed type corresponding to this Vector 1695 // type. If so, convert to the vector type. 1696 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1697 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1698 // Turn this into a return of the vector type. 1699 Tmp2 = PackVectorOp(Tmp2, TVT); 1700 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1701 } else if (NumElems == 1) { 1702 // Turn this into a return of the scalar type. 1703 Tmp2 = PackVectorOp(Tmp2, EVT); 1704 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1705 1706 // FIXME: Returns of gcc generic vectors smaller than a legal type 1707 // should be returned in integer registers! 1708 1709 // The scalarized value type may not be legal, e.g. it might require 1710 // promotion or expansion. Relegalize the return. 1711 Result = LegalizeOp(Result); 1712 } else { 1713 // FIXME: Returns of gcc generic vectors larger than a legal vector 1714 // type should be returned by reference! 1715 SDOperand Lo, Hi; 1716 SplitVectorOp(Tmp2, Lo, Hi); 1717 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1718 Result = LegalizeOp(Result); 1719 } 1720 } 1721 break; 1722 case Promote: 1723 Tmp2 = PromoteOp(Node->getOperand(1)); 1724 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1725 Result = LegalizeOp(Result); 1726 break; 1727 } 1728 break; 1729 case 1: // ret void 1730 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1731 break; 1732 default: { // ret <values> 1733 SmallVector<SDOperand, 8> NewValues; 1734 NewValues.push_back(Tmp1); 1735 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 1736 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1737 case Legal: 1738 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1739 NewValues.push_back(Node->getOperand(i+1)); 1740 break; 1741 case Expand: { 1742 SDOperand Lo, Hi; 1743 assert(Node->getOperand(i).getValueType() != MVT::Vector && 1744 "FIXME: TODO: implement returning non-legal vector types!"); 1745 ExpandOp(Node->getOperand(i), Lo, Hi); 1746 NewValues.push_back(Lo); 1747 NewValues.push_back(Node->getOperand(i+1)); 1748 if (Hi.Val) { 1749 NewValues.push_back(Hi); 1750 NewValues.push_back(Node->getOperand(i+1)); 1751 } 1752 break; 1753 } 1754 case Promote: 1755 assert(0 && "Can't promote multiple return value yet!"); 1756 } 1757 1758 if (NewValues.size() == Node->getNumOperands()) 1759 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 1760 else 1761 Result = DAG.getNode(ISD::RET, MVT::Other, 1762 &NewValues[0], NewValues.size()); 1763 break; 1764 } 1765 } 1766 1767 if (Result.getOpcode() == ISD::RET) { 1768 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 1769 default: assert(0 && "This action is not supported yet!"); 1770 case TargetLowering::Legal: break; 1771 case TargetLowering::Custom: 1772 Tmp1 = TLI.LowerOperation(Result, DAG); 1773 if (Tmp1.Val) Result = Tmp1; 1774 break; 1775 } 1776 } 1777 break; 1778 case ISD::STORE: { 1779 StoreSDNode *ST = cast<StoreSDNode>(Node); 1780 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1781 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1782 1783 if (!ST->isTruncatingStore()) { 1784 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1785 // FIXME: We shouldn't do this for TargetConstantFP's. 1786 // FIXME: move this to the DAG Combiner! Note that we can't regress due 1787 // to phase ordering between legalized code and the dag combiner. This 1788 // probably means that we need to integrate dag combiner and legalizer 1789 // together. 1790 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 1791 if (CFP->getValueType(0) == MVT::f32) { 1792 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 1793 } else { 1794 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1795 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 1796 } 1797 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1798 ST->getSrcValueOffset()); 1799 break; 1800 } 1801 1802 switch (getTypeAction(ST->getStoredVT())) { 1803 case Legal: { 1804 Tmp3 = LegalizeOp(ST->getValue()); 1805 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1806 ST->getOffset()); 1807 1808 MVT::ValueType VT = Tmp3.getValueType(); 1809 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1810 default: assert(0 && "This action is not supported yet!"); 1811 case TargetLowering::Legal: break; 1812 case TargetLowering::Custom: 1813 Tmp1 = TLI.LowerOperation(Result, DAG); 1814 if (Tmp1.Val) Result = Tmp1; 1815 break; 1816 case TargetLowering::Promote: 1817 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 1818 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 1819 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1820 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 1821 ST->getSrcValue(), ST->getSrcValueOffset()); 1822 break; 1823 } 1824 break; 1825 } 1826 case Promote: 1827 // Truncate the value and store the result. 1828 Tmp3 = PromoteOp(ST->getValue()); 1829 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1830 ST->getSrcValueOffset(), ST->getStoredVT()); 1831 break; 1832 1833 case Expand: 1834 unsigned IncrementSize = 0; 1835 SDOperand Lo, Hi; 1836 1837 // If this is a vector type, then we have to calculate the increment as 1838 // the product of the element size in bytes, and the number of elements 1839 // in the high half of the vector. 1840 if (ST->getValue().getValueType() == MVT::Vector) { 1841 SDNode *InVal = ST->getValue().Val; 1842 unsigned NumElems = 1843 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1844 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1845 1846 // Figure out if there is a Packed type corresponding to this Vector 1847 // type. If so, convert to the vector type. 1848 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1849 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1850 // Turn this into a normal store of the vector type. 1851 Tmp3 = PackVectorOp(Node->getOperand(1), TVT); 1852 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1853 ST->getSrcValueOffset()); 1854 Result = LegalizeOp(Result); 1855 break; 1856 } else if (NumElems == 1) { 1857 // Turn this into a normal store of the scalar type. 1858 Tmp3 = PackVectorOp(Node->getOperand(1), EVT); 1859 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1860 ST->getSrcValueOffset()); 1861 // The scalarized value type may not be legal, e.g. it might require 1862 // promotion or expansion. Relegalize the scalar store. 1863 Result = LegalizeOp(Result); 1864 break; 1865 } else { 1866 SplitVectorOp(Node->getOperand(1), Lo, Hi); 1867 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 1868 } 1869 } else { 1870 ExpandOp(Node->getOperand(1), Lo, Hi); 1871 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 1872 1873 if (!TLI.isLittleEndian()) 1874 std::swap(Lo, Hi); 1875 } 1876 1877 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 1878 ST->getSrcValueOffset()); 1879 1880 if (Hi.Val == NULL) { 1881 // Must be int <-> float one-to-one expansion. 1882 Result = Lo; 1883 break; 1884 } 1885 1886 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1887 getIntPtrConstant(IncrementSize)); 1888 assert(isTypeLegal(Tmp2.getValueType()) && 1889 "Pointers must be legal!"); 1890 // FIXME: This sets the srcvalue of both halves to be the same, which is 1891 // wrong. 1892 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 1893 ST->getSrcValueOffset()); 1894 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1895 break; 1896 } 1897 } else { 1898 // Truncating store 1899 assert(isTypeLegal(ST->getValue().getValueType()) && 1900 "Cannot handle illegal TRUNCSTORE yet!"); 1901 Tmp3 = LegalizeOp(ST->getValue()); 1902 1903 // The only promote case we handle is TRUNCSTORE:i1 X into 1904 // -> TRUNCSTORE:i8 (and X, 1) 1905 if (ST->getStoredVT() == MVT::i1 && 1906 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) { 1907 // Promote the bool to a mask then store. 1908 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3, 1909 DAG.getConstant(1, Tmp3.getValueType())); 1910 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 1911 ST->getSrcValueOffset(), MVT::i8); 1912 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1913 Tmp2 != ST->getBasePtr()) { 1914 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1915 ST->getOffset()); 1916 } 1917 1918 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT(); 1919 switch (TLI.getStoreXAction(StVT)) { 1920 default: assert(0 && "This action is not supported yet!"); 1921 case TargetLowering::Legal: break; 1922 case TargetLowering::Custom: 1923 Tmp1 = TLI.LowerOperation(Result, DAG); 1924 if (Tmp1.Val) Result = Tmp1; 1925 break; 1926 } 1927 } 1928 break; 1929 } 1930 case ISD::PCMARKER: 1931 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1932 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1933 break; 1934 case ISD::STACKSAVE: 1935 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1936 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1937 Tmp1 = Result.getValue(0); 1938 Tmp2 = Result.getValue(1); 1939 1940 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 1941 default: assert(0 && "This action is not supported yet!"); 1942 case TargetLowering::Legal: break; 1943 case TargetLowering::Custom: 1944 Tmp3 = TLI.LowerOperation(Result, DAG); 1945 if (Tmp3.Val) { 1946 Tmp1 = LegalizeOp(Tmp3); 1947 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1948 } 1949 break; 1950 case TargetLowering::Expand: 1951 // Expand to CopyFromReg if the target set 1952 // StackPointerRegisterToSaveRestore. 1953 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1954 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 1955 Node->getValueType(0)); 1956 Tmp2 = Tmp1.getValue(1); 1957 } else { 1958 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 1959 Tmp2 = Node->getOperand(0); 1960 } 1961 break; 1962 } 1963 1964 // Since stacksave produce two values, make sure to remember that we 1965 // legalized both of them. 1966 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1967 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1968 return Op.ResNo ? Tmp2 : Tmp1; 1969 1970 case ISD::STACKRESTORE: 1971 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1972 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1973 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1974 1975 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 1976 default: assert(0 && "This action is not supported yet!"); 1977 case TargetLowering::Legal: break; 1978 case TargetLowering::Custom: 1979 Tmp1 = TLI.LowerOperation(Result, DAG); 1980 if (Tmp1.Val) Result = Tmp1; 1981 break; 1982 case TargetLowering::Expand: 1983 // Expand to CopyToReg if the target set 1984 // StackPointerRegisterToSaveRestore. 1985 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1986 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 1987 } else { 1988 Result = Tmp1; 1989 } 1990 break; 1991 } 1992 break; 1993 1994 case ISD::READCYCLECOUNTER: 1995 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1996 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1997 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 1998 Node->getValueType(0))) { 1999 default: assert(0 && "This action is not supported yet!"); 2000 case TargetLowering::Legal: 2001 Tmp1 = Result.getValue(0); 2002 Tmp2 = Result.getValue(1); 2003 break; 2004 case TargetLowering::Custom: 2005 Result = TLI.LowerOperation(Result, DAG); 2006 Tmp1 = LegalizeOp(Result.getValue(0)); 2007 Tmp2 = LegalizeOp(Result.getValue(1)); 2008 break; 2009 } 2010 2011 // Since rdcc produce two values, make sure to remember that we legalized 2012 // both of them. 2013 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2014 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2015 return Result; 2016 2017 case ISD::SELECT: 2018 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2019 case Expand: assert(0 && "It's impossible to expand bools"); 2020 case Legal: 2021 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2022 break; 2023 case Promote: 2024 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2025 // Make sure the condition is either zero or one. 2026 if (!TLI.MaskedValueIsZero(Tmp1, 2027 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 2028 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2029 break; 2030 } 2031 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2032 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2033 2034 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2035 2036 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2037 default: assert(0 && "This action is not supported yet!"); 2038 case TargetLowering::Legal: break; 2039 case TargetLowering::Custom: { 2040 Tmp1 = TLI.LowerOperation(Result, DAG); 2041 if (Tmp1.Val) Result = Tmp1; 2042 break; 2043 } 2044 case TargetLowering::Expand: 2045 if (Tmp1.getOpcode() == ISD::SETCC) { 2046 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2047 Tmp2, Tmp3, 2048 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2049 } else { 2050 Result = DAG.getSelectCC(Tmp1, 2051 DAG.getConstant(0, Tmp1.getValueType()), 2052 Tmp2, Tmp3, ISD::SETNE); 2053 } 2054 break; 2055 case TargetLowering::Promote: { 2056 MVT::ValueType NVT = 2057 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2058 unsigned ExtOp, TruncOp; 2059 if (MVT::isVector(Tmp2.getValueType())) { 2060 ExtOp = ISD::BIT_CONVERT; 2061 TruncOp = ISD::BIT_CONVERT; 2062 } else if (MVT::isInteger(Tmp2.getValueType())) { 2063 ExtOp = ISD::ANY_EXTEND; 2064 TruncOp = ISD::TRUNCATE; 2065 } else { 2066 ExtOp = ISD::FP_EXTEND; 2067 TruncOp = ISD::FP_ROUND; 2068 } 2069 // Promote each of the values to the new type. 2070 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2071 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2072 // Perform the larger operation, then round down. 2073 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2074 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2075 break; 2076 } 2077 } 2078 break; 2079 case ISD::SELECT_CC: { 2080 Tmp1 = Node->getOperand(0); // LHS 2081 Tmp2 = Node->getOperand(1); // RHS 2082 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2083 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2084 SDOperand CC = Node->getOperand(4); 2085 2086 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2087 2088 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2089 // the LHS is a legal SETCC itself. In this case, we need to compare 2090 // the result against zero to select between true and false values. 2091 if (Tmp2.Val == 0) { 2092 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2093 CC = DAG.getCondCode(ISD::SETNE); 2094 } 2095 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2096 2097 // Everything is legal, see if we should expand this op or something. 2098 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2099 default: assert(0 && "This action is not supported yet!"); 2100 case TargetLowering::Legal: break; 2101 case TargetLowering::Custom: 2102 Tmp1 = TLI.LowerOperation(Result, DAG); 2103 if (Tmp1.Val) Result = Tmp1; 2104 break; 2105 } 2106 break; 2107 } 2108 case ISD::SETCC: 2109 Tmp1 = Node->getOperand(0); 2110 Tmp2 = Node->getOperand(1); 2111 Tmp3 = Node->getOperand(2); 2112 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2113 2114 // If we had to Expand the SetCC operands into a SELECT node, then it may 2115 // not always be possible to return a true LHS & RHS. In this case, just 2116 // return the value we legalized, returned in the LHS 2117 if (Tmp2.Val == 0) { 2118 Result = Tmp1; 2119 break; 2120 } 2121 2122 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2123 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2124 case TargetLowering::Custom: 2125 isCustom = true; 2126 // FALLTHROUGH. 2127 case TargetLowering::Legal: 2128 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2129 if (isCustom) { 2130 Tmp4 = TLI.LowerOperation(Result, DAG); 2131 if (Tmp4.Val) Result = Tmp4; 2132 } 2133 break; 2134 case TargetLowering::Promote: { 2135 // First step, figure out the appropriate operation to use. 2136 // Allow SETCC to not be supported for all legal data types 2137 // Mostly this targets FP 2138 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2139 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2140 2141 // Scan for the appropriate larger type to use. 2142 while (1) { 2143 NewInTy = (MVT::ValueType)(NewInTy+1); 2144 2145 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2146 "Fell off of the edge of the integer world"); 2147 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2148 "Fell off of the edge of the floating point world"); 2149 2150 // If the target supports SETCC of this type, use it. 2151 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2152 break; 2153 } 2154 if (MVT::isInteger(NewInTy)) 2155 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2156 else { 2157 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2158 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2159 } 2160 Tmp1 = LegalizeOp(Tmp1); 2161 Tmp2 = LegalizeOp(Tmp2); 2162 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2163 Result = LegalizeOp(Result); 2164 break; 2165 } 2166 case TargetLowering::Expand: 2167 // Expand a setcc node into a select_cc of the same condition, lhs, and 2168 // rhs that selects between const 1 (true) and const 0 (false). 2169 MVT::ValueType VT = Node->getValueType(0); 2170 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2171 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2172 Tmp3); 2173 break; 2174 } 2175 break; 2176 case ISD::MEMSET: 2177 case ISD::MEMCPY: 2178 case ISD::MEMMOVE: { 2179 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2180 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2181 2182 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2183 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2184 case Expand: assert(0 && "Cannot expand a byte!"); 2185 case Legal: 2186 Tmp3 = LegalizeOp(Node->getOperand(2)); 2187 break; 2188 case Promote: 2189 Tmp3 = PromoteOp(Node->getOperand(2)); 2190 break; 2191 } 2192 } else { 2193 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2194 } 2195 2196 SDOperand Tmp4; 2197 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2198 case Expand: { 2199 // Length is too big, just take the lo-part of the length. 2200 SDOperand HiPart; 2201 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2202 break; 2203 } 2204 case Legal: 2205 Tmp4 = LegalizeOp(Node->getOperand(3)); 2206 break; 2207 case Promote: 2208 Tmp4 = PromoteOp(Node->getOperand(3)); 2209 break; 2210 } 2211 2212 SDOperand Tmp5; 2213 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2214 case Expand: assert(0 && "Cannot expand this yet!"); 2215 case Legal: 2216 Tmp5 = LegalizeOp(Node->getOperand(4)); 2217 break; 2218 case Promote: 2219 Tmp5 = PromoteOp(Node->getOperand(4)); 2220 break; 2221 } 2222 2223 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2224 default: assert(0 && "This action not implemented for this operation!"); 2225 case TargetLowering::Custom: 2226 isCustom = true; 2227 // FALLTHROUGH 2228 case TargetLowering::Legal: 2229 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 2230 if (isCustom) { 2231 Tmp1 = TLI.LowerOperation(Result, DAG); 2232 if (Tmp1.Val) Result = Tmp1; 2233 } 2234 break; 2235 case TargetLowering::Expand: { 2236 // Otherwise, the target does not support this operation. Lower the 2237 // operation to an explicit libcall as appropriate. 2238 MVT::ValueType IntPtr = TLI.getPointerTy(); 2239 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2240 TargetLowering::ArgListTy Args; 2241 TargetLowering::ArgListEntry Entry; 2242 2243 const char *FnName = 0; 2244 if (Node->getOpcode() == ISD::MEMSET) { 2245 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; 2246 Args.push_back(Entry); 2247 // Extend the (previously legalized) ubyte argument to be an int value 2248 // for the call. 2249 if (Tmp3.getValueType() > MVT::i32) 2250 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2251 else 2252 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2253 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 2254 Args.push_back(Entry); 2255 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false; 2256 Args.push_back(Entry); 2257 2258 FnName = "memset"; 2259 } else if (Node->getOpcode() == ISD::MEMCPY || 2260 Node->getOpcode() == ISD::MEMMOVE) { 2261 Entry.Ty = IntPtrTy; 2262 Entry.Node = Tmp2; Args.push_back(Entry); 2263 Entry.Node = Tmp3; Args.push_back(Entry); 2264 Entry.Node = Tmp4; Args.push_back(Entry); 2265 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2266 } else { 2267 assert(0 && "Unknown op!"); 2268 } 2269 2270 std::pair<SDOperand,SDOperand> CallResult = 2271 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 2272 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2273 Result = CallResult.second; 2274 break; 2275 } 2276 } 2277 break; 2278 } 2279 2280 case ISD::SHL_PARTS: 2281 case ISD::SRA_PARTS: 2282 case ISD::SRL_PARTS: { 2283 SmallVector<SDOperand, 8> Ops; 2284 bool Changed = false; 2285 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2286 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2287 Changed |= Ops.back() != Node->getOperand(i); 2288 } 2289 if (Changed) 2290 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2291 2292 switch (TLI.getOperationAction(Node->getOpcode(), 2293 Node->getValueType(0))) { 2294 default: assert(0 && "This action is not supported yet!"); 2295 case TargetLowering::Legal: break; 2296 case TargetLowering::Custom: 2297 Tmp1 = TLI.LowerOperation(Result, DAG); 2298 if (Tmp1.Val) { 2299 SDOperand Tmp2, RetVal(0, 0); 2300 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2301 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2302 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2303 if (i == Op.ResNo) 2304 RetVal = Tmp2; 2305 } 2306 assert(RetVal.Val && "Illegal result number"); 2307 return RetVal; 2308 } 2309 break; 2310 } 2311 2312 // Since these produce multiple values, make sure to remember that we 2313 // legalized all of them. 2314 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2315 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2316 return Result.getValue(Op.ResNo); 2317 } 2318 2319 // Binary operators 2320 case ISD::ADD: 2321 case ISD::SUB: 2322 case ISD::MUL: 2323 case ISD::MULHS: 2324 case ISD::MULHU: 2325 case ISD::UDIV: 2326 case ISD::SDIV: 2327 case ISD::AND: 2328 case ISD::OR: 2329 case ISD::XOR: 2330 case ISD::SHL: 2331 case ISD::SRL: 2332 case ISD::SRA: 2333 case ISD::FADD: 2334 case ISD::FSUB: 2335 case ISD::FMUL: 2336 case ISD::FDIV: 2337 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2338 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2339 case Expand: assert(0 && "Not possible"); 2340 case Legal: 2341 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2342 break; 2343 case Promote: 2344 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2345 break; 2346 } 2347 2348 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2349 2350 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2351 default: assert(0 && "BinOp legalize operation not supported"); 2352 case TargetLowering::Legal: break; 2353 case TargetLowering::Custom: 2354 Tmp1 = TLI.LowerOperation(Result, DAG); 2355 if (Tmp1.Val) Result = Tmp1; 2356 break; 2357 case TargetLowering::Expand: { 2358 if (Node->getValueType(0) == MVT::i32) { 2359 switch (Node->getOpcode()) { 2360 default: assert(0 && "Do not know how to expand this integer BinOp!"); 2361 case ISD::UDIV: 2362 case ISD::SDIV: 2363 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV 2364 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 2365 SDOperand Dummy; 2366 bool isSigned = Node->getOpcode() == ISD::SDIV; 2367 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2368 }; 2369 break; 2370 } 2371 2372 assert(MVT::isVector(Node->getValueType(0)) && 2373 "Cannot expand this binary operator!"); 2374 // Expand the operation into a bunch of nasty scalar code. 2375 SmallVector<SDOperand, 8> Ops; 2376 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0)); 2377 MVT::ValueType PtrVT = TLI.getPointerTy(); 2378 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0)); 2379 i != e; ++i) { 2380 SDOperand Idx = DAG.getConstant(i, PtrVT); 2381 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx); 2382 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx); 2383 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS)); 2384 } 2385 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), 2386 &Ops[0], Ops.size()); 2387 break; 2388 } 2389 case TargetLowering::Promote: { 2390 switch (Node->getOpcode()) { 2391 default: assert(0 && "Do not know how to promote this BinOp!"); 2392 case ISD::AND: 2393 case ISD::OR: 2394 case ISD::XOR: { 2395 MVT::ValueType OVT = Node->getValueType(0); 2396 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2397 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2398 // Bit convert each of the values to the new type. 2399 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2400 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2401 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2402 // Bit convert the result back the original type. 2403 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2404 break; 2405 } 2406 } 2407 } 2408 } 2409 break; 2410 2411 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2412 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2413 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2414 case Expand: assert(0 && "Not possible"); 2415 case Legal: 2416 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2417 break; 2418 case Promote: 2419 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2420 break; 2421 } 2422 2423 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2424 2425 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2426 default: assert(0 && "Operation not supported"); 2427 case TargetLowering::Custom: 2428 Tmp1 = TLI.LowerOperation(Result, DAG); 2429 if (Tmp1.Val) Result = Tmp1; 2430 break; 2431 case TargetLowering::Legal: break; 2432 case TargetLowering::Expand: { 2433 // If this target supports fabs/fneg natively and select is cheap, 2434 // do this efficiently. 2435 if (!TLI.isSelectExpensive() && 2436 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 2437 TargetLowering::Legal && 2438 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 2439 TargetLowering::Legal) { 2440 // Get the sign bit of the RHS. 2441 MVT::ValueType IVT = 2442 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2443 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2444 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2445 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2446 // Get the absolute value of the result. 2447 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2448 // Select between the nabs and abs value based on the sign bit of 2449 // the input. 2450 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2451 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2452 AbsVal), 2453 AbsVal); 2454 Result = LegalizeOp(Result); 2455 break; 2456 } 2457 2458 // Otherwise, do bitwise ops! 2459 MVT::ValueType NVT = 2460 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 2461 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 2462 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 2463 Result = LegalizeOp(Result); 2464 break; 2465 } 2466 } 2467 break; 2468 2469 case ISD::ADDC: 2470 case ISD::SUBC: 2471 Tmp1 = LegalizeOp(Node->getOperand(0)); 2472 Tmp2 = LegalizeOp(Node->getOperand(1)); 2473 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2474 // Since this produces two values, make sure to remember that we legalized 2475 // both of them. 2476 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2477 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2478 return Result; 2479 2480 case ISD::ADDE: 2481 case ISD::SUBE: 2482 Tmp1 = LegalizeOp(Node->getOperand(0)); 2483 Tmp2 = LegalizeOp(Node->getOperand(1)); 2484 Tmp3 = LegalizeOp(Node->getOperand(2)); 2485 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2486 // Since this produces two values, make sure to remember that we legalized 2487 // both of them. 2488 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2489 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2490 return Result; 2491 2492 case ISD::BUILD_PAIR: { 2493 MVT::ValueType PairTy = Node->getValueType(0); 2494 // TODO: handle the case where the Lo and Hi operands are not of legal type 2495 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2496 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2497 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2498 case TargetLowering::Promote: 2499 case TargetLowering::Custom: 2500 assert(0 && "Cannot promote/custom this yet!"); 2501 case TargetLowering::Legal: 2502 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2503 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2504 break; 2505 case TargetLowering::Expand: 2506 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2507 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2508 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2509 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2510 TLI.getShiftAmountTy())); 2511 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2512 break; 2513 } 2514 break; 2515 } 2516 2517 case ISD::UREM: 2518 case ISD::SREM: 2519 case ISD::FREM: 2520 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2521 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2522 2523 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2524 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2525 case TargetLowering::Custom: 2526 isCustom = true; 2527 // FALLTHROUGH 2528 case TargetLowering::Legal: 2529 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2530 if (isCustom) { 2531 Tmp1 = TLI.LowerOperation(Result, DAG); 2532 if (Tmp1.Val) Result = Tmp1; 2533 } 2534 break; 2535 case TargetLowering::Expand: 2536 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2537 bool isSigned = DivOpc == ISD::SDIV; 2538 if (MVT::isInteger(Node->getValueType(0))) { 2539 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) == 2540 TargetLowering::Legal) { 2541 // X % Y -> X-X/Y*Y 2542 MVT::ValueType VT = Node->getValueType(0); 2543 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 2544 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2545 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2546 } else { 2547 assert(Node->getValueType(0) == MVT::i32 && 2548 "Cannot expand this binary operator!"); 2549 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 2550 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 2551 SDOperand Dummy; 2552 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2553 } 2554 } else { 2555 // Floating point mod -> fmod libcall. 2556 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 2557 ? RTLIB::REM_F32 : RTLIB::REM_F64; 2558 SDOperand Dummy; 2559 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2560 false/*sign irrelevant*/, Dummy); 2561 } 2562 break; 2563 } 2564 break; 2565 case ISD::VAARG: { 2566 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2567 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2568 2569 MVT::ValueType VT = Node->getValueType(0); 2570 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2571 default: assert(0 && "This action is not supported yet!"); 2572 case TargetLowering::Custom: 2573 isCustom = true; 2574 // FALLTHROUGH 2575 case TargetLowering::Legal: 2576 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2577 Result = Result.getValue(0); 2578 Tmp1 = Result.getValue(1); 2579 2580 if (isCustom) { 2581 Tmp2 = TLI.LowerOperation(Result, DAG); 2582 if (Tmp2.Val) { 2583 Result = LegalizeOp(Tmp2); 2584 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2585 } 2586 } 2587 break; 2588 case TargetLowering::Expand: { 2589 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 2590 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2591 SV->getValue(), SV->getOffset()); 2592 // Increment the pointer, VAList, to the next vaarg 2593 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2594 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2595 TLI.getPointerTy())); 2596 // Store the incremented VAList to the legalized pointer 2597 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 2598 SV->getOffset()); 2599 // Load the actual argument out of the pointer VAList 2600 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 2601 Tmp1 = LegalizeOp(Result.getValue(1)); 2602 Result = LegalizeOp(Result); 2603 break; 2604 } 2605 } 2606 // Since VAARG produces two values, make sure to remember that we 2607 // legalized both of them. 2608 AddLegalizedOperand(SDOperand(Node, 0), Result); 2609 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 2610 return Op.ResNo ? Tmp1 : Result; 2611 } 2612 2613 case ISD::VACOPY: 2614 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2615 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 2616 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 2617 2618 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 2619 default: assert(0 && "This action is not supported yet!"); 2620 case TargetLowering::Custom: 2621 isCustom = true; 2622 // FALLTHROUGH 2623 case TargetLowering::Legal: 2624 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 2625 Node->getOperand(3), Node->getOperand(4)); 2626 if (isCustom) { 2627 Tmp1 = TLI.LowerOperation(Result, DAG); 2628 if (Tmp1.Val) Result = Tmp1; 2629 } 2630 break; 2631 case TargetLowering::Expand: 2632 // This defaults to loading a pointer from the input and storing it to the 2633 // output, returning the chain. 2634 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 2635 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); 2636 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 2637 SVD->getOffset()); 2638 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), 2639 SVS->getOffset()); 2640 break; 2641 } 2642 break; 2643 2644 case ISD::VAEND: 2645 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2646 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2647 2648 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 2649 default: assert(0 && "This action is not supported yet!"); 2650 case TargetLowering::Custom: 2651 isCustom = true; 2652 // FALLTHROUGH 2653 case TargetLowering::Legal: 2654 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2655 if (isCustom) { 2656 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 2657 if (Tmp1.Val) Result = Tmp1; 2658 } 2659 break; 2660 case TargetLowering::Expand: 2661 Result = Tmp1; // Default to a no-op, return the chain 2662 break; 2663 } 2664 break; 2665 2666 case ISD::VASTART: 2667 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2668 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2669 2670 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2671 2672 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 2673 default: assert(0 && "This action is not supported yet!"); 2674 case TargetLowering::Legal: break; 2675 case TargetLowering::Custom: 2676 Tmp1 = TLI.LowerOperation(Result, DAG); 2677 if (Tmp1.Val) Result = Tmp1; 2678 break; 2679 } 2680 break; 2681 2682 case ISD::ROTL: 2683 case ISD::ROTR: 2684 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2685 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2686 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2687 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2688 default: 2689 assert(0 && "ROTL/ROTR legalize operation not supported"); 2690 break; 2691 case TargetLowering::Legal: 2692 break; 2693 case TargetLowering::Custom: 2694 Tmp1 = TLI.LowerOperation(Result, DAG); 2695 if (Tmp1.Val) Result = Tmp1; 2696 break; 2697 case TargetLowering::Promote: 2698 assert(0 && "Do not know how to promote ROTL/ROTR"); 2699 break; 2700 case TargetLowering::Expand: 2701 assert(0 && "Do not know how to expand ROTL/ROTR"); 2702 break; 2703 } 2704 break; 2705 2706 case ISD::BSWAP: 2707 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2708 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2709 case TargetLowering::Custom: 2710 assert(0 && "Cannot custom legalize this yet!"); 2711 case TargetLowering::Legal: 2712 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2713 break; 2714 case TargetLowering::Promote: { 2715 MVT::ValueType OVT = Tmp1.getValueType(); 2716 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2717 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT); 2718 2719 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2720 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2721 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2722 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2723 break; 2724 } 2725 case TargetLowering::Expand: 2726 Result = ExpandBSWAP(Tmp1); 2727 break; 2728 } 2729 break; 2730 2731 case ISD::CTPOP: 2732 case ISD::CTTZ: 2733 case ISD::CTLZ: 2734 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2735 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2736 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!"); 2737 case TargetLowering::Legal: 2738 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2739 break; 2740 case TargetLowering::Promote: { 2741 MVT::ValueType OVT = Tmp1.getValueType(); 2742 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2743 2744 // Zero extend the argument. 2745 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2746 // Perform the larger operation, then subtract if needed. 2747 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2748 switch (Node->getOpcode()) { 2749 case ISD::CTPOP: 2750 Result = Tmp1; 2751 break; 2752 case ISD::CTTZ: 2753 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2754 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2755 DAG.getConstant(getSizeInBits(NVT), NVT), 2756 ISD::SETEQ); 2757 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2758 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 2759 break; 2760 case ISD::CTLZ: 2761 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2762 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2763 DAG.getConstant(getSizeInBits(NVT) - 2764 getSizeInBits(OVT), NVT)); 2765 break; 2766 } 2767 break; 2768 } 2769 case TargetLowering::Expand: 2770 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 2771 break; 2772 } 2773 break; 2774 2775 // Unary operators 2776 case ISD::FABS: 2777 case ISD::FNEG: 2778 case ISD::FSQRT: 2779 case ISD::FSIN: 2780 case ISD::FCOS: 2781 Tmp1 = LegalizeOp(Node->getOperand(0)); 2782 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2783 case TargetLowering::Promote: 2784 case TargetLowering::Custom: 2785 isCustom = true; 2786 // FALLTHROUGH 2787 case TargetLowering::Legal: 2788 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2789 if (isCustom) { 2790 Tmp1 = TLI.LowerOperation(Result, DAG); 2791 if (Tmp1.Val) Result = Tmp1; 2792 } 2793 break; 2794 case TargetLowering::Expand: 2795 switch (Node->getOpcode()) { 2796 default: assert(0 && "Unreachable!"); 2797 case ISD::FNEG: 2798 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2799 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2800 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 2801 break; 2802 case ISD::FABS: { 2803 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2804 MVT::ValueType VT = Node->getValueType(0); 2805 Tmp2 = DAG.getConstantFP(0.0, VT); 2806 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2807 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2808 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2809 break; 2810 } 2811 case ISD::FSQRT: 2812 case ISD::FSIN: 2813 case ISD::FCOS: { 2814 MVT::ValueType VT = Node->getValueType(0); 2815 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2816 switch(Node->getOpcode()) { 2817 case ISD::FSQRT: 2818 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64; 2819 break; 2820 case ISD::FSIN: 2821 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 2822 break; 2823 case ISD::FCOS: 2824 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64; 2825 break; 2826 default: assert(0 && "Unreachable!"); 2827 } 2828 SDOperand Dummy; 2829 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2830 false/*sign irrelevant*/, Dummy); 2831 break; 2832 } 2833 } 2834 break; 2835 } 2836 break; 2837 case ISD::FPOWI: { 2838 // We always lower FPOWI into a libcall. No target support it yet. 2839 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32 2840 ? RTLIB::POWI_F32 : RTLIB::POWI_F64; 2841 SDOperand Dummy; 2842 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2843 false/*sign irrelevant*/, Dummy); 2844 break; 2845 } 2846 case ISD::BIT_CONVERT: 2847 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 2848 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2849 } else { 2850 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2851 Node->getOperand(0).getValueType())) { 2852 default: assert(0 && "Unknown operation action!"); 2853 case TargetLowering::Expand: 2854 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2855 break; 2856 case TargetLowering::Legal: 2857 Tmp1 = LegalizeOp(Node->getOperand(0)); 2858 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2859 break; 2860 } 2861 } 2862 break; 2863 case ISD::VBIT_CONVERT: { 2864 assert(Op.getOperand(0).getValueType() == MVT::Vector && 2865 "Can only have VBIT_CONVERT where input or output is MVT::Vector!"); 2866 2867 // The input has to be a vector type, we have to either scalarize it, pack 2868 // it, or convert it based on whether the input vector type is legal. 2869 SDNode *InVal = Node->getOperand(0).Val; 2870 unsigned NumElems = 2871 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 2872 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 2873 2874 // Figure out if there is a Packed type corresponding to this Vector 2875 // type. If so, convert to the vector type. 2876 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2877 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 2878 // Turn this into a bit convert of the packed input. 2879 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2880 PackVectorOp(Node->getOperand(0), TVT)); 2881 break; 2882 } else if (NumElems == 1) { 2883 // Turn this into a bit convert of the scalar input. 2884 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2885 PackVectorOp(Node->getOperand(0), EVT)); 2886 break; 2887 } else { 2888 // FIXME: UNIMP! Store then reload 2889 assert(0 && "Cast from unsupported vector type not implemented yet!"); 2890 } 2891 } 2892 2893 // Conversion operators. The source and destination have different types. 2894 case ISD::SINT_TO_FP: 2895 case ISD::UINT_TO_FP: { 2896 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2897 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2898 case Legal: 2899 switch (TLI.getOperationAction(Node->getOpcode(), 2900 Node->getOperand(0).getValueType())) { 2901 default: assert(0 && "Unknown operation action!"); 2902 case TargetLowering::Custom: 2903 isCustom = true; 2904 // FALLTHROUGH 2905 case TargetLowering::Legal: 2906 Tmp1 = LegalizeOp(Node->getOperand(0)); 2907 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2908 if (isCustom) { 2909 Tmp1 = TLI.LowerOperation(Result, DAG); 2910 if (Tmp1.Val) Result = Tmp1; 2911 } 2912 break; 2913 case TargetLowering::Expand: 2914 Result = ExpandLegalINT_TO_FP(isSigned, 2915 LegalizeOp(Node->getOperand(0)), 2916 Node->getValueType(0)); 2917 break; 2918 case TargetLowering::Promote: 2919 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2920 Node->getValueType(0), 2921 isSigned); 2922 break; 2923 } 2924 break; 2925 case Expand: 2926 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2927 Node->getValueType(0), Node->getOperand(0)); 2928 break; 2929 case Promote: 2930 Tmp1 = PromoteOp(Node->getOperand(0)); 2931 if (isSigned) { 2932 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 2933 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 2934 } else { 2935 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 2936 Node->getOperand(0).getValueType()); 2937 } 2938 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2939 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 2940 break; 2941 } 2942 break; 2943 } 2944 case ISD::TRUNCATE: 2945 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2946 case Legal: 2947 Tmp1 = LegalizeOp(Node->getOperand(0)); 2948 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2949 break; 2950 case Expand: 2951 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2952 2953 // Since the result is legal, we should just be able to truncate the low 2954 // part of the source. 2955 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2956 break; 2957 case Promote: 2958 Result = PromoteOp(Node->getOperand(0)); 2959 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2960 break; 2961 } 2962 break; 2963 2964 case ISD::FP_TO_SINT: 2965 case ISD::FP_TO_UINT: 2966 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2967 case Legal: 2968 Tmp1 = LegalizeOp(Node->getOperand(0)); 2969 2970 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2971 default: assert(0 && "Unknown operation action!"); 2972 case TargetLowering::Custom: 2973 isCustom = true; 2974 // FALLTHROUGH 2975 case TargetLowering::Legal: 2976 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2977 if (isCustom) { 2978 Tmp1 = TLI.LowerOperation(Result, DAG); 2979 if (Tmp1.Val) Result = Tmp1; 2980 } 2981 break; 2982 case TargetLowering::Promote: 2983 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2984 Node->getOpcode() == ISD::FP_TO_SINT); 2985 break; 2986 case TargetLowering::Expand: 2987 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2988 SDOperand True, False; 2989 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2990 MVT::ValueType NVT = Node->getValueType(0); 2991 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2992 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2993 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2994 Node->getOperand(0), Tmp2, ISD::SETLT); 2995 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2996 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2997 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2998 Tmp2)); 2999 False = DAG.getNode(ISD::XOR, NVT, False, 3000 DAG.getConstant(1ULL << ShiftAmt, NVT)); 3001 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3002 break; 3003 } else { 3004 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3005 } 3006 break; 3007 } 3008 break; 3009 case Expand: { 3010 // Convert f32 / f64 to i32 / i64. 3011 MVT::ValueType VT = Op.getValueType(); 3012 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3013 switch (Node->getOpcode()) { 3014 case ISD::FP_TO_SINT: 3015 if (Node->getOperand(0).getValueType() == MVT::f32) 3016 LC = (VT == MVT::i32) 3017 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3018 else 3019 LC = (VT == MVT::i32) 3020 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3021 break; 3022 case ISD::FP_TO_UINT: 3023 if (Node->getOperand(0).getValueType() == MVT::f32) 3024 LC = (VT == MVT::i32) 3025 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3026 else 3027 LC = (VT == MVT::i32) 3028 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3029 break; 3030 default: assert(0 && "Unreachable!"); 3031 } 3032 SDOperand Dummy; 3033 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3034 false/*sign irrelevant*/, Dummy); 3035 break; 3036 } 3037 case Promote: 3038 Tmp1 = PromoteOp(Node->getOperand(0)); 3039 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3040 Result = LegalizeOp(Result); 3041 break; 3042 } 3043 break; 3044 3045 case ISD::ANY_EXTEND: 3046 case ISD::ZERO_EXTEND: 3047 case ISD::SIGN_EXTEND: 3048 case ISD::FP_EXTEND: 3049 case ISD::FP_ROUND: 3050 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3051 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3052 case Legal: 3053 Tmp1 = LegalizeOp(Node->getOperand(0)); 3054 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3055 break; 3056 case Promote: 3057 switch (Node->getOpcode()) { 3058 case ISD::ANY_EXTEND: 3059 Tmp1 = PromoteOp(Node->getOperand(0)); 3060 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3061 break; 3062 case ISD::ZERO_EXTEND: 3063 Result = PromoteOp(Node->getOperand(0)); 3064 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3065 Result = DAG.getZeroExtendInReg(Result, 3066 Node->getOperand(0).getValueType()); 3067 break; 3068 case ISD::SIGN_EXTEND: 3069 Result = PromoteOp(Node->getOperand(0)); 3070 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3071 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3072 Result, 3073 DAG.getValueType(Node->getOperand(0).getValueType())); 3074 break; 3075 case ISD::FP_EXTEND: 3076 Result = PromoteOp(Node->getOperand(0)); 3077 if (Result.getValueType() != Op.getValueType()) 3078 // Dynamically dead while we have only 2 FP types. 3079 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 3080 break; 3081 case ISD::FP_ROUND: 3082 Result = PromoteOp(Node->getOperand(0)); 3083 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 3084 break; 3085 } 3086 } 3087 break; 3088 case ISD::FP_ROUND_INREG: 3089 case ISD::SIGN_EXTEND_INREG: { 3090 Tmp1 = LegalizeOp(Node->getOperand(0)); 3091 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3092 3093 // If this operation is not supported, convert it to a shl/shr or load/store 3094 // pair. 3095 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3096 default: assert(0 && "This action not supported for this op yet!"); 3097 case TargetLowering::Legal: 3098 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3099 break; 3100 case TargetLowering::Expand: 3101 // If this is an integer extend and shifts are supported, do that. 3102 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3103 // NOTE: we could fall back on load/store here too for targets without 3104 // SAR. However, it is doubtful that any exist. 3105 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3106 MVT::getSizeInBits(ExtraVT); 3107 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3108 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3109 Node->getOperand(0), ShiftCst); 3110 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3111 Result, ShiftCst); 3112 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3113 // The only way we can lower this is to turn it into a TRUNCSTORE, 3114 // EXTLOAD pair, targetting a temporary location (a stack slot). 3115 3116 // NOTE: there is a choice here between constantly creating new stack 3117 // slots and always reusing the same one. We currently always create 3118 // new ones, as reuse may inhibit scheduling. 3119 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 3120 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty); 3121 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3122 MachineFunction &MF = DAG.getMachineFunction(); 3123 int SSFI = 3124 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 3125 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3126 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3127 StackSlot, NULL, 0, ExtraVT); 3128 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 3129 Result, StackSlot, NULL, 0, ExtraVT); 3130 } else { 3131 assert(0 && "Unknown op"); 3132 } 3133 break; 3134 } 3135 break; 3136 } 3137 } 3138 3139 assert(Result.getValueType() == Op.getValueType() && 3140 "Bad legalization!"); 3141 3142 // Make sure that the generated code is itself legal. 3143 if (Result != Op) 3144 Result = LegalizeOp(Result); 3145 3146 // Note that LegalizeOp may be reentered even from single-use nodes, which 3147 // means that we always must cache transformed nodes. 3148 AddLegalizedOperand(Op, Result); 3149 return Result; 3150} 3151 3152/// PromoteOp - Given an operation that produces a value in an invalid type, 3153/// promote it to compute the value into a larger type. The produced value will 3154/// have the correct bits for the low portion of the register, but no guarantee 3155/// is made about the top bits: it may be zero, sign-extended, or garbage. 3156SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 3157 MVT::ValueType VT = Op.getValueType(); 3158 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3159 assert(getTypeAction(VT) == Promote && 3160 "Caller should expand or legalize operands that are not promotable!"); 3161 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 3162 "Cannot promote to smaller type!"); 3163 3164 SDOperand Tmp1, Tmp2, Tmp3; 3165 SDOperand Result; 3166 SDNode *Node = Op.Val; 3167 3168 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 3169 if (I != PromotedNodes.end()) return I->second; 3170 3171 switch (Node->getOpcode()) { 3172 case ISD::CopyFromReg: 3173 assert(0 && "CopyFromReg must be legal!"); 3174 default: 3175#ifndef NDEBUG 3176 cerr << "NODE: "; Node->dump(); cerr << "\n"; 3177#endif 3178 assert(0 && "Do not know how to promote this operator!"); 3179 abort(); 3180 case ISD::UNDEF: 3181 Result = DAG.getNode(ISD::UNDEF, NVT); 3182 break; 3183 case ISD::Constant: 3184 if (VT != MVT::i1) 3185 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 3186 else 3187 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 3188 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 3189 break; 3190 case ISD::ConstantFP: 3191 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 3192 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 3193 break; 3194 3195 case ISD::SETCC: 3196 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 3197 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 3198 Node->getOperand(1), Node->getOperand(2)); 3199 break; 3200 3201 case ISD::TRUNCATE: 3202 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3203 case Legal: 3204 Result = LegalizeOp(Node->getOperand(0)); 3205 assert(Result.getValueType() >= NVT && 3206 "This truncation doesn't make sense!"); 3207 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 3208 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 3209 break; 3210 case Promote: 3211 // The truncation is not required, because we don't guarantee anything 3212 // about high bits anyway. 3213 Result = PromoteOp(Node->getOperand(0)); 3214 break; 3215 case Expand: 3216 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3217 // Truncate the low part of the expanded value to the result type 3218 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 3219 } 3220 break; 3221 case ISD::SIGN_EXTEND: 3222 case ISD::ZERO_EXTEND: 3223 case ISD::ANY_EXTEND: 3224 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3225 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 3226 case Legal: 3227 // Input is legal? Just do extend all the way to the larger type. 3228 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3229 break; 3230 case Promote: 3231 // Promote the reg if it's smaller. 3232 Result = PromoteOp(Node->getOperand(0)); 3233 // The high bits are not guaranteed to be anything. Insert an extend. 3234 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3235 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3236 DAG.getValueType(Node->getOperand(0).getValueType())); 3237 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3238 Result = DAG.getZeroExtendInReg(Result, 3239 Node->getOperand(0).getValueType()); 3240 break; 3241 } 3242 break; 3243 case ISD::BIT_CONVERT: 3244 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3245 Result = PromoteOp(Result); 3246 break; 3247 3248 case ISD::FP_EXTEND: 3249 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3250 case ISD::FP_ROUND: 3251 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3252 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3253 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3254 case Legal: 3255 // Input is legal? Do an FP_ROUND_INREG. 3256 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 3257 DAG.getValueType(VT)); 3258 break; 3259 } 3260 break; 3261 3262 case ISD::SINT_TO_FP: 3263 case ISD::UINT_TO_FP: 3264 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3265 case Legal: 3266 // No extra round required here. 3267 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3268 break; 3269 3270 case Promote: 3271 Result = PromoteOp(Node->getOperand(0)); 3272 if (Node->getOpcode() == ISD::SINT_TO_FP) 3273 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3274 Result, 3275 DAG.getValueType(Node->getOperand(0).getValueType())); 3276 else 3277 Result = DAG.getZeroExtendInReg(Result, 3278 Node->getOperand(0).getValueType()); 3279 // No extra round required here. 3280 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3281 break; 3282 case Expand: 3283 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3284 Node->getOperand(0)); 3285 // Round if we cannot tolerate excess precision. 3286 if (NoExcessFPPrecision) 3287 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3288 DAG.getValueType(VT)); 3289 break; 3290 } 3291 break; 3292 3293 case ISD::SIGN_EXTEND_INREG: 3294 Result = PromoteOp(Node->getOperand(0)); 3295 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3296 Node->getOperand(1)); 3297 break; 3298 case ISD::FP_TO_SINT: 3299 case ISD::FP_TO_UINT: 3300 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3301 case Legal: 3302 case Expand: 3303 Tmp1 = Node->getOperand(0); 3304 break; 3305 case Promote: 3306 // The input result is prerounded, so we don't have to do anything 3307 // special. 3308 Tmp1 = PromoteOp(Node->getOperand(0)); 3309 break; 3310 } 3311 // If we're promoting a UINT to a larger size, check to see if the new node 3312 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3313 // we can use that instead. This allows us to generate better code for 3314 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3315 // legal, such as PowerPC. 3316 if (Node->getOpcode() == ISD::FP_TO_UINT && 3317 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3318 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3319 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3320 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3321 } else { 3322 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3323 } 3324 break; 3325 3326 case ISD::FABS: 3327 case ISD::FNEG: 3328 Tmp1 = PromoteOp(Node->getOperand(0)); 3329 assert(Tmp1.getValueType() == NVT); 3330 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3331 // NOTE: we do not have to do any extra rounding here for 3332 // NoExcessFPPrecision, because we know the input will have the appropriate 3333 // precision, and these operations don't modify precision at all. 3334 break; 3335 3336 case ISD::FSQRT: 3337 case ISD::FSIN: 3338 case ISD::FCOS: 3339 Tmp1 = PromoteOp(Node->getOperand(0)); 3340 assert(Tmp1.getValueType() == NVT); 3341 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3342 if (NoExcessFPPrecision) 3343 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3344 DAG.getValueType(VT)); 3345 break; 3346 3347 case ISD::FPOWI: { 3348 // Promote f32 powi to f64 powi. Note that this could insert a libcall 3349 // directly as well, which may be better. 3350 Tmp1 = PromoteOp(Node->getOperand(0)); 3351 assert(Tmp1.getValueType() == NVT); 3352 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 3353 if (NoExcessFPPrecision) 3354 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3355 DAG.getValueType(VT)); 3356 break; 3357 } 3358 3359 case ISD::AND: 3360 case ISD::OR: 3361 case ISD::XOR: 3362 case ISD::ADD: 3363 case ISD::SUB: 3364 case ISD::MUL: 3365 // The input may have strange things in the top bits of the registers, but 3366 // these operations don't care. They may have weird bits going out, but 3367 // that too is okay if they are integer operations. 3368 Tmp1 = PromoteOp(Node->getOperand(0)); 3369 Tmp2 = PromoteOp(Node->getOperand(1)); 3370 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3371 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3372 break; 3373 case ISD::FADD: 3374 case ISD::FSUB: 3375 case ISD::FMUL: 3376 Tmp1 = PromoteOp(Node->getOperand(0)); 3377 Tmp2 = PromoteOp(Node->getOperand(1)); 3378 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3379 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3380 3381 // Floating point operations will give excess precision that we may not be 3382 // able to tolerate. If we DO allow excess precision, just leave it, 3383 // otherwise excise it. 3384 // FIXME: Why would we need to round FP ops more than integer ones? 3385 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3386 if (NoExcessFPPrecision) 3387 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3388 DAG.getValueType(VT)); 3389 break; 3390 3391 case ISD::SDIV: 3392 case ISD::SREM: 3393 // These operators require that their input be sign extended. 3394 Tmp1 = PromoteOp(Node->getOperand(0)); 3395 Tmp2 = PromoteOp(Node->getOperand(1)); 3396 if (MVT::isInteger(NVT)) { 3397 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3398 DAG.getValueType(VT)); 3399 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3400 DAG.getValueType(VT)); 3401 } 3402 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3403 3404 // Perform FP_ROUND: this is probably overly pessimistic. 3405 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3406 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3407 DAG.getValueType(VT)); 3408 break; 3409 case ISD::FDIV: 3410 case ISD::FREM: 3411 case ISD::FCOPYSIGN: 3412 // These operators require that their input be fp extended. 3413 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3414 case Legal: 3415 Tmp1 = LegalizeOp(Node->getOperand(0)); 3416 break; 3417 case Promote: 3418 Tmp1 = PromoteOp(Node->getOperand(0)); 3419 break; 3420 case Expand: 3421 assert(0 && "not implemented"); 3422 } 3423 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3424 case Legal: 3425 Tmp2 = LegalizeOp(Node->getOperand(1)); 3426 break; 3427 case Promote: 3428 Tmp2 = PromoteOp(Node->getOperand(1)); 3429 break; 3430 case Expand: 3431 assert(0 && "not implemented"); 3432 } 3433 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3434 3435 // Perform FP_ROUND: this is probably overly pessimistic. 3436 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 3437 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3438 DAG.getValueType(VT)); 3439 break; 3440 3441 case ISD::UDIV: 3442 case ISD::UREM: 3443 // These operators require that their input be zero extended. 3444 Tmp1 = PromoteOp(Node->getOperand(0)); 3445 Tmp2 = PromoteOp(Node->getOperand(1)); 3446 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3447 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3448 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3449 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3450 break; 3451 3452 case ISD::SHL: 3453 Tmp1 = PromoteOp(Node->getOperand(0)); 3454 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 3455 break; 3456 case ISD::SRA: 3457 // The input value must be properly sign extended. 3458 Tmp1 = PromoteOp(Node->getOperand(0)); 3459 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3460 DAG.getValueType(VT)); 3461 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 3462 break; 3463 case ISD::SRL: 3464 // The input value must be properly zero extended. 3465 Tmp1 = PromoteOp(Node->getOperand(0)); 3466 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3467 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 3468 break; 3469 3470 case ISD::VAARG: 3471 Tmp1 = Node->getOperand(0); // Get the chain. 3472 Tmp2 = Node->getOperand(1); // Get the pointer. 3473 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 3474 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 3475 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 3476 } else { 3477 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 3478 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3479 SV->getValue(), SV->getOffset()); 3480 // Increment the pointer, VAList, to the next vaarg 3481 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3482 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3483 TLI.getPointerTy())); 3484 // Store the incremented VAList to the legalized pointer 3485 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 3486 SV->getOffset()); 3487 // Load the actual argument out of the pointer VAList 3488 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 3489 } 3490 // Remember that we legalized the chain. 3491 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3492 break; 3493 3494 case ISD::LOAD: { 3495 LoadSDNode *LD = cast<LoadSDNode>(Node); 3496 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 3497 ? ISD::EXTLOAD : LD->getExtensionType(); 3498 Result = DAG.getExtLoad(ExtType, NVT, 3499 LD->getChain(), LD->getBasePtr(), 3500 LD->getSrcValue(), LD->getSrcValueOffset(), 3501 LD->getLoadedVT()); 3502 // Remember that we legalized the chain. 3503 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3504 break; 3505 } 3506 case ISD::SELECT: 3507 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 3508 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 3509 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 3510 break; 3511 case ISD::SELECT_CC: 3512 Tmp2 = PromoteOp(Node->getOperand(2)); // True 3513 Tmp3 = PromoteOp(Node->getOperand(3)); // False 3514 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3515 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 3516 break; 3517 case ISD::BSWAP: 3518 Tmp1 = Node->getOperand(0); 3519 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3520 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3521 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3522 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), 3523 TLI.getShiftAmountTy())); 3524 break; 3525 case ISD::CTPOP: 3526 case ISD::CTTZ: 3527 case ISD::CTLZ: 3528 // Zero extend the argument 3529 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 3530 // Perform the larger operation, then subtract if needed. 3531 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3532 switch(Node->getOpcode()) { 3533 case ISD::CTPOP: 3534 Result = Tmp1; 3535 break; 3536 case ISD::CTTZ: 3537 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3538 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3539 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 3540 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3541 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1); 3542 break; 3543 case ISD::CTLZ: 3544 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3545 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3546 DAG.getConstant(getSizeInBits(NVT) - 3547 getSizeInBits(VT), NVT)); 3548 break; 3549 } 3550 break; 3551 case ISD::VEXTRACT_VECTOR_ELT: 3552 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op)); 3553 break; 3554 case ISD::EXTRACT_VECTOR_ELT: 3555 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 3556 break; 3557 } 3558 3559 assert(Result.Val && "Didn't set a result!"); 3560 3561 // Make sure the result is itself legal. 3562 Result = LegalizeOp(Result); 3563 3564 // Remember that we promoted this! 3565 AddPromotedOperand(Op, Result); 3566 return Result; 3567} 3568 3569/// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a 3570/// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based 3571/// on the vector type. The return type of this matches the element type of the 3572/// vector, which may not be legal for the target. 3573SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) { 3574 // We know that operand #0 is the Vec vector. If the index is a constant 3575 // or if the invec is a supported hardware type, we can use it. Otherwise, 3576 // lower to a store then an indexed load. 3577 SDOperand Vec = Op.getOperand(0); 3578 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 3579 3580 SDNode *InVal = Vec.Val; 3581 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 3582 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 3583 3584 // Figure out if there is a Packed type corresponding to this Vector 3585 // type. If so, convert to the vector type. 3586 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3587 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 3588 // Turn this into a packed extract_vector_elt operation. 3589 Vec = PackVectorOp(Vec, TVT); 3590 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx); 3591 } else if (NumElems == 1) { 3592 // This must be an access of the only element. Return it. 3593 return PackVectorOp(Vec, EVT); 3594 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 3595 SDOperand Lo, Hi; 3596 SplitVectorOp(Vec, Lo, Hi); 3597 if (CIdx->getValue() < NumElems/2) { 3598 Vec = Lo; 3599 } else { 3600 Vec = Hi; 3601 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 3602 } 3603 3604 // It's now an extract from the appropriate high or low part. Recurse. 3605 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3606 return LowerVEXTRACT_VECTOR_ELT(Op); 3607 } else { 3608 // Variable index case for extract element. 3609 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!! 3610 assert(0 && "unimp!"); 3611 return SDOperand(); 3612 } 3613} 3614 3615/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 3616/// memory traffic. 3617SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 3618 SDOperand Vector = Op.getOperand(0); 3619 SDOperand Idx = Op.getOperand(1); 3620 3621 // If the target doesn't support this, store the value to a temporary 3622 // stack slot, then LOAD the scalar element back out. 3623 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType()); 3624 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vector, StackPtr, NULL, 0); 3625 3626 // Add the offset to the index. 3627 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 3628 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 3629 DAG.getConstant(EltSize, Idx.getValueType())); 3630 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 3631 3632 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 3633} 3634 3635 3636/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 3637/// with condition CC on the current target. This usually involves legalizing 3638/// or promoting the arguments. In the case where LHS and RHS must be expanded, 3639/// there may be no choice but to create a new SetCC node to represent the 3640/// legalized value of setcc lhs, rhs. In this case, the value is returned in 3641/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 3642void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 3643 SDOperand &RHS, 3644 SDOperand &CC) { 3645 SDOperand Tmp1, Tmp2, Result; 3646 3647 switch (getTypeAction(LHS.getValueType())) { 3648 case Legal: 3649 Tmp1 = LegalizeOp(LHS); // LHS 3650 Tmp2 = LegalizeOp(RHS); // RHS 3651 break; 3652 case Promote: 3653 Tmp1 = PromoteOp(LHS); // LHS 3654 Tmp2 = PromoteOp(RHS); // RHS 3655 3656 // If this is an FP compare, the operands have already been extended. 3657 if (MVT::isInteger(LHS.getValueType())) { 3658 MVT::ValueType VT = LHS.getValueType(); 3659 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3660 3661 // Otherwise, we have to insert explicit sign or zero extends. Note 3662 // that we could insert sign extends for ALL conditions, but zero extend 3663 // is cheaper on many machines (an AND instead of two shifts), so prefer 3664 // it. 3665 switch (cast<CondCodeSDNode>(CC)->get()) { 3666 default: assert(0 && "Unknown integer comparison!"); 3667 case ISD::SETEQ: 3668 case ISD::SETNE: 3669 case ISD::SETUGE: 3670 case ISD::SETUGT: 3671 case ISD::SETULE: 3672 case ISD::SETULT: 3673 // ALL of these operations will work if we either sign or zero extend 3674 // the operands (including the unsigned comparisons!). Zero extend is 3675 // usually a simpler/cheaper operation, so prefer it. 3676 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3677 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3678 break; 3679 case ISD::SETGE: 3680 case ISD::SETGT: 3681 case ISD::SETLT: 3682 case ISD::SETLE: 3683 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3684 DAG.getValueType(VT)); 3685 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3686 DAG.getValueType(VT)); 3687 break; 3688 } 3689 } 3690 break; 3691 case Expand: { 3692 MVT::ValueType VT = LHS.getValueType(); 3693 if (VT == MVT::f32 || VT == MVT::f64) { 3694 // Expand into one or more soft-fp libcall(s). 3695 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 3696 switch (cast<CondCodeSDNode>(CC)->get()) { 3697 case ISD::SETEQ: 3698 case ISD::SETOEQ: 3699 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 3700 break; 3701 case ISD::SETNE: 3702 case ISD::SETUNE: 3703 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 3704 break; 3705 case ISD::SETGE: 3706 case ISD::SETOGE: 3707 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 3708 break; 3709 case ISD::SETLT: 3710 case ISD::SETOLT: 3711 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3712 break; 3713 case ISD::SETLE: 3714 case ISD::SETOLE: 3715 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 3716 break; 3717 case ISD::SETGT: 3718 case ISD::SETOGT: 3719 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 3720 break; 3721 case ISD::SETUO: 3722 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 3723 break; 3724 case ISD::SETO: 3725 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 3726 break; 3727 default: 3728 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 3729 switch (cast<CondCodeSDNode>(CC)->get()) { 3730 case ISD::SETONE: 3731 // SETONE = SETOLT | SETOGT 3732 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3733 // Fallthrough 3734 case ISD::SETUGT: 3735 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 3736 break; 3737 case ISD::SETUGE: 3738 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 3739 break; 3740 case ISD::SETULT: 3741 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 3742 break; 3743 case ISD::SETULE: 3744 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 3745 break; 3746 case ISD::SETUEQ: 3747 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 3748 break; 3749 default: assert(0 && "Unsupported FP setcc!"); 3750 } 3751 } 3752 3753 SDOperand Dummy; 3754 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 3755 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 3756 false /*sign irrelevant*/, Dummy); 3757 Tmp2 = DAG.getConstant(0, MVT::i32); 3758 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 3759 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 3760 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 3761 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 3762 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 3763 false /*sign irrelevant*/, Dummy); 3764 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 3765 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 3766 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 3767 Tmp2 = SDOperand(); 3768 } 3769 LHS = Tmp1; 3770 RHS = Tmp2; 3771 return; 3772 } 3773 3774 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 3775 ExpandOp(LHS, LHSLo, LHSHi); 3776 ExpandOp(RHS, RHSLo, RHSHi); 3777 switch (cast<CondCodeSDNode>(CC)->get()) { 3778 case ISD::SETEQ: 3779 case ISD::SETNE: 3780 if (RHSLo == RHSHi) 3781 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 3782 if (RHSCST->isAllOnesValue()) { 3783 // Comparison to -1. 3784 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 3785 Tmp2 = RHSLo; 3786 break; 3787 } 3788 3789 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 3790 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 3791 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 3792 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3793 break; 3794 default: 3795 // If this is a comparison of the sign bit, just look at the top part. 3796 // X > -1, x < 0 3797 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 3798 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 3799 CST->getValue() == 0) || // X < 0 3800 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 3801 CST->isAllOnesValue())) { // X > -1 3802 Tmp1 = LHSHi; 3803 Tmp2 = RHSHi; 3804 break; 3805 } 3806 3807 // FIXME: This generated code sucks. 3808 ISD::CondCode LowCC; 3809 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 3810 switch (CCCode) { 3811 default: assert(0 && "Unknown integer setcc!"); 3812 case ISD::SETLT: 3813 case ISD::SETULT: LowCC = ISD::SETULT; break; 3814 case ISD::SETGT: 3815 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 3816 case ISD::SETLE: 3817 case ISD::SETULE: LowCC = ISD::SETULE; break; 3818 case ISD::SETGE: 3819 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 3820 } 3821 3822 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 3823 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 3824 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 3825 3826 // NOTE: on targets without efficient SELECT of bools, we can always use 3827 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 3828 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 3829 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, 3830 false, DagCombineInfo); 3831 if (!Tmp1.Val) 3832 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 3833 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 3834 CCCode, false, DagCombineInfo); 3835 if (!Tmp2.Val) 3836 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC); 3837 3838 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 3839 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 3840 if ((Tmp1C && Tmp1C->getValue() == 0) || 3841 (Tmp2C && Tmp2C->getValue() == 0 && 3842 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 3843 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 3844 (Tmp2C && Tmp2C->getValue() == 1 && 3845 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 3846 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 3847 // low part is known false, returns high part. 3848 // For LE / GE, if high part is known false, ignore the low part. 3849 // For LT / GT, if high part is known true, ignore the low part. 3850 Tmp1 = Tmp2; 3851 Tmp2 = SDOperand(); 3852 } else { 3853 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 3854 ISD::SETEQ, false, DagCombineInfo); 3855 if (!Result.Val) 3856 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 3857 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 3858 Result, Tmp1, Tmp2)); 3859 Tmp1 = Result; 3860 Tmp2 = SDOperand(); 3861 } 3862 } 3863 } 3864 } 3865 LHS = Tmp1; 3866 RHS = Tmp2; 3867} 3868 3869/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 3870/// The resultant code need not be legal. Note that SrcOp is the input operand 3871/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 3872SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 3873 SDOperand SrcOp) { 3874 // Create the stack frame object. 3875 SDOperand FIPtr = CreateStackTemporary(DestVT); 3876 3877 // Emit a store to the stack slot. 3878 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); 3879 // Result is a load from the stack slot. 3880 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 3881} 3882 3883SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 3884 // Create a vector sized/aligned stack slot, store the value to element #0, 3885 // then load the whole vector back out. 3886 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); 3887 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 3888 NULL, 0); 3889 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 3890} 3891 3892 3893/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 3894/// support the operation, but do support the resultant packed vector type. 3895SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 3896 3897 // If the only non-undef value is the low element, turn this into a 3898 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 3899 unsigned NumElems = Node->getNumOperands(); 3900 bool isOnlyLowElement = true; 3901 SDOperand SplatValue = Node->getOperand(0); 3902 std::map<SDOperand, std::vector<unsigned> > Values; 3903 Values[SplatValue].push_back(0); 3904 bool isConstant = true; 3905 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 3906 SplatValue.getOpcode() != ISD::UNDEF) 3907 isConstant = false; 3908 3909 for (unsigned i = 1; i < NumElems; ++i) { 3910 SDOperand V = Node->getOperand(i); 3911 Values[V].push_back(i); 3912 if (V.getOpcode() != ISD::UNDEF) 3913 isOnlyLowElement = false; 3914 if (SplatValue != V) 3915 SplatValue = SDOperand(0,0); 3916 3917 // If this isn't a constant element or an undef, we can't use a constant 3918 // pool load. 3919 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 3920 V.getOpcode() != ISD::UNDEF) 3921 isConstant = false; 3922 } 3923 3924 if (isOnlyLowElement) { 3925 // If the low element is an undef too, then this whole things is an undef. 3926 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 3927 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 3928 // Otherwise, turn this into a scalar_to_vector node. 3929 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 3930 Node->getOperand(0)); 3931 } 3932 3933 // If all elements are constants, create a load from the constant pool. 3934 if (isConstant) { 3935 MVT::ValueType VT = Node->getValueType(0); 3936 const Type *OpNTy = 3937 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 3938 std::vector<Constant*> CV; 3939 for (unsigned i = 0, e = NumElems; i != e; ++i) { 3940 if (ConstantFPSDNode *V = 3941 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 3942 CV.push_back(ConstantFP::get(OpNTy, V->getValue())); 3943 } else if (ConstantSDNode *V = 3944 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 3945 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 3946 } else { 3947 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 3948 CV.push_back(UndefValue::get(OpNTy)); 3949 } 3950 } 3951 Constant *CP = ConstantVector::get(CV); 3952 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 3953 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 3954 } 3955 3956 if (SplatValue.Val) { // Splat of one value? 3957 // Build the shuffle constant vector: <0, 0, 0, 0> 3958 MVT::ValueType MaskVT = 3959 MVT::getIntVectorWithNumElements(NumElems); 3960 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT)); 3961 std::vector<SDOperand> ZeroVec(NumElems, Zero); 3962 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3963 &ZeroVec[0], ZeroVec.size()); 3964 3965 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 3966 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 3967 // Get the splatted value into the low element of a vector register. 3968 SDOperand LowValVec = 3969 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 3970 3971 // Return shuffle(LowValVec, undef, <0,0,0,0>) 3972 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 3973 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 3974 SplatMask); 3975 } 3976 } 3977 3978 // If there are only two unique elements, we may be able to turn this into a 3979 // vector shuffle. 3980 if (Values.size() == 2) { 3981 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 3982 MVT::ValueType MaskVT = 3983 MVT::getIntVectorWithNumElements(NumElems); 3984 std::vector<SDOperand> MaskVec(NumElems); 3985 unsigned i = 0; 3986 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 3987 E = Values.end(); I != E; ++I) { 3988 for (std::vector<unsigned>::iterator II = I->second.begin(), 3989 EE = I->second.end(); II != EE; ++II) 3990 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT)); 3991 i += NumElems; 3992 } 3993 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 3994 &MaskVec[0], MaskVec.size()); 3995 3996 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 3997 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 3998 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 3999 SmallVector<SDOperand, 8> Ops; 4000 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4001 E = Values.end(); I != E; ++I) { 4002 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4003 I->first); 4004 Ops.push_back(Op); 4005 } 4006 Ops.push_back(ShuffleMask); 4007 4008 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 4009 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 4010 &Ops[0], Ops.size()); 4011 } 4012 } 4013 4014 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 4015 // aligned object on the stack, store each element into it, then load 4016 // the result as a vector. 4017 MVT::ValueType VT = Node->getValueType(0); 4018 // Create the stack frame object. 4019 SDOperand FIPtr = CreateStackTemporary(VT); 4020 4021 // Emit a store of each element to the stack slot. 4022 SmallVector<SDOperand, 8> Stores; 4023 unsigned TypeByteSize = 4024 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 4025 // Store (in the right endianness) the elements to memory. 4026 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4027 // Ignore undef elements. 4028 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4029 4030 unsigned Offset = TypeByteSize*i; 4031 4032 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 4033 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 4034 4035 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 4036 NULL, 0)); 4037 } 4038 4039 SDOperand StoreChain; 4040 if (!Stores.empty()) // Not all undef elements? 4041 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4042 &Stores[0], Stores.size()); 4043 else 4044 StoreChain = DAG.getEntryNode(); 4045 4046 // Result is a load from the stack slot. 4047 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 4048} 4049 4050/// CreateStackTemporary - Create a stack temporary, suitable for holding the 4051/// specified value type. 4052SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) { 4053 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4054 unsigned ByteSize = MVT::getSizeInBits(VT)/8; 4055 const Type *Ty = MVT::getTypeForValueType(VT); 4056 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty); 4057 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 4058 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 4059} 4060 4061void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 4062 SDOperand Op, SDOperand Amt, 4063 SDOperand &Lo, SDOperand &Hi) { 4064 // Expand the subcomponents. 4065 SDOperand LHSL, LHSH; 4066 ExpandOp(Op, LHSL, LHSH); 4067 4068 SDOperand Ops[] = { LHSL, LHSH, Amt }; 4069 MVT::ValueType VT = LHSL.getValueType(); 4070 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 4071 Hi = Lo.getValue(1); 4072} 4073 4074 4075/// ExpandShift - Try to find a clever way to expand this shift operation out to 4076/// smaller elements. If we can't find a way that is more efficient than a 4077/// libcall on this target, return false. Otherwise, return true with the 4078/// low-parts expanded into Lo and Hi. 4079bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 4080 SDOperand &Lo, SDOperand &Hi) { 4081 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 4082 "This is not a shift!"); 4083 4084 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 4085 SDOperand ShAmt = LegalizeOp(Amt); 4086 MVT::ValueType ShTy = ShAmt.getValueType(); 4087 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 4088 unsigned NVTBits = MVT::getSizeInBits(NVT); 4089 4090 // Handle the case when Amt is an immediate. Other cases are currently broken 4091 // and are disabled. 4092 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 4093 unsigned Cst = CN->getValue(); 4094 // Expand the incoming operand to be shifted, so that we have its parts 4095 SDOperand InL, InH; 4096 ExpandOp(Op, InL, InH); 4097 switch(Opc) { 4098 case ISD::SHL: 4099 if (Cst > VTBits) { 4100 Lo = DAG.getConstant(0, NVT); 4101 Hi = DAG.getConstant(0, NVT); 4102 } else if (Cst > NVTBits) { 4103 Lo = DAG.getConstant(0, NVT); 4104 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 4105 } else if (Cst == NVTBits) { 4106 Lo = DAG.getConstant(0, NVT); 4107 Hi = InL; 4108 } else { 4109 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 4110 Hi = DAG.getNode(ISD::OR, NVT, 4111 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 4112 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 4113 } 4114 return true; 4115 case ISD::SRL: 4116 if (Cst > VTBits) { 4117 Lo = DAG.getConstant(0, NVT); 4118 Hi = DAG.getConstant(0, NVT); 4119 } else if (Cst > NVTBits) { 4120 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 4121 Hi = DAG.getConstant(0, NVT); 4122 } else if (Cst == NVTBits) { 4123 Lo = InH; 4124 Hi = DAG.getConstant(0, NVT); 4125 } else { 4126 Lo = DAG.getNode(ISD::OR, NVT, 4127 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4128 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4129 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 4130 } 4131 return true; 4132 case ISD::SRA: 4133 if (Cst > VTBits) { 4134 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 4135 DAG.getConstant(NVTBits-1, ShTy)); 4136 } else if (Cst > NVTBits) { 4137 Lo = DAG.getNode(ISD::SRA, NVT, InH, 4138 DAG.getConstant(Cst-NVTBits, ShTy)); 4139 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4140 DAG.getConstant(NVTBits-1, ShTy)); 4141 } else if (Cst == NVTBits) { 4142 Lo = InH; 4143 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4144 DAG.getConstant(NVTBits-1, ShTy)); 4145 } else { 4146 Lo = DAG.getNode(ISD::OR, NVT, 4147 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4148 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4149 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 4150 } 4151 return true; 4152 } 4153 } 4154 4155 // Okay, the shift amount isn't constant. However, if we can tell that it is 4156 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 4157 uint64_t Mask = NVTBits, KnownZero, KnownOne; 4158 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 4159 4160 // If we know that the high bit of the shift amount is one, then we can do 4161 // this as a couple of simple shifts. 4162 if (KnownOne & Mask) { 4163 // Mask out the high bit, which we know is set. 4164 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 4165 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4166 4167 // Expand the incoming operand to be shifted, so that we have its parts 4168 SDOperand InL, InH; 4169 ExpandOp(Op, InL, InH); 4170 switch(Opc) { 4171 case ISD::SHL: 4172 Lo = DAG.getConstant(0, NVT); // Low part is zero. 4173 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 4174 return true; 4175 case ISD::SRL: 4176 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 4177 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 4178 return true; 4179 case ISD::SRA: 4180 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 4181 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4182 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 4183 return true; 4184 } 4185 } 4186 4187 // If we know that the high bit of the shift amount is zero, then we can do 4188 // this as a couple of simple shifts. 4189 if (KnownZero & Mask) { 4190 // Compute 32-amt. 4191 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 4192 DAG.getConstant(NVTBits, Amt.getValueType()), 4193 Amt); 4194 4195 // Expand the incoming operand to be shifted, so that we have its parts 4196 SDOperand InL, InH; 4197 ExpandOp(Op, InL, InH); 4198 switch(Opc) { 4199 case ISD::SHL: 4200 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 4201 Hi = DAG.getNode(ISD::OR, NVT, 4202 DAG.getNode(ISD::SHL, NVT, InH, Amt), 4203 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 4204 return true; 4205 case ISD::SRL: 4206 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 4207 Lo = DAG.getNode(ISD::OR, NVT, 4208 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4209 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4210 return true; 4211 case ISD::SRA: 4212 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 4213 Lo = DAG.getNode(ISD::OR, NVT, 4214 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4215 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4216 return true; 4217 } 4218 } 4219 4220 return false; 4221} 4222 4223 4224// ExpandLibCall - Expand a node into a call to a libcall. If the result value 4225// does not fit into a register, return the lo part and set the hi part to the 4226// by-reg argument. If it does fit into a single register, return the result 4227// and leave the Hi part unset. 4228SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 4229 bool isSigned, SDOperand &Hi) { 4230 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 4231 // The input chain to this libcall is the entry node of the function. 4232 // Legalizing the call will automatically add the previous call to the 4233 // dependence. 4234 SDOperand InChain = DAG.getEntryNode(); 4235 4236 TargetLowering::ArgListTy Args; 4237 TargetLowering::ArgListEntry Entry; 4238 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4239 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 4240 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 4241 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 4242 Entry.isSExt = isSigned; 4243 Args.push_back(Entry); 4244 } 4245 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 4246 4247 // Splice the libcall in wherever FindInputOutputChains tells us to. 4248 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 4249 std::pair<SDOperand,SDOperand> CallInfo = 4250 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false, 4251 Callee, Args, DAG); 4252 4253 // Legalize the call sequence, starting with the chain. This will advance 4254 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 4255 // was added by LowerCallTo (guaranteeing proper serialization of calls). 4256 LegalizeOp(CallInfo.second); 4257 SDOperand Result; 4258 switch (getTypeAction(CallInfo.first.getValueType())) { 4259 default: assert(0 && "Unknown thing"); 4260 case Legal: 4261 Result = CallInfo.first; 4262 break; 4263 case Expand: 4264 ExpandOp(CallInfo.first, Result, Hi); 4265 break; 4266 } 4267 return Result; 4268} 4269 4270 4271/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 4272/// destination type is legal. 4273SDOperand SelectionDAGLegalize:: 4274ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 4275 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 4276 assert(getTypeAction(Source.getValueType()) == Expand && 4277 "This is not an expansion!"); 4278 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 4279 4280 if (!isSigned) { 4281 assert(Source.getValueType() == MVT::i64 && 4282 "This only works for 64-bit -> FP"); 4283 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 4284 // incoming integer is set. To handle this, we dynamically test to see if 4285 // it is set, and, if so, add a fudge factor. 4286 SDOperand Lo, Hi; 4287 ExpandOp(Source, Lo, Hi); 4288 4289 // If this is unsigned, and not supported, first perform the conversion to 4290 // signed, then adjust the result if the sign bit is set. 4291 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 4292 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 4293 4294 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 4295 DAG.getConstant(0, Hi.getValueType()), 4296 ISD::SETLT); 4297 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4298 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4299 SignSet, Four, Zero); 4300 uint64_t FF = 0x5f800000ULL; 4301 if (TLI.isLittleEndian()) FF <<= 32; 4302 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4303 4304 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4305 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4306 SDOperand FudgeInReg; 4307 if (DestTy == MVT::f32) 4308 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4309 else { 4310 assert(DestTy == MVT::f64 && "Unexpected conversion"); 4311 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 4312 CPIdx, NULL, 0, MVT::f32); 4313 } 4314 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 4315 } 4316 4317 // Check to see if the target has a custom way to lower this. If so, use it. 4318 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 4319 default: assert(0 && "This action not implemented for this operation!"); 4320 case TargetLowering::Legal: 4321 case TargetLowering::Expand: 4322 break; // This case is handled below. 4323 case TargetLowering::Custom: { 4324 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 4325 Source), DAG); 4326 if (NV.Val) 4327 return LegalizeOp(NV); 4328 break; // The target decided this was legal after all 4329 } 4330 } 4331 4332 // Expand the source, then glue it back together for the call. We must expand 4333 // the source in case it is shared (this pass of legalize must traverse it). 4334 SDOperand SrcLo, SrcHi; 4335 ExpandOp(Source, SrcLo, SrcHi); 4336 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 4337 4338 RTLIB::Libcall LC; 4339 if (DestTy == MVT::f32) 4340 LC = RTLIB::SINTTOFP_I64_F32; 4341 else { 4342 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 4343 LC = RTLIB::SINTTOFP_I64_F64; 4344 } 4345 4346 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 4347 SDOperand UnusedHiPart; 4348 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 4349 UnusedHiPart); 4350} 4351 4352/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 4353/// INT_TO_FP operation of the specified operand when the target requests that 4354/// we expand it. At this point, we know that the result and operand types are 4355/// legal for the target. 4356SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 4357 SDOperand Op0, 4358 MVT::ValueType DestVT) { 4359 if (Op0.getValueType() == MVT::i32) { 4360 // simple 32-bit [signed|unsigned] integer to float/double expansion 4361 4362 // get the stack frame index of a 8 byte buffer, pessimistically aligned 4363 MachineFunction &MF = DAG.getMachineFunction(); 4364 const Type *F64Type = MVT::getTypeForValueType(MVT::f64); 4365 unsigned StackAlign = 4366 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type); 4367 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign); 4368 // get address of 8 byte buffer 4369 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4370 // word offset constant for Hi/Lo address computation 4371 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 4372 // set up Hi and Lo (into buffer) address based on endian 4373 SDOperand Hi = StackSlot; 4374 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 4375 if (TLI.isLittleEndian()) 4376 std::swap(Hi, Lo); 4377 4378 // if signed map to unsigned space 4379 SDOperand Op0Mapped; 4380 if (isSigned) { 4381 // constant used to invert sign bit (signed to unsigned mapping) 4382 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 4383 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 4384 } else { 4385 Op0Mapped = Op0; 4386 } 4387 // store the lo of the constructed double - based on integer input 4388 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 4389 Op0Mapped, Lo, NULL, 0); 4390 // initial hi portion of constructed double 4391 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 4392 // store the hi of the constructed double - biased exponent 4393 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 4394 // load the constructed double 4395 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 4396 // FP constant to bias correct the final result 4397 SDOperand Bias = DAG.getConstantFP(isSigned ? 4398 BitsToDouble(0x4330000080000000ULL) 4399 : BitsToDouble(0x4330000000000000ULL), 4400 MVT::f64); 4401 // subtract the bias 4402 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 4403 // final result 4404 SDOperand Result; 4405 // handle final rounding 4406 if (DestVT == MVT::f64) { 4407 // do nothing 4408 Result = Sub; 4409 } else { 4410 // if f32 then cast to f32 4411 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 4412 } 4413 return Result; 4414 } 4415 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 4416 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 4417 4418 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 4419 DAG.getConstant(0, Op0.getValueType()), 4420 ISD::SETLT); 4421 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4422 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4423 SignSet, Four, Zero); 4424 4425 // If the sign bit of the integer is set, the large number will be treated 4426 // as a negative number. To counteract this, the dynamic code adds an 4427 // offset depending on the data type. 4428 uint64_t FF; 4429 switch (Op0.getValueType()) { 4430 default: assert(0 && "Unsupported integer type!"); 4431 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 4432 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 4433 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 4434 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 4435 } 4436 if (TLI.isLittleEndian()) FF <<= 32; 4437 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4438 4439 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4440 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4441 SDOperand FudgeInReg; 4442 if (DestVT == MVT::f32) 4443 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4444 else { 4445 assert(DestVT == MVT::f64 && "Unexpected conversion"); 4446 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 4447 DAG.getEntryNode(), CPIdx, 4448 NULL, 0, MVT::f32)); 4449 } 4450 4451 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 4452} 4453 4454/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 4455/// *INT_TO_FP operation of the specified operand when the target requests that 4456/// we promote it. At this point, we know that the result and operand types are 4457/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 4458/// operation that takes a larger input. 4459SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 4460 MVT::ValueType DestVT, 4461 bool isSigned) { 4462 // First step, figure out the appropriate *INT_TO_FP operation to use. 4463 MVT::ValueType NewInTy = LegalOp.getValueType(); 4464 4465 unsigned OpToUse = 0; 4466 4467 // Scan for the appropriate larger type to use. 4468 while (1) { 4469 NewInTy = (MVT::ValueType)(NewInTy+1); 4470 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 4471 4472 // If the target supports SINT_TO_FP of this type, use it. 4473 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 4474 default: break; 4475 case TargetLowering::Legal: 4476 if (!TLI.isTypeLegal(NewInTy)) 4477 break; // Can't use this datatype. 4478 // FALL THROUGH. 4479 case TargetLowering::Custom: 4480 OpToUse = ISD::SINT_TO_FP; 4481 break; 4482 } 4483 if (OpToUse) break; 4484 if (isSigned) continue; 4485 4486 // If the target supports UINT_TO_FP of this type, use it. 4487 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 4488 default: break; 4489 case TargetLowering::Legal: 4490 if (!TLI.isTypeLegal(NewInTy)) 4491 break; // Can't use this datatype. 4492 // FALL THROUGH. 4493 case TargetLowering::Custom: 4494 OpToUse = ISD::UINT_TO_FP; 4495 break; 4496 } 4497 if (OpToUse) break; 4498 4499 // Otherwise, try a larger type. 4500 } 4501 4502 // Okay, we found the operation and type to use. Zero extend our input to the 4503 // desired type then run the operation on it. 4504 return DAG.getNode(OpToUse, DestVT, 4505 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 4506 NewInTy, LegalOp)); 4507} 4508 4509/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 4510/// FP_TO_*INT operation of the specified operand when the target requests that 4511/// we promote it. At this point, we know that the result and operand types are 4512/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 4513/// operation that returns a larger result. 4514SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 4515 MVT::ValueType DestVT, 4516 bool isSigned) { 4517 // First step, figure out the appropriate FP_TO*INT operation to use. 4518 MVT::ValueType NewOutTy = DestVT; 4519 4520 unsigned OpToUse = 0; 4521 4522 // Scan for the appropriate larger type to use. 4523 while (1) { 4524 NewOutTy = (MVT::ValueType)(NewOutTy+1); 4525 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 4526 4527 // If the target supports FP_TO_SINT returning this type, use it. 4528 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 4529 default: break; 4530 case TargetLowering::Legal: 4531 if (!TLI.isTypeLegal(NewOutTy)) 4532 break; // Can't use this datatype. 4533 // FALL THROUGH. 4534 case TargetLowering::Custom: 4535 OpToUse = ISD::FP_TO_SINT; 4536 break; 4537 } 4538 if (OpToUse) break; 4539 4540 // If the target supports FP_TO_UINT of this type, use it. 4541 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 4542 default: break; 4543 case TargetLowering::Legal: 4544 if (!TLI.isTypeLegal(NewOutTy)) 4545 break; // Can't use this datatype. 4546 // FALL THROUGH. 4547 case TargetLowering::Custom: 4548 OpToUse = ISD::FP_TO_UINT; 4549 break; 4550 } 4551 if (OpToUse) break; 4552 4553 // Otherwise, try a larger type. 4554 } 4555 4556 // Okay, we found the operation and type to use. Truncate the result of the 4557 // extended FP_TO_*INT operation to the desired size. 4558 return DAG.getNode(ISD::TRUNCATE, DestVT, 4559 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 4560} 4561 4562/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 4563/// 4564SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 4565 MVT::ValueType VT = Op.getValueType(); 4566 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 4567 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 4568 switch (VT) { 4569 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 4570 case MVT::i16: 4571 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4572 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4573 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 4574 case MVT::i32: 4575 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4576 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4577 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4578 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4579 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 4580 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 4581 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4582 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4583 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4584 case MVT::i64: 4585 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 4586 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 4587 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4588 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4589 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4590 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4591 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 4592 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 4593 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 4594 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 4595 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 4596 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 4597 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 4598 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 4599 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 4600 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 4601 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4602 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4603 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 4604 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4605 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 4606 } 4607} 4608 4609/// ExpandBitCount - Expand the specified bitcount instruction into operations. 4610/// 4611SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 4612 switch (Opc) { 4613 default: assert(0 && "Cannot expand this yet!"); 4614 case ISD::CTPOP: { 4615 static const uint64_t mask[6] = { 4616 0x5555555555555555ULL, 0x3333333333333333ULL, 4617 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 4618 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 4619 }; 4620 MVT::ValueType VT = Op.getValueType(); 4621 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4622 unsigned len = getSizeInBits(VT); 4623 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4624 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 4625 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 4626 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4627 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 4628 DAG.getNode(ISD::AND, VT, 4629 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 4630 } 4631 return Op; 4632 } 4633 case ISD::CTLZ: { 4634 // for now, we do this: 4635 // x = x | (x >> 1); 4636 // x = x | (x >> 2); 4637 // ... 4638 // x = x | (x >>16); 4639 // x = x | (x >>32); // for 64-bit input 4640 // return popcount(~x); 4641 // 4642 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 4643 MVT::ValueType VT = Op.getValueType(); 4644 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4645 unsigned len = getSizeInBits(VT); 4646 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4647 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4648 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 4649 } 4650 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 4651 return DAG.getNode(ISD::CTPOP, VT, Op); 4652 } 4653 case ISD::CTTZ: { 4654 // for now, we use: { return popcount(~x & (x - 1)); } 4655 // unless the target has ctlz but not ctpop, in which case we use: 4656 // { return 32 - nlz(~x & (x-1)); } 4657 // see also http://www.hackersdelight.org/HDcode/ntz.cc 4658 MVT::ValueType VT = Op.getValueType(); 4659 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 4660 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 4661 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 4662 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 4663 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 4664 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 4665 TLI.isOperationLegal(ISD::CTLZ, VT)) 4666 return DAG.getNode(ISD::SUB, VT, 4667 DAG.getConstant(getSizeInBits(VT), VT), 4668 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 4669 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 4670 } 4671 } 4672} 4673 4674/// ExpandOp - Expand the specified SDOperand into its two component pieces 4675/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 4676/// LegalizeNodes map is filled in for any results that are not expanded, the 4677/// ExpandedNodes map is filled in for any results that are expanded, and the 4678/// Lo/Hi values are returned. 4679void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 4680 MVT::ValueType VT = Op.getValueType(); 4681 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4682 SDNode *Node = Op.Val; 4683 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 4684 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 4685 VT == MVT::Vector) && 4686 "Cannot expand to FP value or to larger int value!"); 4687 4688 // See if we already expanded it. 4689 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 4690 = ExpandedNodes.find(Op); 4691 if (I != ExpandedNodes.end()) { 4692 Lo = I->second.first; 4693 Hi = I->second.second; 4694 return; 4695 } 4696 4697 switch (Node->getOpcode()) { 4698 case ISD::CopyFromReg: 4699 assert(0 && "CopyFromReg must be legal!"); 4700 default: 4701#ifndef NDEBUG 4702 cerr << "NODE: "; Node->dump(); cerr << "\n"; 4703#endif 4704 assert(0 && "Do not know how to expand this operator!"); 4705 abort(); 4706 case ISD::UNDEF: 4707 NVT = TLI.getTypeToExpandTo(VT); 4708 Lo = DAG.getNode(ISD::UNDEF, NVT); 4709 Hi = DAG.getNode(ISD::UNDEF, NVT); 4710 break; 4711 case ISD::Constant: { 4712 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 4713 Lo = DAG.getConstant(Cst, NVT); 4714 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 4715 break; 4716 } 4717 case ISD::ConstantFP: { 4718 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 4719 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 4720 if (getTypeAction(Lo.getValueType()) == Expand) 4721 ExpandOp(Lo, Lo, Hi); 4722 break; 4723 } 4724 case ISD::BUILD_PAIR: 4725 // Return the operands. 4726 Lo = Node->getOperand(0); 4727 Hi = Node->getOperand(1); 4728 break; 4729 4730 case ISD::SIGN_EXTEND_INREG: 4731 ExpandOp(Node->getOperand(0), Lo, Hi); 4732 // sext_inreg the low part if needed. 4733 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 4734 4735 // The high part gets the sign extension from the lo-part. This handles 4736 // things like sextinreg V:i64 from i8. 4737 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4738 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 4739 TLI.getShiftAmountTy())); 4740 break; 4741 4742 case ISD::BSWAP: { 4743 ExpandOp(Node->getOperand(0), Lo, Hi); 4744 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 4745 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 4746 Lo = TempLo; 4747 break; 4748 } 4749 4750 case ISD::CTPOP: 4751 ExpandOp(Node->getOperand(0), Lo, Hi); 4752 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 4753 DAG.getNode(ISD::CTPOP, NVT, Lo), 4754 DAG.getNode(ISD::CTPOP, NVT, Hi)); 4755 Hi = DAG.getConstant(0, NVT); 4756 break; 4757 4758 case ISD::CTLZ: { 4759 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 4760 ExpandOp(Node->getOperand(0), Lo, Hi); 4761 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4762 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 4763 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 4764 ISD::SETNE); 4765 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 4766 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 4767 4768 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 4769 Hi = DAG.getConstant(0, NVT); 4770 break; 4771 } 4772 4773 case ISD::CTTZ: { 4774 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 4775 ExpandOp(Node->getOperand(0), Lo, Hi); 4776 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4777 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 4778 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 4779 ISD::SETNE); 4780 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 4781 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 4782 4783 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 4784 Hi = DAG.getConstant(0, NVT); 4785 break; 4786 } 4787 4788 case ISD::VAARG: { 4789 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4790 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4791 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 4792 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 4793 4794 // Remember that we legalized the chain. 4795 Hi = LegalizeOp(Hi); 4796 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 4797 if (!TLI.isLittleEndian()) 4798 std::swap(Lo, Hi); 4799 break; 4800 } 4801 4802 case ISD::LOAD: { 4803 LoadSDNode *LD = cast<LoadSDNode>(Node); 4804 SDOperand Ch = LD->getChain(); // Legalize the chain. 4805 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 4806 ISD::LoadExtType ExtType = LD->getExtensionType(); 4807 4808 if (ExtType == ISD::NON_EXTLOAD) { 4809 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),LD->getSrcValueOffset()); 4810 if (VT == MVT::f32 || VT == MVT::f64) { 4811 // f32->i32 or f64->i64 one to one expansion. 4812 // Remember that we legalized the chain. 4813 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4814 // Recursively expand the new load. 4815 if (getTypeAction(NVT) == Expand) 4816 ExpandOp(Lo, Lo, Hi); 4817 break; 4818 } 4819 4820 // Increment the pointer to the other half. 4821 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 4822 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4823 getIntPtrConstant(IncrementSize)); 4824 // FIXME: This creates a bogus srcvalue! 4825 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),LD->getSrcValueOffset()); 4826 4827 // Build a factor node to remember that this load is independent of the 4828 // other one. 4829 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 4830 Hi.getValue(1)); 4831 4832 // Remember that we legalized the chain. 4833 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 4834 if (!TLI.isLittleEndian()) 4835 std::swap(Lo, Hi); 4836 } else { 4837 MVT::ValueType EVT = LD->getLoadedVT(); 4838 4839 if (VT == MVT::f64 && EVT == MVT::f32) { 4840 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 4841 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 4842 LD->getSrcValueOffset()); 4843 // Remember that we legalized the chain. 4844 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 4845 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 4846 break; 4847 } 4848 4849 if (EVT == NVT) 4850 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 4851 LD->getSrcValueOffset()); 4852 else 4853 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 4854 LD->getSrcValueOffset(), EVT); 4855 4856 // Remember that we legalized the chain. 4857 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4858 4859 if (ExtType == ISD::SEXTLOAD) { 4860 // The high part is obtained by SRA'ing all but one of the bits of the 4861 // lo part. 4862 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4863 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4864 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 4865 } else if (ExtType == ISD::ZEXTLOAD) { 4866 // The high part is just a zero. 4867 Hi = DAG.getConstant(0, NVT); 4868 } else /* if (ExtType == ISD::EXTLOAD) */ { 4869 // The high part is undefined. 4870 Hi = DAG.getNode(ISD::UNDEF, NVT); 4871 } 4872 } 4873 break; 4874 } 4875 case ISD::AND: 4876 case ISD::OR: 4877 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 4878 SDOperand LL, LH, RL, RH; 4879 ExpandOp(Node->getOperand(0), LL, LH); 4880 ExpandOp(Node->getOperand(1), RL, RH); 4881 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 4882 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 4883 break; 4884 } 4885 case ISD::SELECT: { 4886 SDOperand LL, LH, RL, RH; 4887 ExpandOp(Node->getOperand(1), LL, LH); 4888 ExpandOp(Node->getOperand(2), RL, RH); 4889 if (getTypeAction(NVT) == Expand) 4890 NVT = TLI.getTypeToExpandTo(NVT); 4891 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 4892 if (VT != MVT::f32) 4893 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 4894 break; 4895 } 4896 case ISD::SELECT_CC: { 4897 SDOperand TL, TH, FL, FH; 4898 ExpandOp(Node->getOperand(2), TL, TH); 4899 ExpandOp(Node->getOperand(3), FL, FH); 4900 if (getTypeAction(NVT) == Expand) 4901 NVT = TLI.getTypeToExpandTo(NVT); 4902 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4903 Node->getOperand(1), TL, FL, Node->getOperand(4)); 4904 if (VT != MVT::f32) 4905 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4906 Node->getOperand(1), TH, FH, Node->getOperand(4)); 4907 break; 4908 } 4909 case ISD::ANY_EXTEND: 4910 // The low part is any extension of the input (which degenerates to a copy). 4911 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 4912 // The high part is undefined. 4913 Hi = DAG.getNode(ISD::UNDEF, NVT); 4914 break; 4915 case ISD::SIGN_EXTEND: { 4916 // The low part is just a sign extension of the input (which degenerates to 4917 // a copy). 4918 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 4919 4920 // The high part is obtained by SRA'ing all but one of the bits of the lo 4921 // part. 4922 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4923 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4924 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 4925 break; 4926 } 4927 case ISD::ZERO_EXTEND: 4928 // The low part is just a zero extension of the input (which degenerates to 4929 // a copy). 4930 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4931 4932 // The high part is just a zero. 4933 Hi = DAG.getConstant(0, NVT); 4934 break; 4935 4936 case ISD::TRUNCATE: { 4937 // The input value must be larger than this value. Expand *it*. 4938 SDOperand NewLo; 4939 ExpandOp(Node->getOperand(0), NewLo, Hi); 4940 4941 // The low part is now either the right size, or it is closer. If not the 4942 // right size, make an illegal truncate so we recursively expand it. 4943 if (NewLo.getValueType() != Node->getValueType(0)) 4944 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 4945 ExpandOp(NewLo, Lo, Hi); 4946 break; 4947 } 4948 4949 case ISD::BIT_CONVERT: { 4950 SDOperand Tmp; 4951 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 4952 // If the target wants to, allow it to lower this itself. 4953 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4954 case Expand: assert(0 && "cannot expand FP!"); 4955 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 4956 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 4957 } 4958 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 4959 } 4960 4961 // f32 / f64 must be expanded to i32 / i64. 4962 if (VT == MVT::f32 || VT == MVT::f64) { 4963 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 4964 if (getTypeAction(NVT) == Expand) 4965 ExpandOp(Lo, Lo, Hi); 4966 break; 4967 } 4968 4969 // If source operand will be expanded to the same type as VT, i.e. 4970 // i64 <- f64, i32 <- f32, expand the source operand instead. 4971 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 4972 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 4973 ExpandOp(Node->getOperand(0), Lo, Hi); 4974 break; 4975 } 4976 4977 // Turn this into a load/store pair by default. 4978 if (Tmp.Val == 0) 4979 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0)); 4980 4981 ExpandOp(Tmp, Lo, Hi); 4982 break; 4983 } 4984 4985 case ISD::READCYCLECOUNTER: 4986 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 4987 TargetLowering::Custom && 4988 "Must custom expand ReadCycleCounter"); 4989 Lo = TLI.LowerOperation(Op, DAG); 4990 assert(Lo.Val && "Node must be custom expanded!"); 4991 Hi = Lo.getValue(1); 4992 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 4993 LegalizeOp(Lo.getValue(2))); 4994 break; 4995 4996 // These operators cannot be expanded directly, emit them as calls to 4997 // library functions. 4998 case ISD::FP_TO_SINT: { 4999 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 5000 SDOperand Op; 5001 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5002 case Expand: assert(0 && "cannot expand FP!"); 5003 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5004 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5005 } 5006 5007 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 5008 5009 // Now that the custom expander is done, expand the result, which is still 5010 // VT. 5011 if (Op.Val) { 5012 ExpandOp(Op, Lo, Hi); 5013 break; 5014 } 5015 } 5016 5017 RTLIB::Libcall LC; 5018 if (Node->getOperand(0).getValueType() == MVT::f32) 5019 LC = RTLIB::FPTOSINT_F32_I64; 5020 else 5021 LC = RTLIB::FPTOSINT_F64_I64; 5022 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5023 false/*sign irrelevant*/, Hi); 5024 break; 5025 } 5026 5027 case ISD::FP_TO_UINT: { 5028 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 5029 SDOperand Op; 5030 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5031 case Expand: assert(0 && "cannot expand FP!"); 5032 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5033 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5034 } 5035 5036 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 5037 5038 // Now that the custom expander is done, expand the result. 5039 if (Op.Val) { 5040 ExpandOp(Op, Lo, Hi); 5041 break; 5042 } 5043 } 5044 5045 RTLIB::Libcall LC; 5046 if (Node->getOperand(0).getValueType() == MVT::f32) 5047 LC = RTLIB::FPTOUINT_F32_I64; 5048 else 5049 LC = RTLIB::FPTOUINT_F64_I64; 5050 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5051 false/*sign irrelevant*/, Hi); 5052 break; 5053 } 5054 5055 case ISD::SHL: { 5056 // If the target wants custom lowering, do so. 5057 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5058 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 5059 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 5060 Op = TLI.LowerOperation(Op, DAG); 5061 if (Op.Val) { 5062 // Now that the custom expander is done, expand the result, which is 5063 // still VT. 5064 ExpandOp(Op, Lo, Hi); 5065 break; 5066 } 5067 } 5068 5069 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 5070 // this X << 1 as X+X. 5071 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 5072 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 5073 TLI.isOperationLegal(ISD::ADDE, NVT)) { 5074 SDOperand LoOps[2], HiOps[3]; 5075 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 5076 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 5077 LoOps[1] = LoOps[0]; 5078 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5079 5080 HiOps[1] = HiOps[0]; 5081 HiOps[2] = Lo.getValue(1); 5082 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5083 break; 5084 } 5085 } 5086 5087 // If we can emit an efficient shift operation, do so now. 5088 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5089 break; 5090 5091 // If this target supports SHL_PARTS, use it. 5092 TargetLowering::LegalizeAction Action = 5093 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 5094 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5095 Action == TargetLowering::Custom) { 5096 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5097 break; 5098 } 5099 5100 // Otherwise, emit a libcall. 5101 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 5102 false/*left shift=unsigned*/, Hi); 5103 break; 5104 } 5105 5106 case ISD::SRA: { 5107 // If the target wants custom lowering, do so. 5108 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5109 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 5110 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 5111 Op = TLI.LowerOperation(Op, DAG); 5112 if (Op.Val) { 5113 // Now that the custom expander is done, expand the result, which is 5114 // still VT. 5115 ExpandOp(Op, Lo, Hi); 5116 break; 5117 } 5118 } 5119 5120 // If we can emit an efficient shift operation, do so now. 5121 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5122 break; 5123 5124 // If this target supports SRA_PARTS, use it. 5125 TargetLowering::LegalizeAction Action = 5126 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 5127 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5128 Action == TargetLowering::Custom) { 5129 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5130 break; 5131 } 5132 5133 // Otherwise, emit a libcall. 5134 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 5135 true/*ashr is signed*/, Hi); 5136 break; 5137 } 5138 5139 case ISD::SRL: { 5140 // If the target wants custom lowering, do so. 5141 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5142 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 5143 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 5144 Op = TLI.LowerOperation(Op, DAG); 5145 if (Op.Val) { 5146 // Now that the custom expander is done, expand the result, which is 5147 // still VT. 5148 ExpandOp(Op, Lo, Hi); 5149 break; 5150 } 5151 } 5152 5153 // If we can emit an efficient shift operation, do so now. 5154 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5155 break; 5156 5157 // If this target supports SRL_PARTS, use it. 5158 TargetLowering::LegalizeAction Action = 5159 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 5160 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5161 Action == TargetLowering::Custom) { 5162 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5163 break; 5164 } 5165 5166 // Otherwise, emit a libcall. 5167 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 5168 false/*lshr is unsigned*/, Hi); 5169 break; 5170 } 5171 5172 case ISD::ADD: 5173 case ISD::SUB: { 5174 // If the target wants to custom expand this, let them. 5175 if (TLI.getOperationAction(Node->getOpcode(), VT) == 5176 TargetLowering::Custom) { 5177 Op = TLI.LowerOperation(Op, DAG); 5178 if (Op.Val) { 5179 ExpandOp(Op, Lo, Hi); 5180 break; 5181 } 5182 } 5183 5184 // Expand the subcomponents. 5185 SDOperand LHSL, LHSH, RHSL, RHSH; 5186 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5187 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5188 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5189 SDOperand LoOps[2], HiOps[3]; 5190 LoOps[0] = LHSL; 5191 LoOps[1] = RHSL; 5192 HiOps[0] = LHSH; 5193 HiOps[1] = RHSH; 5194 if (Node->getOpcode() == ISD::ADD) { 5195 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5196 HiOps[2] = Lo.getValue(1); 5197 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5198 } else { 5199 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5200 HiOps[2] = Lo.getValue(1); 5201 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5202 } 5203 break; 5204 } 5205 case ISD::MUL: { 5206 // If the target wants to custom expand this, let them. 5207 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 5208 SDOperand New = TLI.LowerOperation(Op, DAG); 5209 if (New.Val) { 5210 ExpandOp(New, Lo, Hi); 5211 break; 5212 } 5213 } 5214 5215 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 5216 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 5217 if (HasMULHS || HasMULHU) { 5218 SDOperand LL, LH, RL, RH; 5219 ExpandOp(Node->getOperand(0), LL, LH); 5220 ExpandOp(Node->getOperand(1), RL, RH); 5221 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 5222 // FIXME: Move this to the dag combiner. 5223 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 5224 // extended the sign bit of the low half through the upper half, and if so 5225 // emit a MULHS instead of the alternate sequence that is valid for any 5226 // i64 x i64 multiply. 5227 if (HasMULHS && 5228 // is RH an extension of the sign bit of RL? 5229 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 5230 RH.getOperand(1).getOpcode() == ISD::Constant && 5231 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 5232 // is LH an extension of the sign bit of LL? 5233 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 5234 LH.getOperand(1).getOpcode() == ISD::Constant && 5235 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 5236 // Low part: 5237 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5238 // High part: 5239 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 5240 break; 5241 } else if (HasMULHU) { 5242 // Low part: 5243 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5244 5245 // High part: 5246 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 5247 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 5248 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 5249 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 5250 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 5251 break; 5252 } 5253 } 5254 5255 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 5256 false/*sign irrelevant*/, Hi); 5257 break; 5258 } 5259 case ISD::SDIV: 5260 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 5261 break; 5262 case ISD::UDIV: 5263 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 5264 break; 5265 case ISD::SREM: 5266 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 5267 break; 5268 case ISD::UREM: 5269 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 5270 break; 5271 5272 case ISD::FADD: 5273 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5274 ? RTLIB::ADD_F32 : RTLIB::ADD_F64), 5275 Node, false, Hi); 5276 break; 5277 case ISD::FSUB: 5278 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5279 ? RTLIB::SUB_F32 : RTLIB::SUB_F64), 5280 Node, false, Hi); 5281 break; 5282 case ISD::FMUL: 5283 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5284 ? RTLIB::MUL_F32 : RTLIB::MUL_F64), 5285 Node, false, Hi); 5286 break; 5287 case ISD::FDIV: 5288 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) 5289 ? RTLIB::DIV_F32 : RTLIB::DIV_F64), 5290 Node, false, Hi); 5291 break; 5292 case ISD::FP_EXTEND: 5293 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 5294 break; 5295 case ISD::FP_ROUND: 5296 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 5297 break; 5298 case ISD::FSQRT: 5299 case ISD::FSIN: 5300 case ISD::FCOS: { 5301 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5302 switch(Node->getOpcode()) { 5303 case ISD::FSQRT: 5304 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64; 5305 break; 5306 case ISD::FSIN: 5307 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 5308 break; 5309 case ISD::FCOS: 5310 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64; 5311 break; 5312 default: assert(0 && "Unreachable!"); 5313 } 5314 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 5315 break; 5316 } 5317 case ISD::FABS: { 5318 SDOperand Mask = (VT == MVT::f64) 5319 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 5320 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 5321 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 5322 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5323 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 5324 if (getTypeAction(NVT) == Expand) 5325 ExpandOp(Lo, Lo, Hi); 5326 break; 5327 } 5328 case ISD::FNEG: { 5329 SDOperand Mask = (VT == MVT::f64) 5330 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 5331 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 5332 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 5333 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5334 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 5335 if (getTypeAction(NVT) == Expand) 5336 ExpandOp(Lo, Lo, Hi); 5337 break; 5338 } 5339 case ISD::FCOPYSIGN: { 5340 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 5341 if (getTypeAction(NVT) == Expand) 5342 ExpandOp(Lo, Lo, Hi); 5343 break; 5344 } 5345 case ISD::SINT_TO_FP: 5346 case ISD::UINT_TO_FP: { 5347 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 5348 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 5349 RTLIB::Libcall LC; 5350 if (Node->getOperand(0).getValueType() == MVT::i64) { 5351 if (VT == MVT::f32) 5352 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 5353 else 5354 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 5355 } else { 5356 if (VT == MVT::f32) 5357 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 5358 else 5359 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 5360 } 5361 5362 // Promote the operand if needed. 5363 if (getTypeAction(SrcVT) == Promote) { 5364 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 5365 Tmp = isSigned 5366 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 5367 DAG.getValueType(SrcVT)) 5368 : DAG.getZeroExtendInReg(Tmp, SrcVT); 5369 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 5370 } 5371 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 5372 break; 5373 } 5374 } 5375 5376 // Make sure the resultant values have been legalized themselves, unless this 5377 // is a type that requires multi-step expansion. 5378 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 5379 Lo = LegalizeOp(Lo); 5380 if (Hi.Val) 5381 // Don't legalize the high part if it is expanded to a single node. 5382 Hi = LegalizeOp(Hi); 5383 } 5384 5385 // Remember in a map if the values will be reused later. 5386 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 5387 assert(isNew && "Value already expanded?!?"); 5388} 5389 5390/// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 5391/// two smaller values of MVT::Vector type. 5392void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 5393 SDOperand &Hi) { 5394 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!"); 5395 SDNode *Node = Op.Val; 5396 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue(); 5397 assert(NumElements > 1 && "Cannot split a single element vector!"); 5398 unsigned NewNumElts = NumElements/2; 5399 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32); 5400 SDOperand TypeNode = *(Node->op_end()-1); 5401 5402 // See if we already split it. 5403 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5404 = SplitNodes.find(Op); 5405 if (I != SplitNodes.end()) { 5406 Lo = I->second.first; 5407 Hi = I->second.second; 5408 return; 5409 } 5410 5411 switch (Node->getOpcode()) { 5412 default: 5413#ifndef NDEBUG 5414 Node->dump(); 5415#endif 5416 assert(0 && "Unhandled operation in SplitVectorOp!"); 5417 case ISD::VBUILD_VECTOR: { 5418 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 5419 Node->op_begin()+NewNumElts); 5420 LoOps.push_back(NewNumEltsNode); 5421 LoOps.push_back(TypeNode); 5422 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size()); 5423 5424 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts, 5425 Node->op_end()-2); 5426 HiOps.push_back(NewNumEltsNode); 5427 HiOps.push_back(TypeNode); 5428 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size()); 5429 break; 5430 } 5431 case ISD::VADD: 5432 case ISD::VSUB: 5433 case ISD::VMUL: 5434 case ISD::VSDIV: 5435 case ISD::VUDIV: 5436 case ISD::VAND: 5437 case ISD::VOR: 5438 case ISD::VXOR: { 5439 SDOperand LL, LH, RL, RH; 5440 SplitVectorOp(Node->getOperand(0), LL, LH); 5441 SplitVectorOp(Node->getOperand(1), RL, RH); 5442 5443 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, 5444 NewNumEltsNode, TypeNode); 5445 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, 5446 NewNumEltsNode, TypeNode); 5447 break; 5448 } 5449 case ISD::VLOAD: { 5450 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5451 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5452 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 5453 5454 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 5455 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8; 5456 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5457 getIntPtrConstant(IncrementSize)); 5458 // FIXME: This creates a bogus srcvalue! 5459 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 5460 5461 // Build a factor node to remember that this load is independent of the 5462 // other one. 5463 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5464 Hi.getValue(1)); 5465 5466 // Remember that we legalized the chain. 5467 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5468 break; 5469 } 5470 case ISD::VBIT_CONVERT: { 5471 // We know the result is a vector. The input may be either a vector or a 5472 // scalar value. 5473 if (Op.getOperand(0).getValueType() != MVT::Vector) { 5474 // Lower to a store/load. FIXME: this could be improved probably. 5475 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType()); 5476 5477 SDOperand St = DAG.getStore(DAG.getEntryNode(), 5478 Op.getOperand(0), Ptr, NULL, 0); 5479 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 5480 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0)); 5481 SplitVectorOp(St, Lo, Hi); 5482 } else { 5483 // If the input is a vector type, we have to either scalarize it, pack it 5484 // or convert it based on whether the input vector type is legal. 5485 SDNode *InVal = Node->getOperand(0).Val; 5486 unsigned NumElems = 5487 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 5488 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 5489 5490 // If the input is from a single element vector, scalarize the vector, 5491 // then treat like a scalar. 5492 if (NumElems == 1) { 5493 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT); 5494 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar, 5495 Op.getOperand(1), Op.getOperand(2)); 5496 SplitVectorOp(Scalar, Lo, Hi); 5497 } else { 5498 // Split the input vector. 5499 SplitVectorOp(Op.getOperand(0), Lo, Hi); 5500 5501 // Convert each of the pieces now. 5502 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo, 5503 NewNumEltsNode, TypeNode); 5504 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi, 5505 NewNumEltsNode, TypeNode); 5506 } 5507 break; 5508 } 5509 } 5510 } 5511 5512 // Remember in a map if the values will be reused later. 5513 bool isNew = 5514 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 5515 assert(isNew && "Value already expanded?!?"); 5516} 5517 5518 5519/// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 5520/// equivalent operation that returns a scalar (e.g. F32) or packed value 5521/// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right 5522/// type for the result. 5523SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, 5524 MVT::ValueType NewVT) { 5525 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!"); 5526 SDNode *Node = Op.Val; 5527 5528 // See if we already packed it. 5529 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op); 5530 if (I != PackedNodes.end()) return I->second; 5531 5532 SDOperand Result; 5533 switch (Node->getOpcode()) { 5534 default: 5535#ifndef NDEBUG 5536 Node->dump(); cerr << "\n"; 5537#endif 5538 assert(0 && "Unknown vector operation in PackVectorOp!"); 5539 case ISD::VADD: 5540 case ISD::VSUB: 5541 case ISD::VMUL: 5542 case ISD::VSDIV: 5543 case ISD::VUDIV: 5544 case ISD::VAND: 5545 case ISD::VOR: 5546 case ISD::VXOR: 5547 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT), 5548 NewVT, 5549 PackVectorOp(Node->getOperand(0), NewVT), 5550 PackVectorOp(Node->getOperand(1), NewVT)); 5551 break; 5552 case ISD::VLOAD: { 5553 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 5554 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 5555 5556 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 5557 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset()); 5558 5559 // Remember that we legalized the chain. 5560 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 5561 break; 5562 } 5563 case ISD::VBUILD_VECTOR: 5564 if (Node->getOperand(0).getValueType() == NewVT) { 5565 // Returning a scalar? 5566 Result = Node->getOperand(0); 5567 } else { 5568 // Returning a BUILD_VECTOR? 5569 5570 // If all elements of the build_vector are undefs, return an undef. 5571 bool AllUndef = true; 5572 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i) 5573 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) { 5574 AllUndef = false; 5575 break; 5576 } 5577 if (AllUndef) { 5578 Result = DAG.getNode(ISD::UNDEF, NewVT); 5579 } else { 5580 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(), 5581 Node->getNumOperands()-2); 5582 } 5583 } 5584 break; 5585 case ISD::VINSERT_VECTOR_ELT: 5586 if (!MVT::isVector(NewVT)) { 5587 // Returning a scalar? Must be the inserted element. 5588 Result = Node->getOperand(1); 5589 } else { 5590 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, 5591 PackVectorOp(Node->getOperand(0), NewVT), 5592 Node->getOperand(1), Node->getOperand(2)); 5593 } 5594 break; 5595 case ISD::VVECTOR_SHUFFLE: 5596 if (!MVT::isVector(NewVT)) { 5597 // Returning a scalar? Figure out if it is the LHS or RHS and return it. 5598 SDOperand EltNum = Node->getOperand(2).getOperand(0); 5599 if (cast<ConstantSDNode>(EltNum)->getValue()) 5600 Result = PackVectorOp(Node->getOperand(1), NewVT); 5601 else 5602 Result = PackVectorOp(Node->getOperand(0), NewVT); 5603 } else { 5604 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index 5605 // vector from a VBUILD_VECTOR to a BUILD_VECTOR. 5606 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(), 5607 Node->getOperand(2).Val->op_end()-2); 5608 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size()); 5609 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, 5610 Node->getOperand(2).Val->op_begin(), 5611 Node->getOperand(2).Val->getNumOperands()-2); 5612 5613 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, 5614 PackVectorOp(Node->getOperand(0), NewVT), 5615 PackVectorOp(Node->getOperand(1), NewVT), BV); 5616 } 5617 break; 5618 case ISD::VBIT_CONVERT: 5619 if (Op.getOperand(0).getValueType() != MVT::Vector) 5620 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 5621 else { 5622 // If the input is a vector type, we have to either scalarize it, pack it 5623 // or convert it based on whether the input vector type is legal. 5624 SDNode *InVal = Node->getOperand(0).Val; 5625 unsigned NumElems = 5626 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 5627 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 5628 5629 // Figure out if there is a Packed type corresponding to this Vector 5630 // type. If so, convert to the vector type. 5631 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 5632 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 5633 // Turn this into a bit convert of the packed input. 5634 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 5635 PackVectorOp(Node->getOperand(0), TVT)); 5636 break; 5637 } else if (NumElems == 1) { 5638 // Turn this into a bit convert of the scalar input. 5639 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 5640 PackVectorOp(Node->getOperand(0), EVT)); 5641 break; 5642 } else { 5643 // FIXME: UNIMP! 5644 assert(0 && "Cast from unsupported vector type not implemented yet!"); 5645 } 5646 } 5647 break; 5648 case ISD::VSELECT: 5649 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 5650 PackVectorOp(Op.getOperand(1), NewVT), 5651 PackVectorOp(Op.getOperand(2), NewVT)); 5652 break; 5653 } 5654 5655 if (TLI.isTypeLegal(NewVT)) 5656 Result = LegalizeOp(Result); 5657 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second; 5658 assert(isNew && "Value already packed?"); 5659 return Result; 5660} 5661 5662 5663// SelectionDAG::Legalize - This is the entry point for the file. 5664// 5665void SelectionDAG::Legalize() { 5666 if (ViewLegalizeDAGs) viewGraph(); 5667 5668 /// run - This is the main entry point to this class. 5669 /// 5670 SelectionDAGLegalize(*this).LegalizeDAG(); 5671} 5672 5673