LegalizeDAG.cpp revision ca68aaa0e50c4037c0faa9bfbe7e091087837259
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/Target/TargetFrameInfo.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetMachine.h" 22#include "llvm/Target/TargetOptions.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/DerivedTypes.h" 26#include "llvm/Support/MathExtras.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Compiler.h" 29#include "llvm/ADT/DenseMap.h" 30#include "llvm/ADT/SmallVector.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include <map> 33using namespace llvm; 34 35#ifndef NDEBUG 36static cl::opt<bool> 37ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 38 cl::desc("Pop up a window to show dags before legalize")); 39#else 40static const bool ViewLegalizeDAGs = 0; 41#endif 42 43//===----------------------------------------------------------------------===// 44/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 45/// hacks on it until the target machine can handle it. This involves 46/// eliminating value sizes the machine cannot handle (promoting small sizes to 47/// large sizes or splitting up large values into small values) as well as 48/// eliminating operations the machine cannot handle. 49/// 50/// This code also does a small amount of optimization and recognition of idioms 51/// as part of its processing. For example, if a target does not support a 52/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 53/// will attempt merge setcc and brc instructions into brcc's. 54/// 55namespace { 56class VISIBILITY_HIDDEN SelectionDAGLegalize { 57 TargetLowering &TLI; 58 SelectionDAG &DAG; 59 60 // Libcall insertion helpers. 61 62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 63 /// legalized. We use this to ensure that calls are properly serialized 64 /// against each other, including inserted libcalls. 65 SDOperand LastCALLSEQ_END; 66 67 /// IsLegalizingCall - This member is used *only* for purposes of providing 68 /// helpful assertions that a libcall isn't created while another call is 69 /// being legalized (which could lead to non-serialized call sequences). 70 bool IsLegalizingCall; 71 72 enum LegalizeAction { 73 Legal, // The target natively supports this operation. 74 Promote, // This operation should be executed in a larger type. 75 Expand // Try to expand this to other ops, otherwise use a libcall. 76 }; 77 78 /// ValueTypeActions - This is a bitvector that contains two bits for each 79 /// value type, where the two bits correspond to the LegalizeAction enum. 80 /// This can be queried with "getTypeAction(VT)". 81 TargetLowering::ValueTypeActionImpl ValueTypeActions; 82 83 /// LegalizedNodes - For nodes that are of legal width, and that have more 84 /// than one use, this map indicates what regularized operand to use. This 85 /// allows us to avoid legalizing the same thing more than once. 86 DenseMap<SDOperand, SDOperand> LegalizedNodes; 87 88 /// PromotedNodes - For nodes that are below legal width, and that have more 89 /// than one use, this map indicates what promoted value to use. This allows 90 /// us to avoid promoting the same thing more than once. 91 DenseMap<SDOperand, SDOperand> PromotedNodes; 92 93 /// ExpandedNodes - For nodes that need to be expanded this map indicates 94 /// which which operands are the expanded version of the input. This allows 95 /// us to avoid expanding the same node more than once. 96 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 97 98 /// SplitNodes - For vector nodes that need to be split, this map indicates 99 /// which which operands are the split version of the input. This allows us 100 /// to avoid splitting the same node more than once. 101 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 102 103 /// ScalarizedNodes - For nodes that need to be converted from vector types to 104 /// scalar types, this contains the mapping of ones we have already 105 /// processed to the result. 106 std::map<SDOperand, SDOperand> ScalarizedNodes; 107 108 void AddLegalizedOperand(SDOperand From, SDOperand To) { 109 LegalizedNodes.insert(std::make_pair(From, To)); 110 // If someone requests legalization of the new node, return itself. 111 if (From != To) 112 LegalizedNodes.insert(std::make_pair(To, To)); 113 } 114 void AddPromotedOperand(SDOperand From, SDOperand To) { 115 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 116 assert(isNew && "Got into the map somehow?"); 117 // If someone requests legalization of the new node, return itself. 118 LegalizedNodes.insert(std::make_pair(To, To)); 119 } 120 121public: 122 123 SelectionDAGLegalize(SelectionDAG &DAG); 124 125 /// getTypeAction - Return how we should legalize values of this type, either 126 /// it is already legal or we need to expand it into multiple registers of 127 /// smaller integer type, or we need to promote it to a larger type. 128 LegalizeAction getTypeAction(MVT::ValueType VT) const { 129 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 130 } 131 132 /// isTypeLegal - Return true if this type is legal on this target. 133 /// 134 bool isTypeLegal(MVT::ValueType VT) const { 135 return getTypeAction(VT) == Legal; 136 } 137 138 void LegalizeDAG(); 139 140private: 141 /// HandleOp - Legalize, Promote, or Expand the specified operand as 142 /// appropriate for its type. 143 void HandleOp(SDOperand Op); 144 145 /// LegalizeOp - We know that the specified value has a legal type. 146 /// Recursively ensure that the operands have legal types, then return the 147 /// result. 148 SDOperand LegalizeOp(SDOperand O); 149 150 /// UnrollVectorOp - We know that the given vector has a legal type, however 151 /// the operation it performs is not legal and is an operation that we have 152 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 153 /// operating on each element individually. 154 SDOperand UnrollVectorOp(SDOperand O); 155 156 /// PromoteOp - Given an operation that produces a value in an invalid type, 157 /// promote it to compute the value into a larger type. The produced value 158 /// will have the correct bits for the low portion of the register, but no 159 /// guarantee is made about the top bits: it may be zero, sign-extended, or 160 /// garbage. 161 SDOperand PromoteOp(SDOperand O); 162 163 /// ExpandOp - Expand the specified SDOperand into its two component pieces 164 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 165 /// the LegalizeNodes map is filled in for any results that are not expanded, 166 /// the ExpandedNodes map is filled in for any results that are expanded, and 167 /// the Lo/Hi values are returned. This applies to integer types and Vector 168 /// types. 169 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 170 171 /// SplitVectorOp - Given an operand of vector type, break it down into 172 /// two smaller values. 173 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 174 175 /// ScalarizeVectorOp - Given an operand of single-element vector type 176 /// (e.g. v1f32), convert it into the equivalent operation that returns a 177 /// scalar (e.g. f32) value. 178 SDOperand ScalarizeVectorOp(SDOperand O); 179 180 /// isShuffleLegal - Return true if a vector shuffle is legal with the 181 /// specified mask and type. Targets can specify exactly which masks they 182 /// support and the code generator is tasked with not creating illegal masks. 183 /// 184 /// Note that this will also return true for shuffles that are promoted to a 185 /// different type. 186 /// 187 /// If this is a legal shuffle, this method returns the (possibly promoted) 188 /// build_vector Mask. If it's not a legal shuffle, it returns null. 189 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 190 191 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 192 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 193 194 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 195 196 SDOperand CreateStackTemporary(MVT::ValueType VT); 197 198 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 199 SDOperand &Hi); 200 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 201 SDOperand Source); 202 203 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 204 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 205 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 206 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 207 SDOperand LegalOp, 208 MVT::ValueType DestVT); 209 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 210 bool isSigned); 211 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 212 bool isSigned); 213 214 SDOperand ExpandBSWAP(SDOperand Op); 215 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 216 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 217 SDOperand &Lo, SDOperand &Hi); 218 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 219 SDOperand &Lo, SDOperand &Hi); 220 221 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 222 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 223 224 SDOperand getIntPtrConstant(uint64_t Val) { 225 return DAG.getConstant(Val, TLI.getPointerTy()); 226 } 227}; 228} 229 230/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 231/// specified mask and type. Targets can specify exactly which masks they 232/// support and the code generator is tasked with not creating illegal masks. 233/// 234/// Note that this will also return true for shuffles that are promoted to a 235/// different type. 236SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 237 SDOperand Mask) const { 238 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 239 default: return 0; 240 case TargetLowering::Legal: 241 case TargetLowering::Custom: 242 break; 243 case TargetLowering::Promote: { 244 // If this is promoted to a different type, convert the shuffle mask and 245 // ask if it is legal in the promoted type! 246 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 247 248 // If we changed # elements, change the shuffle mask. 249 unsigned NumEltsGrowth = 250 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 251 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 252 if (NumEltsGrowth > 1) { 253 // Renumber the elements. 254 SmallVector<SDOperand, 8> Ops; 255 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 256 SDOperand InOp = Mask.getOperand(i); 257 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 258 if (InOp.getOpcode() == ISD::UNDEF) 259 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 260 else { 261 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 262 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 263 } 264 } 265 } 266 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 267 } 268 VT = NVT; 269 break; 270 } 271 } 272 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 273} 274 275SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 276 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 277 ValueTypeActions(TLI.getValueTypeActions()) { 278 assert(MVT::LAST_VALUETYPE <= 32 && 279 "Too many value types for ValueTypeActions to hold!"); 280} 281 282/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 283/// contains all of a nodes operands before it contains the node. 284static void ComputeTopDownOrdering(SelectionDAG &DAG, 285 SmallVector<SDNode*, 64> &Order) { 286 287 DenseMap<SDNode*, unsigned> Visited; 288 std::vector<SDNode*> Worklist; 289 Worklist.reserve(128); 290 291 // Compute ordering from all of the leaves in the graphs, those (like the 292 // entry node) that have no operands. 293 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 294 E = DAG.allnodes_end(); I != E; ++I) { 295 if (I->getNumOperands() == 0) { 296 Visited[I] = 0 - 1U; 297 Worklist.push_back(I); 298 } 299 } 300 301 while (!Worklist.empty()) { 302 SDNode *N = Worklist.back(); 303 Worklist.pop_back(); 304 305 if (++Visited[N] != N->getNumOperands()) 306 continue; // Haven't visited all operands yet 307 308 Order.push_back(N); 309 310 // Now that we have N in, add anything that uses it if all of their operands 311 // are now done. 312 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 313 UI != E; ++UI) 314 Worklist.push_back(*UI); 315 } 316 317 assert(Order.size() == Visited.size() && 318 Order.size() == 319 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 320 "Error: DAG is cyclic!"); 321} 322 323 324void SelectionDAGLegalize::LegalizeDAG() { 325 LastCALLSEQ_END = DAG.getEntryNode(); 326 IsLegalizingCall = false; 327 328 // The legalize process is inherently a bottom-up recursive process (users 329 // legalize their uses before themselves). Given infinite stack space, we 330 // could just start legalizing on the root and traverse the whole graph. In 331 // practice however, this causes us to run out of stack space on large basic 332 // blocks. To avoid this problem, compute an ordering of the nodes where each 333 // node is only legalized after all of its operands are legalized. 334 SmallVector<SDNode*, 64> Order; 335 ComputeTopDownOrdering(DAG, Order); 336 337 for (unsigned i = 0, e = Order.size(); i != e; ++i) 338 HandleOp(SDOperand(Order[i], 0)); 339 340 // Finally, it's possible the root changed. Get the new root. 341 SDOperand OldRoot = DAG.getRoot(); 342 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 343 DAG.setRoot(LegalizedNodes[OldRoot]); 344 345 ExpandedNodes.clear(); 346 LegalizedNodes.clear(); 347 PromotedNodes.clear(); 348 SplitNodes.clear(); 349 ScalarizedNodes.clear(); 350 351 // Remove dead nodes now. 352 DAG.RemoveDeadNodes(); 353} 354 355 356/// FindCallEndFromCallStart - Given a chained node that is part of a call 357/// sequence, find the CALLSEQ_END node that terminates the call sequence. 358static SDNode *FindCallEndFromCallStart(SDNode *Node) { 359 if (Node->getOpcode() == ISD::CALLSEQ_END) 360 return Node; 361 if (Node->use_empty()) 362 return 0; // No CallSeqEnd 363 364 // The chain is usually at the end. 365 SDOperand TheChain(Node, Node->getNumValues()-1); 366 if (TheChain.getValueType() != MVT::Other) { 367 // Sometimes it's at the beginning. 368 TheChain = SDOperand(Node, 0); 369 if (TheChain.getValueType() != MVT::Other) { 370 // Otherwise, hunt for it. 371 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 372 if (Node->getValueType(i) == MVT::Other) { 373 TheChain = SDOperand(Node, i); 374 break; 375 } 376 377 // Otherwise, we walked into a node without a chain. 378 if (TheChain.getValueType() != MVT::Other) 379 return 0; 380 } 381 } 382 383 for (SDNode::use_iterator UI = Node->use_begin(), 384 E = Node->use_end(); UI != E; ++UI) { 385 386 // Make sure to only follow users of our token chain. 387 SDNode *User = *UI; 388 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 389 if (User->getOperand(i) == TheChain) 390 if (SDNode *Result = FindCallEndFromCallStart(User)) 391 return Result; 392 } 393 return 0; 394} 395 396/// FindCallStartFromCallEnd - Given a chained node that is part of a call 397/// sequence, find the CALLSEQ_START node that initiates the call sequence. 398static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 399 assert(Node && "Didn't find callseq_start for a call??"); 400 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 401 402 assert(Node->getOperand(0).getValueType() == MVT::Other && 403 "Node doesn't have a token chain argument!"); 404 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 405} 406 407/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 408/// see if any uses can reach Dest. If no dest operands can get to dest, 409/// legalize them, legalize ourself, and return false, otherwise, return true. 410/// 411/// Keep track of the nodes we fine that actually do lead to Dest in 412/// NodesLeadingTo. This avoids retraversing them exponential number of times. 413/// 414bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 415 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 416 if (N == Dest) return true; // N certainly leads to Dest :) 417 418 // If we've already processed this node and it does lead to Dest, there is no 419 // need to reprocess it. 420 if (NodesLeadingTo.count(N)) return true; 421 422 // If the first result of this node has been already legalized, then it cannot 423 // reach N. 424 switch (getTypeAction(N->getValueType(0))) { 425 case Legal: 426 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 427 break; 428 case Promote: 429 if (PromotedNodes.count(SDOperand(N, 0))) return false; 430 break; 431 case Expand: 432 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 433 break; 434 } 435 436 // Okay, this node has not already been legalized. Check and legalize all 437 // operands. If none lead to Dest, then we can legalize this node. 438 bool OperandsLeadToDest = false; 439 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 440 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 441 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 442 443 if (OperandsLeadToDest) { 444 NodesLeadingTo.insert(N); 445 return true; 446 } 447 448 // Okay, this node looks safe, legalize it and return false. 449 HandleOp(SDOperand(N, 0)); 450 return false; 451} 452 453/// HandleOp - Legalize, Promote, or Expand the specified operand as 454/// appropriate for its type. 455void SelectionDAGLegalize::HandleOp(SDOperand Op) { 456 MVT::ValueType VT = Op.getValueType(); 457 switch (getTypeAction(VT)) { 458 default: assert(0 && "Bad type action!"); 459 case Legal: (void)LegalizeOp(Op); break; 460 case Promote: (void)PromoteOp(Op); break; 461 case Expand: 462 if (!MVT::isVector(VT)) { 463 // If this is an illegal scalar, expand it into its two component 464 // pieces. 465 SDOperand X, Y; 466 if (Op.getOpcode() == ISD::TargetConstant) 467 break; // Allow illegal target nodes. 468 ExpandOp(Op, X, Y); 469 } else if (MVT::getVectorNumElements(VT) == 1) { 470 // If this is an illegal single element vector, convert it to a 471 // scalar operation. 472 (void)ScalarizeVectorOp(Op); 473 } else { 474 // Otherwise, this is an illegal multiple element vector. 475 // Split it in half and legalize both parts. 476 SDOperand X, Y; 477 SplitVectorOp(Op, X, Y); 478 } 479 break; 480 } 481} 482 483/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 484/// a load from the constant pool. 485static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 486 SelectionDAG &DAG, TargetLowering &TLI) { 487 bool Extend = false; 488 489 // If a FP immediate is precise when represented as a float and if the 490 // target can do an extending load from float to double, we put it into 491 // the constant pool as a float, even if it's is statically typed as a 492 // double. 493 MVT::ValueType VT = CFP->getValueType(0); 494 bool isDouble = VT == MVT::f64; 495 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT), 496 CFP->getValueAPF()); 497 if (!UseCP) { 498 if (VT!=MVT::f64 && VT!=MVT::f32) 499 assert(0 && "Invalid type expansion"); 500 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(), 501 isDouble ? MVT::i64 : MVT::i32); 502 } 503 504 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) && 505 // Only do this if the target has a native EXTLOAD instruction from f32. 506 // Do not try to be clever about long doubles (so far) 507 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 508 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 509 VT = MVT::f32; 510 Extend = true; 511 } 512 513 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 514 if (Extend) { 515 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 516 CPIdx, NULL, 0, MVT::f32); 517 } else { 518 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 519 } 520} 521 522 523/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 524/// operations. 525static 526SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 527 SelectionDAG &DAG, TargetLowering &TLI) { 528 MVT::ValueType VT = Node->getValueType(0); 529 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 530 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 531 "fcopysign expansion only supported for f32 and f64"); 532 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 533 534 // First get the sign bit of second operand. 535 SDOperand Mask1 = (SrcVT == MVT::f64) 536 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 537 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 538 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 539 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 540 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 541 // Shift right or sign-extend it if the two operands have different types. 542 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 543 if (SizeDiff > 0) { 544 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 545 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 546 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 547 } else if (SizeDiff < 0) 548 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 549 550 // Clear the sign bit of first operand. 551 SDOperand Mask2 = (VT == MVT::f64) 552 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 553 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 554 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 555 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 556 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 557 558 // Or the value with the sign bit. 559 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 560 return Result; 561} 562 563/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 564static 565SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 566 TargetLowering &TLI) { 567 SDOperand Chain = ST->getChain(); 568 SDOperand Ptr = ST->getBasePtr(); 569 SDOperand Val = ST->getValue(); 570 MVT::ValueType VT = Val.getValueType(); 571 int Alignment = ST->getAlignment(); 572 int SVOffset = ST->getSrcValueOffset(); 573 if (MVT::isFloatingPoint(ST->getStoredVT())) { 574 // Expand to a bitconvert of the value to the integer type of the 575 // same size, then a (misaligned) int store. 576 MVT::ValueType intVT; 577 if (VT==MVT::f64) 578 intVT = MVT::i64; 579 else if (VT==MVT::f32) 580 intVT = MVT::i32; 581 else 582 assert(0 && "Unaligned load of unsupported floating point type"); 583 584 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 585 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 586 SVOffset, ST->isVolatile(), Alignment); 587 } 588 assert(MVT::isInteger(ST->getStoredVT()) && 589 "Unaligned store of unknown type."); 590 // Get the half-size VT 591 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1; 592 int NumBits = MVT::getSizeInBits(NewStoredVT); 593 int IncrementSize = NumBits / 8; 594 595 // Divide the stored value in two parts. 596 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 597 SDOperand Lo = Val; 598 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 599 600 // Store the two parts 601 SDOperand Store1, Store2; 602 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 603 ST->getSrcValue(), SVOffset, NewStoredVT, 604 ST->isVolatile(), Alignment); 605 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 606 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 607 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 608 ST->getSrcValue(), SVOffset + IncrementSize, 609 NewStoredVT, ST->isVolatile(), Alignment); 610 611 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 612} 613 614/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 615static 616SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 617 TargetLowering &TLI) { 618 int SVOffset = LD->getSrcValueOffset(); 619 SDOperand Chain = LD->getChain(); 620 SDOperand Ptr = LD->getBasePtr(); 621 MVT::ValueType VT = LD->getValueType(0); 622 MVT::ValueType LoadedVT = LD->getLoadedVT(); 623 if (MVT::isFloatingPoint(VT)) { 624 // Expand to a (misaligned) integer load of the same size, 625 // then bitconvert to floating point. 626 MVT::ValueType intVT; 627 if (LoadedVT==MVT::f64) 628 intVT = MVT::i64; 629 else if (LoadedVT==MVT::f32) 630 intVT = MVT::i32; 631 else 632 assert(0 && "Unaligned load of unsupported floating point type"); 633 634 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 635 SVOffset, LD->isVolatile(), 636 LD->getAlignment()); 637 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 638 if (LoadedVT != VT) 639 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 640 641 SDOperand Ops[] = { Result, Chain }; 642 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 643 Ops, 2); 644 } 645 assert(MVT::isInteger(LoadedVT) && "Unaligned load of unsupported type."); 646 MVT::ValueType NewLoadedVT = LoadedVT - 1; 647 int NumBits = MVT::getSizeInBits(NewLoadedVT); 648 int Alignment = LD->getAlignment(); 649 int IncrementSize = NumBits / 8; 650 ISD::LoadExtType HiExtType = LD->getExtensionType(); 651 652 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 653 if (HiExtType == ISD::NON_EXTLOAD) 654 HiExtType = ISD::ZEXTLOAD; 655 656 // Load the value in two parts 657 SDOperand Lo, Hi; 658 if (TLI.isLittleEndian()) { 659 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 660 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 661 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 662 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 663 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 664 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 665 Alignment); 666 } else { 667 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 668 NewLoadedVT,LD->isVolatile(), Alignment); 669 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 670 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 671 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 672 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 673 Alignment); 674 } 675 676 // aggregate the two parts 677 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 678 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 679 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 680 681 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 682 Hi.getValue(1)); 683 684 SDOperand Ops[] = { Result, TF }; 685 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 686} 687 688/// UnrollVectorOp - We know that the given vector has a legal type, however 689/// the operation it performs is not legal and is an operation that we have 690/// no way of lowering. "Unroll" the vector, splitting out the scalars and 691/// operating on each element individually. 692SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 693 MVT::ValueType VT = Op.getValueType(); 694 assert(isTypeLegal(VT) && 695 "Caller should expand or promote operands that are not legal!"); 696 assert(Op.Val->getNumValues() == 1 && 697 "Can't unroll a vector with multiple results!"); 698 unsigned NE = MVT::getVectorNumElements(VT); 699 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 700 701 SmallVector<SDOperand, 8> Scalars; 702 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 703 for (unsigned i = 0; i != NE; ++i) { 704 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 705 SDOperand Operand = Op.getOperand(j); 706 MVT::ValueType OperandVT = Operand.getValueType(); 707 if (MVT::isVector(OperandVT)) { 708 // A vector operand; extract a single element. 709 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT); 710 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 711 OperandEltVT, 712 Operand, 713 DAG.getConstant(i, MVT::i32)); 714 } else { 715 // A scalar operand; just use it as is. 716 Operands[j] = Operand; 717 } 718 } 719 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 720 &Operands[0], Operands.size())); 721 } 722 723 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 724} 725 726/// LegalizeOp - We know that the specified value has a legal type, and 727/// that its operands are legal. Now ensure that the operation itself 728/// is legal, recursively ensuring that the operands' operations remain 729/// legal. 730SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 731 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 732 return Op; 733 734 assert(isTypeLegal(Op.getValueType()) && 735 "Caller should expand or promote operands that are not legal!"); 736 SDNode *Node = Op.Val; 737 738 // If this operation defines any values that cannot be represented in a 739 // register on this target, make sure to expand or promote them. 740 if (Node->getNumValues() > 1) { 741 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 742 if (getTypeAction(Node->getValueType(i)) != Legal) { 743 HandleOp(Op.getValue(i)); 744 assert(LegalizedNodes.count(Op) && 745 "Handling didn't add legal operands!"); 746 return LegalizedNodes[Op]; 747 } 748 } 749 750 // Note that LegalizeOp may be reentered even from single-use nodes, which 751 // means that we always must cache transformed nodes. 752 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 753 if (I != LegalizedNodes.end()) return I->second; 754 755 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 756 SDOperand Result = Op; 757 bool isCustom = false; 758 759 switch (Node->getOpcode()) { 760 case ISD::FrameIndex: 761 case ISD::EntryToken: 762 case ISD::Register: 763 case ISD::BasicBlock: 764 case ISD::TargetFrameIndex: 765 case ISD::TargetJumpTable: 766 case ISD::TargetConstant: 767 case ISD::TargetConstantFP: 768 case ISD::TargetConstantPool: 769 case ISD::TargetGlobalAddress: 770 case ISD::TargetGlobalTLSAddress: 771 case ISD::TargetExternalSymbol: 772 case ISD::VALUETYPE: 773 case ISD::SRCVALUE: 774 case ISD::STRING: 775 case ISD::CONDCODE: 776 // Primitives must all be legal. 777 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 778 "This must be legal!"); 779 break; 780 default: 781 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 782 // If this is a target node, legalize it by legalizing the operands then 783 // passing it through. 784 SmallVector<SDOperand, 8> Ops; 785 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 786 Ops.push_back(LegalizeOp(Node->getOperand(i))); 787 788 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 789 790 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 791 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 792 return Result.getValue(Op.ResNo); 793 } 794 // Otherwise this is an unhandled builtin node. splat. 795#ifndef NDEBUG 796 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 797#endif 798 assert(0 && "Do not know how to legalize this operator!"); 799 abort(); 800 case ISD::GLOBAL_OFFSET_TABLE: 801 case ISD::GlobalAddress: 802 case ISD::GlobalTLSAddress: 803 case ISD::ExternalSymbol: 804 case ISD::ConstantPool: 805 case ISD::JumpTable: // Nothing to do. 806 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 807 default: assert(0 && "This action is not supported yet!"); 808 case TargetLowering::Custom: 809 Tmp1 = TLI.LowerOperation(Op, DAG); 810 if (Tmp1.Val) Result = Tmp1; 811 // FALLTHROUGH if the target doesn't want to lower this op after all. 812 case TargetLowering::Legal: 813 break; 814 } 815 break; 816 case ISD::FRAMEADDR: 817 case ISD::RETURNADDR: 818 // The only option for these nodes is to custom lower them. If the target 819 // does not custom lower them, then return zero. 820 Tmp1 = TLI.LowerOperation(Op, DAG); 821 if (Tmp1.Val) 822 Result = Tmp1; 823 else 824 Result = DAG.getConstant(0, TLI.getPointerTy()); 825 break; 826 case ISD::FRAME_TO_ARGS_OFFSET: { 827 MVT::ValueType VT = Node->getValueType(0); 828 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 829 default: assert(0 && "This action is not supported yet!"); 830 case TargetLowering::Custom: 831 Result = TLI.LowerOperation(Op, DAG); 832 if (Result.Val) break; 833 // Fall Thru 834 case TargetLowering::Legal: 835 Result = DAG.getConstant(0, VT); 836 break; 837 } 838 } 839 break; 840 case ISD::EXCEPTIONADDR: { 841 Tmp1 = LegalizeOp(Node->getOperand(0)); 842 MVT::ValueType VT = Node->getValueType(0); 843 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 844 default: assert(0 && "This action is not supported yet!"); 845 case TargetLowering::Expand: { 846 unsigned Reg = TLI.getExceptionAddressRegister(); 847 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo); 848 } 849 break; 850 case TargetLowering::Custom: 851 Result = TLI.LowerOperation(Op, DAG); 852 if (Result.Val) break; 853 // Fall Thru 854 case TargetLowering::Legal: { 855 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 856 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 857 Ops, 2).getValue(Op.ResNo); 858 break; 859 } 860 } 861 } 862 break; 863 case ISD::EHSELECTION: { 864 Tmp1 = LegalizeOp(Node->getOperand(0)); 865 Tmp2 = LegalizeOp(Node->getOperand(1)); 866 MVT::ValueType VT = Node->getValueType(0); 867 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 868 default: assert(0 && "This action is not supported yet!"); 869 case TargetLowering::Expand: { 870 unsigned Reg = TLI.getExceptionSelectorRegister(); 871 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo); 872 } 873 break; 874 case TargetLowering::Custom: 875 Result = TLI.LowerOperation(Op, DAG); 876 if (Result.Val) break; 877 // Fall Thru 878 case TargetLowering::Legal: { 879 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 880 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 881 Ops, 2).getValue(Op.ResNo); 882 break; 883 } 884 } 885 } 886 break; 887 case ISD::EH_RETURN: { 888 MVT::ValueType VT = Node->getValueType(0); 889 // The only "good" option for this node is to custom lower it. 890 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 891 default: assert(0 && "This action is not supported at all!"); 892 case TargetLowering::Custom: 893 Result = TLI.LowerOperation(Op, DAG); 894 if (Result.Val) break; 895 // Fall Thru 896 case TargetLowering::Legal: 897 // Target does not know, how to lower this, lower to noop 898 Result = LegalizeOp(Node->getOperand(0)); 899 break; 900 } 901 } 902 break; 903 case ISD::AssertSext: 904 case ISD::AssertZext: 905 Tmp1 = LegalizeOp(Node->getOperand(0)); 906 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 907 break; 908 case ISD::MERGE_VALUES: 909 // Legalize eliminates MERGE_VALUES nodes. 910 Result = Node->getOperand(Op.ResNo); 911 break; 912 case ISD::CopyFromReg: 913 Tmp1 = LegalizeOp(Node->getOperand(0)); 914 Result = Op.getValue(0); 915 if (Node->getNumValues() == 2) { 916 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 917 } else { 918 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 919 if (Node->getNumOperands() == 3) { 920 Tmp2 = LegalizeOp(Node->getOperand(2)); 921 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 922 } else { 923 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 924 } 925 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 926 } 927 // Since CopyFromReg produces two values, make sure to remember that we 928 // legalized both of them. 929 AddLegalizedOperand(Op.getValue(0), Result); 930 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 931 return Result.getValue(Op.ResNo); 932 case ISD::UNDEF: { 933 MVT::ValueType VT = Op.getValueType(); 934 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 935 default: assert(0 && "This action is not supported yet!"); 936 case TargetLowering::Expand: 937 if (MVT::isInteger(VT)) 938 Result = DAG.getConstant(0, VT); 939 else if (MVT::isFloatingPoint(VT)) 940 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)), 941 VT); 942 else 943 assert(0 && "Unknown value type!"); 944 break; 945 case TargetLowering::Legal: 946 break; 947 } 948 break; 949 } 950 951 case ISD::INTRINSIC_W_CHAIN: 952 case ISD::INTRINSIC_WO_CHAIN: 953 case ISD::INTRINSIC_VOID: { 954 SmallVector<SDOperand, 8> Ops; 955 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 956 Ops.push_back(LegalizeOp(Node->getOperand(i))); 957 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 958 959 // Allow the target to custom lower its intrinsics if it wants to. 960 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 961 TargetLowering::Custom) { 962 Tmp3 = TLI.LowerOperation(Result, DAG); 963 if (Tmp3.Val) Result = Tmp3; 964 } 965 966 if (Result.Val->getNumValues() == 1) break; 967 968 // Must have return value and chain result. 969 assert(Result.Val->getNumValues() == 2 && 970 "Cannot return more than two values!"); 971 972 // Since loads produce two values, make sure to remember that we 973 // legalized both of them. 974 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 975 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 976 return Result.getValue(Op.ResNo); 977 } 978 979 case ISD::LOCATION: 980 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 981 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 982 983 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 984 case TargetLowering::Promote: 985 default: assert(0 && "This action is not supported yet!"); 986 case TargetLowering::Expand: { 987 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 988 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 989 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 990 991 if (MMI && (useDEBUG_LOC || useLABEL)) { 992 const std::string &FName = 993 cast<StringSDNode>(Node->getOperand(3))->getValue(); 994 const std::string &DirName = 995 cast<StringSDNode>(Node->getOperand(4))->getValue(); 996 unsigned SrcFile = MMI->RecordSource(DirName, FName); 997 998 SmallVector<SDOperand, 8> Ops; 999 Ops.push_back(Tmp1); // chain 1000 SDOperand LineOp = Node->getOperand(1); 1001 SDOperand ColOp = Node->getOperand(2); 1002 1003 if (useDEBUG_LOC) { 1004 Ops.push_back(LineOp); // line # 1005 Ops.push_back(ColOp); // col # 1006 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1007 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1008 } else { 1009 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 1010 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 1011 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile); 1012 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 1013 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size()); 1014 } 1015 } else { 1016 Result = Tmp1; // chain 1017 } 1018 break; 1019 } 1020 case TargetLowering::Legal: 1021 if (Tmp1 != Node->getOperand(0) || 1022 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1023 SmallVector<SDOperand, 8> Ops; 1024 Ops.push_back(Tmp1); 1025 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1026 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1027 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1028 } else { 1029 // Otherwise promote them. 1030 Ops.push_back(PromoteOp(Node->getOperand(1))); 1031 Ops.push_back(PromoteOp(Node->getOperand(2))); 1032 } 1033 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1034 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1035 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1036 } 1037 break; 1038 } 1039 break; 1040 1041 case ISD::DEBUG_LOC: 1042 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1043 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1044 default: assert(0 && "This action is not supported yet!"); 1045 case TargetLowering::Legal: 1046 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1047 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1048 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1049 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1050 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1051 break; 1052 } 1053 break; 1054 1055 case ISD::LABEL: 1056 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!"); 1057 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1058 default: assert(0 && "This action is not supported yet!"); 1059 case TargetLowering::Legal: 1060 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1061 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1062 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1063 break; 1064 case TargetLowering::Expand: 1065 Result = LegalizeOp(Node->getOperand(0)); 1066 break; 1067 } 1068 break; 1069 1070 case ISD::Constant: { 1071 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1072 unsigned opAction = 1073 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1074 1075 // We know we don't need to expand constants here, constants only have one 1076 // value and we check that it is fine above. 1077 1078 if (opAction == TargetLowering::Custom) { 1079 Tmp1 = TLI.LowerOperation(Result, DAG); 1080 if (Tmp1.Val) 1081 Result = Tmp1; 1082 } 1083 break; 1084 } 1085 case ISD::ConstantFP: { 1086 // Spill FP immediates to the constant pool if the target cannot directly 1087 // codegen them. Targets often have some immediate values that can be 1088 // efficiently generated into an FP register without a load. We explicitly 1089 // leave these constants as ConstantFP nodes for the target to deal with. 1090 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1091 1092 // Check to see if this FP immediate is already legal. 1093 bool isLegal = false; 1094 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1095 E = TLI.legal_fpimm_end(); I != E; ++I) 1096 if (CFP->isExactlyValue(*I)) { 1097 isLegal = true; 1098 break; 1099 } 1100 1101 // If this is a legal constant, turn it into a TargetConstantFP node. 1102 if (isLegal) { 1103 Result = DAG.getTargetConstantFP(CFP->getValueAPF(), 1104 CFP->getValueType(0)); 1105 break; 1106 } 1107 1108 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1109 default: assert(0 && "This action is not supported yet!"); 1110 case TargetLowering::Custom: 1111 Tmp3 = TLI.LowerOperation(Result, DAG); 1112 if (Tmp3.Val) { 1113 Result = Tmp3; 1114 break; 1115 } 1116 // FALLTHROUGH 1117 case TargetLowering::Expand: 1118 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1119 } 1120 break; 1121 } 1122 case ISD::TokenFactor: 1123 if (Node->getNumOperands() == 2) { 1124 Tmp1 = LegalizeOp(Node->getOperand(0)); 1125 Tmp2 = LegalizeOp(Node->getOperand(1)); 1126 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1127 } else if (Node->getNumOperands() == 3) { 1128 Tmp1 = LegalizeOp(Node->getOperand(0)); 1129 Tmp2 = LegalizeOp(Node->getOperand(1)); 1130 Tmp3 = LegalizeOp(Node->getOperand(2)); 1131 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1132 } else { 1133 SmallVector<SDOperand, 8> Ops; 1134 // Legalize the operands. 1135 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1136 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1137 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1138 } 1139 break; 1140 1141 case ISD::FORMAL_ARGUMENTS: 1142 case ISD::CALL: 1143 // The only option for this is to custom lower it. 1144 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1145 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1146 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() && 1147 "Lowering call/formal_arguments produced unexpected # results!"); 1148 1149 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1150 // remember that we legalized all of them, so it doesn't get relegalized. 1151 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1152 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1153 if (Op.ResNo == i) 1154 Tmp2 = Tmp1; 1155 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1156 } 1157 return Tmp2; 1158 case ISD::EXTRACT_SUBREG: { 1159 Tmp1 = LegalizeOp(Node->getOperand(0)); 1160 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1161 assert(idx && "Operand must be a constant"); 1162 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1163 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1164 } 1165 break; 1166 case ISD::INSERT_SUBREG: { 1167 Tmp1 = LegalizeOp(Node->getOperand(0)); 1168 Tmp2 = LegalizeOp(Node->getOperand(1)); 1169 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1170 assert(idx && "Operand must be a constant"); 1171 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1172 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1173 } 1174 break; 1175 case ISD::BUILD_VECTOR: 1176 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1177 default: assert(0 && "This action is not supported yet!"); 1178 case TargetLowering::Custom: 1179 Tmp3 = TLI.LowerOperation(Result, DAG); 1180 if (Tmp3.Val) { 1181 Result = Tmp3; 1182 break; 1183 } 1184 // FALLTHROUGH 1185 case TargetLowering::Expand: 1186 Result = ExpandBUILD_VECTOR(Result.Val); 1187 break; 1188 } 1189 break; 1190 case ISD::INSERT_VECTOR_ELT: 1191 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1192 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 1193 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1194 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1195 1196 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1197 Node->getValueType(0))) { 1198 default: assert(0 && "This action is not supported yet!"); 1199 case TargetLowering::Legal: 1200 break; 1201 case TargetLowering::Custom: 1202 Tmp3 = TLI.LowerOperation(Result, DAG); 1203 if (Tmp3.Val) { 1204 Result = Tmp3; 1205 break; 1206 } 1207 // FALLTHROUGH 1208 case TargetLowering::Expand: { 1209 // If the insert index is a constant, codegen this as a scalar_to_vector, 1210 // then a shuffle that inserts it into the right position in the vector. 1211 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1212 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1213 Tmp1.getValueType(), Tmp2); 1214 1215 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1216 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1217 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1218 1219 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 1220 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 1221 // the RHS. 1222 SmallVector<SDOperand, 8> ShufOps; 1223 for (unsigned i = 0; i != NumElts; ++i) { 1224 if (i != InsertPos->getValue()) 1225 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1226 else 1227 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1228 } 1229 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1230 &ShufOps[0], ShufOps.size()); 1231 1232 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1233 Tmp1, ScVec, ShufMask); 1234 Result = LegalizeOp(Result); 1235 break; 1236 } 1237 1238 // If the target doesn't support this, we have to spill the input vector 1239 // to a temporary stack slot, update the element, then reload it. This is 1240 // badness. We could also load the value into a vector register (either 1241 // with a "move to register" or "extload into register" instruction, then 1242 // permute it into place, if the idx is a constant and if the idx is 1243 // supported by the target. 1244 MVT::ValueType VT = Tmp1.getValueType(); 1245 MVT::ValueType EltVT = Tmp2.getValueType(); 1246 MVT::ValueType IdxVT = Tmp3.getValueType(); 1247 MVT::ValueType PtrVT = TLI.getPointerTy(); 1248 SDOperand StackPtr = CreateStackTemporary(VT); 1249 // Store the vector. 1250 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); 1251 1252 // Truncate or zero extend offset to target pointer type. 1253 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1254 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1255 // Add the offset to the index. 1256 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1257 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1258 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1259 // Store the scalar value. 1260 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); 1261 // Load the updated vector. 1262 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 1263 break; 1264 } 1265 } 1266 break; 1267 case ISD::SCALAR_TO_VECTOR: 1268 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1269 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1270 break; 1271 } 1272 1273 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1274 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1275 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1276 Node->getValueType(0))) { 1277 default: assert(0 && "This action is not supported yet!"); 1278 case TargetLowering::Legal: 1279 break; 1280 case TargetLowering::Custom: 1281 Tmp3 = TLI.LowerOperation(Result, DAG); 1282 if (Tmp3.Val) { 1283 Result = Tmp3; 1284 break; 1285 } 1286 // FALLTHROUGH 1287 case TargetLowering::Expand: 1288 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1289 break; 1290 } 1291 break; 1292 case ISD::VECTOR_SHUFFLE: 1293 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1294 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1295 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1296 1297 // Allow targets to custom lower the SHUFFLEs they support. 1298 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1299 default: assert(0 && "Unknown operation action!"); 1300 case TargetLowering::Legal: 1301 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1302 "vector shuffle should not be created if not legal!"); 1303 break; 1304 case TargetLowering::Custom: 1305 Tmp3 = TLI.LowerOperation(Result, DAG); 1306 if (Tmp3.Val) { 1307 Result = Tmp3; 1308 break; 1309 } 1310 // FALLTHROUGH 1311 case TargetLowering::Expand: { 1312 MVT::ValueType VT = Node->getValueType(0); 1313 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1314 MVT::ValueType PtrVT = TLI.getPointerTy(); 1315 SDOperand Mask = Node->getOperand(2); 1316 unsigned NumElems = Mask.getNumOperands(); 1317 SmallVector<SDOperand,8> Ops; 1318 for (unsigned i = 0; i != NumElems; ++i) { 1319 SDOperand Arg = Mask.getOperand(i); 1320 if (Arg.getOpcode() == ISD::UNDEF) { 1321 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1322 } else { 1323 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1324 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1325 if (Idx < NumElems) 1326 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1327 DAG.getConstant(Idx, PtrVT))); 1328 else 1329 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1330 DAG.getConstant(Idx - NumElems, PtrVT))); 1331 } 1332 } 1333 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1334 break; 1335 } 1336 case TargetLowering::Promote: { 1337 // Change base type to a different vector type. 1338 MVT::ValueType OVT = Node->getValueType(0); 1339 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1340 1341 // Cast the two input vectors. 1342 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1343 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1344 1345 // Convert the shuffle mask to the right # elements. 1346 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1347 assert(Tmp3.Val && "Shuffle not legal?"); 1348 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1349 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1350 break; 1351 } 1352 } 1353 break; 1354 1355 case ISD::EXTRACT_VECTOR_ELT: 1356 Tmp1 = Node->getOperand(0); 1357 Tmp2 = LegalizeOp(Node->getOperand(1)); 1358 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1359 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1360 break; 1361 1362 case ISD::EXTRACT_SUBVECTOR: 1363 Tmp1 = Node->getOperand(0); 1364 Tmp2 = LegalizeOp(Node->getOperand(1)); 1365 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1366 Result = ExpandEXTRACT_SUBVECTOR(Result); 1367 break; 1368 1369 case ISD::CALLSEQ_START: { 1370 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1371 1372 // Recursively Legalize all of the inputs of the call end that do not lead 1373 // to this call start. This ensures that any libcalls that need be inserted 1374 // are inserted *before* the CALLSEQ_START. 1375 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1376 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1377 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1378 NodesLeadingTo); 1379 } 1380 1381 // Now that we legalized all of the inputs (which may have inserted 1382 // libcalls) create the new CALLSEQ_START node. 1383 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1384 1385 // Merge in the last call, to ensure that this call start after the last 1386 // call ended. 1387 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1388 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1389 Tmp1 = LegalizeOp(Tmp1); 1390 } 1391 1392 // Do not try to legalize the target-specific arguments (#1+). 1393 if (Tmp1 != Node->getOperand(0)) { 1394 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1395 Ops[0] = Tmp1; 1396 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1397 } 1398 1399 // Remember that the CALLSEQ_START is legalized. 1400 AddLegalizedOperand(Op.getValue(0), Result); 1401 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1402 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1403 1404 // Now that the callseq_start and all of the non-call nodes above this call 1405 // sequence have been legalized, legalize the call itself. During this 1406 // process, no libcalls can/will be inserted, guaranteeing that no calls 1407 // can overlap. 1408 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1409 SDOperand InCallSEQ = LastCALLSEQ_END; 1410 // Note that we are selecting this call! 1411 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1412 IsLegalizingCall = true; 1413 1414 // Legalize the call, starting from the CALLSEQ_END. 1415 LegalizeOp(LastCALLSEQ_END); 1416 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1417 return Result; 1418 } 1419 case ISD::CALLSEQ_END: 1420 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1421 // will cause this node to be legalized as well as handling libcalls right. 1422 if (LastCALLSEQ_END.Val != Node) { 1423 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1424 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1425 assert(I != LegalizedNodes.end() && 1426 "Legalizing the call start should have legalized this node!"); 1427 return I->second; 1428 } 1429 1430 // Otherwise, the call start has been legalized and everything is going 1431 // according to plan. Just legalize ourselves normally here. 1432 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1433 // Do not try to legalize the target-specific arguments (#1+), except for 1434 // an optional flag input. 1435 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1436 if (Tmp1 != Node->getOperand(0)) { 1437 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1438 Ops[0] = Tmp1; 1439 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1440 } 1441 } else { 1442 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1443 if (Tmp1 != Node->getOperand(0) || 1444 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1445 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1446 Ops[0] = Tmp1; 1447 Ops.back() = Tmp2; 1448 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1449 } 1450 } 1451 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1452 // This finishes up call legalization. 1453 IsLegalizingCall = false; 1454 1455 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1456 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1457 if (Node->getNumValues() == 2) 1458 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1459 return Result.getValue(Op.ResNo); 1460 case ISD::DYNAMIC_STACKALLOC: { 1461 MVT::ValueType VT = Node->getValueType(0); 1462 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1463 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1464 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1465 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1466 1467 Tmp1 = Result.getValue(0); 1468 Tmp2 = Result.getValue(1); 1469 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1470 default: assert(0 && "This action is not supported yet!"); 1471 case TargetLowering::Expand: { 1472 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1473 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1474 " not tell us which reg is the stack pointer!"); 1475 SDOperand Chain = Tmp1.getOperand(0); 1476 SDOperand Size = Tmp2.getOperand(1); 1477 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1478 Chain = SP.getValue(1); 1479 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1480 unsigned StackAlign = 1481 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1482 if (Align > StackAlign) 1483 SP = DAG.getNode(ISD::AND, VT, SP, 1484 DAG.getConstant(-(uint64_t)Align, VT)); 1485 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1486 Tmp2 = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1487 Tmp1 = LegalizeOp(Tmp1); 1488 Tmp2 = LegalizeOp(Tmp2); 1489 break; 1490 } 1491 case TargetLowering::Custom: 1492 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1493 if (Tmp3.Val) { 1494 Tmp1 = LegalizeOp(Tmp3); 1495 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1496 } 1497 break; 1498 case TargetLowering::Legal: 1499 break; 1500 } 1501 // Since this op produce two values, make sure to remember that we 1502 // legalized both of them. 1503 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1504 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1505 return Op.ResNo ? Tmp2 : Tmp1; 1506 } 1507 case ISD::INLINEASM: { 1508 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1509 bool Changed = false; 1510 // Legalize all of the operands of the inline asm, in case they are nodes 1511 // that need to be expanded or something. Note we skip the asm string and 1512 // all of the TargetConstant flags. 1513 SDOperand Op = LegalizeOp(Ops[0]); 1514 Changed = Op != Ops[0]; 1515 Ops[0] = Op; 1516 1517 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1518 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1519 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1520 for (++i; NumVals; ++i, --NumVals) { 1521 SDOperand Op = LegalizeOp(Ops[i]); 1522 if (Op != Ops[i]) { 1523 Changed = true; 1524 Ops[i] = Op; 1525 } 1526 } 1527 } 1528 1529 if (HasInFlag) { 1530 Op = LegalizeOp(Ops.back()); 1531 Changed |= Op != Ops.back(); 1532 Ops.back() = Op; 1533 } 1534 1535 if (Changed) 1536 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1537 1538 // INLINE asm returns a chain and flag, make sure to add both to the map. 1539 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1540 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1541 return Result.getValue(Op.ResNo); 1542 } 1543 case ISD::BR: 1544 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1545 // Ensure that libcalls are emitted before a branch. 1546 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1547 Tmp1 = LegalizeOp(Tmp1); 1548 LastCALLSEQ_END = DAG.getEntryNode(); 1549 1550 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1551 break; 1552 case ISD::BRIND: 1553 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1554 // Ensure that libcalls are emitted before a branch. 1555 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1556 Tmp1 = LegalizeOp(Tmp1); 1557 LastCALLSEQ_END = DAG.getEntryNode(); 1558 1559 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1560 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1561 case Legal: 1562 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1563 break; 1564 } 1565 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1566 break; 1567 case ISD::BR_JT: 1568 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1569 // Ensure that libcalls are emitted before a branch. 1570 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1571 Tmp1 = LegalizeOp(Tmp1); 1572 LastCALLSEQ_END = DAG.getEntryNode(); 1573 1574 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1575 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1576 1577 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1578 default: assert(0 && "This action is not supported yet!"); 1579 case TargetLowering::Legal: break; 1580 case TargetLowering::Custom: 1581 Tmp1 = TLI.LowerOperation(Result, DAG); 1582 if (Tmp1.Val) Result = Tmp1; 1583 break; 1584 case TargetLowering::Expand: { 1585 SDOperand Chain = Result.getOperand(0); 1586 SDOperand Table = Result.getOperand(1); 1587 SDOperand Index = Result.getOperand(2); 1588 1589 MVT::ValueType PTy = TLI.getPointerTy(); 1590 MachineFunction &MF = DAG.getMachineFunction(); 1591 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1592 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1593 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1594 1595 SDOperand LD; 1596 switch (EntrySize) { 1597 default: assert(0 && "Size of jump table not supported yet."); break; 1598 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; 1599 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; 1600 } 1601 1602 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1603 // For PIC, the sequence is: 1604 // BRIND(load(Jumptable + index) + RelocBase) 1605 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha 1606 SDOperand Reloc; 1607 if (TLI.usesGlobalOffsetTable()) 1608 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy); 1609 else 1610 Reloc = Table; 1611 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD; 1612 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc); 1613 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1614 } else { 1615 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD); 1616 } 1617 } 1618 } 1619 break; 1620 case ISD::BRCOND: 1621 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1622 // Ensure that libcalls are emitted before a return. 1623 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1624 Tmp1 = LegalizeOp(Tmp1); 1625 LastCALLSEQ_END = DAG.getEntryNode(); 1626 1627 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1628 case Expand: assert(0 && "It's impossible to expand bools"); 1629 case Legal: 1630 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1631 break; 1632 case Promote: 1633 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1634 1635 // The top bits of the promoted condition are not necessarily zero, ensure 1636 // that the value is properly zero extended. 1637 if (!DAG.MaskedValueIsZero(Tmp2, 1638 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1639 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1640 break; 1641 } 1642 1643 // Basic block destination (Op#2) is always legal. 1644 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1645 1646 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1647 default: assert(0 && "This action is not supported yet!"); 1648 case TargetLowering::Legal: break; 1649 case TargetLowering::Custom: 1650 Tmp1 = TLI.LowerOperation(Result, DAG); 1651 if (Tmp1.Val) Result = Tmp1; 1652 break; 1653 case TargetLowering::Expand: 1654 // Expand brcond's setcc into its constituent parts and create a BR_CC 1655 // Node. 1656 if (Tmp2.getOpcode() == ISD::SETCC) { 1657 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1658 Tmp2.getOperand(0), Tmp2.getOperand(1), 1659 Node->getOperand(2)); 1660 } else { 1661 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1662 DAG.getCondCode(ISD::SETNE), Tmp2, 1663 DAG.getConstant(0, Tmp2.getValueType()), 1664 Node->getOperand(2)); 1665 } 1666 break; 1667 } 1668 break; 1669 case ISD::BR_CC: 1670 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1671 // Ensure that libcalls are emitted before a branch. 1672 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1673 Tmp1 = LegalizeOp(Tmp1); 1674 Tmp2 = Node->getOperand(2); // LHS 1675 Tmp3 = Node->getOperand(3); // RHS 1676 Tmp4 = Node->getOperand(1); // CC 1677 1678 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1679 LastCALLSEQ_END = DAG.getEntryNode(); 1680 1681 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1682 // the LHS is a legal SETCC itself. In this case, we need to compare 1683 // the result against zero to select between true and false values. 1684 if (Tmp3.Val == 0) { 1685 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1686 Tmp4 = DAG.getCondCode(ISD::SETNE); 1687 } 1688 1689 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1690 Node->getOperand(4)); 1691 1692 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1693 default: assert(0 && "Unexpected action for BR_CC!"); 1694 case TargetLowering::Legal: break; 1695 case TargetLowering::Custom: 1696 Tmp4 = TLI.LowerOperation(Result, DAG); 1697 if (Tmp4.Val) Result = Tmp4; 1698 break; 1699 } 1700 break; 1701 case ISD::LOAD: { 1702 LoadSDNode *LD = cast<LoadSDNode>(Node); 1703 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1704 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1705 1706 ISD::LoadExtType ExtType = LD->getExtensionType(); 1707 if (ExtType == ISD::NON_EXTLOAD) { 1708 MVT::ValueType VT = Node->getValueType(0); 1709 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1710 Tmp3 = Result.getValue(0); 1711 Tmp4 = Result.getValue(1); 1712 1713 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1714 default: assert(0 && "This action is not supported yet!"); 1715 case TargetLowering::Legal: 1716 // If this is an unaligned load and the target doesn't support it, 1717 // expand it. 1718 if (!TLI.allowsUnalignedMemoryAccesses()) { 1719 unsigned ABIAlignment = TLI.getTargetData()-> 1720 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1721 if (LD->getAlignment() < ABIAlignment){ 1722 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1723 TLI); 1724 Tmp3 = Result.getOperand(0); 1725 Tmp4 = Result.getOperand(1); 1726 Tmp3 = LegalizeOp(Tmp3); 1727 Tmp4 = LegalizeOp(Tmp4); 1728 } 1729 } 1730 break; 1731 case TargetLowering::Custom: 1732 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1733 if (Tmp1.Val) { 1734 Tmp3 = LegalizeOp(Tmp1); 1735 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1736 } 1737 break; 1738 case TargetLowering::Promote: { 1739 // Only promote a load of vector type to another. 1740 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1741 // Change base type to a different vector type. 1742 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1743 1744 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1745 LD->getSrcValueOffset(), 1746 LD->isVolatile(), LD->getAlignment()); 1747 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1748 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1749 break; 1750 } 1751 } 1752 // Since loads produce two values, make sure to remember that we 1753 // legalized both of them. 1754 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1755 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1756 return Op.ResNo ? Tmp4 : Tmp3; 1757 } else { 1758 MVT::ValueType SrcVT = LD->getLoadedVT(); 1759 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1760 default: assert(0 && "This action is not supported yet!"); 1761 case TargetLowering::Promote: 1762 assert(SrcVT == MVT::i1 && 1763 "Can only promote extending LOAD from i1 -> i8!"); 1764 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1765 LD->getSrcValue(), LD->getSrcValueOffset(), 1766 MVT::i8, LD->isVolatile(), LD->getAlignment()); 1767 Tmp1 = Result.getValue(0); 1768 Tmp2 = Result.getValue(1); 1769 break; 1770 case TargetLowering::Custom: 1771 isCustom = true; 1772 // FALLTHROUGH 1773 case TargetLowering::Legal: 1774 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1775 Tmp1 = Result.getValue(0); 1776 Tmp2 = Result.getValue(1); 1777 1778 if (isCustom) { 1779 Tmp3 = TLI.LowerOperation(Result, DAG); 1780 if (Tmp3.Val) { 1781 Tmp1 = LegalizeOp(Tmp3); 1782 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1783 } 1784 } else { 1785 // If this is an unaligned load and the target doesn't support it, 1786 // expand it. 1787 if (!TLI.allowsUnalignedMemoryAccesses()) { 1788 unsigned ABIAlignment = TLI.getTargetData()-> 1789 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1790 if (LD->getAlignment() < ABIAlignment){ 1791 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1792 TLI); 1793 Tmp1 = Result.getOperand(0); 1794 Tmp2 = Result.getOperand(1); 1795 Tmp1 = LegalizeOp(Tmp1); 1796 Tmp2 = LegalizeOp(Tmp2); 1797 } 1798 } 1799 } 1800 break; 1801 case TargetLowering::Expand: 1802 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1803 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1804 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1805 LD->getSrcValueOffset(), 1806 LD->isVolatile(), LD->getAlignment()); 1807 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1808 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1809 Tmp2 = LegalizeOp(Load.getValue(1)); 1810 break; 1811 } 1812 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1813 // Turn the unsupported load into an EXTLOAD followed by an explicit 1814 // zero/sign extend inreg. 1815 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1816 Tmp1, Tmp2, LD->getSrcValue(), 1817 LD->getSrcValueOffset(), SrcVT, 1818 LD->isVolatile(), LD->getAlignment()); 1819 SDOperand ValRes; 1820 if (ExtType == ISD::SEXTLOAD) 1821 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1822 Result, DAG.getValueType(SrcVT)); 1823 else 1824 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1825 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1826 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1827 break; 1828 } 1829 // Since loads produce two values, make sure to remember that we legalized 1830 // both of them. 1831 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1832 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1833 return Op.ResNo ? Tmp2 : Tmp1; 1834 } 1835 } 1836 case ISD::EXTRACT_ELEMENT: { 1837 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1838 switch (getTypeAction(OpTy)) { 1839 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1840 case Legal: 1841 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1842 // 1 -> Hi 1843 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1844 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1845 TLI.getShiftAmountTy())); 1846 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1847 } else { 1848 // 0 -> Lo 1849 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1850 Node->getOperand(0)); 1851 } 1852 break; 1853 case Expand: 1854 // Get both the low and high parts. 1855 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1856 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1857 Result = Tmp2; // 1 -> Hi 1858 else 1859 Result = Tmp1; // 0 -> Lo 1860 break; 1861 } 1862 break; 1863 } 1864 1865 case ISD::CopyToReg: 1866 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1867 1868 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1869 "Register type must be legal!"); 1870 // Legalize the incoming value (must be a legal type). 1871 Tmp2 = LegalizeOp(Node->getOperand(2)); 1872 if (Node->getNumValues() == 1) { 1873 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1874 } else { 1875 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1876 if (Node->getNumOperands() == 4) { 1877 Tmp3 = LegalizeOp(Node->getOperand(3)); 1878 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1879 Tmp3); 1880 } else { 1881 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1882 } 1883 1884 // Since this produces two values, make sure to remember that we legalized 1885 // both of them. 1886 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1887 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1888 return Result; 1889 } 1890 break; 1891 1892 case ISD::RET: 1893 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1894 1895 // Ensure that libcalls are emitted before a return. 1896 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1897 Tmp1 = LegalizeOp(Tmp1); 1898 LastCALLSEQ_END = DAG.getEntryNode(); 1899 1900 switch (Node->getNumOperands()) { 1901 case 3: // ret val 1902 Tmp2 = Node->getOperand(1); 1903 Tmp3 = Node->getOperand(2); // Signness 1904 switch (getTypeAction(Tmp2.getValueType())) { 1905 case Legal: 1906 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1907 break; 1908 case Expand: 1909 if (!MVT::isVector(Tmp2.getValueType())) { 1910 SDOperand Lo, Hi; 1911 ExpandOp(Tmp2, Lo, Hi); 1912 1913 // Big endian systems want the hi reg first. 1914 if (!TLI.isLittleEndian()) 1915 std::swap(Lo, Hi); 1916 1917 if (Hi.Val) 1918 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1919 else 1920 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 1921 Result = LegalizeOp(Result); 1922 } else { 1923 SDNode *InVal = Tmp2.Val; 1924 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 1925 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 1926 1927 // Figure out if there is a simple type corresponding to this Vector 1928 // type. If so, convert to the vector type. 1929 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1930 if (TLI.isTypeLegal(TVT)) { 1931 // Turn this into a return of the vector type. 1932 Tmp2 = LegalizeOp(Tmp2); 1933 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1934 } else if (NumElems == 1) { 1935 // Turn this into a return of the scalar type. 1936 Tmp2 = ScalarizeVectorOp(Tmp2); 1937 Tmp2 = LegalizeOp(Tmp2); 1938 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1939 1940 // FIXME: Returns of gcc generic vectors smaller than a legal type 1941 // should be returned in integer registers! 1942 1943 // The scalarized value type may not be legal, e.g. it might require 1944 // promotion or expansion. Relegalize the return. 1945 Result = LegalizeOp(Result); 1946 } else { 1947 // FIXME: Returns of gcc generic vectors larger than a legal vector 1948 // type should be returned by reference! 1949 SDOperand Lo, Hi; 1950 SplitVectorOp(Tmp2, Lo, Hi); 1951 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1952 Result = LegalizeOp(Result); 1953 } 1954 } 1955 break; 1956 case Promote: 1957 Tmp2 = PromoteOp(Node->getOperand(1)); 1958 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1959 Result = LegalizeOp(Result); 1960 break; 1961 } 1962 break; 1963 case 1: // ret void 1964 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1965 break; 1966 default: { // ret <values> 1967 SmallVector<SDOperand, 8> NewValues; 1968 NewValues.push_back(Tmp1); 1969 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 1970 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1971 case Legal: 1972 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1973 NewValues.push_back(Node->getOperand(i+1)); 1974 break; 1975 case Expand: { 1976 SDOperand Lo, Hi; 1977 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && 1978 "FIXME: TODO: implement returning non-legal vector types!"); 1979 ExpandOp(Node->getOperand(i), Lo, Hi); 1980 NewValues.push_back(Lo); 1981 NewValues.push_back(Node->getOperand(i+1)); 1982 if (Hi.Val) { 1983 NewValues.push_back(Hi); 1984 NewValues.push_back(Node->getOperand(i+1)); 1985 } 1986 break; 1987 } 1988 case Promote: 1989 assert(0 && "Can't promote multiple return value yet!"); 1990 } 1991 1992 if (NewValues.size() == Node->getNumOperands()) 1993 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 1994 else 1995 Result = DAG.getNode(ISD::RET, MVT::Other, 1996 &NewValues[0], NewValues.size()); 1997 break; 1998 } 1999 } 2000 2001 if (Result.getOpcode() == ISD::RET) { 2002 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2003 default: assert(0 && "This action is not supported yet!"); 2004 case TargetLowering::Legal: break; 2005 case TargetLowering::Custom: 2006 Tmp1 = TLI.LowerOperation(Result, DAG); 2007 if (Tmp1.Val) Result = Tmp1; 2008 break; 2009 } 2010 } 2011 break; 2012 case ISD::STORE: { 2013 StoreSDNode *ST = cast<StoreSDNode>(Node); 2014 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2015 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2016 int SVOffset = ST->getSrcValueOffset(); 2017 unsigned Alignment = ST->getAlignment(); 2018 bool isVolatile = ST->isVolatile(); 2019 2020 if (!ST->isTruncatingStore()) { 2021 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2022 // FIXME: We shouldn't do this for TargetConstantFP's. 2023 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2024 // to phase ordering between legalized code and the dag combiner. This 2025 // probably means that we need to integrate dag combiner and legalizer 2026 // together. 2027 // We generally can't do this one for long doubles. 2028 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2029 if (CFP->getValueType(0) == MVT::f32) { 2030 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF(). 2031 convertToAPInt().getZExtValue(), 2032 MVT::i32); 2033 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2034 SVOffset, isVolatile, Alignment); 2035 break; 2036 } else if (CFP->getValueType(0) == MVT::f64) { 2037 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2038 getZExtValue(), MVT::i64); 2039 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2040 SVOffset, isVolatile, Alignment); 2041 break; 2042 } 2043 } 2044 2045 switch (getTypeAction(ST->getStoredVT())) { 2046 case Legal: { 2047 Tmp3 = LegalizeOp(ST->getValue()); 2048 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2049 ST->getOffset()); 2050 2051 MVT::ValueType VT = Tmp3.getValueType(); 2052 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2053 default: assert(0 && "This action is not supported yet!"); 2054 case TargetLowering::Legal: 2055 // If this is an unaligned store and the target doesn't support it, 2056 // expand it. 2057 if (!TLI.allowsUnalignedMemoryAccesses()) { 2058 unsigned ABIAlignment = TLI.getTargetData()-> 2059 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2060 if (ST->getAlignment() < ABIAlignment) 2061 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2062 TLI); 2063 } 2064 break; 2065 case TargetLowering::Custom: 2066 Tmp1 = TLI.LowerOperation(Result, DAG); 2067 if (Tmp1.Val) Result = Tmp1; 2068 break; 2069 case TargetLowering::Promote: 2070 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 2071 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2072 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2073 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2074 ST->getSrcValue(), SVOffset, isVolatile, 2075 Alignment); 2076 break; 2077 } 2078 break; 2079 } 2080 case Promote: 2081 // Truncate the value and store the result. 2082 Tmp3 = PromoteOp(ST->getValue()); 2083 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2084 SVOffset, ST->getStoredVT(), 2085 isVolatile, Alignment); 2086 break; 2087 2088 case Expand: 2089 unsigned IncrementSize = 0; 2090 SDOperand Lo, Hi; 2091 2092 // If this is a vector type, then we have to calculate the increment as 2093 // the product of the element size in bytes, and the number of elements 2094 // in the high half of the vector. 2095 if (MVT::isVector(ST->getValue().getValueType())) { 2096 SDNode *InVal = ST->getValue().Val; 2097 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 2098 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 2099 2100 // Figure out if there is a simple type corresponding to this Vector 2101 // type. If so, convert to the vector type. 2102 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2103 if (TLI.isTypeLegal(TVT)) { 2104 // Turn this into a normal store of the vector type. 2105 Tmp3 = LegalizeOp(Node->getOperand(1)); 2106 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2107 SVOffset, isVolatile, Alignment); 2108 Result = LegalizeOp(Result); 2109 break; 2110 } else if (NumElems == 1) { 2111 // Turn this into a normal store of the scalar type. 2112 Tmp3 = ScalarizeVectorOp(Node->getOperand(1)); 2113 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2114 SVOffset, isVolatile, Alignment); 2115 // The scalarized value type may not be legal, e.g. it might require 2116 // promotion or expansion. Relegalize the scalar store. 2117 Result = LegalizeOp(Result); 2118 break; 2119 } else { 2120 SplitVectorOp(Node->getOperand(1), Lo, Hi); 2121 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 2122 } 2123 } else { 2124 ExpandOp(Node->getOperand(1), Lo, Hi); 2125 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 2126 2127 if (!TLI.isLittleEndian()) 2128 std::swap(Lo, Hi); 2129 } 2130 2131 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2132 SVOffset, isVolatile, Alignment); 2133 2134 if (Hi.Val == NULL) { 2135 // Must be int <-> float one-to-one expansion. 2136 Result = Lo; 2137 break; 2138 } 2139 2140 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2141 getIntPtrConstant(IncrementSize)); 2142 assert(isTypeLegal(Tmp2.getValueType()) && 2143 "Pointers must be legal!"); 2144 SVOffset += IncrementSize; 2145 if (Alignment > IncrementSize) 2146 Alignment = IncrementSize; 2147 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2148 SVOffset, isVolatile, Alignment); 2149 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2150 break; 2151 } 2152 } else { 2153 // Truncating store 2154 assert(isTypeLegal(ST->getValue().getValueType()) && 2155 "Cannot handle illegal TRUNCSTORE yet!"); 2156 Tmp3 = LegalizeOp(ST->getValue()); 2157 2158 // The only promote case we handle is TRUNCSTORE:i1 X into 2159 // -> TRUNCSTORE:i8 (and X, 1) 2160 if (ST->getStoredVT() == MVT::i1 && 2161 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) { 2162 // Promote the bool to a mask then store. 2163 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3, 2164 DAG.getConstant(1, Tmp3.getValueType())); 2165 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2166 SVOffset, MVT::i8, 2167 isVolatile, Alignment); 2168 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2169 Tmp2 != ST->getBasePtr()) { 2170 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2171 ST->getOffset()); 2172 } 2173 2174 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT(); 2175 switch (TLI.getStoreXAction(StVT)) { 2176 default: assert(0 && "This action is not supported yet!"); 2177 case TargetLowering::Legal: 2178 // If this is an unaligned store and the target doesn't support it, 2179 // expand it. 2180 if (!TLI.allowsUnalignedMemoryAccesses()) { 2181 unsigned ABIAlignment = TLI.getTargetData()-> 2182 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2183 if (ST->getAlignment() < ABIAlignment) 2184 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2185 TLI); 2186 } 2187 break; 2188 case TargetLowering::Custom: 2189 Tmp1 = TLI.LowerOperation(Result, DAG); 2190 if (Tmp1.Val) Result = Tmp1; 2191 break; 2192 } 2193 } 2194 break; 2195 } 2196 case ISD::PCMARKER: 2197 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2198 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2199 break; 2200 case ISD::STACKSAVE: 2201 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2202 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2203 Tmp1 = Result.getValue(0); 2204 Tmp2 = Result.getValue(1); 2205 2206 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2207 default: assert(0 && "This action is not supported yet!"); 2208 case TargetLowering::Legal: break; 2209 case TargetLowering::Custom: 2210 Tmp3 = TLI.LowerOperation(Result, DAG); 2211 if (Tmp3.Val) { 2212 Tmp1 = LegalizeOp(Tmp3); 2213 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2214 } 2215 break; 2216 case TargetLowering::Expand: 2217 // Expand to CopyFromReg if the target set 2218 // StackPointerRegisterToSaveRestore. 2219 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2220 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2221 Node->getValueType(0)); 2222 Tmp2 = Tmp1.getValue(1); 2223 } else { 2224 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2225 Tmp2 = Node->getOperand(0); 2226 } 2227 break; 2228 } 2229 2230 // Since stacksave produce two values, make sure to remember that we 2231 // legalized both of them. 2232 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2233 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2234 return Op.ResNo ? Tmp2 : Tmp1; 2235 2236 case ISD::STACKRESTORE: 2237 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2238 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2239 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2240 2241 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2242 default: assert(0 && "This action is not supported yet!"); 2243 case TargetLowering::Legal: break; 2244 case TargetLowering::Custom: 2245 Tmp1 = TLI.LowerOperation(Result, DAG); 2246 if (Tmp1.Val) Result = Tmp1; 2247 break; 2248 case TargetLowering::Expand: 2249 // Expand to CopyToReg if the target set 2250 // StackPointerRegisterToSaveRestore. 2251 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2252 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2253 } else { 2254 Result = Tmp1; 2255 } 2256 break; 2257 } 2258 break; 2259 2260 case ISD::READCYCLECOUNTER: 2261 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2262 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2263 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2264 Node->getValueType(0))) { 2265 default: assert(0 && "This action is not supported yet!"); 2266 case TargetLowering::Legal: 2267 Tmp1 = Result.getValue(0); 2268 Tmp2 = Result.getValue(1); 2269 break; 2270 case TargetLowering::Custom: 2271 Result = TLI.LowerOperation(Result, DAG); 2272 Tmp1 = LegalizeOp(Result.getValue(0)); 2273 Tmp2 = LegalizeOp(Result.getValue(1)); 2274 break; 2275 } 2276 2277 // Since rdcc produce two values, make sure to remember that we legalized 2278 // both of them. 2279 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2280 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2281 return Result; 2282 2283 case ISD::SELECT: 2284 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2285 case Expand: assert(0 && "It's impossible to expand bools"); 2286 case Legal: 2287 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2288 break; 2289 case Promote: 2290 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2291 // Make sure the condition is either zero or one. 2292 if (!DAG.MaskedValueIsZero(Tmp1, 2293 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 2294 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2295 break; 2296 } 2297 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2298 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2299 2300 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2301 2302 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2303 default: assert(0 && "This action is not supported yet!"); 2304 case TargetLowering::Legal: break; 2305 case TargetLowering::Custom: { 2306 Tmp1 = TLI.LowerOperation(Result, DAG); 2307 if (Tmp1.Val) Result = Tmp1; 2308 break; 2309 } 2310 case TargetLowering::Expand: 2311 if (Tmp1.getOpcode() == ISD::SETCC) { 2312 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2313 Tmp2, Tmp3, 2314 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2315 } else { 2316 Result = DAG.getSelectCC(Tmp1, 2317 DAG.getConstant(0, Tmp1.getValueType()), 2318 Tmp2, Tmp3, ISD::SETNE); 2319 } 2320 break; 2321 case TargetLowering::Promote: { 2322 MVT::ValueType NVT = 2323 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2324 unsigned ExtOp, TruncOp; 2325 if (MVT::isVector(Tmp2.getValueType())) { 2326 ExtOp = ISD::BIT_CONVERT; 2327 TruncOp = ISD::BIT_CONVERT; 2328 } else if (MVT::isInteger(Tmp2.getValueType())) { 2329 ExtOp = ISD::ANY_EXTEND; 2330 TruncOp = ISD::TRUNCATE; 2331 } else { 2332 ExtOp = ISD::FP_EXTEND; 2333 TruncOp = ISD::FP_ROUND; 2334 } 2335 // Promote each of the values to the new type. 2336 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2337 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2338 // Perform the larger operation, then round down. 2339 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2340 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2341 break; 2342 } 2343 } 2344 break; 2345 case ISD::SELECT_CC: { 2346 Tmp1 = Node->getOperand(0); // LHS 2347 Tmp2 = Node->getOperand(1); // RHS 2348 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2349 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2350 SDOperand CC = Node->getOperand(4); 2351 2352 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2353 2354 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2355 // the LHS is a legal SETCC itself. In this case, we need to compare 2356 // the result against zero to select between true and false values. 2357 if (Tmp2.Val == 0) { 2358 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2359 CC = DAG.getCondCode(ISD::SETNE); 2360 } 2361 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2362 2363 // Everything is legal, see if we should expand this op or something. 2364 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2365 default: assert(0 && "This action is not supported yet!"); 2366 case TargetLowering::Legal: break; 2367 case TargetLowering::Custom: 2368 Tmp1 = TLI.LowerOperation(Result, DAG); 2369 if (Tmp1.Val) Result = Tmp1; 2370 break; 2371 } 2372 break; 2373 } 2374 case ISD::SETCC: 2375 Tmp1 = Node->getOperand(0); 2376 Tmp2 = Node->getOperand(1); 2377 Tmp3 = Node->getOperand(2); 2378 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2379 2380 // If we had to Expand the SetCC operands into a SELECT node, then it may 2381 // not always be possible to return a true LHS & RHS. In this case, just 2382 // return the value we legalized, returned in the LHS 2383 if (Tmp2.Val == 0) { 2384 Result = Tmp1; 2385 break; 2386 } 2387 2388 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2389 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2390 case TargetLowering::Custom: 2391 isCustom = true; 2392 // FALLTHROUGH. 2393 case TargetLowering::Legal: 2394 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2395 if (isCustom) { 2396 Tmp4 = TLI.LowerOperation(Result, DAG); 2397 if (Tmp4.Val) Result = Tmp4; 2398 } 2399 break; 2400 case TargetLowering::Promote: { 2401 // First step, figure out the appropriate operation to use. 2402 // Allow SETCC to not be supported for all legal data types 2403 // Mostly this targets FP 2404 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2405 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2406 2407 // Scan for the appropriate larger type to use. 2408 while (1) { 2409 NewInTy = (MVT::ValueType)(NewInTy+1); 2410 2411 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2412 "Fell off of the edge of the integer world"); 2413 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2414 "Fell off of the edge of the floating point world"); 2415 2416 // If the target supports SETCC of this type, use it. 2417 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2418 break; 2419 } 2420 if (MVT::isInteger(NewInTy)) 2421 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2422 else { 2423 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2424 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2425 } 2426 Tmp1 = LegalizeOp(Tmp1); 2427 Tmp2 = LegalizeOp(Tmp2); 2428 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2429 Result = LegalizeOp(Result); 2430 break; 2431 } 2432 case TargetLowering::Expand: 2433 // Expand a setcc node into a select_cc of the same condition, lhs, and 2434 // rhs that selects between const 1 (true) and const 0 (false). 2435 MVT::ValueType VT = Node->getValueType(0); 2436 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2437 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2438 Tmp3); 2439 break; 2440 } 2441 break; 2442 case ISD::MEMSET: 2443 case ISD::MEMCPY: 2444 case ISD::MEMMOVE: { 2445 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2446 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2447 2448 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2449 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2450 case Expand: assert(0 && "Cannot expand a byte!"); 2451 case Legal: 2452 Tmp3 = LegalizeOp(Node->getOperand(2)); 2453 break; 2454 case Promote: 2455 Tmp3 = PromoteOp(Node->getOperand(2)); 2456 break; 2457 } 2458 } else { 2459 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2460 } 2461 2462 SDOperand Tmp4; 2463 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2464 case Expand: { 2465 // Length is too big, just take the lo-part of the length. 2466 SDOperand HiPart; 2467 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2468 break; 2469 } 2470 case Legal: 2471 Tmp4 = LegalizeOp(Node->getOperand(3)); 2472 break; 2473 case Promote: 2474 Tmp4 = PromoteOp(Node->getOperand(3)); 2475 break; 2476 } 2477 2478 SDOperand Tmp5; 2479 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2480 case Expand: assert(0 && "Cannot expand this yet!"); 2481 case Legal: 2482 Tmp5 = LegalizeOp(Node->getOperand(4)); 2483 break; 2484 case Promote: 2485 Tmp5 = PromoteOp(Node->getOperand(4)); 2486 break; 2487 } 2488 2489 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2490 default: assert(0 && "This action not implemented for this operation!"); 2491 case TargetLowering::Custom: 2492 isCustom = true; 2493 // FALLTHROUGH 2494 case TargetLowering::Legal: 2495 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 2496 if (isCustom) { 2497 Tmp1 = TLI.LowerOperation(Result, DAG); 2498 if (Tmp1.Val) Result = Tmp1; 2499 } 2500 break; 2501 case TargetLowering::Expand: { 2502 // Otherwise, the target does not support this operation. Lower the 2503 // operation to an explicit libcall as appropriate. 2504 MVT::ValueType IntPtr = TLI.getPointerTy(); 2505 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2506 TargetLowering::ArgListTy Args; 2507 TargetLowering::ArgListEntry Entry; 2508 2509 const char *FnName = 0; 2510 if (Node->getOpcode() == ISD::MEMSET) { 2511 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; 2512 Args.push_back(Entry); 2513 // Extend the (previously legalized) ubyte argument to be an int value 2514 // for the call. 2515 if (Tmp3.getValueType() > MVT::i32) 2516 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2517 else 2518 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2519 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 2520 Args.push_back(Entry); 2521 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false; 2522 Args.push_back(Entry); 2523 2524 FnName = "memset"; 2525 } else if (Node->getOpcode() == ISD::MEMCPY || 2526 Node->getOpcode() == ISD::MEMMOVE) { 2527 Entry.Ty = IntPtrTy; 2528 Entry.Node = Tmp2; Args.push_back(Entry); 2529 Entry.Node = Tmp3; Args.push_back(Entry); 2530 Entry.Node = Tmp4; Args.push_back(Entry); 2531 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2532 } else { 2533 assert(0 && "Unknown op!"); 2534 } 2535 2536 std::pair<SDOperand,SDOperand> CallResult = 2537 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 2538 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2539 Result = CallResult.second; 2540 break; 2541 } 2542 } 2543 break; 2544 } 2545 2546 case ISD::SHL_PARTS: 2547 case ISD::SRA_PARTS: 2548 case ISD::SRL_PARTS: { 2549 SmallVector<SDOperand, 8> Ops; 2550 bool Changed = false; 2551 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2552 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2553 Changed |= Ops.back() != Node->getOperand(i); 2554 } 2555 if (Changed) 2556 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2557 2558 switch (TLI.getOperationAction(Node->getOpcode(), 2559 Node->getValueType(0))) { 2560 default: assert(0 && "This action is not supported yet!"); 2561 case TargetLowering::Legal: break; 2562 case TargetLowering::Custom: 2563 Tmp1 = TLI.LowerOperation(Result, DAG); 2564 if (Tmp1.Val) { 2565 SDOperand Tmp2, RetVal(0, 0); 2566 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2567 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2568 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2569 if (i == Op.ResNo) 2570 RetVal = Tmp2; 2571 } 2572 assert(RetVal.Val && "Illegal result number"); 2573 return RetVal; 2574 } 2575 break; 2576 } 2577 2578 // Since these produce multiple values, make sure to remember that we 2579 // legalized all of them. 2580 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2581 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2582 return Result.getValue(Op.ResNo); 2583 } 2584 2585 // Binary operators 2586 case ISD::ADD: 2587 case ISD::SUB: 2588 case ISD::MUL: 2589 case ISD::MULHS: 2590 case ISD::MULHU: 2591 case ISD::UDIV: 2592 case ISD::SDIV: 2593 case ISD::AND: 2594 case ISD::OR: 2595 case ISD::XOR: 2596 case ISD::SHL: 2597 case ISD::SRL: 2598 case ISD::SRA: 2599 case ISD::FADD: 2600 case ISD::FSUB: 2601 case ISD::FMUL: 2602 case ISD::FDIV: 2603 case ISD::FPOW: 2604 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2605 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2606 case Expand: assert(0 && "Not possible"); 2607 case Legal: 2608 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2609 break; 2610 case Promote: 2611 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2612 break; 2613 } 2614 2615 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2616 2617 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2618 default: assert(0 && "BinOp legalize operation not supported"); 2619 case TargetLowering::Legal: break; 2620 case TargetLowering::Custom: 2621 Tmp1 = TLI.LowerOperation(Result, DAG); 2622 if (Tmp1.Val) Result = Tmp1; 2623 break; 2624 case TargetLowering::Expand: { 2625 MVT::ValueType VT = Op.getValueType(); 2626 2627 // See if multiply or divide can be lowered using two-result operations. 2628 SDVTList VTs = DAG.getVTList(VT, VT); 2629 if (Node->getOpcode() == ISD::MUL) { 2630 // We just need the low half of the multiply; try both the signed 2631 // and unsigned forms. If the target supports both SMUL_LOHI and 2632 // UMUL_LOHI, form a preference by checking which forms of plain 2633 // MULH it supports. 2634 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2635 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2636 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2637 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2638 unsigned OpToUse = 0; 2639 if (HasSMUL_LOHI && !HasMULHS) { 2640 OpToUse = ISD::SMUL_LOHI; 2641 } else if (HasUMUL_LOHI && !HasMULHU) { 2642 OpToUse = ISD::UMUL_LOHI; 2643 } else if (HasSMUL_LOHI) { 2644 OpToUse = ISD::SMUL_LOHI; 2645 } else if (HasUMUL_LOHI) { 2646 OpToUse = ISD::UMUL_LOHI; 2647 } 2648 if (OpToUse) { 2649 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 2650 break; 2651 } 2652 } 2653 if (Node->getOpcode() == ISD::MULHS && 2654 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 2655 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2656 break; 2657 } 2658 if (Node->getOpcode() == ISD::MULHU && 2659 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 2660 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2661 break; 2662 } 2663 if (Node->getOpcode() == ISD::SDIV && 2664 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 2665 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 2666 break; 2667 } 2668 if (Node->getOpcode() == ISD::UDIV && 2669 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 2670 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 2671 break; 2672 } 2673 2674 // Check to see if we have a libcall for this operator. 2675 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2676 bool isSigned = false; 2677 switch (Node->getOpcode()) { 2678 case ISD::UDIV: 2679 case ISD::SDIV: 2680 if (VT == MVT::i32) { 2681 LC = Node->getOpcode() == ISD::UDIV 2682 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 2683 isSigned = Node->getOpcode() == ISD::SDIV; 2684 } 2685 break; 2686 case ISD::FPOW: 2687 LC = VT == MVT::f32 ? RTLIB::POW_F32 : 2688 VT == MVT::f64 ? RTLIB::POW_F64 : 2689 VT == MVT::f80 ? RTLIB::POW_F80 : 2690 VT == MVT::ppcf128 ? RTLIB::POW_PPCF128 : 2691 RTLIB::UNKNOWN_LIBCALL; 2692 break; 2693 default: break; 2694 } 2695 if (LC != RTLIB::UNKNOWN_LIBCALL) { 2696 SDOperand Dummy; 2697 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2698 break; 2699 } 2700 2701 assert(MVT::isVector(Node->getValueType(0)) && 2702 "Cannot expand this binary operator!"); 2703 // Expand the operation into a bunch of nasty scalar code. 2704 Result = LegalizeOp(UnrollVectorOp(Op)); 2705 break; 2706 } 2707 case TargetLowering::Promote: { 2708 switch (Node->getOpcode()) { 2709 default: assert(0 && "Do not know how to promote this BinOp!"); 2710 case ISD::AND: 2711 case ISD::OR: 2712 case ISD::XOR: { 2713 MVT::ValueType OVT = Node->getValueType(0); 2714 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2715 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2716 // Bit convert each of the values to the new type. 2717 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2718 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2719 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2720 // Bit convert the result back the original type. 2721 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2722 break; 2723 } 2724 } 2725 } 2726 } 2727 break; 2728 2729 case ISD::SMUL_LOHI: 2730 case ISD::UMUL_LOHI: 2731 case ISD::SDIVREM: 2732 case ISD::UDIVREM: 2733 // These nodes will only be produced by target-specific lowering, so 2734 // they shouldn't be here if they aren't legal. 2735 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 2736 "This must be legal!"); 2737 2738 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2739 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2740 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2741 break; 2742 2743 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2744 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2745 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2746 case Expand: assert(0 && "Not possible"); 2747 case Legal: 2748 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2749 break; 2750 case Promote: 2751 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2752 break; 2753 } 2754 2755 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2756 2757 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2758 default: assert(0 && "Operation not supported"); 2759 case TargetLowering::Custom: 2760 Tmp1 = TLI.LowerOperation(Result, DAG); 2761 if (Tmp1.Val) Result = Tmp1; 2762 break; 2763 case TargetLowering::Legal: break; 2764 case TargetLowering::Expand: { 2765 // If this target supports fabs/fneg natively and select is cheap, 2766 // do this efficiently. 2767 if (!TLI.isSelectExpensive() && 2768 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 2769 TargetLowering::Legal && 2770 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 2771 TargetLowering::Legal) { 2772 // Get the sign bit of the RHS. 2773 MVT::ValueType IVT = 2774 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2775 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2776 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2777 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2778 // Get the absolute value of the result. 2779 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2780 // Select between the nabs and abs value based on the sign bit of 2781 // the input. 2782 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2783 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2784 AbsVal), 2785 AbsVal); 2786 Result = LegalizeOp(Result); 2787 break; 2788 } 2789 2790 // Otherwise, do bitwise ops! 2791 MVT::ValueType NVT = 2792 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 2793 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 2794 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 2795 Result = LegalizeOp(Result); 2796 break; 2797 } 2798 } 2799 break; 2800 2801 case ISD::ADDC: 2802 case ISD::SUBC: 2803 Tmp1 = LegalizeOp(Node->getOperand(0)); 2804 Tmp2 = LegalizeOp(Node->getOperand(1)); 2805 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2806 // Since this produces two values, make sure to remember that we legalized 2807 // both of them. 2808 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2809 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2810 return Result; 2811 2812 case ISD::ADDE: 2813 case ISD::SUBE: 2814 Tmp1 = LegalizeOp(Node->getOperand(0)); 2815 Tmp2 = LegalizeOp(Node->getOperand(1)); 2816 Tmp3 = LegalizeOp(Node->getOperand(2)); 2817 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2818 // Since this produces two values, make sure to remember that we legalized 2819 // both of them. 2820 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2821 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2822 return Result; 2823 2824 case ISD::BUILD_PAIR: { 2825 MVT::ValueType PairTy = Node->getValueType(0); 2826 // TODO: handle the case where the Lo and Hi operands are not of legal type 2827 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2828 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2829 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2830 case TargetLowering::Promote: 2831 case TargetLowering::Custom: 2832 assert(0 && "Cannot promote/custom this yet!"); 2833 case TargetLowering::Legal: 2834 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2835 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2836 break; 2837 case TargetLowering::Expand: 2838 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2839 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2840 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2841 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2842 TLI.getShiftAmountTy())); 2843 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2844 break; 2845 } 2846 break; 2847 } 2848 2849 case ISD::UREM: 2850 case ISD::SREM: 2851 case ISD::FREM: 2852 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2853 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2854 2855 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2856 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2857 case TargetLowering::Custom: 2858 isCustom = true; 2859 // FALLTHROUGH 2860 case TargetLowering::Legal: 2861 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2862 if (isCustom) { 2863 Tmp1 = TLI.LowerOperation(Result, DAG); 2864 if (Tmp1.Val) Result = Tmp1; 2865 } 2866 break; 2867 case TargetLowering::Expand: { 2868 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2869 bool isSigned = DivOpc == ISD::SDIV; 2870 MVT::ValueType VT = Node->getValueType(0); 2871 2872 // See if remainder can be lowered using two-result operations. 2873 SDVTList VTs = DAG.getVTList(VT, VT); 2874 if (Node->getOpcode() == ISD::SREM && 2875 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 2876 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 2877 break; 2878 } 2879 if (Node->getOpcode() == ISD::UREM && 2880 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 2881 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 2882 break; 2883 } 2884 2885 if (MVT::isInteger(VT)) { 2886 if (TLI.getOperationAction(DivOpc, VT) == 2887 TargetLowering::Legal) { 2888 // X % Y -> X-X/Y*Y 2889 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 2890 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2891 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2892 } else { 2893 assert(VT == MVT::i32 && 2894 "Cannot expand this binary operator!"); 2895 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 2896 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 2897 SDOperand Dummy; 2898 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2899 } 2900 } else { 2901 // Floating point mod -> fmod libcall. 2902 RTLIB::Libcall LC = VT == MVT::f32 2903 ? RTLIB::REM_F32 : RTLIB::REM_F64; 2904 SDOperand Dummy; 2905 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 2906 false/*sign irrelevant*/, Dummy); 2907 } 2908 break; 2909 } 2910 } 2911 break; 2912 case ISD::VAARG: { 2913 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2914 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2915 2916 MVT::ValueType VT = Node->getValueType(0); 2917 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2918 default: assert(0 && "This action is not supported yet!"); 2919 case TargetLowering::Custom: 2920 isCustom = true; 2921 // FALLTHROUGH 2922 case TargetLowering::Legal: 2923 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2924 Result = Result.getValue(0); 2925 Tmp1 = Result.getValue(1); 2926 2927 if (isCustom) { 2928 Tmp2 = TLI.LowerOperation(Result, DAG); 2929 if (Tmp2.Val) { 2930 Result = LegalizeOp(Tmp2); 2931 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2932 } 2933 } 2934 break; 2935 case TargetLowering::Expand: { 2936 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 2937 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2938 SV->getValue(), SV->getOffset()); 2939 // Increment the pointer, VAList, to the next vaarg 2940 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2941 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2942 TLI.getPointerTy())); 2943 // Store the incremented VAList to the legalized pointer 2944 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 2945 SV->getOffset()); 2946 // Load the actual argument out of the pointer VAList 2947 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 2948 Tmp1 = LegalizeOp(Result.getValue(1)); 2949 Result = LegalizeOp(Result); 2950 break; 2951 } 2952 } 2953 // Since VAARG produces two values, make sure to remember that we 2954 // legalized both of them. 2955 AddLegalizedOperand(SDOperand(Node, 0), Result); 2956 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 2957 return Op.ResNo ? Tmp1 : Result; 2958 } 2959 2960 case ISD::VACOPY: 2961 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2962 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 2963 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 2964 2965 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 2966 default: assert(0 && "This action is not supported yet!"); 2967 case TargetLowering::Custom: 2968 isCustom = true; 2969 // FALLTHROUGH 2970 case TargetLowering::Legal: 2971 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 2972 Node->getOperand(3), Node->getOperand(4)); 2973 if (isCustom) { 2974 Tmp1 = TLI.LowerOperation(Result, DAG); 2975 if (Tmp1.Val) Result = Tmp1; 2976 } 2977 break; 2978 case TargetLowering::Expand: 2979 // This defaults to loading a pointer from the input and storing it to the 2980 // output, returning the chain. 2981 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 2982 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); 2983 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 2984 SVD->getOffset()); 2985 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), 2986 SVS->getOffset()); 2987 break; 2988 } 2989 break; 2990 2991 case ISD::VAEND: 2992 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2993 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2994 2995 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 2996 default: assert(0 && "This action is not supported yet!"); 2997 case TargetLowering::Custom: 2998 isCustom = true; 2999 // FALLTHROUGH 3000 case TargetLowering::Legal: 3001 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3002 if (isCustom) { 3003 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3004 if (Tmp1.Val) Result = Tmp1; 3005 } 3006 break; 3007 case TargetLowering::Expand: 3008 Result = Tmp1; // Default to a no-op, return the chain 3009 break; 3010 } 3011 break; 3012 3013 case ISD::VASTART: 3014 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3015 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3016 3017 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3018 3019 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3020 default: assert(0 && "This action is not supported yet!"); 3021 case TargetLowering::Legal: break; 3022 case TargetLowering::Custom: 3023 Tmp1 = TLI.LowerOperation(Result, DAG); 3024 if (Tmp1.Val) Result = Tmp1; 3025 break; 3026 } 3027 break; 3028 3029 case ISD::ROTL: 3030 case ISD::ROTR: 3031 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3032 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3033 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3034 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3035 default: 3036 assert(0 && "ROTL/ROTR legalize operation not supported"); 3037 break; 3038 case TargetLowering::Legal: 3039 break; 3040 case TargetLowering::Custom: 3041 Tmp1 = TLI.LowerOperation(Result, DAG); 3042 if (Tmp1.Val) Result = Tmp1; 3043 break; 3044 case TargetLowering::Promote: 3045 assert(0 && "Do not know how to promote ROTL/ROTR"); 3046 break; 3047 case TargetLowering::Expand: 3048 assert(0 && "Do not know how to expand ROTL/ROTR"); 3049 break; 3050 } 3051 break; 3052 3053 case ISD::BSWAP: 3054 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3055 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3056 case TargetLowering::Custom: 3057 assert(0 && "Cannot custom legalize this yet!"); 3058 case TargetLowering::Legal: 3059 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3060 break; 3061 case TargetLowering::Promote: { 3062 MVT::ValueType OVT = Tmp1.getValueType(); 3063 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3064 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 3065 3066 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3067 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3068 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3069 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3070 break; 3071 } 3072 case TargetLowering::Expand: 3073 Result = ExpandBSWAP(Tmp1); 3074 break; 3075 } 3076 break; 3077 3078 case ISD::CTPOP: 3079 case ISD::CTTZ: 3080 case ISD::CTLZ: 3081 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3082 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3083 case TargetLowering::Custom: 3084 case TargetLowering::Legal: 3085 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3086 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3087 TargetLowering::Custom) { 3088 Tmp1 = TLI.LowerOperation(Result, DAG); 3089 if (Tmp1.Val) { 3090 Result = Tmp1; 3091 } 3092 } 3093 break; 3094 case TargetLowering::Promote: { 3095 MVT::ValueType OVT = Tmp1.getValueType(); 3096 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3097 3098 // Zero extend the argument. 3099 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3100 // Perform the larger operation, then subtract if needed. 3101 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3102 switch (Node->getOpcode()) { 3103 case ISD::CTPOP: 3104 Result = Tmp1; 3105 break; 3106 case ISD::CTTZ: 3107 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3108 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3109 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3110 ISD::SETEQ); 3111 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3112 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 3113 break; 3114 case ISD::CTLZ: 3115 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3116 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3117 DAG.getConstant(MVT::getSizeInBits(NVT) - 3118 MVT::getSizeInBits(OVT), NVT)); 3119 break; 3120 } 3121 break; 3122 } 3123 case TargetLowering::Expand: 3124 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3125 break; 3126 } 3127 break; 3128 3129 // Unary operators 3130 case ISD::FABS: 3131 case ISD::FNEG: 3132 case ISD::FSQRT: 3133 case ISD::FSIN: 3134 case ISD::FCOS: 3135 Tmp1 = LegalizeOp(Node->getOperand(0)); 3136 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3137 case TargetLowering::Promote: 3138 case TargetLowering::Custom: 3139 isCustom = true; 3140 // FALLTHROUGH 3141 case TargetLowering::Legal: 3142 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3143 if (isCustom) { 3144 Tmp1 = TLI.LowerOperation(Result, DAG); 3145 if (Tmp1.Val) Result = Tmp1; 3146 } 3147 break; 3148 case TargetLowering::Expand: 3149 switch (Node->getOpcode()) { 3150 default: assert(0 && "Unreachable!"); 3151 case ISD::FNEG: 3152 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3153 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3154 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3155 break; 3156 case ISD::FABS: { 3157 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3158 MVT::ValueType VT = Node->getValueType(0); 3159 Tmp2 = DAG.getConstantFP(0.0, VT); 3160 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 3161 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3162 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3163 break; 3164 } 3165 case ISD::FSQRT: 3166 case ISD::FSIN: 3167 case ISD::FCOS: { 3168 MVT::ValueType VT = Node->getValueType(0); 3169 3170 // Expand unsupported unary vector operators by unrolling them. 3171 if (MVT::isVector(VT)) { 3172 Result = LegalizeOp(UnrollVectorOp(Op)); 3173 break; 3174 } 3175 3176 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3177 switch(Node->getOpcode()) { 3178 case ISD::FSQRT: 3179 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : 3180 VT == MVT::f64 ? RTLIB::SQRT_F64 : 3181 VT == MVT::f80 ? RTLIB::SQRT_F80 : 3182 VT == MVT::ppcf128 ? RTLIB::SQRT_PPCF128 : 3183 RTLIB::UNKNOWN_LIBCALL; 3184 break; 3185 case ISD::FSIN: 3186 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 3187 break; 3188 case ISD::FCOS: 3189 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64; 3190 break; 3191 default: assert(0 && "Unreachable!"); 3192 } 3193 SDOperand Dummy; 3194 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3195 false/*sign irrelevant*/, Dummy); 3196 break; 3197 } 3198 } 3199 break; 3200 } 3201 break; 3202 case ISD::FPOWI: { 3203 MVT::ValueType VT = Node->getValueType(0); 3204 3205 // Expand unsupported unary vector operators by unrolling them. 3206 if (MVT::isVector(VT)) { 3207 Result = LegalizeOp(UnrollVectorOp(Op)); 3208 break; 3209 } 3210 3211 // We always lower FPOWI into a libcall. No target support for it yet. 3212 RTLIB::Libcall LC = 3213 VT == MVT::f32 ? RTLIB::POWI_F32 : 3214 VT == MVT::f64 ? RTLIB::POWI_F64 : 3215 VT == MVT::f80 ? RTLIB::POWI_F80 : 3216 VT == MVT::ppcf128 ? RTLIB::POWI_PPCF128 : 3217 RTLIB::UNKNOWN_LIBCALL; 3218 SDOperand Dummy; 3219 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3220 false/*sign irrelevant*/, Dummy); 3221 break; 3222 } 3223 case ISD::BIT_CONVERT: 3224 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3225 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3226 } else if (MVT::isVector(Op.getOperand(0).getValueType())) { 3227 // The input has to be a vector type, we have to either scalarize it, pack 3228 // it, or convert it based on whether the input vector type is legal. 3229 SDNode *InVal = Node->getOperand(0).Val; 3230 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0)); 3231 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0)); 3232 3233 // Figure out if there is a simple type corresponding to this Vector 3234 // type. If so, convert to the vector type. 3235 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3236 if (TLI.isTypeLegal(TVT)) { 3237 // Turn this into a bit convert of the vector input. 3238 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3239 LegalizeOp(Node->getOperand(0))); 3240 break; 3241 } else if (NumElems == 1) { 3242 // Turn this into a bit convert of the scalar input. 3243 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3244 ScalarizeVectorOp(Node->getOperand(0))); 3245 break; 3246 } else { 3247 // FIXME: UNIMP! Store then reload 3248 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3249 } 3250 } else { 3251 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3252 Node->getOperand(0).getValueType())) { 3253 default: assert(0 && "Unknown operation action!"); 3254 case TargetLowering::Expand: 3255 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3256 break; 3257 case TargetLowering::Legal: 3258 Tmp1 = LegalizeOp(Node->getOperand(0)); 3259 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3260 break; 3261 } 3262 } 3263 break; 3264 3265 // Conversion operators. The source and destination have different types. 3266 case ISD::SINT_TO_FP: 3267 case ISD::UINT_TO_FP: { 3268 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3269 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3270 case Legal: 3271 switch (TLI.getOperationAction(Node->getOpcode(), 3272 Node->getOperand(0).getValueType())) { 3273 default: assert(0 && "Unknown operation action!"); 3274 case TargetLowering::Custom: 3275 isCustom = true; 3276 // FALLTHROUGH 3277 case TargetLowering::Legal: 3278 Tmp1 = LegalizeOp(Node->getOperand(0)); 3279 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3280 if (isCustom) { 3281 Tmp1 = TLI.LowerOperation(Result, DAG); 3282 if (Tmp1.Val) Result = Tmp1; 3283 } 3284 break; 3285 case TargetLowering::Expand: 3286 Result = ExpandLegalINT_TO_FP(isSigned, 3287 LegalizeOp(Node->getOperand(0)), 3288 Node->getValueType(0)); 3289 break; 3290 case TargetLowering::Promote: 3291 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3292 Node->getValueType(0), 3293 isSigned); 3294 break; 3295 } 3296 break; 3297 case Expand: 3298 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3299 Node->getValueType(0), Node->getOperand(0)); 3300 break; 3301 case Promote: 3302 Tmp1 = PromoteOp(Node->getOperand(0)); 3303 if (isSigned) { 3304 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3305 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3306 } else { 3307 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3308 Node->getOperand(0).getValueType()); 3309 } 3310 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3311 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3312 break; 3313 } 3314 break; 3315 } 3316 case ISD::TRUNCATE: 3317 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3318 case Legal: 3319 Tmp1 = LegalizeOp(Node->getOperand(0)); 3320 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3321 break; 3322 case Expand: 3323 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3324 3325 // Since the result is legal, we should just be able to truncate the low 3326 // part of the source. 3327 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3328 break; 3329 case Promote: 3330 Result = PromoteOp(Node->getOperand(0)); 3331 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3332 break; 3333 } 3334 break; 3335 3336 case ISD::FP_TO_SINT: 3337 case ISD::FP_TO_UINT: 3338 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3339 case Legal: 3340 Tmp1 = LegalizeOp(Node->getOperand(0)); 3341 3342 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3343 default: assert(0 && "Unknown operation action!"); 3344 case TargetLowering::Custom: 3345 isCustom = true; 3346 // FALLTHROUGH 3347 case TargetLowering::Legal: 3348 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3349 if (isCustom) { 3350 Tmp1 = TLI.LowerOperation(Result, DAG); 3351 if (Tmp1.Val) Result = Tmp1; 3352 } 3353 break; 3354 case TargetLowering::Promote: 3355 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3356 Node->getOpcode() == ISD::FP_TO_SINT); 3357 break; 3358 case TargetLowering::Expand: 3359 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3360 SDOperand True, False; 3361 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3362 MVT::ValueType NVT = Node->getValueType(0); 3363 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1; 3364 const uint64_t zero[] = {0, 0}; 3365 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero)); 3366 uint64_t x = 1ULL << ShiftAmt; 3367 (void)apf.convertFromZeroExtendedInteger 3368 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven); 3369 Tmp2 = DAG.getConstantFP(apf, VT); 3370 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 3371 Node->getOperand(0), Tmp2, ISD::SETLT); 3372 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3373 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3374 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3375 Tmp2)); 3376 False = DAG.getNode(ISD::XOR, NVT, False, 3377 DAG.getConstant(1ULL << ShiftAmt, NVT)); 3378 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3379 break; 3380 } else { 3381 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3382 } 3383 break; 3384 } 3385 break; 3386 case Expand: { 3387 MVT::ValueType VT = Op.getValueType(); 3388 MVT::ValueType OVT = Node->getOperand(0).getValueType(); 3389 // Convert ppcf128 to i32 3390 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3391 if (Node->getOpcode()==ISD::FP_TO_SINT) 3392 Result = DAG.getNode(ISD::FP_TO_SINT, VT, 3393 DAG.getNode(ISD::FP_ROUND, MVT::f64, 3394 (DAG.getNode(ISD::FP_ROUND_INREG, 3395 MVT::ppcf128, Node->getOperand(0), 3396 DAG.getValueType(MVT::f64))))); 3397 else { 3398 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3399 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3400 Tmp2 = DAG.getConstantFP(apf, OVT); 3401 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3402 // FIXME: generated code sucks. 3403 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3404 DAG.getNode(ISD::ADD, MVT::i32, 3405 DAG.getNode(ISD::FP_TO_SINT, VT, 3406 DAG.getNode(ISD::FSUB, OVT, 3407 Node->getOperand(0), Tmp2)), 3408 DAG.getConstant(0x80000000, MVT::i32)), 3409 DAG.getNode(ISD::FP_TO_SINT, VT, 3410 Node->getOperand(0)), 3411 DAG.getCondCode(ISD::SETGE)); 3412 } 3413 break; 3414 } 3415 // Convert f32 / f64 to i32 / i64. 3416 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3417 switch (Node->getOpcode()) { 3418 case ISD::FP_TO_SINT: { 3419 if (OVT == MVT::f32) 3420 LC = (VT == MVT::i32) 3421 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3422 else if (OVT == MVT::f64) 3423 LC = (VT == MVT::i32) 3424 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3425 else if (OVT == MVT::f80) { 3426 assert(VT == MVT::i64); 3427 LC = RTLIB::FPTOSINT_F80_I64; 3428 } 3429 else if (OVT == MVT::ppcf128) { 3430 assert(VT == MVT::i64); 3431 LC = RTLIB::FPTOSINT_PPCF128_I64; 3432 } 3433 break; 3434 } 3435 case ISD::FP_TO_UINT: { 3436 if (OVT == MVT::f32) 3437 LC = (VT == MVT::i32) 3438 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3439 else if (OVT == MVT::f64) 3440 LC = (VT == MVT::i32) 3441 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3442 else if (OVT == MVT::f80) { 3443 LC = (VT == MVT::i32) 3444 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64; 3445 } 3446 else if (OVT == MVT::ppcf128) { 3447 assert(VT == MVT::i64); 3448 LC = RTLIB::FPTOUINT_PPCF128_I64; 3449 } 3450 break; 3451 } 3452 default: assert(0 && "Unreachable!"); 3453 } 3454 SDOperand Dummy; 3455 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3456 false/*sign irrelevant*/, Dummy); 3457 break; 3458 } 3459 case Promote: 3460 Tmp1 = PromoteOp(Node->getOperand(0)); 3461 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3462 Result = LegalizeOp(Result); 3463 break; 3464 } 3465 break; 3466 3467 case ISD::FP_EXTEND: 3468 case ISD::FP_ROUND: { 3469 MVT::ValueType newVT = Op.getValueType(); 3470 MVT::ValueType oldVT = Op.getOperand(0).getValueType(); 3471 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) { 3472 if (Node->getOpcode() == ISD::FP_ROUND && oldVT == MVT::ppcf128) { 3473 SDOperand Lo, Hi; 3474 ExpandOp(Node->getOperand(0), Lo, Hi); 3475 if (newVT == MVT::f64) 3476 Result = Hi; 3477 else 3478 Result = DAG.getNode(ISD::FP_ROUND, newVT, Hi); 3479 break; 3480 } else { 3481 // The only other way we can lower this is to turn it into a STORE, 3482 // LOAD pair, targetting a temporary location (a stack slot). 3483 3484 // NOTE: there is a choice here between constantly creating new stack 3485 // slots and always reusing the same one. We currently always create 3486 // new ones, as reuse may inhibit scheduling. 3487 MVT::ValueType slotVT = 3488 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT; 3489 const Type *Ty = MVT::getTypeForValueType(slotVT); 3490 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3491 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3492 MachineFunction &MF = DAG.getMachineFunction(); 3493 int SSFI = 3494 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3495 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3496 if (Node->getOpcode() == ISD::FP_EXTEND) { 3497 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), 3498 StackSlot, NULL, 0); 3499 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT, 3500 Result, StackSlot, NULL, 0, oldVT); 3501 } else { 3502 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3503 StackSlot, NULL, 0, newVT); 3504 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT); 3505 } 3506 break; 3507 } 3508 } 3509 } 3510 // FALL THROUGH 3511 case ISD::ANY_EXTEND: 3512 case ISD::ZERO_EXTEND: 3513 case ISD::SIGN_EXTEND: 3514 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3515 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3516 case Legal: 3517 Tmp1 = LegalizeOp(Node->getOperand(0)); 3518 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3519 break; 3520 case Promote: 3521 switch (Node->getOpcode()) { 3522 case ISD::ANY_EXTEND: 3523 Tmp1 = PromoteOp(Node->getOperand(0)); 3524 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3525 break; 3526 case ISD::ZERO_EXTEND: 3527 Result = PromoteOp(Node->getOperand(0)); 3528 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3529 Result = DAG.getZeroExtendInReg(Result, 3530 Node->getOperand(0).getValueType()); 3531 break; 3532 case ISD::SIGN_EXTEND: 3533 Result = PromoteOp(Node->getOperand(0)); 3534 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3535 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3536 Result, 3537 DAG.getValueType(Node->getOperand(0).getValueType())); 3538 break; 3539 case ISD::FP_EXTEND: 3540 Result = PromoteOp(Node->getOperand(0)); 3541 if (Result.getValueType() != Op.getValueType()) 3542 // Dynamically dead while we have only 2 FP types. 3543 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 3544 break; 3545 case ISD::FP_ROUND: 3546 Result = PromoteOp(Node->getOperand(0)); 3547 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 3548 break; 3549 } 3550 } 3551 break; 3552 case ISD::FP_ROUND_INREG: 3553 case ISD::SIGN_EXTEND_INREG: { 3554 Tmp1 = LegalizeOp(Node->getOperand(0)); 3555 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3556 3557 // If this operation is not supported, convert it to a shl/shr or load/store 3558 // pair. 3559 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3560 default: assert(0 && "This action not supported for this op yet!"); 3561 case TargetLowering::Legal: 3562 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3563 break; 3564 case TargetLowering::Expand: 3565 // If this is an integer extend and shifts are supported, do that. 3566 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3567 // NOTE: we could fall back on load/store here too for targets without 3568 // SAR. However, it is doubtful that any exist. 3569 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3570 MVT::getSizeInBits(ExtraVT); 3571 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3572 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3573 Node->getOperand(0), ShiftCst); 3574 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3575 Result, ShiftCst); 3576 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3577 // The only way we can lower this is to turn it into a TRUNCSTORE, 3578 // EXTLOAD pair, targetting a temporary location (a stack slot). 3579 3580 // NOTE: there is a choice here between constantly creating new stack 3581 // slots and always reusing the same one. We currently always create 3582 // new ones, as reuse may inhibit scheduling. 3583 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 3584 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty); 3585 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3586 MachineFunction &MF = DAG.getMachineFunction(); 3587 int SSFI = 3588 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3589 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3590 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3591 StackSlot, NULL, 0, ExtraVT); 3592 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 3593 Result, StackSlot, NULL, 0, ExtraVT); 3594 } else { 3595 assert(0 && "Unknown op"); 3596 } 3597 break; 3598 } 3599 break; 3600 } 3601 case ISD::TRAMPOLINE: { 3602 SDOperand Ops[6]; 3603 for (unsigned i = 0; i != 6; ++i) 3604 Ops[i] = LegalizeOp(Node->getOperand(i)); 3605 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3606 // The only option for this node is to custom lower it. 3607 Result = TLI.LowerOperation(Result, DAG); 3608 assert(Result.Val && "Should always custom lower!"); 3609 3610 // Since trampoline produces two values, make sure to remember that we 3611 // legalized both of them. 3612 Tmp1 = LegalizeOp(Result.getValue(1)); 3613 Result = LegalizeOp(Result); 3614 AddLegalizedOperand(SDOperand(Node, 0), Result); 3615 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3616 return Op.ResNo ? Tmp1 : Result; 3617 } 3618 } 3619 3620 assert(Result.getValueType() == Op.getValueType() && 3621 "Bad legalization!"); 3622 3623 // Make sure that the generated code is itself legal. 3624 if (Result != Op) 3625 Result = LegalizeOp(Result); 3626 3627 // Note that LegalizeOp may be reentered even from single-use nodes, which 3628 // means that we always must cache transformed nodes. 3629 AddLegalizedOperand(Op, Result); 3630 return Result; 3631} 3632 3633/// PromoteOp - Given an operation that produces a value in an invalid type, 3634/// promote it to compute the value into a larger type. The produced value will 3635/// have the correct bits for the low portion of the register, but no guarantee 3636/// is made about the top bits: it may be zero, sign-extended, or garbage. 3637SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 3638 MVT::ValueType VT = Op.getValueType(); 3639 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3640 assert(getTypeAction(VT) == Promote && 3641 "Caller should expand or legalize operands that are not promotable!"); 3642 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 3643 "Cannot promote to smaller type!"); 3644 3645 SDOperand Tmp1, Tmp2, Tmp3; 3646 SDOperand Result; 3647 SDNode *Node = Op.Val; 3648 3649 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 3650 if (I != PromotedNodes.end()) return I->second; 3651 3652 switch (Node->getOpcode()) { 3653 case ISD::CopyFromReg: 3654 assert(0 && "CopyFromReg must be legal!"); 3655 default: 3656#ifndef NDEBUG 3657 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 3658#endif 3659 assert(0 && "Do not know how to promote this operator!"); 3660 abort(); 3661 case ISD::UNDEF: 3662 Result = DAG.getNode(ISD::UNDEF, NVT); 3663 break; 3664 case ISD::Constant: 3665 if (VT != MVT::i1) 3666 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 3667 else 3668 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 3669 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 3670 break; 3671 case ISD::ConstantFP: 3672 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 3673 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 3674 break; 3675 3676 case ISD::SETCC: 3677 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 3678 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 3679 Node->getOperand(1), Node->getOperand(2)); 3680 break; 3681 3682 case ISD::TRUNCATE: 3683 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3684 case Legal: 3685 Result = LegalizeOp(Node->getOperand(0)); 3686 assert(Result.getValueType() >= NVT && 3687 "This truncation doesn't make sense!"); 3688 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 3689 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 3690 break; 3691 case Promote: 3692 // The truncation is not required, because we don't guarantee anything 3693 // about high bits anyway. 3694 Result = PromoteOp(Node->getOperand(0)); 3695 break; 3696 case Expand: 3697 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3698 // Truncate the low part of the expanded value to the result type 3699 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 3700 } 3701 break; 3702 case ISD::SIGN_EXTEND: 3703 case ISD::ZERO_EXTEND: 3704 case ISD::ANY_EXTEND: 3705 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3706 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 3707 case Legal: 3708 // Input is legal? Just do extend all the way to the larger type. 3709 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3710 break; 3711 case Promote: 3712 // Promote the reg if it's smaller. 3713 Result = PromoteOp(Node->getOperand(0)); 3714 // The high bits are not guaranteed to be anything. Insert an extend. 3715 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3716 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3717 DAG.getValueType(Node->getOperand(0).getValueType())); 3718 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3719 Result = DAG.getZeroExtendInReg(Result, 3720 Node->getOperand(0).getValueType()); 3721 break; 3722 } 3723 break; 3724 case ISD::BIT_CONVERT: 3725 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3726 Result = PromoteOp(Result); 3727 break; 3728 3729 case ISD::FP_EXTEND: 3730 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3731 case ISD::FP_ROUND: 3732 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3733 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3734 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3735 case Legal: 3736 // Input is legal? Do an FP_ROUND_INREG. 3737 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 3738 DAG.getValueType(VT)); 3739 break; 3740 } 3741 break; 3742 3743 case ISD::SINT_TO_FP: 3744 case ISD::UINT_TO_FP: 3745 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3746 case Legal: 3747 // No extra round required here. 3748 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3749 break; 3750 3751 case Promote: 3752 Result = PromoteOp(Node->getOperand(0)); 3753 if (Node->getOpcode() == ISD::SINT_TO_FP) 3754 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3755 Result, 3756 DAG.getValueType(Node->getOperand(0).getValueType())); 3757 else 3758 Result = DAG.getZeroExtendInReg(Result, 3759 Node->getOperand(0).getValueType()); 3760 // No extra round required here. 3761 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3762 break; 3763 case Expand: 3764 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3765 Node->getOperand(0)); 3766 // Round if we cannot tolerate excess precision. 3767 if (NoExcessFPPrecision) 3768 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3769 DAG.getValueType(VT)); 3770 break; 3771 } 3772 break; 3773 3774 case ISD::SIGN_EXTEND_INREG: 3775 Result = PromoteOp(Node->getOperand(0)); 3776 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3777 Node->getOperand(1)); 3778 break; 3779 case ISD::FP_TO_SINT: 3780 case ISD::FP_TO_UINT: 3781 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3782 case Legal: 3783 case Expand: 3784 Tmp1 = Node->getOperand(0); 3785 break; 3786 case Promote: 3787 // The input result is prerounded, so we don't have to do anything 3788 // special. 3789 Tmp1 = PromoteOp(Node->getOperand(0)); 3790 break; 3791 } 3792 // If we're promoting a UINT to a larger size, check to see if the new node 3793 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3794 // we can use that instead. This allows us to generate better code for 3795 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3796 // legal, such as PowerPC. 3797 if (Node->getOpcode() == ISD::FP_TO_UINT && 3798 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3799 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3800 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3801 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3802 } else { 3803 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3804 } 3805 break; 3806 3807 case ISD::FABS: 3808 case ISD::FNEG: 3809 Tmp1 = PromoteOp(Node->getOperand(0)); 3810 assert(Tmp1.getValueType() == NVT); 3811 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3812 // NOTE: we do not have to do any extra rounding here for 3813 // NoExcessFPPrecision, because we know the input will have the appropriate 3814 // precision, and these operations don't modify precision at all. 3815 break; 3816 3817 case ISD::FSQRT: 3818 case ISD::FSIN: 3819 case ISD::FCOS: 3820 Tmp1 = PromoteOp(Node->getOperand(0)); 3821 assert(Tmp1.getValueType() == NVT); 3822 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3823 if (NoExcessFPPrecision) 3824 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3825 DAG.getValueType(VT)); 3826 break; 3827 3828 case ISD::FPOWI: { 3829 // Promote f32 powi to f64 powi. Note that this could insert a libcall 3830 // directly as well, which may be better. 3831 Tmp1 = PromoteOp(Node->getOperand(0)); 3832 assert(Tmp1.getValueType() == NVT); 3833 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 3834 if (NoExcessFPPrecision) 3835 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3836 DAG.getValueType(VT)); 3837 break; 3838 } 3839 3840 case ISD::AND: 3841 case ISD::OR: 3842 case ISD::XOR: 3843 case ISD::ADD: 3844 case ISD::SUB: 3845 case ISD::MUL: 3846 // The input may have strange things in the top bits of the registers, but 3847 // these operations don't care. They may have weird bits going out, but 3848 // that too is okay if they are integer operations. 3849 Tmp1 = PromoteOp(Node->getOperand(0)); 3850 Tmp2 = PromoteOp(Node->getOperand(1)); 3851 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3852 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3853 break; 3854 case ISD::FADD: 3855 case ISD::FSUB: 3856 case ISD::FMUL: 3857 Tmp1 = PromoteOp(Node->getOperand(0)); 3858 Tmp2 = PromoteOp(Node->getOperand(1)); 3859 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3860 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3861 3862 // Floating point operations will give excess precision that we may not be 3863 // able to tolerate. If we DO allow excess precision, just leave it, 3864 // otherwise excise it. 3865 // FIXME: Why would we need to round FP ops more than integer ones? 3866 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3867 if (NoExcessFPPrecision) 3868 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3869 DAG.getValueType(VT)); 3870 break; 3871 3872 case ISD::SDIV: 3873 case ISD::SREM: 3874 // These operators require that their input be sign extended. 3875 Tmp1 = PromoteOp(Node->getOperand(0)); 3876 Tmp2 = PromoteOp(Node->getOperand(1)); 3877 if (MVT::isInteger(NVT)) { 3878 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3879 DAG.getValueType(VT)); 3880 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3881 DAG.getValueType(VT)); 3882 } 3883 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3884 3885 // Perform FP_ROUND: this is probably overly pessimistic. 3886 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3887 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3888 DAG.getValueType(VT)); 3889 break; 3890 case ISD::FDIV: 3891 case ISD::FREM: 3892 case ISD::FCOPYSIGN: 3893 // These operators require that their input be fp extended. 3894 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3895 case Legal: 3896 Tmp1 = LegalizeOp(Node->getOperand(0)); 3897 break; 3898 case Promote: 3899 Tmp1 = PromoteOp(Node->getOperand(0)); 3900 break; 3901 case Expand: 3902 assert(0 && "not implemented"); 3903 } 3904 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3905 case Legal: 3906 Tmp2 = LegalizeOp(Node->getOperand(1)); 3907 break; 3908 case Promote: 3909 Tmp2 = PromoteOp(Node->getOperand(1)); 3910 break; 3911 case Expand: 3912 assert(0 && "not implemented"); 3913 } 3914 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3915 3916 // Perform FP_ROUND: this is probably overly pessimistic. 3917 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 3918 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3919 DAG.getValueType(VT)); 3920 break; 3921 3922 case ISD::UDIV: 3923 case ISD::UREM: 3924 // These operators require that their input be zero extended. 3925 Tmp1 = PromoteOp(Node->getOperand(0)); 3926 Tmp2 = PromoteOp(Node->getOperand(1)); 3927 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3928 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3929 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3930 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3931 break; 3932 3933 case ISD::SHL: 3934 Tmp1 = PromoteOp(Node->getOperand(0)); 3935 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 3936 break; 3937 case ISD::SRA: 3938 // The input value must be properly sign extended. 3939 Tmp1 = PromoteOp(Node->getOperand(0)); 3940 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3941 DAG.getValueType(VT)); 3942 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 3943 break; 3944 case ISD::SRL: 3945 // The input value must be properly zero extended. 3946 Tmp1 = PromoteOp(Node->getOperand(0)); 3947 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3948 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 3949 break; 3950 3951 case ISD::VAARG: 3952 Tmp1 = Node->getOperand(0); // Get the chain. 3953 Tmp2 = Node->getOperand(1); // Get the pointer. 3954 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 3955 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 3956 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 3957 } else { 3958 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 3959 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3960 SV->getValue(), SV->getOffset()); 3961 // Increment the pointer, VAList, to the next vaarg 3962 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3963 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3964 TLI.getPointerTy())); 3965 // Store the incremented VAList to the legalized pointer 3966 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 3967 SV->getOffset()); 3968 // Load the actual argument out of the pointer VAList 3969 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 3970 } 3971 // Remember that we legalized the chain. 3972 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3973 break; 3974 3975 case ISD::LOAD: { 3976 LoadSDNode *LD = cast<LoadSDNode>(Node); 3977 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 3978 ? ISD::EXTLOAD : LD->getExtensionType(); 3979 Result = DAG.getExtLoad(ExtType, NVT, 3980 LD->getChain(), LD->getBasePtr(), 3981 LD->getSrcValue(), LD->getSrcValueOffset(), 3982 LD->getLoadedVT(), 3983 LD->isVolatile(), 3984 LD->getAlignment()); 3985 // Remember that we legalized the chain. 3986 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3987 break; 3988 } 3989 case ISD::SELECT: 3990 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 3991 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 3992 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 3993 break; 3994 case ISD::SELECT_CC: 3995 Tmp2 = PromoteOp(Node->getOperand(2)); // True 3996 Tmp3 = PromoteOp(Node->getOperand(3)); // False 3997 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3998 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 3999 break; 4000 case ISD::BSWAP: 4001 Tmp1 = Node->getOperand(0); 4002 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4003 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4004 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4005 DAG.getConstant(MVT::getSizeInBits(NVT) - 4006 MVT::getSizeInBits(VT), 4007 TLI.getShiftAmountTy())); 4008 break; 4009 case ISD::CTPOP: 4010 case ISD::CTTZ: 4011 case ISD::CTLZ: 4012 // Zero extend the argument 4013 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4014 // Perform the larger operation, then subtract if needed. 4015 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4016 switch(Node->getOpcode()) { 4017 case ISD::CTPOP: 4018 Result = Tmp1; 4019 break; 4020 case ISD::CTTZ: 4021 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4022 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 4023 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 4024 ISD::SETEQ); 4025 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4026 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 4027 break; 4028 case ISD::CTLZ: 4029 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4030 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4031 DAG.getConstant(MVT::getSizeInBits(NVT) - 4032 MVT::getSizeInBits(VT), NVT)); 4033 break; 4034 } 4035 break; 4036 case ISD::EXTRACT_SUBVECTOR: 4037 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4038 break; 4039 case ISD::EXTRACT_VECTOR_ELT: 4040 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4041 break; 4042 } 4043 4044 assert(Result.Val && "Didn't set a result!"); 4045 4046 // Make sure the result is itself legal. 4047 Result = LegalizeOp(Result); 4048 4049 // Remember that we promoted this! 4050 AddPromotedOperand(Op, Result); 4051 return Result; 4052} 4053 4054/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4055/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4056/// based on the vector type. The return type of this matches the element type 4057/// of the vector, which may not be legal for the target. 4058SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4059 // We know that operand #0 is the Vec vector. If the index is a constant 4060 // or if the invec is a supported hardware type, we can use it. Otherwise, 4061 // lower to a store then an indexed load. 4062 SDOperand Vec = Op.getOperand(0); 4063 SDOperand Idx = Op.getOperand(1); 4064 4065 MVT::ValueType TVT = Vec.getValueType(); 4066 unsigned NumElems = MVT::getVectorNumElements(TVT); 4067 4068 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4069 default: assert(0 && "This action is not supported yet!"); 4070 case TargetLowering::Custom: { 4071 Vec = LegalizeOp(Vec); 4072 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4073 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4074 if (Tmp3.Val) 4075 return Tmp3; 4076 break; 4077 } 4078 case TargetLowering::Legal: 4079 if (isTypeLegal(TVT)) { 4080 Vec = LegalizeOp(Vec); 4081 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4082 return Op; 4083 } 4084 break; 4085 case TargetLowering::Expand: 4086 break; 4087 } 4088 4089 if (NumElems == 1) { 4090 // This must be an access of the only element. Return it. 4091 Op = ScalarizeVectorOp(Vec); 4092 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4093 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4094 SDOperand Lo, Hi; 4095 SplitVectorOp(Vec, Lo, Hi); 4096 if (CIdx->getValue() < NumElems/2) { 4097 Vec = Lo; 4098 } else { 4099 Vec = Hi; 4100 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, 4101 Idx.getValueType()); 4102 } 4103 4104 // It's now an extract from the appropriate high or low part. Recurse. 4105 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4106 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4107 } else { 4108 // Store the value to a temporary stack slot, then LOAD the scalar 4109 // element back out. 4110 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType()); 4111 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4112 4113 // Add the offset to the index. 4114 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 4115 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4116 DAG.getConstant(EltSize, Idx.getValueType())); 4117 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4118 4119 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4120 } 4121 return Op; 4122} 4123 4124/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4125/// we assume the operation can be split if it is not already legal. 4126SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4127 // We know that operand #0 is the Vec vector. For now we assume the index 4128 // is a constant and that the extracted result is a supported hardware type. 4129 SDOperand Vec = Op.getOperand(0); 4130 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4131 4132 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); 4133 4134 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 4135 // This must be an access of the desired vector length. Return it. 4136 return Vec; 4137 } 4138 4139 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4140 SDOperand Lo, Hi; 4141 SplitVectorOp(Vec, Lo, Hi); 4142 if (CIdx->getValue() < NumElems/2) { 4143 Vec = Lo; 4144 } else { 4145 Vec = Hi; 4146 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4147 } 4148 4149 // It's now an extract from the appropriate high or low part. Recurse. 4150 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4151 return ExpandEXTRACT_SUBVECTOR(Op); 4152} 4153 4154/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4155/// with condition CC on the current target. This usually involves legalizing 4156/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4157/// there may be no choice but to create a new SetCC node to represent the 4158/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4159/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4160void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4161 SDOperand &RHS, 4162 SDOperand &CC) { 4163 SDOperand Tmp1, Tmp2, Tmp3, Result; 4164 4165 switch (getTypeAction(LHS.getValueType())) { 4166 case Legal: 4167 Tmp1 = LegalizeOp(LHS); // LHS 4168 Tmp2 = LegalizeOp(RHS); // RHS 4169 break; 4170 case Promote: 4171 Tmp1 = PromoteOp(LHS); // LHS 4172 Tmp2 = PromoteOp(RHS); // RHS 4173 4174 // If this is an FP compare, the operands have already been extended. 4175 if (MVT::isInteger(LHS.getValueType())) { 4176 MVT::ValueType VT = LHS.getValueType(); 4177 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4178 4179 // Otherwise, we have to insert explicit sign or zero extends. Note 4180 // that we could insert sign extends for ALL conditions, but zero extend 4181 // is cheaper on many machines (an AND instead of two shifts), so prefer 4182 // it. 4183 switch (cast<CondCodeSDNode>(CC)->get()) { 4184 default: assert(0 && "Unknown integer comparison!"); 4185 case ISD::SETEQ: 4186 case ISD::SETNE: 4187 case ISD::SETUGE: 4188 case ISD::SETUGT: 4189 case ISD::SETULE: 4190 case ISD::SETULT: 4191 // ALL of these operations will work if we either sign or zero extend 4192 // the operands (including the unsigned comparisons!). Zero extend is 4193 // usually a simpler/cheaper operation, so prefer it. 4194 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4195 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4196 break; 4197 case ISD::SETGE: 4198 case ISD::SETGT: 4199 case ISD::SETLT: 4200 case ISD::SETLE: 4201 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4202 DAG.getValueType(VT)); 4203 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4204 DAG.getValueType(VT)); 4205 break; 4206 } 4207 } 4208 break; 4209 case Expand: { 4210 MVT::ValueType VT = LHS.getValueType(); 4211 if (VT == MVT::f32 || VT == MVT::f64) { 4212 // Expand into one or more soft-fp libcall(s). 4213 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4214 switch (cast<CondCodeSDNode>(CC)->get()) { 4215 case ISD::SETEQ: 4216 case ISD::SETOEQ: 4217 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4218 break; 4219 case ISD::SETNE: 4220 case ISD::SETUNE: 4221 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4222 break; 4223 case ISD::SETGE: 4224 case ISD::SETOGE: 4225 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4226 break; 4227 case ISD::SETLT: 4228 case ISD::SETOLT: 4229 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4230 break; 4231 case ISD::SETLE: 4232 case ISD::SETOLE: 4233 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4234 break; 4235 case ISD::SETGT: 4236 case ISD::SETOGT: 4237 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4238 break; 4239 case ISD::SETUO: 4240 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4241 break; 4242 case ISD::SETO: 4243 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4244 break; 4245 default: 4246 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4247 switch (cast<CondCodeSDNode>(CC)->get()) { 4248 case ISD::SETONE: 4249 // SETONE = SETOLT | SETOGT 4250 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4251 // Fallthrough 4252 case ISD::SETUGT: 4253 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4254 break; 4255 case ISD::SETUGE: 4256 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4257 break; 4258 case ISD::SETULT: 4259 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4260 break; 4261 case ISD::SETULE: 4262 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4263 break; 4264 case ISD::SETUEQ: 4265 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4266 break; 4267 default: assert(0 && "Unsupported FP setcc!"); 4268 } 4269 } 4270 4271 SDOperand Dummy; 4272 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 4273 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4274 false /*sign irrelevant*/, Dummy); 4275 Tmp2 = DAG.getConstant(0, MVT::i32); 4276 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4277 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4278 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 4279 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 4280 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4281 false /*sign irrelevant*/, Dummy); 4282 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 4283 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4284 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4285 Tmp2 = SDOperand(); 4286 } 4287 LHS = Tmp1; 4288 RHS = Tmp2; 4289 return; 4290 } 4291 4292 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4293 ExpandOp(LHS, LHSLo, LHSHi); 4294 ExpandOp(RHS, RHSLo, RHSHi); 4295 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4296 4297 if (VT==MVT::ppcf128) { 4298 // FIXME: This generated code sucks. We want to generate 4299 // FCMP crN, hi1, hi2 4300 // BNE crN, L: 4301 // FCMP crN, lo1, lo2 4302 // The following can be improved, but not that much. 4303 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4304 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode); 4305 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4306 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE); 4307 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode); 4308 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4309 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4310 Tmp2 = SDOperand(); 4311 break; 4312 } 4313 4314 switch (CCCode) { 4315 case ISD::SETEQ: 4316 case ISD::SETNE: 4317 if (RHSLo == RHSHi) 4318 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4319 if (RHSCST->isAllOnesValue()) { 4320 // Comparison to -1. 4321 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4322 Tmp2 = RHSLo; 4323 break; 4324 } 4325 4326 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4327 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4328 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4329 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4330 break; 4331 default: 4332 // If this is a comparison of the sign bit, just look at the top part. 4333 // X > -1, x < 0 4334 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4335 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4336 CST->getValue() == 0) || // X < 0 4337 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4338 CST->isAllOnesValue())) { // X > -1 4339 Tmp1 = LHSHi; 4340 Tmp2 = RHSHi; 4341 break; 4342 } 4343 4344 // FIXME: This generated code sucks. 4345 ISD::CondCode LowCC; 4346 switch (CCCode) { 4347 default: assert(0 && "Unknown integer setcc!"); 4348 case ISD::SETLT: 4349 case ISD::SETULT: LowCC = ISD::SETULT; break; 4350 case ISD::SETGT: 4351 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4352 case ISD::SETLE: 4353 case ISD::SETULE: LowCC = ISD::SETULE; break; 4354 case ISD::SETGE: 4355 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4356 } 4357 4358 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4359 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4360 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4361 4362 // NOTE: on targets without efficient SELECT of bools, we can always use 4363 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4364 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4365 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, 4366 false, DagCombineInfo); 4367 if (!Tmp1.Val) 4368 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 4369 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4370 CCCode, false, DagCombineInfo); 4371 if (!Tmp2.Val) 4372 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC); 4373 4374 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4375 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4376 if ((Tmp1C && Tmp1C->getValue() == 0) || 4377 (Tmp2C && Tmp2C->getValue() == 0 && 4378 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4379 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4380 (Tmp2C && Tmp2C->getValue() == 1 && 4381 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4382 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4383 // low part is known false, returns high part. 4384 // For LE / GE, if high part is known false, ignore the low part. 4385 // For LT / GT, if high part is known true, ignore the low part. 4386 Tmp1 = Tmp2; 4387 Tmp2 = SDOperand(); 4388 } else { 4389 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4390 ISD::SETEQ, false, DagCombineInfo); 4391 if (!Result.Val) 4392 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4393 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4394 Result, Tmp1, Tmp2)); 4395 Tmp1 = Result; 4396 Tmp2 = SDOperand(); 4397 } 4398 } 4399 } 4400 } 4401 LHS = Tmp1; 4402 RHS = Tmp2; 4403} 4404 4405/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 4406/// The resultant code need not be legal. Note that SrcOp is the input operand 4407/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 4408SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 4409 SDOperand SrcOp) { 4410 // Create the stack frame object. 4411 SDOperand FIPtr = CreateStackTemporary(DestVT); 4412 4413 // Emit a store to the stack slot. 4414 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); 4415 // Result is a load from the stack slot. 4416 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4417} 4418 4419SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4420 // Create a vector sized/aligned stack slot, store the value to element #0, 4421 // then load the whole vector back out. 4422 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); 4423 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4424 NULL, 0); 4425 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 4426} 4427 4428 4429/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4430/// support the operation, but do support the resultant vector type. 4431SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4432 4433 // If the only non-undef value is the low element, turn this into a 4434 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4435 unsigned NumElems = Node->getNumOperands(); 4436 bool isOnlyLowElement = true; 4437 SDOperand SplatValue = Node->getOperand(0); 4438 std::map<SDOperand, std::vector<unsigned> > Values; 4439 Values[SplatValue].push_back(0); 4440 bool isConstant = true; 4441 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4442 SplatValue.getOpcode() != ISD::UNDEF) 4443 isConstant = false; 4444 4445 for (unsigned i = 1; i < NumElems; ++i) { 4446 SDOperand V = Node->getOperand(i); 4447 Values[V].push_back(i); 4448 if (V.getOpcode() != ISD::UNDEF) 4449 isOnlyLowElement = false; 4450 if (SplatValue != V) 4451 SplatValue = SDOperand(0,0); 4452 4453 // If this isn't a constant element or an undef, we can't use a constant 4454 // pool load. 4455 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4456 V.getOpcode() != ISD::UNDEF) 4457 isConstant = false; 4458 } 4459 4460 if (isOnlyLowElement) { 4461 // If the low element is an undef too, then this whole things is an undef. 4462 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4463 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4464 // Otherwise, turn this into a scalar_to_vector node. 4465 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4466 Node->getOperand(0)); 4467 } 4468 4469 // If all elements are constants, create a load from the constant pool. 4470 if (isConstant) { 4471 MVT::ValueType VT = Node->getValueType(0); 4472 const Type *OpNTy = 4473 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 4474 std::vector<Constant*> CV; 4475 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4476 if (ConstantFPSDNode *V = 4477 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4478 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF())); 4479 } else if (ConstantSDNode *V = 4480 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4481 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 4482 } else { 4483 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4484 CV.push_back(UndefValue::get(OpNTy)); 4485 } 4486 } 4487 Constant *CP = ConstantVector::get(CV); 4488 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4489 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 4490 } 4491 4492 if (SplatValue.Val) { // Splat of one value? 4493 // Build the shuffle constant vector: <0, 0, 0, 0> 4494 MVT::ValueType MaskVT = 4495 MVT::getIntVectorWithNumElements(NumElems); 4496 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 4497 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4498 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4499 &ZeroVec[0], ZeroVec.size()); 4500 4501 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4502 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4503 // Get the splatted value into the low element of a vector register. 4504 SDOperand LowValVec = 4505 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4506 4507 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4508 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4509 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4510 SplatMask); 4511 } 4512 } 4513 4514 // If there are only two unique elements, we may be able to turn this into a 4515 // vector shuffle. 4516 if (Values.size() == 2) { 4517 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 4518 MVT::ValueType MaskVT = 4519 MVT::getIntVectorWithNumElements(NumElems); 4520 std::vector<SDOperand> MaskVec(NumElems); 4521 unsigned i = 0; 4522 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4523 E = Values.end(); I != E; ++I) { 4524 for (std::vector<unsigned>::iterator II = I->second.begin(), 4525 EE = I->second.end(); II != EE; ++II) 4526 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT)); 4527 i += NumElems; 4528 } 4529 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4530 &MaskVec[0], MaskVec.size()); 4531 4532 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4533 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 4534 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 4535 SmallVector<SDOperand, 8> Ops; 4536 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4537 E = Values.end(); I != E; ++I) { 4538 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4539 I->first); 4540 Ops.push_back(Op); 4541 } 4542 Ops.push_back(ShuffleMask); 4543 4544 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 4545 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 4546 &Ops[0], Ops.size()); 4547 } 4548 } 4549 4550 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 4551 // aligned object on the stack, store each element into it, then load 4552 // the result as a vector. 4553 MVT::ValueType VT = Node->getValueType(0); 4554 // Create the stack frame object. 4555 SDOperand FIPtr = CreateStackTemporary(VT); 4556 4557 // Emit a store of each element to the stack slot. 4558 SmallVector<SDOperand, 8> Stores; 4559 unsigned TypeByteSize = 4560 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 4561 // Store (in the right endianness) the elements to memory. 4562 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4563 // Ignore undef elements. 4564 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4565 4566 unsigned Offset = TypeByteSize*i; 4567 4568 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 4569 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 4570 4571 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 4572 NULL, 0)); 4573 } 4574 4575 SDOperand StoreChain; 4576 if (!Stores.empty()) // Not all undef elements? 4577 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4578 &Stores[0], Stores.size()); 4579 else 4580 StoreChain = DAG.getEntryNode(); 4581 4582 // Result is a load from the stack slot. 4583 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 4584} 4585 4586/// CreateStackTemporary - Create a stack temporary, suitable for holding the 4587/// specified value type. 4588SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) { 4589 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 4590 unsigned ByteSize = MVT::getSizeInBits(VT)/8; 4591 const Type *Ty = MVT::getTypeForValueType(VT); 4592 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty); 4593 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign); 4594 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 4595} 4596 4597void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 4598 SDOperand Op, SDOperand Amt, 4599 SDOperand &Lo, SDOperand &Hi) { 4600 // Expand the subcomponents. 4601 SDOperand LHSL, LHSH; 4602 ExpandOp(Op, LHSL, LHSH); 4603 4604 SDOperand Ops[] = { LHSL, LHSH, Amt }; 4605 MVT::ValueType VT = LHSL.getValueType(); 4606 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 4607 Hi = Lo.getValue(1); 4608} 4609 4610 4611/// ExpandShift - Try to find a clever way to expand this shift operation out to 4612/// smaller elements. If we can't find a way that is more efficient than a 4613/// libcall on this target, return false. Otherwise, return true with the 4614/// low-parts expanded into Lo and Hi. 4615bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 4616 SDOperand &Lo, SDOperand &Hi) { 4617 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 4618 "This is not a shift!"); 4619 4620 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 4621 SDOperand ShAmt = LegalizeOp(Amt); 4622 MVT::ValueType ShTy = ShAmt.getValueType(); 4623 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 4624 unsigned NVTBits = MVT::getSizeInBits(NVT); 4625 4626 // Handle the case when Amt is an immediate. Other cases are currently broken 4627 // and are disabled. 4628 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 4629 unsigned Cst = CN->getValue(); 4630 // Expand the incoming operand to be shifted, so that we have its parts 4631 SDOperand InL, InH; 4632 ExpandOp(Op, InL, InH); 4633 switch(Opc) { 4634 case ISD::SHL: 4635 if (Cst > VTBits) { 4636 Lo = DAG.getConstant(0, NVT); 4637 Hi = DAG.getConstant(0, NVT); 4638 } else if (Cst > NVTBits) { 4639 Lo = DAG.getConstant(0, NVT); 4640 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 4641 } else if (Cst == NVTBits) { 4642 Lo = DAG.getConstant(0, NVT); 4643 Hi = InL; 4644 } else { 4645 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 4646 Hi = DAG.getNode(ISD::OR, NVT, 4647 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 4648 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 4649 } 4650 return true; 4651 case ISD::SRL: 4652 if (Cst > VTBits) { 4653 Lo = DAG.getConstant(0, NVT); 4654 Hi = DAG.getConstant(0, NVT); 4655 } else if (Cst > NVTBits) { 4656 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 4657 Hi = DAG.getConstant(0, NVT); 4658 } else if (Cst == NVTBits) { 4659 Lo = InH; 4660 Hi = DAG.getConstant(0, NVT); 4661 } else { 4662 Lo = DAG.getNode(ISD::OR, NVT, 4663 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4664 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4665 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 4666 } 4667 return true; 4668 case ISD::SRA: 4669 if (Cst > VTBits) { 4670 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 4671 DAG.getConstant(NVTBits-1, ShTy)); 4672 } else if (Cst > NVTBits) { 4673 Lo = DAG.getNode(ISD::SRA, NVT, InH, 4674 DAG.getConstant(Cst-NVTBits, ShTy)); 4675 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4676 DAG.getConstant(NVTBits-1, ShTy)); 4677 } else if (Cst == NVTBits) { 4678 Lo = InH; 4679 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4680 DAG.getConstant(NVTBits-1, ShTy)); 4681 } else { 4682 Lo = DAG.getNode(ISD::OR, NVT, 4683 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4684 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4685 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 4686 } 4687 return true; 4688 } 4689 } 4690 4691 // Okay, the shift amount isn't constant. However, if we can tell that it is 4692 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 4693 uint64_t Mask = NVTBits, KnownZero, KnownOne; 4694 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 4695 4696 // If we know that the high bit of the shift amount is one, then we can do 4697 // this as a couple of simple shifts. 4698 if (KnownOne & Mask) { 4699 // Mask out the high bit, which we know is set. 4700 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 4701 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4702 4703 // Expand the incoming operand to be shifted, so that we have its parts 4704 SDOperand InL, InH; 4705 ExpandOp(Op, InL, InH); 4706 switch(Opc) { 4707 case ISD::SHL: 4708 Lo = DAG.getConstant(0, NVT); // Low part is zero. 4709 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 4710 return true; 4711 case ISD::SRL: 4712 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 4713 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 4714 return true; 4715 case ISD::SRA: 4716 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 4717 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4718 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 4719 return true; 4720 } 4721 } 4722 4723 // If we know that the high bit of the shift amount is zero, then we can do 4724 // this as a couple of simple shifts. 4725 if (KnownZero & Mask) { 4726 // Compute 32-amt. 4727 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 4728 DAG.getConstant(NVTBits, Amt.getValueType()), 4729 Amt); 4730 4731 // Expand the incoming operand to be shifted, so that we have its parts 4732 SDOperand InL, InH; 4733 ExpandOp(Op, InL, InH); 4734 switch(Opc) { 4735 case ISD::SHL: 4736 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 4737 Hi = DAG.getNode(ISD::OR, NVT, 4738 DAG.getNode(ISD::SHL, NVT, InH, Amt), 4739 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 4740 return true; 4741 case ISD::SRL: 4742 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 4743 Lo = DAG.getNode(ISD::OR, NVT, 4744 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4745 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4746 return true; 4747 case ISD::SRA: 4748 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 4749 Lo = DAG.getNode(ISD::OR, NVT, 4750 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4751 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4752 return true; 4753 } 4754 } 4755 4756 return false; 4757} 4758 4759 4760// ExpandLibCall - Expand a node into a call to a libcall. If the result value 4761// does not fit into a register, return the lo part and set the hi part to the 4762// by-reg argument. If it does fit into a single register, return the result 4763// and leave the Hi part unset. 4764SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 4765 bool isSigned, SDOperand &Hi) { 4766 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 4767 // The input chain to this libcall is the entry node of the function. 4768 // Legalizing the call will automatically add the previous call to the 4769 // dependence. 4770 SDOperand InChain = DAG.getEntryNode(); 4771 4772 TargetLowering::ArgListTy Args; 4773 TargetLowering::ArgListEntry Entry; 4774 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4775 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 4776 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 4777 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 4778 Entry.isSExt = isSigned; 4779 Args.push_back(Entry); 4780 } 4781 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 4782 4783 // Splice the libcall in wherever FindInputOutputChains tells us to. 4784 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 4785 std::pair<SDOperand,SDOperand> CallInfo = 4786 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false, 4787 Callee, Args, DAG); 4788 4789 // Legalize the call sequence, starting with the chain. This will advance 4790 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 4791 // was added by LowerCallTo (guaranteeing proper serialization of calls). 4792 LegalizeOp(CallInfo.second); 4793 SDOperand Result; 4794 switch (getTypeAction(CallInfo.first.getValueType())) { 4795 default: assert(0 && "Unknown thing"); 4796 case Legal: 4797 Result = CallInfo.first; 4798 break; 4799 case Expand: 4800 ExpandOp(CallInfo.first, Result, Hi); 4801 break; 4802 } 4803 return Result; 4804} 4805 4806 4807/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 4808/// 4809SDOperand SelectionDAGLegalize:: 4810ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 4811 assert(getTypeAction(Source.getValueType()) == Expand && 4812 "This is not an expansion!"); 4813 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 4814 4815 if (!isSigned) { 4816 assert(Source.getValueType() == MVT::i64 && 4817 "This only works for 64-bit -> FP"); 4818 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 4819 // incoming integer is set. To handle this, we dynamically test to see if 4820 // it is set, and, if so, add a fudge factor. 4821 SDOperand Lo, Hi; 4822 ExpandOp(Source, Lo, Hi); 4823 4824 // If this is unsigned, and not supported, first perform the conversion to 4825 // signed, then adjust the result if the sign bit is set. 4826 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 4827 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 4828 4829 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 4830 DAG.getConstant(0, Hi.getValueType()), 4831 ISD::SETLT); 4832 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4833 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4834 SignSet, Four, Zero); 4835 uint64_t FF = 0x5f800000ULL; 4836 if (TLI.isLittleEndian()) FF <<= 32; 4837 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4838 4839 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4840 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4841 SDOperand FudgeInReg; 4842 if (DestTy == MVT::f32) 4843 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4844 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) 4845 // FIXME: Avoid the extend by construction the right constantpool? 4846 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 4847 CPIdx, NULL, 0, MVT::f32); 4848 else 4849 assert(0 && "Unexpected conversion"); 4850 4851 MVT::ValueType SCVT = SignedConv.getValueType(); 4852 if (SCVT != DestTy) { 4853 // Destination type needs to be expanded as well. The FADD now we are 4854 // constructing will be expanded into a libcall. 4855 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 4856 assert(SCVT == MVT::i32 && DestTy == MVT::f64); 4857 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, 4858 SignedConv, SignedConv.getValue(1)); 4859 } 4860 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 4861 } 4862 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 4863 } 4864 4865 // Check to see if the target has a custom way to lower this. If so, use it. 4866 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 4867 default: assert(0 && "This action not implemented for this operation!"); 4868 case TargetLowering::Legal: 4869 case TargetLowering::Expand: 4870 break; // This case is handled below. 4871 case TargetLowering::Custom: { 4872 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 4873 Source), DAG); 4874 if (NV.Val) 4875 return LegalizeOp(NV); 4876 break; // The target decided this was legal after all 4877 } 4878 } 4879 4880 // Expand the source, then glue it back together for the call. We must expand 4881 // the source in case it is shared (this pass of legalize must traverse it). 4882 SDOperand SrcLo, SrcHi; 4883 ExpandOp(Source, SrcLo, SrcHi); 4884 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 4885 4886 RTLIB::Libcall LC; 4887 if (DestTy == MVT::f32) 4888 LC = RTLIB::SINTTOFP_I64_F32; 4889 else { 4890 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 4891 LC = RTLIB::SINTTOFP_I64_F64; 4892 } 4893 4894 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 4895 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 4896 SDOperand UnusedHiPart; 4897 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 4898 UnusedHiPart); 4899} 4900 4901/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 4902/// INT_TO_FP operation of the specified operand when the target requests that 4903/// we expand it. At this point, we know that the result and operand types are 4904/// legal for the target. 4905SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 4906 SDOperand Op0, 4907 MVT::ValueType DestVT) { 4908 if (Op0.getValueType() == MVT::i32) { 4909 // simple 32-bit [signed|unsigned] integer to float/double expansion 4910 4911 // get the stack frame index of a 8 byte buffer, pessimistically aligned 4912 MachineFunction &MF = DAG.getMachineFunction(); 4913 const Type *F64Type = MVT::getTypeForValueType(MVT::f64); 4914 unsigned StackAlign = 4915 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type); 4916 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign); 4917 // get address of 8 byte buffer 4918 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 4919 // word offset constant for Hi/Lo address computation 4920 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 4921 // set up Hi and Lo (into buffer) address based on endian 4922 SDOperand Hi = StackSlot; 4923 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 4924 if (TLI.isLittleEndian()) 4925 std::swap(Hi, Lo); 4926 4927 // if signed map to unsigned space 4928 SDOperand Op0Mapped; 4929 if (isSigned) { 4930 // constant used to invert sign bit (signed to unsigned mapping) 4931 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 4932 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 4933 } else { 4934 Op0Mapped = Op0; 4935 } 4936 // store the lo of the constructed double - based on integer input 4937 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 4938 Op0Mapped, Lo, NULL, 0); 4939 // initial hi portion of constructed double 4940 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 4941 // store the hi of the constructed double - biased exponent 4942 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 4943 // load the constructed double 4944 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 4945 // FP constant to bias correct the final result 4946 SDOperand Bias = DAG.getConstantFP(isSigned ? 4947 BitsToDouble(0x4330000080000000ULL) 4948 : BitsToDouble(0x4330000000000000ULL), 4949 MVT::f64); 4950 // subtract the bias 4951 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 4952 // final result 4953 SDOperand Result; 4954 // handle final rounding 4955 if (DestVT == MVT::f64) { 4956 // do nothing 4957 Result = Sub; 4958 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { 4959 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub); 4960 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { 4961 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 4962 } 4963 return Result; 4964 } 4965 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 4966 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 4967 4968 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 4969 DAG.getConstant(0, Op0.getValueType()), 4970 ISD::SETLT); 4971 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4972 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4973 SignSet, Four, Zero); 4974 4975 // If the sign bit of the integer is set, the large number will be treated 4976 // as a negative number. To counteract this, the dynamic code adds an 4977 // offset depending on the data type. 4978 uint64_t FF; 4979 switch (Op0.getValueType()) { 4980 default: assert(0 && "Unsupported integer type!"); 4981 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 4982 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 4983 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 4984 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 4985 } 4986 if (TLI.isLittleEndian()) FF <<= 32; 4987 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 4988 4989 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 4990 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 4991 SDOperand FudgeInReg; 4992 if (DestVT == MVT::f32) 4993 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 4994 else { 4995 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 4996 DAG.getEntryNode(), CPIdx, 4997 NULL, 0, MVT::f32)); 4998 } 4999 5000 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5001} 5002 5003/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5004/// *INT_TO_FP operation of the specified operand when the target requests that 5005/// we promote it. At this point, we know that the result and operand types are 5006/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5007/// operation that takes a larger input. 5008SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5009 MVT::ValueType DestVT, 5010 bool isSigned) { 5011 // First step, figure out the appropriate *INT_TO_FP operation to use. 5012 MVT::ValueType NewInTy = LegalOp.getValueType(); 5013 5014 unsigned OpToUse = 0; 5015 5016 // Scan for the appropriate larger type to use. 5017 while (1) { 5018 NewInTy = (MVT::ValueType)(NewInTy+1); 5019 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 5020 5021 // If the target supports SINT_TO_FP of this type, use it. 5022 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5023 default: break; 5024 case TargetLowering::Legal: 5025 if (!TLI.isTypeLegal(NewInTy)) 5026 break; // Can't use this datatype. 5027 // FALL THROUGH. 5028 case TargetLowering::Custom: 5029 OpToUse = ISD::SINT_TO_FP; 5030 break; 5031 } 5032 if (OpToUse) break; 5033 if (isSigned) continue; 5034 5035 // If the target supports UINT_TO_FP of this type, use it. 5036 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5037 default: break; 5038 case TargetLowering::Legal: 5039 if (!TLI.isTypeLegal(NewInTy)) 5040 break; // Can't use this datatype. 5041 // FALL THROUGH. 5042 case TargetLowering::Custom: 5043 OpToUse = ISD::UINT_TO_FP; 5044 break; 5045 } 5046 if (OpToUse) break; 5047 5048 // Otherwise, try a larger type. 5049 } 5050 5051 // Okay, we found the operation and type to use. Zero extend our input to the 5052 // desired type then run the operation on it. 5053 return DAG.getNode(OpToUse, DestVT, 5054 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5055 NewInTy, LegalOp)); 5056} 5057 5058/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5059/// FP_TO_*INT operation of the specified operand when the target requests that 5060/// we promote it. At this point, we know that the result and operand types are 5061/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5062/// operation that returns a larger result. 5063SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5064 MVT::ValueType DestVT, 5065 bool isSigned) { 5066 // First step, figure out the appropriate FP_TO*INT operation to use. 5067 MVT::ValueType NewOutTy = DestVT; 5068 5069 unsigned OpToUse = 0; 5070 5071 // Scan for the appropriate larger type to use. 5072 while (1) { 5073 NewOutTy = (MVT::ValueType)(NewOutTy+1); 5074 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 5075 5076 // If the target supports FP_TO_SINT returning this type, use it. 5077 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5078 default: break; 5079 case TargetLowering::Legal: 5080 if (!TLI.isTypeLegal(NewOutTy)) 5081 break; // Can't use this datatype. 5082 // FALL THROUGH. 5083 case TargetLowering::Custom: 5084 OpToUse = ISD::FP_TO_SINT; 5085 break; 5086 } 5087 if (OpToUse) break; 5088 5089 // If the target supports FP_TO_UINT of this type, use it. 5090 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5091 default: break; 5092 case TargetLowering::Legal: 5093 if (!TLI.isTypeLegal(NewOutTy)) 5094 break; // Can't use this datatype. 5095 // FALL THROUGH. 5096 case TargetLowering::Custom: 5097 OpToUse = ISD::FP_TO_UINT; 5098 break; 5099 } 5100 if (OpToUse) break; 5101 5102 // Otherwise, try a larger type. 5103 } 5104 5105 // Okay, we found the operation and type to use. Truncate the result of the 5106 // extended FP_TO_*INT operation to the desired size. 5107 return DAG.getNode(ISD::TRUNCATE, DestVT, 5108 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 5109} 5110 5111/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5112/// 5113SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5114 MVT::ValueType VT = Op.getValueType(); 5115 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 5116 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5117 switch (VT) { 5118 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5119 case MVT::i16: 5120 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5121 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5122 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5123 case MVT::i32: 5124 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5125 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5126 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5127 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5128 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5129 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5130 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5131 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5132 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5133 case MVT::i64: 5134 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5135 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5136 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5137 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5138 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5139 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5140 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5141 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5142 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5143 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5144 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5145 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5146 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5147 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5148 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5149 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5150 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5151 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5152 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5153 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5154 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5155 } 5156} 5157 5158/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5159/// 5160SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5161 switch (Opc) { 5162 default: assert(0 && "Cannot expand this yet!"); 5163 case ISD::CTPOP: { 5164 static const uint64_t mask[6] = { 5165 0x5555555555555555ULL, 0x3333333333333333ULL, 5166 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5167 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5168 }; 5169 MVT::ValueType VT = Op.getValueType(); 5170 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5171 unsigned len = MVT::getSizeInBits(VT); 5172 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5173 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5174 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5175 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5176 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5177 DAG.getNode(ISD::AND, VT, 5178 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5179 } 5180 return Op; 5181 } 5182 case ISD::CTLZ: { 5183 // for now, we do this: 5184 // x = x | (x >> 1); 5185 // x = x | (x >> 2); 5186 // ... 5187 // x = x | (x >>16); 5188 // x = x | (x >>32); // for 64-bit input 5189 // return popcount(~x); 5190 // 5191 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5192 MVT::ValueType VT = Op.getValueType(); 5193 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5194 unsigned len = MVT::getSizeInBits(VT); 5195 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5196 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5197 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5198 } 5199 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5200 return DAG.getNode(ISD::CTPOP, VT, Op); 5201 } 5202 case ISD::CTTZ: { 5203 // for now, we use: { return popcount(~x & (x - 1)); } 5204 // unless the target has ctlz but not ctpop, in which case we use: 5205 // { return 32 - nlz(~x & (x-1)); } 5206 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5207 MVT::ValueType VT = Op.getValueType(); 5208 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5209 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5210 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5211 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5212 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5213 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5214 TLI.isOperationLegal(ISD::CTLZ, VT)) 5215 return DAG.getNode(ISD::SUB, VT, 5216 DAG.getConstant(MVT::getSizeInBits(VT), VT), 5217 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5218 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5219 } 5220 } 5221} 5222 5223/// ExpandOp - Expand the specified SDOperand into its two component pieces 5224/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5225/// LegalizeNodes map is filled in for any results that are not expanded, the 5226/// ExpandedNodes map is filled in for any results that are expanded, and the 5227/// Lo/Hi values are returned. 5228void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5229 MVT::ValueType VT = Op.getValueType(); 5230 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 5231 SDNode *Node = Op.Val; 5232 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5233 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 5234 MVT::isVector(VT)) && 5235 "Cannot expand to FP value or to larger int value!"); 5236 5237 // See if we already expanded it. 5238 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5239 = ExpandedNodes.find(Op); 5240 if (I != ExpandedNodes.end()) { 5241 Lo = I->second.first; 5242 Hi = I->second.second; 5243 return; 5244 } 5245 5246 switch (Node->getOpcode()) { 5247 case ISD::CopyFromReg: 5248 assert(0 && "CopyFromReg must be legal!"); 5249 case ISD::FP_ROUND_INREG: 5250 if (VT == MVT::ppcf128 && 5251 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5252 TargetLowering::Custom) { 5253 SDOperand SrcLo, SrcHi, Src; 5254 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5255 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5256 SDOperand Result = TLI.LowerOperation( 5257 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5258 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5259 Lo = Result.Val->getOperand(0); 5260 Hi = Result.Val->getOperand(1); 5261 break; 5262 } 5263 // fall through 5264 default: 5265#ifndef NDEBUG 5266 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5267#endif 5268 assert(0 && "Do not know how to expand this operator!"); 5269 abort(); 5270 case ISD::UNDEF: 5271 NVT = TLI.getTypeToExpandTo(VT); 5272 Lo = DAG.getNode(ISD::UNDEF, NVT); 5273 Hi = DAG.getNode(ISD::UNDEF, NVT); 5274 break; 5275 case ISD::Constant: { 5276 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 5277 Lo = DAG.getConstant(Cst, NVT); 5278 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 5279 break; 5280 } 5281 case ISD::ConstantFP: { 5282 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5283 if (CFP->getValueType(0) == MVT::ppcf128) { 5284 APInt api = CFP->getValueAPF().convertToAPInt(); 5285 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5286 MVT::f64); 5287 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5288 MVT::f64); 5289 break; 5290 } 5291 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5292 if (getTypeAction(Lo.getValueType()) == Expand) 5293 ExpandOp(Lo, Lo, Hi); 5294 break; 5295 } 5296 case ISD::BUILD_PAIR: 5297 // Return the operands. 5298 Lo = Node->getOperand(0); 5299 Hi = Node->getOperand(1); 5300 break; 5301 5302 case ISD::SIGN_EXTEND_INREG: 5303 ExpandOp(Node->getOperand(0), Lo, Hi); 5304 // sext_inreg the low part if needed. 5305 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5306 5307 // The high part gets the sign extension from the lo-part. This handles 5308 // things like sextinreg V:i64 from i8. 5309 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5310 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 5311 TLI.getShiftAmountTy())); 5312 break; 5313 5314 case ISD::BSWAP: { 5315 ExpandOp(Node->getOperand(0), Lo, Hi); 5316 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5317 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5318 Lo = TempLo; 5319 break; 5320 } 5321 5322 case ISD::CTPOP: 5323 ExpandOp(Node->getOperand(0), Lo, Hi); 5324 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5325 DAG.getNode(ISD::CTPOP, NVT, Lo), 5326 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5327 Hi = DAG.getConstant(0, NVT); 5328 break; 5329 5330 case ISD::CTLZ: { 5331 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5332 ExpandOp(Node->getOperand(0), Lo, Hi); 5333 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5334 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5335 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 5336 ISD::SETNE); 5337 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5338 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5339 5340 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5341 Hi = DAG.getConstant(0, NVT); 5342 break; 5343 } 5344 5345 case ISD::CTTZ: { 5346 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5347 ExpandOp(Node->getOperand(0), Lo, Hi); 5348 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5349 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5350 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 5351 ISD::SETNE); 5352 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5353 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5354 5355 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5356 Hi = DAG.getConstant(0, NVT); 5357 break; 5358 } 5359 5360 case ISD::VAARG: { 5361 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5362 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5363 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5364 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5365 5366 // Remember that we legalized the chain. 5367 Hi = LegalizeOp(Hi); 5368 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5369 if (!TLI.isLittleEndian()) 5370 std::swap(Lo, Hi); 5371 break; 5372 } 5373 5374 case ISD::LOAD: { 5375 LoadSDNode *LD = cast<LoadSDNode>(Node); 5376 SDOperand Ch = LD->getChain(); // Legalize the chain. 5377 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5378 ISD::LoadExtType ExtType = LD->getExtensionType(); 5379 int SVOffset = LD->getSrcValueOffset(); 5380 unsigned Alignment = LD->getAlignment(); 5381 bool isVolatile = LD->isVolatile(); 5382 5383 if (ExtType == ISD::NON_EXTLOAD) { 5384 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5385 isVolatile, Alignment); 5386 if (VT == MVT::f32 || VT == MVT::f64) { 5387 // f32->i32 or f64->i64 one to one expansion. 5388 // Remember that we legalized the chain. 5389 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5390 // Recursively expand the new load. 5391 if (getTypeAction(NVT) == Expand) 5392 ExpandOp(Lo, Lo, Hi); 5393 break; 5394 } 5395 5396 // Increment the pointer to the other half. 5397 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 5398 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5399 getIntPtrConstant(IncrementSize)); 5400 SVOffset += IncrementSize; 5401 if (Alignment > IncrementSize) 5402 Alignment = IncrementSize; 5403 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5404 isVolatile, Alignment); 5405 5406 // Build a factor node to remember that this load is independent of the 5407 // other one. 5408 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5409 Hi.getValue(1)); 5410 5411 // Remember that we legalized the chain. 5412 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5413 if (!TLI.isLittleEndian()) 5414 std::swap(Lo, Hi); 5415 } else { 5416 MVT::ValueType EVT = LD->getLoadedVT(); 5417 5418 if (VT == MVT::f64 && EVT == MVT::f32) { 5419 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5420 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5421 SVOffset, isVolatile, Alignment); 5422 // Remember that we legalized the chain. 5423 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 5424 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 5425 break; 5426 } 5427 5428 if (EVT == NVT) 5429 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 5430 SVOffset, isVolatile, Alignment); 5431 else 5432 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 5433 SVOffset, EVT, isVolatile, 5434 Alignment); 5435 5436 // Remember that we legalized the chain. 5437 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5438 5439 if (ExtType == ISD::SEXTLOAD) { 5440 // The high part is obtained by SRA'ing all but one of the bits of the 5441 // lo part. 5442 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5443 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5444 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5445 } else if (ExtType == ISD::ZEXTLOAD) { 5446 // The high part is just a zero. 5447 Hi = DAG.getConstant(0, NVT); 5448 } else /* if (ExtType == ISD::EXTLOAD) */ { 5449 // The high part is undefined. 5450 Hi = DAG.getNode(ISD::UNDEF, NVT); 5451 } 5452 } 5453 break; 5454 } 5455 case ISD::AND: 5456 case ISD::OR: 5457 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 5458 SDOperand LL, LH, RL, RH; 5459 ExpandOp(Node->getOperand(0), LL, LH); 5460 ExpandOp(Node->getOperand(1), RL, RH); 5461 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 5462 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 5463 break; 5464 } 5465 case ISD::SELECT: { 5466 SDOperand LL, LH, RL, RH; 5467 ExpandOp(Node->getOperand(1), LL, LH); 5468 ExpandOp(Node->getOperand(2), RL, RH); 5469 if (getTypeAction(NVT) == Expand) 5470 NVT = TLI.getTypeToExpandTo(NVT); 5471 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 5472 if (VT != MVT::f32) 5473 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 5474 break; 5475 } 5476 case ISD::SELECT_CC: { 5477 SDOperand TL, TH, FL, FH; 5478 ExpandOp(Node->getOperand(2), TL, TH); 5479 ExpandOp(Node->getOperand(3), FL, FH); 5480 if (getTypeAction(NVT) == Expand) 5481 NVT = TLI.getTypeToExpandTo(NVT); 5482 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5483 Node->getOperand(1), TL, FL, Node->getOperand(4)); 5484 if (VT != MVT::f32) 5485 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5486 Node->getOperand(1), TH, FH, Node->getOperand(4)); 5487 break; 5488 } 5489 case ISD::ANY_EXTEND: 5490 // The low part is any extension of the input (which degenerates to a copy). 5491 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 5492 // The high part is undefined. 5493 Hi = DAG.getNode(ISD::UNDEF, NVT); 5494 break; 5495 case ISD::SIGN_EXTEND: { 5496 // The low part is just a sign extension of the input (which degenerates to 5497 // a copy). 5498 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 5499 5500 // The high part is obtained by SRA'ing all but one of the bits of the lo 5501 // part. 5502 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5503 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5504 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5505 break; 5506 } 5507 case ISD::ZERO_EXTEND: 5508 // The low part is just a zero extension of the input (which degenerates to 5509 // a copy). 5510 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 5511 5512 // The high part is just a zero. 5513 Hi = DAG.getConstant(0, NVT); 5514 break; 5515 5516 case ISD::TRUNCATE: { 5517 // The input value must be larger than this value. Expand *it*. 5518 SDOperand NewLo; 5519 ExpandOp(Node->getOperand(0), NewLo, Hi); 5520 5521 // The low part is now either the right size, or it is closer. If not the 5522 // right size, make an illegal truncate so we recursively expand it. 5523 if (NewLo.getValueType() != Node->getValueType(0)) 5524 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 5525 ExpandOp(NewLo, Lo, Hi); 5526 break; 5527 } 5528 5529 case ISD::BIT_CONVERT: { 5530 SDOperand Tmp; 5531 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 5532 // If the target wants to, allow it to lower this itself. 5533 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5534 case Expand: assert(0 && "cannot expand FP!"); 5535 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 5536 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 5537 } 5538 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 5539 } 5540 5541 // f32 / f64 must be expanded to i32 / i64. 5542 if (VT == MVT::f32 || VT == MVT::f64) { 5543 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5544 if (getTypeAction(NVT) == Expand) 5545 ExpandOp(Lo, Lo, Hi); 5546 break; 5547 } 5548 5549 // If source operand will be expanded to the same type as VT, i.e. 5550 // i64 <- f64, i32 <- f32, expand the source operand instead. 5551 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 5552 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 5553 ExpandOp(Node->getOperand(0), Lo, Hi); 5554 break; 5555 } 5556 5557 // Turn this into a load/store pair by default. 5558 if (Tmp.Val == 0) 5559 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0)); 5560 5561 ExpandOp(Tmp, Lo, Hi); 5562 break; 5563 } 5564 5565 case ISD::READCYCLECOUNTER: 5566 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 5567 TargetLowering::Custom && 5568 "Must custom expand ReadCycleCounter"); 5569 Lo = TLI.LowerOperation(Op, DAG); 5570 assert(Lo.Val && "Node must be custom expanded!"); 5571 Hi = Lo.getValue(1); 5572 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 5573 LegalizeOp(Lo.getValue(2))); 5574 break; 5575 5576 // These operators cannot be expanded directly, emit them as calls to 5577 // library functions. 5578 case ISD::FP_TO_SINT: { 5579 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 5580 SDOperand Op; 5581 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5582 case Expand: assert(0 && "cannot expand FP!"); 5583 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5584 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5585 } 5586 5587 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 5588 5589 // Now that the custom expander is done, expand the result, which is still 5590 // VT. 5591 if (Op.Val) { 5592 ExpandOp(Op, Lo, Hi); 5593 break; 5594 } 5595 } 5596 5597 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5598 if (Node->getOperand(0).getValueType() == MVT::f32) 5599 LC = RTLIB::FPTOSINT_F32_I64; 5600 else if (Node->getOperand(0).getValueType() == MVT::f64) 5601 LC = RTLIB::FPTOSINT_F64_I64; 5602 else if (Node->getOperand(0).getValueType() == MVT::f80) 5603 LC = RTLIB::FPTOSINT_F80_I64; 5604 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 5605 LC = RTLIB::FPTOSINT_PPCF128_I64; 5606 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5607 false/*sign irrelevant*/, Hi); 5608 break; 5609 } 5610 5611 case ISD::FP_TO_UINT: { 5612 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 5613 SDOperand Op; 5614 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5615 case Expand: assert(0 && "cannot expand FP!"); 5616 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5617 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5618 } 5619 5620 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 5621 5622 // Now that the custom expander is done, expand the result. 5623 if (Op.Val) { 5624 ExpandOp(Op, Lo, Hi); 5625 break; 5626 } 5627 } 5628 5629 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5630 if (Node->getOperand(0).getValueType() == MVT::f32) 5631 LC = RTLIB::FPTOUINT_F32_I64; 5632 else if (Node->getOperand(0).getValueType() == MVT::f64) 5633 LC = RTLIB::FPTOUINT_F64_I64; 5634 else if (Node->getOperand(0).getValueType() == MVT::f80) 5635 LC = RTLIB::FPTOUINT_F80_I64; 5636 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 5637 LC = RTLIB::FPTOUINT_PPCF128_I64; 5638 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5639 false/*sign irrelevant*/, Hi); 5640 break; 5641 } 5642 5643 case ISD::SHL: { 5644 // If the target wants custom lowering, do so. 5645 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5646 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 5647 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 5648 Op = TLI.LowerOperation(Op, DAG); 5649 if (Op.Val) { 5650 // Now that the custom expander is done, expand the result, which is 5651 // still VT. 5652 ExpandOp(Op, Lo, Hi); 5653 break; 5654 } 5655 } 5656 5657 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 5658 // this X << 1 as X+X. 5659 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 5660 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 5661 TLI.isOperationLegal(ISD::ADDE, NVT)) { 5662 SDOperand LoOps[2], HiOps[3]; 5663 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 5664 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 5665 LoOps[1] = LoOps[0]; 5666 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5667 5668 HiOps[1] = HiOps[0]; 5669 HiOps[2] = Lo.getValue(1); 5670 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5671 break; 5672 } 5673 } 5674 5675 // If we can emit an efficient shift operation, do so now. 5676 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5677 break; 5678 5679 // If this target supports SHL_PARTS, use it. 5680 TargetLowering::LegalizeAction Action = 5681 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 5682 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5683 Action == TargetLowering::Custom) { 5684 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5685 break; 5686 } 5687 5688 // Otherwise, emit a libcall. 5689 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 5690 false/*left shift=unsigned*/, Hi); 5691 break; 5692 } 5693 5694 case ISD::SRA: { 5695 // If the target wants custom lowering, do so. 5696 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5697 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 5698 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 5699 Op = TLI.LowerOperation(Op, DAG); 5700 if (Op.Val) { 5701 // Now that the custom expander is done, expand the result, which is 5702 // still VT. 5703 ExpandOp(Op, Lo, Hi); 5704 break; 5705 } 5706 } 5707 5708 // If we can emit an efficient shift operation, do so now. 5709 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5710 break; 5711 5712 // If this target supports SRA_PARTS, use it. 5713 TargetLowering::LegalizeAction Action = 5714 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 5715 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5716 Action == TargetLowering::Custom) { 5717 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5718 break; 5719 } 5720 5721 // Otherwise, emit a libcall. 5722 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 5723 true/*ashr is signed*/, Hi); 5724 break; 5725 } 5726 5727 case ISD::SRL: { 5728 // If the target wants custom lowering, do so. 5729 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5730 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 5731 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 5732 Op = TLI.LowerOperation(Op, DAG); 5733 if (Op.Val) { 5734 // Now that the custom expander is done, expand the result, which is 5735 // still VT. 5736 ExpandOp(Op, Lo, Hi); 5737 break; 5738 } 5739 } 5740 5741 // If we can emit an efficient shift operation, do so now. 5742 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5743 break; 5744 5745 // If this target supports SRL_PARTS, use it. 5746 TargetLowering::LegalizeAction Action = 5747 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 5748 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5749 Action == TargetLowering::Custom) { 5750 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5751 break; 5752 } 5753 5754 // Otherwise, emit a libcall. 5755 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 5756 false/*lshr is unsigned*/, Hi); 5757 break; 5758 } 5759 5760 case ISD::ADD: 5761 case ISD::SUB: { 5762 // If the target wants to custom expand this, let them. 5763 if (TLI.getOperationAction(Node->getOpcode(), VT) == 5764 TargetLowering::Custom) { 5765 Op = TLI.LowerOperation(Op, DAG); 5766 if (Op.Val) { 5767 ExpandOp(Op, Lo, Hi); 5768 break; 5769 } 5770 } 5771 5772 // Expand the subcomponents. 5773 SDOperand LHSL, LHSH, RHSL, RHSH; 5774 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5775 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5776 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5777 SDOperand LoOps[2], HiOps[3]; 5778 LoOps[0] = LHSL; 5779 LoOps[1] = RHSL; 5780 HiOps[0] = LHSH; 5781 HiOps[1] = RHSH; 5782 if (Node->getOpcode() == ISD::ADD) { 5783 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5784 HiOps[2] = Lo.getValue(1); 5785 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5786 } else { 5787 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5788 HiOps[2] = Lo.getValue(1); 5789 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5790 } 5791 break; 5792 } 5793 5794 case ISD::ADDC: 5795 case ISD::SUBC: { 5796 // Expand the subcomponents. 5797 SDOperand LHSL, LHSH, RHSL, RHSH; 5798 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5799 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5800 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5801 SDOperand LoOps[2] = { LHSL, RHSL }; 5802 SDOperand HiOps[3] = { LHSH, RHSH }; 5803 5804 if (Node->getOpcode() == ISD::ADDC) { 5805 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5806 HiOps[2] = Lo.getValue(1); 5807 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5808 } else { 5809 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5810 HiOps[2] = Lo.getValue(1); 5811 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5812 } 5813 // Remember that we legalized the flag. 5814 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5815 break; 5816 } 5817 case ISD::ADDE: 5818 case ISD::SUBE: { 5819 // Expand the subcomponents. 5820 SDOperand LHSL, LHSH, RHSL, RHSH; 5821 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5822 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5823 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5824 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 5825 SDOperand HiOps[3] = { LHSH, RHSH }; 5826 5827 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 5828 HiOps[2] = Lo.getValue(1); 5829 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 5830 5831 // Remember that we legalized the flag. 5832 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 5833 break; 5834 } 5835 case ISD::MUL: { 5836 // If the target wants to custom expand this, let them. 5837 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 5838 SDOperand New = TLI.LowerOperation(Op, DAG); 5839 if (New.Val) { 5840 ExpandOp(New, Lo, Hi); 5841 break; 5842 } 5843 } 5844 5845 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 5846 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 5847 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 5848 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 5849 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 5850 SDOperand LL, LH, RL, RH; 5851 ExpandOp(Node->getOperand(0), LL, LH); 5852 ExpandOp(Node->getOperand(1), RL, RH); 5853 unsigned BitSize = MVT::getSizeInBits(RH.getValueType()); 5854 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 5855 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 5856 // FIXME: generalize this to handle other bit sizes 5857 if (LHSSB == 32 && RHSSB == 32 && 5858 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) && 5859 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) { 5860 // The inputs are both zero-extended. 5861 if (HasUMUL_LOHI) { 5862 // We can emit a umul_lohi. 5863 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 5864 Hi = SDOperand(Lo.Val, 1); 5865 break; 5866 } 5867 if (HasMULHU) { 5868 // We can emit a mulhu+mul. 5869 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5870 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 5871 break; 5872 } 5873 break; 5874 } 5875 if (LHSSB > BitSize && RHSSB > BitSize) { 5876 // The input values are both sign-extended. 5877 if (HasSMUL_LOHI) { 5878 // We can emit a smul_lohi. 5879 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 5880 Hi = SDOperand(Lo.Val, 1); 5881 break; 5882 } 5883 if (HasMULHS) { 5884 // We can emit a mulhs+mul. 5885 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 5886 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 5887 break; 5888 } 5889 } 5890 if (HasUMUL_LOHI) { 5891 // Lo,Hi = umul LHS, RHS. 5892 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 5893 DAG.getVTList(NVT, NVT), LL, RL); 5894 Lo = UMulLOHI; 5895 Hi = UMulLOHI.getValue(1); 5896 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 5897 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 5898 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 5899 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 5900 break; 5901 } 5902 } 5903 5904 // If nothing else, we can make a libcall. 5905 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 5906 false/*sign irrelevant*/, Hi); 5907 break; 5908 } 5909 case ISD::SDIV: 5910 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 5911 break; 5912 case ISD::UDIV: 5913 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 5914 break; 5915 case ISD::SREM: 5916 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 5917 break; 5918 case ISD::UREM: 5919 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 5920 break; 5921 5922 case ISD::FADD: 5923 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::ADD_F32 : 5924 VT == MVT::f64 ? RTLIB::ADD_F64 : 5925 VT == MVT::ppcf128 ? 5926 RTLIB::ADD_PPCF128 : 5927 RTLIB::UNKNOWN_LIBCALL), 5928 Node, false, Hi); 5929 break; 5930 case ISD::FSUB: 5931 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::SUB_F32 : 5932 VT == MVT::f64 ? RTLIB::SUB_F64 : 5933 VT == MVT::ppcf128 ? 5934 RTLIB::SUB_PPCF128 : 5935 RTLIB::UNKNOWN_LIBCALL), 5936 Node, false, Hi); 5937 break; 5938 case ISD::FMUL: 5939 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::MUL_F32 : 5940 VT == MVT::f64 ? RTLIB::MUL_F64 : 5941 VT == MVT::ppcf128 ? 5942 RTLIB::MUL_PPCF128 : 5943 RTLIB::UNKNOWN_LIBCALL), 5944 Node, false, Hi); 5945 break; 5946 case ISD::FDIV: 5947 Lo = ExpandLibCall(TLI.getLibcallName(VT == MVT::f32 ? RTLIB::DIV_F32 : 5948 VT == MVT::f64 ? RTLIB::DIV_F64 : 5949 VT == MVT::ppcf128 ? 5950 RTLIB::DIV_PPCF128 : 5951 RTLIB::UNKNOWN_LIBCALL), 5952 Node, false, Hi); 5953 break; 5954 case ISD::FP_EXTEND: 5955 if (VT == MVT::ppcf128) { 5956 assert(Node->getOperand(0).getValueType()==MVT::f32 || 5957 Node->getOperand(0).getValueType()==MVT::f64); 5958 const uint64_t zero = 0; 5959 if (Node->getOperand(0).getValueType()==MVT::f32) 5960 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 5961 else 5962 Hi = Node->getOperand(0); 5963 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 5964 break; 5965 } 5966 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 5967 break; 5968 case ISD::FP_ROUND: 5969 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 5970 break; 5971 case ISD::FPOWI: 5972 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32) ? RTLIB::POWI_F32 : 5973 (VT == MVT::f64) ? RTLIB::POWI_F64 : 5974 (VT == MVT::f80) ? RTLIB::POWI_F80 : 5975 (VT == MVT::ppcf128) ? 5976 RTLIB::POWI_PPCF128 : 5977 RTLIB::UNKNOWN_LIBCALL), 5978 Node, false, Hi); 5979 break; 5980 case ISD::FSQRT: 5981 case ISD::FSIN: 5982 case ISD::FCOS: { 5983 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5984 switch(Node->getOpcode()) { 5985 case ISD::FSQRT: 5986 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : 5987 (VT == MVT::f64) ? RTLIB::SQRT_F64 : 5988 (VT == MVT::f80) ? RTLIB::SQRT_F80 : 5989 (VT == MVT::ppcf128) ? RTLIB::SQRT_PPCF128 : 5990 RTLIB::UNKNOWN_LIBCALL; 5991 break; 5992 case ISD::FSIN: 5993 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64; 5994 break; 5995 case ISD::FCOS: 5996 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64; 5997 break; 5998 default: assert(0 && "Unreachable!"); 5999 } 6000 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 6001 break; 6002 } 6003 case ISD::FABS: { 6004 SDOperand Mask = (VT == MVT::f64) 6005 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6006 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6007 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6008 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6009 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6010 if (getTypeAction(NVT) == Expand) 6011 ExpandOp(Lo, Lo, Hi); 6012 break; 6013 } 6014 case ISD::FNEG: { 6015 SDOperand Mask = (VT == MVT::f64) 6016 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6017 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6018 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6019 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6020 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6021 if (getTypeAction(NVT) == Expand) 6022 ExpandOp(Lo, Lo, Hi); 6023 break; 6024 } 6025 case ISD::FCOPYSIGN: { 6026 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6027 if (getTypeAction(NVT) == Expand) 6028 ExpandOp(Lo, Lo, Hi); 6029 break; 6030 } 6031 case ISD::SINT_TO_FP: 6032 case ISD::UINT_TO_FP: { 6033 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6034 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 6035 if (VT == MVT::ppcf128) { 6036 static uint64_t zero = 0; 6037 if (isSigned) { 6038 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6039 Node->getOperand(0))); 6040 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6041 } else { 6042 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6043 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6044 Node->getOperand(0))); 6045 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6046 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6047 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6048 DAG.getConstant(0, MVT::i32), 6049 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6050 DAG.getConstantFP( 6051 APFloat(APInt(128, 2, TwoE32)), 6052 MVT::ppcf128)), 6053 Hi, 6054 DAG.getCondCode(ISD::SETLT)), 6055 Lo, Hi); 6056 } 6057 break; 6058 } 6059 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6060 if (Node->getOperand(0).getValueType() == MVT::i64) { 6061 if (VT == MVT::f32) 6062 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 6063 else if (VT == MVT::f64) 6064 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 6065 else if (VT == MVT::f80) { 6066 assert(isSigned); 6067 LC = RTLIB::SINTTOFP_I64_F80; 6068 } 6069 else if (VT == MVT::ppcf128) { 6070 assert(isSigned); 6071 LC = RTLIB::SINTTOFP_I64_PPCF128; 6072 } 6073 } else { 6074 if (VT == MVT::f32) 6075 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 6076 else 6077 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 6078 } 6079 6080 // Promote the operand if needed. 6081 if (getTypeAction(SrcVT) == Promote) { 6082 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6083 Tmp = isSigned 6084 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6085 DAG.getValueType(SrcVT)) 6086 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6087 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6088 } 6089 6090 const char *LibCall = TLI.getLibcallName(LC); 6091 if (LibCall) 6092 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 6093 else { 6094 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6095 Node->getOperand(0)); 6096 if (getTypeAction(Lo.getValueType()) == Expand) 6097 ExpandOp(Lo, Lo, Hi); 6098 } 6099 break; 6100 } 6101 } 6102 6103 // Make sure the resultant values have been legalized themselves, unless this 6104 // is a type that requires multi-step expansion. 6105 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6106 Lo = LegalizeOp(Lo); 6107 if (Hi.Val) 6108 // Don't legalize the high part if it is expanded to a single node. 6109 Hi = LegalizeOp(Hi); 6110 } 6111 6112 // Remember in a map if the values will be reused later. 6113 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6114 assert(isNew && "Value already expanded?!?"); 6115} 6116 6117/// SplitVectorOp - Given an operand of vector type, break it down into 6118/// two smaller values, still of vector type. 6119void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6120 SDOperand &Hi) { 6121 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); 6122 SDNode *Node = Op.Val; 6123 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType()); 6124 assert(NumElements > 1 && "Cannot split a single element vector!"); 6125 unsigned NewNumElts = NumElements/2; 6126 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType()); 6127 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts); 6128 6129 // See if we already split it. 6130 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6131 = SplitNodes.find(Op); 6132 if (I != SplitNodes.end()) { 6133 Lo = I->second.first; 6134 Hi = I->second.second; 6135 return; 6136 } 6137 6138 switch (Node->getOpcode()) { 6139 default: 6140#ifndef NDEBUG 6141 Node->dump(&DAG); 6142#endif 6143 assert(0 && "Unhandled operation in SplitVectorOp!"); 6144 case ISD::BUILD_PAIR: 6145 Lo = Node->getOperand(0); 6146 Hi = Node->getOperand(1); 6147 break; 6148 case ISD::INSERT_VECTOR_ELT: { 6149 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6150 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 6151 SDOperand ScalarOp = Node->getOperand(1); 6152 if (Index < NewNumElts) 6153 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, Lo, ScalarOp, 6154 DAG.getConstant(Index, TLI.getPointerTy())); 6155 else 6156 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, Hi, ScalarOp, 6157 DAG.getConstant(Index - NewNumElts, TLI.getPointerTy())); 6158 break; 6159 } 6160 case ISD::BUILD_VECTOR: { 6161 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6162 Node->op_begin()+NewNumElts); 6163 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size()); 6164 6165 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts, 6166 Node->op_end()); 6167 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size()); 6168 break; 6169 } 6170 case ISD::CONCAT_VECTORS: { 6171 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6172 if (NewNumSubvectors == 1) { 6173 Lo = Node->getOperand(0); 6174 Hi = Node->getOperand(1); 6175 } else { 6176 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6177 Node->op_begin()+NewNumSubvectors); 6178 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size()); 6179 6180 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6181 Node->op_end()); 6182 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size()); 6183 } 6184 break; 6185 } 6186 case ISD::ADD: 6187 case ISD::SUB: 6188 case ISD::MUL: 6189 case ISD::FADD: 6190 case ISD::FSUB: 6191 case ISD::FMUL: 6192 case ISD::SDIV: 6193 case ISD::UDIV: 6194 case ISD::FDIV: 6195 case ISD::FPOW: 6196 case ISD::AND: 6197 case ISD::OR: 6198 case ISD::XOR: { 6199 SDOperand LL, LH, RL, RH; 6200 SplitVectorOp(Node->getOperand(0), LL, LH); 6201 SplitVectorOp(Node->getOperand(1), RL, RH); 6202 6203 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL); 6204 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH); 6205 break; 6206 } 6207 case ISD::FPOWI: { 6208 SDOperand L, H; 6209 SplitVectorOp(Node->getOperand(0), L, H); 6210 6211 Lo = DAG.getNode(Node->getOpcode(), NewVT, L, Node->getOperand(1)); 6212 Hi = DAG.getNode(Node->getOpcode(), NewVT, H, Node->getOperand(1)); 6213 break; 6214 } 6215 case ISD::CTTZ: 6216 case ISD::CTLZ: 6217 case ISD::CTPOP: 6218 case ISD::FNEG: 6219 case ISD::FABS: 6220 case ISD::FSQRT: 6221 case ISD::FSIN: 6222 case ISD::FCOS: { 6223 SDOperand L, H; 6224 SplitVectorOp(Node->getOperand(0), L, H); 6225 6226 Lo = DAG.getNode(Node->getOpcode(), NewVT, L); 6227 Hi = DAG.getNode(Node->getOpcode(), NewVT, H); 6228 break; 6229 } 6230 case ISD::LOAD: { 6231 LoadSDNode *LD = cast<LoadSDNode>(Node); 6232 SDOperand Ch = LD->getChain(); 6233 SDOperand Ptr = LD->getBasePtr(); 6234 const Value *SV = LD->getSrcValue(); 6235 int SVOffset = LD->getSrcValueOffset(); 6236 unsigned Alignment = LD->getAlignment(); 6237 bool isVolatile = LD->isVolatile(); 6238 6239 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6240 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8; 6241 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6242 getIntPtrConstant(IncrementSize)); 6243 SVOffset += IncrementSize; 6244 if (Alignment > IncrementSize) 6245 Alignment = IncrementSize; 6246 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6247 6248 // Build a factor node to remember that this load is independent of the 6249 // other one. 6250 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6251 Hi.getValue(1)); 6252 6253 // Remember that we legalized the chain. 6254 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6255 break; 6256 } 6257 case ISD::BIT_CONVERT: { 6258 // We know the result is a vector. The input may be either a vector or a 6259 // scalar value. 6260 SDOperand InOp = Node->getOperand(0); 6261 if (!MVT::isVector(InOp.getValueType()) || 6262 MVT::getVectorNumElements(InOp.getValueType()) == 1) { 6263 // The input is a scalar or single-element vector. 6264 // Lower to a store/load so that it can be split. 6265 // FIXME: this could be improved probably. 6266 SDOperand Ptr = CreateStackTemporary(InOp.getValueType()); 6267 6268 SDOperand St = DAG.getStore(DAG.getEntryNode(), 6269 InOp, Ptr, NULL, 0); 6270 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0); 6271 } 6272 // Split the vector and convert each of the pieces now. 6273 SplitVectorOp(InOp, Lo, Hi); 6274 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo); 6275 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi); 6276 break; 6277 } 6278 } 6279 6280 // Remember in a map if the values will be reused later. 6281 bool isNew = 6282 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 6283 assert(isNew && "Value already split?!?"); 6284} 6285 6286 6287/// ScalarizeVectorOp - Given an operand of single-element vector type 6288/// (e.g. v1f32), convert it into the equivalent operation that returns a 6289/// scalar (e.g. f32) value. 6290SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 6291 assert(MVT::isVector(Op.getValueType()) && 6292 "Bad ScalarizeVectorOp invocation!"); 6293 SDNode *Node = Op.Val; 6294 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); 6295 assert(MVT::getVectorNumElements(Op.getValueType()) == 1); 6296 6297 // See if we already scalarized it. 6298 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 6299 if (I != ScalarizedNodes.end()) return I->second; 6300 6301 SDOperand Result; 6302 switch (Node->getOpcode()) { 6303 default: 6304#ifndef NDEBUG 6305 Node->dump(&DAG); cerr << "\n"; 6306#endif 6307 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 6308 case ISD::ADD: 6309 case ISD::FADD: 6310 case ISD::SUB: 6311 case ISD::FSUB: 6312 case ISD::MUL: 6313 case ISD::FMUL: 6314 case ISD::SDIV: 6315 case ISD::UDIV: 6316 case ISD::FDIV: 6317 case ISD::SREM: 6318 case ISD::UREM: 6319 case ISD::FREM: 6320 case ISD::FPOW: 6321 case ISD::AND: 6322 case ISD::OR: 6323 case ISD::XOR: 6324 Result = DAG.getNode(Node->getOpcode(), 6325 NewVT, 6326 ScalarizeVectorOp(Node->getOperand(0)), 6327 ScalarizeVectorOp(Node->getOperand(1))); 6328 break; 6329 case ISD::FNEG: 6330 case ISD::FABS: 6331 case ISD::FSQRT: 6332 case ISD::FSIN: 6333 case ISD::FCOS: 6334 Result = DAG.getNode(Node->getOpcode(), 6335 NewVT, 6336 ScalarizeVectorOp(Node->getOperand(0))); 6337 break; 6338 case ISD::LOAD: { 6339 LoadSDNode *LD = cast<LoadSDNode>(Node); 6340 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 6341 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 6342 6343 const Value *SV = LD->getSrcValue(); 6344 int SVOffset = LD->getSrcValueOffset(); 6345 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 6346 LD->isVolatile(), LD->getAlignment()); 6347 6348 // Remember that we legalized the chain. 6349 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 6350 break; 6351 } 6352 case ISD::BUILD_VECTOR: 6353 Result = Node->getOperand(0); 6354 break; 6355 case ISD::INSERT_VECTOR_ELT: 6356 // Returning the inserted scalar element. 6357 Result = Node->getOperand(1); 6358 break; 6359 case ISD::CONCAT_VECTORS: 6360 assert(Node->getOperand(0).getValueType() == NewVT && 6361 "Concat of non-legal vectors not yet supported!"); 6362 Result = Node->getOperand(0); 6363 break; 6364 case ISD::VECTOR_SHUFFLE: { 6365 // Figure out if the scalar is the LHS or RHS and return it. 6366 SDOperand EltNum = Node->getOperand(2).getOperand(0); 6367 if (cast<ConstantSDNode>(EltNum)->getValue()) 6368 Result = ScalarizeVectorOp(Node->getOperand(1)); 6369 else 6370 Result = ScalarizeVectorOp(Node->getOperand(0)); 6371 break; 6372 } 6373 case ISD::EXTRACT_SUBVECTOR: 6374 Result = Node->getOperand(0); 6375 assert(Result.getValueType() == NewVT); 6376 break; 6377 case ISD::BIT_CONVERT: 6378 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 6379 break; 6380 case ISD::SELECT: 6381 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 6382 ScalarizeVectorOp(Op.getOperand(1)), 6383 ScalarizeVectorOp(Op.getOperand(2))); 6384 break; 6385 } 6386 6387 if (TLI.isTypeLegal(NewVT)) 6388 Result = LegalizeOp(Result); 6389 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 6390 assert(isNew && "Value already scalarized?"); 6391 return Result; 6392} 6393 6394 6395// SelectionDAG::Legalize - This is the entry point for the file. 6396// 6397void SelectionDAG::Legalize() { 6398 if (ViewLegalizeDAGs) viewGraph(); 6399 6400 /// run - This is the main entry point to this class. 6401 /// 6402 SelectionDAGLegalize(*this).LegalizeDAG(); 6403} 6404 6405