LegalizeDAG.cpp revision cad542c6e68d975a35847b2a85f233ad34a004f5
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/DwarfWriter.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/CodeGen/PseudoSourceValue.h" 22#include "llvm/Target/TargetFrameInfo.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetData.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Target/TargetSubtarget.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/DerivedTypes.h" 31#include "llvm/Function.h" 32#include "llvm/GlobalVariable.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Compiler.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/ADT/DenseMap.h" 37#include "llvm/ADT/SmallVector.h" 38#include "llvm/ADT/SmallPtrSet.h" 39#include <map> 40using namespace llvm; 41 42//===----------------------------------------------------------------------===// 43/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 44/// hacks on it until the target machine can handle it. This involves 45/// eliminating value sizes the machine cannot handle (promoting small sizes to 46/// large sizes or splitting up large values into small values) as well as 47/// eliminating operations the machine cannot handle. 48/// 49/// This code also does a small amount of optimization and recognition of idioms 50/// as part of its processing. For example, if a target does not support a 51/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 52/// will attempt merge setcc and brc instructions into brcc's. 53/// 54namespace { 55class VISIBILITY_HIDDEN SelectionDAGLegalize { 56 TargetLowering &TLI; 57 SelectionDAG &DAG; 58 CodeGenOpt::Level OptLevel; 59 bool TypesNeedLegalizing; 60 61 // Libcall insertion helpers. 62 63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 64 /// legalized. We use this to ensure that calls are properly serialized 65 /// against each other, including inserted libcalls. 66 SDValue LastCALLSEQ_END; 67 68 /// IsLegalizingCall - This member is used *only* for purposes of providing 69 /// helpful assertions that a libcall isn't created while another call is 70 /// being legalized (which could lead to non-serialized call sequences). 71 bool IsLegalizingCall; 72 73 /// IsLegalizingCallArguments - This member is used only for the purpose 74 /// of providing assert to check for LegalizeTypes because legalizing an 75 /// operation might introduce call nodes that might need type legalization. 76 bool IsLegalizingCallArgs; 77 78 enum LegalizeAction { 79 Legal, // The target natively supports this operation. 80 Promote, // This operation should be executed in a larger type. 81 Expand // Try to expand this to other ops, otherwise use a libcall. 82 }; 83 84 /// ValueTypeActions - This is a bitvector that contains two bits for each 85 /// value type, where the two bits correspond to the LegalizeAction enum. 86 /// This can be queried with "getTypeAction(VT)". 87 TargetLowering::ValueTypeActionImpl ValueTypeActions; 88 89 /// LegalizedNodes - For nodes that are of legal width, and that have more 90 /// than one use, this map indicates what regularized operand to use. This 91 /// allows us to avoid legalizing the same thing more than once. 92 DenseMap<SDValue, SDValue> LegalizedNodes; 93 94 /// PromotedNodes - For nodes that are below legal width, and that have more 95 /// than one use, this map indicates what promoted value to use. This allows 96 /// us to avoid promoting the same thing more than once. 97 DenseMap<SDValue, SDValue> PromotedNodes; 98 99 /// ExpandedNodes - For nodes that need to be expanded this map indicates 100 /// which operands are the expanded version of the input. This allows 101 /// us to avoid expanding the same node more than once. 102 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes; 103 104 /// SplitNodes - For vector nodes that need to be split, this map indicates 105 /// which operands are the split version of the input. This allows us 106 /// to avoid splitting the same node more than once. 107 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes; 108 109 /// ScalarizedNodes - For nodes that need to be converted from vector types to 110 /// scalar types, this contains the mapping of ones we have already 111 /// processed to the result. 112 std::map<SDValue, SDValue> ScalarizedNodes; 113 114 /// WidenNodes - For nodes that need to be widened from one vector type to 115 /// another, this contains the mapping of those that we have already widen. 116 /// This allows us to avoid widening more than once. 117 std::map<SDValue, SDValue> WidenNodes; 118 119 void AddLegalizedOperand(SDValue From, SDValue To) { 120 LegalizedNodes.insert(std::make_pair(From, To)); 121 // If someone requests legalization of the new node, return itself. 122 if (From != To) 123 LegalizedNodes.insert(std::make_pair(To, To)); 124 } 125 void AddPromotedOperand(SDValue From, SDValue To) { 126 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 127 assert(isNew && "Got into the map somehow?"); 128 isNew = isNew; 129 // If someone requests legalization of the new node, return itself. 130 LegalizedNodes.insert(std::make_pair(To, To)); 131 } 132 void AddWidenedOperand(SDValue From, SDValue To) { 133 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second; 134 assert(isNew && "Got into the map somehow?"); 135 isNew = isNew; 136 // If someone requests legalization of the new node, return itself. 137 LegalizedNodes.insert(std::make_pair(To, To)); 138 } 139 140public: 141 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing, 142 CodeGenOpt::Level ol); 143 144 /// getTypeAction - Return how we should legalize values of this type, either 145 /// it is already legal or we need to expand it into multiple registers of 146 /// smaller integer type, or we need to promote it to a larger type. 147 LegalizeAction getTypeAction(MVT VT) const { 148 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 149 } 150 151 /// isTypeLegal - Return true if this type is legal on this target. 152 /// 153 bool isTypeLegal(MVT VT) const { 154 return getTypeAction(VT) == Legal; 155 } 156 157 void LegalizeDAG(); 158 159private: 160 /// HandleOp - Legalize, Promote, or Expand the specified operand as 161 /// appropriate for its type. 162 void HandleOp(SDValue Op); 163 164 /// LegalizeOp - We know that the specified value has a legal type. 165 /// Recursively ensure that the operands have legal types, then return the 166 /// result. 167 SDValue LegalizeOp(SDValue O); 168 169 /// UnrollVectorOp - We know that the given vector has a legal type, however 170 /// the operation it performs is not legal and is an operation that we have 171 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 172 /// operating on each element individually. 173 SDValue UnrollVectorOp(SDValue O); 174 175 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 176 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 177 /// is necessary to spill the vector being inserted into to memory, perform 178 /// the insert there, and then read the result back. 179 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 180 SDValue Idx, DebugLoc dl); 181 182 /// PromoteOp - Given an operation that produces a value in an invalid type, 183 /// promote it to compute the value into a larger type. The produced value 184 /// will have the correct bits for the low portion of the register, but no 185 /// guarantee is made about the top bits: it may be zero, sign-extended, or 186 /// garbage. 187 SDValue PromoteOp(SDValue O); 188 189 /// ExpandOp - Expand the specified SDValue into its two component pieces 190 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 191 /// the LegalizedNodes map is filled in for any results that are not expanded, 192 /// the ExpandedNodes map is filled in for any results that are expanded, and 193 /// the Lo/Hi values are returned. This applies to integer types and Vector 194 /// types. 195 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi); 196 197 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT 198 /// (e.g., v3i32 to v4i32). The produced value will have the correct value 199 /// for the existing elements but no guarantee is made about the new elements 200 /// at the end of the vector: it may be zero, ones, or garbage. This is useful 201 /// when we have an instruction operating on an illegal vector type and we 202 /// want to widen it to do the computation on a legal wider vector type. 203 SDValue WidenVectorOp(SDValue Op, MVT WidenVT); 204 205 /// SplitVectorOp - Given an operand of vector type, break it down into 206 /// two smaller values. 207 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi); 208 209 /// ScalarizeVectorOp - Given an operand of single-element vector type 210 /// (e.g. v1f32), convert it into the equivalent operation that returns a 211 /// scalar (e.g. f32) value. 212 SDValue ScalarizeVectorOp(SDValue O); 213 214 /// Useful 16 element vector type that is used to pass operands for widening. 215 typedef SmallVector<SDValue, 16> SDValueVector; 216 217 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if 218 /// the LdChain contains a single load and false if it contains a token 219 /// factor for multiple loads. It takes 220 /// Result: location to return the result 221 /// LdChain: location to return the load chain 222 /// Op: load operation to widen 223 /// NVT: widen vector result type we want for the load 224 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain, 225 SDValue Op, MVT NVT); 226 227 /// Helper genWidenVectorLoads - Helper function to generate a set of 228 /// loads to load a vector with a resulting wider type. It takes 229 /// LdChain: list of chains for the load we have generated 230 /// Chain: incoming chain for the ld vector 231 /// BasePtr: base pointer to load from 232 /// SV: memory disambiguation source value 233 /// SVOffset: memory disambiugation offset 234 /// Alignment: alignment of the memory 235 /// isVolatile: volatile load 236 /// LdWidth: width of memory that we want to load 237 /// ResType: the wider result result type for the resulting loaded vector 238 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain, 239 SDValue BasePtr, const Value *SV, 240 int SVOffset, unsigned Alignment, 241 bool isVolatile, unsigned LdWidth, 242 MVT ResType, DebugLoc dl); 243 244 /// StoreWidenVectorOp - Stores a widen vector into non widen memory 245 /// location. It takes 246 /// ST: store node that we want to replace 247 /// Chain: incoming store chain 248 /// BasePtr: base address of where we want to store into 249 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain, 250 SDValue BasePtr); 251 252 /// Helper genWidenVectorStores - Helper function to generate a set of 253 /// stores to store a widen vector into non widen memory 254 // It takes 255 // StChain: list of chains for the stores we have generated 256 // Chain: incoming chain for the ld vector 257 // BasePtr: base pointer to load from 258 // SV: memory disambiguation source value 259 // SVOffset: memory disambiugation offset 260 // Alignment: alignment of the memory 261 // isVolatile: volatile lod 262 // ValOp: value to store 263 // StWidth: width of memory that we want to store 264 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain, 265 SDValue BasePtr, const Value *SV, 266 int SVOffset, unsigned Alignment, 267 bool isVolatile, SDValue ValOp, 268 unsigned StWidth, DebugLoc dl); 269 270 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 271 /// performs the same shuffe in terms of order or result bytes, but on a type 272 /// whose vector element type is narrower than the original shuffle type. 273 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 274 SDValue ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl, 275 SDValue N1, SDValue N2, 276 SmallVectorImpl<int> &Mask) const; 277 278 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 279 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 280 281 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC, 282 DebugLoc dl); 283 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 284 DebugLoc dl); 285 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 286 DebugLoc dl) { 287 LegalizeSetCCOperands(LHS, RHS, CC, dl); 288 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl); 289 } 290 291 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 292 SDValue &Hi); 293 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl); 294 295 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl); 296 SDValue ExpandBUILD_VECTOR(SDNode *Node); 297 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 298 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, 299 SDValue Op, DebugLoc dl); 300 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT, 301 DebugLoc dl); 302 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned, 303 DebugLoc dl); 304 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned, 305 DebugLoc dl); 306 307 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 308 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 309 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt, 310 SDValue &Lo, SDValue &Hi, DebugLoc dl); 311 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt, 312 SDValue &Lo, SDValue &Hi, DebugLoc dl); 313 314 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op); 315 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op); 316}; 317} 318 319/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 320/// performs the same shuffe in terms of order or result bytes, but on a type 321/// whose vector element type is narrower than the original shuffle type. 322/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 323SDValue 324SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl, 325 SDValue N1, SDValue N2, 326 SmallVectorImpl<int> &Mask) const { 327 MVT EltVT = NVT.getVectorElementType(); 328 unsigned NumMaskElts = VT.getVectorNumElements(); 329 unsigned NumDestElts = NVT.getVectorNumElements(); 330 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 331 332 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 333 334 if (NumEltsGrowth == 1) 335 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 336 337 SmallVector<int, 8> NewMask; 338 for (unsigned i = 0; i != NumMaskElts; ++i) { 339 int Idx = Mask[i]; 340 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 341 if (Idx < 0) 342 NewMask.push_back(-1); 343 else 344 NewMask.push_back(Idx * NumEltsGrowth + j); 345 } 346 } 347 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 348 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 349 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 350} 351 352SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 353 bool types, CodeGenOpt::Level ol) 354 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), 355 TypesNeedLegalizing(types), ValueTypeActions(TLI.getValueTypeActions()) { 356 assert(MVT::LAST_VALUETYPE <= 32 && 357 "Too many value types for ValueTypeActions to hold!"); 358} 359 360void SelectionDAGLegalize::LegalizeDAG() { 361 LastCALLSEQ_END = DAG.getEntryNode(); 362 IsLegalizingCall = false; 363 IsLegalizingCallArgs = false; 364 365 // The legalize process is inherently a bottom-up recursive process (users 366 // legalize their uses before themselves). Given infinite stack space, we 367 // could just start legalizing on the root and traverse the whole graph. In 368 // practice however, this causes us to run out of stack space on large basic 369 // blocks. To avoid this problem, compute an ordering of the nodes where each 370 // node is only legalized after all of its operands are legalized. 371 DAG.AssignTopologicalOrder(); 372 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 373 E = prior(DAG.allnodes_end()); I != next(E); ++I) 374 HandleOp(SDValue(I, 0)); 375 376 // Finally, it's possible the root changed. Get the new root. 377 SDValue OldRoot = DAG.getRoot(); 378 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 379 DAG.setRoot(LegalizedNodes[OldRoot]); 380 381 ExpandedNodes.clear(); 382 LegalizedNodes.clear(); 383 PromotedNodes.clear(); 384 SplitNodes.clear(); 385 ScalarizedNodes.clear(); 386 WidenNodes.clear(); 387 388 // Remove dead nodes now. 389 DAG.RemoveDeadNodes(); 390} 391 392 393/// FindCallEndFromCallStart - Given a chained node that is part of a call 394/// sequence, find the CALLSEQ_END node that terminates the call sequence. 395static SDNode *FindCallEndFromCallStart(SDNode *Node) { 396 if (Node->getOpcode() == ISD::CALLSEQ_END) 397 return Node; 398 if (Node->use_empty()) 399 return 0; // No CallSeqEnd 400 401 // The chain is usually at the end. 402 SDValue TheChain(Node, Node->getNumValues()-1); 403 if (TheChain.getValueType() != MVT::Other) { 404 // Sometimes it's at the beginning. 405 TheChain = SDValue(Node, 0); 406 if (TheChain.getValueType() != MVT::Other) { 407 // Otherwise, hunt for it. 408 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 409 if (Node->getValueType(i) == MVT::Other) { 410 TheChain = SDValue(Node, i); 411 break; 412 } 413 414 // Otherwise, we walked into a node without a chain. 415 if (TheChain.getValueType() != MVT::Other) 416 return 0; 417 } 418 } 419 420 for (SDNode::use_iterator UI = Node->use_begin(), 421 E = Node->use_end(); UI != E; ++UI) { 422 423 // Make sure to only follow users of our token chain. 424 SDNode *User = *UI; 425 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 426 if (User->getOperand(i) == TheChain) 427 if (SDNode *Result = FindCallEndFromCallStart(User)) 428 return Result; 429 } 430 return 0; 431} 432 433/// FindCallStartFromCallEnd - Given a chained node that is part of a call 434/// sequence, find the CALLSEQ_START node that initiates the call sequence. 435static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 436 assert(Node && "Didn't find callseq_start for a call??"); 437 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 438 439 assert(Node->getOperand(0).getValueType() == MVT::Other && 440 "Node doesn't have a token chain argument!"); 441 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 442} 443 444/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 445/// see if any uses can reach Dest. If no dest operands can get to dest, 446/// legalize them, legalize ourself, and return false, otherwise, return true. 447/// 448/// Keep track of the nodes we fine that actually do lead to Dest in 449/// NodesLeadingTo. This avoids retraversing them exponential number of times. 450/// 451bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 452 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 453 if (N == Dest) return true; // N certainly leads to Dest :) 454 455 // If we've already processed this node and it does lead to Dest, there is no 456 // need to reprocess it. 457 if (NodesLeadingTo.count(N)) return true; 458 459 // If the first result of this node has been already legalized, then it cannot 460 // reach N. 461 switch (getTypeAction(N->getValueType(0))) { 462 case Legal: 463 if (LegalizedNodes.count(SDValue(N, 0))) return false; 464 break; 465 case Promote: 466 if (PromotedNodes.count(SDValue(N, 0))) return false; 467 break; 468 case Expand: 469 if (ExpandedNodes.count(SDValue(N, 0))) return false; 470 break; 471 } 472 473 // Okay, this node has not already been legalized. Check and legalize all 474 // operands. If none lead to Dest, then we can legalize this node. 475 bool OperandsLeadToDest = false; 476 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 477 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 478 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 479 480 if (OperandsLeadToDest) { 481 NodesLeadingTo.insert(N); 482 return true; 483 } 484 485 // Okay, this node looks safe, legalize it and return false. 486 HandleOp(SDValue(N, 0)); 487 return false; 488} 489 490/// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as 491/// appropriate for its type. 492void SelectionDAGLegalize::HandleOp(SDValue Op) { 493 MVT VT = Op.getValueType(); 494 // If the type legalizer was run then we should never see any illegal result 495 // types here except for target constants (the type legalizer does not touch 496 // those) or for build vector used as a mask for a vector shuffle. 497 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal || 498 IsLegalizingCallArgs || Op.getOpcode() == ISD::TargetConstant) && 499 "Illegal type introduced after type legalization?"); 500 switch (getTypeAction(VT)) { 501 default: assert(0 && "Bad type action!"); 502 case Legal: (void)LegalizeOp(Op); break; 503 case Promote: 504 if (!VT.isVector()) { 505 (void)PromoteOp(Op); 506 break; 507 } 508 else { 509 // See if we can widen otherwise use Expand to either scalarize or split 510 MVT WidenVT = TLI.getWidenVectorType(VT); 511 if (WidenVT != MVT::Other) { 512 (void) WidenVectorOp(Op, WidenVT); 513 break; 514 } 515 // else fall thru to expand since we can't widen the vector 516 } 517 case Expand: 518 if (!VT.isVector()) { 519 // If this is an illegal scalar, expand it into its two component 520 // pieces. 521 SDValue X, Y; 522 if (Op.getOpcode() == ISD::TargetConstant) 523 break; // Allow illegal target nodes. 524 ExpandOp(Op, X, Y); 525 } else if (VT.getVectorNumElements() == 1) { 526 // If this is an illegal single element vector, convert it to a 527 // scalar operation. 528 (void)ScalarizeVectorOp(Op); 529 } else { 530 // This is an illegal multiple element vector. 531 // Split it in half and legalize both parts. 532 SDValue X, Y; 533 SplitVectorOp(Op, X, Y); 534 } 535 break; 536 } 537} 538 539/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 540/// a load from the constant pool. 541static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 542 SelectionDAG &DAG, const TargetLowering &TLI) { 543 bool Extend = false; 544 DebugLoc dl = CFP->getDebugLoc(); 545 546 // If a FP immediate is precise when represented as a float and if the 547 // target can do an extending load from float to double, we put it into 548 // the constant pool as a float, even if it's is statically typed as a 549 // double. This shrinks FP constants and canonicalizes them for targets where 550 // an FP extending load is the same cost as a normal load (such as on the x87 551 // fp stack or PPC FP unit). 552 MVT VT = CFP->getValueType(0); 553 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 554 if (!UseCP) { 555 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 556 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 557 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 558 } 559 560 MVT OrigVT = VT; 561 MVT SVT = VT; 562 while (SVT != MVT::f32) { 563 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 564 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 565 // Only do this if the target has a native EXTLOAD instruction from 566 // smaller type. 567 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 568 TLI.ShouldShrinkFPConstant(OrigVT)) { 569 const Type *SType = SVT.getTypeForMVT(); 570 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 571 VT = SVT; 572 Extend = true; 573 } 574 } 575 576 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 577 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 578 if (Extend) 579 return DAG.getExtLoad(ISD::EXTLOAD, dl, 580 OrigVT, DAG.getEntryNode(), 581 CPIdx, PseudoSourceValue::getConstantPool(), 582 0, VT, false, Alignment); 583 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 584 PseudoSourceValue::getConstantPool(), 0, false, Alignment); 585} 586 587 588/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 589/// operations. 590static 591SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, 592 SelectionDAG &DAG, 593 const TargetLowering &TLI) { 594 DebugLoc dl = Node->getDebugLoc(); 595 MVT VT = Node->getValueType(0); 596 MVT SrcVT = Node->getOperand(1).getValueType(); 597 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 598 "fcopysign expansion only supported for f32 and f64"); 599 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 600 601 // First get the sign bit of second operand. 602 SDValue Mask1 = (SrcVT == MVT::f64) 603 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 604 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 605 Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1); 606 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, 607 Node->getOperand(1)); 608 SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1); 609 // Shift right or sign-extend it if the two operands have different types. 610 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); 611 if (SizeDiff > 0) { 612 SignBit = DAG.getNode(ISD::SRL, dl, SrcNVT, SignBit, 613 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 614 SignBit = DAG.getNode(ISD::TRUNCATE, dl, NVT, SignBit); 615 } else if (SizeDiff < 0) { 616 SignBit = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, SignBit); 617 SignBit = DAG.getNode(ISD::SHL, dl, NVT, SignBit, 618 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy())); 619 } 620 621 // Clear the sign bit of first operand. 622 SDValue Mask2 = (VT == MVT::f64) 623 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 624 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 625 Mask2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask2); 626 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 627 Result = DAG.getNode(ISD::AND, dl, NVT, Result, Mask2); 628 629 // Or the value with the sign bit. 630 Result = DAG.getNode(ISD::OR, dl, NVT, Result, SignBit); 631 return Result; 632} 633 634/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 635static 636SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 637 const TargetLowering &TLI) { 638 SDValue Chain = ST->getChain(); 639 SDValue Ptr = ST->getBasePtr(); 640 SDValue Val = ST->getValue(); 641 MVT VT = Val.getValueType(); 642 int Alignment = ST->getAlignment(); 643 int SVOffset = ST->getSrcValueOffset(); 644 DebugLoc dl = ST->getDebugLoc(); 645 if (ST->getMemoryVT().isFloatingPoint() || 646 ST->getMemoryVT().isVector()) { 647 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits()); 648 if (TLI.isTypeLegal(intVT)) { 649 // Expand to a bitconvert of the value to the integer type of the 650 // same size, then a (misaligned) int store. 651 // FIXME: Does not handle truncating floating point stores! 652 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 653 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 654 SVOffset, ST->isVolatile(), Alignment); 655 } else { 656 // Do a (aligned) store to a stack slot, then copy from the stack slot 657 // to the final destination using (unaligned) integer loads and stores. 658 MVT StoredVT = ST->getMemoryVT(); 659 MVT RegVT = 660 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits())); 661 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 662 unsigned RegBytes = RegVT.getSizeInBits() / 8; 663 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 664 665 // Make sure the stack slot is also aligned for the register type. 666 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 667 668 // Perform the original store, only redirected to the stack slot. 669 SDValue Store = DAG.getTruncStore(Chain, dl, 670 Val, StackPtr, NULL, 0, StoredVT); 671 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 672 SmallVector<SDValue, 8> Stores; 673 unsigned Offset = 0; 674 675 // Do all but one copies using the full register width. 676 for (unsigned i = 1; i < NumRegs; i++) { 677 // Load one integer register's worth from the stack slot. 678 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0); 679 // Store it to the final location. Remember the store. 680 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 681 ST->getSrcValue(), SVOffset + Offset, 682 ST->isVolatile(), 683 MinAlign(ST->getAlignment(), Offset))); 684 // Increment the pointers. 685 Offset += RegBytes; 686 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 687 Increment); 688 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 689 } 690 691 // The last store may be partial. Do a truncating store. On big-endian 692 // machines this requires an extending load from the stack slot to ensure 693 // that the bits are in the right place. 694 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset)); 695 696 // Load from the stack slot. 697 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 698 NULL, 0, MemVT); 699 700 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 701 ST->getSrcValue(), SVOffset + Offset, 702 MemVT, ST->isVolatile(), 703 MinAlign(ST->getAlignment(), Offset))); 704 // The order of the stores doesn't matter - say it with a TokenFactor. 705 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 706 Stores.size()); 707 } 708 } 709 assert(ST->getMemoryVT().isInteger() && 710 !ST->getMemoryVT().isVector() && 711 "Unaligned store of unknown type."); 712 // Get the half-size VT 713 MVT NewStoredVT = 714 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 715 int NumBits = NewStoredVT.getSizeInBits(); 716 int IncrementSize = NumBits / 8; 717 718 // Divide the stored value in two parts. 719 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 720 SDValue Lo = Val; 721 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 722 723 // Store the two parts 724 SDValue Store1, Store2; 725 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 726 ST->getSrcValue(), SVOffset, NewStoredVT, 727 ST->isVolatile(), Alignment); 728 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 729 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 730 Alignment = MinAlign(Alignment, IncrementSize); 731 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 732 ST->getSrcValue(), SVOffset + IncrementSize, 733 NewStoredVT, ST->isVolatile(), Alignment); 734 735 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 736} 737 738/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 739static 740SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 741 const TargetLowering &TLI) { 742 int SVOffset = LD->getSrcValueOffset(); 743 SDValue Chain = LD->getChain(); 744 SDValue Ptr = LD->getBasePtr(); 745 MVT VT = LD->getValueType(0); 746 MVT LoadedVT = LD->getMemoryVT(); 747 DebugLoc dl = LD->getDebugLoc(); 748 if (VT.isFloatingPoint() || VT.isVector()) { 749 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits()); 750 if (TLI.isTypeLegal(intVT)) { 751 // Expand to a (misaligned) integer load of the same size, 752 // then bitconvert to floating point or vector. 753 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 754 SVOffset, LD->isVolatile(), 755 LD->getAlignment()); 756 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 757 if (VT.isFloatingPoint() && LoadedVT != VT) 758 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 759 760 SDValue Ops[] = { Result, Chain }; 761 return DAG.getMergeValues(Ops, 2, dl); 762 } else { 763 // Copy the value to a (aligned) stack slot using (unaligned) integer 764 // loads and stores, then do a (aligned) load from the stack slot. 765 MVT RegVT = TLI.getRegisterType(intVT); 766 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 767 unsigned RegBytes = RegVT.getSizeInBits() / 8; 768 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 769 770 // Make sure the stack slot is also aligned for the register type. 771 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 772 773 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 774 SmallVector<SDValue, 8> Stores; 775 SDValue StackPtr = StackBase; 776 unsigned Offset = 0; 777 778 // Do all but one copies using the full register width. 779 for (unsigned i = 1; i < NumRegs; i++) { 780 // Load one integer register's worth from the original location. 781 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 782 SVOffset + Offset, LD->isVolatile(), 783 MinAlign(LD->getAlignment(), Offset)); 784 // Follow the load with a store to the stack slot. Remember the store. 785 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 786 NULL, 0)); 787 // Increment the pointers. 788 Offset += RegBytes; 789 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 790 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 791 Increment); 792 } 793 794 // The last copy may be partial. Do an extending load. 795 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset)); 796 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 797 LD->getSrcValue(), SVOffset + Offset, 798 MemVT, LD->isVolatile(), 799 MinAlign(LD->getAlignment(), Offset)); 800 // Follow the load with a store to the stack slot. Remember the store. 801 // On big-endian machines this requires a truncating store to ensure 802 // that the bits end up in the right place. 803 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 804 NULL, 0, MemVT)); 805 806 // The order of the stores doesn't matter - say it with a TokenFactor. 807 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 808 Stores.size()); 809 810 // Finally, perform the original load only redirected to the stack slot. 811 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 812 NULL, 0, LoadedVT); 813 814 // Callers expect a MERGE_VALUES node. 815 SDValue Ops[] = { Load, TF }; 816 return DAG.getMergeValues(Ops, 2, dl); 817 } 818 } 819 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 820 "Unaligned load of unsupported type."); 821 822 // Compute the new VT that is half the size of the old one. This is an 823 // integer MVT. 824 unsigned NumBits = LoadedVT.getSizeInBits(); 825 MVT NewLoadedVT; 826 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 827 NumBits >>= 1; 828 829 unsigned Alignment = LD->getAlignment(); 830 unsigned IncrementSize = NumBits / 8; 831 ISD::LoadExtType HiExtType = LD->getExtensionType(); 832 833 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 834 if (HiExtType == ISD::NON_EXTLOAD) 835 HiExtType = ISD::ZEXTLOAD; 836 837 // Load the value in two parts 838 SDValue Lo, Hi; 839 if (TLI.isLittleEndian()) { 840 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 841 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 842 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 843 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 844 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 845 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 846 MinAlign(Alignment, IncrementSize)); 847 } else { 848 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 849 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 850 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 851 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 852 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 853 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 854 MinAlign(Alignment, IncrementSize)); 855 } 856 857 // aggregate the two parts 858 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 859 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 860 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 861 862 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 863 Hi.getValue(1)); 864 865 SDValue Ops[] = { Result, TF }; 866 return DAG.getMergeValues(Ops, 2, dl); 867} 868 869/// UnrollVectorOp - We know that the given vector has a legal type, however 870/// the operation it performs is not legal and is an operation that we have 871/// no way of lowering. "Unroll" the vector, splitting out the scalars and 872/// operating on each element individually. 873SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) { 874 MVT VT = Op.getValueType(); 875 assert(isTypeLegal(VT) && 876 "Caller should expand or promote operands that are not legal!"); 877 assert(Op.getNode()->getNumValues() == 1 && 878 "Can't unroll a vector with multiple results!"); 879 unsigned NE = VT.getVectorNumElements(); 880 MVT EltVT = VT.getVectorElementType(); 881 DebugLoc dl = Op.getDebugLoc(); 882 883 SmallVector<SDValue, 8> Scalars; 884 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 885 for (unsigned i = 0; i != NE; ++i) { 886 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 887 SDValue Operand = Op.getOperand(j); 888 MVT OperandVT = Operand.getValueType(); 889 if (OperandVT.isVector()) { 890 // A vector operand; extract a single element. 891 MVT OperandEltVT = OperandVT.getVectorElementType(); 892 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 893 OperandEltVT, 894 Operand, 895 DAG.getConstant(i, MVT::i32)); 896 } else { 897 // A scalar operand; just use it as is. 898 Operands[j] = Operand; 899 } 900 } 901 902 switch (Op.getOpcode()) { 903 default: 904 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, 905 &Operands[0], Operands.size())); 906 break; 907 case ISD::SHL: 908 case ISD::SRA: 909 case ISD::SRL: 910 case ISD::ROTL: 911 case ISD::ROTR: 912 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0], 913 DAG.getShiftAmountOperand(Operands[1]))); 914 break; 915 } 916 } 917 918 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size()); 919} 920 921/// GetFPLibCall - Return the right libcall for the given floating point type. 922static RTLIB::Libcall GetFPLibCall(MVT VT, 923 RTLIB::Libcall Call_F32, 924 RTLIB::Libcall Call_F64, 925 RTLIB::Libcall Call_F80, 926 RTLIB::Libcall Call_PPCF128) { 927 return 928 VT == MVT::f32 ? Call_F32 : 929 VT == MVT::f64 ? Call_F64 : 930 VT == MVT::f80 ? Call_F80 : 931 VT == MVT::ppcf128 ? Call_PPCF128 : 932 RTLIB::UNKNOWN_LIBCALL; 933} 934 935/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 936/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 937/// is necessary to spill the vector being inserted into to memory, perform 938/// the insert there, and then read the result back. 939SDValue SelectionDAGLegalize:: 940PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 941 DebugLoc dl) { 942 SDValue Tmp1 = Vec; 943 SDValue Tmp2 = Val; 944 SDValue Tmp3 = Idx; 945 946 // If the target doesn't support this, we have to spill the input vector 947 // to a temporary stack slot, update the element, then reload it. This is 948 // badness. We could also load the value into a vector register (either 949 // with a "move to register" or "extload into register" instruction, then 950 // permute it into place, if the idx is a constant and if the idx is 951 // supported by the target. 952 MVT VT = Tmp1.getValueType(); 953 MVT EltVT = VT.getVectorElementType(); 954 MVT IdxVT = Tmp3.getValueType(); 955 MVT PtrVT = TLI.getPointerTy(); 956 SDValue StackPtr = DAG.CreateStackTemporary(VT); 957 958 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 959 960 // Store the vector. 961 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 962 PseudoSourceValue::getFixedStack(SPFI), 0); 963 964 // Truncate or zero extend offset to target pointer type. 965 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 966 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 967 // Add the offset to the index. 968 unsigned EltSize = EltVT.getSizeInBits()/8; 969 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 970 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 971 // Store the scalar value. 972 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 973 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 974 // Load the updated vector. 975 return DAG.getLoad(VT, dl, Ch, StackPtr, 976 PseudoSourceValue::getFixedStack(SPFI), 0); 977} 978 979 980/// LegalizeOp - We know that the specified value has a legal type, and 981/// that its operands are legal. Now ensure that the operation itself 982/// is legal, recursively ensuring that the operands' operations remain 983/// legal. 984SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 985 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 986 return Op; 987 988 assert(isTypeLegal(Op.getValueType()) && 989 "Caller should expand or promote operands that are not legal!"); 990 SDNode *Node = Op.getNode(); 991 DebugLoc dl = Node->getDebugLoc(); 992 993 // If this operation defines any values that cannot be represented in a 994 // register on this target, make sure to expand or promote them. 995 if (Node->getNumValues() > 1) { 996 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 997 if (getTypeAction(Node->getValueType(i)) != Legal) { 998 HandleOp(Op.getValue(i)); 999 assert(LegalizedNodes.count(Op) && 1000 "Handling didn't add legal operands!"); 1001 return LegalizedNodes[Op]; 1002 } 1003 } 1004 1005 // Note that LegalizeOp may be reentered even from single-use nodes, which 1006 // means that we always must cache transformed nodes. 1007 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1008 if (I != LegalizedNodes.end()) return I->second; 1009 1010 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 1011 SDValue Result = Op; 1012 bool isCustom = false; 1013 1014 switch (Node->getOpcode()) { 1015 case ISD::FrameIndex: 1016 case ISD::EntryToken: 1017 case ISD::Register: 1018 case ISD::BasicBlock: 1019 case ISD::TargetFrameIndex: 1020 case ISD::TargetJumpTable: 1021 case ISD::TargetConstant: 1022 case ISD::TargetConstantFP: 1023 case ISD::TargetConstantPool: 1024 case ISD::TargetGlobalAddress: 1025 case ISD::TargetGlobalTLSAddress: 1026 case ISD::TargetExternalSymbol: 1027 case ISD::VALUETYPE: 1028 case ISD::SRCVALUE: 1029 case ISD::MEMOPERAND: 1030 case ISD::CONDCODE: 1031 case ISD::ARG_FLAGS: 1032 // Primitives must all be legal. 1033 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 1034 "This must be legal!"); 1035 break; 1036 default: 1037 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 1038 // If this is a target node, legalize it by legalizing the operands then 1039 // passing it through. 1040 SmallVector<SDValue, 8> Ops; 1041 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1042 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1043 1044 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 1045 1046 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1047 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 1048 return Result.getValue(Op.getResNo()); 1049 } 1050 // Otherwise this is an unhandled builtin node. splat. 1051#ifndef NDEBUG 1052 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 1053#endif 1054 assert(0 && "Do not know how to legalize this operator!"); 1055 abort(); 1056 case ISD::GLOBAL_OFFSET_TABLE: 1057 case ISD::GlobalAddress: 1058 case ISD::GlobalTLSAddress: 1059 case ISD::ExternalSymbol: 1060 case ISD::ConstantPool: 1061 case ISD::JumpTable: // Nothing to do. 1062 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1063 default: assert(0 && "This action is not supported yet!"); 1064 case TargetLowering::Custom: 1065 Tmp1 = TLI.LowerOperation(Op, DAG); 1066 if (Tmp1.getNode()) Result = Tmp1; 1067 // FALLTHROUGH if the target doesn't want to lower this op after all. 1068 case TargetLowering::Legal: 1069 break; 1070 } 1071 break; 1072 case ISD::FRAMEADDR: 1073 case ISD::RETURNADDR: 1074 // The only option for these nodes is to custom lower them. If the target 1075 // does not custom lower them, then return zero. 1076 Tmp1 = TLI.LowerOperation(Op, DAG); 1077 if (Tmp1.getNode()) 1078 Result = Tmp1; 1079 else 1080 Result = DAG.getConstant(0, TLI.getPointerTy()); 1081 break; 1082 case ISD::FRAME_TO_ARGS_OFFSET: { 1083 MVT VT = Node->getValueType(0); 1084 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1085 default: assert(0 && "This action is not supported yet!"); 1086 case TargetLowering::Custom: 1087 Result = TLI.LowerOperation(Op, DAG); 1088 if (Result.getNode()) break; 1089 // Fall Thru 1090 case TargetLowering::Legal: 1091 Result = DAG.getConstant(0, VT); 1092 break; 1093 } 1094 } 1095 break; 1096 case ISD::EXCEPTIONADDR: { 1097 Tmp1 = LegalizeOp(Node->getOperand(0)); 1098 MVT VT = Node->getValueType(0); 1099 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1100 default: assert(0 && "This action is not supported yet!"); 1101 case TargetLowering::Expand: { 1102 unsigned Reg = TLI.getExceptionAddressRegister(); 1103 Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT); 1104 } 1105 break; 1106 case TargetLowering::Custom: 1107 Result = TLI.LowerOperation(Op, DAG); 1108 if (Result.getNode()) break; 1109 // Fall Thru 1110 case TargetLowering::Legal: { 1111 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 1112 Result = DAG.getMergeValues(Ops, 2, dl); 1113 break; 1114 } 1115 } 1116 } 1117 if (Result.getNode()->getNumValues() == 1) break; 1118 1119 assert(Result.getNode()->getNumValues() == 2 && 1120 "Cannot return more than two values!"); 1121 1122 // Since we produced two values, make sure to remember that we 1123 // legalized both of them. 1124 Tmp1 = LegalizeOp(Result); 1125 Tmp2 = LegalizeOp(Result.getValue(1)); 1126 AddLegalizedOperand(Op.getValue(0), Tmp1); 1127 AddLegalizedOperand(Op.getValue(1), Tmp2); 1128 return Op.getResNo() ? Tmp2 : Tmp1; 1129 case ISD::EHSELECTION: { 1130 Tmp1 = LegalizeOp(Node->getOperand(0)); 1131 Tmp2 = LegalizeOp(Node->getOperand(1)); 1132 MVT VT = Node->getValueType(0); 1133 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1134 default: assert(0 && "This action is not supported yet!"); 1135 case TargetLowering::Expand: { 1136 unsigned Reg = TLI.getExceptionSelectorRegister(); 1137 Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT); 1138 } 1139 break; 1140 case TargetLowering::Custom: 1141 Result = TLI.LowerOperation(Op, DAG); 1142 if (Result.getNode()) break; 1143 // Fall Thru 1144 case TargetLowering::Legal: { 1145 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 1146 Result = DAG.getMergeValues(Ops, 2, dl); 1147 break; 1148 } 1149 } 1150 } 1151 if (Result.getNode()->getNumValues() == 1) break; 1152 1153 assert(Result.getNode()->getNumValues() == 2 && 1154 "Cannot return more than two values!"); 1155 1156 // Since we produced two values, make sure to remember that we 1157 // legalized both of them. 1158 Tmp1 = LegalizeOp(Result); 1159 Tmp2 = LegalizeOp(Result.getValue(1)); 1160 AddLegalizedOperand(Op.getValue(0), Tmp1); 1161 AddLegalizedOperand(Op.getValue(1), Tmp2); 1162 return Op.getResNo() ? Tmp2 : Tmp1; 1163 case ISD::EH_RETURN: { 1164 MVT VT = Node->getValueType(0); 1165 // The only "good" option for this node is to custom lower it. 1166 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1167 default: assert(0 && "This action is not supported at all!"); 1168 case TargetLowering::Custom: 1169 Result = TLI.LowerOperation(Op, DAG); 1170 if (Result.getNode()) break; 1171 // Fall Thru 1172 case TargetLowering::Legal: 1173 // Target does not know, how to lower this, lower to noop 1174 Result = LegalizeOp(Node->getOperand(0)); 1175 break; 1176 } 1177 } 1178 break; 1179 case ISD::AssertSext: 1180 case ISD::AssertZext: 1181 Tmp1 = LegalizeOp(Node->getOperand(0)); 1182 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1183 break; 1184 case ISD::MERGE_VALUES: 1185 // Legalize eliminates MERGE_VALUES nodes. 1186 Result = Node->getOperand(Op.getResNo()); 1187 break; 1188 case ISD::CopyFromReg: 1189 Tmp1 = LegalizeOp(Node->getOperand(0)); 1190 Result = Op.getValue(0); 1191 if (Node->getNumValues() == 2) { 1192 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1193 } else { 1194 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 1195 if (Node->getNumOperands() == 3) { 1196 Tmp2 = LegalizeOp(Node->getOperand(2)); 1197 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1198 } else { 1199 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1200 } 1201 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 1202 } 1203 // Since CopyFromReg produces two values, make sure to remember that we 1204 // legalized both of them. 1205 AddLegalizedOperand(Op.getValue(0), Result); 1206 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1207 return Result.getValue(Op.getResNo()); 1208 case ISD::UNDEF: { 1209 MVT VT = Op.getValueType(); 1210 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 1211 default: assert(0 && "This action is not supported yet!"); 1212 case TargetLowering::Expand: 1213 if (VT.isInteger()) 1214 Result = DAG.getConstant(0, VT); 1215 else if (VT.isFloatingPoint()) 1216 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), 1217 VT); 1218 else 1219 assert(0 && "Unknown value type!"); 1220 break; 1221 case TargetLowering::Legal: 1222 break; 1223 } 1224 break; 1225 } 1226 1227 case ISD::INTRINSIC_W_CHAIN: 1228 case ISD::INTRINSIC_WO_CHAIN: 1229 case ISD::INTRINSIC_VOID: { 1230 SmallVector<SDValue, 8> Ops; 1231 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1232 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1233 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1234 1235 // Allow the target to custom lower its intrinsics if it wants to. 1236 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1237 TargetLowering::Custom) { 1238 Tmp3 = TLI.LowerOperation(Result, DAG); 1239 if (Tmp3.getNode()) Result = Tmp3; 1240 } 1241 1242 if (Result.getNode()->getNumValues() == 1) break; 1243 1244 // Must have return value and chain result. 1245 assert(Result.getNode()->getNumValues() == 2 && 1246 "Cannot return more than two values!"); 1247 1248 // Since loads produce two values, make sure to remember that we 1249 // legalized both of them. 1250 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1251 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1252 return Result.getValue(Op.getResNo()); 1253 } 1254 1255 case ISD::DBG_STOPPOINT: 1256 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!"); 1257 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1258 1259 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) { 1260 case TargetLowering::Promote: 1261 default: assert(0 && "This action is not supported yet!"); 1262 case TargetLowering::Expand: { 1263 DwarfWriter *DW = DAG.getDwarfWriter(); 1264 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, 1265 MVT::Other); 1266 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); 1267 1268 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1269 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit()); 1270 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) { 1271 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit())); 1272 1273 unsigned Line = DSP->getLine(); 1274 unsigned Col = DSP->getColumn(); 1275 1276 if (OptLevel == CodeGenOpt::None) { 1277 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it 1278 // won't hurt anything. 1279 if (useDEBUG_LOC) { 1280 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), 1281 DAG.getConstant(Col, MVT::i32), 1282 DAG.getSrcValue(CU.getGV()) }; 1283 Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4); 1284 } else { 1285 unsigned ID = DW->RecordSourceLine(Line, Col, CU); 1286 Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID); 1287 } 1288 } else { 1289 Result = Tmp1; // chain 1290 } 1291 } else { 1292 Result = Tmp1; // chain 1293 } 1294 break; 1295 } 1296 case TargetLowering::Custom: 1297 Result = TLI.LowerOperation(Op, DAG); 1298 if (Result.getNode()) 1299 break; 1300 case TargetLowering::Legal: { 1301 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1302 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1303 break; 1304 1305 SmallVector<SDValue, 8> Ops; 1306 Ops.push_back(Tmp1); 1307 if (Action == Legal) { 1308 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1309 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1310 } else { 1311 // Otherwise promote them. 1312 Ops.push_back(PromoteOp(Node->getOperand(1))); 1313 Ops.push_back(PromoteOp(Node->getOperand(2))); 1314 } 1315 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1316 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1317 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1318 break; 1319 } 1320 } 1321 break; 1322 1323 case ISD::DECLARE: 1324 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1325 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1326 default: assert(0 && "This action is not supported yet!"); 1327 case TargetLowering::Legal: 1328 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1329 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1330 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1331 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1332 break; 1333 case TargetLowering::Expand: 1334 Result = LegalizeOp(Node->getOperand(0)); 1335 break; 1336 } 1337 break; 1338 1339 case ISD::DEBUG_LOC: 1340 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1341 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1342 default: assert(0 && "This action is not supported yet!"); 1343 case TargetLowering::Legal: { 1344 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1345 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1346 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1347 break; 1348 if (Action == Legal) { 1349 Tmp2 = Node->getOperand(1); 1350 Tmp3 = Node->getOperand(2); 1351 Tmp4 = Node->getOperand(3); 1352 } else { 1353 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1354 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1355 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1356 } 1357 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1358 break; 1359 } 1360 } 1361 break; 1362 1363 case ISD::DBG_LABEL: 1364 case ISD::EH_LABEL: 1365 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!"); 1366 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1367 default: assert(0 && "This action is not supported yet!"); 1368 case TargetLowering::Legal: 1369 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1370 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1371 break; 1372 case TargetLowering::Expand: 1373 Result = LegalizeOp(Node->getOperand(0)); 1374 break; 1375 } 1376 break; 1377 1378 case ISD::PREFETCH: 1379 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1380 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1381 default: assert(0 && "This action is not supported yet!"); 1382 case TargetLowering::Legal: 1383 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1384 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1385 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1386 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1387 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1388 break; 1389 case TargetLowering::Expand: 1390 // It's a noop. 1391 Result = LegalizeOp(Node->getOperand(0)); 1392 break; 1393 } 1394 break; 1395 1396 case ISD::MEMBARRIER: { 1397 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1398 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1399 default: assert(0 && "This action is not supported yet!"); 1400 case TargetLowering::Legal: { 1401 SDValue Ops[6]; 1402 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1403 for (int x = 1; x < 6; ++x) { 1404 Ops[x] = Node->getOperand(x); 1405 if (!isTypeLegal(Ops[x].getValueType())) 1406 Ops[x] = PromoteOp(Ops[x]); 1407 } 1408 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1409 break; 1410 } 1411 case TargetLowering::Expand: 1412 //There is no libgcc call for this op 1413 Result = Node->getOperand(0); // Noop 1414 break; 1415 } 1416 break; 1417 } 1418 1419 case ISD::ATOMIC_CMP_SWAP: { 1420 unsigned int num_operands = 4; 1421 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1422 SDValue Ops[4]; 1423 for (unsigned int x = 0; x < num_operands; ++x) 1424 Ops[x] = LegalizeOp(Node->getOperand(x)); 1425 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1426 1427 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1428 default: assert(0 && "This action is not supported yet!"); 1429 case TargetLowering::Custom: 1430 Result = TLI.LowerOperation(Result, DAG); 1431 break; 1432 case TargetLowering::Legal: 1433 break; 1434 } 1435 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1436 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1437 return Result.getValue(Op.getResNo()); 1438 } 1439 case ISD::ATOMIC_LOAD_ADD: 1440 case ISD::ATOMIC_LOAD_SUB: 1441 case ISD::ATOMIC_LOAD_AND: 1442 case ISD::ATOMIC_LOAD_OR: 1443 case ISD::ATOMIC_LOAD_XOR: 1444 case ISD::ATOMIC_LOAD_NAND: 1445 case ISD::ATOMIC_LOAD_MIN: 1446 case ISD::ATOMIC_LOAD_MAX: 1447 case ISD::ATOMIC_LOAD_UMIN: 1448 case ISD::ATOMIC_LOAD_UMAX: 1449 case ISD::ATOMIC_SWAP: { 1450 unsigned int num_operands = 3; 1451 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1452 SDValue Ops[3]; 1453 for (unsigned int x = 0; x < num_operands; ++x) 1454 Ops[x] = LegalizeOp(Node->getOperand(x)); 1455 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1456 1457 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1458 default: assert(0 && "This action is not supported yet!"); 1459 case TargetLowering::Custom: 1460 Result = TLI.LowerOperation(Result, DAG); 1461 break; 1462 case TargetLowering::Legal: 1463 break; 1464 } 1465 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1466 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1467 return Result.getValue(Op.getResNo()); 1468 } 1469 case ISD::Constant: { 1470 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1471 unsigned opAction = 1472 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1473 1474 // We know we don't need to expand constants here, constants only have one 1475 // value and we check that it is fine above. 1476 1477 if (opAction == TargetLowering::Custom) { 1478 Tmp1 = TLI.LowerOperation(Result, DAG); 1479 if (Tmp1.getNode()) 1480 Result = Tmp1; 1481 } 1482 break; 1483 } 1484 case ISD::ConstantFP: { 1485 // Spill FP immediates to the constant pool if the target cannot directly 1486 // codegen them. Targets often have some immediate values that can be 1487 // efficiently generated into an FP register without a load. We explicitly 1488 // leave these constants as ConstantFP nodes for the target to deal with. 1489 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1490 1491 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1492 default: assert(0 && "This action is not supported yet!"); 1493 case TargetLowering::Legal: 1494 break; 1495 case TargetLowering::Custom: 1496 Tmp3 = TLI.LowerOperation(Result, DAG); 1497 if (Tmp3.getNode()) { 1498 Result = Tmp3; 1499 break; 1500 } 1501 // FALLTHROUGH 1502 case TargetLowering::Expand: { 1503 // Check to see if this FP immediate is already legal. 1504 bool isLegal = false; 1505 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1506 E = TLI.legal_fpimm_end(); I != E; ++I) { 1507 if (CFP->isExactlyValue(*I)) { 1508 isLegal = true; 1509 break; 1510 } 1511 } 1512 // If this is a legal constant, turn it into a TargetConstantFP node. 1513 if (isLegal) 1514 break; 1515 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1516 } 1517 } 1518 break; 1519 } 1520 case ISD::TokenFactor: 1521 if (Node->getNumOperands() == 2) { 1522 Tmp1 = LegalizeOp(Node->getOperand(0)); 1523 Tmp2 = LegalizeOp(Node->getOperand(1)); 1524 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1525 } else if (Node->getNumOperands() == 3) { 1526 Tmp1 = LegalizeOp(Node->getOperand(0)); 1527 Tmp2 = LegalizeOp(Node->getOperand(1)); 1528 Tmp3 = LegalizeOp(Node->getOperand(2)); 1529 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1530 } else { 1531 SmallVector<SDValue, 8> Ops; 1532 // Legalize the operands. 1533 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1534 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1535 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1536 } 1537 break; 1538 1539 case ISD::FORMAL_ARGUMENTS: 1540 case ISD::CALL: 1541 // The only option for this is to custom lower it. 1542 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1543 assert(Tmp3.getNode() && "Target didn't custom lower this node!"); 1544 // A call within a calling sequence must be legalized to something 1545 // other than the normal CALLSEQ_END. Violating this gets Legalize 1546 // into an infinite loop. 1547 assert ((!IsLegalizingCall || 1548 Node->getOpcode() != ISD::CALL || 1549 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) && 1550 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1551 1552 // The number of incoming and outgoing values should match; unless the final 1553 // outgoing value is a flag. 1554 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || 1555 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 && 1556 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == 1557 MVT::Flag)) && 1558 "Lowering call/formal_arguments produced unexpected # results!"); 1559 1560 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1561 // remember that we legalized all of them, so it doesn't get relegalized. 1562 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) { 1563 if (Tmp3.getNode()->getValueType(i) == MVT::Flag) 1564 continue; 1565 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1566 if (Op.getResNo() == i) 1567 Tmp2 = Tmp1; 1568 AddLegalizedOperand(SDValue(Node, i), Tmp1); 1569 } 1570 return Tmp2; 1571 case ISD::BUILD_VECTOR: 1572 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1573 default: assert(0 && "This action is not supported yet!"); 1574 case TargetLowering::Custom: 1575 Tmp3 = TLI.LowerOperation(Result, DAG); 1576 if (Tmp3.getNode()) { 1577 Result = Tmp3; 1578 break; 1579 } 1580 // FALLTHROUGH 1581 case TargetLowering::Expand: 1582 Result = ExpandBUILD_VECTOR(Result.getNode()); 1583 break; 1584 } 1585 break; 1586 case ISD::INSERT_VECTOR_ELT: 1587 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1588 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1589 1590 // The type of the value to insert may not be legal, even though the vector 1591 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1592 // here. 1593 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1594 default: assert(0 && "Cannot expand insert element operand"); 1595 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1596 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1597 case Expand: 1598 // FIXME: An alternative would be to check to see if the target is not 1599 // going to custom lower this operation, we could bitcast to half elt 1600 // width and perform two inserts at that width, if that is legal. 1601 Tmp2 = Node->getOperand(1); 1602 break; 1603 } 1604 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1605 1606 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1607 Node->getValueType(0))) { 1608 default: assert(0 && "This action is not supported yet!"); 1609 case TargetLowering::Legal: 1610 break; 1611 case TargetLowering::Custom: 1612 Tmp4 = TLI.LowerOperation(Result, DAG); 1613 if (Tmp4.getNode()) { 1614 Result = Tmp4; 1615 break; 1616 } 1617 // FALLTHROUGH 1618 case TargetLowering::Promote: 1619 // Fall thru for vector case 1620 case TargetLowering::Expand: { 1621 // If the insert index is a constant, codegen this as a scalar_to_vector, 1622 // then a shuffle that inserts it into the right position in the vector. 1623 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1624 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1625 // match the element type of the vector being created, except for 1626 // integers in which case the inserted value can be over width. 1627 MVT EltVT = Op.getValueType().getVectorElementType(); 1628 if (Tmp2.getValueType() == EltVT || 1629 (EltVT.isInteger() && Tmp2.getValueType().bitsGE(EltVT))) { 1630 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 1631 Tmp1.getValueType(), Tmp2); 1632 1633 unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); 1634 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1635 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1636 // elt 0 of the RHS. 1637 SmallVector<int, 8> ShufOps; 1638 for (unsigned i = 0; i != NumElts; ++i) 1639 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 1640 1641 Result = DAG.getVectorShuffle(Tmp1.getValueType(), dl, Tmp1, ScVec, 1642 &ShufOps[0]); 1643 Result = LegalizeOp(Result); 1644 break; 1645 } 1646 } 1647 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl); 1648 break; 1649 } 1650 } 1651 break; 1652 case ISD::SCALAR_TO_VECTOR: 1653 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1654 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1655 break; 1656 } 1657 1658 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1659 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1660 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1661 Node->getValueType(0))) { 1662 default: assert(0 && "This action is not supported yet!"); 1663 case TargetLowering::Legal: 1664 break; 1665 case TargetLowering::Custom: 1666 Tmp3 = TLI.LowerOperation(Result, DAG); 1667 if (Tmp3.getNode()) { 1668 Result = Tmp3; 1669 break; 1670 } 1671 // FALLTHROUGH 1672 case TargetLowering::Expand: 1673 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1674 break; 1675 } 1676 break; 1677 case ISD::VECTOR_SHUFFLE: { 1678 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1679 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1680 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1681 MVT VT = Result.getValueType(); 1682 1683 // Copy the Mask to a local SmallVector for use with isShuffleMaskLegal. 1684 SmallVector<int, 8> Mask; 1685 cast<ShuffleVectorSDNode>(Result)->getMask(Mask); 1686 1687 // Allow targets to custom lower the SHUFFLEs they support. 1688 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 1689 default: assert(0 && "Unknown operation action!"); 1690 case TargetLowering::Legal: 1691 assert(TLI.isShuffleMaskLegal(Mask, VT) && 1692 "vector shuffle should not be created if not legal!"); 1693 break; 1694 case TargetLowering::Custom: 1695 Tmp3 = TLI.LowerOperation(Result, DAG); 1696 if (Tmp3.getNode()) { 1697 Result = Tmp3; 1698 break; 1699 } 1700 // FALLTHROUGH 1701 case TargetLowering::Expand: { 1702 MVT EltVT = VT.getVectorElementType(); 1703 unsigned NumElems = VT.getVectorNumElements(); 1704 SmallVector<SDValue, 8> Ops; 1705 for (unsigned i = 0; i != NumElems; ++i) { 1706 if (Mask[i] < 0) { 1707 Ops.push_back(DAG.getUNDEF(EltVT)); 1708 continue; 1709 } 1710 unsigned Idx = Mask[i]; 1711 if (Idx < NumElems) 1712 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1, 1713 DAG.getIntPtrConstant(Idx))); 1714 else 1715 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2, 1716 DAG.getIntPtrConstant(Idx - NumElems))); 1717 } 1718 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 1719 break; 1720 } 1721 case TargetLowering::Promote: { 1722 // Change base type to a different vector type. 1723 MVT OVT = Node->getValueType(0); 1724 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1725 1726 // Cast the two input vectors. 1727 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1); 1728 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2); 1729 1730 // Convert the shuffle mask to the right # elements. 1731 Result = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 1732 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result); 1733 break; 1734 } 1735 } 1736 break; 1737 } 1738 case ISD::EXTRACT_VECTOR_ELT: 1739 Tmp1 = Node->getOperand(0); 1740 Tmp2 = LegalizeOp(Node->getOperand(1)); 1741 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1742 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1743 break; 1744 1745 case ISD::EXTRACT_SUBVECTOR: 1746 Tmp1 = Node->getOperand(0); 1747 Tmp2 = LegalizeOp(Node->getOperand(1)); 1748 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1749 Result = ExpandEXTRACT_SUBVECTOR(Result); 1750 break; 1751 1752 case ISD::CONCAT_VECTORS: { 1753 // Legalize the operands. 1754 SmallVector<SDValue, 8> Ops; 1755 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1756 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1757 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1758 1759 switch (TLI.getOperationAction(ISD::CONCAT_VECTORS, 1760 Node->getValueType(0))) { 1761 default: assert(0 && "Unknown operation action!"); 1762 case TargetLowering::Legal: 1763 break; 1764 case TargetLowering::Custom: 1765 Tmp3 = TLI.LowerOperation(Result, DAG); 1766 if (Tmp3.getNode()) { 1767 Result = Tmp3; 1768 break; 1769 } 1770 // FALLTHROUGH 1771 case TargetLowering::Expand: { 1772 // Use extract/insert/build vector for now. We might try to be 1773 // more clever later. 1774 MVT PtrVT = TLI.getPointerTy(); 1775 SmallVector<SDValue, 8> Ops; 1776 unsigned NumOperands = Node->getNumOperands(); 1777 for (unsigned i=0; i < NumOperands; ++i) { 1778 SDValue SubOp = Node->getOperand(i); 1779 MVT VVT = SubOp.getNode()->getValueType(0); 1780 MVT EltVT = VVT.getVectorElementType(); 1781 unsigned NumSubElem = VVT.getVectorNumElements(); 1782 for (unsigned j=0; j < NumSubElem; ++j) { 1783 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, 1784 DAG.getConstant(j, PtrVT))); 1785 } 1786 } 1787 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, dl, 1788 Node->getValueType(0), 1789 &Ops[0], Ops.size())); 1790 } 1791 } 1792 break; 1793 } 1794 1795 case ISD::CALLSEQ_START: { 1796 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1797 1798 // Recursively Legalize all of the inputs of the call end that do not lead 1799 // to this call start. This ensures that any libcalls that need be inserted 1800 // are inserted *before* the CALLSEQ_START. 1801 IsLegalizingCallArgs = true; 1802 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1803 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1804 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1805 NodesLeadingTo); 1806 } 1807 IsLegalizingCallArgs = false; 1808 1809 // Now that we legalized all of the inputs (which may have inserted 1810 // libcalls) create the new CALLSEQ_START node. 1811 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1812 1813 // Merge in the last call, to ensure that this call start after the last 1814 // call ended. 1815 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1816 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1817 Tmp1, LastCALLSEQ_END); 1818 Tmp1 = LegalizeOp(Tmp1); 1819 } 1820 1821 // Do not try to legalize the target-specific arguments (#1+). 1822 if (Tmp1 != Node->getOperand(0)) { 1823 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1824 Ops[0] = Tmp1; 1825 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1826 } 1827 1828 // Remember that the CALLSEQ_START is legalized. 1829 AddLegalizedOperand(Op.getValue(0), Result); 1830 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1831 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1832 1833 // Now that the callseq_start and all of the non-call nodes above this call 1834 // sequence have been legalized, legalize the call itself. During this 1835 // process, no libcalls can/will be inserted, guaranteeing that no calls 1836 // can overlap. 1837 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1838 // Note that we are selecting this call! 1839 LastCALLSEQ_END = SDValue(CallEnd, 0); 1840 IsLegalizingCall = true; 1841 1842 // Legalize the call, starting from the CALLSEQ_END. 1843 LegalizeOp(LastCALLSEQ_END); 1844 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1845 return Result; 1846 } 1847 case ISD::CALLSEQ_END: 1848 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1849 // will cause this node to be legalized as well as handling libcalls right. 1850 if (LastCALLSEQ_END.getNode() != Node) { 1851 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1852 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1853 assert(I != LegalizedNodes.end() && 1854 "Legalizing the call start should have legalized this node!"); 1855 return I->second; 1856 } 1857 1858 // Otherwise, the call start has been legalized and everything is going 1859 // according to plan. Just legalize ourselves normally here. 1860 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1861 // Do not try to legalize the target-specific arguments (#1+), except for 1862 // an optional flag input. 1863 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1864 if (Tmp1 != Node->getOperand(0)) { 1865 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1866 Ops[0] = Tmp1; 1867 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1868 } 1869 } else { 1870 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1871 if (Tmp1 != Node->getOperand(0) || 1872 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1873 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1874 Ops[0] = Tmp1; 1875 Ops.back() = Tmp2; 1876 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1877 } 1878 } 1879 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1880 // This finishes up call legalization. 1881 IsLegalizingCall = false; 1882 1883 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1884 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1885 if (Node->getNumValues() == 2) 1886 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1887 return Result.getValue(Op.getResNo()); 1888 case ISD::DYNAMIC_STACKALLOC: { 1889 MVT VT = Node->getValueType(0); 1890 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1891 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1892 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1893 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1894 1895 Tmp1 = Result.getValue(0); 1896 Tmp2 = Result.getValue(1); 1897 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1898 default: assert(0 && "This action is not supported yet!"); 1899 case TargetLowering::Expand: { 1900 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1901 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1902 " not tell us which reg is the stack pointer!"); 1903 SDValue Chain = Tmp1.getOperand(0); 1904 1905 // Chain the dynamic stack allocation so that it doesn't modify the stack 1906 // pointer when other instructions are using the stack. 1907 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1908 1909 SDValue Size = Tmp2.getOperand(1); 1910 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1911 Chain = SP.getValue(1); 1912 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1913 unsigned StackAlign = 1914 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1915 if (Align > StackAlign) 1916 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1917 DAG.getConstant(-(uint64_t)Align, VT)); 1918 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1919 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1920 1921 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1922 DAG.getIntPtrConstant(0, true), SDValue()); 1923 1924 Tmp1 = LegalizeOp(Tmp1); 1925 Tmp2 = LegalizeOp(Tmp2); 1926 break; 1927 } 1928 case TargetLowering::Custom: 1929 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1930 if (Tmp3.getNode()) { 1931 Tmp1 = LegalizeOp(Tmp3); 1932 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1933 } 1934 break; 1935 case TargetLowering::Legal: 1936 break; 1937 } 1938 // Since this op produce two values, make sure to remember that we 1939 // legalized both of them. 1940 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1941 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1942 return Op.getResNo() ? Tmp2 : Tmp1; 1943 } 1944 case ISD::INLINEASM: { 1945 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1946 bool Changed = false; 1947 // Legalize all of the operands of the inline asm, in case they are nodes 1948 // that need to be expanded or something. Note we skip the asm string and 1949 // all of the TargetConstant flags. 1950 SDValue Op = LegalizeOp(Ops[0]); 1951 Changed = Op != Ops[0]; 1952 Ops[0] = Op; 1953 1954 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1955 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1956 unsigned NumVals = InlineAsm:: 1957 getNumOperandRegisters(cast<ConstantSDNode>(Ops[i])->getZExtValue()); 1958 for (++i; NumVals; ++i, --NumVals) { 1959 SDValue Op = LegalizeOp(Ops[i]); 1960 if (Op != Ops[i]) { 1961 Changed = true; 1962 Ops[i] = Op; 1963 } 1964 } 1965 } 1966 1967 if (HasInFlag) { 1968 Op = LegalizeOp(Ops.back()); 1969 Changed |= Op != Ops.back(); 1970 Ops.back() = Op; 1971 } 1972 1973 if (Changed) 1974 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1975 1976 // INLINE asm returns a chain and flag, make sure to add both to the map. 1977 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1978 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1979 return Result.getValue(Op.getResNo()); 1980 } 1981 case ISD::BR: 1982 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1983 // Ensure that libcalls are emitted before a branch. 1984 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 1985 Tmp1 = LegalizeOp(Tmp1); 1986 LastCALLSEQ_END = DAG.getEntryNode(); 1987 1988 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1989 break; 1990 case ISD::BRIND: 1991 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1992 // Ensure that libcalls are emitted before a branch. 1993 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 1994 Tmp1 = LegalizeOp(Tmp1); 1995 LastCALLSEQ_END = DAG.getEntryNode(); 1996 1997 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1998 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1999 case Legal: 2000 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 2001 break; 2002 } 2003 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2004 break; 2005 case ISD::BR_JT: 2006 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2007 // Ensure that libcalls are emitted before a branch. 2008 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 2009 Tmp1 = LegalizeOp(Tmp1); 2010 LastCALLSEQ_END = DAG.getEntryNode(); 2011 2012 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 2013 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2014 2015 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 2016 default: assert(0 && "This action is not supported yet!"); 2017 case TargetLowering::Legal: break; 2018 case TargetLowering::Custom: 2019 Tmp1 = TLI.LowerOperation(Result, DAG); 2020 if (Tmp1.getNode()) Result = Tmp1; 2021 break; 2022 case TargetLowering::Expand: { 2023 SDValue Chain = Result.getOperand(0); 2024 SDValue Table = Result.getOperand(1); 2025 SDValue Index = Result.getOperand(2); 2026 2027 MVT PTy = TLI.getPointerTy(); 2028 MachineFunction &MF = DAG.getMachineFunction(); 2029 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 2030 Index= DAG.getNode(ISD::MUL, dl, PTy, 2031 Index, DAG.getConstant(EntrySize, PTy)); 2032 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2033 2034 MVT MemVT = MVT::getIntegerVT(EntrySize * 8); 2035 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 2036 PseudoSourceValue::getJumpTable(), 0, MemVT); 2037 Addr = LD; 2038 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2039 // For PIC, the sequence is: 2040 // BRIND(load(Jumptable + index) + RelocBase) 2041 // RelocBase can be JumpTable, GOT or some sort of global base. 2042 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 2043 TLI.getPICJumpTableRelocBase(Table, DAG)); 2044 } 2045 Result = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 2046 } 2047 } 2048 break; 2049 case ISD::BRCOND: 2050 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2051 // Ensure that libcalls are emitted before a return. 2052 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 2053 Tmp1 = LegalizeOp(Tmp1); 2054 LastCALLSEQ_END = DAG.getEntryNode(); 2055 2056 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2057 case Expand: assert(0 && "It's impossible to expand bools"); 2058 case Legal: 2059 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 2060 break; 2061 case Promote: { 2062 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 2063 2064 // The top bits of the promoted condition are not necessarily zero, ensure 2065 // that the value is properly zero extended. 2066 unsigned BitWidth = Tmp2.getValueSizeInBits(); 2067 if (!DAG.MaskedValueIsZero(Tmp2, 2068 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2069 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1); 2070 break; 2071 } 2072 } 2073 2074 // Basic block destination (Op#2) is always legal. 2075 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2076 2077 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 2078 default: assert(0 && "This action is not supported yet!"); 2079 case TargetLowering::Legal: break; 2080 case TargetLowering::Custom: 2081 Tmp1 = TLI.LowerOperation(Result, DAG); 2082 if (Tmp1.getNode()) Result = Tmp1; 2083 break; 2084 case TargetLowering::Expand: 2085 // Expand brcond's setcc into its constituent parts and create a BR_CC 2086 // Node. 2087 if (Tmp2.getOpcode() == ISD::SETCC) { 2088 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 2089 Tmp1, Tmp2.getOperand(2), 2090 Tmp2.getOperand(0), Tmp2.getOperand(1), 2091 Node->getOperand(2)); 2092 } else { 2093 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 2094 DAG.getCondCode(ISD::SETNE), Tmp2, 2095 DAG.getConstant(0, Tmp2.getValueType()), 2096 Node->getOperand(2)); 2097 } 2098 break; 2099 } 2100 break; 2101 case ISD::BR_CC: 2102 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2103 // Ensure that libcalls are emitted before a branch. 2104 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 2105 Tmp1 = LegalizeOp(Tmp1); 2106 Tmp2 = Node->getOperand(2); // LHS 2107 Tmp3 = Node->getOperand(3); // RHS 2108 Tmp4 = Node->getOperand(1); // CC 2109 2110 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()), 2111 Tmp2, Tmp3, Tmp4, dl); 2112 LastCALLSEQ_END = DAG.getEntryNode(); 2113 2114 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 2115 // the LHS is a legal SETCC itself. In this case, we need to compare 2116 // the result against zero to select between true and false values. 2117 if (Tmp3.getNode() == 0) { 2118 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 2119 Tmp4 = DAG.getCondCode(ISD::SETNE); 2120 } 2121 2122 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 2123 Node->getOperand(4)); 2124 2125 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 2126 default: assert(0 && "Unexpected action for BR_CC!"); 2127 case TargetLowering::Legal: break; 2128 case TargetLowering::Custom: 2129 Tmp4 = TLI.LowerOperation(Result, DAG); 2130 if (Tmp4.getNode()) Result = Tmp4; 2131 break; 2132 } 2133 break; 2134 case ISD::LOAD: { 2135 LoadSDNode *LD = cast<LoadSDNode>(Node); 2136 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 2137 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 2138 2139 ISD::LoadExtType ExtType = LD->getExtensionType(); 2140 if (ExtType == ISD::NON_EXTLOAD) { 2141 MVT VT = Node->getValueType(0); 2142 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2143 Tmp3 = Result.getValue(0); 2144 Tmp4 = Result.getValue(1); 2145 2146 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 2147 default: assert(0 && "This action is not supported yet!"); 2148 case TargetLowering::Legal: 2149 // If this is an unaligned load and the target doesn't support it, 2150 // expand it. 2151 if (!TLI.allowsUnalignedMemoryAccesses()) { 2152 unsigned ABIAlignment = TLI.getTargetData()-> 2153 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2154 if (LD->getAlignment() < ABIAlignment){ 2155 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 2156 TLI); 2157 Tmp3 = Result.getOperand(0); 2158 Tmp4 = Result.getOperand(1); 2159 Tmp3 = LegalizeOp(Tmp3); 2160 Tmp4 = LegalizeOp(Tmp4); 2161 } 2162 } 2163 break; 2164 case TargetLowering::Custom: 2165 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 2166 if (Tmp1.getNode()) { 2167 Tmp3 = LegalizeOp(Tmp1); 2168 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 2169 } 2170 break; 2171 case TargetLowering::Promote: { 2172 // Only promote a load of vector type to another. 2173 assert(VT.isVector() && "Cannot promote this load!"); 2174 // Change base type to a different vector type. 2175 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 2176 2177 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 2178 LD->getSrcValueOffset(), 2179 LD->isVolatile(), LD->getAlignment()); 2180 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 2181 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 2182 break; 2183 } 2184 } 2185 // Since loads produce two values, make sure to remember that we 2186 // legalized both of them. 2187 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 2188 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 2189 return Op.getResNo() ? Tmp4 : Tmp3; 2190 } else { 2191 MVT SrcVT = LD->getMemoryVT(); 2192 unsigned SrcWidth = SrcVT.getSizeInBits(); 2193 int SVOffset = LD->getSrcValueOffset(); 2194 unsigned Alignment = LD->getAlignment(); 2195 bool isVolatile = LD->isVolatile(); 2196 2197 if (SrcWidth != SrcVT.getStoreSizeInBits() && 2198 // Some targets pretend to have an i1 loading operation, and actually 2199 // load an i8. This trick is correct for ZEXTLOAD because the top 7 2200 // bits are guaranteed to be zero; it helps the optimizers understand 2201 // that these bits are zero. It is also useful for EXTLOAD, since it 2202 // tells the optimizers that those bits are undefined. It would be 2203 // nice to have an effective generic way of getting these benefits... 2204 // Until such a way is found, don't insist on promoting i1 here. 2205 (SrcVT != MVT::i1 || 2206 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 2207 // Promote to a byte-sized load if not loading an integral number of 2208 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 2209 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 2210 MVT NVT = MVT::getIntegerVT(NewWidth); 2211 SDValue Ch; 2212 2213 // The extra bits are guaranteed to be zero, since we stored them that 2214 // way. A zext load from NVT thus automatically gives zext from SrcVT. 2215 2216 ISD::LoadExtType NewExtType = 2217 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2218 2219 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 2220 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2221 NVT, isVolatile, Alignment); 2222 2223 Ch = Result.getValue(1); // The chain. 2224 2225 if (ExtType == ISD::SEXTLOAD) 2226 // Having the top bits zero doesn't help when sign extending. 2227 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 2228 Result.getValueType(), 2229 Result, DAG.getValueType(SrcVT)); 2230 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2231 // All the top bits are guaranteed to be zero - inform the optimizers. 2232 Result = DAG.getNode(ISD::AssertZext, dl, 2233 Result.getValueType(), Result, 2234 DAG.getValueType(SrcVT)); 2235 2236 Tmp1 = LegalizeOp(Result); 2237 Tmp2 = LegalizeOp(Ch); 2238 } else if (SrcWidth & (SrcWidth - 1)) { 2239 // If not loading a power-of-2 number of bits, expand as two loads. 2240 assert(SrcVT.isExtended() && !SrcVT.isVector() && 2241 "Unsupported extload!"); 2242 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2243 assert(RoundWidth < SrcWidth); 2244 unsigned ExtraWidth = SrcWidth - RoundWidth; 2245 assert(ExtraWidth < RoundWidth); 2246 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2247 "Load size not an integral number of bytes!"); 2248 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2249 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2250 SDValue Lo, Hi, Ch; 2251 unsigned IncrementSize; 2252 2253 if (TLI.isLittleEndian()) { 2254 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2255 // Load the bottom RoundWidth bits. 2256 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 2257 Node->getValueType(0), Tmp1, Tmp2, 2258 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2259 Alignment); 2260 2261 // Load the remaining ExtraWidth bits. 2262 IncrementSize = RoundWidth / 8; 2263 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 2264 DAG.getIntPtrConstant(IncrementSize)); 2265 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 2266 LD->getSrcValue(), SVOffset + IncrementSize, 2267 ExtraVT, isVolatile, 2268 MinAlign(Alignment, IncrementSize)); 2269 2270 // Build a factor node to remember that this load is independent of the 2271 // other one. 2272 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 2273 Hi.getValue(1)); 2274 2275 // Move the top bits to the right place. 2276 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 2277 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2278 2279 // Join the hi and lo parts. 2280 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 2281 } else { 2282 // Big endian - avoid unaligned loads. 2283 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2284 // Load the top RoundWidth bits. 2285 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 2286 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2287 Alignment); 2288 2289 // Load the remaining ExtraWidth bits. 2290 IncrementSize = RoundWidth / 8; 2291 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 2292 DAG.getIntPtrConstant(IncrementSize)); 2293 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 2294 Node->getValueType(0), Tmp1, Tmp2, 2295 LD->getSrcValue(), SVOffset + IncrementSize, 2296 ExtraVT, isVolatile, 2297 MinAlign(Alignment, IncrementSize)); 2298 2299 // Build a factor node to remember that this load is independent of the 2300 // other one. 2301 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 2302 Hi.getValue(1)); 2303 2304 // Move the top bits to the right place. 2305 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 2306 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2307 2308 // Join the hi and lo parts. 2309 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 2310 } 2311 2312 Tmp1 = LegalizeOp(Result); 2313 Tmp2 = LegalizeOp(Ch); 2314 } else { 2315 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 2316 default: assert(0 && "This action is not supported yet!"); 2317 case TargetLowering::Custom: 2318 isCustom = true; 2319 // FALLTHROUGH 2320 case TargetLowering::Legal: 2321 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2322 Tmp1 = Result.getValue(0); 2323 Tmp2 = Result.getValue(1); 2324 2325 if (isCustom) { 2326 Tmp3 = TLI.LowerOperation(Result, DAG); 2327 if (Tmp3.getNode()) { 2328 Tmp1 = LegalizeOp(Tmp3); 2329 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2330 } 2331 } else { 2332 // If this is an unaligned load and the target doesn't support it, 2333 // expand it. 2334 if (!TLI.allowsUnalignedMemoryAccesses()) { 2335 unsigned ABIAlignment = TLI.getTargetData()-> 2336 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2337 if (LD->getAlignment() < ABIAlignment){ 2338 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 2339 TLI); 2340 Tmp1 = Result.getOperand(0); 2341 Tmp2 = Result.getOperand(1); 2342 Tmp1 = LegalizeOp(Tmp1); 2343 Tmp2 = LegalizeOp(Tmp2); 2344 } 2345 } 2346 } 2347 break; 2348 case TargetLowering::Expand: 2349 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2350 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2351 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 2352 LD->getSrcValueOffset(), 2353 LD->isVolatile(), LD->getAlignment()); 2354 Result = DAG.getNode(ISD::FP_EXTEND, dl, 2355 Node->getValueType(0), Load); 2356 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2357 Tmp2 = LegalizeOp(Load.getValue(1)); 2358 break; 2359 } 2360 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2361 // Turn the unsupported load into an EXTLOAD followed by an explicit 2362 // zero/sign extend inreg. 2363 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 2364 Tmp1, Tmp2, LD->getSrcValue(), 2365 LD->getSrcValueOffset(), SrcVT, 2366 LD->isVolatile(), LD->getAlignment()); 2367 SDValue ValRes; 2368 if (ExtType == ISD::SEXTLOAD) 2369 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 2370 Result.getValueType(), 2371 Result, DAG.getValueType(SrcVT)); 2372 else 2373 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 2374 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2375 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2376 break; 2377 } 2378 } 2379 2380 // Since loads produce two values, make sure to remember that we legalized 2381 // both of them. 2382 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2383 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2384 return Op.getResNo() ? Tmp2 : Tmp1; 2385 } 2386 } 2387 case ISD::EXTRACT_ELEMENT: { 2388 MVT OpTy = Node->getOperand(0).getValueType(); 2389 switch (getTypeAction(OpTy)) { 2390 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2391 case Legal: 2392 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2393 // 1 -> Hi 2394 Result = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2395 DAG.getConstant(OpTy.getSizeInBits()/2, 2396 TLI.getShiftAmountTy())); 2397 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Result); 2398 } else { 2399 // 0 -> Lo 2400 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2401 Node->getOperand(0)); 2402 } 2403 break; 2404 case Expand: 2405 // Get both the low and high parts. 2406 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2407 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) 2408 Result = Tmp2; // 1 -> Hi 2409 else 2410 Result = Tmp1; // 0 -> Lo 2411 break; 2412 } 2413 break; 2414 } 2415 2416 case ISD::CopyToReg: 2417 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2418 2419 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2420 "Register type must be legal!"); 2421 // Legalize the incoming value (must be a legal type). 2422 Tmp2 = LegalizeOp(Node->getOperand(2)); 2423 if (Node->getNumValues() == 1) { 2424 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2425 } else { 2426 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2427 if (Node->getNumOperands() == 4) { 2428 Tmp3 = LegalizeOp(Node->getOperand(3)); 2429 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2430 Tmp3); 2431 } else { 2432 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2433 } 2434 2435 // Since this produces two values, make sure to remember that we legalized 2436 // both of them. 2437 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 2438 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 2439 return Result; 2440 } 2441 break; 2442 2443 case ISD::RET: 2444 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2445 2446 // Ensure that libcalls are emitted before a return. 2447 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 2448 Tmp1 = LegalizeOp(Tmp1); 2449 LastCALLSEQ_END = DAG.getEntryNode(); 2450 2451 switch (Node->getNumOperands()) { 2452 case 3: // ret val 2453 Tmp2 = Node->getOperand(1); 2454 Tmp3 = Node->getOperand(2); // Signness 2455 switch (getTypeAction(Tmp2.getValueType())) { 2456 case Legal: 2457 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2458 break; 2459 case Expand: 2460 if (!Tmp2.getValueType().isVector()) { 2461 SDValue Lo, Hi; 2462 ExpandOp(Tmp2, Lo, Hi); 2463 2464 // Big endian systems want the hi reg first. 2465 if (TLI.isBigEndian()) 2466 std::swap(Lo, Hi); 2467 2468 if (Hi.getNode()) 2469 Result = DAG.getNode(ISD::RET, dl, MVT::Other, 2470 Tmp1, Lo, Tmp3, Hi, Tmp3); 2471 else 2472 Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3); 2473 Result = LegalizeOp(Result); 2474 } else { 2475 SDNode *InVal = Tmp2.getNode(); 2476 int InIx = Tmp2.getResNo(); 2477 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 2478 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 2479 2480 // Figure out if there is a simple type corresponding to this Vector 2481 // type. If so, convert to the vector type. 2482 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2483 if (TLI.isTypeLegal(TVT)) { 2484 // Turn this into a return of the vector type. 2485 Tmp2 = LegalizeOp(Tmp2); 2486 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2487 } else if (NumElems == 1) { 2488 // Turn this into a return of the scalar type. 2489 Tmp2 = ScalarizeVectorOp(Tmp2); 2490 Tmp2 = LegalizeOp(Tmp2); 2491 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2492 2493 // FIXME: Returns of gcc generic vectors smaller than a legal type 2494 // should be returned in integer registers! 2495 2496 // The scalarized value type may not be legal, e.g. it might require 2497 // promotion or expansion. Relegalize the return. 2498 Result = LegalizeOp(Result); 2499 } else { 2500 // FIXME: Returns of gcc generic vectors larger than a legal vector 2501 // type should be returned by reference! 2502 SDValue Lo, Hi; 2503 SplitVectorOp(Tmp2, Lo, Hi); 2504 Result = DAG.getNode(ISD::RET, dl, MVT::Other, 2505 Tmp1, Lo, Tmp3, Hi, Tmp3); 2506 Result = LegalizeOp(Result); 2507 } 2508 } 2509 break; 2510 case Promote: 2511 Tmp2 = PromoteOp(Node->getOperand(1)); 2512 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2513 Result = LegalizeOp(Result); 2514 break; 2515 } 2516 break; 2517 case 1: // ret void 2518 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2519 break; 2520 default: { // ret <values> 2521 SmallVector<SDValue, 8> NewValues; 2522 NewValues.push_back(Tmp1); 2523 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2524 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2525 case Legal: 2526 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2527 NewValues.push_back(Node->getOperand(i+1)); 2528 break; 2529 case Expand: { 2530 SDValue Lo, Hi; 2531 assert(!Node->getOperand(i).getValueType().isExtended() && 2532 "FIXME: TODO: implement returning non-legal vector types!"); 2533 ExpandOp(Node->getOperand(i), Lo, Hi); 2534 NewValues.push_back(Lo); 2535 NewValues.push_back(Node->getOperand(i+1)); 2536 if (Hi.getNode()) { 2537 NewValues.push_back(Hi); 2538 NewValues.push_back(Node->getOperand(i+1)); 2539 } 2540 break; 2541 } 2542 case Promote: 2543 assert(0 && "Can't promote multiple return value yet!"); 2544 } 2545 2546 if (NewValues.size() == Node->getNumOperands()) 2547 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2548 else 2549 Result = DAG.getNode(ISD::RET, dl, MVT::Other, 2550 &NewValues[0], NewValues.size()); 2551 break; 2552 } 2553 } 2554 2555 if (Result.getOpcode() == ISD::RET) { 2556 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2557 default: assert(0 && "This action is not supported yet!"); 2558 case TargetLowering::Legal: break; 2559 case TargetLowering::Custom: 2560 Tmp1 = TLI.LowerOperation(Result, DAG); 2561 if (Tmp1.getNode()) Result = Tmp1; 2562 break; 2563 } 2564 } 2565 break; 2566 case ISD::STORE: { 2567 StoreSDNode *ST = cast<StoreSDNode>(Node); 2568 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2569 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2570 int SVOffset = ST->getSrcValueOffset(); 2571 unsigned Alignment = ST->getAlignment(); 2572 bool isVolatile = ST->isVolatile(); 2573 2574 if (!ST->isTruncatingStore()) { 2575 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2576 // FIXME: We shouldn't do this for TargetConstantFP's. 2577 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2578 // to phase ordering between legalized code and the dag combiner. This 2579 // probably means that we need to integrate dag combiner and legalizer 2580 // together. 2581 // We generally can't do this one for long doubles. 2582 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2583 if (CFP->getValueType(0) == MVT::f32 && 2584 getTypeAction(MVT::i32) == Legal) { 2585 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2586 bitcastToAPInt().zextOrTrunc(32), 2587 MVT::i32); 2588 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2589 SVOffset, isVolatile, Alignment); 2590 break; 2591 } else if (CFP->getValueType(0) == MVT::f64) { 2592 // If this target supports 64-bit registers, do a single 64-bit store. 2593 if (getTypeAction(MVT::i64) == Legal) { 2594 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 2595 zextOrTrunc(64), MVT::i64); 2596 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2597 SVOffset, isVolatile, Alignment); 2598 break; 2599 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 2600 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2601 // stores. If the target supports neither 32- nor 64-bits, this 2602 // xform is certainly not worth it. 2603 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 2604 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2605 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2606 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2607 2608 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 2609 SVOffset, isVolatile, Alignment); 2610 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 2611 DAG.getIntPtrConstant(4)); 2612 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2613 isVolatile, MinAlign(Alignment, 4U)); 2614 2615 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2616 break; 2617 } 2618 } 2619 } 2620 2621 switch (getTypeAction(ST->getMemoryVT())) { 2622 case Legal: { 2623 Tmp3 = LegalizeOp(ST->getValue()); 2624 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2625 ST->getOffset()); 2626 2627 MVT VT = Tmp3.getValueType(); 2628 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2629 default: assert(0 && "This action is not supported yet!"); 2630 case TargetLowering::Legal: 2631 // If this is an unaligned store and the target doesn't support it, 2632 // expand it. 2633 if (!TLI.allowsUnalignedMemoryAccesses()) { 2634 unsigned ABIAlignment = TLI.getTargetData()-> 2635 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2636 if (ST->getAlignment() < ABIAlignment) 2637 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 2638 TLI); 2639 } 2640 break; 2641 case TargetLowering::Custom: 2642 Tmp1 = TLI.LowerOperation(Result, DAG); 2643 if (Tmp1.getNode()) Result = Tmp1; 2644 break; 2645 case TargetLowering::Promote: 2646 assert(VT.isVector() && "Unknown legal promote case!"); 2647 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 2648 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2649 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 2650 ST->getSrcValue(), SVOffset, isVolatile, 2651 Alignment); 2652 break; 2653 } 2654 break; 2655 } 2656 case Promote: 2657 if (!ST->getMemoryVT().isVector()) { 2658 // Truncate the value and store the result. 2659 Tmp3 = PromoteOp(ST->getValue()); 2660 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2661 SVOffset, ST->getMemoryVT(), 2662 isVolatile, Alignment); 2663 break; 2664 } 2665 // Fall thru to expand for vector 2666 case Expand: { 2667 unsigned IncrementSize = 0; 2668 SDValue Lo, Hi; 2669 2670 // If this is a vector type, then we have to calculate the increment as 2671 // the product of the element size in bytes, and the number of elements 2672 // in the high half of the vector. 2673 if (ST->getValue().getValueType().isVector()) { 2674 SDNode *InVal = ST->getValue().getNode(); 2675 int InIx = ST->getValue().getResNo(); 2676 MVT InVT = InVal->getValueType(InIx); 2677 unsigned NumElems = InVT.getVectorNumElements(); 2678 MVT EVT = InVT.getVectorElementType(); 2679 2680 // Figure out if there is a simple type corresponding to this Vector 2681 // type. If so, convert to the vector type. 2682 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2683 if (TLI.isTypeLegal(TVT)) { 2684 // Turn this into a normal store of the vector type. 2685 Tmp3 = LegalizeOp(ST->getValue()); 2686 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2687 SVOffset, isVolatile, Alignment); 2688 Result = LegalizeOp(Result); 2689 break; 2690 } else if (NumElems == 1) { 2691 // Turn this into a normal store of the scalar type. 2692 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2693 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2694 SVOffset, isVolatile, Alignment); 2695 // The scalarized value type may not be legal, e.g. it might require 2696 // promotion or expansion. Relegalize the scalar store. 2697 Result = LegalizeOp(Result); 2698 break; 2699 } else { 2700 // Check if we have widen this node with another value 2701 std::map<SDValue, SDValue>::iterator I = 2702 WidenNodes.find(ST->getValue()); 2703 if (I != WidenNodes.end()) { 2704 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2); 2705 break; 2706 } 2707 else { 2708 SplitVectorOp(ST->getValue(), Lo, Hi); 2709 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() * 2710 EVT.getSizeInBits()/8; 2711 } 2712 } 2713 } else { 2714 ExpandOp(ST->getValue(), Lo, Hi); 2715 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0; 2716 2717 if (Hi.getNode() && TLI.isBigEndian()) 2718 std::swap(Lo, Hi); 2719 } 2720 2721 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 2722 SVOffset, isVolatile, Alignment); 2723 2724 if (Hi.getNode() == NULL) { 2725 // Must be int <-> float one-to-one expansion. 2726 Result = Lo; 2727 break; 2728 } 2729 2730 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 2731 DAG.getIntPtrConstant(IncrementSize)); 2732 assert(isTypeLegal(Tmp2.getValueType()) && 2733 "Pointers must be legal!"); 2734 SVOffset += IncrementSize; 2735 Alignment = MinAlign(Alignment, IncrementSize); 2736 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 2737 SVOffset, isVolatile, Alignment); 2738 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2739 break; 2740 } // case Expand 2741 } 2742 } else { 2743 switch (getTypeAction(ST->getValue().getValueType())) { 2744 case Legal: 2745 Tmp3 = LegalizeOp(ST->getValue()); 2746 break; 2747 case Promote: 2748 if (!ST->getValue().getValueType().isVector()) { 2749 // We can promote the value, the truncstore will still take care of it. 2750 Tmp3 = PromoteOp(ST->getValue()); 2751 break; 2752 } 2753 // Vector case falls through to expand 2754 case Expand: 2755 // Just store the low part. This may become a non-trunc store, so make 2756 // sure to use getTruncStore, not UpdateNodeOperands below. 2757 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2758 return DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2759 SVOffset, MVT::i8, isVolatile, Alignment); 2760 } 2761 2762 MVT StVT = ST->getMemoryVT(); 2763 unsigned StWidth = StVT.getSizeInBits(); 2764 2765 if (StWidth != StVT.getStoreSizeInBits()) { 2766 // Promote to a byte-sized store with upper bits zero if not 2767 // storing an integral number of bytes. For example, promote 2768 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2769 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 2770 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 2771 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2772 SVOffset, NVT, isVolatile, Alignment); 2773 } else if (StWidth & (StWidth - 1)) { 2774 // If not storing a power-of-2 number of bits, expand as two stores. 2775 assert(StVT.isExtended() && !StVT.isVector() && 2776 "Unsupported truncstore!"); 2777 unsigned RoundWidth = 1 << Log2_32(StWidth); 2778 assert(RoundWidth < StWidth); 2779 unsigned ExtraWidth = StWidth - RoundWidth; 2780 assert(ExtraWidth < RoundWidth); 2781 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2782 "Store size not an integral number of bytes!"); 2783 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2784 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2785 SDValue Lo, Hi; 2786 unsigned IncrementSize; 2787 2788 if (TLI.isLittleEndian()) { 2789 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2790 // Store the bottom RoundWidth bits. 2791 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2792 SVOffset, RoundVT, 2793 isVolatile, Alignment); 2794 2795 // Store the remaining ExtraWidth bits. 2796 IncrementSize = RoundWidth / 8; 2797 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 2798 DAG.getIntPtrConstant(IncrementSize)); 2799 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 2800 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2801 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 2802 SVOffset + IncrementSize, ExtraVT, isVolatile, 2803 MinAlign(Alignment, IncrementSize)); 2804 } else { 2805 // Big endian - avoid unaligned stores. 2806 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2807 // Store the top RoundWidth bits. 2808 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 2809 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2810 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 2811 SVOffset, RoundVT, isVolatile, Alignment); 2812 2813 // Store the remaining ExtraWidth bits. 2814 IncrementSize = RoundWidth / 8; 2815 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 2816 DAG.getIntPtrConstant(IncrementSize)); 2817 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2818 SVOffset + IncrementSize, ExtraVT, isVolatile, 2819 MinAlign(Alignment, IncrementSize)); 2820 } 2821 2822 // The order of the stores doesn't matter. 2823 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2824 } else { 2825 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2826 Tmp2 != ST->getBasePtr()) 2827 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2828 ST->getOffset()); 2829 2830 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2831 default: assert(0 && "This action is not supported yet!"); 2832 case TargetLowering::Legal: 2833 // If this is an unaligned store and the target doesn't support it, 2834 // expand it. 2835 if (!TLI.allowsUnalignedMemoryAccesses()) { 2836 unsigned ABIAlignment = TLI.getTargetData()-> 2837 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2838 if (ST->getAlignment() < ABIAlignment) 2839 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 2840 TLI); 2841 } 2842 break; 2843 case TargetLowering::Custom: 2844 Result = TLI.LowerOperation(Result, DAG); 2845 break; 2846 case Expand: 2847 // TRUNCSTORE:i16 i32 -> STORE i16 2848 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2849 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 2850 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 2851 SVOffset, isVolatile, Alignment); 2852 break; 2853 } 2854 } 2855 } 2856 break; 2857 } 2858 case ISD::PCMARKER: 2859 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2860 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2861 break; 2862 case ISD::STACKSAVE: 2863 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2864 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2865 Tmp1 = Result.getValue(0); 2866 Tmp2 = Result.getValue(1); 2867 2868 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2869 default: assert(0 && "This action is not supported yet!"); 2870 case TargetLowering::Legal: break; 2871 case TargetLowering::Custom: 2872 Tmp3 = TLI.LowerOperation(Result, DAG); 2873 if (Tmp3.getNode()) { 2874 Tmp1 = LegalizeOp(Tmp3); 2875 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2876 } 2877 break; 2878 case TargetLowering::Expand: 2879 // Expand to CopyFromReg if the target set 2880 // StackPointerRegisterToSaveRestore. 2881 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2882 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP, 2883 Node->getValueType(0)); 2884 Tmp2 = Tmp1.getValue(1); 2885 } else { 2886 Tmp1 = DAG.getUNDEF(Node->getValueType(0)); 2887 Tmp2 = Node->getOperand(0); 2888 } 2889 break; 2890 } 2891 2892 // Since stacksave produce two values, make sure to remember that we 2893 // legalized both of them. 2894 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2895 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2896 return Op.getResNo() ? Tmp2 : Tmp1; 2897 2898 case ISD::STACKRESTORE: 2899 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2900 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2901 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2902 2903 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2904 default: assert(0 && "This action is not supported yet!"); 2905 case TargetLowering::Legal: break; 2906 case TargetLowering::Custom: 2907 Tmp1 = TLI.LowerOperation(Result, DAG); 2908 if (Tmp1.getNode()) Result = Tmp1; 2909 break; 2910 case TargetLowering::Expand: 2911 // Expand to CopyToReg if the target set 2912 // StackPointerRegisterToSaveRestore. 2913 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2914 Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2); 2915 } else { 2916 Result = Tmp1; 2917 } 2918 break; 2919 } 2920 break; 2921 2922 case ISD::READCYCLECOUNTER: 2923 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2924 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2925 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2926 Node->getValueType(0))) { 2927 default: assert(0 && "This action is not supported yet!"); 2928 case TargetLowering::Legal: 2929 Tmp1 = Result.getValue(0); 2930 Tmp2 = Result.getValue(1); 2931 break; 2932 case TargetLowering::Custom: 2933 Result = TLI.LowerOperation(Result, DAG); 2934 Tmp1 = LegalizeOp(Result.getValue(0)); 2935 Tmp2 = LegalizeOp(Result.getValue(1)); 2936 break; 2937 } 2938 2939 // Since rdcc produce two values, make sure to remember that we legalized 2940 // both of them. 2941 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2942 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2943 return Result; 2944 2945 case ISD::SELECT: 2946 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2947 case Expand: assert(0 && "It's impossible to expand bools"); 2948 case Legal: 2949 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2950 break; 2951 case Promote: { 2952 assert(!Node->getOperand(0).getValueType().isVector() && "not possible"); 2953 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2954 // Make sure the condition is either zero or one. 2955 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2956 if (!DAG.MaskedValueIsZero(Tmp1, 2957 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2958 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, MVT::i1); 2959 break; 2960 } 2961 } 2962 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2963 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2964 2965 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2966 2967 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2968 default: assert(0 && "This action is not supported yet!"); 2969 case TargetLowering::Legal: break; 2970 case TargetLowering::Custom: { 2971 Tmp1 = TLI.LowerOperation(Result, DAG); 2972 if (Tmp1.getNode()) Result = Tmp1; 2973 break; 2974 } 2975 case TargetLowering::Expand: 2976 if (Tmp1.getOpcode() == ISD::SETCC) { 2977 Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 2978 Tmp2, Tmp3, 2979 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2980 } else { 2981 Result = DAG.getSelectCC(dl, Tmp1, 2982 DAG.getConstant(0, Tmp1.getValueType()), 2983 Tmp2, Tmp3, ISD::SETNE); 2984 } 2985 break; 2986 case TargetLowering::Promote: { 2987 MVT NVT = 2988 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2989 unsigned ExtOp, TruncOp; 2990 if (Tmp2.getValueType().isVector()) { 2991 ExtOp = ISD::BIT_CONVERT; 2992 TruncOp = ISD::BIT_CONVERT; 2993 } else if (Tmp2.getValueType().isInteger()) { 2994 ExtOp = ISD::ANY_EXTEND; 2995 TruncOp = ISD::TRUNCATE; 2996 } else { 2997 ExtOp = ISD::FP_EXTEND; 2998 TruncOp = ISD::FP_ROUND; 2999 } 3000 // Promote each of the values to the new type. 3001 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2); 3002 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3); 3003 // Perform the larger operation, then round down. 3004 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3005 if (TruncOp != ISD::FP_ROUND) 3006 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result); 3007 else 3008 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result, 3009 DAG.getIntPtrConstant(0)); 3010 break; 3011 } 3012 } 3013 break; 3014 case ISD::SELECT_CC: { 3015 Tmp1 = Node->getOperand(0); // LHS 3016 Tmp2 = Node->getOperand(1); // RHS 3017 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 3018 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 3019 SDValue CC = Node->getOperand(4); 3020 3021 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), 3022 Tmp1, Tmp2, CC, dl); 3023 3024 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 3025 // the LHS is a legal SETCC itself. In this case, we need to compare 3026 // the result against zero to select between true and false values. 3027 if (Tmp2.getNode() == 0) { 3028 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3029 CC = DAG.getCondCode(ISD::SETNE); 3030 } 3031 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 3032 3033 // Everything is legal, see if we should expand this op or something. 3034 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 3035 default: assert(0 && "This action is not supported yet!"); 3036 case TargetLowering::Legal: break; 3037 case TargetLowering::Custom: 3038 Tmp1 = TLI.LowerOperation(Result, DAG); 3039 if (Tmp1.getNode()) Result = Tmp1; 3040 break; 3041 } 3042 break; 3043 } 3044 case ISD::SETCC: 3045 Tmp1 = Node->getOperand(0); 3046 Tmp2 = Node->getOperand(1); 3047 Tmp3 = Node->getOperand(2); 3048 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 3049 3050 // If we had to Expand the SetCC operands into a SELECT node, then it may 3051 // not always be possible to return a true LHS & RHS. In this case, just 3052 // return the value we legalized, returned in the LHS 3053 if (Tmp2.getNode() == 0) { 3054 Result = Tmp1; 3055 break; 3056 } 3057 3058 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 3059 default: assert(0 && "Cannot handle this action for SETCC yet!"); 3060 case TargetLowering::Custom: 3061 isCustom = true; 3062 // FALLTHROUGH. 3063 case TargetLowering::Legal: 3064 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3065 if (isCustom) { 3066 Tmp4 = TLI.LowerOperation(Result, DAG); 3067 if (Tmp4.getNode()) Result = Tmp4; 3068 } 3069 break; 3070 case TargetLowering::Promote: { 3071 // First step, figure out the appropriate operation to use. 3072 // Allow SETCC to not be supported for all legal data types 3073 // Mostly this targets FP 3074 MVT NewInTy = Node->getOperand(0).getValueType(); 3075 MVT OldVT = NewInTy; OldVT = OldVT; 3076 3077 // Scan for the appropriate larger type to use. 3078 while (1) { 3079 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 3080 3081 assert(NewInTy.isInteger() == OldVT.isInteger() && 3082 "Fell off of the edge of the integer world"); 3083 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 3084 "Fell off of the edge of the floating point world"); 3085 3086 // If the target supports SETCC of this type, use it. 3087 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy)) 3088 break; 3089 } 3090 if (NewInTy.isInteger()) 3091 assert(0 && "Cannot promote Legal Integer SETCC yet"); 3092 else { 3093 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1); 3094 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2); 3095 } 3096 Tmp1 = LegalizeOp(Tmp1); 3097 Tmp2 = LegalizeOp(Tmp2); 3098 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3099 Result = LegalizeOp(Result); 3100 break; 3101 } 3102 case TargetLowering::Expand: 3103 // Expand a setcc node into a select_cc of the same condition, lhs, and 3104 // rhs that selects between const 1 (true) and const 0 (false). 3105 MVT VT = Node->getValueType(0); 3106 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3107 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3108 Tmp3); 3109 break; 3110 } 3111 break; 3112 case ISD::VSETCC: { 3113 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3114 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3115 SDValue CC = Node->getOperand(2); 3116 3117 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC); 3118 3119 // Everything is legal, see if we should expand this op or something. 3120 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) { 3121 default: assert(0 && "This action is not supported yet!"); 3122 case TargetLowering::Legal: break; 3123 case TargetLowering::Custom: 3124 Tmp1 = TLI.LowerOperation(Result, DAG); 3125 if (Tmp1.getNode()) Result = Tmp1; 3126 break; 3127 case TargetLowering::Expand: { 3128 // Unroll into a nasty set of scalar code for now. 3129 MVT VT = Node->getValueType(0); 3130 unsigned NumElems = VT.getVectorNumElements(); 3131 MVT EltVT = VT.getVectorElementType(); 3132 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType(); 3133 SmallVector<SDValue, 8> Ops(NumElems); 3134 for (unsigned i = 0; i < NumElems; ++i) { 3135 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, 3136 Tmp1, DAG.getIntPtrConstant(i)); 3137 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT), 3138 In1, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 3139 TmpEltVT, Tmp2, 3140 DAG.getIntPtrConstant(i)), 3141 CC); 3142 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], 3143 DAG.getConstant(APInt::getAllOnesValue 3144 (EltVT.getSizeInBits()), EltVT), 3145 DAG.getConstant(0, EltVT)); 3146 } 3147 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems); 3148 break; 3149 } 3150 } 3151 break; 3152 } 3153 3154 case ISD::SHL_PARTS: 3155 case ISD::SRA_PARTS: 3156 case ISD::SRL_PARTS: { 3157 SmallVector<SDValue, 8> Ops; 3158 bool Changed = false; 3159 unsigned N = Node->getNumOperands(); 3160 for (unsigned i = 0; i + 1 < N; ++i) { 3161 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3162 Changed |= Ops.back() != Node->getOperand(i); 3163 } 3164 Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1)))); 3165 Changed |= Ops.back() != Node->getOperand(N-1); 3166 if (Changed) 3167 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 3168 3169 switch (TLI.getOperationAction(Node->getOpcode(), 3170 Node->getValueType(0))) { 3171 default: assert(0 && "This action is not supported yet!"); 3172 case TargetLowering::Legal: break; 3173 case TargetLowering::Custom: 3174 Tmp1 = TLI.LowerOperation(Result, DAG); 3175 if (Tmp1.getNode()) { 3176 SDValue Tmp2, RetVal(0, 0); 3177 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 3178 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 3179 AddLegalizedOperand(SDValue(Node, i), Tmp2); 3180 if (i == Op.getResNo()) 3181 RetVal = Tmp2; 3182 } 3183 assert(RetVal.getNode() && "Illegal result number"); 3184 return RetVal; 3185 } 3186 break; 3187 } 3188 3189 // Since these produce multiple values, make sure to remember that we 3190 // legalized all of them. 3191 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3192 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i)); 3193 return Result.getValue(Op.getResNo()); 3194 } 3195 3196 // Binary operators 3197 case ISD::ADD: 3198 case ISD::SUB: 3199 case ISD::MUL: 3200 case ISD::MULHS: 3201 case ISD::MULHU: 3202 case ISD::UDIV: 3203 case ISD::SDIV: 3204 case ISD::AND: 3205 case ISD::OR: 3206 case ISD::XOR: 3207 case ISD::SHL: 3208 case ISD::SRL: 3209 case ISD::SRA: 3210 case ISD::FADD: 3211 case ISD::FSUB: 3212 case ISD::FMUL: 3213 case ISD::FDIV: 3214 case ISD::FPOW: 3215 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3216 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3217 3218 if ((Node->getOpcode() == ISD::SHL || 3219 Node->getOpcode() == ISD::SRL || 3220 Node->getOpcode() == ISD::SRA) && 3221 !Node->getValueType(0).isVector()) 3222 Tmp2 = DAG.getShiftAmountOperand(Tmp2); 3223 3224 switch (getTypeAction(Tmp2.getValueType())) { 3225 case Expand: assert(0 && "Not possible"); 3226 case Legal: 3227 Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS. 3228 break; 3229 case Promote: 3230 Tmp2 = PromoteOp(Tmp2); // Promote the RHS. 3231 break; 3232 } 3233 3234 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3235 3236 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3237 default: assert(0 && "BinOp legalize operation not supported"); 3238 case TargetLowering::Legal: break; 3239 case TargetLowering::Custom: 3240 Tmp1 = TLI.LowerOperation(Result, DAG); 3241 if (Tmp1.getNode()) { 3242 Result = Tmp1; 3243 break; 3244 } 3245 // Fall through if the custom lower can't deal with the operation 3246 case TargetLowering::Expand: { 3247 MVT VT = Op.getValueType(); 3248 3249 // See if multiply or divide can be lowered using two-result operations. 3250 SDVTList VTs = DAG.getVTList(VT, VT); 3251 if (Node->getOpcode() == ISD::MUL) { 3252 // We just need the low half of the multiply; try both the signed 3253 // and unsigned forms. If the target supports both SMUL_LOHI and 3254 // UMUL_LOHI, form a preference by checking which forms of plain 3255 // MULH it supports. 3256 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 3257 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 3258 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 3259 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 3260 unsigned OpToUse = 0; 3261 if (HasSMUL_LOHI && !HasMULHS) { 3262 OpToUse = ISD::SMUL_LOHI; 3263 } else if (HasUMUL_LOHI && !HasMULHU) { 3264 OpToUse = ISD::UMUL_LOHI; 3265 } else if (HasSMUL_LOHI) { 3266 OpToUse = ISD::SMUL_LOHI; 3267 } else if (HasUMUL_LOHI) { 3268 OpToUse = ISD::UMUL_LOHI; 3269 } 3270 if (OpToUse) { 3271 Result = DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2); 3272 break; 3273 } 3274 } 3275 if (Node->getOpcode() == ISD::MULHS && 3276 TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) { 3277 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, 3278 VTs, Tmp1, Tmp2).getNode(), 3279 1); 3280 break; 3281 } 3282 if (Node->getOpcode() == ISD::MULHU && 3283 TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) { 3284 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, 3285 VTs, Tmp1, Tmp2).getNode(), 3286 1); 3287 break; 3288 } 3289 if (Node->getOpcode() == ISD::SDIV && 3290 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) { 3291 Result = DAG.getNode(ISD::SDIVREM, dl, VTs, Tmp1, Tmp2); 3292 break; 3293 } 3294 if (Node->getOpcode() == ISD::UDIV && 3295 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) { 3296 Result = DAG.getNode(ISD::UDIVREM, dl, VTs, Tmp1, Tmp2); 3297 break; 3298 } 3299 if (Node->getOpcode() == ISD::SUB && 3300 TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 3301 TLI.isOperationLegalOrCustom(ISD::XOR, VT)) { 3302 Tmp2 = DAG.getNode(ISD::XOR, dl, VT, Tmp2, 3303 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 3304 Tmp2 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 3305 Result = DAG.getNode(ISD::ADD, dl, VT, Tmp1, Tmp2); 3306 break; 3307 } 3308 3309 // Check to see if we have a libcall for this operator. 3310 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3311 bool isSigned = false; 3312 switch (Node->getOpcode()) { 3313 case ISD::UDIV: 3314 case ISD::SDIV: 3315 isSigned = Node->getOpcode() == ISD::SDIV; 3316 if (VT == MVT::i16) 3317 LC = (isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16); 3318 else if (VT == MVT::i32) 3319 LC = (isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32); 3320 else if (VT == MVT::i64) 3321 LC = (isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64); 3322 else if (VT == MVT::i128) 3323 LC = (isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128); 3324 break; 3325 case ISD::MUL: 3326 if (VT == MVT::i16) 3327 LC = RTLIB::MUL_I16; 3328 else if (VT == MVT::i32) 3329 LC = RTLIB::MUL_I32; 3330 else if (VT == MVT::i64) 3331 LC = RTLIB::MUL_I64; 3332 else if (VT == MVT::i128) 3333 LC = RTLIB::MUL_I128; 3334 break; 3335 case ISD::FPOW: 3336 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3337 RTLIB::POW_PPCF128); 3338 break; 3339 case ISD::FDIV: 3340 LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80, 3341 RTLIB::DIV_PPCF128); 3342 break; 3343 default: break; 3344 } 3345 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3346 SDValue Dummy; 3347 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3348 break; 3349 } 3350 3351 assert(Node->getValueType(0).isVector() && 3352 "Cannot expand this binary operator!"); 3353 // Expand the operation into a bunch of nasty scalar code. 3354 Result = LegalizeOp(UnrollVectorOp(Op)); 3355 break; 3356 } 3357 case TargetLowering::Promote: { 3358 switch (Node->getOpcode()) { 3359 default: assert(0 && "Do not know how to promote this BinOp!"); 3360 case ISD::AND: 3361 case ISD::OR: 3362 case ISD::XOR: { 3363 MVT OVT = Node->getValueType(0); 3364 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3365 assert(OVT.isVector() && "Cannot promote this BinOp!"); 3366 // Bit convert each of the values to the new type. 3367 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1); 3368 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2); 3369 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3370 // Bit convert the result back the original type. 3371 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result); 3372 break; 3373 } 3374 } 3375 } 3376 } 3377 break; 3378 3379 case ISD::SMUL_LOHI: 3380 case ISD::UMUL_LOHI: 3381 case ISD::SDIVREM: 3382 case ISD::UDIVREM: 3383 // These nodes will only be produced by target-specific lowering, so 3384 // they shouldn't be here if they aren't legal. 3385 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3386 "This must be legal!"); 3387 3388 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3389 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3390 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3391 break; 3392 3393 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3394 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3395 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3396 case Expand: assert(0 && "Not possible"); 3397 case Legal: 3398 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3399 break; 3400 case Promote: 3401 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3402 break; 3403 } 3404 3405 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3406 3407 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3408 default: assert(0 && "Operation not supported"); 3409 case TargetLowering::Custom: 3410 Tmp1 = TLI.LowerOperation(Result, DAG); 3411 if (Tmp1.getNode()) Result = Tmp1; 3412 break; 3413 case TargetLowering::Legal: break; 3414 case TargetLowering::Expand: { 3415 // If this target supports fabs/fneg natively and select is cheap, 3416 // do this efficiently. 3417 if (!TLI.isSelectExpensive() && 3418 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3419 TargetLowering::Legal && 3420 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3421 TargetLowering::Legal) { 3422 // Get the sign bit of the RHS. 3423 MVT IVT = 3424 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3425 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 3426 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(IVT), 3427 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3428 // Get the absolute value of the result. 3429 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 3430 // Select between the nabs and abs value based on the sign bit of 3431 // the input. 3432 Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 3433 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), 3434 AbsVal), 3435 AbsVal); 3436 Result = LegalizeOp(Result); 3437 break; 3438 } 3439 3440 // Otherwise, do bitwise ops! 3441 MVT NVT = 3442 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3443 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3444 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Result); 3445 Result = LegalizeOp(Result); 3446 break; 3447 } 3448 } 3449 break; 3450 3451 case ISD::ADDC: 3452 case ISD::SUBC: 3453 Tmp1 = LegalizeOp(Node->getOperand(0)); 3454 Tmp2 = LegalizeOp(Node->getOperand(1)); 3455 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3456 Tmp3 = Result.getValue(0); 3457 Tmp4 = Result.getValue(1); 3458 3459 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3460 default: assert(0 && "This action is not supported yet!"); 3461 case TargetLowering::Legal: 3462 break; 3463 case TargetLowering::Custom: 3464 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 3465 if (Tmp1.getNode() != NULL) { 3466 Tmp3 = LegalizeOp(Tmp1); 3467 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 3468 } 3469 break; 3470 } 3471 // Since this produces two values, make sure to remember that we legalized 3472 // both of them. 3473 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 3474 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 3475 return Op.getResNo() ? Tmp4 : Tmp3; 3476 3477 case ISD::ADDE: 3478 case ISD::SUBE: 3479 Tmp1 = LegalizeOp(Node->getOperand(0)); 3480 Tmp2 = LegalizeOp(Node->getOperand(1)); 3481 Tmp3 = LegalizeOp(Node->getOperand(2)); 3482 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3483 Tmp3 = Result.getValue(0); 3484 Tmp4 = Result.getValue(1); 3485 3486 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3487 default: assert(0 && "This action is not supported yet!"); 3488 case TargetLowering::Legal: 3489 break; 3490 case TargetLowering::Custom: 3491 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 3492 if (Tmp1.getNode() != NULL) { 3493 Tmp3 = LegalizeOp(Tmp1); 3494 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 3495 } 3496 break; 3497 } 3498 // Since this produces two values, make sure to remember that we legalized 3499 // both of them. 3500 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 3501 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 3502 return Op.getResNo() ? Tmp4 : Tmp3; 3503 3504 case ISD::BUILD_PAIR: { 3505 MVT PairTy = Node->getValueType(0); 3506 // TODO: handle the case where the Lo and Hi operands are not of legal type 3507 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3508 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3509 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3510 case TargetLowering::Promote: 3511 case TargetLowering::Custom: 3512 assert(0 && "Cannot promote/custom this yet!"); 3513 case TargetLowering::Legal: 3514 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3515 Result = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Tmp1, Tmp2); 3516 break; 3517 case TargetLowering::Expand: 3518 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Tmp1); 3519 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Tmp2); 3520 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 3521 DAG.getConstant(PairTy.getSizeInBits()/2, 3522 TLI.getShiftAmountTy())); 3523 Result = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2); 3524 break; 3525 } 3526 break; 3527 } 3528 3529 case ISD::UREM: 3530 case ISD::SREM: 3531 case ISD::FREM: 3532 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3533 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3534 3535 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3536 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3537 case TargetLowering::Custom: 3538 isCustom = true; 3539 // FALLTHROUGH 3540 case TargetLowering::Legal: 3541 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3542 if (isCustom) { 3543 Tmp1 = TLI.LowerOperation(Result, DAG); 3544 if (Tmp1.getNode()) Result = Tmp1; 3545 } 3546 break; 3547 case TargetLowering::Expand: { 3548 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3549 bool isSigned = DivOpc == ISD::SDIV; 3550 MVT VT = Node->getValueType(0); 3551 3552 // See if remainder can be lowered using two-result operations. 3553 SDVTList VTs = DAG.getVTList(VT, VT); 3554 if (Node->getOpcode() == ISD::SREM && 3555 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) { 3556 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl, 3557 VTs, Tmp1, Tmp2).getNode(), 1); 3558 break; 3559 } 3560 if (Node->getOpcode() == ISD::UREM && 3561 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) { 3562 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl, 3563 VTs, Tmp1, Tmp2).getNode(), 1); 3564 break; 3565 } 3566 3567 if (VT.isInteger()) { 3568 if (TLI.getOperationAction(DivOpc, VT) == 3569 TargetLowering::Legal) { 3570 // X % Y -> X-X/Y*Y 3571 Result = DAG.getNode(DivOpc, dl, VT, Tmp1, Tmp2); 3572 Result = DAG.getNode(ISD::MUL, dl, VT, Result, Tmp2); 3573 Result = DAG.getNode(ISD::SUB, dl, VT, Tmp1, Result); 3574 } else if (VT.isVector()) { 3575 Result = LegalizeOp(UnrollVectorOp(Op)); 3576 } else { 3577 assert(VT == MVT::i32 && 3578 "Cannot expand this binary operator!"); 3579 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3580 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3581 SDValue Dummy; 3582 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3583 } 3584 } else { 3585 assert(VT.isFloatingPoint() && 3586 "remainder op must have integer or floating-point type"); 3587 if (VT.isVector()) { 3588 Result = LegalizeOp(UnrollVectorOp(Op)); 3589 } else { 3590 // Floating point mod -> fmod libcall. 3591 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3592 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3593 SDValue Dummy; 3594 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3595 } 3596 } 3597 break; 3598 } 3599 } 3600 break; 3601 case ISD::VAARG: { 3602 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3603 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3604 3605 MVT VT = Node->getValueType(0); 3606 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3607 default: assert(0 && "This action is not supported yet!"); 3608 case TargetLowering::Custom: 3609 isCustom = true; 3610 // FALLTHROUGH 3611 case TargetLowering::Legal: 3612 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3613 Result = Result.getValue(0); 3614 Tmp1 = Result.getValue(1); 3615 3616 if (isCustom) { 3617 Tmp2 = TLI.LowerOperation(Result, DAG); 3618 if (Tmp2.getNode()) { 3619 Result = LegalizeOp(Tmp2); 3620 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3621 } 3622 } 3623 break; 3624 case TargetLowering::Expand: { 3625 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3626 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0); 3627 // Increment the pointer, VAList, to the next vaarg 3628 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 3629 DAG.getConstant(TLI.getTargetData()-> 3630 getTypePaddedSize(VT.getTypeForMVT()), 3631 TLI.getPointerTy())); 3632 // Store the incremented VAList to the legalized pointer 3633 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0); 3634 // Load the actual argument out of the pointer VAList 3635 Result = DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0); 3636 Tmp1 = LegalizeOp(Result.getValue(1)); 3637 Result = LegalizeOp(Result); 3638 break; 3639 } 3640 } 3641 // Since VAARG produces two values, make sure to remember that we 3642 // legalized both of them. 3643 AddLegalizedOperand(SDValue(Node, 0), Result); 3644 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 3645 return Op.getResNo() ? Tmp1 : Result; 3646 } 3647 3648 case ISD::VACOPY: 3649 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3650 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3651 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3652 3653 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3654 default: assert(0 && "This action is not supported yet!"); 3655 case TargetLowering::Custom: 3656 isCustom = true; 3657 // FALLTHROUGH 3658 case TargetLowering::Legal: 3659 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3660 Node->getOperand(3), Node->getOperand(4)); 3661 if (isCustom) { 3662 Tmp1 = TLI.LowerOperation(Result, DAG); 3663 if (Tmp1.getNode()) Result = Tmp1; 3664 } 3665 break; 3666 case TargetLowering::Expand: 3667 // This defaults to loading a pointer from the input and storing it to the 3668 // output, returning the chain. 3669 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3670 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3671 Tmp4 = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp3, VS, 0); 3672 Result = DAG.getStore(Tmp4.getValue(1), dl, Tmp4, Tmp2, VD, 0); 3673 break; 3674 } 3675 break; 3676 3677 case ISD::VAEND: 3678 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3679 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3680 3681 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3682 default: assert(0 && "This action is not supported yet!"); 3683 case TargetLowering::Custom: 3684 isCustom = true; 3685 // FALLTHROUGH 3686 case TargetLowering::Legal: 3687 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3688 if (isCustom) { 3689 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3690 if (Tmp1.getNode()) Result = Tmp1; 3691 } 3692 break; 3693 case TargetLowering::Expand: 3694 Result = Tmp1; // Default to a no-op, return the chain 3695 break; 3696 } 3697 break; 3698 3699 case ISD::VASTART: 3700 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3701 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3702 3703 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3704 3705 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3706 default: assert(0 && "This action is not supported yet!"); 3707 case TargetLowering::Legal: break; 3708 case TargetLowering::Custom: 3709 Tmp1 = TLI.LowerOperation(Result, DAG); 3710 if (Tmp1.getNode()) Result = Tmp1; 3711 break; 3712 } 3713 break; 3714 3715 case ISD::ROTL: 3716 case ISD::ROTR: 3717 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3718 Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS 3719 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3720 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3721 default: 3722 assert(0 && "ROTL/ROTR legalize operation not supported"); 3723 break; 3724 case TargetLowering::Legal: 3725 break; 3726 case TargetLowering::Custom: 3727 Tmp1 = TLI.LowerOperation(Result, DAG); 3728 if (Tmp1.getNode()) Result = Tmp1; 3729 break; 3730 case TargetLowering::Promote: 3731 assert(0 && "Do not know how to promote ROTL/ROTR"); 3732 break; 3733 case TargetLowering::Expand: 3734 assert(0 && "Do not know how to expand ROTL/ROTR"); 3735 break; 3736 } 3737 break; 3738 3739 case ISD::BSWAP: 3740 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3741 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3742 case TargetLowering::Custom: 3743 assert(0 && "Cannot custom legalize this yet!"); 3744 case TargetLowering::Legal: 3745 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3746 break; 3747 case TargetLowering::Promote: { 3748 MVT OVT = Tmp1.getValueType(); 3749 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3750 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3751 3752 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); 3753 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3754 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3755 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3756 break; 3757 } 3758 case TargetLowering::Expand: 3759 Result = ExpandBSWAP(Tmp1, dl); 3760 break; 3761 } 3762 break; 3763 3764 case ISD::CTPOP: 3765 case ISD::CTTZ: 3766 case ISD::CTLZ: 3767 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3768 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3769 case TargetLowering::Custom: 3770 case TargetLowering::Legal: 3771 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3772 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3773 TargetLowering::Custom) { 3774 Tmp1 = TLI.LowerOperation(Result, DAG); 3775 if (Tmp1.getNode()) { 3776 Result = Tmp1; 3777 } 3778 } 3779 break; 3780 case TargetLowering::Promote: { 3781 MVT OVT = Tmp1.getValueType(); 3782 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3783 3784 // Zero extend the argument. 3785 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); 3786 // Perform the larger operation, then subtract if needed. 3787 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1); 3788 switch (Node->getOpcode()) { 3789 case ISD::CTPOP: 3790 Result = Tmp1; 3791 break; 3792 case ISD::CTTZ: 3793 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3794 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 3795 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3796 ISD::SETEQ); 3797 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3798 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3799 break; 3800 case ISD::CTLZ: 3801 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3802 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3803 DAG.getConstant(NVT.getSizeInBits() - 3804 OVT.getSizeInBits(), NVT)); 3805 break; 3806 } 3807 break; 3808 } 3809 case TargetLowering::Expand: 3810 Result = ExpandBitCount(Node->getOpcode(), Tmp1, dl); 3811 break; 3812 } 3813 break; 3814 3815 // Unary operators 3816 case ISD::FABS: 3817 case ISD::FNEG: 3818 case ISD::FSQRT: 3819 case ISD::FSIN: 3820 case ISD::FCOS: 3821 case ISD::FLOG: 3822 case ISD::FLOG2: 3823 case ISD::FLOG10: 3824 case ISD::FEXP: 3825 case ISD::FEXP2: 3826 case ISD::FTRUNC: 3827 case ISD::FFLOOR: 3828 case ISD::FCEIL: 3829 case ISD::FRINT: 3830 case ISD::FNEARBYINT: 3831 Tmp1 = LegalizeOp(Node->getOperand(0)); 3832 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3833 case TargetLowering::Promote: 3834 case TargetLowering::Custom: 3835 isCustom = true; 3836 // FALLTHROUGH 3837 case TargetLowering::Legal: 3838 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3839 if (isCustom) { 3840 Tmp1 = TLI.LowerOperation(Result, DAG); 3841 if (Tmp1.getNode()) Result = Tmp1; 3842 } 3843 break; 3844 case TargetLowering::Expand: 3845 switch (Node->getOpcode()) { 3846 default: assert(0 && "Unreachable!"); 3847 case ISD::FNEG: 3848 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3849 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3850 Result = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp2, Tmp1); 3851 break; 3852 case ISD::FABS: { 3853 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3854 MVT VT = Node->getValueType(0); 3855 Tmp2 = DAG.getConstantFP(0.0, VT); 3856 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 3857 Tmp1, Tmp2, ISD::SETUGT); 3858 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 3859 Result = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 3860 break; 3861 } 3862 case ISD::FSQRT: 3863 case ISD::FSIN: 3864 case ISD::FCOS: 3865 case ISD::FLOG: 3866 case ISD::FLOG2: 3867 case ISD::FLOG10: 3868 case ISD::FEXP: 3869 case ISD::FEXP2: 3870 case ISD::FTRUNC: 3871 case ISD::FFLOOR: 3872 case ISD::FCEIL: 3873 case ISD::FRINT: 3874 case ISD::FNEARBYINT: { 3875 MVT VT = Node->getValueType(0); 3876 3877 // Expand unsupported unary vector operators by unrolling them. 3878 if (VT.isVector()) { 3879 Result = LegalizeOp(UnrollVectorOp(Op)); 3880 break; 3881 } 3882 3883 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3884 switch(Node->getOpcode()) { 3885 case ISD::FSQRT: 3886 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3887 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3888 break; 3889 case ISD::FSIN: 3890 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3891 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3892 break; 3893 case ISD::FCOS: 3894 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3895 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3896 break; 3897 case ISD::FLOG: 3898 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64, 3899 RTLIB::LOG_F80, RTLIB::LOG_PPCF128); 3900 break; 3901 case ISD::FLOG2: 3902 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 3903 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128); 3904 break; 3905 case ISD::FLOG10: 3906 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 3907 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128); 3908 break; 3909 case ISD::FEXP: 3910 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64, 3911 RTLIB::EXP_F80, RTLIB::EXP_PPCF128); 3912 break; 3913 case ISD::FEXP2: 3914 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 3915 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128); 3916 break; 3917 case ISD::FTRUNC: 3918 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 3919 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 3920 break; 3921 case ISD::FFLOOR: 3922 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 3923 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 3924 break; 3925 case ISD::FCEIL: 3926 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 3927 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 3928 break; 3929 case ISD::FRINT: 3930 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 3931 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 3932 break; 3933 case ISD::FNEARBYINT: 3934 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 3935 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 3936 break; 3937 break; 3938 default: assert(0 && "Unreachable!"); 3939 } 3940 SDValue Dummy; 3941 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3942 break; 3943 } 3944 } 3945 break; 3946 } 3947 break; 3948 case ISD::FPOWI: { 3949 MVT VT = Node->getValueType(0); 3950 3951 // Expand unsupported unary vector operators by unrolling them. 3952 if (VT.isVector()) { 3953 Result = LegalizeOp(UnrollVectorOp(Op)); 3954 break; 3955 } 3956 3957 // We always lower FPOWI into a libcall. No target support for it yet. 3958 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3959 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3960 SDValue Dummy; 3961 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3962 break; 3963 } 3964 case ISD::BIT_CONVERT: 3965 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3966 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3967 Node->getValueType(0), dl); 3968 } else if (Op.getOperand(0).getValueType().isVector()) { 3969 // The input has to be a vector type, we have to either scalarize it, pack 3970 // it, or convert it based on whether the input vector type is legal. 3971 SDNode *InVal = Node->getOperand(0).getNode(); 3972 int InIx = Node->getOperand(0).getResNo(); 3973 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 3974 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 3975 3976 // Figure out if there is a simple type corresponding to this Vector 3977 // type. If so, convert to the vector type. 3978 MVT TVT = MVT::getVectorVT(EVT, NumElems); 3979 if (TLI.isTypeLegal(TVT)) { 3980 // Turn this into a bit convert of the vector input. 3981 Tmp1 = LegalizeOp(Node->getOperand(0)); 3982 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Tmp1); 3983 break; 3984 } else if (NumElems == 1) { 3985 // Turn this into a bit convert of the scalar input. 3986 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 3987 ScalarizeVectorOp(Node->getOperand(0))); 3988 break; 3989 } else { 3990 // FIXME: UNIMP! Store then reload 3991 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3992 } 3993 } else { 3994 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3995 Node->getOperand(0).getValueType())) { 3996 default: assert(0 && "Unknown operation action!"); 3997 case TargetLowering::Expand: 3998 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3999 Node->getValueType(0), dl); 4000 break; 4001 case TargetLowering::Legal: 4002 Tmp1 = LegalizeOp(Node->getOperand(0)); 4003 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4004 break; 4005 } 4006 } 4007 break; 4008 case ISD::CONVERT_RNDSAT: { 4009 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 4010 switch (CvtCode) { 4011 default: assert(0 && "Unknown cvt code!"); 4012 case ISD::CVT_SF: 4013 case ISD::CVT_UF: 4014 case ISD::CVT_FF: 4015 break; 4016 case ISD::CVT_FS: 4017 case ISD::CVT_FU: 4018 case ISD::CVT_SS: 4019 case ISD::CVT_SU: 4020 case ISD::CVT_US: 4021 case ISD::CVT_UU: { 4022 SDValue DTyOp = Node->getOperand(1); 4023 SDValue STyOp = Node->getOperand(2); 4024 SDValue RndOp = Node->getOperand(3); 4025 SDValue SatOp = Node->getOperand(4); 4026 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4027 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4028 case Legal: 4029 Tmp1 = LegalizeOp(Node->getOperand(0)); 4030 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp, 4031 RndOp, SatOp); 4032 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 4033 TargetLowering::Custom) { 4034 Tmp1 = TLI.LowerOperation(Result, DAG); 4035 if (Tmp1.getNode()) Result = Tmp1; 4036 } 4037 break; 4038 case Promote: 4039 Result = PromoteOp(Node->getOperand(0)); 4040 // For FP, make Op1 a i32 4041 4042 Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result, 4043 DTyOp, STyOp, RndOp, SatOp, CvtCode); 4044 break; 4045 } 4046 break; 4047 } 4048 } // end switch CvtCode 4049 break; 4050 } 4051 // Conversion operators. The source and destination have different types. 4052 case ISD::SINT_TO_FP: 4053 case ISD::UINT_TO_FP: { 4054 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 4055 Result = LegalizeINT_TO_FP(Result, isSigned, 4056 Node->getValueType(0), Node->getOperand(0), dl); 4057 break; 4058 } 4059 case ISD::TRUNCATE: 4060 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4061 case Legal: 4062 Tmp1 = LegalizeOp(Node->getOperand(0)); 4063 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 4064 default: assert(0 && "Unknown TRUNCATE legalization operation action!"); 4065 case TargetLowering::Custom: 4066 isCustom = true; 4067 // FALLTHROUGH 4068 case TargetLowering::Legal: 4069 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4070 if (isCustom) { 4071 Tmp1 = TLI.LowerOperation(Result, DAG); 4072 if (Tmp1.getNode()) Result = Tmp1; 4073 } 4074 break; 4075 case TargetLowering::Expand: 4076 assert(Result.getValueType().isVector() && "must be vector type"); 4077 // Unroll the truncate. We should do better. 4078 Result = LegalizeOp(UnrollVectorOp(Result)); 4079 } 4080 break; 4081 case Expand: 4082 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4083 4084 // Since the result is legal, we should just be able to truncate the low 4085 // part of the source. 4086 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 4087 break; 4088 case Promote: 4089 Result = PromoteOp(Node->getOperand(0)); 4090 Result = DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Result); 4091 break; 4092 } 4093 break; 4094 4095 case ISD::FP_TO_SINT: 4096 case ISD::FP_TO_UINT: 4097 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4098 case Legal: 4099 Tmp1 = LegalizeOp(Node->getOperand(0)); 4100 4101 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 4102 default: assert(0 && "Unknown operation action!"); 4103 case TargetLowering::Custom: 4104 isCustom = true; 4105 // FALLTHROUGH 4106 case TargetLowering::Legal: 4107 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4108 if (isCustom) { 4109 Tmp1 = TLI.LowerOperation(Result, DAG); 4110 if (Tmp1.getNode()) Result = Tmp1; 4111 } 4112 break; 4113 case TargetLowering::Promote: 4114 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 4115 Node->getOpcode() == ISD::FP_TO_SINT, 4116 dl); 4117 break; 4118 case TargetLowering::Expand: 4119 if (Node->getOpcode() == ISD::FP_TO_UINT) { 4120 SDValue True, False; 4121 MVT VT = Node->getOperand(0).getValueType(); 4122 MVT NVT = Node->getValueType(0); 4123 const uint64_t zero[] = {0, 0}; 4124 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 4125 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 4126 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 4127 Tmp2 = DAG.getConstantFP(apf, VT); 4128 Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 4129 Node->getOperand(0), 4130 Tmp2, ISD::SETLT); 4131 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 4132 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 4133 DAG.getNode(ISD::FSUB, dl, VT, 4134 Node->getOperand(0), Tmp2)); 4135 False = DAG.getNode(ISD::XOR, dl, NVT, False, 4136 DAG.getConstant(x, NVT)); 4137 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False); 4138 break; 4139 } else { 4140 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 4141 } 4142 break; 4143 } 4144 break; 4145 case Expand: { 4146 MVT VT = Op.getValueType(); 4147 MVT OVT = Node->getOperand(0).getValueType(); 4148 // Convert ppcf128 to i32 4149 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 4150 if (Node->getOpcode() == ISD::FP_TO_SINT) { 4151 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128, 4152 Node->getOperand(0), DAG.getValueType(MVT::f64)); 4153 Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result, 4154 DAG.getIntPtrConstant(1)); 4155 Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result); 4156 } else { 4157 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 4158 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 4159 Tmp2 = DAG.getConstantFP(apf, OVT); 4160 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 4161 // FIXME: generated code sucks. 4162 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0), 4163 Tmp2, 4164 DAG.getNode(ISD::ADD, dl, MVT::i32, 4165 DAG.getNode(ISD::FP_TO_SINT, dl, VT, 4166 DAG.getNode(ISD::FSUB, dl, OVT, 4167 Node->getOperand(0), Tmp2)), 4168 DAG.getConstant(0x80000000, MVT::i32)), 4169 DAG.getNode(ISD::FP_TO_SINT, dl, VT, 4170 Node->getOperand(0)), 4171 DAG.getCondCode(ISD::SETGE)); 4172 } 4173 break; 4174 } 4175 // Convert f32 / f64 to i32 / i64 / i128. 4176 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ? 4177 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT); 4178 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!"); 4179 SDValue Dummy; 4180 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 4181 break; 4182 } 4183 case Promote: 4184 Tmp1 = PromoteOp(Node->getOperand(0)); 4185 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 4186 Result = LegalizeOp(Result); 4187 break; 4188 } 4189 break; 4190 4191 case ISD::FP_EXTEND: { 4192 MVT DstVT = Op.getValueType(); 4193 MVT SrcVT = Op.getOperand(0).getValueType(); 4194 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 4195 // The only other way we can lower this is to turn it into a STORE, 4196 // LOAD pair, targetting a temporary location (a stack slot). 4197 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl); 4198 break; 4199 } 4200 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4201 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4202 case Legal: 4203 Tmp1 = LegalizeOp(Node->getOperand(0)); 4204 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4205 break; 4206 case Promote: 4207 Tmp1 = PromoteOp(Node->getOperand(0)); 4208 Result = DAG.getNode(ISD::FP_EXTEND, dl, Op.getValueType(), Tmp1); 4209 break; 4210 } 4211 break; 4212 } 4213 case ISD::FP_ROUND: { 4214 MVT DstVT = Op.getValueType(); 4215 MVT SrcVT = Op.getOperand(0).getValueType(); 4216 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 4217 if (SrcVT == MVT::ppcf128) { 4218 SDValue Lo; 4219 ExpandOp(Node->getOperand(0), Lo, Result); 4220 // Round it the rest of the way (e.g. to f32) if needed. 4221 if (DstVT!=MVT::f64) 4222 Result = DAG.getNode(ISD::FP_ROUND, dl, 4223 DstVT, Result, Op.getOperand(1)); 4224 break; 4225 } 4226 // The only other way we can lower this is to turn it into a STORE, 4227 // LOAD pair, targetting a temporary location (a stack slot). 4228 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl); 4229 break; 4230 } 4231 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4232 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4233 case Legal: 4234 Tmp1 = LegalizeOp(Node->getOperand(0)); 4235 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 4236 break; 4237 case Promote: 4238 Tmp1 = PromoteOp(Node->getOperand(0)); 4239 Result = DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(), Tmp1, 4240 Node->getOperand(1)); 4241 break; 4242 } 4243 break; 4244 } 4245 case ISD::ANY_EXTEND: 4246 case ISD::ZERO_EXTEND: 4247 case ISD::SIGN_EXTEND: 4248 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4249 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4250 case Legal: 4251 Tmp1 = LegalizeOp(Node->getOperand(0)); 4252 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4253 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 4254 TargetLowering::Custom) { 4255 Tmp1 = TLI.LowerOperation(Result, DAG); 4256 if (Tmp1.getNode()) Result = Tmp1; 4257 } 4258 break; 4259 case Promote: 4260 switch (Node->getOpcode()) { 4261 case ISD::ANY_EXTEND: 4262 Tmp1 = PromoteOp(Node->getOperand(0)); 4263 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Tmp1); 4264 break; 4265 case ISD::ZERO_EXTEND: 4266 Result = PromoteOp(Node->getOperand(0)); 4267 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result); 4268 Result = DAG.getZeroExtendInReg(Result, dl, 4269 Node->getOperand(0).getValueType()); 4270 break; 4271 case ISD::SIGN_EXTEND: 4272 Result = PromoteOp(Node->getOperand(0)); 4273 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result); 4274 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(), 4275 Result, 4276 DAG.getValueType(Node->getOperand(0).getValueType())); 4277 break; 4278 } 4279 } 4280 break; 4281 case ISD::FP_ROUND_INREG: 4282 case ISD::SIGN_EXTEND_INREG: { 4283 Tmp1 = LegalizeOp(Node->getOperand(0)); 4284 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 4285 4286 // If this operation is not supported, convert it to a shl/shr or load/store 4287 // pair. 4288 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 4289 default: assert(0 && "This action not supported for this op yet!"); 4290 case TargetLowering::Legal: 4291 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 4292 break; 4293 case TargetLowering::Expand: 4294 // If this is an integer extend and shifts are supported, do that. 4295 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 4296 // NOTE: we could fall back on load/store here too for targets without 4297 // SAR. However, it is doubtful that any exist. 4298 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 4299 ExtraVT.getSizeInBits(); 4300 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 4301 Result = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 4302 Node->getOperand(0), ShiftCst); 4303 Result = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), 4304 Result, ShiftCst); 4305 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 4306 // The only way we can lower this is to turn it into a TRUNCSTORE, 4307 // EXTLOAD pair, targetting a temporary location (a stack slot). 4308 4309 // NOTE: there is a choice here between constantly creating new stack 4310 // slots and always reusing the same one. We currently always create 4311 // new ones, as reuse may inhibit scheduling. 4312 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 4313 Node->getValueType(0), dl); 4314 } else { 4315 assert(0 && "Unknown op"); 4316 } 4317 break; 4318 } 4319 break; 4320 } 4321 case ISD::TRAMPOLINE: { 4322 SDValue Ops[6]; 4323 for (unsigned i = 0; i != 6; ++i) 4324 Ops[i] = LegalizeOp(Node->getOperand(i)); 4325 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 4326 // The only option for this node is to custom lower it. 4327 Result = TLI.LowerOperation(Result, DAG); 4328 assert(Result.getNode() && "Should always custom lower!"); 4329 4330 // Since trampoline produces two values, make sure to remember that we 4331 // legalized both of them. 4332 Tmp1 = LegalizeOp(Result.getValue(1)); 4333 Result = LegalizeOp(Result); 4334 AddLegalizedOperand(SDValue(Node, 0), Result); 4335 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 4336 return Op.getResNo() ? Tmp1 : Result; 4337 } 4338 case ISD::FLT_ROUNDS_: { 4339 MVT VT = Node->getValueType(0); 4340 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4341 default: assert(0 && "This action not supported for this op yet!"); 4342 case TargetLowering::Custom: 4343 Result = TLI.LowerOperation(Op, DAG); 4344 if (Result.getNode()) break; 4345 // Fall Thru 4346 case TargetLowering::Legal: 4347 // If this operation is not supported, lower it to constant 1 4348 Result = DAG.getConstant(1, VT); 4349 break; 4350 } 4351 break; 4352 } 4353 case ISD::TRAP: { 4354 MVT VT = Node->getValueType(0); 4355 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4356 default: assert(0 && "This action not supported for this op yet!"); 4357 case TargetLowering::Legal: 4358 Tmp1 = LegalizeOp(Node->getOperand(0)); 4359 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4360 break; 4361 case TargetLowering::Custom: 4362 Result = TLI.LowerOperation(Op, DAG); 4363 if (Result.getNode()) break; 4364 // Fall Thru 4365 case TargetLowering::Expand: 4366 // If this operation is not supported, lower it to 'abort()' call 4367 Tmp1 = LegalizeOp(Node->getOperand(0)); 4368 TargetLowering::ArgListTy Args; 4369 std::pair<SDValue, SDValue> CallResult = 4370 TLI.LowerCallTo(Tmp1, Type::VoidTy, 4371 false, false, false, false, CallingConv::C, false, 4372 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 4373 Args, DAG, dl); 4374 Result = CallResult.second; 4375 break; 4376 } 4377 break; 4378 } 4379 4380 case ISD::SADDO: 4381 case ISD::SSUBO: { 4382 MVT VT = Node->getValueType(0); 4383 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4384 default: assert(0 && "This action not supported for this op yet!"); 4385 case TargetLowering::Custom: 4386 Result = TLI.LowerOperation(Op, DAG); 4387 if (Result.getNode()) break; 4388 // FALLTHROUGH 4389 case TargetLowering::Legal: { 4390 SDValue LHS = LegalizeOp(Node->getOperand(0)); 4391 SDValue RHS = LegalizeOp(Node->getOperand(1)); 4392 4393 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 4394 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 4395 LHS, RHS); 4396 MVT OType = Node->getValueType(1); 4397 4398 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 4399 4400 // LHSSign -> LHS >= 0 4401 // RHSSign -> RHS >= 0 4402 // SumSign -> Sum >= 0 4403 // 4404 // Add: 4405 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 4406 // Sub: 4407 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 4408 // 4409 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 4410 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 4411 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 4412 Node->getOpcode() == ISD::SADDO ? 4413 ISD::SETEQ : ISD::SETNE); 4414 4415 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 4416 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 4417 4418 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 4419 4420 MVT ValueVTs[] = { LHS.getValueType(), OType }; 4421 SDValue Ops[] = { Sum, Cmp }; 4422 4423 Result = DAG.getNode(ISD::MERGE_VALUES, dl, 4424 DAG.getVTList(&ValueVTs[0], 2), 4425 &Ops[0], 2); 4426 SDNode *RNode = Result.getNode(); 4427 DAG.ReplaceAllUsesWith(Node, RNode); 4428 break; 4429 } 4430 } 4431 4432 break; 4433 } 4434 case ISD::UADDO: 4435 case ISD::USUBO: { 4436 MVT VT = Node->getValueType(0); 4437 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4438 default: assert(0 && "This action not supported for this op yet!"); 4439 case TargetLowering::Custom: 4440 Result = TLI.LowerOperation(Op, DAG); 4441 if (Result.getNode()) break; 4442 // FALLTHROUGH 4443 case TargetLowering::Legal: { 4444 SDValue LHS = LegalizeOp(Node->getOperand(0)); 4445 SDValue RHS = LegalizeOp(Node->getOperand(1)); 4446 4447 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 4448 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 4449 LHS, RHS); 4450 MVT OType = Node->getValueType(1); 4451 SDValue Cmp = DAG.getSetCC(dl, OType, Sum, LHS, 4452 Node->getOpcode () == ISD::UADDO ? 4453 ISD::SETULT : ISD::SETUGT); 4454 4455 MVT ValueVTs[] = { LHS.getValueType(), OType }; 4456 SDValue Ops[] = { Sum, Cmp }; 4457 4458 Result = DAG.getNode(ISD::MERGE_VALUES, dl, 4459 DAG.getVTList(&ValueVTs[0], 2), 4460 &Ops[0], 2); 4461 SDNode *RNode = Result.getNode(); 4462 DAG.ReplaceAllUsesWith(Node, RNode); 4463 break; 4464 } 4465 } 4466 4467 break; 4468 } 4469 case ISD::SMULO: 4470 case ISD::UMULO: { 4471 MVT VT = Node->getValueType(0); 4472 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4473 default: assert(0 && "This action is not supported at all!"); 4474 case TargetLowering::Custom: 4475 Result = TLI.LowerOperation(Op, DAG); 4476 if (Result.getNode()) break; 4477 // Fall Thru 4478 case TargetLowering::Legal: 4479 // FIXME: According to Hacker's Delight, this can be implemented in 4480 // target independent lowering, but it would be inefficient, since it 4481 // requires a division + a branch. 4482 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!"); 4483 break; 4484 } 4485 break; 4486 } 4487 4488 } 4489 4490 assert(Result.getValueType() == Op.getValueType() && 4491 "Bad legalization!"); 4492 4493 // Make sure that the generated code is itself legal. 4494 if (Result != Op) 4495 Result = LegalizeOp(Result); 4496 4497 // Note that LegalizeOp may be reentered even from single-use nodes, which 4498 // means that we always must cache transformed nodes. 4499 AddLegalizedOperand(Op, Result); 4500 return Result; 4501} 4502 4503/// PromoteOp - Given an operation that produces a value in an invalid type, 4504/// promote it to compute the value into a larger type. The produced value will 4505/// have the correct bits for the low portion of the register, but no guarantee 4506/// is made about the top bits: it may be zero, sign-extended, or garbage. 4507SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { 4508 MVT VT = Op.getValueType(); 4509 MVT NVT = TLI.getTypeToTransformTo(VT); 4510 assert(getTypeAction(VT) == Promote && 4511 "Caller should expand or legalize operands that are not promotable!"); 4512 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() && 4513 "Cannot promote to smaller type!"); 4514 4515 SDValue Tmp1, Tmp2, Tmp3; 4516 SDValue Result; 4517 SDNode *Node = Op.getNode(); 4518 DebugLoc dl = Node->getDebugLoc(); 4519 4520 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op); 4521 if (I != PromotedNodes.end()) return I->second; 4522 4523 switch (Node->getOpcode()) { 4524 case ISD::CopyFromReg: 4525 assert(0 && "CopyFromReg must be legal!"); 4526 default: 4527#ifndef NDEBUG 4528 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4529#endif 4530 assert(0 && "Do not know how to promote this operator!"); 4531 abort(); 4532 case ISD::UNDEF: 4533 Result = DAG.getUNDEF(NVT); 4534 break; 4535 case ISD::Constant: 4536 if (VT != MVT::i1) 4537 Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op); 4538 else 4539 Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op); 4540 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4541 break; 4542 case ISD::ConstantFP: 4543 Result = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op); 4544 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4545 break; 4546 4547 case ISD::SETCC: { 4548 MVT VT0 = Node->getOperand(0).getValueType(); 4549 assert(isTypeLegal(TLI.getSetCCResultType(VT0)) 4550 && "SetCC type is not legal??"); 4551 Result = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(VT0), 4552 Node->getOperand(0), Node->getOperand(1), 4553 Node->getOperand(2)); 4554 break; 4555 } 4556 case ISD::TRUNCATE: 4557 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4558 case Legal: 4559 Result = LegalizeOp(Node->getOperand(0)); 4560 assert(Result.getValueType().bitsGE(NVT) && 4561 "This truncation doesn't make sense!"); 4562 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT 4563 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Result); 4564 break; 4565 case Promote: 4566 // The truncation is not required, because we don't guarantee anything 4567 // about high bits anyway. 4568 Result = PromoteOp(Node->getOperand(0)); 4569 break; 4570 case Expand: 4571 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4572 // Truncate the low part of the expanded value to the result type 4573 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Tmp1); 4574 } 4575 break; 4576 case ISD::SIGN_EXTEND: 4577 case ISD::ZERO_EXTEND: 4578 case ISD::ANY_EXTEND: 4579 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4580 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4581 case Legal: 4582 // Input is legal? Just do extend all the way to the larger type. 4583 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0)); 4584 break; 4585 case Promote: 4586 // Promote the reg if it's smaller. 4587 Result = PromoteOp(Node->getOperand(0)); 4588 // The high bits are not guaranteed to be anything. Insert an extend. 4589 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4590 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result, 4591 DAG.getValueType(Node->getOperand(0).getValueType())); 4592 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4593 Result = DAG.getZeroExtendInReg(Result, dl, 4594 Node->getOperand(0).getValueType()); 4595 break; 4596 } 4597 break; 4598 case ISD::CONVERT_RNDSAT: { 4599 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 4600 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 4601 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 4602 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 4603 "can only promote integers"); 4604 Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0), 4605 Node->getOperand(1), Node->getOperand(2), 4606 Node->getOperand(3), Node->getOperand(4), 4607 CvtCode); 4608 break; 4609 4610 } 4611 case ISD::BIT_CONVERT: 4612 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4613 Node->getValueType(0), dl); 4614 Result = PromoteOp(Result); 4615 break; 4616 4617 case ISD::FP_EXTEND: 4618 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4619 case ISD::FP_ROUND: 4620 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4621 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4622 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4623 case Legal: 4624 if (Node->getConstantOperandVal(1) == 0) { 4625 // Input is legal? Do an FP_ROUND_INREG. 4626 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Node->getOperand(0), 4627 DAG.getValueType(VT)); 4628 } else { 4629 // Just remove the truncate, it isn't affecting the value. 4630 Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0), 4631 Node->getOperand(1)); 4632 } 4633 break; 4634 } 4635 break; 4636 case ISD::SINT_TO_FP: 4637 case ISD::UINT_TO_FP: 4638 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4639 case Legal: 4640 // No extra round required here. 4641 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0)); 4642 break; 4643 4644 case Promote: 4645 Result = PromoteOp(Node->getOperand(0)); 4646 if (Node->getOpcode() == ISD::SINT_TO_FP) 4647 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(), 4648 Result, 4649 DAG.getValueType(Node->getOperand(0).getValueType())); 4650 else 4651 Result = DAG.getZeroExtendInReg(Result, dl, 4652 Node->getOperand(0).getValueType()); 4653 // No extra round required here. 4654 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Result); 4655 break; 4656 case Expand: 4657 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4658 Node->getOperand(0), dl); 4659 // Round if we cannot tolerate excess precision. 4660 if (NoExcessFPPrecision) 4661 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, 4662 DAG.getValueType(VT)); 4663 break; 4664 } 4665 break; 4666 4667 case ISD::SIGN_EXTEND_INREG: 4668 Result = PromoteOp(Node->getOperand(0)); 4669 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result, 4670 Node->getOperand(1)); 4671 break; 4672 case ISD::FP_TO_SINT: 4673 case ISD::FP_TO_UINT: 4674 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4675 case Legal: 4676 case Expand: 4677 Tmp1 = Node->getOperand(0); 4678 break; 4679 case Promote: 4680 // The input result is prerounded, so we don't have to do anything 4681 // special. 4682 Tmp1 = PromoteOp(Node->getOperand(0)); 4683 break; 4684 } 4685 // If we're promoting a UINT to a larger size, check to see if the new node 4686 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4687 // we can use that instead. This allows us to generate better code for 4688 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4689 // legal, such as PowerPC. 4690 if (Node->getOpcode() == ISD::FP_TO_UINT && 4691 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) && 4692 (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) || 4693 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4694 Result = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1); 4695 } else { 4696 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 4697 } 4698 break; 4699 4700 case ISD::FABS: 4701 case ISD::FNEG: 4702 Tmp1 = PromoteOp(Node->getOperand(0)); 4703 assert(Tmp1.getValueType() == NVT); 4704 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 4705 // NOTE: we do not have to do any extra rounding here for 4706 // NoExcessFPPrecision, because we know the input will have the appropriate 4707 // precision, and these operations don't modify precision at all. 4708 break; 4709 4710 case ISD::FLOG: 4711 case ISD::FLOG2: 4712 case ISD::FLOG10: 4713 case ISD::FEXP: 4714 case ISD::FEXP2: 4715 case ISD::FSQRT: 4716 case ISD::FSIN: 4717 case ISD::FCOS: 4718 case ISD::FTRUNC: 4719 case ISD::FFLOOR: 4720 case ISD::FCEIL: 4721 case ISD::FRINT: 4722 case ISD::FNEARBYINT: 4723 Tmp1 = PromoteOp(Node->getOperand(0)); 4724 assert(Tmp1.getValueType() == NVT); 4725 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 4726 if (NoExcessFPPrecision) 4727 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, 4728 DAG.getValueType(VT)); 4729 break; 4730 4731 case ISD::FPOW: 4732 case ISD::FPOWI: { 4733 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall 4734 // directly as well, which may be better. 4735 Tmp1 = PromoteOp(Node->getOperand(0)); 4736 Tmp2 = Node->getOperand(1); 4737 if (Node->getOpcode() == ISD::FPOW) 4738 Tmp2 = PromoteOp(Tmp2); 4739 assert(Tmp1.getValueType() == NVT); 4740 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 4741 if (NoExcessFPPrecision) 4742 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, 4743 DAG.getValueType(VT)); 4744 break; 4745 } 4746 4747 case ISD::ATOMIC_CMP_SWAP: { 4748 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4749 Tmp2 = PromoteOp(Node->getOperand(2)); 4750 Tmp3 = PromoteOp(Node->getOperand(3)); 4751 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(), 4752 AtomNode->getChain(), 4753 AtomNode->getBasePtr(), Tmp2, Tmp3, 4754 AtomNode->getSrcValue(), 4755 AtomNode->getAlignment()); 4756 // Remember that we legalized the chain. 4757 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4758 break; 4759 } 4760 case ISD::ATOMIC_LOAD_ADD: 4761 case ISD::ATOMIC_LOAD_SUB: 4762 case ISD::ATOMIC_LOAD_AND: 4763 case ISD::ATOMIC_LOAD_OR: 4764 case ISD::ATOMIC_LOAD_XOR: 4765 case ISD::ATOMIC_LOAD_NAND: 4766 case ISD::ATOMIC_LOAD_MIN: 4767 case ISD::ATOMIC_LOAD_MAX: 4768 case ISD::ATOMIC_LOAD_UMIN: 4769 case ISD::ATOMIC_LOAD_UMAX: 4770 case ISD::ATOMIC_SWAP: { 4771 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4772 Tmp2 = PromoteOp(Node->getOperand(2)); 4773 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(), 4774 AtomNode->getChain(), 4775 AtomNode->getBasePtr(), Tmp2, 4776 AtomNode->getSrcValue(), 4777 AtomNode->getAlignment()); 4778 // Remember that we legalized the chain. 4779 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4780 break; 4781 } 4782 4783 case ISD::AND: 4784 case ISD::OR: 4785 case ISD::XOR: 4786 case ISD::ADD: 4787 case ISD::SUB: 4788 case ISD::MUL: 4789 // The input may have strange things in the top bits of the registers, but 4790 // these operations don't care. They may have weird bits going out, but 4791 // that too is okay if they are integer operations. 4792 Tmp1 = PromoteOp(Node->getOperand(0)); 4793 Tmp2 = PromoteOp(Node->getOperand(1)); 4794 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4795 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 4796 break; 4797 case ISD::FADD: 4798 case ISD::FSUB: 4799 case ISD::FMUL: 4800 Tmp1 = PromoteOp(Node->getOperand(0)); 4801 Tmp2 = PromoteOp(Node->getOperand(1)); 4802 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4803 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 4804 4805 // Floating point operations will give excess precision that we may not be 4806 // able to tolerate. If we DO allow excess precision, just leave it, 4807 // otherwise excise it. 4808 // FIXME: Why would we need to round FP ops more than integer ones? 4809 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4810 if (NoExcessFPPrecision) 4811 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, 4812 DAG.getValueType(VT)); 4813 break; 4814 4815 case ISD::SDIV: 4816 case ISD::SREM: 4817 // These operators require that their input be sign extended. 4818 Tmp1 = PromoteOp(Node->getOperand(0)); 4819 Tmp2 = PromoteOp(Node->getOperand(1)); 4820 if (NVT.isInteger()) { 4821 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1, 4822 DAG.getValueType(VT)); 4823 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2, 4824 DAG.getValueType(VT)); 4825 } 4826 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 4827 4828 // Perform FP_ROUND: this is probably overly pessimistic. 4829 if (NVT.isFloatingPoint() && NoExcessFPPrecision) 4830 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, 4831 DAG.getValueType(VT)); 4832 break; 4833 case ISD::FDIV: 4834 case ISD::FREM: 4835 case ISD::FCOPYSIGN: 4836 // These operators require that their input be fp extended. 4837 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4838 case Expand: assert(0 && "not implemented"); 4839 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4840 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4841 } 4842 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4843 case Expand: assert(0 && "not implemented"); 4844 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4845 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4846 } 4847 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 4848 4849 // Perform FP_ROUND: this is probably overly pessimistic. 4850 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4851 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result, 4852 DAG.getValueType(VT)); 4853 break; 4854 4855 case ISD::UDIV: 4856 case ISD::UREM: 4857 // These operators require that their input be zero extended. 4858 Tmp1 = PromoteOp(Node->getOperand(0)); 4859 Tmp2 = PromoteOp(Node->getOperand(1)); 4860 assert(NVT.isInteger() && "Operators don't apply to FP!"); 4861 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT); 4862 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT); 4863 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 4864 break; 4865 4866 case ISD::SHL: 4867 Tmp1 = PromoteOp(Node->getOperand(0)); 4868 Result = DAG.getNode(ISD::SHL, dl, NVT, Tmp1, Node->getOperand(1)); 4869 break; 4870 case ISD::SRA: 4871 // The input value must be properly sign extended. 4872 Tmp1 = PromoteOp(Node->getOperand(0)); 4873 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1, 4874 DAG.getValueType(VT)); 4875 Result = DAG.getNode(ISD::SRA, dl, NVT, Tmp1, Node->getOperand(1)); 4876 break; 4877 case ISD::SRL: 4878 // The input value must be properly zero extended. 4879 Tmp1 = PromoteOp(Node->getOperand(0)); 4880 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT); 4881 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Node->getOperand(1)); 4882 break; 4883 4884 case ISD::VAARG: 4885 Tmp1 = Node->getOperand(0); // Get the chain. 4886 Tmp2 = Node->getOperand(1); // Get the pointer. 4887 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4888 Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2)); 4889 Result = TLI.LowerOperation(Tmp3, DAG); 4890 } else { 4891 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4892 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0); 4893 // Increment the pointer, VAList, to the next vaarg 4894 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 4895 DAG.getConstant(VT.getSizeInBits()/8, 4896 TLI.getPointerTy())); 4897 // Store the incremented VAList to the legalized pointer 4898 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0); 4899 // Load the actual argument out of the pointer VAList 4900 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT); 4901 } 4902 // Remember that we legalized the chain. 4903 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4904 break; 4905 4906 case ISD::LOAD: { 4907 LoadSDNode *LD = cast<LoadSDNode>(Node); 4908 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4909 ? ISD::EXTLOAD : LD->getExtensionType(); 4910 Result = DAG.getExtLoad(ExtType, dl, NVT, 4911 LD->getChain(), LD->getBasePtr(), 4912 LD->getSrcValue(), LD->getSrcValueOffset(), 4913 LD->getMemoryVT(), 4914 LD->isVolatile(), 4915 LD->getAlignment()); 4916 // Remember that we legalized the chain. 4917 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4918 break; 4919 } 4920 case ISD::SELECT: { 4921 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4922 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4923 4924 MVT VT2 = Tmp2.getValueType(); 4925 assert(VT2 == Tmp3.getValueType() 4926 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); 4927 // Ensure that the resulting node is at least the same size as the operands' 4928 // value types, because we cannot assume that TLI.getSetCCValueType() is 4929 // constant. 4930 Result = DAG.getNode(ISD::SELECT, dl, VT2, Node->getOperand(0), Tmp2, Tmp3); 4931 break; 4932 } 4933 case ISD::SELECT_CC: 4934 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4935 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4936 Result = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0), 4937 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4938 break; 4939 case ISD::BSWAP: 4940 Tmp1 = Node->getOperand(0); 4941 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); 4942 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 4943 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 4944 DAG.getConstant(NVT.getSizeInBits() - 4945 VT.getSizeInBits(), 4946 TLI.getShiftAmountTy())); 4947 break; 4948 case ISD::CTPOP: 4949 case ISD::CTTZ: 4950 case ISD::CTLZ: 4951 // Zero extend the argument 4952 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 4953 // Perform the larger operation, then subtract if needed. 4954 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 4955 switch(Node->getOpcode()) { 4956 case ISD::CTPOP: 4957 Result = Tmp1; 4958 break; 4959 case ISD::CTTZ: 4960 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4961 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1, 4962 DAG.getConstant(NVT.getSizeInBits(), NVT), 4963 ISD::SETEQ); 4964 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 4965 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); 4966 break; 4967 case ISD::CTLZ: 4968 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4969 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 4970 DAG.getConstant(NVT.getSizeInBits() - 4971 VT.getSizeInBits(), NVT)); 4972 break; 4973 } 4974 break; 4975 case ISD::EXTRACT_SUBVECTOR: 4976 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4977 break; 4978 case ISD::EXTRACT_VECTOR_ELT: 4979 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4980 break; 4981 } 4982 4983 assert(Result.getNode() && "Didn't set a result!"); 4984 4985 // Make sure the result is itself legal. 4986 Result = LegalizeOp(Result); 4987 4988 // Remember that we promoted this! 4989 AddPromotedOperand(Op, Result); 4990 return Result; 4991} 4992 4993/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4994/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4995/// based on the vector type. The return type of this matches the element type 4996/// of the vector, which may not be legal for the target. 4997SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) { 4998 // We know that operand #0 is the Vec vector. If the index is a constant 4999 // or if the invec is a supported hardware type, we can use it. Otherwise, 5000 // lower to a store then an indexed load. 5001 SDValue Vec = Op.getOperand(0); 5002 SDValue Idx = Op.getOperand(1); 5003 DebugLoc dl = Op.getDebugLoc(); 5004 5005 MVT TVT = Vec.getValueType(); 5006 unsigned NumElems = TVT.getVectorNumElements(); 5007 5008 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 5009 default: assert(0 && "This action is not supported yet!"); 5010 case TargetLowering::Custom: { 5011 Vec = LegalizeOp(Vec); 5012 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 5013 SDValue Tmp3 = TLI.LowerOperation(Op, DAG); 5014 if (Tmp3.getNode()) 5015 return Tmp3; 5016 break; 5017 } 5018 case TargetLowering::Legal: 5019 if (isTypeLegal(TVT)) { 5020 Vec = LegalizeOp(Vec); 5021 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 5022 return Op; 5023 } 5024 break; 5025 case TargetLowering::Promote: 5026 assert(TVT.isVector() && "not vector type"); 5027 // fall thru to expand since vectors are by default are promote 5028 case TargetLowering::Expand: 5029 break; 5030 } 5031 5032 if (NumElems == 1) { 5033 // This must be an access of the only element. Return it. 5034 Op = ScalarizeVectorOp(Vec); 5035 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 5036 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 5037 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 5038 SDValue Lo, Hi; 5039 SplitVectorOp(Vec, Lo, Hi); 5040 if (CIdx->getZExtValue() < NumLoElts) { 5041 Vec = Lo; 5042 } else { 5043 Vec = Hi; 5044 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts, 5045 Idx.getValueType()); 5046 } 5047 5048 // It's now an extract from the appropriate high or low part. Recurse. 5049 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 5050 Op = ExpandEXTRACT_VECTOR_ELT(Op); 5051 } else { 5052 // Store the value to a temporary stack slot, then LOAD the scalar 5053 // element back out. 5054 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 5055 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0); 5056 5057 // Add the offset to the index. 5058 unsigned EltSize = Op.getValueType().getSizeInBits()/8; 5059 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 5060 DAG.getConstant(EltSize, Idx.getValueType())); 5061 5062 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 5063 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 5064 else 5065 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 5066 5067 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 5068 5069 Op = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0); 5070 } 5071 return Op; 5072} 5073 5074/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 5075/// we assume the operation can be split if it is not already legal. 5076SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) { 5077 // We know that operand #0 is the Vec vector. For now we assume the index 5078 // is a constant and that the extracted result is a supported hardware type. 5079 SDValue Vec = Op.getOperand(0); 5080 SDValue Idx = LegalizeOp(Op.getOperand(1)); 5081 5082 unsigned NumElems = Vec.getValueType().getVectorNumElements(); 5083 5084 if (NumElems == Op.getValueType().getVectorNumElements()) { 5085 // This must be an access of the desired vector length. Return it. 5086 return Vec; 5087 } 5088 5089 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 5090 SDValue Lo, Hi; 5091 SplitVectorOp(Vec, Lo, Hi); 5092 if (CIdx->getZExtValue() < NumElems/2) { 5093 Vec = Lo; 5094 } else { 5095 Vec = Hi; 5096 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2, 5097 Idx.getValueType()); 5098 } 5099 5100 // It's now an extract from the appropriate high or low part. Recurse. 5101 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 5102 return ExpandEXTRACT_SUBVECTOR(Op); 5103} 5104 5105/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 5106/// with condition CC on the current target. This usually involves legalizing 5107/// or promoting the arguments. In the case where LHS and RHS must be expanded, 5108/// there may be no choice but to create a new SetCC node to represent the 5109/// legalized value of setcc lhs, rhs. In this case, the value is returned in 5110/// LHS, and the SDValue returned in RHS has a nil SDNode value. 5111void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS, 5112 SDValue &RHS, 5113 SDValue &CC, 5114 DebugLoc dl) { 5115 SDValue Tmp1, Tmp2, Tmp3, Result; 5116 5117 switch (getTypeAction(LHS.getValueType())) { 5118 case Legal: 5119 Tmp1 = LegalizeOp(LHS); // LHS 5120 Tmp2 = LegalizeOp(RHS); // RHS 5121 break; 5122 case Promote: 5123 Tmp1 = PromoteOp(LHS); // LHS 5124 Tmp2 = PromoteOp(RHS); // RHS 5125 5126 // If this is an FP compare, the operands have already been extended. 5127 if (LHS.getValueType().isInteger()) { 5128 MVT VT = LHS.getValueType(); 5129 MVT NVT = TLI.getTypeToTransformTo(VT); 5130 5131 // Otherwise, we have to insert explicit sign or zero extends. Note 5132 // that we could insert sign extends for ALL conditions, but zero extend 5133 // is cheaper on many machines (an AND instead of two shifts), so prefer 5134 // it. 5135 switch (cast<CondCodeSDNode>(CC)->get()) { 5136 default: assert(0 && "Unknown integer comparison!"); 5137 case ISD::SETEQ: 5138 case ISD::SETNE: 5139 case ISD::SETUGE: 5140 case ISD::SETUGT: 5141 case ISD::SETULE: 5142 case ISD::SETULT: 5143 // ALL of these operations will work if we either sign or zero extend 5144 // the operands (including the unsigned comparisons!). Zero extend is 5145 // usually a simpler/cheaper operation, so prefer it. 5146 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT); 5147 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT); 5148 break; 5149 case ISD::SETGE: 5150 case ISD::SETGT: 5151 case ISD::SETLT: 5152 case ISD::SETLE: 5153 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1, 5154 DAG.getValueType(VT)); 5155 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2, 5156 DAG.getValueType(VT)); 5157 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes. 5158 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes. 5159 break; 5160 } 5161 } 5162 break; 5163 case Expand: { 5164 MVT VT = LHS.getValueType(); 5165 if (VT == MVT::f32 || VT == MVT::f64) { 5166 // Expand into one or more soft-fp libcall(s). 5167 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; 5168 switch (cast<CondCodeSDNode>(CC)->get()) { 5169 case ISD::SETEQ: 5170 case ISD::SETOEQ: 5171 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 5172 break; 5173 case ISD::SETNE: 5174 case ISD::SETUNE: 5175 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 5176 break; 5177 case ISD::SETGE: 5178 case ISD::SETOGE: 5179 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 5180 break; 5181 case ISD::SETLT: 5182 case ISD::SETOLT: 5183 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5184 break; 5185 case ISD::SETLE: 5186 case ISD::SETOLE: 5187 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 5188 break; 5189 case ISD::SETGT: 5190 case ISD::SETOGT: 5191 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 5192 break; 5193 case ISD::SETUO: 5194 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 5195 break; 5196 case ISD::SETO: 5197 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 5198 break; 5199 default: 5200 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 5201 switch (cast<CondCodeSDNode>(CC)->get()) { 5202 case ISD::SETONE: 5203 // SETONE = SETOLT | SETOGT 5204 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5205 // Fallthrough 5206 case ISD::SETUGT: 5207 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 5208 break; 5209 case ISD::SETUGE: 5210 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 5211 break; 5212 case ISD::SETULT: 5213 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5214 break; 5215 case ISD::SETULE: 5216 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 5217 break; 5218 case ISD::SETUEQ: 5219 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 5220 break; 5221 default: assert(0 && "Unsupported FP setcc!"); 5222 } 5223 } 5224 5225 SDValue Dummy; 5226 SDValue Ops[2] = { LHS, RHS }; 5227 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2, dl).getNode(), 5228 false /*sign irrelevant*/, Dummy); 5229 Tmp2 = DAG.getConstant(0, MVT::i32); 5230 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 5231 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 5232 Tmp1 = DAG.getNode(ISD::SETCC, dl, 5233 TLI.getSetCCResultType(Tmp1.getValueType()), 5234 Tmp1, Tmp2, CC); 5235 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2, dl).getNode(), 5236 false /*sign irrelevant*/, Dummy); 5237 Tmp2 = DAG.getNode(ISD::SETCC, dl, 5238 TLI.getSetCCResultType(LHS.getValueType()), LHS, 5239 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 5240 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2); 5241 Tmp2 = SDValue(); 5242 } 5243 LHS = LegalizeOp(Tmp1); 5244 RHS = Tmp2; 5245 return; 5246 } 5247 5248 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 5249 ExpandOp(LHS, LHSLo, LHSHi); 5250 ExpandOp(RHS, RHSLo, RHSHi); 5251 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 5252 5253 if (VT==MVT::ppcf128) { 5254 // FIXME: This generated code sucks. We want to generate 5255 // FCMPU crN, hi1, hi2 5256 // BNE crN, L: 5257 // FCMPU crN, lo1, lo2 5258 // The following can be improved, but not that much. 5259 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 5260 LHSHi, RHSHi, ISD::SETOEQ); 5261 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 5262 LHSLo, RHSLo, CCCode); 5263 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); 5264 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 5265 LHSHi, RHSHi, ISD::SETUNE); 5266 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 5267 LHSHi, RHSHi, CCCode); 5268 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); 5269 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); 5270 Tmp2 = SDValue(); 5271 break; 5272 } 5273 5274 switch (CCCode) { 5275 case ISD::SETEQ: 5276 case ISD::SETNE: 5277 if (RHSLo == RHSHi) 5278 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 5279 if (RHSCST->isAllOnesValue()) { 5280 // Comparison to -1. 5281 Tmp1 = DAG.getNode(ISD::AND, dl,LHSLo.getValueType(), LHSLo, LHSHi); 5282 Tmp2 = RHSLo; 5283 break; 5284 } 5285 5286 Tmp1 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 5287 Tmp2 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 5288 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2); 5289 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 5290 break; 5291 default: 5292 // If this is a comparison of the sign bit, just look at the top part. 5293 // X > -1, x < 0 5294 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 5295 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 5296 CST->isNullValue()) || // X < 0 5297 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 5298 CST->isAllOnesValue())) { // X > -1 5299 Tmp1 = LHSHi; 5300 Tmp2 = RHSHi; 5301 break; 5302 } 5303 5304 // FIXME: This generated code sucks. 5305 ISD::CondCode LowCC; 5306 switch (CCCode) { 5307 default: assert(0 && "Unknown integer setcc!"); 5308 case ISD::SETLT: 5309 case ISD::SETULT: LowCC = ISD::SETULT; break; 5310 case ISD::SETGT: 5311 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 5312 case ISD::SETLE: 5313 case ISD::SETULE: LowCC = ISD::SETULE; break; 5314 case ISD::SETGE: 5315 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 5316 } 5317 5318 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 5319 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 5320 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 5321 5322 // NOTE: on targets without efficient SELECT of bools, we can always use 5323 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 5324 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 5325 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), 5326 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl); 5327 if (!Tmp1.getNode()) 5328 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 5329 LHSLo, RHSLo, LowCC); 5330 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 5331 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl); 5332 if (!Tmp2.getNode()) 5333 Tmp2 = DAG.getNode(ISD::SETCC, dl, 5334 TLI.getSetCCResultType(LHSHi.getValueType()), 5335 LHSHi, RHSHi, CC); 5336 5337 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 5338 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 5339 if ((Tmp1C && Tmp1C->isNullValue()) || 5340 (Tmp2C && Tmp2C->isNullValue() && 5341 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 5342 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 5343 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 5344 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 5345 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 5346 // low part is known false, returns high part. 5347 // For LE / GE, if high part is known false, ignore the low part. 5348 // For LT / GT, if high part is known true, ignore the low part. 5349 Tmp1 = Tmp2; 5350 Tmp2 = SDValue(); 5351 } else { 5352 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 5353 LHSHi, RHSHi, ISD::SETEQ, false, 5354 DagCombineInfo, dl); 5355 if (!Result.getNode()) 5356 Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 5357 LHSHi, RHSHi, ISD::SETEQ); 5358 Result = LegalizeOp(DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), 5359 Result, Tmp1, Tmp2)); 5360 Tmp1 = Result; 5361 Tmp2 = SDValue(); 5362 } 5363 } 5364 } 5365 } 5366 LHS = Tmp1; 5367 RHS = Tmp2; 5368} 5369 5370/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 5371/// condition code CC on the current target. This routine assumes LHS and rHS 5372/// have already been legalized by LegalizeSetCCOperands. It expands SETCC with 5373/// illegal condition code into AND / OR of multiple SETCC values. 5374void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, 5375 SDValue &LHS, SDValue &RHS, 5376 SDValue &CC, 5377 DebugLoc dl) { 5378 MVT OpVT = LHS.getValueType(); 5379 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 5380 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 5381 default: assert(0 && "Unknown condition code action!"); 5382 case TargetLowering::Legal: 5383 // Nothing to do. 5384 break; 5385 case TargetLowering::Expand: { 5386 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 5387 unsigned Opc = 0; 5388 switch (CCCode) { 5389 default: assert(0 && "Don't know how to expand this condition!"); abort(); 5390 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 5391 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 5392 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5393 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 5394 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5395 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5396 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5397 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5398 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5399 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5400 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5401 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5402 // FIXME: Implement more expansions. 5403 } 5404 5405 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 5406 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 5407 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 5408 RHS = SDValue(); 5409 CC = SDValue(); 5410 break; 5411 } 5412 } 5413} 5414 5415/// EmitStackConvert - Emit a store/load combination to the stack. This stores 5416/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 5417/// a load from the stack slot to DestVT, extending it if needed. 5418/// The resultant code need not be legal. 5419SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 5420 MVT SlotVT, 5421 MVT DestVT, 5422 DebugLoc dl) { 5423 // Create the stack frame object. 5424 unsigned SrcAlign = 5425 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 5426 getTypeForMVT()); 5427 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 5428 5429 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 5430 int SPFI = StackPtrFI->getIndex(); 5431 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 5432 5433 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 5434 unsigned SlotSize = SlotVT.getSizeInBits(); 5435 unsigned DestSize = DestVT.getSizeInBits(); 5436 unsigned DestAlign = 5437 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT()); 5438 5439 // Emit a store to the stack slot. Use a truncstore if the input value is 5440 // later than DestVT. 5441 SDValue Store; 5442 5443 if (SrcSize > SlotSize) 5444 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 5445 SV, 0, SlotVT, false, SrcAlign); 5446 else { 5447 assert(SrcSize == SlotSize && "Invalid store"); 5448 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 5449 SV, 0, false, SrcAlign); 5450 } 5451 5452 // Result is a load from the stack slot. 5453 if (SlotSize == DestSize) 5454 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign); 5455 5456 assert(SlotSize < DestSize && "Unknown extension!"); 5457 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, 5458 false, DestAlign); 5459} 5460 5461SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 5462 DebugLoc dl = Node->getDebugLoc(); 5463 // Create a vector sized/aligned stack slot, store the value to element #0, 5464 // then load the whole vector back out. 5465 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 5466 5467 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 5468 int SPFI = StackPtrFI->getIndex(); 5469 5470 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 5471 StackPtr, 5472 PseudoSourceValue::getFixedStack(SPFI), 0, 5473 Node->getValueType(0).getVectorElementType()); 5474 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 5475 PseudoSourceValue::getFixedStack(SPFI), 0); 5476} 5477 5478 5479/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 5480/// support the operation, but do support the resultant vector type. 5481SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 5482 unsigned NumElems = Node->getNumOperands(); 5483 SDValue SplatValue = Node->getOperand(0); 5484 DebugLoc dl = Node->getDebugLoc(); 5485 MVT VT = Node->getValueType(0); 5486 MVT OpVT = SplatValue.getValueType(); 5487 MVT EltVT = VT.getVectorElementType(); 5488 5489 // If the only non-undef value is the low element, turn this into a 5490 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 5491 bool isOnlyLowElement = true; 5492 5493 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t> 5494 // and use a bitmask instead of a list of elements. 5495 // FIXME: this doesn't treat <0, u, 0, u> for example, as a splat. 5496 std::map<SDValue, std::vector<unsigned> > Values; 5497 Values[SplatValue].push_back(0); 5498 bool isConstant = true; 5499 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 5500 SplatValue.getOpcode() != ISD::UNDEF) 5501 isConstant = false; 5502 5503 for (unsigned i = 1; i < NumElems; ++i) { 5504 SDValue V = Node->getOperand(i); 5505 Values[V].push_back(i); 5506 if (V.getOpcode() != ISD::UNDEF) 5507 isOnlyLowElement = false; 5508 if (SplatValue != V) 5509 SplatValue = SDValue(0, 0); 5510 5511 // If this isn't a constant element or an undef, we can't use a constant 5512 // pool load. 5513 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 5514 V.getOpcode() != ISD::UNDEF) 5515 isConstant = false; 5516 } 5517 5518 if (isOnlyLowElement) { 5519 // If the low element is an undef too, then this whole things is an undef. 5520 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 5521 return DAG.getUNDEF(VT); 5522 // Otherwise, turn this into a scalar_to_vector node. 5523 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 5524 } 5525 5526 // If all elements are constants, create a load from the constant pool. 5527 if (isConstant) { 5528 std::vector<Constant*> CV; 5529 for (unsigned i = 0, e = NumElems; i != e; ++i) { 5530 if (ConstantFPSDNode *V = 5531 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 5532 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 5533 } else if (ConstantSDNode *V = 5534 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 5535 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 5536 } else { 5537 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 5538 const Type *OpNTy = OpVT.getTypeForMVT(); 5539 CV.push_back(UndefValue::get(OpNTy)); 5540 } 5541 } 5542 Constant *CP = ConstantVector::get(CV); 5543 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 5544 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5545 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 5546 PseudoSourceValue::getConstantPool(), 0, 5547 false, Alignment); 5548 } 5549 5550 if (SplatValue.getNode()) { // Splat of one value? 5551 // Build the shuffle constant vector: <0, 0, 0, 0> 5552 SmallVector<int, 8> ZeroVec(NumElems, 0); 5553 5554 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 5555 if (TLI.isShuffleMaskLegal(ZeroVec, Node->getValueType(0))) { 5556 // Get the splatted value into the low element of a vector register. 5557 SDValue LowValVec = 5558 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, SplatValue); 5559 5560 // Return shuffle(LowValVec, undef, <0,0,0,0>) 5561 return DAG.getVectorShuffle(VT, dl, LowValVec, DAG.getUNDEF(VT), 5562 &ZeroVec[0]); 5563 } 5564 } 5565 5566 // If there are only two unique elements, we may be able to turn this into a 5567 // vector shuffle. 5568 if (Values.size() == 2) { 5569 // Get the two values in deterministic order. 5570 SDValue Val1 = Node->getOperand(1); 5571 SDValue Val2; 5572 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin(); 5573 if (MI->first != Val1) 5574 Val2 = MI->first; 5575 else 5576 Val2 = (++MI)->first; 5577 5578 // If Val1 is an undef, make sure it ends up as Val2, to ensure that our 5579 // vector shuffle has the undef vector on the RHS. 5580 if (Val1.getOpcode() == ISD::UNDEF) 5581 std::swap(Val1, Val2); 5582 5583 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 5584 SmallVector<int, 8> ShuffleMask(NumElems, -1); 5585 5586 // Set elements of the shuffle mask for Val1. 5587 std::vector<unsigned> &Val1Elts = Values[Val1]; 5588 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 5589 ShuffleMask[Val1Elts[i]] = 0; 5590 5591 // Set elements of the shuffle mask for Val2. 5592 std::vector<unsigned> &Val2Elts = Values[Val2]; 5593 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 5594 if (Val2.getOpcode() != ISD::UNDEF) 5595 ShuffleMask[Val2Elts[i]] = NumElems; 5596 5597 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 5598 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, VT) && 5599 TLI.isShuffleMaskLegal(ShuffleMask, VT)) { 5600 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val1); 5601 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val2); 5602 return DAG.getVectorShuffle(VT, dl, Val1, Val2, &ShuffleMask[0]); 5603 } 5604 } 5605 5606 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5607 // aligned object on the stack, store each element into it, then load 5608 // the result as a vector. 5609 // Create the stack frame object. 5610 SDValue FIPtr = DAG.CreateStackTemporary(VT); 5611 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 5612 const Value *SV = PseudoSourceValue::getFixedStack(FI); 5613 5614 // Emit a store of each element to the stack slot. 5615 SmallVector<SDValue, 8> Stores; 5616 unsigned TypeByteSize = OpVT.getSizeInBits() / 8; 5617 // Store (in the right endianness) the elements to memory. 5618 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5619 // Ignore undef elements. 5620 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5621 5622 unsigned Offset = TypeByteSize*i; 5623 5624 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5625 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 5626 5627 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i), 5628 Idx, SV, Offset)); 5629 } 5630 5631 SDValue StoreChain; 5632 if (!Stores.empty()) // Not all undef elements? 5633 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 5634 &Stores[0], Stores.size()); 5635 else 5636 StoreChain = DAG.getEntryNode(); 5637 5638 // Result is a load from the stack slot. 5639 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0); 5640} 5641 5642void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5643 SDValue Op, SDValue Amt, 5644 SDValue &Lo, SDValue &Hi, 5645 DebugLoc dl) { 5646 // Expand the subcomponents. 5647 SDValue LHSL, LHSH; 5648 ExpandOp(Op, LHSL, LHSH); 5649 5650 SDValue Ops[] = { LHSL, LHSH, Amt }; 5651 MVT VT = LHSL.getValueType(); 5652 Lo = DAG.getNode(NodeOp, dl, DAG.getVTList(VT, VT), Ops, 3); 5653 Hi = Lo.getValue(1); 5654} 5655 5656 5657/// ExpandShift - Try to find a clever way to expand this shift operation out to 5658/// smaller elements. If we can't find a way that is more efficient than a 5659/// libcall on this target, return false. Otherwise, return true with the 5660/// low-parts expanded into Lo and Hi. 5661bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op, SDValue Amt, 5662 SDValue &Lo, SDValue &Hi, 5663 DebugLoc dl) { 5664 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5665 "This is not a shift!"); 5666 5667 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5668 SDValue ShAmt = LegalizeOp(Amt); 5669 MVT ShTy = ShAmt.getValueType(); 5670 unsigned ShBits = ShTy.getSizeInBits(); 5671 unsigned VTBits = Op.getValueType().getSizeInBits(); 5672 unsigned NVTBits = NVT.getSizeInBits(); 5673 5674 // Handle the case when Amt is an immediate. 5675 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) { 5676 unsigned Cst = CN->getZExtValue(); 5677 // Expand the incoming operand to be shifted, so that we have its parts 5678 SDValue InL, InH; 5679 ExpandOp(Op, InL, InH); 5680 switch(Opc) { 5681 case ISD::SHL: 5682 if (Cst > VTBits) { 5683 Lo = DAG.getConstant(0, NVT); 5684 Hi = DAG.getConstant(0, NVT); 5685 } else if (Cst > NVTBits) { 5686 Lo = DAG.getConstant(0, NVT); 5687 Hi = DAG.getNode(ISD::SHL, dl, 5688 NVT, InL, DAG.getConstant(Cst-NVTBits, ShTy)); 5689 } else if (Cst == NVTBits) { 5690 Lo = DAG.getConstant(0, NVT); 5691 Hi = InL; 5692 } else { 5693 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)); 5694 Hi = DAG.getNode(ISD::OR, dl, NVT, 5695 DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)), 5696 DAG.getNode(ISD::SRL, dl, NVT, InL, 5697 DAG.getConstant(NVTBits-Cst, ShTy))); 5698 } 5699 return true; 5700 case ISD::SRL: 5701 if (Cst > VTBits) { 5702 Lo = DAG.getConstant(0, NVT); 5703 Hi = DAG.getConstant(0, NVT); 5704 } else if (Cst > NVTBits) { 5705 Lo = DAG.getNode(ISD::SRL, dl, NVT, 5706 InH, DAG.getConstant(Cst-NVTBits, ShTy)); 5707 Hi = DAG.getConstant(0, NVT); 5708 } else if (Cst == NVTBits) { 5709 Lo = InH; 5710 Hi = DAG.getConstant(0, NVT); 5711 } else { 5712 Lo = DAG.getNode(ISD::OR, dl, NVT, 5713 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)), 5714 DAG.getNode(ISD::SHL, dl, NVT, InH, 5715 DAG.getConstant(NVTBits-Cst, ShTy))); 5716 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)); 5717 } 5718 return true; 5719 case ISD::SRA: 5720 if (Cst > VTBits) { 5721 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 5722 DAG.getConstant(NVTBits-1, ShTy)); 5723 } else if (Cst > NVTBits) { 5724 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 5725 DAG.getConstant(Cst-NVTBits, ShTy)); 5726 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 5727 DAG.getConstant(NVTBits-1, ShTy)); 5728 } else if (Cst == NVTBits) { 5729 Lo = InH; 5730 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 5731 DAG.getConstant(NVTBits-1, ShTy)); 5732 } else { 5733 Lo = DAG.getNode(ISD::OR, dl, NVT, 5734 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)), 5735 DAG.getNode(ISD::SHL, dl, 5736 NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5737 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy)); 5738 } 5739 return true; 5740 } 5741 } 5742 5743 // Okay, the shift amount isn't constant. However, if we can tell that it is 5744 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5745 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5746 APInt KnownZero, KnownOne; 5747 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5748 5749 // If we know that if any of the high bits of the shift amount are one, then 5750 // we can do this as a couple of simple shifts. 5751 if (KnownOne.intersects(Mask)) { 5752 // Mask out the high bit, which we know is set. 5753 Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt, 5754 DAG.getConstant(~Mask, Amt.getValueType())); 5755 5756 // Expand the incoming operand to be shifted, so that we have its parts 5757 SDValue InL, InH; 5758 ExpandOp(Op, InL, InH); 5759 switch(Opc) { 5760 case ISD::SHL: 5761 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5762 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 5763 return true; 5764 case ISD::SRL: 5765 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5766 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 5767 return true; 5768 case ISD::SRA: 5769 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 5770 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5771 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 5772 return true; 5773 } 5774 } 5775 5776 // If we know that the high bits of the shift amount are all zero, then we can 5777 // do this as a couple of simple shifts. 5778 if ((KnownZero & Mask) == Mask) { 5779 // Compute 32-amt. 5780 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(), 5781 DAG.getConstant(NVTBits, Amt.getValueType()), 5782 Amt); 5783 5784 // Expand the incoming operand to be shifted, so that we have its parts 5785 SDValue InL, InH; 5786 ExpandOp(Op, InL, InH); 5787 switch(Opc) { 5788 case ISD::SHL: 5789 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); 5790 Hi = DAG.getNode(ISD::OR, dl, NVT, 5791 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt), 5792 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2)); 5793 return true; 5794 case ISD::SRL: 5795 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); 5796 Lo = DAG.getNode(ISD::OR, dl, NVT, 5797 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 5798 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2)); 5799 return true; 5800 case ISD::SRA: 5801 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); 5802 Lo = DAG.getNode(ISD::OR, dl, NVT, 5803 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 5804 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2)); 5805 return true; 5806 } 5807 } 5808 5809 return false; 5810} 5811 5812 5813// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5814// does not fit into a register, return the lo part and set the hi part to the 5815// by-reg argument. If it does fit into a single register, return the result 5816// and leave the Hi part unset. 5817SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5818 bool isSigned, SDValue &Hi) { 5819 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5820 // The input chain to this libcall is the entry node of the function. 5821 // Legalizing the call will automatically add the previous call to the 5822 // dependence. 5823 SDValue InChain = DAG.getEntryNode(); 5824 5825 TargetLowering::ArgListTy Args; 5826 TargetLowering::ArgListEntry Entry; 5827 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5828 MVT ArgVT = Node->getOperand(i).getValueType(); 5829 const Type *ArgTy = ArgVT.getTypeForMVT(); 5830 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5831 Entry.isSExt = isSigned; 5832 Entry.isZExt = !isSigned; 5833 Args.push_back(Entry); 5834 } 5835 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5836 TLI.getPointerTy()); 5837 5838 // Splice the libcall in wherever FindInputOutputChains tells us to. 5839 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 5840 std::pair<SDValue, SDValue> CallInfo = 5841 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 5842 CallingConv::C, false, Callee, Args, DAG, 5843 Node->getDebugLoc()); 5844 5845 // Legalize the call sequence, starting with the chain. This will advance 5846 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5847 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5848 LegalizeOp(CallInfo.second); 5849 SDValue Result; 5850 switch (getTypeAction(CallInfo.first.getValueType())) { 5851 default: assert(0 && "Unknown thing"); 5852 case Legal: 5853 Result = CallInfo.first; 5854 break; 5855 case Expand: 5856 ExpandOp(CallInfo.first, Result, Hi); 5857 break; 5858 } 5859 return Result; 5860} 5861 5862/// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation. 5863/// 5864SDValue SelectionDAGLegalize:: 5865LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op, 5866 DebugLoc dl) { 5867 bool isCustom = false; 5868 SDValue Tmp1; 5869 switch (getTypeAction(Op.getValueType())) { 5870 case Legal: 5871 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5872 Op.getValueType())) { 5873 default: assert(0 && "Unknown operation action!"); 5874 case TargetLowering::Custom: 5875 isCustom = true; 5876 // FALLTHROUGH 5877 case TargetLowering::Legal: 5878 Tmp1 = LegalizeOp(Op); 5879 if (Result.getNode()) 5880 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5881 else 5882 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl, 5883 DestTy, Tmp1); 5884 if (isCustom) { 5885 Tmp1 = TLI.LowerOperation(Result, DAG); 5886 if (Tmp1.getNode()) Result = Tmp1; 5887 } 5888 break; 5889 case TargetLowering::Expand: 5890 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy, dl); 5891 break; 5892 case TargetLowering::Promote: 5893 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned, dl); 5894 break; 5895 } 5896 break; 5897 case Expand: 5898 Result = ExpandIntToFP(isSigned, DestTy, Op, dl) ; 5899 break; 5900 case Promote: 5901 Tmp1 = PromoteOp(Op); 5902 if (isSigned) { 5903 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(), 5904 Tmp1, DAG.getValueType(Op.getValueType())); 5905 } else { 5906 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, Op.getValueType()); 5907 } 5908 if (Result.getNode()) 5909 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5910 else 5911 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl, 5912 DestTy, Tmp1); 5913 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 5914 break; 5915 } 5916 return Result; 5917} 5918 5919/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5920/// 5921SDValue SelectionDAGLegalize:: 5922ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) { 5923 MVT SourceVT = Source.getValueType(); 5924 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5925 5926 // Expand unsupported int-to-fp vector casts by unrolling them. 5927 if (DestTy.isVector()) { 5928 if (!ExpandSource) 5929 return LegalizeOp(UnrollVectorOp(Source)); 5930 MVT DestEltTy = DestTy.getVectorElementType(); 5931 if (DestTy.getVectorNumElements() == 1) { 5932 SDValue Scalar = ScalarizeVectorOp(Source); 5933 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned, 5934 DestEltTy, Scalar, dl); 5935 return DAG.getNode(ISD::BUILD_VECTOR, dl, DestTy, Result); 5936 } 5937 SDValue Lo, Hi; 5938 SplitVectorOp(Source, Lo, Hi); 5939 MVT SplitDestTy = MVT::getVectorVT(DestEltTy, 5940 DestTy.getVectorNumElements() / 2); 5941 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, 5942 Lo, dl); 5943 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, 5944 Hi, dl); 5945 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult, 5946 HiResult)); 5947 } 5948 5949 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5950 if (!isSigned && SourceVT != MVT::i32) { 5951 // The integer value loaded will be incorrectly if the 'sign bit' of the 5952 // incoming integer is set. To handle this, we dynamically test to see if 5953 // it is set, and, if so, add a fudge factor. 5954 SDValue Hi; 5955 if (ExpandSource) { 5956 SDValue Lo; 5957 ExpandOp(Source, Lo, Hi); 5958 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, Lo, Hi); 5959 } else { 5960 // The comparison for the sign bit will use the entire operand. 5961 Hi = Source; 5962 } 5963 5964 // Check to see if the target has a custom way to lower this. If so, use 5965 // it. (Note we've already expanded the operand in this case.) 5966 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) { 5967 default: assert(0 && "This action not implemented for this operation!"); 5968 case TargetLowering::Legal: 5969 case TargetLowering::Expand: 5970 break; // This case is handled below. 5971 case TargetLowering::Custom: { 5972 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, dl, DestTy, 5973 Source), DAG); 5974 if (NV.getNode()) 5975 return LegalizeOp(NV); 5976 break; // The target decided this was legal after all 5977 } 5978 } 5979 5980 // If this is unsigned, and not supported, first perform the conversion to 5981 // signed, then adjust the result if the sign bit is set. 5982 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl); 5983 5984 SDValue SignSet = DAG.getSetCC(dl, 5985 TLI.getSetCCResultType(Hi.getValueType()), 5986 Hi, DAG.getConstant(0, Hi.getValueType()), 5987 ISD::SETLT); 5988 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5989 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 5990 SignSet, Four, Zero); 5991 uint64_t FF = 0x5f800000ULL; 5992 if (TLI.isLittleEndian()) FF <<= 32; 5993 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5994 5995 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5996 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5997 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 5998 Alignment = std::min(Alignment, 4u); 5999 SDValue FudgeInReg; 6000 if (DestTy == MVT::f32) 6001 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 6002 PseudoSourceValue::getConstantPool(), 0, 6003 false, Alignment); 6004 else if (DestTy.bitsGT(MVT::f32)) 6005 // FIXME: Avoid the extend by construction the right constantpool? 6006 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, dl, DestTy, DAG.getEntryNode(), 6007 CPIdx, 6008 PseudoSourceValue::getConstantPool(), 0, 6009 MVT::f32, false, Alignment); 6010 else 6011 assert(0 && "Unexpected conversion"); 6012 6013 MVT SCVT = SignedConv.getValueType(); 6014 if (SCVT != DestTy) { 6015 // Destination type needs to be expanded as well. The FADD now we are 6016 // constructing will be expanded into a libcall. 6017 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { 6018 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); 6019 SignedConv = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, 6020 SignedConv, SignedConv.getValue(1)); 6021 } 6022 SignedConv = DAG.getNode(ISD::BIT_CONVERT, dl, DestTy, SignedConv); 6023 } 6024 return DAG.getNode(ISD::FADD, dl, DestTy, SignedConv, FudgeInReg); 6025 } 6026 6027 // Check to see if the target has a custom way to lower this. If so, use it. 6028 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 6029 default: assert(0 && "This action not implemented for this operation!"); 6030 case TargetLowering::Legal: 6031 case TargetLowering::Expand: 6032 break; // This case is handled below. 6033 case TargetLowering::Custom: { 6034 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, 6035 Source), DAG); 6036 if (NV.getNode()) 6037 return LegalizeOp(NV); 6038 break; // The target decided this was legal after all 6039 } 6040 } 6041 6042 // Expand the source, then glue it back together for the call. We must expand 6043 // the source in case it is shared (this pass of legalize must traverse it). 6044 if (ExpandSource) { 6045 SDValue SrcLo, SrcHi; 6046 ExpandOp(Source, SrcLo, SrcHi); 6047 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, SrcLo, SrcHi); 6048 } 6049 6050 RTLIB::Libcall LC = isSigned ? 6051 RTLIB::getSINTTOFP(SourceVT, DestTy) : 6052 RTLIB::getUINTTOFP(SourceVT, DestTy); 6053 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type"); 6054 6055 Source = DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source); 6056 SDValue HiPart; 6057 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart); 6058 if (Result.getValueType() != DestTy && HiPart.getNode()) 6059 Result = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, Result, HiPart); 6060 return Result; 6061} 6062 6063/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 6064/// INT_TO_FP operation of the specified operand when the target requests that 6065/// we expand it. At this point, we know that the result and operand types are 6066/// legal for the target. 6067SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 6068 SDValue Op0, 6069 MVT DestVT, 6070 DebugLoc dl) { 6071 if (Op0.getValueType() == MVT::i32) { 6072 // simple 32-bit [signed|unsigned] integer to float/double expansion 6073 6074 // Get the stack frame index of a 8 byte buffer. 6075 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 6076 6077 // word offset constant for Hi/Lo address computation 6078 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 6079 // set up Hi and Lo (into buffer) address based on endian 6080 SDValue Hi = StackSlot; 6081 SDValue Lo = DAG.getNode(ISD::ADD, dl, 6082 TLI.getPointerTy(), StackSlot, WordOff); 6083 if (TLI.isLittleEndian()) 6084 std::swap(Hi, Lo); 6085 6086 // if signed map to unsigned space 6087 SDValue Op0Mapped; 6088 if (isSigned) { 6089 // constant used to invert sign bit (signed to unsigned mapping) 6090 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 6091 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 6092 } else { 6093 Op0Mapped = Op0; 6094 } 6095 // store the lo of the constructed double - based on integer input 6096 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 6097 Op0Mapped, Lo, NULL, 0); 6098 // initial hi portion of constructed double 6099 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 6100 // store the hi of the constructed double - biased exponent 6101 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0); 6102 // load the constructed double 6103 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0); 6104 // FP constant to bias correct the final result 6105 SDValue Bias = DAG.getConstantFP(isSigned ? 6106 BitsToDouble(0x4330000080000000ULL) : 6107 BitsToDouble(0x4330000000000000ULL), 6108 MVT::f64); 6109 // subtract the bias 6110 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 6111 // final result 6112 SDValue Result; 6113 // handle final rounding 6114 if (DestVT == MVT::f64) { 6115 // do nothing 6116 Result = Sub; 6117 } else if (DestVT.bitsLT(MVT::f64)) { 6118 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 6119 DAG.getIntPtrConstant(0)); 6120 } else if (DestVT.bitsGT(MVT::f64)) { 6121 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 6122 } 6123 return Result; 6124 } 6125 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 6126 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 6127 6128 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 6129 Op0, DAG.getConstant(0, Op0.getValueType()), 6130 ISD::SETLT); 6131 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 6132 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 6133 SignSet, Four, Zero); 6134 6135 // If the sign bit of the integer is set, the large number will be treated 6136 // as a negative number. To counteract this, the dynamic code adds an 6137 // offset depending on the data type. 6138 uint64_t FF; 6139 switch (Op0.getValueType().getSimpleVT()) { 6140 default: assert(0 && "Unsupported integer type!"); 6141 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 6142 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 6143 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 6144 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 6145 } 6146 if (TLI.isLittleEndian()) FF <<= 32; 6147 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 6148 6149 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 6150 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6151 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 6152 Alignment = std::min(Alignment, 4u); 6153 SDValue FudgeInReg; 6154 if (DestVT == MVT::f32) 6155 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 6156 PseudoSourceValue::getConstantPool(), 0, 6157 false, Alignment); 6158 else { 6159 FudgeInReg = 6160 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 6161 DAG.getEntryNode(), CPIdx, 6162 PseudoSourceValue::getConstantPool(), 0, 6163 MVT::f32, false, Alignment)); 6164 } 6165 6166 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 6167} 6168 6169/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 6170/// *INT_TO_FP operation of the specified operand when the target requests that 6171/// we promote it. At this point, we know that the result and operand types are 6172/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 6173/// operation that takes a larger input. 6174SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 6175 MVT DestVT, 6176 bool isSigned, 6177 DebugLoc dl) { 6178 // First step, figure out the appropriate *INT_TO_FP operation to use. 6179 MVT NewInTy = LegalOp.getValueType(); 6180 6181 unsigned OpToUse = 0; 6182 6183 // Scan for the appropriate larger type to use. 6184 while (1) { 6185 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 6186 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 6187 6188 // If the target supports SINT_TO_FP of this type, use it. 6189 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 6190 default: break; 6191 case TargetLowering::Legal: 6192 if (!TLI.isTypeLegal(NewInTy)) 6193 break; // Can't use this datatype. 6194 // FALL THROUGH. 6195 case TargetLowering::Custom: 6196 OpToUse = ISD::SINT_TO_FP; 6197 break; 6198 } 6199 if (OpToUse) break; 6200 if (isSigned) continue; 6201 6202 // If the target supports UINT_TO_FP of this type, use it. 6203 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 6204 default: break; 6205 case TargetLowering::Legal: 6206 if (!TLI.isTypeLegal(NewInTy)) 6207 break; // Can't use this datatype. 6208 // FALL THROUGH. 6209 case TargetLowering::Custom: 6210 OpToUse = ISD::UINT_TO_FP; 6211 break; 6212 } 6213 if (OpToUse) break; 6214 6215 // Otherwise, try a larger type. 6216 } 6217 6218 // Okay, we found the operation and type to use. Zero extend our input to the 6219 // desired type then run the operation on it. 6220 return DAG.getNode(OpToUse, dl, DestVT, 6221 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 6222 dl, NewInTy, LegalOp)); 6223} 6224 6225/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 6226/// FP_TO_*INT operation of the specified operand when the target requests that 6227/// we promote it. At this point, we know that the result and operand types are 6228/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 6229/// operation that returns a larger result. 6230SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 6231 MVT DestVT, 6232 bool isSigned, 6233 DebugLoc dl) { 6234 // First step, figure out the appropriate FP_TO*INT operation to use. 6235 MVT NewOutTy = DestVT; 6236 6237 unsigned OpToUse = 0; 6238 6239 // Scan for the appropriate larger type to use. 6240 while (1) { 6241 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 6242 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 6243 6244 // If the target supports FP_TO_SINT returning this type, use it. 6245 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 6246 default: break; 6247 case TargetLowering::Legal: 6248 if (!TLI.isTypeLegal(NewOutTy)) 6249 break; // Can't use this datatype. 6250 // FALL THROUGH. 6251 case TargetLowering::Custom: 6252 OpToUse = ISD::FP_TO_SINT; 6253 break; 6254 } 6255 if (OpToUse) break; 6256 6257 // If the target supports FP_TO_UINT of this type, use it. 6258 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 6259 default: break; 6260 case TargetLowering::Legal: 6261 if (!TLI.isTypeLegal(NewOutTy)) 6262 break; // Can't use this datatype. 6263 // FALL THROUGH. 6264 case TargetLowering::Custom: 6265 OpToUse = ISD::FP_TO_UINT; 6266 break; 6267 } 6268 if (OpToUse) break; 6269 6270 // Otherwise, try a larger type. 6271 } 6272 6273 6274 // Okay, we found the operation and type to use. 6275 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 6276 6277 // If the operation produces an invalid type, it must be custom lowered. Use 6278 // the target lowering hooks to expand it. Just keep the low part of the 6279 // expanded operation, we know that we're truncating anyway. 6280 if (getTypeAction(NewOutTy) == Expand) { 6281 SmallVector<SDValue, 2> Results; 6282 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG); 6283 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!"); 6284 Operation = Results[0]; 6285 } 6286 6287 // Truncate the result of the extended FP_TO_*INT operation to the desired 6288 // size. 6289 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 6290} 6291 6292/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 6293/// 6294SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 6295 MVT VT = Op.getValueType(); 6296 MVT SHVT = TLI.getShiftAmountTy(); 6297 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 6298 switch (VT.getSimpleVT()) { 6299 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 6300 case MVT::i16: 6301 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 6302 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 6303 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 6304 case MVT::i32: 6305 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 6306 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 6307 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 6308 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 6309 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 6310 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 6311 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 6312 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 6313 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 6314 case MVT::i64: 6315 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 6316 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 6317 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 6318 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 6319 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 6320 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 6321 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 6322 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 6323 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 6324 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 6325 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 6326 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 6327 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 6328 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 6329 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 6330 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 6331 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 6332 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 6333 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 6334 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 6335 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 6336 } 6337} 6338 6339/// ExpandBitCount - Expand the specified bitcount instruction into operations. 6340/// 6341SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 6342 DebugLoc dl) { 6343 switch (Opc) { 6344 default: assert(0 && "Cannot expand this yet!"); 6345 case ISD::CTPOP: { 6346 static const uint64_t mask[6] = { 6347 0x5555555555555555ULL, 0x3333333333333333ULL, 6348 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 6349 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 6350 }; 6351 MVT VT = Op.getValueType(); 6352 MVT ShVT = TLI.getShiftAmountTy(); 6353 unsigned len = VT.getSizeInBits(); 6354 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 6355 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 6356 unsigned EltSize = VT.isVector() ? 6357 VT.getVectorElementType().getSizeInBits() : len; 6358 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 6359 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 6360 Op = DAG.getNode(ISD::ADD, dl, VT, 6361 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 6362 DAG.getNode(ISD::AND, dl, VT, 6363 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 6364 Tmp2)); 6365 } 6366 return Op; 6367 } 6368 case ISD::CTLZ: { 6369 // for now, we do this: 6370 // x = x | (x >> 1); 6371 // x = x | (x >> 2); 6372 // ... 6373 // x = x | (x >>16); 6374 // x = x | (x >>32); // for 64-bit input 6375 // return popcount(~x); 6376 // 6377 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 6378 MVT VT = Op.getValueType(); 6379 MVT ShVT = TLI.getShiftAmountTy(); 6380 unsigned len = VT.getSizeInBits(); 6381 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 6382 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 6383 Op = DAG.getNode(ISD::OR, dl, VT, Op, 6384 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 6385 } 6386 Op = DAG.getNOT(dl, Op, VT); 6387 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 6388 } 6389 case ISD::CTTZ: { 6390 // for now, we use: { return popcount(~x & (x - 1)); } 6391 // unless the target has ctlz but not ctpop, in which case we use: 6392 // { return 32 - nlz(~x & (x-1)); } 6393 // see also http://www.hackersdelight.org/HDcode/ntz.cc 6394 MVT VT = Op.getValueType(); 6395 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 6396 DAG.getNOT(dl, Op, VT), 6397 DAG.getNode(ISD::SUB, dl, VT, Op, 6398 DAG.getConstant(1, VT))); 6399 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 6400 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 6401 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 6402 return DAG.getNode(ISD::SUB, dl, VT, 6403 DAG.getConstant(VT.getSizeInBits(), VT), 6404 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 6405 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 6406 } 6407 } 6408} 6409 6410/// ExpandOp - Expand the specified SDValue into its two component pieces 6411/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 6412/// LegalizedNodes map is filled in for any results that are not expanded, the 6413/// ExpandedNodes map is filled in for any results that are expanded, and the 6414/// Lo/Hi values are returned. 6415void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ 6416 MVT VT = Op.getValueType(); 6417 MVT NVT = TLI.getTypeToTransformTo(VT); 6418 SDNode *Node = Op.getNode(); 6419 DebugLoc dl = Node->getDebugLoc(); 6420 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 6421 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || 6422 VT.isVector()) && "Cannot expand to FP value or to larger int value!"); 6423 6424 // See if we already expanded it. 6425 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I 6426 = ExpandedNodes.find(Op); 6427 if (I != ExpandedNodes.end()) { 6428 Lo = I->second.first; 6429 Hi = I->second.second; 6430 return; 6431 } 6432 6433 switch (Node->getOpcode()) { 6434 case ISD::CopyFromReg: 6435 assert(0 && "CopyFromReg must be legal!"); 6436 case ISD::FP_ROUND_INREG: 6437 if (VT == MVT::ppcf128 && 6438 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 6439 TargetLowering::Custom) { 6440 SDValue SrcLo, SrcHi, Src; 6441 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 6442 Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi); 6443 SDValue Result = 6444 TLI.LowerOperation(DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src, 6445 Op.getOperand(1)), DAG); 6446 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR); 6447 Lo = Result.getNode()->getOperand(0); 6448 Hi = Result.getNode()->getOperand(1); 6449 break; 6450 } 6451 // fall through 6452 default: 6453#ifndef NDEBUG 6454 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 6455#endif 6456 assert(0 && "Do not know how to expand this operator!"); 6457 abort(); 6458 case ISD::EXTRACT_ELEMENT: 6459 ExpandOp(Node->getOperand(0), Lo, Hi); 6460 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) 6461 return ExpandOp(Hi, Lo, Hi); 6462 return ExpandOp(Lo, Lo, Hi); 6463 case ISD::EXTRACT_VECTOR_ELT: 6464 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 6465 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 6466 return ExpandOp(Lo, Lo, Hi); 6467 case ISD::UNDEF: 6468 Lo = DAG.getUNDEF(NVT); 6469 Hi = DAG.getUNDEF(NVT); 6470 break; 6471 case ISD::Constant: { 6472 unsigned NVTBits = NVT.getSizeInBits(); 6473 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 6474 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 6475 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 6476 break; 6477 } 6478 case ISD::ConstantFP: { 6479 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 6480 if (CFP->getValueType(0) == MVT::ppcf128) { 6481 APInt api = CFP->getValueAPF().bitcastToAPInt(); 6482 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 6483 MVT::f64); 6484 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 6485 MVT::f64); 6486 break; 6487 } 6488 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 6489 if (getTypeAction(Lo.getValueType()) == Expand) 6490 ExpandOp(Lo, Lo, Hi); 6491 break; 6492 } 6493 case ISD::BUILD_PAIR: 6494 // Return the operands. 6495 Lo = Node->getOperand(0); 6496 Hi = Node->getOperand(1); 6497 break; 6498 6499 case ISD::MERGE_VALUES: 6500 if (Node->getNumValues() == 1) { 6501 ExpandOp(Op.getOperand(0), Lo, Hi); 6502 break; 6503 } 6504 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 6505 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 && 6506 Op.getValue(1).getValueType() == MVT::Other && 6507 "unhandled MERGE_VALUES"); 6508 ExpandOp(Op.getOperand(0), Lo, Hi); 6509 // Remember that we legalized the chain. 6510 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 6511 break; 6512 6513 case ISD::SIGN_EXTEND_INREG: 6514 ExpandOp(Node->getOperand(0), Lo, Hi); 6515 // sext_inreg the low part if needed. 6516 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Lo, Node->getOperand(1)); 6517 6518 // The high part gets the sign extension from the lo-part. This handles 6519 // things like sextinreg V:i64 from i8. 6520 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 6521 DAG.getConstant(NVT.getSizeInBits()-1, 6522 TLI.getShiftAmountTy())); 6523 break; 6524 6525 case ISD::BSWAP: { 6526 ExpandOp(Node->getOperand(0), Lo, Hi); 6527 SDValue TempLo = DAG.getNode(ISD::BSWAP, dl, NVT, Hi); 6528 Hi = DAG.getNode(ISD::BSWAP, dl, NVT, Lo); 6529 Lo = TempLo; 6530 break; 6531 } 6532 6533 case ISD::CTPOP: 6534 ExpandOp(Node->getOperand(0), Lo, Hi); 6535 Lo = DAG.getNode(ISD::ADD, dl, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 6536 DAG.getNode(ISD::CTPOP, dl, NVT, Lo), 6537 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); 6538 Hi = DAG.getConstant(0, NVT); 6539 break; 6540 6541 case ISD::CTLZ: { 6542 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 6543 ExpandOp(Node->getOperand(0), Lo, Hi); 6544 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 6545 SDValue HLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi); 6546 SDValue TopNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), HLZ, 6547 BitsC, ISD::SETNE); 6548 SDValue LowPart = DAG.getNode(ISD::CTLZ, dl, NVT, Lo); 6549 LowPart = DAG.getNode(ISD::ADD, dl, NVT, LowPart, BitsC); 6550 6551 Lo = DAG.getNode(ISD::SELECT, dl, NVT, TopNotZero, HLZ, LowPart); 6552 Hi = DAG.getConstant(0, NVT); 6553 break; 6554 } 6555 6556 case ISD::CTTZ: { 6557 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 6558 ExpandOp(Node->getOperand(0), Lo, Hi); 6559 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 6560 SDValue LTZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); 6561 SDValue BotNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), LTZ, 6562 BitsC, ISD::SETNE); 6563 SDValue HiPart = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); 6564 HiPart = DAG.getNode(ISD::ADD, dl, NVT, HiPart, BitsC); 6565 6566 Lo = DAG.getNode(ISD::SELECT, dl, NVT, BotNotZero, LTZ, HiPart); 6567 Hi = DAG.getConstant(0, NVT); 6568 break; 6569 } 6570 6571 case ISD::VAARG: { 6572 SDValue Ch = Node->getOperand(0); // Legalize the chain. 6573 SDValue Ptr = Node->getOperand(1); // Legalize the pointer. 6574 Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2)); 6575 Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2)); 6576 6577 // Remember that we legalized the chain. 6578 Hi = LegalizeOp(Hi); 6579 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 6580 if (TLI.isBigEndian()) 6581 std::swap(Lo, Hi); 6582 break; 6583 } 6584 6585 case ISD::LOAD: { 6586 LoadSDNode *LD = cast<LoadSDNode>(Node); 6587 SDValue Ch = LD->getChain(); // Legalize the chain. 6588 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer. 6589 ISD::LoadExtType ExtType = LD->getExtensionType(); 6590 const Value *SV = LD->getSrcValue(); 6591 int SVOffset = LD->getSrcValueOffset(); 6592 unsigned Alignment = LD->getAlignment(); 6593 bool isVolatile = LD->isVolatile(); 6594 6595 if (ExtType == ISD::NON_EXTLOAD) { 6596 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset, 6597 isVolatile, Alignment); 6598 if (VT == MVT::f32 || VT == MVT::f64) { 6599 // f32->i32 or f64->i64 one to one expansion. 6600 // Remember that we legalized the chain. 6601 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 6602 // Recursively expand the new load. 6603 if (getTypeAction(NVT) == Expand) 6604 ExpandOp(Lo, Lo, Hi); 6605 break; 6606 } 6607 6608 // Increment the pointer to the other half. 6609 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 6610 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 6611 DAG.getIntPtrConstant(IncrementSize)); 6612 SVOffset += IncrementSize; 6613 Alignment = MinAlign(Alignment, IncrementSize); 6614 Hi = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset, 6615 isVolatile, Alignment); 6616 6617 // Build a factor node to remember that this load is independent of the 6618 // other one. 6619 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 6620 Hi.getValue(1)); 6621 6622 // Remember that we legalized the chain. 6623 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6624 if (TLI.isBigEndian()) 6625 std::swap(Lo, Hi); 6626 } else { 6627 MVT EVT = LD->getMemoryVT(); 6628 6629 if ((VT == MVT::f64 && EVT == MVT::f32) || 6630 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 6631 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 6632 SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV, 6633 SVOffset, isVolatile, Alignment); 6634 // Remember that we legalized the chain. 6635 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1))); 6636 ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi); 6637 break; 6638 } 6639 6640 if (EVT == NVT) 6641 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, 6642 SVOffset, isVolatile, Alignment); 6643 else 6644 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, SV, 6645 SVOffset, EVT, isVolatile, 6646 Alignment); 6647 6648 // Remember that we legalized the chain. 6649 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 6650 6651 if (ExtType == ISD::SEXTLOAD) { 6652 // The high part is obtained by SRA'ing all but one of the bits of the 6653 // lo part. 6654 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6655 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 6656 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6657 } else if (ExtType == ISD::ZEXTLOAD) { 6658 // The high part is just a zero. 6659 Hi = DAG.getConstant(0, NVT); 6660 } else /* if (ExtType == ISD::EXTLOAD) */ { 6661 // The high part is undefined. 6662 Hi = DAG.getUNDEF(NVT); 6663 } 6664 } 6665 break; 6666 } 6667 case ISD::AND: 6668 case ISD::OR: 6669 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6670 SDValue LL, LH, RL, RH; 6671 ExpandOp(Node->getOperand(0), LL, LH); 6672 ExpandOp(Node->getOperand(1), RL, RH); 6673 Lo = DAG.getNode(Node->getOpcode(), dl, NVT, LL, RL); 6674 Hi = DAG.getNode(Node->getOpcode(), dl, NVT, LH, RH); 6675 break; 6676 } 6677 case ISD::SELECT: { 6678 SDValue LL, LH, RL, RH; 6679 ExpandOp(Node->getOperand(1), LL, LH); 6680 ExpandOp(Node->getOperand(2), RL, RH); 6681 if (getTypeAction(NVT) == Expand) 6682 NVT = TLI.getTypeToExpandTo(NVT); 6683 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LL, RL); 6684 if (VT != MVT::f32) 6685 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LH, RH); 6686 break; 6687 } 6688 case ISD::SELECT_CC: { 6689 SDValue TL, TH, FL, FH; 6690 ExpandOp(Node->getOperand(2), TL, TH); 6691 ExpandOp(Node->getOperand(3), FL, FH); 6692 if (getTypeAction(NVT) == Expand) 6693 NVT = TLI.getTypeToExpandTo(NVT); 6694 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0), 6695 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6696 if (VT != MVT::f32) 6697 Hi = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0), 6698 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6699 break; 6700 } 6701 case ISD::ANY_EXTEND: 6702 // The low part is any extension of the input (which degenerates to a copy). 6703 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0)); 6704 // The high part is undefined. 6705 Hi = DAG.getUNDEF(NVT); 6706 break; 6707 case ISD::SIGN_EXTEND: { 6708 // The low part is just a sign extension of the input (which degenerates to 6709 // a copy). 6710 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(0)); 6711 6712 // The high part is obtained by SRA'ing all but one of the bits of the lo 6713 // part. 6714 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6715 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 6716 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6717 break; 6718 } 6719 case ISD::ZERO_EXTEND: 6720 // The low part is just a zero extension of the input (which degenerates to 6721 // a copy). 6722 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 6723 6724 // The high part is just a zero. 6725 Hi = DAG.getConstant(0, NVT); 6726 break; 6727 6728 case ISD::TRUNCATE: { 6729 // The input value must be larger than this value. Expand *it*. 6730 SDValue NewLo; 6731 ExpandOp(Node->getOperand(0), NewLo, Hi); 6732 6733 // The low part is now either the right size, or it is closer. If not the 6734 // right size, make an illegal truncate so we recursively expand it. 6735 if (NewLo.getValueType() != Node->getValueType(0)) 6736 NewLo = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), NewLo); 6737 ExpandOp(NewLo, Lo, Hi); 6738 break; 6739 } 6740 6741 case ISD::BIT_CONVERT: { 6742 SDValue Tmp; 6743 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6744 // If the target wants to, allow it to lower this itself. 6745 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6746 case Expand: assert(0 && "cannot expand FP!"); 6747 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6748 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6749 } 6750 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp), DAG); 6751 } 6752 6753 // f32 / f64 must be expanded to i32 / i64. 6754 if (VT == MVT::f32 || VT == MVT::f64) { 6755 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 6756 if (getTypeAction(NVT) == Expand) 6757 ExpandOp(Lo, Lo, Hi); 6758 break; 6759 } 6760 6761 // If source operand will be expanded to the same type as VT, i.e. 6762 // i64 <- f64, i32 <- f32, expand the source operand instead. 6763 MVT VT0 = Node->getOperand(0).getValueType(); 6764 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6765 ExpandOp(Node->getOperand(0), Lo, Hi); 6766 break; 6767 } 6768 6769 // Turn this into a load/store pair by default. 6770 if (Tmp.getNode() == 0) 6771 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT, dl); 6772 6773 ExpandOp(Tmp, Lo, Hi); 6774 break; 6775 } 6776 6777 case ISD::READCYCLECOUNTER: { 6778 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6779 TargetLowering::Custom && 6780 "Must custom expand ReadCycleCounter"); 6781 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6782 assert(Tmp.getNode() && "Node must be custom expanded!"); 6783 ExpandOp(Tmp.getValue(0), Lo, Hi); 6784 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6785 LegalizeOp(Tmp.getValue(1))); 6786 break; 6787 } 6788 6789 case ISD::ATOMIC_CMP_SWAP: { 6790 // This operation does not need a loop. 6791 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6792 assert(Tmp.getNode() && "Node must be custom expanded!"); 6793 ExpandOp(Tmp.getValue(0), Lo, Hi); 6794 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6795 LegalizeOp(Tmp.getValue(1))); 6796 break; 6797 } 6798 6799 case ISD::ATOMIC_LOAD_ADD: 6800 case ISD::ATOMIC_LOAD_SUB: 6801 case ISD::ATOMIC_LOAD_AND: 6802 case ISD::ATOMIC_LOAD_OR: 6803 case ISD::ATOMIC_LOAD_XOR: 6804 case ISD::ATOMIC_LOAD_NAND: 6805 case ISD::ATOMIC_SWAP: { 6806 // These operations require a loop to be generated. We can't do that yet, 6807 // so substitute a target-dependent pseudo and expand that later. 6808 SDValue In2Lo, In2Hi, In2; 6809 ExpandOp(Op.getOperand(2), In2Lo, In2Hi); 6810 In2 = DAG.getNode(ISD::BUILD_PAIR, dl, VT, In2Lo, In2Hi); 6811 AtomicSDNode* Anode = cast<AtomicSDNode>(Node); 6812 SDValue Replace = 6813 DAG.getAtomic(Op.getOpcode(), dl, Anode->getMemoryVT(), 6814 Op.getOperand(0), Op.getOperand(1), In2, 6815 Anode->getSrcValue(), Anode->getAlignment()); 6816 SDValue Result = TLI.LowerOperation(Replace, DAG); 6817 ExpandOp(Result.getValue(0), Lo, Hi); 6818 // Remember that we legalized the chain. 6819 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Result.getValue(1))); 6820 break; 6821 } 6822 6823 // These operators cannot be expanded directly, emit them as calls to 6824 // library functions. 6825 case ISD::FP_TO_SINT: { 6826 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6827 SDValue Op; 6828 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6829 case Expand: assert(0 && "cannot expand FP!"); 6830 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6831 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6832 } 6833 6834 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op), DAG); 6835 6836 // Now that the custom expander is done, expand the result, which is still 6837 // VT. 6838 if (Op.getNode()) { 6839 ExpandOp(Op, Lo, Hi); 6840 break; 6841 } 6842 } 6843 6844 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(), 6845 VT); 6846 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!"); 6847 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6848 break; 6849 } 6850 6851 case ISD::FP_TO_UINT: { 6852 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6853 SDValue Op; 6854 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6855 case Expand: assert(0 && "cannot expand FP!"); 6856 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6857 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6858 } 6859 6860 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op), DAG); 6861 6862 // Now that the custom expander is done, expand the result. 6863 if (Op.getNode()) { 6864 ExpandOp(Op, Lo, Hi); 6865 break; 6866 } 6867 } 6868 6869 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(), 6870 VT); 6871 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 6872 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6873 break; 6874 } 6875 6876 case ISD::SHL: { 6877 // If the target wants custom lowering, do so. 6878 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6879 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6880 SDValue Op = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftAmt); 6881 Op = TLI.LowerOperation(Op, DAG); 6882 if (Op.getNode()) { 6883 // Now that the custom expander is done, expand the result, which is 6884 // still VT. 6885 ExpandOp(Op, Lo, Hi); 6886 break; 6887 } 6888 } 6889 6890 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6891 // this X << 1 as X+X. 6892 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6893 if (ShAmt->getAPIntValue() == 1 && 6894 TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) && 6895 TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) { 6896 SDValue LoOps[2], HiOps[3]; 6897 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6898 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6899 LoOps[1] = LoOps[0]; 6900 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 6901 6902 HiOps[1] = HiOps[0]; 6903 HiOps[2] = Lo.getValue(1); 6904 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 6905 break; 6906 } 6907 } 6908 6909 // If we can emit an efficient shift operation, do so now. 6910 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl)) 6911 break; 6912 6913 // If this target supports SHL_PARTS, use it. 6914 TargetLowering::LegalizeAction Action = 6915 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6916 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6917 Action == TargetLowering::Custom) { 6918 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), 6919 ShiftAmt, Lo, Hi, dl); 6920 break; 6921 } 6922 6923 // Otherwise, emit a libcall. 6924 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6925 break; 6926 } 6927 6928 case ISD::SRA: { 6929 // If the target wants custom lowering, do so. 6930 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6931 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6932 SDValue Op = DAG.getNode(ISD::SRA, dl, VT, Node->getOperand(0), ShiftAmt); 6933 Op = TLI.LowerOperation(Op, DAG); 6934 if (Op.getNode()) { 6935 // Now that the custom expander is done, expand the result, which is 6936 // still VT. 6937 ExpandOp(Op, Lo, Hi); 6938 break; 6939 } 6940 } 6941 6942 // If we can emit an efficient shift operation, do so now. 6943 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl)) 6944 break; 6945 6946 // If this target supports SRA_PARTS, use it. 6947 TargetLowering::LegalizeAction Action = 6948 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6949 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6950 Action == TargetLowering::Custom) { 6951 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), 6952 ShiftAmt, Lo, Hi, dl); 6953 break; 6954 } 6955 6956 // Otherwise, emit a libcall. 6957 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6958 break; 6959 } 6960 6961 case ISD::SRL: { 6962 // If the target wants custom lowering, do so. 6963 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6964 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6965 SDValue Op = DAG.getNode(ISD::SRL, dl, VT, Node->getOperand(0), ShiftAmt); 6966 Op = TLI.LowerOperation(Op, DAG); 6967 if (Op.getNode()) { 6968 // Now that the custom expander is done, expand the result, which is 6969 // still VT. 6970 ExpandOp(Op, Lo, Hi); 6971 break; 6972 } 6973 } 6974 6975 // If we can emit an efficient shift operation, do so now. 6976 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl)) 6977 break; 6978 6979 // If this target supports SRL_PARTS, use it. 6980 TargetLowering::LegalizeAction Action = 6981 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6982 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6983 Action == TargetLowering::Custom) { 6984 ExpandShiftParts(ISD::SRL_PARTS, 6985 Node->getOperand(0), ShiftAmt, Lo, Hi, dl); 6986 break; 6987 } 6988 6989 // Otherwise, emit a libcall. 6990 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6991 break; 6992 } 6993 6994 case ISD::ADD: 6995 case ISD::SUB: { 6996 // If the target wants to custom expand this, let them. 6997 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6998 TargetLowering::Custom) { 6999 SDValue Result = TLI.LowerOperation(Op, DAG); 7000 if (Result.getNode()) { 7001 ExpandOp(Result, Lo, Hi); 7002 break; 7003 } 7004 } 7005 // Expand the subcomponents. 7006 SDValue LHSL, LHSH, RHSL, RHSH; 7007 ExpandOp(Node->getOperand(0), LHSL, LHSH); 7008 ExpandOp(Node->getOperand(1), RHSL, RHSH); 7009 SDValue LoOps[2], HiOps[3]; 7010 LoOps[0] = LHSL; 7011 LoOps[1] = RHSL; 7012 HiOps[0] = LHSH; 7013 HiOps[1] = RHSH; 7014 7015 //cascaded check to see if any smaller size has a a carry flag. 7016 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC; 7017 bool hasCarry = false; 7018 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) { 7019 MVT AVT = MVT::getIntegerVT(BitSize); 7020 if (TLI.isOperationLegalOrCustom(OpV, AVT)) { 7021 hasCarry = true; 7022 break; 7023 } 7024 } 7025 7026 if(hasCarry) { 7027 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 7028 if (Node->getOpcode() == ISD::ADD) { 7029 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 7030 HiOps[2] = Lo.getValue(1); 7031 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 7032 } else { 7033 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 7034 HiOps[2] = Lo.getValue(1); 7035 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 7036 } 7037 break; 7038 } else { 7039 if (Node->getOpcode() == ISD::ADD) { 7040 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); 7041 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); 7042 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 7043 Lo, LoOps[0], ISD::SETULT); 7044 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, 7045 DAG.getConstant(1, NVT), 7046 DAG.getConstant(0, NVT)); 7047 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 7048 Lo, LoOps[1], ISD::SETULT); 7049 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, 7050 DAG.getConstant(1, NVT), 7051 Carry1); 7052 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); 7053 } else { 7054 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 7055 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); 7056 SDValue Cmp = DAG.getSetCC(dl, NVT, LoOps[0], LoOps[1], ISD::SETULT); 7057 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, 7058 DAG.getConstant(1, NVT), 7059 DAG.getConstant(0, NVT)); 7060 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); 7061 } 7062 break; 7063 } 7064 } 7065 7066 case ISD::ADDC: 7067 case ISD::SUBC: { 7068 // Expand the subcomponents. 7069 SDValue LHSL, LHSH, RHSL, RHSH; 7070 ExpandOp(Node->getOperand(0), LHSL, LHSH); 7071 ExpandOp(Node->getOperand(1), RHSL, RHSH); 7072 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 7073 SDValue LoOps[2] = { LHSL, RHSL }; 7074 SDValue HiOps[3] = { LHSH, RHSH }; 7075 7076 if (Node->getOpcode() == ISD::ADDC) { 7077 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 7078 HiOps[2] = Lo.getValue(1); 7079 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 7080 } else { 7081 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 7082 HiOps[2] = Lo.getValue(1); 7083 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 7084 } 7085 // Remember that we legalized the flag. 7086 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 7087 break; 7088 } 7089 case ISD::ADDE: 7090 case ISD::SUBE: { 7091 // Expand the subcomponents. 7092 SDValue LHSL, LHSH, RHSL, RHSH; 7093 ExpandOp(Node->getOperand(0), LHSL, LHSH); 7094 ExpandOp(Node->getOperand(1), RHSL, RHSH); 7095 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 7096 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 7097 SDValue HiOps[3] = { LHSH, RHSH }; 7098 7099 Lo = DAG.getNode(Node->getOpcode(), dl, VTList, LoOps, 3); 7100 HiOps[2] = Lo.getValue(1); 7101 Hi = DAG.getNode(Node->getOpcode(), dl, VTList, HiOps, 3); 7102 7103 // Remember that we legalized the flag. 7104 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 7105 break; 7106 } 7107 case ISD::MUL: { 7108 // If the target wants to custom expand this, let them. 7109 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 7110 SDValue New = TLI.LowerOperation(Op, DAG); 7111 if (New.getNode()) { 7112 ExpandOp(New, Lo, Hi); 7113 break; 7114 } 7115 } 7116 7117 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 7118 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 7119 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 7120 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 7121 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 7122 SDValue LL, LH, RL, RH; 7123 ExpandOp(Node->getOperand(0), LL, LH); 7124 ExpandOp(Node->getOperand(1), RL, RH); 7125 unsigned OuterBitSize = Op.getValueSizeInBits(); 7126 unsigned InnerBitSize = RH.getValueSizeInBits(); 7127 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 7128 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 7129 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 7130 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 7131 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 7132 // The inputs are both zero-extended. 7133 if (HasUMUL_LOHI) { 7134 // We can emit a umul_lohi. 7135 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 7136 Hi = SDValue(Lo.getNode(), 1); 7137 break; 7138 } 7139 if (HasMULHU) { 7140 // We can emit a mulhu+mul. 7141 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 7142 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 7143 break; 7144 } 7145 } 7146 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 7147 // The input values are both sign-extended. 7148 if (HasSMUL_LOHI) { 7149 // We can emit a smul_lohi. 7150 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 7151 Hi = SDValue(Lo.getNode(), 1); 7152 break; 7153 } 7154 if (HasMULHS) { 7155 // We can emit a mulhs+mul. 7156 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 7157 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); 7158 break; 7159 } 7160 } 7161 if (HasUMUL_LOHI) { 7162 // Lo,Hi = umul LHS, RHS. 7163 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 7164 DAG.getVTList(NVT, NVT), LL, RL); 7165 Lo = UMulLOHI; 7166 Hi = UMulLOHI.getValue(1); 7167 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 7168 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 7169 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 7170 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 7171 break; 7172 } 7173 if (HasMULHU) { 7174 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 7175 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 7176 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 7177 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 7178 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 7179 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 7180 break; 7181 } 7182 } 7183 7184 // If nothing else, we can make a libcall. 7185 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 7186 break; 7187 } 7188 case ISD::SDIV: 7189 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 7190 break; 7191 case ISD::UDIV: 7192 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 7193 break; 7194 case ISD::SREM: 7195 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 7196 break; 7197 case ISD::UREM: 7198 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 7199 break; 7200 7201 case ISD::FADD: 7202 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 7203 RTLIB::ADD_F64, 7204 RTLIB::ADD_F80, 7205 RTLIB::ADD_PPCF128), 7206 Node, false, Hi); 7207 break; 7208 case ISD::FSUB: 7209 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 7210 RTLIB::SUB_F64, 7211 RTLIB::SUB_F80, 7212 RTLIB::SUB_PPCF128), 7213 Node, false, Hi); 7214 break; 7215 case ISD::FMUL: 7216 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 7217 RTLIB::MUL_F64, 7218 RTLIB::MUL_F80, 7219 RTLIB::MUL_PPCF128), 7220 Node, false, Hi); 7221 break; 7222 case ISD::FDIV: 7223 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 7224 RTLIB::DIV_F64, 7225 RTLIB::DIV_F80, 7226 RTLIB::DIV_PPCF128), 7227 Node, false, Hi); 7228 break; 7229 case ISD::FP_EXTEND: { 7230 if (VT == MVT::ppcf128) { 7231 assert(Node->getOperand(0).getValueType()==MVT::f32 || 7232 Node->getOperand(0).getValueType()==MVT::f64); 7233 const uint64_t zero = 0; 7234 if (Node->getOperand(0).getValueType()==MVT::f32) 7235 Hi = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Node->getOperand(0)); 7236 else 7237 Hi = Node->getOperand(0); 7238 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7239 break; 7240 } 7241 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT); 7242 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!"); 7243 Lo = ExpandLibCall(LC, Node, true, Hi); 7244 break; 7245 } 7246 case ISD::FP_ROUND: { 7247 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(), 7248 VT); 7249 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!"); 7250 Lo = ExpandLibCall(LC, Node, true, Hi); 7251 break; 7252 } 7253 case ISD::FSQRT: 7254 case ISD::FSIN: 7255 case ISD::FCOS: 7256 case ISD::FLOG: 7257 case ISD::FLOG2: 7258 case ISD::FLOG10: 7259 case ISD::FEXP: 7260 case ISD::FEXP2: 7261 case ISD::FTRUNC: 7262 case ISD::FFLOOR: 7263 case ISD::FCEIL: 7264 case ISD::FRINT: 7265 case ISD::FNEARBYINT: 7266 case ISD::FPOW: 7267 case ISD::FPOWI: { 7268 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 7269 switch(Node->getOpcode()) { 7270 case ISD::FSQRT: 7271 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 7272 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 7273 break; 7274 case ISD::FSIN: 7275 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 7276 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 7277 break; 7278 case ISD::FCOS: 7279 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 7280 RTLIB::COS_F80, RTLIB::COS_PPCF128); 7281 break; 7282 case ISD::FLOG: 7283 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64, 7284 RTLIB::LOG_F80, RTLIB::LOG_PPCF128); 7285 break; 7286 case ISD::FLOG2: 7287 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 7288 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128); 7289 break; 7290 case ISD::FLOG10: 7291 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 7292 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128); 7293 break; 7294 case ISD::FEXP: 7295 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64, 7296 RTLIB::EXP_F80, RTLIB::EXP_PPCF128); 7297 break; 7298 case ISD::FEXP2: 7299 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 7300 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128); 7301 break; 7302 case ISD::FTRUNC: 7303 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 7304 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 7305 break; 7306 case ISD::FFLOOR: 7307 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 7308 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 7309 break; 7310 case ISD::FCEIL: 7311 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 7312 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 7313 break; 7314 case ISD::FRINT: 7315 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 7316 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 7317 break; 7318 case ISD::FNEARBYINT: 7319 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 7320 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 7321 break; 7322 case ISD::FPOW: 7323 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 7324 RTLIB::POW_PPCF128); 7325 break; 7326 case ISD::FPOWI: 7327 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80, 7328 RTLIB::POWI_PPCF128); 7329 break; 7330 default: assert(0 && "Unreachable!"); 7331 } 7332 Lo = ExpandLibCall(LC, Node, false, Hi); 7333 break; 7334 } 7335 case ISD::FABS: { 7336 if (VT == MVT::ppcf128) { 7337 SDValue Tmp; 7338 ExpandOp(Node->getOperand(0), Lo, Tmp); 7339 Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp); 7340 // lo = hi==fabs(hi) ? lo : -lo; 7341 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp, 7342 Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo), 7343 DAG.getCondCode(ISD::SETEQ)); 7344 break; 7345 } 7346 SDValue Mask = (VT == MVT::f64) 7347 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 7348 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 7349 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask); 7350 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 7351 Lo = DAG.getNode(ISD::AND, dl, NVT, Lo, Mask); 7352 if (getTypeAction(NVT) == Expand) 7353 ExpandOp(Lo, Lo, Hi); 7354 break; 7355 } 7356 case ISD::FNEG: { 7357 if (VT == MVT::ppcf128) { 7358 ExpandOp(Node->getOperand(0), Lo, Hi); 7359 Lo = DAG.getNode(ISD::FNEG, dl, MVT::f64, Lo); 7360 Hi = DAG.getNode(ISD::FNEG, dl, MVT::f64, Hi); 7361 break; 7362 } 7363 SDValue Mask = (VT == MVT::f64) 7364 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 7365 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 7366 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask); 7367 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 7368 Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Mask); 7369 if (getTypeAction(NVT) == Expand) 7370 ExpandOp(Lo, Lo, Hi); 7371 break; 7372 } 7373 case ISD::FCOPYSIGN: { 7374 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 7375 if (getTypeAction(NVT) == Expand) 7376 ExpandOp(Lo, Lo, Hi); 7377 break; 7378 } 7379 case ISD::SINT_TO_FP: 7380 case ISD::UINT_TO_FP: { 7381 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 7382 MVT SrcVT = Node->getOperand(0).getValueType(); 7383 7384 // Promote the operand if needed. Do this before checking for 7385 // ppcf128 so conversions of i16 and i8 work. 7386 if (getTypeAction(SrcVT) == Promote) { 7387 SDValue Tmp = PromoteOp(Node->getOperand(0)); 7388 Tmp = isSigned 7389 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp.getValueType(), Tmp, 7390 DAG.getValueType(SrcVT)) 7391 : DAG.getZeroExtendInReg(Tmp, dl, SrcVT); 7392 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode(); 7393 SrcVT = Node->getOperand(0).getValueType(); 7394 } 7395 7396 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 7397 static const uint64_t zero = 0; 7398 if (isSigned) { 7399 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64, 7400 Node->getOperand(0))); 7401 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7402 } else { 7403 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 7404 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64, 7405 Node->getOperand(0))); 7406 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7407 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi); 7408 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 7409 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, 7410 MVT::ppcf128, Node->getOperand(0), 7411 DAG.getConstant(0, MVT::i32), 7412 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi, 7413 DAG.getConstantFP 7414 (APFloat(APInt(128, 2, TwoE32)), 7415 MVT::ppcf128)), 7416 Hi, 7417 DAG.getCondCode(ISD::SETLT)), 7418 Lo, Hi); 7419 } 7420 break; 7421 } 7422 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 7423 // si64->ppcf128 done by libcall, below 7424 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 7425 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::ppcf128, 7426 Node->getOperand(0)), Lo, Hi); 7427 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi); 7428 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 7429 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, MVT::ppcf128, 7430 Node->getOperand(0), 7431 DAG.getConstant(0, MVT::i64), 7432 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi, 7433 DAG.getConstantFP 7434 (APFloat(APInt(128, 2, TwoE64)), 7435 MVT::ppcf128)), 7436 Hi, 7437 DAG.getCondCode(ISD::SETLT)), 7438 Lo, Hi); 7439 break; 7440 } 7441 7442 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 7443 Node->getOperand(0), dl); 7444 if (getTypeAction(Lo.getValueType()) == Expand) 7445 // float to i32 etc. can be 'expanded' to a single node. 7446 ExpandOp(Lo, Lo, Hi); 7447 break; 7448 } 7449 } 7450 7451 // Make sure the resultant values have been legalized themselves, unless this 7452 // is a type that requires multi-step expansion. 7453 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 7454 Lo = LegalizeOp(Lo); 7455 if (Hi.getNode()) 7456 // Don't legalize the high part if it is expanded to a single node. 7457 Hi = LegalizeOp(Hi); 7458 } 7459 7460 // Remember in a map if the values will be reused later. 7461 bool isNew = 7462 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7463 assert(isNew && "Value already expanded?!?"); 7464 isNew = isNew; 7465} 7466 7467/// SplitVectorOp - Given an operand of vector type, break it down into 7468/// two smaller values, still of vector type. 7469void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo, 7470 SDValue &Hi) { 7471 assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); 7472 SDNode *Node = Op.getNode(); 7473 DebugLoc dl = Node->getDebugLoc(); 7474 unsigned NumElements = Op.getValueType().getVectorNumElements(); 7475 assert(NumElements > 1 && "Cannot split a single element vector!"); 7476 7477 MVT NewEltVT = Op.getValueType().getVectorElementType(); 7478 7479 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 7480 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 7481 7482 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); 7483 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); 7484 7485 // See if we already split it. 7486 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I 7487 = SplitNodes.find(Op); 7488 if (I != SplitNodes.end()) { 7489 Lo = I->second.first; 7490 Hi = I->second.second; 7491 return; 7492 } 7493 7494 switch (Node->getOpcode()) { 7495 default: 7496#ifndef NDEBUG 7497 Node->dump(&DAG); 7498#endif 7499 assert(0 && "Unhandled operation in SplitVectorOp!"); 7500 case ISD::UNDEF: 7501 Lo = DAG.getUNDEF(NewVT_Lo); 7502 Hi = DAG.getUNDEF(NewVT_Hi); 7503 break; 7504 case ISD::BUILD_PAIR: 7505 Lo = Node->getOperand(0); 7506 Hi = Node->getOperand(1); 7507 break; 7508 case ISD::INSERT_VECTOR_ELT: { 7509 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 7510 SplitVectorOp(Node->getOperand(0), Lo, Hi); 7511 unsigned Index = Idx->getZExtValue(); 7512 SDValue ScalarOp = Node->getOperand(1); 7513 if (Index < NewNumElts_Lo) 7514 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Lo, Lo, ScalarOp, 7515 DAG.getIntPtrConstant(Index)); 7516 else 7517 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Hi, Hi, ScalarOp, 7518 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 7519 break; 7520 } 7521 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 7522 Node->getOperand(1), 7523 Node->getOperand(2), dl); 7524 SplitVectorOp(Tmp, Lo, Hi); 7525 break; 7526 } 7527 case ISD::VECTOR_SHUFFLE: { 7528 // Build the low part. 7529 SDValue Mask = Node->getOperand(2); 7530 SmallVector<SDValue, 8> Ops; 7531 MVT PtrVT = TLI.getPointerTy(); 7532 7533 // Insert all of the elements from the input that are needed. We use 7534 // buildvector of extractelement here because the input vectors will have 7535 // to be legalized, so this makes the code simpler. 7536 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 7537 SDValue IdxNode = Mask.getOperand(i); 7538 if (IdxNode.getOpcode() == ISD::UNDEF) { 7539 Ops.push_back(DAG.getUNDEF(NewEltVT)); 7540 continue; 7541 } 7542 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); 7543 SDValue InVec = Node->getOperand(0); 7544 if (Idx >= NumElements) { 7545 InVec = Node->getOperand(1); 7546 Idx -= NumElements; 7547 } 7548 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec, 7549 DAG.getConstant(Idx, PtrVT))); 7550 } 7551 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &Ops[0], Ops.size()); 7552 Ops.clear(); 7553 7554 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 7555 SDValue IdxNode = Mask.getOperand(i); 7556 if (IdxNode.getOpcode() == ISD::UNDEF) { 7557 Ops.push_back(DAG.getUNDEF(NewEltVT)); 7558 continue; 7559 } 7560 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); 7561 SDValue InVec = Node->getOperand(0); 7562 if (Idx >= NumElements) { 7563 InVec = Node->getOperand(1); 7564 Idx -= NumElements; 7565 } 7566 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec, 7567 DAG.getConstant(Idx, PtrVT))); 7568 } 7569 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &Ops[0], Ops.size()); 7570 break; 7571 } 7572 case ISD::BUILD_VECTOR: { 7573 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 7574 Node->op_begin()+NewNumElts_Lo); 7575 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &LoOps[0], LoOps.size()); 7576 7577 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 7578 Node->op_end()); 7579 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &HiOps[0], HiOps.size()); 7580 break; 7581 } 7582 case ISD::CONCAT_VECTORS: { 7583 // FIXME: Handle non-power-of-two vectors? 7584 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 7585 if (NewNumSubvectors == 1) { 7586 Lo = Node->getOperand(0); 7587 Hi = Node->getOperand(1); 7588 } else { 7589 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 7590 Node->op_begin()+NewNumSubvectors); 7591 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo, 7592 &LoOps[0], LoOps.size()); 7593 7594 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors, 7595 Node->op_end()); 7596 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi, 7597 &HiOps[0], HiOps.size()); 7598 } 7599 break; 7600 } 7601 case ISD::EXTRACT_SUBVECTOR: { 7602 SDValue Vec = Op.getOperand(0); 7603 SDValue Idx = Op.getOperand(1); 7604 MVT IdxVT = Idx.getValueType(); 7605 7606 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx); 7607 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx); 7608 if (CIdx) { 7609 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, 7610 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo, 7611 IdxVT)); 7612 } else { 7613 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx, 7614 DAG.getConstant(NewNumElts_Lo, IdxVT)); 7615 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, Idx); 7616 } 7617 break; 7618 } 7619 case ISD::SELECT: { 7620 SDValue Cond = Node->getOperand(0); 7621 7622 SDValue LL, LH, RL, RH; 7623 SplitVectorOp(Node->getOperand(1), LL, LH); 7624 SplitVectorOp(Node->getOperand(2), RL, RH); 7625 7626 if (Cond.getValueType().isVector()) { 7627 // Handle a vector merge. 7628 SDValue CL, CH; 7629 SplitVectorOp(Cond, CL, CH); 7630 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, CL, LL, RL); 7631 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, CH, LH, RH); 7632 } else { 7633 // Handle a simple select with vector operands. 7634 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, Cond, LL, RL); 7635 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, Cond, LH, RH); 7636 } 7637 break; 7638 } 7639 case ISD::SELECT_CC: { 7640 SDValue CondLHS = Node->getOperand(0); 7641 SDValue CondRHS = Node->getOperand(1); 7642 SDValue CondCode = Node->getOperand(4); 7643 7644 SDValue LL, LH, RL, RH; 7645 SplitVectorOp(Node->getOperand(2), LL, LH); 7646 SplitVectorOp(Node->getOperand(3), RL, RH); 7647 7648 // Handle a simple select with vector operands. 7649 Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS, 7650 LL, RL, CondCode); 7651 Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS, 7652 LH, RH, CondCode); 7653 break; 7654 } 7655 case ISD::VSETCC: { 7656 SDValue LL, LH, RL, RH; 7657 SplitVectorOp(Node->getOperand(0), LL, LH); 7658 SplitVectorOp(Node->getOperand(1), RL, RH); 7659 Lo = DAG.getNode(ISD::VSETCC, dl, NewVT_Lo, LL, RL, Node->getOperand(2)); 7660 Hi = DAG.getNode(ISD::VSETCC, dl, NewVT_Hi, LH, RH, Node->getOperand(2)); 7661 break; 7662 } 7663 case ISD::ADD: 7664 case ISD::SUB: 7665 case ISD::MUL: 7666 case ISD::FADD: 7667 case ISD::FSUB: 7668 case ISD::FMUL: 7669 case ISD::SDIV: 7670 case ISD::UDIV: 7671 case ISD::FDIV: 7672 case ISD::FPOW: 7673 case ISD::AND: 7674 case ISD::OR: 7675 case ISD::XOR: 7676 case ISD::UREM: 7677 case ISD::SREM: 7678 case ISD::FREM: 7679 case ISD::SHL: 7680 case ISD::SRA: 7681 case ISD::SRL: { 7682 SDValue LL, LH, RL, RH; 7683 SplitVectorOp(Node->getOperand(0), LL, LH); 7684 SplitVectorOp(Node->getOperand(1), RL, RH); 7685 7686 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL); 7687 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH); 7688 break; 7689 } 7690 case ISD::FP_ROUND: 7691 case ISD::FPOWI: { 7692 SDValue L, H; 7693 SplitVectorOp(Node->getOperand(0), L, H); 7694 7695 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L, Node->getOperand(1)); 7696 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H, Node->getOperand(1)); 7697 break; 7698 } 7699 case ISD::CTTZ: 7700 case ISD::CTLZ: 7701 case ISD::CTPOP: 7702 case ISD::FNEG: 7703 case ISD::FABS: 7704 case ISD::FSQRT: 7705 case ISD::FSIN: 7706 case ISD::FCOS: 7707 case ISD::FLOG: 7708 case ISD::FLOG2: 7709 case ISD::FLOG10: 7710 case ISD::FEXP: 7711 case ISD::FEXP2: 7712 case ISD::FP_TO_SINT: 7713 case ISD::FP_TO_UINT: 7714 case ISD::SINT_TO_FP: 7715 case ISD::UINT_TO_FP: 7716 case ISD::TRUNCATE: 7717 case ISD::ANY_EXTEND: 7718 case ISD::SIGN_EXTEND: 7719 case ISD::ZERO_EXTEND: 7720 case ISD::FP_EXTEND: { 7721 SDValue L, H; 7722 SplitVectorOp(Node->getOperand(0), L, H); 7723 7724 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L); 7725 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H); 7726 break; 7727 } 7728 case ISD::CONVERT_RNDSAT: { 7729 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 7730 SDValue L, H; 7731 SplitVectorOp(Node->getOperand(0), L, H); 7732 SDValue DTyOpL = DAG.getValueType(NewVT_Lo); 7733 SDValue DTyOpH = DAG.getValueType(NewVT_Hi); 7734 SDValue STyOpL = DAG.getValueType(L.getValueType()); 7735 SDValue STyOpH = DAG.getValueType(H.getValueType()); 7736 7737 SDValue RndOp = Node->getOperand(3); 7738 SDValue SatOp = Node->getOperand(4); 7739 7740 Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL, 7741 RndOp, SatOp, CvtCode); 7742 Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH, 7743 RndOp, SatOp, CvtCode); 7744 break; 7745 } 7746 case ISD::LOAD: { 7747 LoadSDNode *LD = cast<LoadSDNode>(Node); 7748 SDValue Ch = LD->getChain(); 7749 SDValue Ptr = LD->getBasePtr(); 7750 ISD::LoadExtType ExtType = LD->getExtensionType(); 7751 const Value *SV = LD->getSrcValue(); 7752 int SVOffset = LD->getSrcValueOffset(); 7753 MVT MemoryVT = LD->getMemoryVT(); 7754 unsigned Alignment = LD->getAlignment(); 7755 bool isVolatile = LD->isVolatile(); 7756 7757 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7758 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 7759 7760 MVT MemNewEltVT = MemoryVT.getVectorElementType(); 7761 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo); 7762 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi); 7763 7764 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, 7765 NewVT_Lo, Ch, Ptr, Offset, 7766 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment); 7767 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8; 7768 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 7769 DAG.getIntPtrConstant(IncrementSize)); 7770 SVOffset += IncrementSize; 7771 Alignment = MinAlign(Alignment, IncrementSize); 7772 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, 7773 NewVT_Hi, Ch, Ptr, Offset, 7774 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment); 7775 7776 // Build a factor node to remember that this load is independent of the 7777 // other one. 7778 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 7779 Hi.getValue(1)); 7780 7781 // Remember that we legalized the chain. 7782 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 7783 break; 7784 } 7785 case ISD::BIT_CONVERT: { 7786 // We know the result is a vector. The input may be either a vector or a 7787 // scalar value. 7788 SDValue InOp = Node->getOperand(0); 7789 if (!InOp.getValueType().isVector() || 7790 InOp.getValueType().getVectorNumElements() == 1) { 7791 // The input is a scalar or single-element vector. 7792 // Lower to a store/load so that it can be split. 7793 // FIXME: this could be improved probably. 7794 unsigned LdAlign = TLI.getTargetData()-> 7795 getPrefTypeAlignment(Op.getValueType().getTypeForMVT()); 7796 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign); 7797 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex(); 7798 7799 SDValue St = DAG.getStore(DAG.getEntryNode(), dl, 7800 InOp, Ptr, 7801 PseudoSourceValue::getFixedStack(FI), 0); 7802 InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr, 7803 PseudoSourceValue::getFixedStack(FI), 0); 7804 } 7805 // Split the vector and convert each of the pieces now. 7806 SplitVectorOp(InOp, Lo, Hi); 7807 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Lo, Lo); 7808 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Hi, Hi); 7809 break; 7810 } 7811 } 7812 7813 // Remember in a map if the values will be reused later. 7814 bool isNew = 7815 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7816 assert(isNew && "Value already split?!?"); 7817 isNew = isNew; 7818} 7819 7820 7821/// ScalarizeVectorOp - Given an operand of single-element vector type 7822/// (e.g. v1f32), convert it into the equivalent operation that returns a 7823/// scalar (e.g. f32) value. 7824SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) { 7825 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); 7826 SDNode *Node = Op.getNode(); 7827 DebugLoc dl = Node->getDebugLoc(); 7828 MVT NewVT = Op.getValueType().getVectorElementType(); 7829 assert(Op.getValueType().getVectorNumElements() == 1); 7830 7831 // See if we already scalarized it. 7832 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op); 7833 if (I != ScalarizedNodes.end()) return I->second; 7834 7835 SDValue Result; 7836 switch (Node->getOpcode()) { 7837 default: 7838#ifndef NDEBUG 7839 Node->dump(&DAG); cerr << "\n"; 7840#endif 7841 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7842 case ISD::ADD: 7843 case ISD::FADD: 7844 case ISD::SUB: 7845 case ISD::FSUB: 7846 case ISD::MUL: 7847 case ISD::FMUL: 7848 case ISD::SDIV: 7849 case ISD::UDIV: 7850 case ISD::FDIV: 7851 case ISD::SREM: 7852 case ISD::UREM: 7853 case ISD::FREM: 7854 case ISD::FPOW: 7855 case ISD::AND: 7856 case ISD::OR: 7857 case ISD::XOR: 7858 Result = DAG.getNode(Node->getOpcode(), dl, 7859 NewVT, 7860 ScalarizeVectorOp(Node->getOperand(0)), 7861 ScalarizeVectorOp(Node->getOperand(1))); 7862 break; 7863 case ISD::FNEG: 7864 case ISD::FABS: 7865 case ISD::FSQRT: 7866 case ISD::FSIN: 7867 case ISD::FCOS: 7868 case ISD::FLOG: 7869 case ISD::FLOG2: 7870 case ISD::FLOG10: 7871 case ISD::FEXP: 7872 case ISD::FEXP2: 7873 case ISD::FP_TO_SINT: 7874 case ISD::FP_TO_UINT: 7875 case ISD::SINT_TO_FP: 7876 case ISD::UINT_TO_FP: 7877 case ISD::SIGN_EXTEND: 7878 case ISD::ZERO_EXTEND: 7879 case ISD::ANY_EXTEND: 7880 case ISD::TRUNCATE: 7881 case ISD::FP_EXTEND: 7882 Result = DAG.getNode(Node->getOpcode(), dl, 7883 NewVT, 7884 ScalarizeVectorOp(Node->getOperand(0))); 7885 break; 7886 case ISD::CONVERT_RNDSAT: { 7887 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0)); 7888 Result = DAG.getConvertRndSat(NewVT, dl, Op0, 7889 DAG.getValueType(NewVT), 7890 DAG.getValueType(Op0.getValueType()), 7891 Node->getOperand(3), 7892 Node->getOperand(4), 7893 cast<CvtRndSatSDNode>(Node)->getCvtCode()); 7894 break; 7895 } 7896 case ISD::FPOWI: 7897 case ISD::FP_ROUND: 7898 Result = DAG.getNode(Node->getOpcode(), dl, 7899 NewVT, 7900 ScalarizeVectorOp(Node->getOperand(0)), 7901 Node->getOperand(1)); 7902 break; 7903 case ISD::LOAD: { 7904 LoadSDNode *LD = cast<LoadSDNode>(Node); 7905 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7906 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7907 ISD::LoadExtType ExtType = LD->getExtensionType(); 7908 const Value *SV = LD->getSrcValue(); 7909 int SVOffset = LD->getSrcValueOffset(); 7910 MVT MemoryVT = LD->getMemoryVT(); 7911 unsigned Alignment = LD->getAlignment(); 7912 bool isVolatile = LD->isVolatile(); 7913 7914 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7915 SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); 7916 7917 Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, 7918 NewVT, Ch, Ptr, Offset, SV, SVOffset, 7919 MemoryVT.getVectorElementType(), 7920 isVolatile, Alignment); 7921 7922 // Remember that we legalized the chain. 7923 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7924 break; 7925 } 7926 case ISD::BUILD_VECTOR: 7927 Result = Node->getOperand(0); 7928 break; 7929 case ISD::INSERT_VECTOR_ELT: 7930 // Returning the inserted scalar element. 7931 Result = Node->getOperand(1); 7932 break; 7933 case ISD::CONCAT_VECTORS: 7934 assert(Node->getOperand(0).getValueType() == NewVT && 7935 "Concat of non-legal vectors not yet supported!"); 7936 Result = Node->getOperand(0); 7937 break; 7938 case ISD::VECTOR_SHUFFLE: { 7939 // Figure out if the scalar is the LHS or RHS and return it. 7940 SDValue EltNum = Node->getOperand(2).getOperand(0); 7941 if (cast<ConstantSDNode>(EltNum)->getZExtValue()) 7942 Result = ScalarizeVectorOp(Node->getOperand(1)); 7943 else 7944 Result = ScalarizeVectorOp(Node->getOperand(0)); 7945 break; 7946 } 7947 case ISD::EXTRACT_SUBVECTOR: 7948 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, 7949 Node->getOperand(0), Node->getOperand(1)); 7950 break; 7951 case ISD::BIT_CONVERT: { 7952 SDValue Op0 = Op.getOperand(0); 7953 if (Op0.getValueType().getVectorNumElements() == 1) 7954 Op0 = ScalarizeVectorOp(Op0); 7955 Result = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, Op0); 7956 break; 7957 } 7958 case ISD::SELECT: 7959 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Op.getOperand(0), 7960 ScalarizeVectorOp(Op.getOperand(1)), 7961 ScalarizeVectorOp(Op.getOperand(2))); 7962 break; 7963 case ISD::SELECT_CC: 7964 Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0), 7965 Node->getOperand(1), 7966 ScalarizeVectorOp(Op.getOperand(2)), 7967 ScalarizeVectorOp(Op.getOperand(3)), 7968 Node->getOperand(4)); 7969 break; 7970 case ISD::VSETCC: { 7971 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0)); 7972 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1)); 7973 Result = DAG.getNode(ISD::SETCC, dl, 7974 TLI.getSetCCResultType(Op0.getValueType()), 7975 Op0, Op1, Op.getOperand(2)); 7976 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Result, 7977 DAG.getConstant(-1ULL, NewVT), 7978 DAG.getConstant(0ULL, NewVT)); 7979 break; 7980 } 7981 } 7982 7983 if (TLI.isTypeLegal(NewVT)) 7984 Result = LegalizeOp(Result); 7985 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7986 assert(isNew && "Value already scalarized?"); 7987 isNew = isNew; 7988 return Result; 7989} 7990 7991 7992SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) { 7993 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op); 7994 if (I != WidenNodes.end()) return I->second; 7995 7996 MVT VT = Op.getValueType(); 7997 assert(VT.isVector() && "Cannot widen non-vector type!"); 7998 7999 SDValue Result; 8000 SDNode *Node = Op.getNode(); 8001 DebugLoc dl = Node->getDebugLoc(); 8002 MVT EVT = VT.getVectorElementType(); 8003 8004 unsigned NumElts = VT.getVectorNumElements(); 8005 unsigned NewNumElts = WidenVT.getVectorNumElements(); 8006 assert(NewNumElts > NumElts && "Cannot widen to smaller type!"); 8007 assert(NewNumElts < 17); 8008 8009 // When widen is called, it is assumed that it is more efficient to use a 8010 // wide type. The default action is to widen to operation to a wider legal 8011 // vector type and then do the operation if it is legal by calling LegalizeOp 8012 // again. If there is no vector equivalent, we will unroll the operation, do 8013 // it, and rebuild the vector. If most of the operations are vectorizible to 8014 // the legal type, the resulting code will be more efficient. If this is not 8015 // the case, the resulting code will preform badly as we end up generating 8016 // code to pack/unpack the results. It is the function that calls widen 8017 // that is responsible for seeing this doesn't happen. 8018 switch (Node->getOpcode()) { 8019 default: 8020#ifndef NDEBUG 8021 Node->dump(&DAG); 8022#endif 8023 assert(0 && "Unexpected operation in WidenVectorOp!"); 8024 break; 8025 case ISD::CopyFromReg: 8026 assert(0 && "CopyFromReg doesn't need widening!"); 8027 case ISD::Constant: 8028 case ISD::ConstantFP: 8029 // To build a vector of these elements, clients should call BuildVector 8030 // and with each element instead of creating a node with a vector type 8031 assert(0 && "Unexpected operation in WidenVectorOp!"); 8032 case ISD::VAARG: 8033 // Variable Arguments with vector types doesn't make any sense to me 8034 assert(0 && "Unexpected operation in WidenVectorOp!"); 8035 break; 8036 case ISD::UNDEF: 8037 Result = DAG.getUNDEF(WidenVT); 8038 break; 8039 case ISD::BUILD_VECTOR: { 8040 // Build a vector with undefined for the new nodes 8041 SDValueVector NewOps(Node->op_begin(), Node->op_end()); 8042 for (unsigned i = NumElts; i < NewNumElts; ++i) { 8043 NewOps.push_back(DAG.getUNDEF(EVT)); 8044 } 8045 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, 8046 &NewOps[0], NewOps.size()); 8047 break; 8048 } 8049 case ISD::INSERT_VECTOR_ELT: { 8050 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8051 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WidenVT, Tmp1, 8052 Node->getOperand(1), Node->getOperand(2)); 8053 break; 8054 } 8055 case ISD::VECTOR_SHUFFLE: { 8056 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8057 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT); 8058 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Node); 8059 SmallVector<int, 8> NewMask; 8060 for (unsigned i = 0; i < NumElts; ++i) { 8061 int Idx = SVOp->getMaskElt(i); 8062 if (Idx < (int)NumElts) 8063 NewMask.push_back(Idx); 8064 else 8065 NewMask.push_back(Idx + NewNumElts - NumElts); 8066 } 8067 for (unsigned i = NumElts; i < NewNumElts; ++i) 8068 NewMask.push_back(-1); 8069 8070 Result = DAG.getVectorShuffle(WidenVT, dl, Tmp1, Tmp2, &NewMask[0]); 8071 break; 8072 } 8073 case ISD::LOAD: { 8074 // If the load widen returns true, we can use a single load for the 8075 // vector. Otherwise, it is returning a token factor for multiple 8076 // loads. 8077 SDValue TFOp; 8078 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT)) 8079 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1))); 8080 else 8081 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0))); 8082 break; 8083 } 8084 8085 case ISD::BIT_CONVERT: { 8086 SDValue Tmp1 = Node->getOperand(0); 8087 // Converts between two different types so we need to determine 8088 // the correct widen type for the input operand. 8089 MVT InVT = Tmp1.getValueType(); 8090 unsigned WidenSize = WidenVT.getSizeInBits(); 8091 if (InVT.isVector()) { 8092 MVT InEltVT = InVT.getVectorElementType(); 8093 unsigned InEltSize = InEltVT.getSizeInBits(); 8094 assert(WidenSize % InEltSize == 0 && 8095 "can not widen bit convert that are not multiple of element type"); 8096 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize); 8097 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT); 8098 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits()); 8099 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Tmp1); 8100 } else { 8101 // If the result size is a multiple of the input size, widen the input 8102 // and then convert. 8103 unsigned InSize = InVT.getSizeInBits(); 8104 assert(WidenSize % InSize == 0 && 8105 "can not widen bit convert that are not multiple of element type"); 8106 unsigned NewNumElts = WidenSize / InSize; 8107 SmallVector<SDValue, 16> Ops(NewNumElts); 8108 SDValue UndefVal = DAG.getUNDEF(InVT); 8109 Ops[0] = Tmp1; 8110 for (unsigned i = 1; i < NewNumElts; ++i) 8111 Ops[i] = UndefVal; 8112 8113 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts); 8114 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, &Ops[0], NewNumElts); 8115 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Result); 8116 } 8117 break; 8118 } 8119 8120 case ISD::SINT_TO_FP: 8121 case ISD::UINT_TO_FP: 8122 case ISD::FP_TO_SINT: 8123 case ISD::FP_TO_UINT: 8124 case ISD::FP_ROUND: { 8125 SDValue Tmp1 = Node->getOperand(0); 8126 // Converts between two different types so we need to determine 8127 // the correct widen type for the input operand. 8128 MVT TVT = Tmp1.getValueType(); 8129 assert(TVT.isVector() && "can not widen non vector type"); 8130 MVT TEVT = TVT.getVectorElementType(); 8131 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts); 8132 Tmp1 = WidenVectorOp(Tmp1, TWidenVT); 8133 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts); 8134 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1); 8135 break; 8136 } 8137 8138 case ISD::FP_EXTEND: 8139 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 8140 case ISD::TRUNCATE: 8141 case ISD::SIGN_EXTEND: 8142 case ISD::ZERO_EXTEND: 8143 case ISD::ANY_EXTEND: 8144 case ISD::SIGN_EXTEND_INREG: 8145 case ISD::FABS: 8146 case ISD::FNEG: 8147 case ISD::FSQRT: 8148 case ISD::FSIN: 8149 case ISD::FCOS: 8150 case ISD::CTPOP: 8151 case ISD::CTTZ: 8152 case ISD::CTLZ: { 8153 // Unary op widening 8154 SDValue Tmp1; 8155 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8156 assert(Tmp1.getValueType() == WidenVT); 8157 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1); 8158 break; 8159 } 8160 case ISD::CONVERT_RNDSAT: { 8161 SDValue RndOp = Node->getOperand(3); 8162 SDValue SatOp = Node->getOperand(4); 8163 SDValue SrcOp = Node->getOperand(0); 8164 8165 // Converts between two different types so we need to determine 8166 // the correct widen type for the input operand. 8167 MVT SVT = SrcOp.getValueType(); 8168 assert(SVT.isVector() && "can not widen non vector type"); 8169 MVT SEVT = SVT.getVectorElementType(); 8170 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts); 8171 8172 SrcOp = WidenVectorOp(SrcOp, SWidenVT); 8173 assert(SrcOp.getValueType() == WidenVT); 8174 SDValue DTyOp = DAG.getValueType(WidenVT); 8175 SDValue STyOp = DAG.getValueType(SrcOp.getValueType()); 8176 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 8177 8178 Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp, 8179 RndOp, SatOp, CvtCode); 8180 break; 8181 } 8182 case ISD::FPOW: 8183 case ISD::FPOWI: 8184 case ISD::ADD: 8185 case ISD::SUB: 8186 case ISD::MUL: 8187 case ISD::MULHS: 8188 case ISD::MULHU: 8189 case ISD::AND: 8190 case ISD::OR: 8191 case ISD::XOR: 8192 case ISD::FADD: 8193 case ISD::FSUB: 8194 case ISD::FMUL: 8195 case ISD::SDIV: 8196 case ISD::SREM: 8197 case ISD::FDIV: 8198 case ISD::FREM: 8199 case ISD::FCOPYSIGN: 8200 case ISD::UDIV: 8201 case ISD::UREM: 8202 case ISD::BSWAP: { 8203 // Binary op widening 8204 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8205 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT); 8206 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT); 8207 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2); 8208 break; 8209 } 8210 8211 case ISD::SHL: 8212 case ISD::SRA: 8213 case ISD::SRL: { 8214 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8215 assert(Tmp1.getValueType() == WidenVT); 8216 SDValue ShOp = Node->getOperand(1); 8217 MVT ShVT = ShOp.getValueType(); 8218 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(), 8219 WidenVT.getVectorNumElements()); 8220 ShOp = WidenVectorOp(ShOp, NewShVT); 8221 assert(ShOp.getValueType() == NewShVT); 8222 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, ShOp); 8223 break; 8224 } 8225 8226 case ISD::EXTRACT_VECTOR_ELT: { 8227 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8228 assert(Tmp1.getValueType() == WidenVT); 8229 Result = DAG.getNode(Node->getOpcode(), dl, EVT, Tmp1, Node->getOperand(1)); 8230 break; 8231 } 8232 case ISD::CONCAT_VECTORS: { 8233 // We concurrently support only widen on a multiple of the incoming vector. 8234 // We could widen on a multiple of the incoming operand if necessary. 8235 unsigned NumConcat = NewNumElts / NumElts; 8236 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector"); 8237 SDValue UndefVal = DAG.getUNDEF(VT); 8238 SmallVector<SDValue, 8> MOps; 8239 MOps.push_back(Op); 8240 for (unsigned i = 1; i != NumConcat; ++i) { 8241 MOps.push_back(UndefVal); 8242 } 8243 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, 8244 &MOps[0], MOps.size())); 8245 break; 8246 } 8247 case ISD::EXTRACT_SUBVECTOR: { 8248 SDValue Tmp1 = Node->getOperand(0); 8249 SDValue Idx = Node->getOperand(1); 8250 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx); 8251 if (CIdx && CIdx->getZExtValue() == 0) { 8252 // Since we are access the start of the vector, the incoming 8253 // vector type might be the proper. 8254 MVT Tmp1VT = Tmp1.getValueType(); 8255 if (Tmp1VT == WidenVT) 8256 return Tmp1; 8257 else { 8258 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements(); 8259 if (Tmp1VTNumElts < NewNumElts) 8260 Result = WidenVectorOp(Tmp1, WidenVT); 8261 else 8262 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, Tmp1, Idx); 8263 } 8264 } else if (NewNumElts % NumElts == 0) { 8265 // Widen the extracted subvector. 8266 unsigned NumConcat = NewNumElts / NumElts; 8267 SDValue UndefVal = DAG.getUNDEF(VT); 8268 SmallVector<SDValue, 8> MOps; 8269 MOps.push_back(Op); 8270 for (unsigned i = 1; i != NumConcat; ++i) { 8271 MOps.push_back(UndefVal); 8272 } 8273 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, 8274 &MOps[0], MOps.size())); 8275 } else { 8276 assert(0 && "can not widen extract subvector"); 8277 // This could be implemented using insert and build vector but I would 8278 // like to see when this happens. 8279 } 8280 break; 8281 } 8282 8283 case ISD::SELECT: { 8284 // Determine new condition widen type and widen 8285 SDValue Cond1 = Node->getOperand(0); 8286 MVT CondVT = Cond1.getValueType(); 8287 assert(CondVT.isVector() && "can not widen non vector type"); 8288 MVT CondEVT = CondVT.getVectorElementType(); 8289 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts); 8290 Cond1 = WidenVectorOp(Cond1, CondWidenVT); 8291 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen"); 8292 8293 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT); 8294 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT); 8295 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT); 8296 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2); 8297 break; 8298 } 8299 8300 case ISD::SELECT_CC: { 8301 // Determine new condition widen type and widen 8302 SDValue Cond1 = Node->getOperand(0); 8303 SDValue Cond2 = Node->getOperand(1); 8304 MVT CondVT = Cond1.getValueType(); 8305 assert(CondVT.isVector() && "can not widen non vector type"); 8306 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs"); 8307 MVT CondEVT = CondVT.getVectorElementType(); 8308 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts); 8309 Cond1 = WidenVectorOp(Cond1, CondWidenVT); 8310 Cond2 = WidenVectorOp(Cond2, CondWidenVT); 8311 assert(Cond1.getValueType() == CondWidenVT && 8312 Cond2.getValueType() == CondWidenVT && "condition not widen"); 8313 8314 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT); 8315 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT); 8316 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT && 8317 "operands not widen"); 8318 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Cond2, Tmp1, 8319 Tmp2, Node->getOperand(4)); 8320 break; 8321 } 8322 case ISD::VSETCC: { 8323 // Determine widen for the operand 8324 SDValue Tmp1 = Node->getOperand(0); 8325 MVT TmpVT = Tmp1.getValueType(); 8326 assert(TmpVT.isVector() && "can not widen non vector type"); 8327 MVT TmpEVT = TmpVT.getVectorElementType(); 8328 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts); 8329 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT); 8330 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT); 8331 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2, 8332 Node->getOperand(2)); 8333 break; 8334 } 8335 case ISD::ATOMIC_CMP_SWAP: 8336 case ISD::ATOMIC_LOAD_ADD: 8337 case ISD::ATOMIC_LOAD_SUB: 8338 case ISD::ATOMIC_LOAD_AND: 8339 case ISD::ATOMIC_LOAD_OR: 8340 case ISD::ATOMIC_LOAD_XOR: 8341 case ISD::ATOMIC_LOAD_NAND: 8342 case ISD::ATOMIC_LOAD_MIN: 8343 case ISD::ATOMIC_LOAD_MAX: 8344 case ISD::ATOMIC_LOAD_UMIN: 8345 case ISD::ATOMIC_LOAD_UMAX: 8346 case ISD::ATOMIC_SWAP: { 8347 // For now, we assume that using vectors for these operations don't make 8348 // much sense so we just split it. We return an empty result 8349 SDValue X, Y; 8350 SplitVectorOp(Op, X, Y); 8351 return Result; 8352 break; 8353 } 8354 8355 } // end switch (Node->getOpcode()) 8356 8357 assert(Result.getNode() && "Didn't set a result!"); 8358 if (Result != Op) 8359 Result = LegalizeOp(Result); 8360 8361 AddWidenedOperand(Op, Result); 8362 return Result; 8363} 8364 8365// Utility function to find a legal vector type and its associated element 8366// type from a preferred width and whose vector type must be the same size 8367// as the VVT. 8368// TLI: Target lowering used to determine legal types 8369// Width: Preferred width of element type 8370// VVT: Vector value type whose size we must match. 8371// Returns VecEVT and EVT - the vector type and its associated element type 8372static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT, 8373 MVT& EVT, MVT& VecEVT) { 8374 // We start with the preferred width, make it a power of 2 and see if 8375 // we can find a vector type of that width. If not, we reduce it by 8376 // another power of 2. If we have widen the type, a vector of bytes should 8377 // always be legal. 8378 assert(TLI.isTypeLegal(VVT)); 8379 unsigned EWidth = Width + 1; 8380 do { 8381 assert(EWidth > 0); 8382 EWidth = (1 << Log2_32(EWidth-1)); 8383 EVT = MVT::getIntegerVT(EWidth); 8384 unsigned NumEVT = VVT.getSizeInBits()/EWidth; 8385 VecEVT = MVT::getVectorVT(EVT, NumEVT); 8386 } while (!TLI.isTypeLegal(VecEVT) || 8387 VVT.getSizeInBits() != VecEVT.getSizeInBits()); 8388} 8389 8390SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain, 8391 SDValue Chain, 8392 SDValue BasePtr, 8393 const Value *SV, 8394 int SVOffset, 8395 unsigned Alignment, 8396 bool isVolatile, 8397 unsigned LdWidth, 8398 MVT ResType, 8399 DebugLoc dl) { 8400 // We assume that we have good rules to handle loading power of two loads so 8401 // we break down the operations to power of 2 loads. The strategy is to 8402 // load the largest power of 2 that we can easily transform to a legal vector 8403 // and then insert into that vector, and the cast the result into the legal 8404 // vector that we want. This avoids unnecessary stack converts. 8405 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and 8406 // the load is nonvolatile, we an use a wider load for the value. 8407 // Find a vector length we can load a large chunk 8408 MVT EVT, VecEVT; 8409 unsigned EVTWidth; 8410 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT); 8411 EVTWidth = EVT.getSizeInBits(); 8412 8413 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset, 8414 isVolatile, Alignment); 8415 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp); 8416 LdChain.push_back(LdOp.getValue(1)); 8417 8418 // Check if we can load the element with one instruction 8419 if (LdWidth == EVTWidth) { 8420 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp); 8421 } 8422 8423 // The vector element order is endianness dependent. 8424 unsigned Idx = 1; 8425 LdWidth -= EVTWidth; 8426 unsigned Offset = 0; 8427 8428 while (LdWidth > 0) { 8429 unsigned Increment = EVTWidth / 8; 8430 Offset += Increment; 8431 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 8432 DAG.getIntPtrConstant(Increment)); 8433 8434 if (LdWidth < EVTWidth) { 8435 // Our current type we are using is too large, use a smaller size by 8436 // using a smaller power of 2 8437 unsigned oEVTWidth = EVTWidth; 8438 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT); 8439 EVTWidth = EVT.getSizeInBits(); 8440 // Readjust position and vector position based on new load type 8441 Idx = Idx * (oEVTWidth/EVTWidth); 8442 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp); 8443 } 8444 8445 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, 8446 SVOffset+Offset, isVolatile, 8447 MinAlign(Alignment, Offset)); 8448 LdChain.push_back(LdOp.getValue(1)); 8449 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp, 8450 DAG.getIntPtrConstant(Idx++)); 8451 8452 LdWidth -= EVTWidth; 8453 } 8454 8455 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp); 8456} 8457 8458bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result, 8459 SDValue& TFOp, 8460 SDValue Op, 8461 MVT NVT) { 8462 // TODO: Add support for ConcatVec and the ability to load many vector 8463 // types (e.g., v4i8). This will not work when a vector register 8464 // to memory mapping is strange (e.g., vector elements are not 8465 // stored in some sequential order). 8466 8467 // It must be true that the widen vector type is bigger than where 8468 // we need to load from. 8469 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); 8470 MVT LdVT = LD->getMemoryVT(); 8471 DebugLoc dl = LD->getDebugLoc(); 8472 assert(LdVT.isVector() && NVT.isVector()); 8473 assert(LdVT.getVectorElementType() == NVT.getVectorElementType()); 8474 8475 // Load information 8476 SDValue Chain = LD->getChain(); 8477 SDValue BasePtr = LD->getBasePtr(); 8478 int SVOffset = LD->getSrcValueOffset(); 8479 unsigned Alignment = LD->getAlignment(); 8480 bool isVolatile = LD->isVolatile(); 8481 const Value *SV = LD->getSrcValue(); 8482 unsigned int LdWidth = LdVT.getSizeInBits(); 8483 8484 // Load value as a large register 8485 SDValueVector LdChain; 8486 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset, 8487 Alignment, isVolatile, LdWidth, NVT, dl); 8488 8489 if (LdChain.size() == 1) { 8490 TFOp = LdChain[0]; 8491 return true; 8492 } 8493 else { 8494 TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 8495 &LdChain[0], LdChain.size()); 8496 return false; 8497 } 8498} 8499 8500 8501void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain, 8502 SDValue Chain, 8503 SDValue BasePtr, 8504 const Value *SV, 8505 int SVOffset, 8506 unsigned Alignment, 8507 bool isVolatile, 8508 SDValue ValOp, 8509 unsigned StWidth, 8510 DebugLoc dl) { 8511 // Breaks the stores into a series of power of 2 width stores. For any 8512 // width, we convert the vector to the vector of element size that we 8513 // want to store. This avoids requiring a stack convert. 8514 8515 // Find a width of the element type we can store with 8516 MVT VVT = ValOp.getValueType(); 8517 MVT EVT, VecEVT; 8518 unsigned EVTWidth; 8519 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT); 8520 EVTWidth = EVT.getSizeInBits(); 8521 8522 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, ValOp); 8523 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp, 8524 DAG.getIntPtrConstant(0)); 8525 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset, 8526 isVolatile, Alignment); 8527 StChain.push_back(StOp); 8528 8529 // Check if we are done 8530 if (StWidth == EVTWidth) { 8531 return; 8532 } 8533 8534 unsigned Idx = 1; 8535 StWidth -= EVTWidth; 8536 unsigned Offset = 0; 8537 8538 while (StWidth > 0) { 8539 unsigned Increment = EVTWidth / 8; 8540 Offset += Increment; 8541 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, 8542 DAG.getIntPtrConstant(Increment)); 8543 8544 if (StWidth < EVTWidth) { 8545 // Our current type we are using is too large, use a smaller size by 8546 // using a smaller power of 2 8547 unsigned oEVTWidth = EVTWidth; 8548 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT); 8549 EVTWidth = EVT.getSizeInBits(); 8550 // Readjust position and vector position based on new load type 8551 Idx = Idx * (oEVTWidth/EVTWidth); 8552 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp); 8553 } 8554 8555 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp, 8556 DAG.getIntPtrConstant(Idx++)); 8557 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV, 8558 SVOffset + Offset, isVolatile, 8559 MinAlign(Alignment, Offset))); 8560 StWidth -= EVTWidth; 8561 } 8562} 8563 8564 8565SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST, 8566 SDValue Chain, 8567 SDValue BasePtr) { 8568 // TODO: It might be cleaner if we can use SplitVector and have more legal 8569 // vector types that can be stored into memory (e.g., v4xi8 can 8570 // be stored as a word). This will not work when a vector register 8571 // to memory mapping is strange (e.g., vector elements are not 8572 // stored in some sequential order). 8573 8574 MVT StVT = ST->getMemoryVT(); 8575 SDValue ValOp = ST->getValue(); 8576 DebugLoc dl = ST->getDebugLoc(); 8577 8578 // Check if we have widen this node with another value 8579 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp); 8580 if (I != WidenNodes.end()) 8581 ValOp = I->second; 8582 8583 MVT VVT = ValOp.getValueType(); 8584 8585 // It must be true that we the widen vector type is bigger than where 8586 // we need to store. 8587 assert(StVT.isVector() && VVT.isVector()); 8588 assert(StVT.bitsLT(VVT)); 8589 assert(StVT.getVectorElementType() == VVT.getVectorElementType()); 8590 8591 // Store value 8592 SDValueVector StChain; 8593 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(), 8594 ST->getSrcValueOffset(), ST->getAlignment(), 8595 ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl); 8596 if (StChain.size() == 1) 8597 return StChain[0]; 8598 else 8599 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 8600 &StChain[0], StChain.size()); 8601} 8602 8603 8604// SelectionDAG::Legalize - This is the entry point for the file. 8605// 8606void SelectionDAG::Legalize(bool TypesNeedLegalizing, 8607 CodeGenOpt::Level OptLevel) { 8608 /// run - This is the main entry point to this class. 8609 /// 8610 SelectionDAGLegalize(*this, TypesNeedLegalizing, OptLevel).LegalizeDAG(); 8611} 8612 8613