LegalizeDAG.cpp revision cc827e60b67b2cbcf08a37b119e68081e4171b8a
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned long long ValueTypeActions; 56 57 /// NeedsAnotherIteration - This is set when we expand a large integer 58 /// operation into smaller integer operations, but the smaller operations are 59 /// not set. This occurs only rarely in practice, for targets that don't have 60 /// 32-bit or larger integer registers. 61 bool NeedsAnotherIteration; 62 63 /// LegalizedNodes - For nodes that are of legal width, and that have more 64 /// than one use, this map indicates what regularized operand to use. This 65 /// allows us to avoid legalizing the same thing more than once. 66 std::map<SDOperand, SDOperand> LegalizedNodes; 67 68 /// PromotedNodes - For nodes that are below legal width, and that have more 69 /// than one use, this map indicates what promoted value to use. This allows 70 /// us to avoid promoting the same thing more than once. 71 std::map<SDOperand, SDOperand> PromotedNodes; 72 73 /// ExpandedNodes - For nodes that need to be expanded, and which have more 74 /// than one use, this map indicates which which operands are the expanded 75 /// version of the input. This allows us to avoid expanding the same node 76 /// more than once. 77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 78 79 void AddLegalizedOperand(SDOperand From, SDOperand To) { 80 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second; 81 assert(isNew && "Got into the map somehow?"); 82 } 83 void AddPromotedOperand(SDOperand From, SDOperand To) { 84 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 85 assert(isNew && "Got into the map somehow?"); 86 } 87 88public: 89 90 SelectionDAGLegalize(SelectionDAG &DAG); 91 92 /// Run - While there is still lowering to do, perform a pass over the DAG. 93 /// Most regularization can be done in a single pass, but targets that require 94 /// large values to be split into registers multiple times (e.g. i64 -> 4x 95 /// i16) require iteration for these values (the first iteration will demote 96 /// to i32, the second will demote to i16). 97 void Run() { 98 do { 99 NeedsAnotherIteration = false; 100 LegalizeDAG(); 101 } while (NeedsAnotherIteration); 102 } 103 104 /// getTypeAction - Return how we should legalize values of this type, either 105 /// it is already legal or we need to expand it into multiple registers of 106 /// smaller integer type, or we need to promote it to a larger type. 107 LegalizeAction getTypeAction(MVT::ValueType VT) const { 108 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 109 } 110 111 /// isTypeLegal - Return true if this type is legal on this target. 112 /// 113 bool isTypeLegal(MVT::ValueType VT) const { 114 return getTypeAction(VT) == Legal; 115 } 116 117private: 118 void LegalizeDAG(); 119 120 SDOperand LegalizeOp(SDOperand O); 121 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 122 SDOperand PromoteOp(SDOperand O); 123 124 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 125 SDOperand &Hi); 126 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 127 SDOperand Source); 128 129 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 130 SDOperand LegalOp, 131 MVT::ValueType DestVT); 132 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 133 bool isSigned); 134 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 135 bool isSigned); 136 137 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 138 SDOperand &Lo, SDOperand &Hi); 139 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 140 SDOperand &Lo, SDOperand &Hi); 141 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 142 SDOperand &Lo, SDOperand &Hi); 143 144 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 145 146 SDOperand getIntPtrConstant(uint64_t Val) { 147 return DAG.getConstant(Val, TLI.getPointerTy()); 148 } 149}; 150} 151 152static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 153 switch (VecOp) { 154 default: assert(0 && "Don't know how to scalarize this opcode!"); 155 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 156 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 157 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 158 } 159} 160 161SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 162 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 163 ValueTypeActions(TLI.getValueTypeActions()) { 164 assert(MVT::LAST_VALUETYPE <= 32 && 165 "Too many value types for ValueTypeActions to hold!"); 166} 167 168/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 169/// INT_TO_FP operation of the specified operand when the target requests that 170/// we expand it. At this point, we know that the result and operand types are 171/// legal for the target. 172SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 173 SDOperand Op0, 174 MVT::ValueType DestVT) { 175 if (Op0.getValueType() == MVT::i32) { 176 // simple 32-bit [signed|unsigned] integer to float/double expansion 177 178 // get the stack frame index of a 8 byte buffer 179 MachineFunction &MF = DAG.getMachineFunction(); 180 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 181 // get address of 8 byte buffer 182 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 183 // word offset constant for Hi/Lo address computation 184 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 185 // set up Hi and Lo (into buffer) address based on endian 186 SDOperand Hi, Lo; 187 if (TLI.isLittleEndian()) { 188 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 189 Lo = StackSlot; 190 } else { 191 Hi = StackSlot; 192 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 193 } 194 // if signed map to unsigned space 195 SDOperand Op0Mapped; 196 if (isSigned) { 197 // constant used to invert sign bit (signed to unsigned mapping) 198 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 199 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 200 } else { 201 Op0Mapped = Op0; 202 } 203 // store the lo of the constructed double - based on integer input 204 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 205 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 206 // initial hi portion of constructed double 207 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 208 // store the hi of the constructed double - biased exponent 209 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 210 InitialHi, Hi, DAG.getSrcValue(NULL)); 211 // load the constructed double 212 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 213 DAG.getSrcValue(NULL)); 214 // FP constant to bias correct the final result 215 SDOperand Bias = DAG.getConstantFP(isSigned ? 216 BitsToDouble(0x4330000080000000ULL) 217 : BitsToDouble(0x4330000000000000ULL), 218 MVT::f64); 219 // subtract the bias 220 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 221 // final result 222 SDOperand Result; 223 // handle final rounding 224 if (DestVT == MVT::f64) { 225 // do nothing 226 Result = Sub; 227 } else { 228 // if f32 then cast to f32 229 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 230 } 231 NeedsAnotherIteration = true; 232 return Result; 233 } 234 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 235 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 236 237 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 238 DAG.getConstant(0, Op0.getValueType()), 239 ISD::SETLT); 240 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 241 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 242 SignSet, Four, Zero); 243 244 // If the sign bit of the integer is set, the large number will be treated 245 // as a negative number. To counteract this, the dynamic code adds an 246 // offset depending on the data type. 247 uint64_t FF; 248 switch (Op0.getValueType()) { 249 default: assert(0 && "Unsupported integer type!"); 250 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 251 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 252 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 253 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 254 } 255 if (TLI.isLittleEndian()) FF <<= 32; 256 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 257 258 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 259 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 260 SDOperand FudgeInReg; 261 if (DestVT == MVT::f32) 262 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 263 DAG.getSrcValue(NULL)); 264 else { 265 assert(DestVT == MVT::f64 && "Unexpected conversion"); 266 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 267 DAG.getEntryNode(), CPIdx, 268 DAG.getSrcValue(NULL), MVT::f32)); 269 } 270 271 NeedsAnotherIteration = true; 272 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 273} 274 275/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 276/// *INT_TO_FP operation of the specified operand when the target requests that 277/// we promote it. At this point, we know that the result and operand types are 278/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 279/// operation that takes a larger input. 280SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 281 MVT::ValueType DestVT, 282 bool isSigned) { 283 // First step, figure out the appropriate *INT_TO_FP operation to use. 284 MVT::ValueType NewInTy = LegalOp.getValueType(); 285 286 unsigned OpToUse = 0; 287 288 // Scan for the appropriate larger type to use. 289 while (1) { 290 NewInTy = (MVT::ValueType)(NewInTy+1); 291 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 292 293 // If the target supports SINT_TO_FP of this type, use it. 294 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 295 default: break; 296 case TargetLowering::Legal: 297 if (!TLI.isTypeLegal(NewInTy)) 298 break; // Can't use this datatype. 299 // FALL THROUGH. 300 case TargetLowering::Custom: 301 OpToUse = ISD::SINT_TO_FP; 302 break; 303 } 304 if (OpToUse) break; 305 if (isSigned) continue; 306 307 // If the target supports UINT_TO_FP of this type, use it. 308 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 309 default: break; 310 case TargetLowering::Legal: 311 if (!TLI.isTypeLegal(NewInTy)) 312 break; // Can't use this datatype. 313 // FALL THROUGH. 314 case TargetLowering::Custom: 315 OpToUse = ISD::UINT_TO_FP; 316 break; 317 } 318 if (OpToUse) break; 319 320 // Otherwise, try a larger type. 321 } 322 323 // Make sure to legalize any nodes we create here in the next pass. 324 NeedsAnotherIteration = true; 325 326 // Okay, we found the operation and type to use. Zero extend our input to the 327 // desired type then run the operation on it. 328 return DAG.getNode(OpToUse, DestVT, 329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 330 NewInTy, LegalOp)); 331} 332 333/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 334/// FP_TO_*INT operation of the specified operand when the target requests that 335/// we promote it. At this point, we know that the result and operand types are 336/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 337/// operation that returns a larger result. 338SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 339 MVT::ValueType DestVT, 340 bool isSigned) { 341 // First step, figure out the appropriate FP_TO*INT operation to use. 342 MVT::ValueType NewOutTy = DestVT; 343 344 unsigned OpToUse = 0; 345 346 // Scan for the appropriate larger type to use. 347 while (1) { 348 NewOutTy = (MVT::ValueType)(NewOutTy+1); 349 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 350 351 // If the target supports FP_TO_SINT returning this type, use it. 352 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 353 default: break; 354 case TargetLowering::Legal: 355 if (!TLI.isTypeLegal(NewOutTy)) 356 break; // Can't use this datatype. 357 // FALL THROUGH. 358 case TargetLowering::Custom: 359 OpToUse = ISD::FP_TO_SINT; 360 break; 361 } 362 if (OpToUse) break; 363 364 // If the target supports FP_TO_UINT of this type, use it. 365 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 366 default: break; 367 case TargetLowering::Legal: 368 if (!TLI.isTypeLegal(NewOutTy)) 369 break; // Can't use this datatype. 370 // FALL THROUGH. 371 case TargetLowering::Custom: 372 OpToUse = ISD::FP_TO_UINT; 373 break; 374 } 375 if (OpToUse) break; 376 377 // Otherwise, try a larger type. 378 } 379 380 // Make sure to legalize any nodes we create here in the next pass. 381 NeedsAnotherIteration = true; 382 383 // Okay, we found the operation and type to use. Truncate the result of the 384 // extended FP_TO_*INT operation to the desired size. 385 return DAG.getNode(ISD::TRUNCATE, DestVT, 386 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 387} 388 389/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 390/// not been visited yet and if all of its operands have already been visited. 391static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 392 std::map<SDNode*, unsigned> &Visited) { 393 if (++Visited[N] != N->getNumOperands()) 394 return; // Haven't visited all operands yet 395 396 Order.push_back(N); 397 398 if (N->hasOneUse()) { // Tail recurse in common case. 399 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 400 return; 401 } 402 403 // Now that we have N in, add anything that uses it if all of their operands 404 // are now done. 405 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 406 ComputeTopDownOrdering(*UI, Order, Visited); 407} 408 409 410void SelectionDAGLegalize::LegalizeDAG() { 411 // The legalize process is inherently a bottom-up recursive process (users 412 // legalize their uses before themselves). Given infinite stack space, we 413 // could just start legalizing on the root and traverse the whole graph. In 414 // practice however, this causes us to run out of stack space on large basic 415 // blocks. To avoid this problem, compute an ordering of the nodes where each 416 // node is only legalized after all of its operands are legalized. 417 std::map<SDNode*, unsigned> Visited; 418 std::vector<SDNode*> Order; 419 420 // Compute ordering from all of the leaves in the graphs, those (like the 421 // entry node) that have no operands. 422 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 423 E = DAG.allnodes_end(); I != E; ++I) { 424 if (I->getNumOperands() == 0) { 425 Visited[I] = 0 - 1U; 426 ComputeTopDownOrdering(I, Order, Visited); 427 } 428 } 429 430 assert(Order.size() == Visited.size() && 431 Order.size() == 432 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 433 "Error: DAG is cyclic!"); 434 Visited.clear(); 435 436 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 437 SDNode *N = Order[i]; 438 switch (getTypeAction(N->getValueType(0))) { 439 default: assert(0 && "Bad type action!"); 440 case Legal: 441 LegalizeOp(SDOperand(N, 0)); 442 break; 443 case Promote: 444 PromoteOp(SDOperand(N, 0)); 445 break; 446 case Expand: { 447 SDOperand X, Y; 448 ExpandOp(SDOperand(N, 0), X, Y); 449 break; 450 } 451 } 452 } 453 454 // Finally, it's possible the root changed. Get the new root. 455 SDOperand OldRoot = DAG.getRoot(); 456 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 457 DAG.setRoot(LegalizedNodes[OldRoot]); 458 459 ExpandedNodes.clear(); 460 LegalizedNodes.clear(); 461 PromotedNodes.clear(); 462 463 // Remove dead nodes now. 464 DAG.RemoveDeadNodes(OldRoot.Val); 465} 466 467SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 468 assert(isTypeLegal(Op.getValueType()) && 469 "Caller should expand or promote operands that are not legal!"); 470 SDNode *Node = Op.Val; 471 472 // If this operation defines any values that cannot be represented in a 473 // register on this target, make sure to expand or promote them. 474 if (Node->getNumValues() > 1) { 475 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 476 switch (getTypeAction(Node->getValueType(i))) { 477 case Legal: break; // Nothing to do. 478 case Expand: { 479 SDOperand T1, T2; 480 ExpandOp(Op.getValue(i), T1, T2); 481 assert(LegalizedNodes.count(Op) && 482 "Expansion didn't add legal operands!"); 483 return LegalizedNodes[Op]; 484 } 485 case Promote: 486 PromoteOp(Op.getValue(i)); 487 assert(LegalizedNodes.count(Op) && 488 "Expansion didn't add legal operands!"); 489 return LegalizedNodes[Op]; 490 } 491 } 492 493 // Note that LegalizeOp may be reentered even from single-use nodes, which 494 // means that we always must cache transformed nodes. 495 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 496 if (I != LegalizedNodes.end()) return I->second; 497 498 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 499 500 SDOperand Result = Op; 501 502 switch (Node->getOpcode()) { 503 default: 504 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 505 // If this is a target node, legalize it by legalizing the operands then 506 // passing it through. 507 std::vector<SDOperand> Ops; 508 bool Changed = false; 509 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 510 Ops.push_back(LegalizeOp(Node->getOperand(i))); 511 Changed = Changed || Node->getOperand(i) != Ops.back(); 512 } 513 if (Changed) 514 if (Node->getNumValues() == 1) 515 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 516 else { 517 std::vector<MVT::ValueType> VTs(Node->value_begin(), 518 Node->value_end()); 519 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 520 } 521 522 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 523 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 524 return Result.getValue(Op.ResNo); 525 } 526 // Otherwise this is an unhandled builtin node. splat. 527 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 528 assert(0 && "Do not know how to legalize this operator!"); 529 abort(); 530 case ISD::EntryToken: 531 case ISD::FrameIndex: 532 case ISD::TargetFrameIndex: 533 case ISD::Register: 534 case ISD::TargetConstant: 535 case ISD::GlobalAddress: 536 case ISD::TargetGlobalAddress: 537 case ISD::ExternalSymbol: 538 case ISD::ConstantPool: // Nothing to do. 539 case ISD::BasicBlock: 540 case ISD::CONDCODE: 541 case ISD::VALUETYPE: 542 case ISD::SRCVALUE: 543 case ISD::STRING: 544 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 545 default: assert(0 && "This action is not supported yet!"); 546 case TargetLowering::Custom: { 547 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 548 if (Tmp.Val) { 549 Result = LegalizeOp(Tmp); 550 break; 551 } 552 } // FALLTHROUGH if the target doesn't want to lower this op after all. 553 case TargetLowering::Legal: 554 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!"); 555 break; 556 } 557 break; 558 case ISD::AssertSext: 559 case ISD::AssertZext: 560 Tmp1 = LegalizeOp(Node->getOperand(0)); 561 if (Tmp1 != Node->getOperand(0)) 562 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 563 Node->getOperand(1)); 564 break; 565 case ISD::MERGE_VALUES: 566 return LegalizeOp(Node->getOperand(Op.ResNo)); 567 case ISD::CopyFromReg: 568 Tmp1 = LegalizeOp(Node->getOperand(0)); 569 if (Tmp1 != Node->getOperand(0)) 570 Result = DAG.getCopyFromReg(Tmp1, 571 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 572 Node->getValueType(0)); 573 else 574 Result = Op.getValue(0); 575 576 // Since CopyFromReg produces two values, make sure to remember that we 577 // legalized both of them. 578 AddLegalizedOperand(Op.getValue(0), Result); 579 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 580 return Result.getValue(Op.ResNo); 581 case ISD::ImplicitDef: 582 Tmp1 = LegalizeOp(Node->getOperand(0)); 583 if (Tmp1 != Node->getOperand(0)) 584 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other, 585 Tmp1, Node->getOperand(1)); 586 break; 587 case ISD::UNDEF: { 588 MVT::ValueType VT = Op.getValueType(); 589 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 590 default: assert(0 && "This action is not supported yet!"); 591 case TargetLowering::Expand: 592 case TargetLowering::Promote: 593 if (MVT::isInteger(VT)) 594 Result = DAG.getConstant(0, VT); 595 else if (MVT::isFloatingPoint(VT)) 596 Result = DAG.getConstantFP(0, VT); 597 else 598 assert(0 && "Unknown value type!"); 599 break; 600 case TargetLowering::Legal: 601 break; 602 } 603 break; 604 } 605 606 case ISD::LOCATION: 607 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 608 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 609 610 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 611 case TargetLowering::Promote: 612 default: assert(0 && "This action is not supported yet!"); 613 case TargetLowering::Expand: 614 // If the target doesn't support line numbers, ignore this node. 615 Result = Tmp1; 616 break; 617 case TargetLowering::Legal: 618 if (Tmp1 != Node->getOperand(0) || 619 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 620 std::vector<SDOperand> Ops; 621 Ops.push_back(Tmp1); 622 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 623 Ops.push_back(Node->getOperand(1)); // line # must be legal. 624 Ops.push_back(Node->getOperand(2)); // col # must be legal. 625 } else { 626 // Otherwise promote them. 627 Ops.push_back(PromoteOp(Node->getOperand(1))); 628 Ops.push_back(PromoteOp(Node->getOperand(2))); 629 } 630 Ops.push_back(Node->getOperand(3)); // filename must be legal. 631 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 632 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops); 633 } 634 break; 635 } 636 break; 637 638 case ISD::Constant: 639 // We know we don't need to expand constants here, constants only have one 640 // value and we check that it is fine above. 641 642 // FIXME: Maybe we should handle things like targets that don't support full 643 // 32-bit immediates? 644 break; 645 case ISD::ConstantFP: { 646 // Spill FP immediates to the constant pool if the target cannot directly 647 // codegen them. Targets often have some immediate values that can be 648 // efficiently generated into an FP register without a load. We explicitly 649 // leave these constants as ConstantFP nodes for the target to deal with. 650 651 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 652 653 // Check to see if this FP immediate is already legal. 654 bool isLegal = false; 655 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 656 E = TLI.legal_fpimm_end(); I != E; ++I) 657 if (CFP->isExactlyValue(*I)) { 658 isLegal = true; 659 break; 660 } 661 662 if (!isLegal) { 663 // Otherwise we need to spill the constant to memory. 664 bool Extend = false; 665 666 // If a FP immediate is precise when represented as a float, we put it 667 // into the constant pool as a float, even if it's is statically typed 668 // as a double. 669 MVT::ValueType VT = CFP->getValueType(0); 670 bool isDouble = VT == MVT::f64; 671 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 672 Type::FloatTy, CFP->getValue()); 673 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 674 // Only do this if the target has a native EXTLOAD instruction from 675 // f32. 676 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 677 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 678 VT = MVT::f32; 679 Extend = true; 680 } 681 682 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 683 if (Extend) { 684 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 685 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 686 } else { 687 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 688 DAG.getSrcValue(NULL)); 689 } 690 } 691 break; 692 } 693 case ISD::ConstantVec: { 694 // We assume that vector constants are not legal, and will be immediately 695 // spilled to the constant pool. 696 // 697 // FIXME: revisit this when we have some kind of mechanism by which targets 698 // can decided legality of vector constants, of which there may be very 699 // many. 700 // 701 // Create a ConstantPacked, and put it in the constant pool. 702 std::vector<Constant*> CV; 703 MVT::ValueType VT = Node->getValueType(0); 704 for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) { 705 SDOperand OpN = Node->getOperand(I); 706 const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType()); 707 if (MVT::isFloatingPoint(VT)) 708 CV.push_back(ConstantFP::get(OpNTy, 709 cast<ConstantFPSDNode>(OpN)->getValue())); 710 else 711 CV.push_back(ConstantUInt::get(OpNTy, 712 cast<ConstantSDNode>(OpN)->getValue())); 713 } 714 Constant *CP = ConstantPacked::get(CV); 715 SDOperand CPIdx = DAG.getConstantPool(CP, Node->getValueType(0)); 716 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL)); 717 break; 718 } 719 case ISD::TokenFactor: 720 if (Node->getNumOperands() == 2) { 721 bool Changed = false; 722 SDOperand Op0 = LegalizeOp(Node->getOperand(0)); 723 SDOperand Op1 = LegalizeOp(Node->getOperand(1)); 724 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1)) 725 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1); 726 } else { 727 std::vector<SDOperand> Ops; 728 bool Changed = false; 729 // Legalize the operands. 730 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 731 SDOperand Op = Node->getOperand(i); 732 Ops.push_back(LegalizeOp(Op)); 733 Changed |= Ops[i] != Op; 734 } 735 if (Changed) 736 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 737 } 738 break; 739 740 case ISD::CALLSEQ_START: 741 case ISD::CALLSEQ_END: 742 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 743 // Do not try to legalize the target-specific arguments (#1+) 744 Tmp2 = Node->getOperand(0); 745 if (Tmp1 != Tmp2) 746 Node->setAdjCallChain(Tmp1); 747 748 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These 749 // nodes are treated specially and are mutated in place. This makes the dag 750 // legalization process more efficient and also makes libcall insertion 751 // easier. 752 break; 753 case ISD::DYNAMIC_STACKALLOC: 754 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 755 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 756 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 757 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 758 Tmp3 != Node->getOperand(2)) { 759 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 760 std::vector<SDOperand> Ops; 761 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 762 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 763 } else 764 Result = Op.getValue(0); 765 766 // Since this op produces two values, make sure to remember that we 767 // legalized both of them. 768 AddLegalizedOperand(SDOperand(Node, 0), Result); 769 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 770 return Result.getValue(Op.ResNo); 771 772 case ISD::TAILCALL: 773 case ISD::CALL: { 774 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 775 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 776 777 bool Changed = false; 778 std::vector<SDOperand> Ops; 779 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 780 Ops.push_back(LegalizeOp(Node->getOperand(i))); 781 Changed |= Ops.back() != Node->getOperand(i); 782 } 783 784 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 785 std::vector<MVT::ValueType> RetTyVTs; 786 RetTyVTs.reserve(Node->getNumValues()); 787 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 788 RetTyVTs.push_back(Node->getValueType(i)); 789 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 790 Node->getOpcode() == ISD::TAILCALL), 0); 791 } else { 792 Result = Result.getValue(0); 793 } 794 // Since calls produce multiple values, make sure to remember that we 795 // legalized all of them. 796 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 797 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 798 return Result.getValue(Op.ResNo); 799 } 800 case ISD::BR: 801 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 802 if (Tmp1 != Node->getOperand(0)) 803 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 804 break; 805 806 case ISD::BRCOND: 807 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 808 809 switch (getTypeAction(Node->getOperand(1).getValueType())) { 810 case Expand: assert(0 && "It's impossible to expand bools"); 811 case Legal: 812 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 813 break; 814 case Promote: 815 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 816 break; 817 } 818 819 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 820 default: assert(0 && "This action is not supported yet!"); 821 case TargetLowering::Expand: 822 // Expand brcond's setcc into its constituent parts and create a BR_CC 823 // Node. 824 if (Tmp2.getOpcode() == ISD::SETCC) { 825 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 826 Tmp2.getOperand(0), Tmp2.getOperand(1), 827 Node->getOperand(2)); 828 } else { 829 // Make sure the condition is either zero or one. It may have been 830 // promoted from something else. 831 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 832 833 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 834 DAG.getCondCode(ISD::SETNE), Tmp2, 835 DAG.getConstant(0, Tmp2.getValueType()), 836 Node->getOperand(2)); 837 } 838 break; 839 case TargetLowering::Legal: 840 // Basic block destination (Op#2) is always legal. 841 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 842 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 843 Node->getOperand(2)); 844 break; 845 } 846 break; 847 case ISD::BR_CC: 848 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 849 850 if (isTypeLegal(Node->getOperand(2).getValueType())) { 851 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 852 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 853 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 854 Tmp3 != Node->getOperand(3)) { 855 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 856 Tmp2, Tmp3, Node->getOperand(4)); 857 } 858 break; 859 } else { 860 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 861 Node->getOperand(2), // LHS 862 Node->getOperand(3), // RHS 863 Node->getOperand(1))); 864 // If we get a SETCC back from legalizing the SETCC node we just 865 // created, then use its LHS, RHS, and CC directly in creating a new 866 // node. Otherwise, select between the true and false value based on 867 // comparing the result of the legalized with zero. 868 if (Tmp2.getOpcode() == ISD::SETCC) { 869 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 870 Tmp2.getOperand(0), Tmp2.getOperand(1), 871 Node->getOperand(4)); 872 } else { 873 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 874 DAG.getCondCode(ISD::SETNE), 875 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 876 Node->getOperand(4)); 877 } 878 } 879 break; 880 case ISD::BRCONDTWOWAY: 881 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 882 switch (getTypeAction(Node->getOperand(1).getValueType())) { 883 case Expand: assert(0 && "It's impossible to expand bools"); 884 case Legal: 885 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 886 break; 887 case Promote: 888 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 889 break; 890 } 891 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 892 // pair. 893 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 894 case TargetLowering::Promote: 895 default: assert(0 && "This action is not supported yet!"); 896 case TargetLowering::Legal: 897 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 898 std::vector<SDOperand> Ops; 899 Ops.push_back(Tmp1); 900 Ops.push_back(Tmp2); 901 Ops.push_back(Node->getOperand(2)); 902 Ops.push_back(Node->getOperand(3)); 903 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 904 } 905 break; 906 case TargetLowering::Expand: 907 // If BRTWOWAY_CC is legal for this target, then simply expand this node 908 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 909 // BRCOND/BR pair. 910 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 911 if (Tmp2.getOpcode() == ISD::SETCC) { 912 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 913 Tmp2.getOperand(0), Tmp2.getOperand(1), 914 Node->getOperand(2), Node->getOperand(3)); 915 } else { 916 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 917 DAG.getConstant(0, Tmp2.getValueType()), 918 Node->getOperand(2), Node->getOperand(3)); 919 } 920 } else { 921 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 922 Node->getOperand(2)); 923 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 924 } 925 break; 926 } 927 break; 928 case ISD::BRTWOWAY_CC: 929 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 930 if (isTypeLegal(Node->getOperand(2).getValueType())) { 931 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 932 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 933 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 934 Tmp3 != Node->getOperand(3)) { 935 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3, 936 Node->getOperand(4), Node->getOperand(5)); 937 } 938 break; 939 } else { 940 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 941 Node->getOperand(2), // LHS 942 Node->getOperand(3), // RHS 943 Node->getOperand(1))); 944 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 945 // pair. 946 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 947 default: assert(0 && "This action is not supported yet!"); 948 case TargetLowering::Legal: 949 // If we get a SETCC back from legalizing the SETCC node we just 950 // created, then use its LHS, RHS, and CC directly in creating a new 951 // node. Otherwise, select between the true and false value based on 952 // comparing the result of the legalized with zero. 953 if (Tmp2.getOpcode() == ISD::SETCC) { 954 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 955 Tmp2.getOperand(0), Tmp2.getOperand(1), 956 Node->getOperand(4), Node->getOperand(5)); 957 } else { 958 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 959 DAG.getConstant(0, Tmp2.getValueType()), 960 Node->getOperand(4), Node->getOperand(5)); 961 } 962 break; 963 case TargetLowering::Expand: 964 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 965 Node->getOperand(4)); 966 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 967 break; 968 } 969 } 970 break; 971 case ISD::LOAD: 972 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 973 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 974 975 if (Tmp1 != Node->getOperand(0) || 976 Tmp2 != Node->getOperand(1)) 977 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, 978 Node->getOperand(2)); 979 else 980 Result = SDOperand(Node, 0); 981 982 // Since loads produce two values, make sure to remember that we legalized 983 // both of them. 984 AddLegalizedOperand(SDOperand(Node, 0), Result); 985 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 986 return Result.getValue(Op.ResNo); 987 988 case ISD::EXTLOAD: 989 case ISD::SEXTLOAD: 990 case ISD::ZEXTLOAD: { 991 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 992 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 993 994 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 995 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 996 default: assert(0 && "This action is not supported yet!"); 997 case TargetLowering::Promote: 998 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 999 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1000 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 1001 // Since loads produce two values, make sure to remember that we legalized 1002 // both of them. 1003 AddLegalizedOperand(SDOperand(Node, 0), Result); 1004 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1005 return Result.getValue(Op.ResNo); 1006 1007 case TargetLowering::Legal: 1008 if (Tmp1 != Node->getOperand(0) || 1009 Tmp2 != Node->getOperand(1)) 1010 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1011 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1012 else 1013 Result = SDOperand(Node, 0); 1014 1015 // Since loads produce two values, make sure to remember that we legalized 1016 // both of them. 1017 AddLegalizedOperand(SDOperand(Node, 0), Result); 1018 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1019 return Result.getValue(Op.ResNo); 1020 case TargetLowering::Expand: 1021 //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1022 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1023 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 1024 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1025 if (Op.ResNo) 1026 return Load.getValue(1); 1027 return Result; 1028 } 1029 assert(Node->getOpcode() != ISD::EXTLOAD && 1030 "EXTLOAD should always be supported!"); 1031 // Turn the unsupported load into an EXTLOAD followed by an explicit 1032 // zero/sign extend inreg. 1033 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1034 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1035 SDOperand ValRes; 1036 if (Node->getOpcode() == ISD::SEXTLOAD) 1037 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1038 Result, DAG.getValueType(SrcVT)); 1039 else 1040 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1041 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 1042 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1043 if (Op.ResNo) 1044 return Result.getValue(1); 1045 return ValRes; 1046 } 1047 assert(0 && "Unreachable"); 1048 } 1049 case ISD::EXTRACT_ELEMENT: { 1050 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1051 switch (getTypeAction(OpTy)) { 1052 default: 1053 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1054 break; 1055 case Legal: 1056 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1057 // 1 -> Hi 1058 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1059 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1060 TLI.getShiftAmountTy())); 1061 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1062 } else { 1063 // 0 -> Lo 1064 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1065 Node->getOperand(0)); 1066 } 1067 Result = LegalizeOp(Result); 1068 break; 1069 case Expand: 1070 // Get both the low and high parts. 1071 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1072 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1073 Result = Tmp2; // 1 -> Hi 1074 else 1075 Result = Tmp1; // 0 -> Lo 1076 break; 1077 } 1078 break; 1079 } 1080 1081 case ISD::CopyToReg: 1082 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1083 1084 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1085 "Register type must be legal!"); 1086 // Legalize the incoming value (must be legal). 1087 Tmp2 = LegalizeOp(Node->getOperand(2)); 1088 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2)) 1089 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1, 1090 Node->getOperand(1), Tmp2); 1091 break; 1092 1093 case ISD::RET: 1094 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1095 switch (Node->getNumOperands()) { 1096 case 2: // ret val 1097 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1098 case Legal: 1099 Tmp2 = LegalizeOp(Node->getOperand(1)); 1100 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1101 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1102 break; 1103 case Expand: { 1104 SDOperand Lo, Hi; 1105 ExpandOp(Node->getOperand(1), Lo, Hi); 1106 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1107 break; 1108 } 1109 case Promote: 1110 Tmp2 = PromoteOp(Node->getOperand(1)); 1111 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1112 break; 1113 } 1114 break; 1115 case 1: // ret void 1116 if (Tmp1 != Node->getOperand(0)) 1117 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 1118 break; 1119 default: { // ret <values> 1120 std::vector<SDOperand> NewValues; 1121 NewValues.push_back(Tmp1); 1122 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1123 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1124 case Legal: 1125 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1126 break; 1127 case Expand: { 1128 SDOperand Lo, Hi; 1129 ExpandOp(Node->getOperand(i), Lo, Hi); 1130 NewValues.push_back(Lo); 1131 NewValues.push_back(Hi); 1132 break; 1133 } 1134 case Promote: 1135 assert(0 && "Can't promote multiple return value yet!"); 1136 } 1137 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1138 break; 1139 } 1140 } 1141 break; 1142 case ISD::STORE: 1143 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1144 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1145 1146 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1147 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1148 if (CFP->getValueType(0) == MVT::f32) { 1149 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1150 DAG.getConstant(FloatToBits(CFP->getValue()), 1151 MVT::i32), 1152 Tmp2, 1153 Node->getOperand(3)); 1154 } else { 1155 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1156 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1157 DAG.getConstant(DoubleToBits(CFP->getValue()), 1158 MVT::i64), 1159 Tmp2, 1160 Node->getOperand(3)); 1161 } 1162 Node = Result.Val; 1163 } 1164 1165 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1166 case Legal: { 1167 SDOperand Val = LegalizeOp(Node->getOperand(1)); 1168 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 1169 Tmp2 != Node->getOperand(2)) 1170 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 1171 Node->getOperand(3)); 1172 break; 1173 } 1174 case Promote: 1175 // Truncate the value and store the result. 1176 Tmp3 = PromoteOp(Node->getOperand(1)); 1177 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1178 Node->getOperand(3), 1179 DAG.getValueType(Node->getOperand(1).getValueType())); 1180 break; 1181 1182 case Expand: 1183 SDOperand Lo, Hi; 1184 unsigned IncrementSize; 1185 ExpandOp(Node->getOperand(1), Lo, Hi); 1186 1187 if (!TLI.isLittleEndian()) 1188 std::swap(Lo, Hi); 1189 1190 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1191 Node->getOperand(3)); 1192 // If this is a vector type, then we have to calculate the increment as 1193 // the product of the element size in bytes, and the number of elements 1194 // in the high half of the vector. 1195 if (MVT::Vector == Hi.getValueType()) { 1196 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue(); 1197 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT(); 1198 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8; 1199 } else { 1200 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1201 } 1202 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1203 getIntPtrConstant(IncrementSize)); 1204 assert(isTypeLegal(Tmp2.getValueType()) && 1205 "Pointers must be legal!"); 1206 //Again, claiming both parts of the store came form the same Instr 1207 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1208 Node->getOperand(3)); 1209 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1210 break; 1211 } 1212 break; 1213 case ISD::PCMARKER: 1214 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1215 if (Tmp1 != Node->getOperand(0)) 1216 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 1217 break; 1218 case ISD::READCYCLECOUNTER: 1219 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1220 if (Tmp1 != Node->getOperand(0)) { 1221 std::vector<MVT::ValueType> rtypes; 1222 std::vector<SDOperand> rvals; 1223 rtypes.push_back(MVT::i64); 1224 rtypes.push_back(MVT::Other); 1225 rvals.push_back(Tmp1); 1226 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals); 1227 } 1228 1229 // Since rdcc produce two values, make sure to remember that we legalized 1230 // both of them. 1231 AddLegalizedOperand(SDOperand(Node, 0), Result); 1232 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1233 return Result.getValue(Op.ResNo); 1234 break; 1235 1236 case ISD::TRUNCSTORE: 1237 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1238 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1239 1240 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1241 case Legal: 1242 Tmp2 = LegalizeOp(Node->getOperand(1)); 1243 1244 // The only promote case we handle is TRUNCSTORE:i1 X into 1245 // -> TRUNCSTORE:i8 (and X, 1) 1246 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1247 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1248 TargetLowering::Promote) { 1249 // Promote the bool to a mask then store. 1250 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1251 DAG.getConstant(1, Tmp2.getValueType())); 1252 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1253 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1254 1255 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1256 Tmp3 != Node->getOperand(2)) { 1257 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1258 Node->getOperand(3), Node->getOperand(4)); 1259 } 1260 break; 1261 case Promote: 1262 case Expand: 1263 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 1264 } 1265 break; 1266 case ISD::SELECT: 1267 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1268 case Expand: assert(0 && "It's impossible to expand bools"); 1269 case Legal: 1270 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1271 break; 1272 case Promote: 1273 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1274 break; 1275 } 1276 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1277 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1278 1279 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1280 default: assert(0 && "This action is not supported yet!"); 1281 case TargetLowering::Expand: 1282 if (Tmp1.getOpcode() == ISD::SETCC) { 1283 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1284 Tmp2, Tmp3, 1285 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1286 } else { 1287 // Make sure the condition is either zero or one. It may have been 1288 // promoted from something else. 1289 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1290 Result = DAG.getSelectCC(Tmp1, 1291 DAG.getConstant(0, Tmp1.getValueType()), 1292 Tmp2, Tmp3, ISD::SETNE); 1293 } 1294 break; 1295 case TargetLowering::Legal: 1296 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1297 Tmp3 != Node->getOperand(2)) 1298 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 1299 Tmp1, Tmp2, Tmp3); 1300 break; 1301 case TargetLowering::Promote: { 1302 MVT::ValueType NVT = 1303 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1304 unsigned ExtOp, TruncOp; 1305 if (MVT::isInteger(Tmp2.getValueType())) { 1306 ExtOp = ISD::ANY_EXTEND; 1307 TruncOp = ISD::TRUNCATE; 1308 } else { 1309 ExtOp = ISD::FP_EXTEND; 1310 TruncOp = ISD::FP_ROUND; 1311 } 1312 // Promote each of the values to the new type. 1313 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1314 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1315 // Perform the larger operation, then round down. 1316 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1317 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1318 break; 1319 } 1320 } 1321 break; 1322 case ISD::SELECT_CC: 1323 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1324 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1325 1326 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1327 // Everything is legal, see if we should expand this op or something. 1328 switch (TLI.getOperationAction(ISD::SELECT_CC, 1329 Node->getOperand(0).getValueType())) { 1330 default: assert(0 && "This action is not supported yet!"); 1331 case TargetLowering::Custom: { 1332 SDOperand Tmp = 1333 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), 1334 Node->getOperand(0), 1335 Node->getOperand(1), Tmp3, Tmp4, 1336 Node->getOperand(4)), DAG); 1337 if (Tmp.Val) { 1338 Result = LegalizeOp(Tmp); 1339 break; 1340 } 1341 } // FALLTHROUGH if the target can't lower this operation after all. 1342 case TargetLowering::Legal: 1343 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1344 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1345 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1346 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { 1347 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2, 1348 Tmp3, Tmp4, Node->getOperand(4)); 1349 } 1350 break; 1351 } 1352 break; 1353 } else { 1354 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1355 Node->getOperand(0), // LHS 1356 Node->getOperand(1), // RHS 1357 Node->getOperand(4))); 1358 // If we get a SETCC back from legalizing the SETCC node we just 1359 // created, then use its LHS, RHS, and CC directly in creating a new 1360 // node. Otherwise, select between the true and false value based on 1361 // comparing the result of the legalized with zero. 1362 if (Tmp1.getOpcode() == ISD::SETCC) { 1363 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1364 Tmp1.getOperand(0), Tmp1.getOperand(1), 1365 Tmp3, Tmp4, Tmp1.getOperand(2)); 1366 } else { 1367 Result = DAG.getSelectCC(Tmp1, 1368 DAG.getConstant(0, Tmp1.getValueType()), 1369 Tmp3, Tmp4, ISD::SETNE); 1370 } 1371 } 1372 break; 1373 case ISD::SETCC: 1374 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1375 case Legal: 1376 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1377 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1378 break; 1379 case Promote: 1380 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1381 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1382 1383 // If this is an FP compare, the operands have already been extended. 1384 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1385 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1386 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1387 1388 // Otherwise, we have to insert explicit sign or zero extends. Note 1389 // that we could insert sign extends for ALL conditions, but zero extend 1390 // is cheaper on many machines (an AND instead of two shifts), so prefer 1391 // it. 1392 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1393 default: assert(0 && "Unknown integer comparison!"); 1394 case ISD::SETEQ: 1395 case ISD::SETNE: 1396 case ISD::SETUGE: 1397 case ISD::SETUGT: 1398 case ISD::SETULE: 1399 case ISD::SETULT: 1400 // ALL of these operations will work if we either sign or zero extend 1401 // the operands (including the unsigned comparisons!). Zero extend is 1402 // usually a simpler/cheaper operation, so prefer it. 1403 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1404 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1405 break; 1406 case ISD::SETGE: 1407 case ISD::SETGT: 1408 case ISD::SETLT: 1409 case ISD::SETLE: 1410 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1411 DAG.getValueType(VT)); 1412 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1413 DAG.getValueType(VT)); 1414 break; 1415 } 1416 } 1417 break; 1418 case Expand: 1419 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1420 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1421 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1422 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1423 case ISD::SETEQ: 1424 case ISD::SETNE: 1425 if (RHSLo == RHSHi) 1426 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1427 if (RHSCST->isAllOnesValue()) { 1428 // Comparison to -1. 1429 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1430 Tmp2 = RHSLo; 1431 break; 1432 } 1433 1434 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1435 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1436 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1437 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1438 break; 1439 default: 1440 // If this is a comparison of the sign bit, just look at the top part. 1441 // X > -1, x < 0 1442 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1443 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1444 CST->getValue() == 0) || // X < 0 1445 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1446 (CST->isAllOnesValue()))) { // X > -1 1447 Tmp1 = LHSHi; 1448 Tmp2 = RHSHi; 1449 break; 1450 } 1451 1452 // FIXME: This generated code sucks. 1453 ISD::CondCode LowCC; 1454 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1455 default: assert(0 && "Unknown integer setcc!"); 1456 case ISD::SETLT: 1457 case ISD::SETULT: LowCC = ISD::SETULT; break; 1458 case ISD::SETGT: 1459 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1460 case ISD::SETLE: 1461 case ISD::SETULE: LowCC = ISD::SETULE; break; 1462 case ISD::SETGE: 1463 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1464 } 1465 1466 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1467 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1468 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1469 1470 // NOTE: on targets without efficient SELECT of bools, we can always use 1471 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1472 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1473 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1474 Node->getOperand(2)); 1475 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1476 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1477 Result, Tmp1, Tmp2)); 1478 return Result; 1479 } 1480 } 1481 1482 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) { 1483 default: 1484 assert(0 && "Cannot handle this action for SETCC yet!"); 1485 break; 1486 case TargetLowering::Promote: { 1487 // First step, figure out the appropriate operation to use. 1488 // Allow SETCC to not be supported for all legal data types 1489 // Mostly this targets FP 1490 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1491 MVT::ValueType OldVT = NewInTy; 1492 1493 // Scan for the appropriate larger type to use. 1494 while (1) { 1495 NewInTy = (MVT::ValueType)(NewInTy+1); 1496 1497 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1498 "Fell off of the edge of the integer world"); 1499 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1500 "Fell off of the edge of the floating point world"); 1501 1502 // If the target supports SETCC of this type, use it. 1503 if (TLI.getOperationAction(ISD::SETCC, NewInTy) == TargetLowering::Legal) 1504 break; 1505 } 1506 if (MVT::isInteger(NewInTy)) 1507 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1508 else { 1509 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1510 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1511 } 1512 1513 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1514 Node->getOperand(2)); 1515 break; 1516 } 1517 case TargetLowering::Legal: 1518 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1519 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1520 Node->getOperand(2)); 1521 break; 1522 case TargetLowering::Expand: 1523 // Expand a setcc node into a select_cc of the same condition, lhs, and 1524 // rhs that selects between const 1 (true) and const 0 (false). 1525 MVT::ValueType VT = Node->getValueType(0); 1526 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1527 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1528 Node->getOperand(2)); 1529 Result = LegalizeOp(Result); 1530 break; 1531 } 1532 break; 1533 1534 case ISD::MEMSET: 1535 case ISD::MEMCPY: 1536 case ISD::MEMMOVE: { 1537 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1538 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1539 1540 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1541 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1542 case Expand: assert(0 && "Cannot expand a byte!"); 1543 case Legal: 1544 Tmp3 = LegalizeOp(Node->getOperand(2)); 1545 break; 1546 case Promote: 1547 Tmp3 = PromoteOp(Node->getOperand(2)); 1548 break; 1549 } 1550 } else { 1551 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1552 } 1553 1554 SDOperand Tmp4; 1555 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1556 case Expand: { 1557 // Length is too big, just take the lo-part of the length. 1558 SDOperand HiPart; 1559 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1560 break; 1561 } 1562 case Legal: 1563 Tmp4 = LegalizeOp(Node->getOperand(3)); 1564 break; 1565 case Promote: 1566 Tmp4 = PromoteOp(Node->getOperand(3)); 1567 break; 1568 } 1569 1570 SDOperand Tmp5; 1571 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1572 case Expand: assert(0 && "Cannot expand this yet!"); 1573 case Legal: 1574 Tmp5 = LegalizeOp(Node->getOperand(4)); 1575 break; 1576 case Promote: 1577 Tmp5 = PromoteOp(Node->getOperand(4)); 1578 break; 1579 } 1580 1581 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1582 default: assert(0 && "This action not implemented for this operation!"); 1583 case TargetLowering::Custom: { 1584 SDOperand Tmp = 1585 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 1586 Tmp2, Tmp3, Tmp4, Tmp5), DAG); 1587 if (Tmp.Val) { 1588 Result = LegalizeOp(Tmp); 1589 break; 1590 } 1591 // FALLTHROUGH if the target thinks it is legal. 1592 } 1593 case TargetLowering::Legal: 1594 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1595 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 1596 Tmp5 != Node->getOperand(4)) { 1597 std::vector<SDOperand> Ops; 1598 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 1599 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 1600 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 1601 } 1602 break; 1603 case TargetLowering::Expand: { 1604 // Otherwise, the target does not support this operation. Lower the 1605 // operation to an explicit libcall as appropriate. 1606 MVT::ValueType IntPtr = TLI.getPointerTy(); 1607 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1608 std::vector<std::pair<SDOperand, const Type*> > Args; 1609 1610 const char *FnName = 0; 1611 if (Node->getOpcode() == ISD::MEMSET) { 1612 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1613 // Extend the ubyte argument to be an int value for the call. 1614 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1615 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1616 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1617 1618 FnName = "memset"; 1619 } else if (Node->getOpcode() == ISD::MEMCPY || 1620 Node->getOpcode() == ISD::MEMMOVE) { 1621 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1622 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1623 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1624 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1625 } else { 1626 assert(0 && "Unknown op!"); 1627 } 1628 1629 std::pair<SDOperand,SDOperand> CallResult = 1630 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1631 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1632 Result = CallResult.second; 1633 NeedsAnotherIteration = true; 1634 break; 1635 } 1636 } 1637 break; 1638 } 1639 1640 case ISD::READPORT: 1641 Tmp1 = LegalizeOp(Node->getOperand(0)); 1642 Tmp2 = LegalizeOp(Node->getOperand(1)); 1643 1644 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1645 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1646 std::vector<SDOperand> Ops; 1647 Ops.push_back(Tmp1); 1648 Ops.push_back(Tmp2); 1649 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1650 } else 1651 Result = SDOperand(Node, 0); 1652 // Since these produce two values, make sure to remember that we legalized 1653 // both of them. 1654 AddLegalizedOperand(SDOperand(Node, 0), Result); 1655 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1656 return Result.getValue(Op.ResNo); 1657 case ISD::WRITEPORT: 1658 Tmp1 = LegalizeOp(Node->getOperand(0)); 1659 Tmp2 = LegalizeOp(Node->getOperand(1)); 1660 Tmp3 = LegalizeOp(Node->getOperand(2)); 1661 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1662 Tmp3 != Node->getOperand(2)) 1663 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1664 break; 1665 1666 case ISD::READIO: 1667 Tmp1 = LegalizeOp(Node->getOperand(0)); 1668 Tmp2 = LegalizeOp(Node->getOperand(1)); 1669 1670 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1671 case TargetLowering::Custom: 1672 default: assert(0 && "This action not implemented for this operation!"); 1673 case TargetLowering::Legal: 1674 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1675 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1676 std::vector<SDOperand> Ops; 1677 Ops.push_back(Tmp1); 1678 Ops.push_back(Tmp2); 1679 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1680 } else 1681 Result = SDOperand(Node, 0); 1682 break; 1683 case TargetLowering::Expand: 1684 // Replace this with a load from memory. 1685 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 1686 Node->getOperand(1), DAG.getSrcValue(NULL)); 1687 Result = LegalizeOp(Result); 1688 break; 1689 } 1690 1691 // Since these produce two values, make sure to remember that we legalized 1692 // both of them. 1693 AddLegalizedOperand(SDOperand(Node, 0), Result); 1694 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1695 return Result.getValue(Op.ResNo); 1696 1697 case ISD::WRITEIO: 1698 Tmp1 = LegalizeOp(Node->getOperand(0)); 1699 Tmp2 = LegalizeOp(Node->getOperand(1)); 1700 Tmp3 = LegalizeOp(Node->getOperand(2)); 1701 1702 switch (TLI.getOperationAction(Node->getOpcode(), 1703 Node->getOperand(1).getValueType())) { 1704 case TargetLowering::Custom: 1705 default: assert(0 && "This action not implemented for this operation!"); 1706 case TargetLowering::Legal: 1707 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1708 Tmp3 != Node->getOperand(2)) 1709 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1710 break; 1711 case TargetLowering::Expand: 1712 // Replace this with a store to memory. 1713 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 1714 Node->getOperand(1), Node->getOperand(2), 1715 DAG.getSrcValue(NULL)); 1716 Result = LegalizeOp(Result); 1717 break; 1718 } 1719 break; 1720 1721 case ISD::ADD_PARTS: 1722 case ISD::SUB_PARTS: 1723 case ISD::SHL_PARTS: 1724 case ISD::SRA_PARTS: 1725 case ISD::SRL_PARTS: { 1726 std::vector<SDOperand> Ops; 1727 bool Changed = false; 1728 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1729 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1730 Changed |= Ops.back() != Node->getOperand(i); 1731 } 1732 if (Changed) { 1733 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1734 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 1735 } 1736 1737 // Since these produce multiple values, make sure to remember that we 1738 // legalized all of them. 1739 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1740 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1741 return Result.getValue(Op.ResNo); 1742 } 1743 1744 // Binary operators 1745 case ISD::ADD: 1746 case ISD::SUB: 1747 case ISD::MUL: 1748 case ISD::MULHS: 1749 case ISD::MULHU: 1750 case ISD::UDIV: 1751 case ISD::SDIV: 1752 case ISD::AND: 1753 case ISD::OR: 1754 case ISD::XOR: 1755 case ISD::SHL: 1756 case ISD::SRL: 1757 case ISD::SRA: 1758 case ISD::FADD: 1759 case ISD::FSUB: 1760 case ISD::FMUL: 1761 case ISD::FDIV: 1762 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1763 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1764 case Expand: assert(0 && "Not possible"); 1765 case Legal: 1766 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1767 break; 1768 case Promote: 1769 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 1770 break; 1771 } 1772 if (Tmp1 != Node->getOperand(0) || 1773 Tmp2 != Node->getOperand(1)) 1774 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 1775 break; 1776 1777 case ISD::BUILD_PAIR: { 1778 MVT::ValueType PairTy = Node->getValueType(0); 1779 // TODO: handle the case where the Lo and Hi operands are not of legal type 1780 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 1781 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 1782 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 1783 case TargetLowering::Legal: 1784 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1785 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 1786 break; 1787 case TargetLowering::Promote: 1788 case TargetLowering::Custom: 1789 assert(0 && "Cannot promote/custom this yet!"); 1790 case TargetLowering::Expand: 1791 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 1792 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 1793 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 1794 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 1795 TLI.getShiftAmountTy())); 1796 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2)); 1797 break; 1798 } 1799 break; 1800 } 1801 1802 case ISD::UREM: 1803 case ISD::SREM: 1804 case ISD::FREM: 1805 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1806 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1807 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1808 case TargetLowering::Legal: 1809 if (Tmp1 != Node->getOperand(0) || 1810 Tmp2 != Node->getOperand(1)) 1811 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1812 Tmp2); 1813 break; 1814 case TargetLowering::Promote: 1815 case TargetLowering::Custom: 1816 assert(0 && "Cannot promote/custom handle this yet!"); 1817 case TargetLowering::Expand: 1818 if (MVT::isInteger(Node->getValueType(0))) { 1819 MVT::ValueType VT = Node->getValueType(0); 1820 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 1821 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 1822 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 1823 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 1824 } else { 1825 // Floating point mod -> fmod libcall. 1826 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 1827 SDOperand Dummy; 1828 Result = ExpandLibCall(FnName, Node, Dummy); 1829 } 1830 break; 1831 } 1832 break; 1833 1834 case ISD::CTPOP: 1835 case ISD::CTTZ: 1836 case ISD::CTLZ: 1837 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1838 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1839 case TargetLowering::Legal: 1840 if (Tmp1 != Node->getOperand(0)) 1841 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1842 break; 1843 case TargetLowering::Promote: { 1844 MVT::ValueType OVT = Tmp1.getValueType(); 1845 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1846 1847 // Zero extend the argument. 1848 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1849 // Perform the larger operation, then subtract if needed. 1850 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1851 switch(Node->getOpcode()) 1852 { 1853 case ISD::CTPOP: 1854 Result = Tmp1; 1855 break; 1856 case ISD::CTTZ: 1857 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 1858 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 1859 DAG.getConstant(getSizeInBits(NVT), NVT), 1860 ISD::SETEQ); 1861 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 1862 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 1863 break; 1864 case ISD::CTLZ: 1865 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 1866 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 1867 DAG.getConstant(getSizeInBits(NVT) - 1868 getSizeInBits(OVT), NVT)); 1869 break; 1870 } 1871 break; 1872 } 1873 case TargetLowering::Custom: 1874 assert(0 && "Cannot custom handle this yet!"); 1875 case TargetLowering::Expand: 1876 switch(Node->getOpcode()) 1877 { 1878 case ISD::CTPOP: { 1879 static const uint64_t mask[6] = { 1880 0x5555555555555555ULL, 0x3333333333333333ULL, 1881 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 1882 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 1883 }; 1884 MVT::ValueType VT = Tmp1.getValueType(); 1885 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1886 unsigned len = getSizeInBits(VT); 1887 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1888 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 1889 Tmp2 = DAG.getConstant(mask[i], VT); 1890 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1891 Tmp1 = DAG.getNode(ISD::ADD, VT, 1892 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 1893 DAG.getNode(ISD::AND, VT, 1894 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 1895 Tmp2)); 1896 } 1897 Result = Tmp1; 1898 break; 1899 } 1900 case ISD::CTLZ: { 1901 /* for now, we do this: 1902 x = x | (x >> 1); 1903 x = x | (x >> 2); 1904 ... 1905 x = x | (x >>16); 1906 x = x | (x >>32); // for 64-bit input 1907 return popcount(~x); 1908 1909 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ 1910 MVT::ValueType VT = Tmp1.getValueType(); 1911 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1912 unsigned len = getSizeInBits(VT); 1913 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1914 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1915 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, 1916 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); 1917 } 1918 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); 1919 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1920 break; 1921 } 1922 case ISD::CTTZ: { 1923 // for now, we use: { return popcount(~x & (x - 1)); } 1924 // unless the target has ctlz but not ctpop, in which case we use: 1925 // { return 32 - nlz(~x & (x-1)); } 1926 // see also http://www.hackersdelight.org/HDcode/ntz.cc 1927 MVT::ValueType VT = Tmp1.getValueType(); 1928 Tmp2 = DAG.getConstant(~0ULL, VT); 1929 Tmp3 = DAG.getNode(ISD::AND, VT, 1930 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), 1931 DAG.getNode(ISD::SUB, VT, Tmp1, 1932 DAG.getConstant(1, VT))); 1933 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead 1934 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 1935 TLI.isOperationLegal(ISD::CTLZ, VT)) { 1936 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, 1937 DAG.getConstant(getSizeInBits(VT), VT), 1938 DAG.getNode(ISD::CTLZ, VT, Tmp3))); 1939 } else { 1940 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1941 } 1942 break; 1943 } 1944 default: 1945 assert(0 && "Cannot expand this yet!"); 1946 break; 1947 } 1948 break; 1949 } 1950 break; 1951 1952 // Unary operators 1953 case ISD::FABS: 1954 case ISD::FNEG: 1955 case ISD::FSQRT: 1956 case ISD::FSIN: 1957 case ISD::FCOS: 1958 Tmp1 = LegalizeOp(Node->getOperand(0)); 1959 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1960 case TargetLowering::Legal: 1961 if (Tmp1 != Node->getOperand(0)) 1962 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1963 break; 1964 case TargetLowering::Promote: 1965 case TargetLowering::Custom: 1966 assert(0 && "Cannot promote/custom handle this yet!"); 1967 case TargetLowering::Expand: 1968 switch(Node->getOpcode()) { 1969 case ISD::FNEG: { 1970 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 1971 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 1972 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0), 1973 Tmp2, Tmp1)); 1974 break; 1975 } 1976 case ISD::FABS: { 1977 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 1978 MVT::ValueType VT = Node->getValueType(0); 1979 Tmp2 = DAG.getConstantFP(0.0, VT); 1980 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 1981 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 1982 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 1983 Result = LegalizeOp(Result); 1984 break; 1985 } 1986 case ISD::FSQRT: 1987 case ISD::FSIN: 1988 case ISD::FCOS: { 1989 MVT::ValueType VT = Node->getValueType(0); 1990 const char *FnName = 0; 1991 switch(Node->getOpcode()) { 1992 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 1993 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 1994 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 1995 default: assert(0 && "Unreachable!"); 1996 } 1997 SDOperand Dummy; 1998 Result = ExpandLibCall(FnName, Node, Dummy); 1999 break; 2000 } 2001 default: 2002 assert(0 && "Unreachable!"); 2003 } 2004 break; 2005 } 2006 break; 2007 2008 // Conversion operators. The source and destination have different types. 2009 case ISD::SINT_TO_FP: 2010 case ISD::UINT_TO_FP: { 2011 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2012 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2013 case Legal: 2014 switch (TLI.getOperationAction(Node->getOpcode(), 2015 Node->getOperand(0).getValueType())) { 2016 default: assert(0 && "Unknown operation action!"); 2017 case TargetLowering::Expand: 2018 Result = ExpandLegalINT_TO_FP(isSigned, 2019 LegalizeOp(Node->getOperand(0)), 2020 Node->getValueType(0)); 2021 AddLegalizedOperand(Op, Result); 2022 return Result; 2023 case TargetLowering::Promote: 2024 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2025 Node->getValueType(0), 2026 isSigned); 2027 AddLegalizedOperand(Op, Result); 2028 return Result; 2029 case TargetLowering::Legal: 2030 break; 2031 case TargetLowering::Custom: { 2032 Tmp1 = LegalizeOp(Node->getOperand(0)); 2033 SDOperand Tmp = 2034 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2035 Tmp = TLI.LowerOperation(Tmp, DAG); 2036 if (Tmp.Val) { 2037 AddLegalizedOperand(Op, Tmp); 2038 NeedsAnotherIteration = true; 2039 return Tmp; 2040 } else { 2041 assert(0 && "Target Must Lower this"); 2042 } 2043 } 2044 } 2045 2046 Tmp1 = LegalizeOp(Node->getOperand(0)); 2047 if (Tmp1 != Node->getOperand(0)) 2048 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2049 break; 2050 case Expand: 2051 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2052 Node->getValueType(0), Node->getOperand(0)); 2053 break; 2054 case Promote: 2055 if (isSigned) { 2056 Result = PromoteOp(Node->getOperand(0)); 2057 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2058 Result, DAG.getValueType(Node->getOperand(0).getValueType())); 2059 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 2060 } else { 2061 Result = PromoteOp(Node->getOperand(0)); 2062 Result = DAG.getZeroExtendInReg(Result, 2063 Node->getOperand(0).getValueType()); 2064 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 2065 } 2066 break; 2067 } 2068 break; 2069 } 2070 case ISD::TRUNCATE: 2071 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2072 case Legal: 2073 Tmp1 = LegalizeOp(Node->getOperand(0)); 2074 if (Tmp1 != Node->getOperand(0)) 2075 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2076 break; 2077 case Expand: 2078 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2079 2080 // Since the result is legal, we should just be able to truncate the low 2081 // part of the source. 2082 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2083 break; 2084 case Promote: 2085 Result = PromoteOp(Node->getOperand(0)); 2086 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2087 break; 2088 } 2089 break; 2090 2091 case ISD::FP_TO_SINT: 2092 case ISD::FP_TO_UINT: 2093 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2094 case Legal: 2095 Tmp1 = LegalizeOp(Node->getOperand(0)); 2096 2097 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2098 default: assert(0 && "Unknown operation action!"); 2099 case TargetLowering::Expand: 2100 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2101 SDOperand True, False; 2102 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2103 MVT::ValueType NVT = Node->getValueType(0); 2104 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2105 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2106 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2107 Node->getOperand(0), Tmp2, ISD::SETLT); 2108 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2109 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2110 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2111 Tmp2)); 2112 False = DAG.getNode(ISD::XOR, NVT, False, 2113 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2114 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False)); 2115 return Result; 2116 } else { 2117 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2118 } 2119 break; 2120 case TargetLowering::Promote: 2121 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2122 Node->getOpcode() == ISD::FP_TO_SINT); 2123 AddLegalizedOperand(Op, Result); 2124 return Result; 2125 case TargetLowering::Custom: { 2126 SDOperand Tmp = 2127 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2128 Tmp = TLI.LowerOperation(Tmp, DAG); 2129 if (Tmp.Val) { 2130 AddLegalizedOperand(Op, Tmp); 2131 NeedsAnotherIteration = true; 2132 return Tmp; 2133 } else { 2134 // The target thinks this is legal afterall. 2135 break; 2136 } 2137 } 2138 case TargetLowering::Legal: 2139 break; 2140 } 2141 2142 if (Tmp1 != Node->getOperand(0)) 2143 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2144 break; 2145 case Expand: 2146 assert(0 && "Shouldn't need to expand other operators here!"); 2147 case Promote: 2148 Result = PromoteOp(Node->getOperand(0)); 2149 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2150 break; 2151 } 2152 break; 2153 2154 case ISD::ANY_EXTEND: 2155 case ISD::ZERO_EXTEND: 2156 case ISD::SIGN_EXTEND: 2157 case ISD::FP_EXTEND: 2158 case ISD::FP_ROUND: 2159 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2160 case Legal: 2161 Tmp1 = LegalizeOp(Node->getOperand(0)); 2162 if (Tmp1 != Node->getOperand(0)) 2163 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2164 break; 2165 case Expand: 2166 assert(0 && "Shouldn't need to expand other operators here!"); 2167 2168 case Promote: 2169 switch (Node->getOpcode()) { 2170 case ISD::ANY_EXTEND: 2171 Result = PromoteOp(Node->getOperand(0)); 2172 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2173 break; 2174 case ISD::ZERO_EXTEND: 2175 Result = PromoteOp(Node->getOperand(0)); 2176 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2177 Result = DAG.getZeroExtendInReg(Result, 2178 Node->getOperand(0).getValueType()); 2179 break; 2180 case ISD::SIGN_EXTEND: 2181 Result = PromoteOp(Node->getOperand(0)); 2182 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2183 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2184 Result, 2185 DAG.getValueType(Node->getOperand(0).getValueType())); 2186 break; 2187 case ISD::FP_EXTEND: 2188 Result = PromoteOp(Node->getOperand(0)); 2189 if (Result.getValueType() != Op.getValueType()) 2190 // Dynamically dead while we have only 2 FP types. 2191 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2192 break; 2193 case ISD::FP_ROUND: 2194 Result = PromoteOp(Node->getOperand(0)); 2195 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2196 break; 2197 } 2198 } 2199 break; 2200 case ISD::FP_ROUND_INREG: 2201 case ISD::SIGN_EXTEND_INREG: { 2202 Tmp1 = LegalizeOp(Node->getOperand(0)); 2203 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2204 2205 // If this operation is not supported, convert it to a shl/shr or load/store 2206 // pair. 2207 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2208 default: assert(0 && "This action not supported for this op yet!"); 2209 case TargetLowering::Legal: 2210 if (Tmp1 != Node->getOperand(0)) 2211 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2212 DAG.getValueType(ExtraVT)); 2213 break; 2214 case TargetLowering::Expand: 2215 // If this is an integer extend and shifts are supported, do that. 2216 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2217 // NOTE: we could fall back on load/store here too for targets without 2218 // SAR. However, it is doubtful that any exist. 2219 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2220 MVT::getSizeInBits(ExtraVT); 2221 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2222 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2223 Node->getOperand(0), ShiftCst); 2224 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2225 Result, ShiftCst); 2226 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2227 // The only way we can lower this is to turn it into a STORETRUNC, 2228 // EXTLOAD pair, targetting a temporary location (a stack slot). 2229 2230 // NOTE: there is a choice here between constantly creating new stack 2231 // slots and always reusing the same one. We currently always create 2232 // new ones, as reuse may inhibit scheduling. 2233 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2234 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2235 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2236 MachineFunction &MF = DAG.getMachineFunction(); 2237 int SSFI = 2238 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2239 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2240 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2241 Node->getOperand(0), StackSlot, 2242 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2243 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2244 Result, StackSlot, DAG.getSrcValue(NULL), 2245 ExtraVT); 2246 } else { 2247 assert(0 && "Unknown op"); 2248 } 2249 Result = LegalizeOp(Result); 2250 break; 2251 } 2252 break; 2253 } 2254 } 2255 2256 // Note that LegalizeOp may be reentered even from single-use nodes, which 2257 // means that we always must cache transformed nodes. 2258 AddLegalizedOperand(Op, Result); 2259 return Result; 2260} 2261 2262/// PromoteOp - Given an operation that produces a value in an invalid type, 2263/// promote it to compute the value into a larger type. The produced value will 2264/// have the correct bits for the low portion of the register, but no guarantee 2265/// is made about the top bits: it may be zero, sign-extended, or garbage. 2266SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2267 MVT::ValueType VT = Op.getValueType(); 2268 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2269 assert(getTypeAction(VT) == Promote && 2270 "Caller should expand or legalize operands that are not promotable!"); 2271 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2272 "Cannot promote to smaller type!"); 2273 2274 SDOperand Tmp1, Tmp2, Tmp3; 2275 2276 SDOperand Result; 2277 SDNode *Node = Op.Val; 2278 2279 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2280 if (I != PromotedNodes.end()) return I->second; 2281 2282 // Promotion needs an optimization step to clean up after it, and is not 2283 // careful to avoid operations the target does not support. Make sure that 2284 // all generated operations are legalized in the next iteration. 2285 NeedsAnotherIteration = true; 2286 2287 switch (Node->getOpcode()) { 2288 case ISD::CopyFromReg: 2289 assert(0 && "CopyFromReg must be legal!"); 2290 default: 2291 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2292 assert(0 && "Do not know how to promote this operator!"); 2293 abort(); 2294 case ISD::UNDEF: 2295 Result = DAG.getNode(ISD::UNDEF, NVT); 2296 break; 2297 case ISD::Constant: 2298 if (VT != MVT::i1) 2299 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2300 else 2301 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2302 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2303 break; 2304 case ISD::ConstantFP: 2305 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2306 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2307 break; 2308 2309 case ISD::SETCC: 2310 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2311 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2312 Node->getOperand(1), Node->getOperand(2)); 2313 Result = LegalizeOp(Result); 2314 break; 2315 2316 case ISD::TRUNCATE: 2317 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2318 case Legal: 2319 Result = LegalizeOp(Node->getOperand(0)); 2320 assert(Result.getValueType() >= NVT && 2321 "This truncation doesn't make sense!"); 2322 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2323 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2324 break; 2325 case Promote: 2326 // The truncation is not required, because we don't guarantee anything 2327 // about high bits anyway. 2328 Result = PromoteOp(Node->getOperand(0)); 2329 break; 2330 case Expand: 2331 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2332 // Truncate the low part of the expanded value to the result type 2333 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2334 } 2335 break; 2336 case ISD::SIGN_EXTEND: 2337 case ISD::ZERO_EXTEND: 2338 case ISD::ANY_EXTEND: 2339 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2340 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2341 case Legal: 2342 // Input is legal? Just do extend all the way to the larger type. 2343 Result = LegalizeOp(Node->getOperand(0)); 2344 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2345 break; 2346 case Promote: 2347 // Promote the reg if it's smaller. 2348 Result = PromoteOp(Node->getOperand(0)); 2349 // The high bits are not guaranteed to be anything. Insert an extend. 2350 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2351 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2352 DAG.getValueType(Node->getOperand(0).getValueType())); 2353 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2354 Result = DAG.getZeroExtendInReg(Result, 2355 Node->getOperand(0).getValueType()); 2356 break; 2357 } 2358 break; 2359 2360 case ISD::FP_EXTEND: 2361 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2362 case ISD::FP_ROUND: 2363 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2364 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2365 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2366 case Legal: 2367 // Input is legal? Do an FP_ROUND_INREG. 2368 Result = LegalizeOp(Node->getOperand(0)); 2369 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2370 DAG.getValueType(VT)); 2371 break; 2372 } 2373 break; 2374 2375 case ISD::SINT_TO_FP: 2376 case ISD::UINT_TO_FP: 2377 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2378 case Legal: 2379 Result = LegalizeOp(Node->getOperand(0)); 2380 // No extra round required here. 2381 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2382 break; 2383 2384 case Promote: 2385 Result = PromoteOp(Node->getOperand(0)); 2386 if (Node->getOpcode() == ISD::SINT_TO_FP) 2387 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2388 Result, 2389 DAG.getValueType(Node->getOperand(0).getValueType())); 2390 else 2391 Result = DAG.getZeroExtendInReg(Result, 2392 Node->getOperand(0).getValueType()); 2393 // No extra round required here. 2394 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2395 break; 2396 case Expand: 2397 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2398 Node->getOperand(0)); 2399 // Round if we cannot tolerate excess precision. 2400 if (NoExcessFPPrecision) 2401 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2402 DAG.getValueType(VT)); 2403 break; 2404 } 2405 break; 2406 2407 case ISD::FP_TO_SINT: 2408 case ISD::FP_TO_UINT: 2409 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2410 case Legal: 2411 Tmp1 = LegalizeOp(Node->getOperand(0)); 2412 break; 2413 case Promote: 2414 // The input result is prerounded, so we don't have to do anything 2415 // special. 2416 Tmp1 = PromoteOp(Node->getOperand(0)); 2417 break; 2418 case Expand: 2419 assert(0 && "not implemented"); 2420 } 2421 // If we're promoting a UINT to a larger size, check to see if the new node 2422 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2423 // we can use that instead. This allows us to generate better code for 2424 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2425 // legal, such as PowerPC. 2426 if (Node->getOpcode() == ISD::FP_TO_UINT && 2427 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2428 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2429 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2430 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2431 } else { 2432 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2433 } 2434 break; 2435 2436 case ISD::FABS: 2437 case ISD::FNEG: 2438 Tmp1 = PromoteOp(Node->getOperand(0)); 2439 assert(Tmp1.getValueType() == NVT); 2440 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2441 // NOTE: we do not have to do any extra rounding here for 2442 // NoExcessFPPrecision, because we know the input will have the appropriate 2443 // precision, and these operations don't modify precision at all. 2444 break; 2445 2446 case ISD::FSQRT: 2447 case ISD::FSIN: 2448 case ISD::FCOS: 2449 Tmp1 = PromoteOp(Node->getOperand(0)); 2450 assert(Tmp1.getValueType() == NVT); 2451 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2452 if(NoExcessFPPrecision) 2453 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2454 DAG.getValueType(VT)); 2455 break; 2456 2457 case ISD::AND: 2458 case ISD::OR: 2459 case ISD::XOR: 2460 case ISD::ADD: 2461 case ISD::SUB: 2462 case ISD::MUL: 2463 // The input may have strange things in the top bits of the registers, but 2464 // these operations don't care. They may have weird bits going out, but 2465 // that too is okay if they are integer operations. 2466 Tmp1 = PromoteOp(Node->getOperand(0)); 2467 Tmp2 = PromoteOp(Node->getOperand(1)); 2468 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2469 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2470 break; 2471 case ISD::FADD: 2472 case ISD::FSUB: 2473 case ISD::FMUL: 2474 // The input may have strange things in the top bits of the registers, but 2475 // these operations don't care. 2476 Tmp1 = PromoteOp(Node->getOperand(0)); 2477 Tmp2 = PromoteOp(Node->getOperand(1)); 2478 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2479 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2480 2481 // Floating point operations will give excess precision that we may not be 2482 // able to tolerate. If we DO allow excess precision, just leave it, 2483 // otherwise excise it. 2484 // FIXME: Why would we need to round FP ops more than integer ones? 2485 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2486 if (NoExcessFPPrecision) 2487 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2488 DAG.getValueType(VT)); 2489 break; 2490 2491 case ISD::SDIV: 2492 case ISD::SREM: 2493 // These operators require that their input be sign extended. 2494 Tmp1 = PromoteOp(Node->getOperand(0)); 2495 Tmp2 = PromoteOp(Node->getOperand(1)); 2496 if (MVT::isInteger(NVT)) { 2497 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2498 DAG.getValueType(VT)); 2499 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2500 DAG.getValueType(VT)); 2501 } 2502 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2503 2504 // Perform FP_ROUND: this is probably overly pessimistic. 2505 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2506 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2507 DAG.getValueType(VT)); 2508 break; 2509 case ISD::FDIV: 2510 case ISD::FREM: 2511 // These operators require that their input be fp extended. 2512 Tmp1 = PromoteOp(Node->getOperand(0)); 2513 Tmp2 = PromoteOp(Node->getOperand(1)); 2514 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2515 2516 // Perform FP_ROUND: this is probably overly pessimistic. 2517 if (NoExcessFPPrecision) 2518 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2519 DAG.getValueType(VT)); 2520 break; 2521 2522 case ISD::UDIV: 2523 case ISD::UREM: 2524 // These operators require that their input be zero extended. 2525 Tmp1 = PromoteOp(Node->getOperand(0)); 2526 Tmp2 = PromoteOp(Node->getOperand(1)); 2527 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2528 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2529 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2530 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2531 break; 2532 2533 case ISD::SHL: 2534 Tmp1 = PromoteOp(Node->getOperand(0)); 2535 Tmp2 = LegalizeOp(Node->getOperand(1)); 2536 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 2537 break; 2538 case ISD::SRA: 2539 // The input value must be properly sign extended. 2540 Tmp1 = PromoteOp(Node->getOperand(0)); 2541 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2542 DAG.getValueType(VT)); 2543 Tmp2 = LegalizeOp(Node->getOperand(1)); 2544 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 2545 break; 2546 case ISD::SRL: 2547 // The input value must be properly zero extended. 2548 Tmp1 = PromoteOp(Node->getOperand(0)); 2549 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2550 Tmp2 = LegalizeOp(Node->getOperand(1)); 2551 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 2552 break; 2553 case ISD::LOAD: 2554 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2555 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2556 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2, 2557 Node->getOperand(2), VT); 2558 // Remember that we legalized the chain. 2559 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2560 break; 2561 case ISD::SEXTLOAD: 2562 case ISD::ZEXTLOAD: 2563 case ISD::EXTLOAD: 2564 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2565 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2566 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2, 2567 Node->getOperand(2), 2568 cast<VTSDNode>(Node->getOperand(3))->getVT()); 2569 // Remember that we legalized the chain. 2570 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2571 break; 2572 case ISD::SELECT: 2573 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2574 case Expand: assert(0 && "It's impossible to expand bools"); 2575 case Legal: 2576 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 2577 break; 2578 case Promote: 2579 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2580 break; 2581 } 2582 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 2583 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 2584 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 2585 break; 2586 case ISD::SELECT_CC: 2587 Tmp2 = PromoteOp(Node->getOperand(2)); // True 2588 Tmp3 = PromoteOp(Node->getOperand(3)); // False 2589 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 2590 Node->getOperand(1), Tmp2, Tmp3, 2591 Node->getOperand(4)); 2592 break; 2593 case ISD::TAILCALL: 2594 case ISD::CALL: { 2595 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2596 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 2597 2598 std::vector<SDOperand> Ops; 2599 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 2600 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2601 2602 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 2603 "Can only promote single result calls"); 2604 std::vector<MVT::ValueType> RetTyVTs; 2605 RetTyVTs.reserve(2); 2606 RetTyVTs.push_back(NVT); 2607 RetTyVTs.push_back(MVT::Other); 2608 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 2609 Node->getOpcode() == ISD::TAILCALL); 2610 Result = SDOperand(NC, 0); 2611 2612 // Insert the new chain mapping. 2613 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2614 break; 2615 } 2616 case ISD::CTPOP: 2617 case ISD::CTTZ: 2618 case ISD::CTLZ: 2619 Tmp1 = Node->getOperand(0); 2620 //Zero extend the argument 2621 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2622 // Perform the larger operation, then subtract if needed. 2623 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2624 switch(Node->getOpcode()) 2625 { 2626 case ISD::CTPOP: 2627 Result = Tmp1; 2628 break; 2629 case ISD::CTTZ: 2630 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2631 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2632 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 2633 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2634 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 2635 break; 2636 case ISD::CTLZ: 2637 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2638 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2639 DAG.getConstant(getSizeInBits(NVT) - 2640 getSizeInBits(VT), NVT)); 2641 break; 2642 } 2643 break; 2644 } 2645 2646 assert(Result.Val && "Didn't set a result!"); 2647 AddPromotedOperand(Op, Result); 2648 return Result; 2649} 2650 2651/// ExpandAddSub - Find a clever way to expand this add operation into 2652/// subcomponents. 2653void SelectionDAGLegalize:: 2654ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 2655 SDOperand &Lo, SDOperand &Hi) { 2656 // Expand the subcomponents. 2657 SDOperand LHSL, LHSH, RHSL, RHSH; 2658 ExpandOp(LHS, LHSL, LHSH); 2659 ExpandOp(RHS, RHSL, RHSH); 2660 2661 std::vector<SDOperand> Ops; 2662 Ops.push_back(LHSL); 2663 Ops.push_back(LHSH); 2664 Ops.push_back(RHSL); 2665 Ops.push_back(RHSH); 2666 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2667 Lo = DAG.getNode(NodeOp, VTs, Ops); 2668 Hi = Lo.getValue(1); 2669} 2670 2671void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 2672 SDOperand Op, SDOperand Amt, 2673 SDOperand &Lo, SDOperand &Hi) { 2674 // Expand the subcomponents. 2675 SDOperand LHSL, LHSH; 2676 ExpandOp(Op, LHSL, LHSH); 2677 2678 std::vector<SDOperand> Ops; 2679 Ops.push_back(LHSL); 2680 Ops.push_back(LHSH); 2681 Ops.push_back(Amt); 2682 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2683 Lo = DAG.getNode(NodeOp, VTs, Ops); 2684 Hi = Lo.getValue(1); 2685} 2686 2687 2688/// ExpandShift - Try to find a clever way to expand this shift operation out to 2689/// smaller elements. If we can't find a way that is more efficient than a 2690/// libcall on this target, return false. Otherwise, return true with the 2691/// low-parts expanded into Lo and Hi. 2692bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 2693 SDOperand &Lo, SDOperand &Hi) { 2694 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 2695 "This is not a shift!"); 2696 2697 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 2698 SDOperand ShAmt = LegalizeOp(Amt); 2699 MVT::ValueType ShTy = ShAmt.getValueType(); 2700 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 2701 unsigned NVTBits = MVT::getSizeInBits(NVT); 2702 2703 // Handle the case when Amt is an immediate. Other cases are currently broken 2704 // and are disabled. 2705 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 2706 unsigned Cst = CN->getValue(); 2707 // Expand the incoming operand to be shifted, so that we have its parts 2708 SDOperand InL, InH; 2709 ExpandOp(Op, InL, InH); 2710 switch(Opc) { 2711 case ISD::SHL: 2712 if (Cst > VTBits) { 2713 Lo = DAG.getConstant(0, NVT); 2714 Hi = DAG.getConstant(0, NVT); 2715 } else if (Cst > NVTBits) { 2716 Lo = DAG.getConstant(0, NVT); 2717 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 2718 } else if (Cst == NVTBits) { 2719 Lo = DAG.getConstant(0, NVT); 2720 Hi = InL; 2721 } else { 2722 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 2723 Hi = DAG.getNode(ISD::OR, NVT, 2724 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 2725 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 2726 } 2727 return true; 2728 case ISD::SRL: 2729 if (Cst > VTBits) { 2730 Lo = DAG.getConstant(0, NVT); 2731 Hi = DAG.getConstant(0, NVT); 2732 } else if (Cst > NVTBits) { 2733 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 2734 Hi = DAG.getConstant(0, NVT); 2735 } else if (Cst == NVTBits) { 2736 Lo = InH; 2737 Hi = DAG.getConstant(0, NVT); 2738 } else { 2739 Lo = DAG.getNode(ISD::OR, NVT, 2740 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2741 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2742 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 2743 } 2744 return true; 2745 case ISD::SRA: 2746 if (Cst > VTBits) { 2747 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 2748 DAG.getConstant(NVTBits-1, ShTy)); 2749 } else if (Cst > NVTBits) { 2750 Lo = DAG.getNode(ISD::SRA, NVT, InH, 2751 DAG.getConstant(Cst-NVTBits, ShTy)); 2752 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2753 DAG.getConstant(NVTBits-1, ShTy)); 2754 } else if (Cst == NVTBits) { 2755 Lo = InH; 2756 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2757 DAG.getConstant(NVTBits-1, ShTy)); 2758 } else { 2759 Lo = DAG.getNode(ISD::OR, NVT, 2760 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2761 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2762 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 2763 } 2764 return true; 2765 } 2766 } 2767 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 2768 // so disable it for now. Currently targets are handling this via SHL_PARTS 2769 // and friends. 2770 return false; 2771 2772 // If we have an efficient select operation (or if the selects will all fold 2773 // away), lower to some complex code, otherwise just emit the libcall. 2774 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt)) 2775 return false; 2776 2777 SDOperand InL, InH; 2778 ExpandOp(Op, InL, InH); 2779 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 2780 DAG.getConstant(NVTBits, ShTy), ShAmt); 2781 2782 // Compare the unmasked shift amount against 32. 2783 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt, 2784 DAG.getConstant(NVTBits, ShTy), ISD::SETGE); 2785 2786 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 2787 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 2788 DAG.getConstant(NVTBits-1, ShTy)); 2789 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 2790 DAG.getConstant(NVTBits-1, ShTy)); 2791 } 2792 2793 if (Opc == ISD::SHL) { 2794 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 2795 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 2796 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 2797 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 2798 2799 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2800 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 2801 } else { 2802 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 2803 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt, 2804 DAG.getConstant(32, ShTy), 2805 ISD::SETEQ), 2806 DAG.getConstant(0, NVT), 2807 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 2808 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 2809 HiLoPart, 2810 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 2811 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 2812 2813 SDOperand HiPart; 2814 if (Opc == ISD::SRA) 2815 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 2816 DAG.getConstant(NVTBits-1, ShTy)); 2817 else 2818 HiPart = DAG.getConstant(0, NVT); 2819 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2820 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 2821 } 2822 return true; 2823} 2824 2825/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 2826/// NodeDepth) node that is an CallSeqStart operation and occurs later than 2827/// Found. 2828static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) { 2829 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 2830 2831 // If we found an CALLSEQ_START, we already know this node occurs later 2832 // than the Found node. Just remember this node and return. 2833 if (Node->getOpcode() == ISD::CALLSEQ_START) { 2834 Found = Node; 2835 return; 2836 } 2837 2838 // Otherwise, scan the operands of Node to see if any of them is a call. 2839 assert(Node->getNumOperands() != 0 && 2840 "All leaves should have depth equal to the entry node!"); 2841 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 2842 FindLatestCallSeqStart(Node->getOperand(i).Val, Found); 2843 2844 // Tail recurse for the last iteration. 2845 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 2846 Found); 2847} 2848 2849 2850/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 2851/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 2852/// than Found. 2853static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 2854 std::set<SDNode*> &Visited) { 2855 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 2856 !Visited.insert(Node).second) return; 2857 2858 // If we found an CALLSEQ_END, we already know this node occurs earlier 2859 // than the Found node. Just remember this node and return. 2860 if (Node->getOpcode() == ISD::CALLSEQ_END) { 2861 Found = Node; 2862 return; 2863 } 2864 2865 // Otherwise, scan the operands of Node to see if any of them is a call. 2866 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 2867 if (UI == E) return; 2868 for (--E; UI != E; ++UI) 2869 FindEarliestCallSeqEnd(*UI, Found, Visited); 2870 2871 // Tail recurse for the last iteration. 2872 FindEarliestCallSeqEnd(*UI, Found, Visited); 2873} 2874 2875/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 2876/// find the CALLSEQ_END node that terminates the call sequence. 2877static SDNode *FindCallSeqEnd(SDNode *Node) { 2878 if (Node->getOpcode() == ISD::CALLSEQ_END) 2879 return Node; 2880 if (Node->use_empty()) 2881 return 0; // No CallSeqEnd 2882 2883 SDOperand TheChain(Node, Node->getNumValues()-1); 2884 if (TheChain.getValueType() != MVT::Other) 2885 TheChain = SDOperand(Node, 0); 2886 if (TheChain.getValueType() != MVT::Other) 2887 return 0; 2888 2889 for (SDNode::use_iterator UI = Node->use_begin(), 2890 E = Node->use_end(); UI != E; ++UI) { 2891 2892 // Make sure to only follow users of our token chain. 2893 SDNode *User = *UI; 2894 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 2895 if (User->getOperand(i) == TheChain) 2896 if (SDNode *Result = FindCallSeqEnd(User)) 2897 return Result; 2898 } 2899 return 0; 2900} 2901 2902/// FindCallSeqStart - Given a chained node that is part of a call sequence, 2903/// find the CALLSEQ_START node that initiates the call sequence. 2904static SDNode *FindCallSeqStart(SDNode *Node) { 2905 assert(Node && "Didn't find callseq_start for a call??"); 2906 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 2907 2908 assert(Node->getOperand(0).getValueType() == MVT::Other && 2909 "Node doesn't have a token chain argument!"); 2910 return FindCallSeqStart(Node->getOperand(0).Val); 2911} 2912 2913 2914/// FindInputOutputChains - If we are replacing an operation with a call we need 2915/// to find the call that occurs before and the call that occurs after it to 2916/// properly serialize the calls in the block. The returned operand is the 2917/// input chain value for the new call (e.g. the entry node or the previous 2918/// call), and OutChain is set to be the chain node to update to point to the 2919/// end of the call chain. 2920static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 2921 SDOperand Entry) { 2922 SDNode *LatestCallSeqStart = Entry.Val; 2923 SDNode *LatestCallSeqEnd = 0; 2924 FindLatestCallSeqStart(OpNode, LatestCallSeqStart); 2925 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 2926 2927 // It is possible that no ISD::CALLSEQ_START was found because there is no 2928 // previous call in the function. LatestCallStackDown may in that case be 2929 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 2930 // unless LatestCallStackDown is an CALLSEQ_START. 2931 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 2932 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 2933 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 2934 } else { 2935 LatestCallSeqEnd = Entry.Val; 2936 } 2937 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 2938 2939 // Finally, find the first call that this must come before, first we find the 2940 // CallSeqEnd that ends the call. 2941 OutChain = 0; 2942 std::set<SDNode*> Visited; 2943 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 2944 2945 // If we found one, translate from the adj up to the callseq_start. 2946 if (OutChain) 2947 OutChain = FindCallSeqStart(OutChain); 2948 2949 return SDOperand(LatestCallSeqEnd, 0); 2950} 2951 2952/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 2953void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 2954 SDNode *OutChain) { 2955 // Nothing to splice it into? 2956 if (OutChain == 0) return; 2957 2958 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 2959 //OutChain->dump(); 2960 2961 // Form a token factor node merging the old inval and the new inval. 2962 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 2963 OutChain->getOperand(0)); 2964 // Change the node to refer to the new token. 2965 OutChain->setAdjCallChain(InToken); 2966} 2967 2968 2969// ExpandLibCall - Expand a node into a call to a libcall. If the result value 2970// does not fit into a register, return the lo part and set the hi part to the 2971// by-reg argument. If it does fit into a single register, return the result 2972// and leave the Hi part unset. 2973SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 2974 SDOperand &Hi) { 2975 SDNode *OutChain; 2976 SDOperand InChain = FindInputOutputChains(Node, OutChain, 2977 DAG.getEntryNode()); 2978 if (InChain.Val == 0) 2979 InChain = DAG.getEntryNode(); 2980 2981 TargetLowering::ArgListTy Args; 2982 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2983 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 2984 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 2985 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 2986 } 2987 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 2988 2989 // Splice the libcall in wherever FindInputOutputChains tells us to. 2990 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 2991 std::pair<SDOperand,SDOperand> CallInfo = 2992 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 2993 Callee, Args, DAG); 2994 2995 SDOperand Result; 2996 switch (getTypeAction(CallInfo.first.getValueType())) { 2997 default: assert(0 && "Unknown thing"); 2998 case Legal: 2999 Result = CallInfo.first; 3000 break; 3001 case Promote: 3002 assert(0 && "Cannot promote this yet!"); 3003 case Expand: 3004 ExpandOp(CallInfo.first, Result, Hi); 3005 CallInfo.second = LegalizeOp(CallInfo.second); 3006 break; 3007 } 3008 3009 SpliceCallInto(CallInfo.second, OutChain); 3010 NeedsAnotherIteration = true; 3011 return Result; 3012} 3013 3014 3015/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 3016/// destination type is legal. 3017SDOperand SelectionDAGLegalize:: 3018ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 3019 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 3020 assert(getTypeAction(Source.getValueType()) == Expand && 3021 "This is not an expansion!"); 3022 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 3023 3024 if (!isSigned) { 3025 assert(Source.getValueType() == MVT::i64 && 3026 "This only works for 64-bit -> FP"); 3027 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 3028 // incoming integer is set. To handle this, we dynamically test to see if 3029 // it is set, and, if so, add a fudge factor. 3030 SDOperand Lo, Hi; 3031 ExpandOp(Source, Lo, Hi); 3032 3033 // If this is unsigned, and not supported, first perform the conversion to 3034 // signed, then adjust the result if the sign bit is set. 3035 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 3036 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 3037 3038 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 3039 DAG.getConstant(0, Hi.getValueType()), 3040 ISD::SETLT); 3041 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3042 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3043 SignSet, Four, Zero); 3044 uint64_t FF = 0x5f800000ULL; 3045 if (TLI.isLittleEndian()) FF <<= 32; 3046 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3047 3048 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3049 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3050 SDOperand FudgeInReg; 3051 if (DestTy == MVT::f32) 3052 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3053 DAG.getSrcValue(NULL)); 3054 else { 3055 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3056 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3057 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 3058 } 3059 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3060 } 3061 3062 // Check to see if the target has a custom way to lower this. If so, use it. 3063 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3064 default: assert(0 && "This action not implemented for this operation!"); 3065 case TargetLowering::Legal: 3066 case TargetLowering::Expand: 3067 break; // This case is handled below. 3068 case TargetLowering::Custom: { 3069 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3070 Source), DAG); 3071 if (NV.Val) 3072 return LegalizeOp(NV); 3073 break; // The target decided this was legal after all 3074 } 3075 } 3076 3077 // Expand the source, then glue it back together for the call. We must expand 3078 // the source in case it is shared (this pass of legalize must traverse it). 3079 SDOperand SrcLo, SrcHi; 3080 ExpandOp(Source, SrcLo, SrcHi); 3081 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3082 3083 SDNode *OutChain = 0; 3084 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 3085 DAG.getEntryNode()); 3086 const char *FnName = 0; 3087 if (DestTy == MVT::f32) 3088 FnName = "__floatdisf"; 3089 else { 3090 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3091 FnName = "__floatdidf"; 3092 } 3093 3094 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 3095 3096 TargetLowering::ArgListTy Args; 3097 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 3098 3099 Args.push_back(std::make_pair(Source, ArgTy)); 3100 3101 // We don't care about token chains for libcalls. We just use the entry 3102 // node as our input and ignore the output chain. This allows us to place 3103 // calls wherever we need them to satisfy data dependences. 3104 const Type *RetTy = MVT::getTypeForValueType(DestTy); 3105 3106 std::pair<SDOperand,SDOperand> CallResult = 3107 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 3108 Callee, Args, DAG); 3109 3110 SpliceCallInto(CallResult.second, OutChain); 3111 return CallResult.first; 3112} 3113 3114 3115 3116/// ExpandOp - Expand the specified SDOperand into its two component pieces 3117/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 3118/// LegalizeNodes map is filled in for any results that are not expanded, the 3119/// ExpandedNodes map is filled in for any results that are expanded, and the 3120/// Lo/Hi values are returned. 3121void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 3122 MVT::ValueType VT = Op.getValueType(); 3123 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3124 SDNode *Node = Op.Val; 3125 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 3126 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 3127 "Cannot expand FP values!"); 3128 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 3129 "Cannot expand to FP value or to larger int value!"); 3130 3131 // See if we already expanded it. 3132 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 3133 = ExpandedNodes.find(Op); 3134 if (I != ExpandedNodes.end()) { 3135 Lo = I->second.first; 3136 Hi = I->second.second; 3137 return; 3138 } 3139 3140 // Expanding to multiple registers needs to perform an optimization step, and 3141 // is not careful to avoid operations the target does not support. Make sure 3142 // that all generated operations are legalized in the next iteration. 3143 NeedsAnotherIteration = true; 3144 3145 switch (Node->getOpcode()) { 3146 case ISD::CopyFromReg: 3147 assert(0 && "CopyFromReg must be legal!"); 3148 default: 3149 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 3150 assert(0 && "Do not know how to expand this operator!"); 3151 abort(); 3152 case ISD::UNDEF: 3153 Lo = DAG.getNode(ISD::UNDEF, NVT); 3154 Hi = DAG.getNode(ISD::UNDEF, NVT); 3155 break; 3156 case ISD::Constant: { 3157 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 3158 Lo = DAG.getConstant(Cst, NVT); 3159 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3160 break; 3161 } 3162 case ISD::ConstantVec: { 3163 unsigned NumElements = Node->getNumOperands(); 3164 // If we only have two elements left in the constant vector, just break it 3165 // apart into the two scalar constants it contains. Otherwise, bisect the 3166 // ConstantVec, and return each half as a new ConstantVec. 3167 // FIXME: this is hard coded as big endian, it may have to change to support 3168 // SSE and Alpha MVI 3169 if (NumElements == 2) { 3170 Hi = Node->getOperand(0); 3171 Lo = Node->getOperand(1); 3172 } else { 3173 NumElements /= 2; 3174 std::vector<SDOperand> LoOps, HiOps; 3175 for (unsigned I = 0, E = NumElements; I < E; ++I) { 3176 HiOps.push_back(Node->getOperand(I)); 3177 LoOps.push_back(Node->getOperand(I+NumElements)); 3178 } 3179 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps); 3180 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps); 3181 } 3182 break; 3183 } 3184 3185 case ISD::BUILD_PAIR: 3186 // Legalize both operands. FIXME: in the future we should handle the case 3187 // where the two elements are not legal. 3188 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 3189 Lo = LegalizeOp(Node->getOperand(0)); 3190 Hi = LegalizeOp(Node->getOperand(1)); 3191 break; 3192 3193 case ISD::CTPOP: 3194 ExpandOp(Node->getOperand(0), Lo, Hi); 3195 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3196 DAG.getNode(ISD::CTPOP, NVT, Lo), 3197 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3198 Hi = DAG.getConstant(0, NVT); 3199 break; 3200 3201 case ISD::CTLZ: { 3202 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3203 ExpandOp(Node->getOperand(0), Lo, Hi); 3204 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3205 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3206 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3207 ISD::SETNE); 3208 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3209 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3210 3211 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3212 Hi = DAG.getConstant(0, NVT); 3213 break; 3214 } 3215 3216 case ISD::CTTZ: { 3217 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3218 ExpandOp(Node->getOperand(0), Lo, Hi); 3219 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3220 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3221 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3222 ISD::SETNE); 3223 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3224 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3225 3226 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3227 Hi = DAG.getConstant(0, NVT); 3228 break; 3229 } 3230 3231 case ISD::LOAD: { 3232 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3233 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3234 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3235 3236 // Increment the pointer to the other half. 3237 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3238 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3239 getIntPtrConstant(IncrementSize)); 3240 //Is this safe? declaring that the two parts of the split load 3241 //are from the same instruction? 3242 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3243 3244 // Build a factor node to remember that this load is independent of the 3245 // other one. 3246 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3247 Hi.getValue(1)); 3248 3249 // Remember that we legalized the chain. 3250 AddLegalizedOperand(Op.getValue(1), TF); 3251 if (!TLI.isLittleEndian()) 3252 std::swap(Lo, Hi); 3253 break; 3254 } 3255 case ISD::VLOAD: { 3256 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3257 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3258 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3259 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3260 3261 // If we only have two elements, turn into a pair of scalar loads. 3262 // FIXME: handle case where a vector of two elements is fine, such as 3263 // 2 x double on SSE2. 3264 if (NumElements == 2) { 3265 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3266 // Increment the pointer to the other half. 3267 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8; 3268 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3269 getIntPtrConstant(IncrementSize)); 3270 //Is this safe? declaring that the two parts of the split load 3271 //are from the same instruction? 3272 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3273 } else { 3274 NumElements /= 2; // Split the vector in half 3275 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3276 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8; 3277 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3278 getIntPtrConstant(IncrementSize)); 3279 //Is this safe? declaring that the two parts of the split load 3280 //are from the same instruction? 3281 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3282 } 3283 3284 // Build a factor node to remember that this load is independent of the 3285 // other one. 3286 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3287 Hi.getValue(1)); 3288 3289 // Remember that we legalized the chain. 3290 AddLegalizedOperand(Op.getValue(1), TF); 3291 if (!TLI.isLittleEndian()) 3292 std::swap(Lo, Hi); 3293 break; 3294 } 3295 case ISD::VADD: 3296 case ISD::VSUB: 3297 case ISD::VMUL: { 3298 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3299 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3300 SDOperand LL, LH, RL, RH; 3301 3302 ExpandOp(Node->getOperand(0), LL, LH); 3303 ExpandOp(Node->getOperand(1), RL, RH); 3304 3305 // If we only have two elements, turn into a pair of scalar loads. 3306 // FIXME: handle case where a vector of two elements is fine, such as 3307 // 2 x double on SSE2. 3308 if (NumElements == 2) { 3309 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT); 3310 Lo = DAG.getNode(Opc, EVT, LL, RL); 3311 Hi = DAG.getNode(Opc, EVT, LH, RH); 3312 } else { 3313 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2), 3314 LL.getOperand(3)); 3315 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2), 3316 LH.getOperand(3)); 3317 } 3318 break; 3319 } 3320 case ISD::TAILCALL: 3321 case ISD::CALL: { 3322 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3323 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 3324 3325 bool Changed = false; 3326 std::vector<SDOperand> Ops; 3327 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 3328 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3329 Changed |= Ops.back() != Node->getOperand(i); 3330 } 3331 3332 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 3333 "Can only expand a call once so far, not i64 -> i16!"); 3334 3335 std::vector<MVT::ValueType> RetTyVTs; 3336 RetTyVTs.reserve(3); 3337 RetTyVTs.push_back(NVT); 3338 RetTyVTs.push_back(NVT); 3339 RetTyVTs.push_back(MVT::Other); 3340 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops, 3341 Node->getOpcode() == ISD::TAILCALL); 3342 Lo = SDOperand(NC, 0); 3343 Hi = SDOperand(NC, 1); 3344 3345 // Insert the new chain mapping. 3346 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 3347 break; 3348 } 3349 case ISD::AND: 3350 case ISD::OR: 3351 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 3352 SDOperand LL, LH, RL, RH; 3353 ExpandOp(Node->getOperand(0), LL, LH); 3354 ExpandOp(Node->getOperand(1), RL, RH); 3355 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 3356 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 3357 break; 3358 } 3359 case ISD::SELECT: { 3360 SDOperand C, LL, LH, RL, RH; 3361 3362 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3363 case Expand: assert(0 && "It's impossible to expand bools"); 3364 case Legal: 3365 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 3366 break; 3367 case Promote: 3368 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 3369 break; 3370 } 3371 ExpandOp(Node->getOperand(1), LL, LH); 3372 ExpandOp(Node->getOperand(2), RL, RH); 3373 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 3374 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 3375 break; 3376 } 3377 case ISD::SELECT_CC: { 3378 SDOperand TL, TH, FL, FH; 3379 ExpandOp(Node->getOperand(2), TL, TH); 3380 ExpandOp(Node->getOperand(3), FL, FH); 3381 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3382 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3383 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3384 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3385 Lo = LegalizeOp(Lo); 3386 Hi = LegalizeOp(Hi); 3387 break; 3388 } 3389 case ISD::SEXTLOAD: { 3390 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3391 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3392 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3393 3394 if (EVT == NVT) 3395 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3396 else 3397 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3398 EVT); 3399 3400 // Remember that we legalized the chain. 3401 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3402 3403 // The high part is obtained by SRA'ing all but one of the bits of the lo 3404 // part. 3405 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3406 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3407 TLI.getShiftAmountTy())); 3408 Lo = LegalizeOp(Lo); 3409 Hi = LegalizeOp(Hi); 3410 break; 3411 } 3412 case ISD::ZEXTLOAD: { 3413 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3414 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3415 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3416 3417 if (EVT == NVT) 3418 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3419 else 3420 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3421 EVT); 3422 3423 // Remember that we legalized the chain. 3424 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3425 3426 // The high part is just a zero. 3427 Hi = LegalizeOp(DAG.getConstant(0, NVT)); 3428 Lo = LegalizeOp(Lo); 3429 break; 3430 } 3431 case ISD::EXTLOAD: { 3432 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3433 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3434 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3435 3436 if (EVT == NVT) 3437 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3438 else 3439 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3440 EVT); 3441 3442 // Remember that we legalized the chain. 3443 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3444 3445 // The high part is undefined. 3446 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT)); 3447 Lo = LegalizeOp(Lo); 3448 break; 3449 } 3450 case ISD::ANY_EXTEND: { 3451 SDOperand In; 3452 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3453 case Expand: assert(0 && "expand-expand not implemented yet!"); 3454 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3455 case Promote: 3456 In = PromoteOp(Node->getOperand(0)); 3457 break; 3458 } 3459 3460 // The low part is any extension of the input (which degenerates to a copy). 3461 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In); 3462 // The high part is undefined. 3463 Hi = DAG.getNode(ISD::UNDEF, NVT); 3464 break; 3465 } 3466 case ISD::SIGN_EXTEND: { 3467 SDOperand In; 3468 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3469 case Expand: assert(0 && "expand-expand not implemented yet!"); 3470 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3471 case Promote: 3472 In = PromoteOp(Node->getOperand(0)); 3473 // Emit the appropriate sign_extend_inreg to get the value we want. 3474 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 3475 DAG.getValueType(Node->getOperand(0).getValueType())); 3476 break; 3477 } 3478 3479 // The low part is just a sign extension of the input (which degenerates to 3480 // a copy). 3481 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 3482 3483 // The high part is obtained by SRA'ing all but one of the bits of the lo 3484 // part. 3485 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3486 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3487 TLI.getShiftAmountTy())); 3488 break; 3489 } 3490 case ISD::ZERO_EXTEND: { 3491 SDOperand In; 3492 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3493 case Expand: assert(0 && "expand-expand not implemented yet!"); 3494 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3495 case Promote: 3496 In = PromoteOp(Node->getOperand(0)); 3497 // Emit the appropriate zero_extend_inreg to get the value we want. 3498 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 3499 break; 3500 } 3501 3502 // The low part is just a zero extension of the input (which degenerates to 3503 // a copy). 3504 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 3505 3506 // The high part is just a zero. 3507 Hi = DAG.getConstant(0, NVT); 3508 break; 3509 } 3510 3511 case ISD::READCYCLECOUNTER: { 3512 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 3513 TargetLowering::Custom && 3514 "Must custom expand ReadCycleCounter"); 3515 SDOperand T = TLI.LowerOperation(Op, DAG); 3516 assert(T.Val && "Node must be custom expanded!"); 3517 Lo = LegalizeOp(T.getValue(0)); 3518 Hi = LegalizeOp(T.getValue(1)); 3519 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 3520 LegalizeOp(T.getValue(2))); 3521 break; 3522 } 3523 3524 // These operators cannot be expanded directly, emit them as calls to 3525 // library functions. 3526 case ISD::FP_TO_SINT: 3527 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 3528 SDOperand Op; 3529 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3530 case Expand: assert(0 && "cannot expand FP!"); 3531 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3532 case Promote: Op = PromoteOp(Node->getOperand(0)); break; 3533 } 3534 3535 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 3536 3537 // Now that the custom expander is done, expand the result, which is still 3538 // VT. 3539 if (Op.Val) { 3540 ExpandOp(Op, Lo, Hi); 3541 break; 3542 } 3543 } 3544 3545 if (Node->getOperand(0).getValueType() == MVT::f32) 3546 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 3547 else 3548 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 3549 break; 3550 3551 case ISD::FP_TO_UINT: 3552 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 3553 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, 3554 LegalizeOp(Node->getOperand(0))); 3555 // Now that the custom expander is done, expand the result, which is still 3556 // VT. 3557 Op = TLI.LowerOperation(Op, DAG); 3558 if (Op.Val) { 3559 ExpandOp(Op, Lo, Hi); 3560 break; 3561 } 3562 } 3563 3564 if (Node->getOperand(0).getValueType() == MVT::f32) 3565 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 3566 else 3567 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 3568 break; 3569 3570 case ISD::SHL: 3571 // If the target wants custom lowering, do so. 3572 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 3573 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), 3574 LegalizeOp(Node->getOperand(1))); 3575 Op = TLI.LowerOperation(Op, DAG); 3576 if (Op.Val) { 3577 // Now that the custom expander is done, expand the result, which is 3578 // still VT. 3579 ExpandOp(Op, Lo, Hi); 3580 break; 3581 } 3582 } 3583 3584 // If we can emit an efficient shift operation, do so now. 3585 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3586 break; 3587 3588 // If this target supports SHL_PARTS, use it. 3589 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) { 3590 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 3591 Lo, Hi); 3592 break; 3593 } 3594 3595 // Otherwise, emit a libcall. 3596 Lo = ExpandLibCall("__ashldi3", Node, Hi); 3597 break; 3598 3599 case ISD::SRA: 3600 // If the target wants custom lowering, do so. 3601 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 3602 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), 3603 LegalizeOp(Node->getOperand(1))); 3604 Op = TLI.LowerOperation(Op, DAG); 3605 if (Op.Val) { 3606 // Now that the custom expander is done, expand the result, which is 3607 // still VT. 3608 ExpandOp(Op, Lo, Hi); 3609 break; 3610 } 3611 } 3612 3613 // If we can emit an efficient shift operation, do so now. 3614 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3615 break; 3616 3617 // If this target supports SRA_PARTS, use it. 3618 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) { 3619 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 3620 Lo, Hi); 3621 break; 3622 } 3623 3624 // Otherwise, emit a libcall. 3625 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 3626 break; 3627 case ISD::SRL: 3628 // If the target wants custom lowering, do so. 3629 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 3630 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), 3631 LegalizeOp(Node->getOperand(1))); 3632 Op = TLI.LowerOperation(Op, DAG); 3633 if (Op.Val) { 3634 // Now that the custom expander is done, expand the result, which is 3635 // still VT. 3636 ExpandOp(Op, Lo, Hi); 3637 break; 3638 } 3639 } 3640 3641 // If we can emit an efficient shift operation, do so now. 3642 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3643 break; 3644 3645 // If this target supports SRL_PARTS, use it. 3646 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) { 3647 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 3648 Lo, Hi); 3649 break; 3650 } 3651 3652 // Otherwise, emit a libcall. 3653 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 3654 break; 3655 3656 case ISD::ADD: 3657 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 3658 Lo, Hi); 3659 break; 3660 case ISD::SUB: 3661 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 3662 Lo, Hi); 3663 break; 3664 case ISD::MUL: { 3665 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 3666 SDOperand LL, LH, RL, RH; 3667 ExpandOp(Node->getOperand(0), LL, LH); 3668 ExpandOp(Node->getOperand(1), RL, RH); 3669 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 3670 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 3671 // extended the sign bit of the low half through the upper half, and if so 3672 // emit a MULHS instead of the alternate sequence that is valid for any 3673 // i64 x i64 multiply. 3674 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 3675 // is RH an extension of the sign bit of RL? 3676 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 3677 RH.getOperand(1).getOpcode() == ISD::Constant && 3678 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 3679 // is LH an extension of the sign bit of LL? 3680 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 3681 LH.getOperand(1).getOpcode() == ISD::Constant && 3682 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 3683 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 3684 } else { 3685 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 3686 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 3687 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 3688 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 3689 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 3690 } 3691 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 3692 } else { 3693 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 3694 } 3695 break; 3696 } 3697 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 3698 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 3699 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 3700 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 3701 } 3702 3703 // Remember in a map if the values will be reused later. 3704 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 3705 std::make_pair(Lo, Hi))).second; 3706 assert(isNew && "Value already expanded?!?"); 3707} 3708 3709 3710// SelectionDAG::Legalize - This is the entry point for the file. 3711// 3712void SelectionDAG::Legalize() { 3713 /// run - This is the main entry point to this class. 3714 /// 3715 SelectionDAGLegalize(*this).Run(); 3716} 3717 3718