LegalizeDAG.cpp revision cde0f5cfe7b7e0a73708c0db29dcfc0d00294e98
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned long long ValueTypeActions; 56 57 /// NeedsAnotherIteration - This is set when we expand a large integer 58 /// operation into smaller integer operations, but the smaller operations are 59 /// not set. This occurs only rarely in practice, for targets that don't have 60 /// 32-bit or larger integer registers. 61 bool NeedsAnotherIteration; 62 63 /// LegalizedNodes - For nodes that are of legal width, and that have more 64 /// than one use, this map indicates what regularized operand to use. This 65 /// allows us to avoid legalizing the same thing more than once. 66 std::map<SDOperand, SDOperand> LegalizedNodes; 67 68 /// PromotedNodes - For nodes that are below legal width, and that have more 69 /// than one use, this map indicates what promoted value to use. This allows 70 /// us to avoid promoting the same thing more than once. 71 std::map<SDOperand, SDOperand> PromotedNodes; 72 73 /// ExpandedNodes - For nodes that need to be expanded, and which have more 74 /// than one use, this map indicates which which operands are the expanded 75 /// version of the input. This allows us to avoid expanding the same node 76 /// more than once. 77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 78 79 void AddLegalizedOperand(SDOperand From, SDOperand To) { 80 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second; 81 assert(isNew && "Got into the map somehow?"); 82 } 83 void AddPromotedOperand(SDOperand From, SDOperand To) { 84 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 85 assert(isNew && "Got into the map somehow?"); 86 } 87 88public: 89 90 SelectionDAGLegalize(SelectionDAG &DAG); 91 92 /// Run - While there is still lowering to do, perform a pass over the DAG. 93 /// Most regularization can be done in a single pass, but targets that require 94 /// large values to be split into registers multiple times (e.g. i64 -> 4x 95 /// i16) require iteration for these values (the first iteration will demote 96 /// to i32, the second will demote to i16). 97 void Run() { 98 do { 99 NeedsAnotherIteration = false; 100 LegalizeDAG(); 101 } while (NeedsAnotherIteration); 102 } 103 104 /// getTypeAction - Return how we should legalize values of this type, either 105 /// it is already legal or we need to expand it into multiple registers of 106 /// smaller integer type, or we need to promote it to a larger type. 107 LegalizeAction getTypeAction(MVT::ValueType VT) const { 108 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 109 } 110 111 /// isTypeLegal - Return true if this type is legal on this target. 112 /// 113 bool isTypeLegal(MVT::ValueType VT) const { 114 return getTypeAction(VT) == Legal; 115 } 116 117private: 118 void LegalizeDAG(); 119 120 SDOperand LegalizeOp(SDOperand O); 121 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 122 SDOperand PromoteOp(SDOperand O); 123 124 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 125 SDOperand &Hi); 126 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 127 SDOperand Source); 128 129 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 130 SDOperand LegalOp, 131 MVT::ValueType DestVT); 132 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 133 bool isSigned); 134 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 135 bool isSigned); 136 137 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 138 SDOperand &Lo, SDOperand &Hi); 139 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 140 SDOperand &Lo, SDOperand &Hi); 141 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 142 SDOperand &Lo, SDOperand &Hi); 143 144 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 145 146 SDOperand getIntPtrConstant(uint64_t Val) { 147 return DAG.getConstant(Val, TLI.getPointerTy()); 148 } 149}; 150} 151 152static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 153 switch (VecOp) { 154 default: assert(0 && "Don't know how to scalarize this opcode!"); 155 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 156 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 157 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 158 } 159} 160 161SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 162 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 163 ValueTypeActions(TLI.getValueTypeActions()) { 164 assert(MVT::LAST_VALUETYPE <= 32 && 165 "Too many value types for ValueTypeActions to hold!"); 166} 167 168/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 169/// INT_TO_FP operation of the specified operand when the target requests that 170/// we expand it. At this point, we know that the result and operand types are 171/// legal for the target. 172SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 173 SDOperand Op0, 174 MVT::ValueType DestVT) { 175 if (Op0.getValueType() == MVT::i32) { 176 // simple 32-bit [signed|unsigned] integer to float/double expansion 177 178 // get the stack frame index of a 8 byte buffer 179 MachineFunction &MF = DAG.getMachineFunction(); 180 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 181 // get address of 8 byte buffer 182 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 183 // word offset constant for Hi/Lo address computation 184 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 185 // set up Hi and Lo (into buffer) address based on endian 186 SDOperand Hi, Lo; 187 if (TLI.isLittleEndian()) { 188 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 189 Lo = StackSlot; 190 } else { 191 Hi = StackSlot; 192 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 193 } 194 // if signed map to unsigned space 195 SDOperand Op0Mapped; 196 if (isSigned) { 197 // constant used to invert sign bit (signed to unsigned mapping) 198 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 199 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 200 } else { 201 Op0Mapped = Op0; 202 } 203 // store the lo of the constructed double - based on integer input 204 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 205 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 206 // initial hi portion of constructed double 207 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 208 // store the hi of the constructed double - biased exponent 209 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 210 InitialHi, Hi, DAG.getSrcValue(NULL)); 211 // load the constructed double 212 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 213 DAG.getSrcValue(NULL)); 214 // FP constant to bias correct the final result 215 SDOperand Bias = DAG.getConstantFP(isSigned ? 216 BitsToDouble(0x4330000080000000ULL) 217 : BitsToDouble(0x4330000000000000ULL), 218 MVT::f64); 219 // subtract the bias 220 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 221 // final result 222 SDOperand Result; 223 // handle final rounding 224 if (DestVT == MVT::f64) { 225 // do nothing 226 Result = Sub; 227 } else { 228 // if f32 then cast to f32 229 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 230 } 231 NeedsAnotherIteration = true; 232 return Result; 233 } 234 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 235 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 236 237 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 238 DAG.getConstant(0, Op0.getValueType()), 239 ISD::SETLT); 240 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 241 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 242 SignSet, Four, Zero); 243 244 // If the sign bit of the integer is set, the large number will be treated 245 // as a negative number. To counteract this, the dynamic code adds an 246 // offset depending on the data type. 247 uint64_t FF; 248 switch (Op0.getValueType()) { 249 default: assert(0 && "Unsupported integer type!"); 250 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 251 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 252 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 253 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 254 } 255 if (TLI.isLittleEndian()) FF <<= 32; 256 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 257 258 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 259 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 260 SDOperand FudgeInReg; 261 if (DestVT == MVT::f32) 262 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 263 DAG.getSrcValue(NULL)); 264 else { 265 assert(DestVT == MVT::f64 && "Unexpected conversion"); 266 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 267 DAG.getEntryNode(), CPIdx, 268 DAG.getSrcValue(NULL), MVT::f32)); 269 } 270 271 NeedsAnotherIteration = true; 272 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 273} 274 275/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 276/// *INT_TO_FP operation of the specified operand when the target requests that 277/// we promote it. At this point, we know that the result and operand types are 278/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 279/// operation that takes a larger input. 280SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 281 MVT::ValueType DestVT, 282 bool isSigned) { 283 // First step, figure out the appropriate *INT_TO_FP operation to use. 284 MVT::ValueType NewInTy = LegalOp.getValueType(); 285 286 unsigned OpToUse = 0; 287 288 // Scan for the appropriate larger type to use. 289 while (1) { 290 NewInTy = (MVT::ValueType)(NewInTy+1); 291 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 292 293 // If the target supports SINT_TO_FP of this type, use it. 294 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 295 default: break; 296 case TargetLowering::Legal: 297 if (!TLI.isTypeLegal(NewInTy)) 298 break; // Can't use this datatype. 299 // FALL THROUGH. 300 case TargetLowering::Custom: 301 OpToUse = ISD::SINT_TO_FP; 302 break; 303 } 304 if (OpToUse) break; 305 if (isSigned) continue; 306 307 // If the target supports UINT_TO_FP of this type, use it. 308 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 309 default: break; 310 case TargetLowering::Legal: 311 if (!TLI.isTypeLegal(NewInTy)) 312 break; // Can't use this datatype. 313 // FALL THROUGH. 314 case TargetLowering::Custom: 315 OpToUse = ISD::UINT_TO_FP; 316 break; 317 } 318 if (OpToUse) break; 319 320 // Otherwise, try a larger type. 321 } 322 323 // Make sure to legalize any nodes we create here in the next pass. 324 NeedsAnotherIteration = true; 325 326 // Okay, we found the operation and type to use. Zero extend our input to the 327 // desired type then run the operation on it. 328 return DAG.getNode(OpToUse, DestVT, 329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 330 NewInTy, LegalOp)); 331} 332 333/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 334/// FP_TO_*INT operation of the specified operand when the target requests that 335/// we promote it. At this point, we know that the result and operand types are 336/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 337/// operation that returns a larger result. 338SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 339 MVT::ValueType DestVT, 340 bool isSigned) { 341 // First step, figure out the appropriate FP_TO*INT operation to use. 342 MVT::ValueType NewOutTy = DestVT; 343 344 unsigned OpToUse = 0; 345 346 // Scan for the appropriate larger type to use. 347 while (1) { 348 NewOutTy = (MVT::ValueType)(NewOutTy+1); 349 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 350 351 // If the target supports FP_TO_SINT returning this type, use it. 352 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 353 default: break; 354 case TargetLowering::Legal: 355 if (!TLI.isTypeLegal(NewOutTy)) 356 break; // Can't use this datatype. 357 // FALL THROUGH. 358 case TargetLowering::Custom: 359 OpToUse = ISD::FP_TO_SINT; 360 break; 361 } 362 if (OpToUse) break; 363 364 // If the target supports FP_TO_UINT of this type, use it. 365 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 366 default: break; 367 case TargetLowering::Legal: 368 if (!TLI.isTypeLegal(NewOutTy)) 369 break; // Can't use this datatype. 370 // FALL THROUGH. 371 case TargetLowering::Custom: 372 OpToUse = ISD::FP_TO_UINT; 373 break; 374 } 375 if (OpToUse) break; 376 377 // Otherwise, try a larger type. 378 } 379 380 // Make sure to legalize any nodes we create here in the next pass. 381 NeedsAnotherIteration = true; 382 383 // Okay, we found the operation and type to use. Truncate the result of the 384 // extended FP_TO_*INT operation to the desired size. 385 return DAG.getNode(ISD::TRUNCATE, DestVT, 386 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 387} 388 389/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 390/// not been visited yet and if all of its operands have already been visited. 391static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 392 std::map<SDNode*, unsigned> &Visited) { 393 if (++Visited[N] != N->getNumOperands()) 394 return; // Haven't visited all operands yet 395 396 Order.push_back(N); 397 398 if (N->hasOneUse()) { // Tail recurse in common case. 399 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 400 return; 401 } 402 403 // Now that we have N in, add anything that uses it if all of their operands 404 // are now done. 405 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 406 ComputeTopDownOrdering(*UI, Order, Visited); 407} 408 409 410void SelectionDAGLegalize::LegalizeDAG() { 411 // The legalize process is inherently a bottom-up recursive process (users 412 // legalize their uses before themselves). Given infinite stack space, we 413 // could just start legalizing on the root and traverse the whole graph. In 414 // practice however, this causes us to run out of stack space on large basic 415 // blocks. To avoid this problem, compute an ordering of the nodes where each 416 // node is only legalized after all of its operands are legalized. 417 std::map<SDNode*, unsigned> Visited; 418 std::vector<SDNode*> Order; 419 420 // Compute ordering from all of the leaves in the graphs, those (like the 421 // entry node) that have no operands. 422 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 423 E = DAG.allnodes_end(); I != E; ++I) { 424 if (I->getNumOperands() == 0) { 425 Visited[I] = 0 - 1U; 426 ComputeTopDownOrdering(I, Order, Visited); 427 } 428 } 429 430 assert(Order.size() == Visited.size() && 431 Order.size() == 432 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 433 "Error: DAG is cyclic!"); 434 Visited.clear(); 435 436 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 437 SDNode *N = Order[i]; 438 switch (getTypeAction(N->getValueType(0))) { 439 default: assert(0 && "Bad type action!"); 440 case Legal: 441 LegalizeOp(SDOperand(N, 0)); 442 break; 443 case Promote: 444 PromoteOp(SDOperand(N, 0)); 445 break; 446 case Expand: { 447 SDOperand X, Y; 448 ExpandOp(SDOperand(N, 0), X, Y); 449 break; 450 } 451 } 452 } 453 454 // Finally, it's possible the root changed. Get the new root. 455 SDOperand OldRoot = DAG.getRoot(); 456 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 457 DAG.setRoot(LegalizedNodes[OldRoot]); 458 459 ExpandedNodes.clear(); 460 LegalizedNodes.clear(); 461 PromotedNodes.clear(); 462 463 // Remove dead nodes now. 464 DAG.RemoveDeadNodes(OldRoot.Val); 465} 466 467SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 468 assert(isTypeLegal(Op.getValueType()) && 469 "Caller should expand or promote operands that are not legal!"); 470 SDNode *Node = Op.Val; 471 472 // If this operation defines any values that cannot be represented in a 473 // register on this target, make sure to expand or promote them. 474 if (Node->getNumValues() > 1) { 475 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 476 switch (getTypeAction(Node->getValueType(i))) { 477 case Legal: break; // Nothing to do. 478 case Expand: { 479 SDOperand T1, T2; 480 ExpandOp(Op.getValue(i), T1, T2); 481 assert(LegalizedNodes.count(Op) && 482 "Expansion didn't add legal operands!"); 483 return LegalizedNodes[Op]; 484 } 485 case Promote: 486 PromoteOp(Op.getValue(i)); 487 assert(LegalizedNodes.count(Op) && 488 "Expansion didn't add legal operands!"); 489 return LegalizedNodes[Op]; 490 } 491 } 492 493 // Note that LegalizeOp may be reentered even from single-use nodes, which 494 // means that we always must cache transformed nodes. 495 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 496 if (I != LegalizedNodes.end()) return I->second; 497 498 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 499 500 SDOperand Result = Op; 501 502 switch (Node->getOpcode()) { 503 default: 504 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 505 // If this is a target node, legalize it by legalizing the operands then 506 // passing it through. 507 std::vector<SDOperand> Ops; 508 bool Changed = false; 509 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 510 Ops.push_back(LegalizeOp(Node->getOperand(i))); 511 Changed = Changed || Node->getOperand(i) != Ops.back(); 512 } 513 if (Changed) 514 if (Node->getNumValues() == 1) 515 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 516 else { 517 std::vector<MVT::ValueType> VTs(Node->value_begin(), 518 Node->value_end()); 519 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 520 } 521 522 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 523 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 524 return Result.getValue(Op.ResNo); 525 } 526 // Otherwise this is an unhandled builtin node. splat. 527 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 528 assert(0 && "Do not know how to legalize this operator!"); 529 abort(); 530 case ISD::EntryToken: 531 case ISD::FrameIndex: 532 case ISD::TargetFrameIndex: 533 case ISD::Register: 534 case ISD::TargetConstant: 535 case ISD::GlobalAddress: 536 case ISD::TargetGlobalAddress: 537 case ISD::ExternalSymbol: 538 case ISD::ConstantPool: // Nothing to do. 539 case ISD::BasicBlock: 540 case ISD::CONDCODE: 541 case ISD::VALUETYPE: 542 case ISD::SRCVALUE: 543 case ISD::STRING: 544 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 545 default: assert(0 && "This action is not supported yet!"); 546 case TargetLowering::Custom: { 547 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 548 if (Tmp.Val) { 549 Result = LegalizeOp(Tmp); 550 break; 551 } 552 } // FALLTHROUGH if the target doesn't want to lower this op after all. 553 case TargetLowering::Legal: 554 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!"); 555 break; 556 } 557 break; 558 case ISD::AssertSext: 559 case ISD::AssertZext: 560 Tmp1 = LegalizeOp(Node->getOperand(0)); 561 if (Tmp1 != Node->getOperand(0)) 562 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 563 Node->getOperand(1)); 564 break; 565 case ISD::MERGE_VALUES: 566 return LegalizeOp(Node->getOperand(Op.ResNo)); 567 case ISD::CopyFromReg: 568 Tmp1 = LegalizeOp(Node->getOperand(0)); 569 if (Tmp1 != Node->getOperand(0)) 570 Result = DAG.getCopyFromReg(Tmp1, 571 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 572 Node->getValueType(0)); 573 else 574 Result = Op.getValue(0); 575 576 // Since CopyFromReg produces two values, make sure to remember that we 577 // legalized both of them. 578 AddLegalizedOperand(Op.getValue(0), Result); 579 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 580 return Result.getValue(Op.ResNo); 581 case ISD::ImplicitDef: 582 Tmp1 = LegalizeOp(Node->getOperand(0)); 583 if (Tmp1 != Node->getOperand(0)) 584 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other, 585 Tmp1, Node->getOperand(1)); 586 break; 587 case ISD::UNDEF: { 588 MVT::ValueType VT = Op.getValueType(); 589 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 590 default: assert(0 && "This action is not supported yet!"); 591 case TargetLowering::Expand: 592 case TargetLowering::Promote: 593 if (MVT::isInteger(VT)) 594 Result = DAG.getConstant(0, VT); 595 else if (MVT::isFloatingPoint(VT)) 596 Result = DAG.getConstantFP(0, VT); 597 else 598 assert(0 && "Unknown value type!"); 599 break; 600 case TargetLowering::Legal: 601 break; 602 } 603 break; 604 } 605 606 case ISD::LOCATION: 607 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 608 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 609 610 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 611 case TargetLowering::Promote: 612 default: assert(0 && "This action is not supported yet!"); 613 case TargetLowering::Expand: 614 // If the target doesn't support line numbers, ignore this node. 615 Result = Tmp1; 616 break; 617 case TargetLowering::Legal: 618 if (Tmp1 != Node->getOperand(0) || 619 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 620 std::vector<SDOperand> Ops; 621 Ops.push_back(Tmp1); 622 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 623 Ops.push_back(Node->getOperand(1)); // line # must be legal. 624 Ops.push_back(Node->getOperand(2)); // col # must be legal. 625 } else { 626 // Otherwise promote them. 627 Ops.push_back(PromoteOp(Node->getOperand(1))); 628 Ops.push_back(PromoteOp(Node->getOperand(2))); 629 } 630 Ops.push_back(Node->getOperand(3)); // filename must be legal. 631 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 632 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops); 633 } 634 break; 635 } 636 break; 637 638 case ISD::Constant: 639 // We know we don't need to expand constants here, constants only have one 640 // value and we check that it is fine above. 641 642 // FIXME: Maybe we should handle things like targets that don't support full 643 // 32-bit immediates? 644 break; 645 case ISD::ConstantFP: { 646 // Spill FP immediates to the constant pool if the target cannot directly 647 // codegen them. Targets often have some immediate values that can be 648 // efficiently generated into an FP register without a load. We explicitly 649 // leave these constants as ConstantFP nodes for the target to deal with. 650 651 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 652 653 // Check to see if this FP immediate is already legal. 654 bool isLegal = false; 655 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 656 E = TLI.legal_fpimm_end(); I != E; ++I) 657 if (CFP->isExactlyValue(*I)) { 658 isLegal = true; 659 break; 660 } 661 662 if (!isLegal) { 663 // Otherwise we need to spill the constant to memory. 664 bool Extend = false; 665 666 // If a FP immediate is precise when represented as a float, we put it 667 // into the constant pool as a float, even if it's is statically typed 668 // as a double. 669 MVT::ValueType VT = CFP->getValueType(0); 670 bool isDouble = VT == MVT::f64; 671 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 672 Type::FloatTy, CFP->getValue()); 673 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 674 // Only do this if the target has a native EXTLOAD instruction from 675 // f32. 676 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 677 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 678 VT = MVT::f32; 679 Extend = true; 680 } 681 682 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 683 if (Extend) { 684 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 685 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 686 } else { 687 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 688 DAG.getSrcValue(NULL)); 689 } 690 } 691 break; 692 } 693 case ISD::TokenFactor: 694 if (Node->getNumOperands() == 2) { 695 bool Changed = false; 696 SDOperand Op0 = LegalizeOp(Node->getOperand(0)); 697 SDOperand Op1 = LegalizeOp(Node->getOperand(1)); 698 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1)) 699 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1); 700 } else { 701 std::vector<SDOperand> Ops; 702 bool Changed = false; 703 // Legalize the operands. 704 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 705 SDOperand Op = Node->getOperand(i); 706 Ops.push_back(LegalizeOp(Op)); 707 Changed |= Ops[i] != Op; 708 } 709 if (Changed) 710 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 711 } 712 break; 713 714 case ISD::CALLSEQ_START: 715 case ISD::CALLSEQ_END: 716 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 717 // Do not try to legalize the target-specific arguments (#1+) 718 Tmp2 = Node->getOperand(0); 719 if (Tmp1 != Tmp2) 720 Node->setAdjCallChain(Tmp1); 721 722 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These 723 // nodes are treated specially and are mutated in place. This makes the dag 724 // legalization process more efficient and also makes libcall insertion 725 // easier. 726 break; 727 case ISD::DYNAMIC_STACKALLOC: 728 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 729 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 730 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 731 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 732 Tmp3 != Node->getOperand(2)) { 733 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 734 std::vector<SDOperand> Ops; 735 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 736 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 737 } else 738 Result = Op.getValue(0); 739 740 // Since this op produces two values, make sure to remember that we 741 // legalized both of them. 742 AddLegalizedOperand(SDOperand(Node, 0), Result); 743 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 744 return Result.getValue(Op.ResNo); 745 746 case ISD::TAILCALL: 747 case ISD::CALL: { 748 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 749 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 750 751 bool Changed = false; 752 std::vector<SDOperand> Ops; 753 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 754 Ops.push_back(LegalizeOp(Node->getOperand(i))); 755 Changed |= Ops.back() != Node->getOperand(i); 756 } 757 758 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 759 std::vector<MVT::ValueType> RetTyVTs; 760 RetTyVTs.reserve(Node->getNumValues()); 761 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 762 RetTyVTs.push_back(Node->getValueType(i)); 763 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 764 Node->getOpcode() == ISD::TAILCALL), 0); 765 } else { 766 Result = Result.getValue(0); 767 } 768 // Since calls produce multiple values, make sure to remember that we 769 // legalized all of them. 770 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 771 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 772 return Result.getValue(Op.ResNo); 773 } 774 case ISD::BR: 775 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 776 if (Tmp1 != Node->getOperand(0)) 777 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 778 break; 779 780 case ISD::BRCOND: 781 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 782 783 switch (getTypeAction(Node->getOperand(1).getValueType())) { 784 case Expand: assert(0 && "It's impossible to expand bools"); 785 case Legal: 786 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 787 break; 788 case Promote: 789 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 790 break; 791 } 792 793 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 794 default: assert(0 && "This action is not supported yet!"); 795 case TargetLowering::Expand: 796 // Expand brcond's setcc into its constituent parts and create a BR_CC 797 // Node. 798 if (Tmp2.getOpcode() == ISD::SETCC) { 799 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 800 Tmp2.getOperand(0), Tmp2.getOperand(1), 801 Node->getOperand(2)); 802 } else { 803 // Make sure the condition is either zero or one. It may have been 804 // promoted from something else. 805 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 806 807 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 808 DAG.getCondCode(ISD::SETNE), Tmp2, 809 DAG.getConstant(0, Tmp2.getValueType()), 810 Node->getOperand(2)); 811 } 812 break; 813 case TargetLowering::Legal: 814 // Basic block destination (Op#2) is always legal. 815 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 816 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 817 Node->getOperand(2)); 818 break; 819 } 820 break; 821 case ISD::BR_CC: 822 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 823 824 if (isTypeLegal(Node->getOperand(2).getValueType())) { 825 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 826 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 827 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 828 Tmp3 != Node->getOperand(3)) { 829 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 830 Tmp2, Tmp3, Node->getOperand(4)); 831 } 832 break; 833 } else { 834 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 835 Node->getOperand(2), // LHS 836 Node->getOperand(3), // RHS 837 Node->getOperand(1))); 838 // If we get a SETCC back from legalizing the SETCC node we just 839 // created, then use its LHS, RHS, and CC directly in creating a new 840 // node. Otherwise, select between the true and false value based on 841 // comparing the result of the legalized with zero. 842 if (Tmp2.getOpcode() == ISD::SETCC) { 843 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 844 Tmp2.getOperand(0), Tmp2.getOperand(1), 845 Node->getOperand(4)); 846 } else { 847 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 848 DAG.getCondCode(ISD::SETNE), 849 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 850 Node->getOperand(4)); 851 } 852 } 853 break; 854 case ISD::BRCONDTWOWAY: 855 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 856 switch (getTypeAction(Node->getOperand(1).getValueType())) { 857 case Expand: assert(0 && "It's impossible to expand bools"); 858 case Legal: 859 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 860 break; 861 case Promote: 862 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 863 break; 864 } 865 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 866 // pair. 867 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 868 case TargetLowering::Promote: 869 default: assert(0 && "This action is not supported yet!"); 870 case TargetLowering::Legal: 871 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 872 std::vector<SDOperand> Ops; 873 Ops.push_back(Tmp1); 874 Ops.push_back(Tmp2); 875 Ops.push_back(Node->getOperand(2)); 876 Ops.push_back(Node->getOperand(3)); 877 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 878 } 879 break; 880 case TargetLowering::Expand: 881 // If BRTWOWAY_CC is legal for this target, then simply expand this node 882 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 883 // BRCOND/BR pair. 884 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 885 if (Tmp2.getOpcode() == ISD::SETCC) { 886 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 887 Tmp2.getOperand(0), Tmp2.getOperand(1), 888 Node->getOperand(2), Node->getOperand(3)); 889 } else { 890 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 891 DAG.getConstant(0, Tmp2.getValueType()), 892 Node->getOperand(2), Node->getOperand(3)); 893 } 894 } else { 895 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 896 Node->getOperand(2)); 897 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 898 } 899 break; 900 } 901 break; 902 case ISD::BRTWOWAY_CC: 903 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 904 if (isTypeLegal(Node->getOperand(2).getValueType())) { 905 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 906 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 907 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 908 Tmp3 != Node->getOperand(3)) { 909 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3, 910 Node->getOperand(4), Node->getOperand(5)); 911 } 912 break; 913 } else { 914 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 915 Node->getOperand(2), // LHS 916 Node->getOperand(3), // RHS 917 Node->getOperand(1))); 918 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 919 // pair. 920 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 921 default: assert(0 && "This action is not supported yet!"); 922 case TargetLowering::Legal: 923 // If we get a SETCC back from legalizing the SETCC node we just 924 // created, then use its LHS, RHS, and CC directly in creating a new 925 // node. Otherwise, select between the true and false value based on 926 // comparing the result of the legalized with zero. 927 if (Tmp2.getOpcode() == ISD::SETCC) { 928 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 929 Tmp2.getOperand(0), Tmp2.getOperand(1), 930 Node->getOperand(4), Node->getOperand(5)); 931 } else { 932 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 933 DAG.getConstant(0, Tmp2.getValueType()), 934 Node->getOperand(4), Node->getOperand(5)); 935 } 936 break; 937 case TargetLowering::Expand: 938 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 939 Node->getOperand(4)); 940 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 941 break; 942 } 943 } 944 break; 945 case ISD::LOAD: 946 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 947 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 948 949 if (Tmp1 != Node->getOperand(0) || 950 Tmp2 != Node->getOperand(1)) 951 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, 952 Node->getOperand(2)); 953 else 954 Result = SDOperand(Node, 0); 955 956 // Since loads produce two values, make sure to remember that we legalized 957 // both of them. 958 AddLegalizedOperand(SDOperand(Node, 0), Result); 959 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 960 return Result.getValue(Op.ResNo); 961 962 case ISD::EXTLOAD: 963 case ISD::SEXTLOAD: 964 case ISD::ZEXTLOAD: { 965 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 966 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 967 968 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 969 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 970 default: assert(0 && "This action is not supported yet!"); 971 case TargetLowering::Promote: 972 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 973 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 974 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 975 // Since loads produce two values, make sure to remember that we legalized 976 // both of them. 977 AddLegalizedOperand(SDOperand(Node, 0), Result); 978 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 979 return Result.getValue(Op.ResNo); 980 981 case TargetLowering::Legal: 982 if (Tmp1 != Node->getOperand(0) || 983 Tmp2 != Node->getOperand(1)) 984 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 985 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 986 else 987 Result = SDOperand(Node, 0); 988 989 // Since loads produce two values, make sure to remember that we legalized 990 // both of them. 991 AddLegalizedOperand(SDOperand(Node, 0), Result); 992 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 993 return Result.getValue(Op.ResNo); 994 case TargetLowering::Expand: 995 //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 996 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 997 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 998 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 999 if (Op.ResNo) 1000 return Load.getValue(1); 1001 return Result; 1002 } 1003 assert(Node->getOpcode() != ISD::EXTLOAD && 1004 "EXTLOAD should always be supported!"); 1005 // Turn the unsupported load into an EXTLOAD followed by an explicit 1006 // zero/sign extend inreg. 1007 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1008 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1009 SDOperand ValRes; 1010 if (Node->getOpcode() == ISD::SEXTLOAD) 1011 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1012 Result, DAG.getValueType(SrcVT)); 1013 else 1014 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1015 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 1016 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1017 if (Op.ResNo) 1018 return Result.getValue(1); 1019 return ValRes; 1020 } 1021 assert(0 && "Unreachable"); 1022 } 1023 case ISD::EXTRACT_ELEMENT: { 1024 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1025 switch (getTypeAction(OpTy)) { 1026 default: 1027 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1028 break; 1029 case Legal: 1030 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1031 // 1 -> Hi 1032 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1033 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1034 TLI.getShiftAmountTy())); 1035 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1036 } else { 1037 // 0 -> Lo 1038 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1039 Node->getOperand(0)); 1040 } 1041 Result = LegalizeOp(Result); 1042 break; 1043 case Expand: 1044 // Get both the low and high parts. 1045 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1046 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1047 Result = Tmp2; // 1 -> Hi 1048 else 1049 Result = Tmp1; // 0 -> Lo 1050 break; 1051 } 1052 break; 1053 } 1054 1055 case ISD::CopyToReg: 1056 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1057 1058 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1059 "Register type must be legal!"); 1060 // Legalize the incoming value (must be legal). 1061 Tmp2 = LegalizeOp(Node->getOperand(2)); 1062 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2)) 1063 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1, 1064 Node->getOperand(1), Tmp2); 1065 break; 1066 1067 case ISD::RET: 1068 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1069 switch (Node->getNumOperands()) { 1070 case 2: // ret val 1071 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1072 case Legal: 1073 Tmp2 = LegalizeOp(Node->getOperand(1)); 1074 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1075 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1076 break; 1077 case Expand: { 1078 SDOperand Lo, Hi; 1079 ExpandOp(Node->getOperand(1), Lo, Hi); 1080 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1081 break; 1082 } 1083 case Promote: 1084 Tmp2 = PromoteOp(Node->getOperand(1)); 1085 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1086 break; 1087 } 1088 break; 1089 case 1: // ret void 1090 if (Tmp1 != Node->getOperand(0)) 1091 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 1092 break; 1093 default: { // ret <values> 1094 std::vector<SDOperand> NewValues; 1095 NewValues.push_back(Tmp1); 1096 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1097 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1098 case Legal: 1099 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1100 break; 1101 case Expand: { 1102 SDOperand Lo, Hi; 1103 ExpandOp(Node->getOperand(i), Lo, Hi); 1104 NewValues.push_back(Lo); 1105 NewValues.push_back(Hi); 1106 break; 1107 } 1108 case Promote: 1109 assert(0 && "Can't promote multiple return value yet!"); 1110 } 1111 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1112 break; 1113 } 1114 } 1115 break; 1116 case ISD::STORE: 1117 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1118 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1119 1120 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1121 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1122 if (CFP->getValueType(0) == MVT::f32) { 1123 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1124 DAG.getConstant(FloatToBits(CFP->getValue()), 1125 MVT::i32), 1126 Tmp2, 1127 Node->getOperand(3)); 1128 } else { 1129 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1130 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1131 DAG.getConstant(DoubleToBits(CFP->getValue()), 1132 MVT::i64), 1133 Tmp2, 1134 Node->getOperand(3)); 1135 } 1136 Node = Result.Val; 1137 } 1138 1139 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1140 case Legal: { 1141 SDOperand Val = LegalizeOp(Node->getOperand(1)); 1142 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 1143 Tmp2 != Node->getOperand(2)) 1144 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 1145 Node->getOperand(3)); 1146 break; 1147 } 1148 case Promote: 1149 // Truncate the value and store the result. 1150 Tmp3 = PromoteOp(Node->getOperand(1)); 1151 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1152 Node->getOperand(3), 1153 DAG.getValueType(Node->getOperand(1).getValueType())); 1154 break; 1155 1156 case Expand: 1157 SDOperand Lo, Hi; 1158 unsigned IncrementSize; 1159 ExpandOp(Node->getOperand(1), Lo, Hi); 1160 1161 if (!TLI.isLittleEndian()) 1162 std::swap(Lo, Hi); 1163 1164 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1165 Node->getOperand(3)); 1166 // If this is a vector type, then we have to calculate the increment as 1167 // the product of the element size in bytes, and the number of elements 1168 // in the high half of the vector. 1169 if (MVT::Vector == Hi.getValueType()) { 1170 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue(); 1171 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT(); 1172 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8; 1173 } else { 1174 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1175 } 1176 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1177 getIntPtrConstant(IncrementSize)); 1178 assert(isTypeLegal(Tmp2.getValueType()) && 1179 "Pointers must be legal!"); 1180 //Again, claiming both parts of the store came form the same Instr 1181 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1182 Node->getOperand(3)); 1183 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1184 break; 1185 } 1186 break; 1187 case ISD::PCMARKER: 1188 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1189 if (Tmp1 != Node->getOperand(0)) 1190 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 1191 break; 1192 case ISD::READCYCLECOUNTER: 1193 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1194 if (Tmp1 != Node->getOperand(0)) { 1195 std::vector<MVT::ValueType> rtypes; 1196 std::vector<SDOperand> rvals; 1197 rtypes.push_back(MVT::i64); 1198 rtypes.push_back(MVT::Other); 1199 rvals.push_back(Tmp1); 1200 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals); 1201 } 1202 1203 // Since rdcc produce two values, make sure to remember that we legalized 1204 // both of them. 1205 AddLegalizedOperand(SDOperand(Node, 0), Result); 1206 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1207 return Result.getValue(Op.ResNo); 1208 break; 1209 1210 case ISD::TRUNCSTORE: 1211 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1212 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1213 1214 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1215 case Legal: 1216 Tmp2 = LegalizeOp(Node->getOperand(1)); 1217 1218 // The only promote case we handle is TRUNCSTORE:i1 X into 1219 // -> TRUNCSTORE:i8 (and X, 1) 1220 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1221 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1222 TargetLowering::Promote) { 1223 // Promote the bool to a mask then store. 1224 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1225 DAG.getConstant(1, Tmp2.getValueType())); 1226 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1227 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1228 1229 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1230 Tmp3 != Node->getOperand(2)) { 1231 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1232 Node->getOperand(3), Node->getOperand(4)); 1233 } 1234 break; 1235 case Promote: 1236 case Expand: 1237 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 1238 } 1239 break; 1240 case ISD::SELECT: 1241 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1242 case Expand: assert(0 && "It's impossible to expand bools"); 1243 case Legal: 1244 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1245 break; 1246 case Promote: 1247 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1248 break; 1249 } 1250 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1251 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1252 1253 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1254 default: assert(0 && "This action is not supported yet!"); 1255 case TargetLowering::Expand: 1256 if (Tmp1.getOpcode() == ISD::SETCC) { 1257 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1258 Tmp2, Tmp3, 1259 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1260 } else { 1261 // Make sure the condition is either zero or one. It may have been 1262 // promoted from something else. 1263 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1264 Result = DAG.getSelectCC(Tmp1, 1265 DAG.getConstant(0, Tmp1.getValueType()), 1266 Tmp2, Tmp3, ISD::SETNE); 1267 } 1268 break; 1269 case TargetLowering::Legal: 1270 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1271 Tmp3 != Node->getOperand(2)) 1272 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 1273 Tmp1, Tmp2, Tmp3); 1274 break; 1275 case TargetLowering::Promote: { 1276 MVT::ValueType NVT = 1277 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1278 unsigned ExtOp, TruncOp; 1279 if (MVT::isInteger(Tmp2.getValueType())) { 1280 ExtOp = ISD::ANY_EXTEND; 1281 TruncOp = ISD::TRUNCATE; 1282 } else { 1283 ExtOp = ISD::FP_EXTEND; 1284 TruncOp = ISD::FP_ROUND; 1285 } 1286 // Promote each of the values to the new type. 1287 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1288 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1289 // Perform the larger operation, then round down. 1290 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1291 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1292 break; 1293 } 1294 } 1295 break; 1296 case ISD::SELECT_CC: 1297 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1298 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1299 1300 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1301 // Everything is legal, see if we should expand this op or something. 1302 switch (TLI.getOperationAction(ISD::SELECT_CC, 1303 Node->getOperand(0).getValueType())) { 1304 default: assert(0 && "This action is not supported yet!"); 1305 case TargetLowering::Custom: { 1306 SDOperand Tmp = 1307 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), 1308 Node->getOperand(0), 1309 Node->getOperand(1), Tmp3, Tmp4, 1310 Node->getOperand(4)), DAG); 1311 if (Tmp.Val) { 1312 Result = LegalizeOp(Tmp); 1313 break; 1314 } 1315 } // FALLTHROUGH if the target can't lower this operation after all. 1316 case TargetLowering::Legal: 1317 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1318 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1319 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1320 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { 1321 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2, 1322 Tmp3, Tmp4, Node->getOperand(4)); 1323 } 1324 break; 1325 } 1326 break; 1327 } else { 1328 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1329 Node->getOperand(0), // LHS 1330 Node->getOperand(1), // RHS 1331 Node->getOperand(4))); 1332 // If we get a SETCC back from legalizing the SETCC node we just 1333 // created, then use its LHS, RHS, and CC directly in creating a new 1334 // node. Otherwise, select between the true and false value based on 1335 // comparing the result of the legalized with zero. 1336 if (Tmp1.getOpcode() == ISD::SETCC) { 1337 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1338 Tmp1.getOperand(0), Tmp1.getOperand(1), 1339 Tmp3, Tmp4, Tmp1.getOperand(2)); 1340 } else { 1341 Result = DAG.getSelectCC(Tmp1, 1342 DAG.getConstant(0, Tmp1.getValueType()), 1343 Tmp3, Tmp4, ISD::SETNE); 1344 } 1345 } 1346 break; 1347 case ISD::SETCC: 1348 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1349 case Legal: 1350 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1351 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1352 break; 1353 case Promote: 1354 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1355 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1356 1357 // If this is an FP compare, the operands have already been extended. 1358 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1359 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1360 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1361 1362 // Otherwise, we have to insert explicit sign or zero extends. Note 1363 // that we could insert sign extends for ALL conditions, but zero extend 1364 // is cheaper on many machines (an AND instead of two shifts), so prefer 1365 // it. 1366 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1367 default: assert(0 && "Unknown integer comparison!"); 1368 case ISD::SETEQ: 1369 case ISD::SETNE: 1370 case ISD::SETUGE: 1371 case ISD::SETUGT: 1372 case ISD::SETULE: 1373 case ISD::SETULT: 1374 // ALL of these operations will work if we either sign or zero extend 1375 // the operands (including the unsigned comparisons!). Zero extend is 1376 // usually a simpler/cheaper operation, so prefer it. 1377 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1378 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1379 break; 1380 case ISD::SETGE: 1381 case ISD::SETGT: 1382 case ISD::SETLT: 1383 case ISD::SETLE: 1384 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1385 DAG.getValueType(VT)); 1386 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1387 DAG.getValueType(VT)); 1388 break; 1389 } 1390 } 1391 break; 1392 case Expand: 1393 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1394 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1395 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1396 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1397 case ISD::SETEQ: 1398 case ISD::SETNE: 1399 if (RHSLo == RHSHi) 1400 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1401 if (RHSCST->isAllOnesValue()) { 1402 // Comparison to -1. 1403 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1404 Tmp2 = RHSLo; 1405 break; 1406 } 1407 1408 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1409 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1410 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1411 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1412 break; 1413 default: 1414 // If this is a comparison of the sign bit, just look at the top part. 1415 // X > -1, x < 0 1416 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1417 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1418 CST->getValue() == 0) || // X < 0 1419 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1420 (CST->isAllOnesValue()))) { // X > -1 1421 Tmp1 = LHSHi; 1422 Tmp2 = RHSHi; 1423 break; 1424 } 1425 1426 // FIXME: This generated code sucks. 1427 ISD::CondCode LowCC; 1428 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1429 default: assert(0 && "Unknown integer setcc!"); 1430 case ISD::SETLT: 1431 case ISD::SETULT: LowCC = ISD::SETULT; break; 1432 case ISD::SETGT: 1433 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1434 case ISD::SETLE: 1435 case ISD::SETULE: LowCC = ISD::SETULE; break; 1436 case ISD::SETGE: 1437 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1438 } 1439 1440 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1441 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1442 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1443 1444 // NOTE: on targets without efficient SELECT of bools, we can always use 1445 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1446 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1447 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1448 Node->getOperand(2)); 1449 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1450 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1451 Result, Tmp1, Tmp2)); 1452 return Result; 1453 } 1454 } 1455 1456 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) { 1457 default: 1458 assert(0 && "Cannot handle this action for SETCC yet!"); 1459 break; 1460 case TargetLowering::Promote: { 1461 // First step, figure out the appropriate operation to use. 1462 // Allow SETCC to not be supported for all legal data types 1463 // Mostly this targets FP 1464 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1465 MVT::ValueType OldVT = NewInTy; 1466 1467 // Scan for the appropriate larger type to use. 1468 while (1) { 1469 NewInTy = (MVT::ValueType)(NewInTy+1); 1470 1471 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1472 "Fell off of the edge of the integer world"); 1473 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1474 "Fell off of the edge of the floating point world"); 1475 1476 // If the target supports SETCC of this type, use it. 1477 if (TLI.getOperationAction(ISD::SETCC, NewInTy) == TargetLowering::Legal) 1478 break; 1479 } 1480 if (MVT::isInteger(NewInTy)) 1481 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1482 else { 1483 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1484 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1485 } 1486 1487 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1488 Node->getOperand(2)); 1489 break; 1490 } 1491 case TargetLowering::Legal: 1492 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1493 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1494 Node->getOperand(2)); 1495 break; 1496 case TargetLowering::Expand: 1497 // Expand a setcc node into a select_cc of the same condition, lhs, and 1498 // rhs that selects between const 1 (true) and const 0 (false). 1499 MVT::ValueType VT = Node->getValueType(0); 1500 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1501 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1502 Node->getOperand(2)); 1503 Result = LegalizeOp(Result); 1504 break; 1505 } 1506 break; 1507 1508 case ISD::MEMSET: 1509 case ISD::MEMCPY: 1510 case ISD::MEMMOVE: { 1511 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1512 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1513 1514 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1515 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1516 case Expand: assert(0 && "Cannot expand a byte!"); 1517 case Legal: 1518 Tmp3 = LegalizeOp(Node->getOperand(2)); 1519 break; 1520 case Promote: 1521 Tmp3 = PromoteOp(Node->getOperand(2)); 1522 break; 1523 } 1524 } else { 1525 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1526 } 1527 1528 SDOperand Tmp4; 1529 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1530 case Expand: { 1531 // Length is too big, just take the lo-part of the length. 1532 SDOperand HiPart; 1533 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1534 break; 1535 } 1536 case Legal: 1537 Tmp4 = LegalizeOp(Node->getOperand(3)); 1538 break; 1539 case Promote: 1540 Tmp4 = PromoteOp(Node->getOperand(3)); 1541 break; 1542 } 1543 1544 SDOperand Tmp5; 1545 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1546 case Expand: assert(0 && "Cannot expand this yet!"); 1547 case Legal: 1548 Tmp5 = LegalizeOp(Node->getOperand(4)); 1549 break; 1550 case Promote: 1551 Tmp5 = PromoteOp(Node->getOperand(4)); 1552 break; 1553 } 1554 1555 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1556 default: assert(0 && "This action not implemented for this operation!"); 1557 case TargetLowering::Custom: { 1558 SDOperand Tmp = 1559 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 1560 Tmp2, Tmp3, Tmp4, Tmp5), DAG); 1561 if (Tmp.Val) { 1562 Result = LegalizeOp(Tmp); 1563 break; 1564 } 1565 // FALLTHROUGH if the target thinks it is legal. 1566 } 1567 case TargetLowering::Legal: 1568 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1569 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 1570 Tmp5 != Node->getOperand(4)) { 1571 std::vector<SDOperand> Ops; 1572 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 1573 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 1574 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 1575 } 1576 break; 1577 case TargetLowering::Expand: { 1578 // Otherwise, the target does not support this operation. Lower the 1579 // operation to an explicit libcall as appropriate. 1580 MVT::ValueType IntPtr = TLI.getPointerTy(); 1581 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1582 std::vector<std::pair<SDOperand, const Type*> > Args; 1583 1584 const char *FnName = 0; 1585 if (Node->getOpcode() == ISD::MEMSET) { 1586 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1587 // Extend the ubyte argument to be an int value for the call. 1588 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1589 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1590 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1591 1592 FnName = "memset"; 1593 } else if (Node->getOpcode() == ISD::MEMCPY || 1594 Node->getOpcode() == ISD::MEMMOVE) { 1595 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1596 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1597 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1598 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1599 } else { 1600 assert(0 && "Unknown op!"); 1601 } 1602 1603 std::pair<SDOperand,SDOperand> CallResult = 1604 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1605 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1606 Result = CallResult.second; 1607 NeedsAnotherIteration = true; 1608 break; 1609 } 1610 } 1611 break; 1612 } 1613 1614 case ISD::READPORT: 1615 Tmp1 = LegalizeOp(Node->getOperand(0)); 1616 Tmp2 = LegalizeOp(Node->getOperand(1)); 1617 1618 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1619 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1620 std::vector<SDOperand> Ops; 1621 Ops.push_back(Tmp1); 1622 Ops.push_back(Tmp2); 1623 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1624 } else 1625 Result = SDOperand(Node, 0); 1626 // Since these produce two values, make sure to remember that we legalized 1627 // both of them. 1628 AddLegalizedOperand(SDOperand(Node, 0), Result); 1629 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1630 return Result.getValue(Op.ResNo); 1631 case ISD::WRITEPORT: 1632 Tmp1 = LegalizeOp(Node->getOperand(0)); 1633 Tmp2 = LegalizeOp(Node->getOperand(1)); 1634 Tmp3 = LegalizeOp(Node->getOperand(2)); 1635 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1636 Tmp3 != Node->getOperand(2)) 1637 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1638 break; 1639 1640 case ISD::READIO: 1641 Tmp1 = LegalizeOp(Node->getOperand(0)); 1642 Tmp2 = LegalizeOp(Node->getOperand(1)); 1643 1644 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1645 case TargetLowering::Custom: 1646 default: assert(0 && "This action not implemented for this operation!"); 1647 case TargetLowering::Legal: 1648 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1649 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1650 std::vector<SDOperand> Ops; 1651 Ops.push_back(Tmp1); 1652 Ops.push_back(Tmp2); 1653 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1654 } else 1655 Result = SDOperand(Node, 0); 1656 break; 1657 case TargetLowering::Expand: 1658 // Replace this with a load from memory. 1659 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 1660 Node->getOperand(1), DAG.getSrcValue(NULL)); 1661 Result = LegalizeOp(Result); 1662 break; 1663 } 1664 1665 // Since these produce two values, make sure to remember that we legalized 1666 // both of them. 1667 AddLegalizedOperand(SDOperand(Node, 0), Result); 1668 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1669 return Result.getValue(Op.ResNo); 1670 1671 case ISD::WRITEIO: 1672 Tmp1 = LegalizeOp(Node->getOperand(0)); 1673 Tmp2 = LegalizeOp(Node->getOperand(1)); 1674 Tmp3 = LegalizeOp(Node->getOperand(2)); 1675 1676 switch (TLI.getOperationAction(Node->getOpcode(), 1677 Node->getOperand(1).getValueType())) { 1678 case TargetLowering::Custom: 1679 default: assert(0 && "This action not implemented for this operation!"); 1680 case TargetLowering::Legal: 1681 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1682 Tmp3 != Node->getOperand(2)) 1683 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1684 break; 1685 case TargetLowering::Expand: 1686 // Replace this with a store to memory. 1687 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 1688 Node->getOperand(1), Node->getOperand(2), 1689 DAG.getSrcValue(NULL)); 1690 Result = LegalizeOp(Result); 1691 break; 1692 } 1693 break; 1694 1695 case ISD::ADD_PARTS: 1696 case ISD::SUB_PARTS: 1697 case ISD::SHL_PARTS: 1698 case ISD::SRA_PARTS: 1699 case ISD::SRL_PARTS: { 1700 std::vector<SDOperand> Ops; 1701 bool Changed = false; 1702 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1703 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1704 Changed |= Ops.back() != Node->getOperand(i); 1705 } 1706 if (Changed) { 1707 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1708 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 1709 } 1710 1711 // Since these produce multiple values, make sure to remember that we 1712 // legalized all of them. 1713 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1714 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1715 return Result.getValue(Op.ResNo); 1716 } 1717 1718 // Binary operators 1719 case ISD::ADD: 1720 case ISD::SUB: 1721 case ISD::MUL: 1722 case ISD::MULHS: 1723 case ISD::MULHU: 1724 case ISD::UDIV: 1725 case ISD::SDIV: 1726 case ISD::AND: 1727 case ISD::OR: 1728 case ISD::XOR: 1729 case ISD::SHL: 1730 case ISD::SRL: 1731 case ISD::SRA: 1732 case ISD::FADD: 1733 case ISD::FSUB: 1734 case ISD::FMUL: 1735 case ISD::FDIV: 1736 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1737 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1738 case Expand: assert(0 && "Not possible"); 1739 case Legal: 1740 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1741 break; 1742 case Promote: 1743 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 1744 break; 1745 } 1746 if (Tmp1 != Node->getOperand(0) || 1747 Tmp2 != Node->getOperand(1)) 1748 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 1749 break; 1750 1751 case ISD::BUILD_PAIR: { 1752 MVT::ValueType PairTy = Node->getValueType(0); 1753 // TODO: handle the case where the Lo and Hi operands are not of legal type 1754 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 1755 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 1756 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 1757 case TargetLowering::Legal: 1758 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1759 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 1760 break; 1761 case TargetLowering::Promote: 1762 case TargetLowering::Custom: 1763 assert(0 && "Cannot promote/custom this yet!"); 1764 case TargetLowering::Expand: 1765 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 1766 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 1767 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 1768 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 1769 TLI.getShiftAmountTy())); 1770 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2)); 1771 break; 1772 } 1773 break; 1774 } 1775 1776 case ISD::UREM: 1777 case ISD::SREM: 1778 case ISD::FREM: 1779 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1780 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1781 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1782 case TargetLowering::Legal: 1783 if (Tmp1 != Node->getOperand(0) || 1784 Tmp2 != Node->getOperand(1)) 1785 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1786 Tmp2); 1787 break; 1788 case TargetLowering::Promote: 1789 case TargetLowering::Custom: 1790 assert(0 && "Cannot promote/custom handle this yet!"); 1791 case TargetLowering::Expand: 1792 if (MVT::isInteger(Node->getValueType(0))) { 1793 MVT::ValueType VT = Node->getValueType(0); 1794 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 1795 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 1796 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 1797 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 1798 } else { 1799 // Floating point mod -> fmod libcall. 1800 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 1801 SDOperand Dummy; 1802 Result = ExpandLibCall(FnName, Node, Dummy); 1803 } 1804 break; 1805 } 1806 break; 1807 1808 case ISD::CTPOP: 1809 case ISD::CTTZ: 1810 case ISD::CTLZ: 1811 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1812 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1813 case TargetLowering::Legal: 1814 if (Tmp1 != Node->getOperand(0)) 1815 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1816 break; 1817 case TargetLowering::Promote: { 1818 MVT::ValueType OVT = Tmp1.getValueType(); 1819 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1820 1821 // Zero extend the argument. 1822 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1823 // Perform the larger operation, then subtract if needed. 1824 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1825 switch(Node->getOpcode()) 1826 { 1827 case ISD::CTPOP: 1828 Result = Tmp1; 1829 break; 1830 case ISD::CTTZ: 1831 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 1832 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 1833 DAG.getConstant(getSizeInBits(NVT), NVT), 1834 ISD::SETEQ); 1835 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 1836 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 1837 break; 1838 case ISD::CTLZ: 1839 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 1840 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 1841 DAG.getConstant(getSizeInBits(NVT) - 1842 getSizeInBits(OVT), NVT)); 1843 break; 1844 } 1845 break; 1846 } 1847 case TargetLowering::Custom: 1848 assert(0 && "Cannot custom handle this yet!"); 1849 case TargetLowering::Expand: 1850 switch(Node->getOpcode()) 1851 { 1852 case ISD::CTPOP: { 1853 static const uint64_t mask[6] = { 1854 0x5555555555555555ULL, 0x3333333333333333ULL, 1855 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 1856 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 1857 }; 1858 MVT::ValueType VT = Tmp1.getValueType(); 1859 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1860 unsigned len = getSizeInBits(VT); 1861 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1862 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 1863 Tmp2 = DAG.getConstant(mask[i], VT); 1864 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1865 Tmp1 = DAG.getNode(ISD::ADD, VT, 1866 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 1867 DAG.getNode(ISD::AND, VT, 1868 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 1869 Tmp2)); 1870 } 1871 Result = Tmp1; 1872 break; 1873 } 1874 case ISD::CTLZ: { 1875 /* for now, we do this: 1876 x = x | (x >> 1); 1877 x = x | (x >> 2); 1878 ... 1879 x = x | (x >>16); 1880 x = x | (x >>32); // for 64-bit input 1881 return popcount(~x); 1882 1883 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ 1884 MVT::ValueType VT = Tmp1.getValueType(); 1885 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 1886 unsigned len = getSizeInBits(VT); 1887 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 1888 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 1889 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, 1890 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); 1891 } 1892 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); 1893 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1894 break; 1895 } 1896 case ISD::CTTZ: { 1897 // for now, we use: { return popcount(~x & (x - 1)); } 1898 // unless the target has ctlz but not ctpop, in which case we use: 1899 // { return 32 - nlz(~x & (x-1)); } 1900 // see also http://www.hackersdelight.org/HDcode/ntz.cc 1901 MVT::ValueType VT = Tmp1.getValueType(); 1902 Tmp2 = DAG.getConstant(~0ULL, VT); 1903 Tmp3 = DAG.getNode(ISD::AND, VT, 1904 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), 1905 DAG.getNode(ISD::SUB, VT, Tmp1, 1906 DAG.getConstant(1, VT))); 1907 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead 1908 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 1909 TLI.isOperationLegal(ISD::CTLZ, VT)) { 1910 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, 1911 DAG.getConstant(getSizeInBits(VT), VT), 1912 DAG.getNode(ISD::CTLZ, VT, Tmp3))); 1913 } else { 1914 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 1915 } 1916 break; 1917 } 1918 default: 1919 assert(0 && "Cannot expand this yet!"); 1920 break; 1921 } 1922 break; 1923 } 1924 break; 1925 1926 // Unary operators 1927 case ISD::FABS: 1928 case ISD::FNEG: 1929 case ISD::FSQRT: 1930 case ISD::FSIN: 1931 case ISD::FCOS: 1932 Tmp1 = LegalizeOp(Node->getOperand(0)); 1933 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1934 case TargetLowering::Legal: 1935 if (Tmp1 != Node->getOperand(0)) 1936 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1937 break; 1938 case TargetLowering::Promote: 1939 case TargetLowering::Custom: 1940 assert(0 && "Cannot promote/custom handle this yet!"); 1941 case TargetLowering::Expand: 1942 switch(Node->getOpcode()) { 1943 case ISD::FNEG: { 1944 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 1945 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 1946 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0), 1947 Tmp2, Tmp1)); 1948 break; 1949 } 1950 case ISD::FABS: { 1951 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 1952 MVT::ValueType VT = Node->getValueType(0); 1953 Tmp2 = DAG.getConstantFP(0.0, VT); 1954 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 1955 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 1956 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 1957 Result = LegalizeOp(Result); 1958 break; 1959 } 1960 case ISD::FSQRT: 1961 case ISD::FSIN: 1962 case ISD::FCOS: { 1963 MVT::ValueType VT = Node->getValueType(0); 1964 const char *FnName = 0; 1965 switch(Node->getOpcode()) { 1966 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 1967 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 1968 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 1969 default: assert(0 && "Unreachable!"); 1970 } 1971 SDOperand Dummy; 1972 Result = ExpandLibCall(FnName, Node, Dummy); 1973 break; 1974 } 1975 default: 1976 assert(0 && "Unreachable!"); 1977 } 1978 break; 1979 } 1980 break; 1981 1982 // Conversion operators. The source and destination have different types. 1983 case ISD::SINT_TO_FP: 1984 case ISD::UINT_TO_FP: { 1985 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 1986 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1987 case Legal: 1988 switch (TLI.getOperationAction(Node->getOpcode(), 1989 Node->getOperand(0).getValueType())) { 1990 default: assert(0 && "Unknown operation action!"); 1991 case TargetLowering::Expand: 1992 Result = ExpandLegalINT_TO_FP(isSigned, 1993 LegalizeOp(Node->getOperand(0)), 1994 Node->getValueType(0)); 1995 AddLegalizedOperand(Op, Result); 1996 return Result; 1997 case TargetLowering::Promote: 1998 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 1999 Node->getValueType(0), 2000 isSigned); 2001 AddLegalizedOperand(Op, Result); 2002 return Result; 2003 case TargetLowering::Legal: 2004 break; 2005 case TargetLowering::Custom: { 2006 Tmp1 = LegalizeOp(Node->getOperand(0)); 2007 SDOperand Tmp = 2008 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2009 Tmp = TLI.LowerOperation(Tmp, DAG); 2010 if (Tmp.Val) { 2011 AddLegalizedOperand(Op, Tmp); 2012 NeedsAnotherIteration = true; 2013 return Tmp; 2014 } else { 2015 assert(0 && "Target Must Lower this"); 2016 } 2017 } 2018 } 2019 2020 Tmp1 = LegalizeOp(Node->getOperand(0)); 2021 if (Tmp1 != Node->getOperand(0)) 2022 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2023 break; 2024 case Expand: 2025 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2026 Node->getValueType(0), Node->getOperand(0)); 2027 break; 2028 case Promote: 2029 if (isSigned) { 2030 Result = PromoteOp(Node->getOperand(0)); 2031 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2032 Result, DAG.getValueType(Node->getOperand(0).getValueType())); 2033 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 2034 } else { 2035 Result = PromoteOp(Node->getOperand(0)); 2036 Result = DAG.getZeroExtendInReg(Result, 2037 Node->getOperand(0).getValueType()); 2038 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 2039 } 2040 break; 2041 } 2042 break; 2043 } 2044 case ISD::TRUNCATE: 2045 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2046 case Legal: 2047 Tmp1 = LegalizeOp(Node->getOperand(0)); 2048 if (Tmp1 != Node->getOperand(0)) 2049 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2050 break; 2051 case Expand: 2052 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2053 2054 // Since the result is legal, we should just be able to truncate the low 2055 // part of the source. 2056 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2057 break; 2058 case Promote: 2059 Result = PromoteOp(Node->getOperand(0)); 2060 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2061 break; 2062 } 2063 break; 2064 2065 case ISD::FP_TO_SINT: 2066 case ISD::FP_TO_UINT: 2067 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2068 case Legal: 2069 Tmp1 = LegalizeOp(Node->getOperand(0)); 2070 2071 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2072 default: assert(0 && "Unknown operation action!"); 2073 case TargetLowering::Expand: 2074 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2075 SDOperand True, False; 2076 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2077 MVT::ValueType NVT = Node->getValueType(0); 2078 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2079 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2080 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2081 Node->getOperand(0), Tmp2, ISD::SETLT); 2082 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2083 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2084 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2085 Tmp2)); 2086 False = DAG.getNode(ISD::XOR, NVT, False, 2087 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2088 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False)); 2089 return Result; 2090 } else { 2091 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2092 } 2093 break; 2094 case TargetLowering::Promote: 2095 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2096 Node->getOpcode() == ISD::FP_TO_SINT); 2097 AddLegalizedOperand(Op, Result); 2098 return Result; 2099 case TargetLowering::Custom: { 2100 SDOperand Tmp = 2101 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2102 Tmp = TLI.LowerOperation(Tmp, DAG); 2103 if (Tmp.Val) { 2104 AddLegalizedOperand(Op, Tmp); 2105 NeedsAnotherIteration = true; 2106 return Tmp; 2107 } else { 2108 // The target thinks this is legal afterall. 2109 break; 2110 } 2111 } 2112 case TargetLowering::Legal: 2113 break; 2114 } 2115 2116 if (Tmp1 != Node->getOperand(0)) 2117 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2118 break; 2119 case Expand: 2120 assert(0 && "Shouldn't need to expand other operators here!"); 2121 case Promote: 2122 Result = PromoteOp(Node->getOperand(0)); 2123 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2124 break; 2125 } 2126 break; 2127 2128 case ISD::ANY_EXTEND: 2129 case ISD::ZERO_EXTEND: 2130 case ISD::SIGN_EXTEND: 2131 case ISD::FP_EXTEND: 2132 case ISD::FP_ROUND: 2133 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2134 case Legal: 2135 Tmp1 = LegalizeOp(Node->getOperand(0)); 2136 if (Tmp1 != Node->getOperand(0)) 2137 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2138 break; 2139 case Expand: 2140 assert(0 && "Shouldn't need to expand other operators here!"); 2141 2142 case Promote: 2143 switch (Node->getOpcode()) { 2144 case ISD::ANY_EXTEND: 2145 Result = PromoteOp(Node->getOperand(0)); 2146 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2147 break; 2148 case ISD::ZERO_EXTEND: 2149 Result = PromoteOp(Node->getOperand(0)); 2150 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2151 Result = DAG.getZeroExtendInReg(Result, 2152 Node->getOperand(0).getValueType()); 2153 break; 2154 case ISD::SIGN_EXTEND: 2155 Result = PromoteOp(Node->getOperand(0)); 2156 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2157 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2158 Result, 2159 DAG.getValueType(Node->getOperand(0).getValueType())); 2160 break; 2161 case ISD::FP_EXTEND: 2162 Result = PromoteOp(Node->getOperand(0)); 2163 if (Result.getValueType() != Op.getValueType()) 2164 // Dynamically dead while we have only 2 FP types. 2165 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2166 break; 2167 case ISD::FP_ROUND: 2168 Result = PromoteOp(Node->getOperand(0)); 2169 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2170 break; 2171 } 2172 } 2173 break; 2174 case ISD::FP_ROUND_INREG: 2175 case ISD::SIGN_EXTEND_INREG: { 2176 Tmp1 = LegalizeOp(Node->getOperand(0)); 2177 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2178 2179 // If this operation is not supported, convert it to a shl/shr or load/store 2180 // pair. 2181 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2182 default: assert(0 && "This action not supported for this op yet!"); 2183 case TargetLowering::Legal: 2184 if (Tmp1 != Node->getOperand(0)) 2185 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2186 DAG.getValueType(ExtraVT)); 2187 break; 2188 case TargetLowering::Expand: 2189 // If this is an integer extend and shifts are supported, do that. 2190 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2191 // NOTE: we could fall back on load/store here too for targets without 2192 // SAR. However, it is doubtful that any exist. 2193 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2194 MVT::getSizeInBits(ExtraVT); 2195 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2196 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2197 Node->getOperand(0), ShiftCst); 2198 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2199 Result, ShiftCst); 2200 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2201 // The only way we can lower this is to turn it into a STORETRUNC, 2202 // EXTLOAD pair, targetting a temporary location (a stack slot). 2203 2204 // NOTE: there is a choice here between constantly creating new stack 2205 // slots and always reusing the same one. We currently always create 2206 // new ones, as reuse may inhibit scheduling. 2207 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2208 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2209 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2210 MachineFunction &MF = DAG.getMachineFunction(); 2211 int SSFI = 2212 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2213 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2214 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2215 Node->getOperand(0), StackSlot, 2216 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2217 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2218 Result, StackSlot, DAG.getSrcValue(NULL), 2219 ExtraVT); 2220 } else { 2221 assert(0 && "Unknown op"); 2222 } 2223 Result = LegalizeOp(Result); 2224 break; 2225 } 2226 break; 2227 } 2228 } 2229 2230 // Note that LegalizeOp may be reentered even from single-use nodes, which 2231 // means that we always must cache transformed nodes. 2232 AddLegalizedOperand(Op, Result); 2233 return Result; 2234} 2235 2236/// PromoteOp - Given an operation that produces a value in an invalid type, 2237/// promote it to compute the value into a larger type. The produced value will 2238/// have the correct bits for the low portion of the register, but no guarantee 2239/// is made about the top bits: it may be zero, sign-extended, or garbage. 2240SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2241 MVT::ValueType VT = Op.getValueType(); 2242 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2243 assert(getTypeAction(VT) == Promote && 2244 "Caller should expand or legalize operands that are not promotable!"); 2245 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2246 "Cannot promote to smaller type!"); 2247 2248 SDOperand Tmp1, Tmp2, Tmp3; 2249 2250 SDOperand Result; 2251 SDNode *Node = Op.Val; 2252 2253 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2254 if (I != PromotedNodes.end()) return I->second; 2255 2256 // Promotion needs an optimization step to clean up after it, and is not 2257 // careful to avoid operations the target does not support. Make sure that 2258 // all generated operations are legalized in the next iteration. 2259 NeedsAnotherIteration = true; 2260 2261 switch (Node->getOpcode()) { 2262 case ISD::CopyFromReg: 2263 assert(0 && "CopyFromReg must be legal!"); 2264 default: 2265 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2266 assert(0 && "Do not know how to promote this operator!"); 2267 abort(); 2268 case ISD::UNDEF: 2269 Result = DAG.getNode(ISD::UNDEF, NVT); 2270 break; 2271 case ISD::Constant: 2272 if (VT != MVT::i1) 2273 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2274 else 2275 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2276 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2277 break; 2278 case ISD::ConstantFP: 2279 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2280 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2281 break; 2282 2283 case ISD::SETCC: 2284 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2285 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2286 Node->getOperand(1), Node->getOperand(2)); 2287 Result = LegalizeOp(Result); 2288 break; 2289 2290 case ISD::TRUNCATE: 2291 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2292 case Legal: 2293 Result = LegalizeOp(Node->getOperand(0)); 2294 assert(Result.getValueType() >= NVT && 2295 "This truncation doesn't make sense!"); 2296 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2297 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2298 break; 2299 case Promote: 2300 // The truncation is not required, because we don't guarantee anything 2301 // about high bits anyway. 2302 Result = PromoteOp(Node->getOperand(0)); 2303 break; 2304 case Expand: 2305 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2306 // Truncate the low part of the expanded value to the result type 2307 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2308 } 2309 break; 2310 case ISD::SIGN_EXTEND: 2311 case ISD::ZERO_EXTEND: 2312 case ISD::ANY_EXTEND: 2313 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2314 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2315 case Legal: 2316 // Input is legal? Just do extend all the way to the larger type. 2317 Result = LegalizeOp(Node->getOperand(0)); 2318 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2319 break; 2320 case Promote: 2321 // Promote the reg if it's smaller. 2322 Result = PromoteOp(Node->getOperand(0)); 2323 // The high bits are not guaranteed to be anything. Insert an extend. 2324 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2325 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2326 DAG.getValueType(Node->getOperand(0).getValueType())); 2327 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2328 Result = DAG.getZeroExtendInReg(Result, 2329 Node->getOperand(0).getValueType()); 2330 break; 2331 } 2332 break; 2333 2334 case ISD::FP_EXTEND: 2335 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2336 case ISD::FP_ROUND: 2337 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2338 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2339 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2340 case Legal: 2341 // Input is legal? Do an FP_ROUND_INREG. 2342 Result = LegalizeOp(Node->getOperand(0)); 2343 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2344 DAG.getValueType(VT)); 2345 break; 2346 } 2347 break; 2348 2349 case ISD::SINT_TO_FP: 2350 case ISD::UINT_TO_FP: 2351 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2352 case Legal: 2353 Result = LegalizeOp(Node->getOperand(0)); 2354 // No extra round required here. 2355 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2356 break; 2357 2358 case Promote: 2359 Result = PromoteOp(Node->getOperand(0)); 2360 if (Node->getOpcode() == ISD::SINT_TO_FP) 2361 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2362 Result, 2363 DAG.getValueType(Node->getOperand(0).getValueType())); 2364 else 2365 Result = DAG.getZeroExtendInReg(Result, 2366 Node->getOperand(0).getValueType()); 2367 // No extra round required here. 2368 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2369 break; 2370 case Expand: 2371 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2372 Node->getOperand(0)); 2373 // Round if we cannot tolerate excess precision. 2374 if (NoExcessFPPrecision) 2375 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2376 DAG.getValueType(VT)); 2377 break; 2378 } 2379 break; 2380 2381 case ISD::FP_TO_SINT: 2382 case ISD::FP_TO_UINT: 2383 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2384 case Legal: 2385 Tmp1 = LegalizeOp(Node->getOperand(0)); 2386 break; 2387 case Promote: 2388 // The input result is prerounded, so we don't have to do anything 2389 // special. 2390 Tmp1 = PromoteOp(Node->getOperand(0)); 2391 break; 2392 case Expand: 2393 assert(0 && "not implemented"); 2394 } 2395 // If we're promoting a UINT to a larger size, check to see if the new node 2396 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2397 // we can use that instead. This allows us to generate better code for 2398 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2399 // legal, such as PowerPC. 2400 if (Node->getOpcode() == ISD::FP_TO_UINT && 2401 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2402 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2403 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2404 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2405 } else { 2406 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2407 } 2408 break; 2409 2410 case ISD::FABS: 2411 case ISD::FNEG: 2412 Tmp1 = PromoteOp(Node->getOperand(0)); 2413 assert(Tmp1.getValueType() == NVT); 2414 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2415 // NOTE: we do not have to do any extra rounding here for 2416 // NoExcessFPPrecision, because we know the input will have the appropriate 2417 // precision, and these operations don't modify precision at all. 2418 break; 2419 2420 case ISD::FSQRT: 2421 case ISD::FSIN: 2422 case ISD::FCOS: 2423 Tmp1 = PromoteOp(Node->getOperand(0)); 2424 assert(Tmp1.getValueType() == NVT); 2425 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2426 if(NoExcessFPPrecision) 2427 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2428 DAG.getValueType(VT)); 2429 break; 2430 2431 case ISD::AND: 2432 case ISD::OR: 2433 case ISD::XOR: 2434 case ISD::ADD: 2435 case ISD::SUB: 2436 case ISD::MUL: 2437 // The input may have strange things in the top bits of the registers, but 2438 // these operations don't care. They may have weird bits going out, but 2439 // that too is okay if they are integer operations. 2440 Tmp1 = PromoteOp(Node->getOperand(0)); 2441 Tmp2 = PromoteOp(Node->getOperand(1)); 2442 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2443 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2444 break; 2445 case ISD::FADD: 2446 case ISD::FSUB: 2447 case ISD::FMUL: 2448 // The input may have strange things in the top bits of the registers, but 2449 // these operations don't care. 2450 Tmp1 = PromoteOp(Node->getOperand(0)); 2451 Tmp2 = PromoteOp(Node->getOperand(1)); 2452 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2453 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2454 2455 // Floating point operations will give excess precision that we may not be 2456 // able to tolerate. If we DO allow excess precision, just leave it, 2457 // otherwise excise it. 2458 // FIXME: Why would we need to round FP ops more than integer ones? 2459 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2460 if (NoExcessFPPrecision) 2461 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2462 DAG.getValueType(VT)); 2463 break; 2464 2465 case ISD::SDIV: 2466 case ISD::SREM: 2467 // These operators require that their input be sign extended. 2468 Tmp1 = PromoteOp(Node->getOperand(0)); 2469 Tmp2 = PromoteOp(Node->getOperand(1)); 2470 if (MVT::isInteger(NVT)) { 2471 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2472 DAG.getValueType(VT)); 2473 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2474 DAG.getValueType(VT)); 2475 } 2476 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2477 2478 // Perform FP_ROUND: this is probably overly pessimistic. 2479 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2480 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2481 DAG.getValueType(VT)); 2482 break; 2483 case ISD::FDIV: 2484 case ISD::FREM: 2485 // These operators require that their input be fp extended. 2486 Tmp1 = PromoteOp(Node->getOperand(0)); 2487 Tmp2 = PromoteOp(Node->getOperand(1)); 2488 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2489 2490 // Perform FP_ROUND: this is probably overly pessimistic. 2491 if (NoExcessFPPrecision) 2492 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2493 DAG.getValueType(VT)); 2494 break; 2495 2496 case ISD::UDIV: 2497 case ISD::UREM: 2498 // These operators require that their input be zero extended. 2499 Tmp1 = PromoteOp(Node->getOperand(0)); 2500 Tmp2 = PromoteOp(Node->getOperand(1)); 2501 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2502 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2503 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2504 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2505 break; 2506 2507 case ISD::SHL: 2508 Tmp1 = PromoteOp(Node->getOperand(0)); 2509 Tmp2 = LegalizeOp(Node->getOperand(1)); 2510 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 2511 break; 2512 case ISD::SRA: 2513 // The input value must be properly sign extended. 2514 Tmp1 = PromoteOp(Node->getOperand(0)); 2515 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2516 DAG.getValueType(VT)); 2517 Tmp2 = LegalizeOp(Node->getOperand(1)); 2518 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 2519 break; 2520 case ISD::SRL: 2521 // The input value must be properly zero extended. 2522 Tmp1 = PromoteOp(Node->getOperand(0)); 2523 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2524 Tmp2 = LegalizeOp(Node->getOperand(1)); 2525 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 2526 break; 2527 case ISD::LOAD: 2528 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2529 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2530 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2, 2531 Node->getOperand(2), VT); 2532 // Remember that we legalized the chain. 2533 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2534 break; 2535 case ISD::SEXTLOAD: 2536 case ISD::ZEXTLOAD: 2537 case ISD::EXTLOAD: 2538 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2539 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2540 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2, 2541 Node->getOperand(2), 2542 cast<VTSDNode>(Node->getOperand(3))->getVT()); 2543 // Remember that we legalized the chain. 2544 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2545 break; 2546 case ISD::SELECT: 2547 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2548 case Expand: assert(0 && "It's impossible to expand bools"); 2549 case Legal: 2550 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 2551 break; 2552 case Promote: 2553 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2554 break; 2555 } 2556 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 2557 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 2558 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 2559 break; 2560 case ISD::SELECT_CC: 2561 Tmp2 = PromoteOp(Node->getOperand(2)); // True 2562 Tmp3 = PromoteOp(Node->getOperand(3)); // False 2563 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 2564 Node->getOperand(1), Tmp2, Tmp3, 2565 Node->getOperand(4)); 2566 break; 2567 case ISD::TAILCALL: 2568 case ISD::CALL: { 2569 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2570 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 2571 2572 std::vector<SDOperand> Ops; 2573 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 2574 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2575 2576 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 2577 "Can only promote single result calls"); 2578 std::vector<MVT::ValueType> RetTyVTs; 2579 RetTyVTs.reserve(2); 2580 RetTyVTs.push_back(NVT); 2581 RetTyVTs.push_back(MVT::Other); 2582 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 2583 Node->getOpcode() == ISD::TAILCALL); 2584 Result = SDOperand(NC, 0); 2585 2586 // Insert the new chain mapping. 2587 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2588 break; 2589 } 2590 case ISD::CTPOP: 2591 case ISD::CTTZ: 2592 case ISD::CTLZ: 2593 Tmp1 = Node->getOperand(0); 2594 //Zero extend the argument 2595 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2596 // Perform the larger operation, then subtract if needed. 2597 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2598 switch(Node->getOpcode()) 2599 { 2600 case ISD::CTPOP: 2601 Result = Tmp1; 2602 break; 2603 case ISD::CTTZ: 2604 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2605 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2606 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 2607 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2608 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 2609 break; 2610 case ISD::CTLZ: 2611 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2612 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2613 DAG.getConstant(getSizeInBits(NVT) - 2614 getSizeInBits(VT), NVT)); 2615 break; 2616 } 2617 break; 2618 } 2619 2620 assert(Result.Val && "Didn't set a result!"); 2621 AddPromotedOperand(Op, Result); 2622 return Result; 2623} 2624 2625/// ExpandAddSub - Find a clever way to expand this add operation into 2626/// subcomponents. 2627void SelectionDAGLegalize:: 2628ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 2629 SDOperand &Lo, SDOperand &Hi) { 2630 // Expand the subcomponents. 2631 SDOperand LHSL, LHSH, RHSL, RHSH; 2632 ExpandOp(LHS, LHSL, LHSH); 2633 ExpandOp(RHS, RHSL, RHSH); 2634 2635 std::vector<SDOperand> Ops; 2636 Ops.push_back(LHSL); 2637 Ops.push_back(LHSH); 2638 Ops.push_back(RHSL); 2639 Ops.push_back(RHSH); 2640 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2641 Lo = DAG.getNode(NodeOp, VTs, Ops); 2642 Hi = Lo.getValue(1); 2643} 2644 2645void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 2646 SDOperand Op, SDOperand Amt, 2647 SDOperand &Lo, SDOperand &Hi) { 2648 // Expand the subcomponents. 2649 SDOperand LHSL, LHSH; 2650 ExpandOp(Op, LHSL, LHSH); 2651 2652 std::vector<SDOperand> Ops; 2653 Ops.push_back(LHSL); 2654 Ops.push_back(LHSH); 2655 Ops.push_back(Amt); 2656 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2657 Lo = DAG.getNode(NodeOp, VTs, Ops); 2658 Hi = Lo.getValue(1); 2659} 2660 2661 2662/// ExpandShift - Try to find a clever way to expand this shift operation out to 2663/// smaller elements. If we can't find a way that is more efficient than a 2664/// libcall on this target, return false. Otherwise, return true with the 2665/// low-parts expanded into Lo and Hi. 2666bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 2667 SDOperand &Lo, SDOperand &Hi) { 2668 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 2669 "This is not a shift!"); 2670 2671 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 2672 SDOperand ShAmt = LegalizeOp(Amt); 2673 MVT::ValueType ShTy = ShAmt.getValueType(); 2674 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 2675 unsigned NVTBits = MVT::getSizeInBits(NVT); 2676 2677 // Handle the case when Amt is an immediate. Other cases are currently broken 2678 // and are disabled. 2679 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 2680 unsigned Cst = CN->getValue(); 2681 // Expand the incoming operand to be shifted, so that we have its parts 2682 SDOperand InL, InH; 2683 ExpandOp(Op, InL, InH); 2684 switch(Opc) { 2685 case ISD::SHL: 2686 if (Cst > VTBits) { 2687 Lo = DAG.getConstant(0, NVT); 2688 Hi = DAG.getConstant(0, NVT); 2689 } else if (Cst > NVTBits) { 2690 Lo = DAG.getConstant(0, NVT); 2691 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 2692 } else if (Cst == NVTBits) { 2693 Lo = DAG.getConstant(0, NVT); 2694 Hi = InL; 2695 } else { 2696 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 2697 Hi = DAG.getNode(ISD::OR, NVT, 2698 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 2699 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 2700 } 2701 return true; 2702 case ISD::SRL: 2703 if (Cst > VTBits) { 2704 Lo = DAG.getConstant(0, NVT); 2705 Hi = DAG.getConstant(0, NVT); 2706 } else if (Cst > NVTBits) { 2707 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 2708 Hi = DAG.getConstant(0, NVT); 2709 } else if (Cst == NVTBits) { 2710 Lo = InH; 2711 Hi = DAG.getConstant(0, NVT); 2712 } else { 2713 Lo = DAG.getNode(ISD::OR, NVT, 2714 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2715 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2716 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 2717 } 2718 return true; 2719 case ISD::SRA: 2720 if (Cst > VTBits) { 2721 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 2722 DAG.getConstant(NVTBits-1, ShTy)); 2723 } else if (Cst > NVTBits) { 2724 Lo = DAG.getNode(ISD::SRA, NVT, InH, 2725 DAG.getConstant(Cst-NVTBits, ShTy)); 2726 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2727 DAG.getConstant(NVTBits-1, ShTy)); 2728 } else if (Cst == NVTBits) { 2729 Lo = InH; 2730 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2731 DAG.getConstant(NVTBits-1, ShTy)); 2732 } else { 2733 Lo = DAG.getNode(ISD::OR, NVT, 2734 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2735 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2736 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 2737 } 2738 return true; 2739 } 2740 } 2741 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 2742 // so disable it for now. Currently targets are handling this via SHL_PARTS 2743 // and friends. 2744 return false; 2745 2746 // If we have an efficient select operation (or if the selects will all fold 2747 // away), lower to some complex code, otherwise just emit the libcall. 2748 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt)) 2749 return false; 2750 2751 SDOperand InL, InH; 2752 ExpandOp(Op, InL, InH); 2753 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 2754 DAG.getConstant(NVTBits, ShTy), ShAmt); 2755 2756 // Compare the unmasked shift amount against 32. 2757 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt, 2758 DAG.getConstant(NVTBits, ShTy), ISD::SETGE); 2759 2760 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 2761 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 2762 DAG.getConstant(NVTBits-1, ShTy)); 2763 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 2764 DAG.getConstant(NVTBits-1, ShTy)); 2765 } 2766 2767 if (Opc == ISD::SHL) { 2768 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 2769 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 2770 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 2771 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 2772 2773 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2774 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 2775 } else { 2776 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 2777 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt, 2778 DAG.getConstant(32, ShTy), 2779 ISD::SETEQ), 2780 DAG.getConstant(0, NVT), 2781 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 2782 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 2783 HiLoPart, 2784 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 2785 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 2786 2787 SDOperand HiPart; 2788 if (Opc == ISD::SRA) 2789 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 2790 DAG.getConstant(NVTBits-1, ShTy)); 2791 else 2792 HiPart = DAG.getConstant(0, NVT); 2793 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2794 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 2795 } 2796 return true; 2797} 2798 2799/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 2800/// NodeDepth) node that is an CallSeqStart operation and occurs later than 2801/// Found. 2802static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) { 2803 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 2804 2805 // If we found an CALLSEQ_START, we already know this node occurs later 2806 // than the Found node. Just remember this node and return. 2807 if (Node->getOpcode() == ISD::CALLSEQ_START) { 2808 Found = Node; 2809 return; 2810 } 2811 2812 // Otherwise, scan the operands of Node to see if any of them is a call. 2813 assert(Node->getNumOperands() != 0 && 2814 "All leaves should have depth equal to the entry node!"); 2815 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 2816 FindLatestCallSeqStart(Node->getOperand(i).Val, Found); 2817 2818 // Tail recurse for the last iteration. 2819 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 2820 Found); 2821} 2822 2823 2824/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 2825/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 2826/// than Found. 2827static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 2828 std::set<SDNode*> &Visited) { 2829 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 2830 !Visited.insert(Node).second) return; 2831 2832 // If we found an CALLSEQ_END, we already know this node occurs earlier 2833 // than the Found node. Just remember this node and return. 2834 if (Node->getOpcode() == ISD::CALLSEQ_END) { 2835 Found = Node; 2836 return; 2837 } 2838 2839 // Otherwise, scan the operands of Node to see if any of them is a call. 2840 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 2841 if (UI == E) return; 2842 for (--E; UI != E; ++UI) 2843 FindEarliestCallSeqEnd(*UI, Found, Visited); 2844 2845 // Tail recurse for the last iteration. 2846 FindEarliestCallSeqEnd(*UI, Found, Visited); 2847} 2848 2849/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 2850/// find the CALLSEQ_END node that terminates the call sequence. 2851static SDNode *FindCallSeqEnd(SDNode *Node) { 2852 if (Node->getOpcode() == ISD::CALLSEQ_END) 2853 return Node; 2854 if (Node->use_empty()) 2855 return 0; // No CallSeqEnd 2856 2857 SDOperand TheChain(Node, Node->getNumValues()-1); 2858 if (TheChain.getValueType() != MVT::Other) 2859 TheChain = SDOperand(Node, 0); 2860 if (TheChain.getValueType() != MVT::Other) 2861 return 0; 2862 2863 for (SDNode::use_iterator UI = Node->use_begin(), 2864 E = Node->use_end(); UI != E; ++UI) { 2865 2866 // Make sure to only follow users of our token chain. 2867 SDNode *User = *UI; 2868 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 2869 if (User->getOperand(i) == TheChain) 2870 if (SDNode *Result = FindCallSeqEnd(User)) 2871 return Result; 2872 } 2873 return 0; 2874} 2875 2876/// FindCallSeqStart - Given a chained node that is part of a call sequence, 2877/// find the CALLSEQ_START node that initiates the call sequence. 2878static SDNode *FindCallSeqStart(SDNode *Node) { 2879 assert(Node && "Didn't find callseq_start for a call??"); 2880 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 2881 2882 assert(Node->getOperand(0).getValueType() == MVT::Other && 2883 "Node doesn't have a token chain argument!"); 2884 return FindCallSeqStart(Node->getOperand(0).Val); 2885} 2886 2887 2888/// FindInputOutputChains - If we are replacing an operation with a call we need 2889/// to find the call that occurs before and the call that occurs after it to 2890/// properly serialize the calls in the block. The returned operand is the 2891/// input chain value for the new call (e.g. the entry node or the previous 2892/// call), and OutChain is set to be the chain node to update to point to the 2893/// end of the call chain. 2894static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 2895 SDOperand Entry) { 2896 SDNode *LatestCallSeqStart = Entry.Val; 2897 SDNode *LatestCallSeqEnd = 0; 2898 FindLatestCallSeqStart(OpNode, LatestCallSeqStart); 2899 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 2900 2901 // It is possible that no ISD::CALLSEQ_START was found because there is no 2902 // previous call in the function. LatestCallStackDown may in that case be 2903 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 2904 // unless LatestCallStackDown is an CALLSEQ_START. 2905 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 2906 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 2907 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 2908 } else { 2909 LatestCallSeqEnd = Entry.Val; 2910 } 2911 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 2912 2913 // Finally, find the first call that this must come before, first we find the 2914 // CallSeqEnd that ends the call. 2915 OutChain = 0; 2916 std::set<SDNode*> Visited; 2917 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 2918 2919 // If we found one, translate from the adj up to the callseq_start. 2920 if (OutChain) 2921 OutChain = FindCallSeqStart(OutChain); 2922 2923 return SDOperand(LatestCallSeqEnd, 0); 2924} 2925 2926/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 2927void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 2928 SDNode *OutChain) { 2929 // Nothing to splice it into? 2930 if (OutChain == 0) return; 2931 2932 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 2933 //OutChain->dump(); 2934 2935 // Form a token factor node merging the old inval and the new inval. 2936 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 2937 OutChain->getOperand(0)); 2938 // Change the node to refer to the new token. 2939 OutChain->setAdjCallChain(InToken); 2940} 2941 2942 2943// ExpandLibCall - Expand a node into a call to a libcall. If the result value 2944// does not fit into a register, return the lo part and set the hi part to the 2945// by-reg argument. If it does fit into a single register, return the result 2946// and leave the Hi part unset. 2947SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 2948 SDOperand &Hi) { 2949 SDNode *OutChain; 2950 SDOperand InChain = FindInputOutputChains(Node, OutChain, 2951 DAG.getEntryNode()); 2952 if (InChain.Val == 0) 2953 InChain = DAG.getEntryNode(); 2954 2955 TargetLowering::ArgListTy Args; 2956 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2957 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 2958 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 2959 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 2960 } 2961 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 2962 2963 // Splice the libcall in wherever FindInputOutputChains tells us to. 2964 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 2965 std::pair<SDOperand,SDOperand> CallInfo = 2966 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 2967 Callee, Args, DAG); 2968 2969 SDOperand Result; 2970 switch (getTypeAction(CallInfo.first.getValueType())) { 2971 default: assert(0 && "Unknown thing"); 2972 case Legal: 2973 Result = CallInfo.first; 2974 break; 2975 case Promote: 2976 assert(0 && "Cannot promote this yet!"); 2977 case Expand: 2978 ExpandOp(CallInfo.first, Result, Hi); 2979 CallInfo.second = LegalizeOp(CallInfo.second); 2980 break; 2981 } 2982 2983 SpliceCallInto(CallInfo.second, OutChain); 2984 NeedsAnotherIteration = true; 2985 return Result; 2986} 2987 2988 2989/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 2990/// destination type is legal. 2991SDOperand SelectionDAGLegalize:: 2992ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 2993 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 2994 assert(getTypeAction(Source.getValueType()) == Expand && 2995 "This is not an expansion!"); 2996 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 2997 2998 if (!isSigned) { 2999 assert(Source.getValueType() == MVT::i64 && 3000 "This only works for 64-bit -> FP"); 3001 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 3002 // incoming integer is set. To handle this, we dynamically test to see if 3003 // it is set, and, if so, add a fudge factor. 3004 SDOperand Lo, Hi; 3005 ExpandOp(Source, Lo, Hi); 3006 3007 // If this is unsigned, and not supported, first perform the conversion to 3008 // signed, then adjust the result if the sign bit is set. 3009 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 3010 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 3011 3012 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 3013 DAG.getConstant(0, Hi.getValueType()), 3014 ISD::SETLT); 3015 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3016 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3017 SignSet, Four, Zero); 3018 uint64_t FF = 0x5f800000ULL; 3019 if (TLI.isLittleEndian()) FF <<= 32; 3020 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3021 3022 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3023 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3024 SDOperand FudgeInReg; 3025 if (DestTy == MVT::f32) 3026 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3027 DAG.getSrcValue(NULL)); 3028 else { 3029 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3030 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3031 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 3032 } 3033 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3034 } 3035 3036 // Check to see if the target has a custom way to lower this. If so, use it. 3037 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3038 default: assert(0 && "This action not implemented for this operation!"); 3039 case TargetLowering::Legal: 3040 case TargetLowering::Expand: 3041 break; // This case is handled below. 3042 case TargetLowering::Custom: { 3043 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3044 Source), DAG); 3045 if (NV.Val) 3046 return LegalizeOp(NV); 3047 break; // The target decided this was legal after all 3048 } 3049 } 3050 3051 // Expand the source, then glue it back together for the call. We must expand 3052 // the source in case it is shared (this pass of legalize must traverse it). 3053 SDOperand SrcLo, SrcHi; 3054 ExpandOp(Source, SrcLo, SrcHi); 3055 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3056 3057 SDNode *OutChain = 0; 3058 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 3059 DAG.getEntryNode()); 3060 const char *FnName = 0; 3061 if (DestTy == MVT::f32) 3062 FnName = "__floatdisf"; 3063 else { 3064 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3065 FnName = "__floatdidf"; 3066 } 3067 3068 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 3069 3070 TargetLowering::ArgListTy Args; 3071 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 3072 3073 Args.push_back(std::make_pair(Source, ArgTy)); 3074 3075 // We don't care about token chains for libcalls. We just use the entry 3076 // node as our input and ignore the output chain. This allows us to place 3077 // calls wherever we need them to satisfy data dependences. 3078 const Type *RetTy = MVT::getTypeForValueType(DestTy); 3079 3080 std::pair<SDOperand,SDOperand> CallResult = 3081 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 3082 Callee, Args, DAG); 3083 3084 SpliceCallInto(CallResult.second, OutChain); 3085 return CallResult.first; 3086} 3087 3088 3089 3090/// ExpandOp - Expand the specified SDOperand into its two component pieces 3091/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 3092/// LegalizeNodes map is filled in for any results that are not expanded, the 3093/// ExpandedNodes map is filled in for any results that are expanded, and the 3094/// Lo/Hi values are returned. 3095void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 3096 MVT::ValueType VT = Op.getValueType(); 3097 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3098 SDNode *Node = Op.Val; 3099 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 3100 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 3101 "Cannot expand FP values!"); 3102 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 3103 "Cannot expand to FP value or to larger int value!"); 3104 3105 // See if we already expanded it. 3106 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 3107 = ExpandedNodes.find(Op); 3108 if (I != ExpandedNodes.end()) { 3109 Lo = I->second.first; 3110 Hi = I->second.second; 3111 return; 3112 } 3113 3114 // Expanding to multiple registers needs to perform an optimization step, and 3115 // is not careful to avoid operations the target does not support. Make sure 3116 // that all generated operations are legalized in the next iteration. 3117 NeedsAnotherIteration = true; 3118 3119 switch (Node->getOpcode()) { 3120 case ISD::CopyFromReg: 3121 assert(0 && "CopyFromReg must be legal!"); 3122 default: 3123 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 3124 assert(0 && "Do not know how to expand this operator!"); 3125 abort(); 3126 case ISD::UNDEF: 3127 Lo = DAG.getNode(ISD::UNDEF, NVT); 3128 Hi = DAG.getNode(ISD::UNDEF, NVT); 3129 break; 3130 case ISD::Constant: { 3131 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 3132 Lo = DAG.getConstant(Cst, NVT); 3133 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3134 break; 3135 } 3136 3137 case ISD::BUILD_PAIR: 3138 // Legalize both operands. FIXME: in the future we should handle the case 3139 // where the two elements are not legal. 3140 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 3141 Lo = LegalizeOp(Node->getOperand(0)); 3142 Hi = LegalizeOp(Node->getOperand(1)); 3143 break; 3144 3145 case ISD::CTPOP: 3146 ExpandOp(Node->getOperand(0), Lo, Hi); 3147 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3148 DAG.getNode(ISD::CTPOP, NVT, Lo), 3149 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3150 Hi = DAG.getConstant(0, NVT); 3151 break; 3152 3153 case ISD::CTLZ: { 3154 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3155 ExpandOp(Node->getOperand(0), Lo, Hi); 3156 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3157 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3158 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3159 ISD::SETNE); 3160 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3161 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3162 3163 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3164 Hi = DAG.getConstant(0, NVT); 3165 break; 3166 } 3167 3168 case ISD::CTTZ: { 3169 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3170 ExpandOp(Node->getOperand(0), Lo, Hi); 3171 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3172 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3173 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3174 ISD::SETNE); 3175 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3176 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3177 3178 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3179 Hi = DAG.getConstant(0, NVT); 3180 break; 3181 } 3182 3183 case ISD::LOAD: { 3184 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3185 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3186 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3187 3188 // Increment the pointer to the other half. 3189 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3190 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3191 getIntPtrConstant(IncrementSize)); 3192 //Is this safe? declaring that the two parts of the split load 3193 //are from the same instruction? 3194 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3195 3196 // Build a factor node to remember that this load is independent of the 3197 // other one. 3198 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3199 Hi.getValue(1)); 3200 3201 // Remember that we legalized the chain. 3202 AddLegalizedOperand(Op.getValue(1), TF); 3203 if (!TLI.isLittleEndian()) 3204 std::swap(Lo, Hi); 3205 break; 3206 } 3207 case ISD::VLOAD: { 3208 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3209 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3210 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3211 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3212 3213 // If we only have two elements, turn into a pair of scalar loads. 3214 // FIXME: handle case where a vector of two elements is fine, such as 3215 // 2 x double on SSE2. 3216 if (NumElements == 2) { 3217 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3218 // Increment the pointer to the other half. 3219 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8; 3220 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3221 getIntPtrConstant(IncrementSize)); 3222 //Is this safe? declaring that the two parts of the split load 3223 //are from the same instruction? 3224 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3225 } else { 3226 NumElements /= 2; // Split the vector in half 3227 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3228 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8; 3229 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3230 getIntPtrConstant(IncrementSize)); 3231 //Is this safe? declaring that the two parts of the split load 3232 //are from the same instruction? 3233 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3234 } 3235 3236 // Build a factor node to remember that this load is independent of the 3237 // other one. 3238 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3239 Hi.getValue(1)); 3240 3241 // Remember that we legalized the chain. 3242 AddLegalizedOperand(Op.getValue(1), TF); 3243 if (!TLI.isLittleEndian()) 3244 std::swap(Lo, Hi); 3245 break; 3246 } 3247 case ISD::VADD: 3248 case ISD::VSUB: 3249 case ISD::VMUL: { 3250 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3251 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3252 SDOperand LL, LH, RL, RH; 3253 3254 ExpandOp(Node->getOperand(0), LL, LH); 3255 ExpandOp(Node->getOperand(1), RL, RH); 3256 3257 // If we only have two elements, turn into a pair of scalar loads. 3258 // FIXME: handle case where a vector of two elements is fine, such as 3259 // 2 x double on SSE2. 3260 if (NumElements == 2) { 3261 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT); 3262 Lo = DAG.getNode(Opc, EVT, LL, RL); 3263 Hi = DAG.getNode(Opc, EVT, LH, RH); 3264 } else { 3265 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2), 3266 LL.getOperand(3)); 3267 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2), 3268 LH.getOperand(3)); 3269 } 3270 break; 3271 } 3272 case ISD::TAILCALL: 3273 case ISD::CALL: { 3274 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3275 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 3276 3277 bool Changed = false; 3278 std::vector<SDOperand> Ops; 3279 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 3280 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3281 Changed |= Ops.back() != Node->getOperand(i); 3282 } 3283 3284 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 3285 "Can only expand a call once so far, not i64 -> i16!"); 3286 3287 std::vector<MVT::ValueType> RetTyVTs; 3288 RetTyVTs.reserve(3); 3289 RetTyVTs.push_back(NVT); 3290 RetTyVTs.push_back(NVT); 3291 RetTyVTs.push_back(MVT::Other); 3292 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops, 3293 Node->getOpcode() == ISD::TAILCALL); 3294 Lo = SDOperand(NC, 0); 3295 Hi = SDOperand(NC, 1); 3296 3297 // Insert the new chain mapping. 3298 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 3299 break; 3300 } 3301 case ISD::AND: 3302 case ISD::OR: 3303 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 3304 SDOperand LL, LH, RL, RH; 3305 ExpandOp(Node->getOperand(0), LL, LH); 3306 ExpandOp(Node->getOperand(1), RL, RH); 3307 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 3308 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 3309 break; 3310 } 3311 case ISD::SELECT: { 3312 SDOperand C, LL, LH, RL, RH; 3313 3314 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3315 case Expand: assert(0 && "It's impossible to expand bools"); 3316 case Legal: 3317 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 3318 break; 3319 case Promote: 3320 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 3321 break; 3322 } 3323 ExpandOp(Node->getOperand(1), LL, LH); 3324 ExpandOp(Node->getOperand(2), RL, RH); 3325 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 3326 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 3327 break; 3328 } 3329 case ISD::SELECT_CC: { 3330 SDOperand TL, TH, FL, FH; 3331 ExpandOp(Node->getOperand(2), TL, TH); 3332 ExpandOp(Node->getOperand(3), FL, FH); 3333 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3334 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3335 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3336 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3337 Lo = LegalizeOp(Lo); 3338 Hi = LegalizeOp(Hi); 3339 break; 3340 } 3341 case ISD::SEXTLOAD: { 3342 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3343 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3344 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3345 3346 if (EVT == NVT) 3347 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3348 else 3349 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3350 EVT); 3351 3352 // Remember that we legalized the chain. 3353 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3354 3355 // The high part is obtained by SRA'ing all but one of the bits of the lo 3356 // part. 3357 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3358 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3359 TLI.getShiftAmountTy())); 3360 Lo = LegalizeOp(Lo); 3361 Hi = LegalizeOp(Hi); 3362 break; 3363 } 3364 case ISD::ZEXTLOAD: { 3365 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3366 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3367 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3368 3369 if (EVT == NVT) 3370 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3371 else 3372 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3373 EVT); 3374 3375 // Remember that we legalized the chain. 3376 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3377 3378 // The high part is just a zero. 3379 Hi = LegalizeOp(DAG.getConstant(0, NVT)); 3380 Lo = LegalizeOp(Lo); 3381 break; 3382 } 3383 case ISD::EXTLOAD: { 3384 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3385 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3386 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3387 3388 if (EVT == NVT) 3389 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3390 else 3391 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3392 EVT); 3393 3394 // Remember that we legalized the chain. 3395 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3396 3397 // The high part is undefined. 3398 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT)); 3399 Lo = LegalizeOp(Lo); 3400 break; 3401 } 3402 case ISD::ANY_EXTEND: { 3403 SDOperand In; 3404 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3405 case Expand: assert(0 && "expand-expand not implemented yet!"); 3406 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3407 case Promote: 3408 In = PromoteOp(Node->getOperand(0)); 3409 break; 3410 } 3411 3412 // The low part is any extension of the input (which degenerates to a copy). 3413 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In); 3414 // The high part is undefined. 3415 Hi = DAG.getNode(ISD::UNDEF, NVT); 3416 break; 3417 } 3418 case ISD::SIGN_EXTEND: { 3419 SDOperand In; 3420 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3421 case Expand: assert(0 && "expand-expand not implemented yet!"); 3422 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3423 case Promote: 3424 In = PromoteOp(Node->getOperand(0)); 3425 // Emit the appropriate sign_extend_inreg to get the value we want. 3426 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 3427 DAG.getValueType(Node->getOperand(0).getValueType())); 3428 break; 3429 } 3430 3431 // The low part is just a sign extension of the input (which degenerates to 3432 // a copy). 3433 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 3434 3435 // The high part is obtained by SRA'ing all but one of the bits of the lo 3436 // part. 3437 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3438 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3439 TLI.getShiftAmountTy())); 3440 break; 3441 } 3442 case ISD::ZERO_EXTEND: { 3443 SDOperand In; 3444 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3445 case Expand: assert(0 && "expand-expand not implemented yet!"); 3446 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3447 case Promote: 3448 In = PromoteOp(Node->getOperand(0)); 3449 // Emit the appropriate zero_extend_inreg to get the value we want. 3450 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 3451 break; 3452 } 3453 3454 // The low part is just a zero extension of the input (which degenerates to 3455 // a copy). 3456 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 3457 3458 // The high part is just a zero. 3459 Hi = DAG.getConstant(0, NVT); 3460 break; 3461 } 3462 3463 case ISD::READCYCLECOUNTER: { 3464 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 3465 TargetLowering::Custom && 3466 "Must custom expand ReadCycleCounter"); 3467 SDOperand T = TLI.LowerOperation(Op, DAG); 3468 assert(T.Val && "Node must be custom expanded!"); 3469 Lo = LegalizeOp(T.getValue(0)); 3470 Hi = LegalizeOp(T.getValue(1)); 3471 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 3472 LegalizeOp(T.getValue(2))); 3473 break; 3474 } 3475 3476 // These operators cannot be expanded directly, emit them as calls to 3477 // library functions. 3478 case ISD::FP_TO_SINT: 3479 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 3480 SDOperand Op; 3481 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3482 case Expand: assert(0 && "cannot expand FP!"); 3483 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3484 case Promote: Op = PromoteOp(Node->getOperand(0)); break; 3485 } 3486 3487 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 3488 3489 // Now that the custom expander is done, expand the result, which is still 3490 // VT. 3491 if (Op.Val) { 3492 ExpandOp(Op, Lo, Hi); 3493 break; 3494 } 3495 } 3496 3497 if (Node->getOperand(0).getValueType() == MVT::f32) 3498 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 3499 else 3500 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 3501 break; 3502 3503 case ISD::FP_TO_UINT: 3504 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 3505 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, 3506 LegalizeOp(Node->getOperand(0))); 3507 // Now that the custom expander is done, expand the result, which is still 3508 // VT. 3509 Op = TLI.LowerOperation(Op, DAG); 3510 if (Op.Val) { 3511 ExpandOp(Op, Lo, Hi); 3512 break; 3513 } 3514 } 3515 3516 if (Node->getOperand(0).getValueType() == MVT::f32) 3517 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 3518 else 3519 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 3520 break; 3521 3522 case ISD::SHL: 3523 // If the target wants custom lowering, do so. 3524 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 3525 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), 3526 LegalizeOp(Node->getOperand(1))); 3527 Op = TLI.LowerOperation(Op, DAG); 3528 if (Op.Val) { 3529 // Now that the custom expander is done, expand the result, which is 3530 // still VT. 3531 ExpandOp(Op, Lo, Hi); 3532 break; 3533 } 3534 } 3535 3536 // If we can emit an efficient shift operation, do so now. 3537 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3538 break; 3539 3540 // If this target supports SHL_PARTS, use it. 3541 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) { 3542 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 3543 Lo, Hi); 3544 break; 3545 } 3546 3547 // Otherwise, emit a libcall. 3548 Lo = ExpandLibCall("__ashldi3", Node, Hi); 3549 break; 3550 3551 case ISD::SRA: 3552 // If the target wants custom lowering, do so. 3553 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 3554 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), 3555 LegalizeOp(Node->getOperand(1))); 3556 Op = TLI.LowerOperation(Op, DAG); 3557 if (Op.Val) { 3558 // Now that the custom expander is done, expand the result, which is 3559 // still VT. 3560 ExpandOp(Op, Lo, Hi); 3561 break; 3562 } 3563 } 3564 3565 // If we can emit an efficient shift operation, do so now. 3566 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3567 break; 3568 3569 // If this target supports SRA_PARTS, use it. 3570 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) { 3571 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 3572 Lo, Hi); 3573 break; 3574 } 3575 3576 // Otherwise, emit a libcall. 3577 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 3578 break; 3579 case ISD::SRL: 3580 // If the target wants custom lowering, do so. 3581 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 3582 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), 3583 LegalizeOp(Node->getOperand(1))); 3584 Op = TLI.LowerOperation(Op, DAG); 3585 if (Op.Val) { 3586 // Now that the custom expander is done, expand the result, which is 3587 // still VT. 3588 ExpandOp(Op, Lo, Hi); 3589 break; 3590 } 3591 } 3592 3593 // If we can emit an efficient shift operation, do so now. 3594 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3595 break; 3596 3597 // If this target supports SRL_PARTS, use it. 3598 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) { 3599 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 3600 Lo, Hi); 3601 break; 3602 } 3603 3604 // Otherwise, emit a libcall. 3605 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 3606 break; 3607 3608 case ISD::ADD: 3609 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 3610 Lo, Hi); 3611 break; 3612 case ISD::SUB: 3613 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 3614 Lo, Hi); 3615 break; 3616 case ISD::MUL: { 3617 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 3618 SDOperand LL, LH, RL, RH; 3619 ExpandOp(Node->getOperand(0), LL, LH); 3620 ExpandOp(Node->getOperand(1), RL, RH); 3621 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 3622 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 3623 // extended the sign bit of the low half through the upper half, and if so 3624 // emit a MULHS instead of the alternate sequence that is valid for any 3625 // i64 x i64 multiply. 3626 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 3627 // is RH an extension of the sign bit of RL? 3628 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 3629 RH.getOperand(1).getOpcode() == ISD::Constant && 3630 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 3631 // is LH an extension of the sign bit of LL? 3632 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 3633 LH.getOperand(1).getOpcode() == ISD::Constant && 3634 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 3635 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 3636 } else { 3637 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 3638 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 3639 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 3640 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 3641 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 3642 } 3643 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 3644 } else { 3645 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 3646 } 3647 break; 3648 } 3649 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 3650 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 3651 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 3652 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 3653 } 3654 3655 // Remember in a map if the values will be reused later. 3656 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 3657 std::make_pair(Lo, Hi))).second; 3658 assert(isNew && "Value already expanded?!?"); 3659} 3660 3661 3662// SelectionDAG::Legalize - This is the entry point for the file. 3663// 3664void SelectionDAG::Legalize() { 3665 /// run - This is the main entry point to this class. 3666 /// 3667 SelectionDAGLegalize(*this).Run(); 3668} 3669 3670