LegalizeDAG.cpp revision ced9ff8ea2fac344da91d925294817ad51f51e06
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/DwarfWriter.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/CodeGen/PseudoSourceValue.h" 22#include "llvm/Target/TargetFrameInfo.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetData.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Target/TargetSubtarget.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/DerivedTypes.h" 31#include "llvm/Function.h" 32#include "llvm/GlobalVariable.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Compiler.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/ADT/DenseMap.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/SmallPtrSet.h" 40#include <map> 41using namespace llvm; 42 43//===----------------------------------------------------------------------===// 44/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 45/// hacks on it until the target machine can handle it. This involves 46/// eliminating value sizes the machine cannot handle (promoting small sizes to 47/// large sizes or splitting up large values into small values) as well as 48/// eliminating operations the machine cannot handle. 49/// 50/// This code also does a small amount of optimization and recognition of idioms 51/// as part of its processing. For example, if a target does not support a 52/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 53/// will attempt merge setcc and brc instructions into brcc's. 54/// 55namespace { 56class VISIBILITY_HIDDEN SelectionDAGLegalize { 57 TargetLowering &TLI; 58 SelectionDAG &DAG; 59 CodeGenOpt::Level OptLevel; 60 61 // Libcall insertion helpers. 62 63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 64 /// legalized. We use this to ensure that calls are properly serialized 65 /// against each other, including inserted libcalls. 66 SDValue LastCALLSEQ_END; 67 68 /// IsLegalizingCall - This member is used *only* for purposes of providing 69 /// helpful assertions that a libcall isn't created while another call is 70 /// being legalized (which could lead to non-serialized call sequences). 71 bool IsLegalizingCall; 72 73 enum LegalizeAction { 74 Legal, // The target natively supports this operation. 75 Promote, // This operation should be executed in a larger type. 76 Expand // Try to expand this to other ops, otherwise use a libcall. 77 }; 78 79 /// ValueTypeActions - This is a bitvector that contains two bits for each 80 /// value type, where the two bits correspond to the LegalizeAction enum. 81 /// This can be queried with "getTypeAction(VT)". 82 TargetLowering::ValueTypeActionImpl ValueTypeActions; 83 84 /// LegalizedNodes - For nodes that are of legal width, and that have more 85 /// than one use, this map indicates what regularized operand to use. This 86 /// allows us to avoid legalizing the same thing more than once. 87 DenseMap<SDValue, SDValue> LegalizedNodes; 88 89 void AddLegalizedOperand(SDValue From, SDValue To) { 90 LegalizedNodes.insert(std::make_pair(From, To)); 91 // If someone requests legalization of the new node, return itself. 92 if (From != To) 93 LegalizedNodes.insert(std::make_pair(To, To)); 94 } 95 96public: 97 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 98 99 /// getTypeAction - Return how we should legalize values of this type, either 100 /// it is already legal or we need to expand it into multiple registers of 101 /// smaller integer type, or we need to promote it to a larger type. 102 LegalizeAction getTypeAction(MVT VT) const { 103 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 104 } 105 106 /// isTypeLegal - Return true if this type is legal on this target. 107 /// 108 bool isTypeLegal(MVT VT) const { 109 return getTypeAction(VT) == Legal; 110 } 111 112 void LegalizeDAG(); 113 114private: 115 /// LegalizeOp - We know that the specified value has a legal type. 116 /// Recursively ensure that the operands have legal types, then return the 117 /// result. 118 SDValue LegalizeOp(SDValue O); 119 120 SDValue OptimizeFloatStore(StoreSDNode *ST); 121 122 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 123 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 124 /// is necessary to spill the vector being inserted into to memory, perform 125 /// the insert there, and then read the result back. 126 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 127 SDValue Idx, DebugLoc dl); 128 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 129 SDValue Idx, DebugLoc dl); 130 131 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 132 /// performs the same shuffe in terms of order or result bytes, but on a type 133 /// whose vector element type is narrower than the original shuffle type. 134 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 135 SDValue ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl, 136 SDValue N1, SDValue N2, 137 SmallVectorImpl<int> &Mask) const; 138 139 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 140 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 141 142 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 143 DebugLoc dl); 144 145 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 146 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 147 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 148 RTLIB::Libcall Call_PPCF128); 149 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, RTLIB::Libcall Call_I16, 150 RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64, 151 RTLIB::Libcall Call_I128); 152 153 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl); 154 SDValue ExpandBUILD_VECTOR(SDNode *Node); 155 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 156 SDValue ExpandDBG_STOPPOINT(SDNode *Node); 157 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 158 SmallVectorImpl<SDValue> &Results); 159 SDValue ExpandFCOPYSIGN(SDNode *Node); 160 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT, 161 DebugLoc dl); 162 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned, 163 DebugLoc dl); 164 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned, 165 DebugLoc dl); 166 167 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 168 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 169 170 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 171 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 172 173 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 174 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 175}; 176} 177 178/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 179/// performs the same shuffe in terms of order or result bytes, but on a type 180/// whose vector element type is narrower than the original shuffle type. 181/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 182SDValue 183SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl, 184 SDValue N1, SDValue N2, 185 SmallVectorImpl<int> &Mask) const { 186 MVT EltVT = NVT.getVectorElementType(); 187 unsigned NumMaskElts = VT.getVectorNumElements(); 188 unsigned NumDestElts = NVT.getVectorNumElements(); 189 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 190 191 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 192 193 if (NumEltsGrowth == 1) 194 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 195 196 SmallVector<int, 8> NewMask; 197 for (unsigned i = 0; i != NumMaskElts; ++i) { 198 int Idx = Mask[i]; 199 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 200 if (Idx < 0) 201 NewMask.push_back(-1); 202 else 203 NewMask.push_back(Idx * NumEltsGrowth + j); 204 } 205 } 206 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 207 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 208 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 209} 210 211SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 212 CodeGenOpt::Level ol) 213 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), 214 ValueTypeActions(TLI.getValueTypeActions()) { 215 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 216 "Too many value types for ValueTypeActions to hold!"); 217} 218 219void SelectionDAGLegalize::LegalizeDAG() { 220 LastCALLSEQ_END = DAG.getEntryNode(); 221 IsLegalizingCall = false; 222 223 // The legalize process is inherently a bottom-up recursive process (users 224 // legalize their uses before themselves). Given infinite stack space, we 225 // could just start legalizing on the root and traverse the whole graph. In 226 // practice however, this causes us to run out of stack space on large basic 227 // blocks. To avoid this problem, compute an ordering of the nodes where each 228 // node is only legalized after all of its operands are legalized. 229 DAG.AssignTopologicalOrder(); 230 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 231 E = prior(DAG.allnodes_end()); I != next(E); ++I) 232 LegalizeOp(SDValue(I, 0)); 233 234 // Finally, it's possible the root changed. Get the new root. 235 SDValue OldRoot = DAG.getRoot(); 236 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 237 DAG.setRoot(LegalizedNodes[OldRoot]); 238 239 LegalizedNodes.clear(); 240 241 // Remove dead nodes now. 242 DAG.RemoveDeadNodes(); 243} 244 245 246/// FindCallEndFromCallStart - Given a chained node that is part of a call 247/// sequence, find the CALLSEQ_END node that terminates the call sequence. 248static SDNode *FindCallEndFromCallStart(SDNode *Node) { 249 if (Node->getOpcode() == ISD::CALLSEQ_END) 250 return Node; 251 if (Node->use_empty()) 252 return 0; // No CallSeqEnd 253 254 // The chain is usually at the end. 255 SDValue TheChain(Node, Node->getNumValues()-1); 256 if (TheChain.getValueType() != MVT::Other) { 257 // Sometimes it's at the beginning. 258 TheChain = SDValue(Node, 0); 259 if (TheChain.getValueType() != MVT::Other) { 260 // Otherwise, hunt for it. 261 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 262 if (Node->getValueType(i) == MVT::Other) { 263 TheChain = SDValue(Node, i); 264 break; 265 } 266 267 // Otherwise, we walked into a node without a chain. 268 if (TheChain.getValueType() != MVT::Other) 269 return 0; 270 } 271 } 272 273 for (SDNode::use_iterator UI = Node->use_begin(), 274 E = Node->use_end(); UI != E; ++UI) { 275 276 // Make sure to only follow users of our token chain. 277 SDNode *User = *UI; 278 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 279 if (User->getOperand(i) == TheChain) 280 if (SDNode *Result = FindCallEndFromCallStart(User)) 281 return Result; 282 } 283 return 0; 284} 285 286/// FindCallStartFromCallEnd - Given a chained node that is part of a call 287/// sequence, find the CALLSEQ_START node that initiates the call sequence. 288static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 289 assert(Node && "Didn't find callseq_start for a call??"); 290 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 291 292 assert(Node->getOperand(0).getValueType() == MVT::Other && 293 "Node doesn't have a token chain argument!"); 294 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 295} 296 297/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 298/// see if any uses can reach Dest. If no dest operands can get to dest, 299/// legalize them, legalize ourself, and return false, otherwise, return true. 300/// 301/// Keep track of the nodes we fine that actually do lead to Dest in 302/// NodesLeadingTo. This avoids retraversing them exponential number of times. 303/// 304bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 305 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 306 if (N == Dest) return true; // N certainly leads to Dest :) 307 308 // If we've already processed this node and it does lead to Dest, there is no 309 // need to reprocess it. 310 if (NodesLeadingTo.count(N)) return true; 311 312 // If the first result of this node has been already legalized, then it cannot 313 // reach N. 314 if (LegalizedNodes.count(SDValue(N, 0))) return false; 315 316 // Okay, this node has not already been legalized. Check and legalize all 317 // operands. If none lead to Dest, then we can legalize this node. 318 bool OperandsLeadToDest = false; 319 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 320 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 321 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 322 323 if (OperandsLeadToDest) { 324 NodesLeadingTo.insert(N); 325 return true; 326 } 327 328 // Okay, this node looks safe, legalize it and return false. 329 LegalizeOp(SDValue(N, 0)); 330 return false; 331} 332 333/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 334/// a load from the constant pool. 335static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 336 SelectionDAG &DAG, const TargetLowering &TLI) { 337 bool Extend = false; 338 DebugLoc dl = CFP->getDebugLoc(); 339 340 // If a FP immediate is precise when represented as a float and if the 341 // target can do an extending load from float to double, we put it into 342 // the constant pool as a float, even if it's is statically typed as a 343 // double. This shrinks FP constants and canonicalizes them for targets where 344 // an FP extending load is the same cost as a normal load (such as on the x87 345 // fp stack or PPC FP unit). 346 MVT VT = CFP->getValueType(0); 347 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 348 if (!UseCP) { 349 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 350 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 351 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 352 } 353 354 MVT OrigVT = VT; 355 MVT SVT = VT; 356 while (SVT != MVT::f32) { 357 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 358 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 359 // Only do this if the target has a native EXTLOAD instruction from 360 // smaller type. 361 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 362 TLI.ShouldShrinkFPConstant(OrigVT)) { 363 const Type *SType = SVT.getTypeForMVT(*DAG.getContext()); 364 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 365 VT = SVT; 366 Extend = true; 367 } 368 } 369 370 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 371 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 372 if (Extend) 373 return DAG.getExtLoad(ISD::EXTLOAD, dl, 374 OrigVT, DAG.getEntryNode(), 375 CPIdx, PseudoSourceValue::getConstantPool(), 376 0, VT, false, Alignment); 377 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 378 PseudoSourceValue::getConstantPool(), 0, false, Alignment); 379} 380 381/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 382static 383SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 384 const TargetLowering &TLI) { 385 SDValue Chain = ST->getChain(); 386 SDValue Ptr = ST->getBasePtr(); 387 SDValue Val = ST->getValue(); 388 MVT VT = Val.getValueType(); 389 int Alignment = ST->getAlignment(); 390 int SVOffset = ST->getSrcValueOffset(); 391 DebugLoc dl = ST->getDebugLoc(); 392 if (ST->getMemoryVT().isFloatingPoint() || 393 ST->getMemoryVT().isVector()) { 394 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits()); 395 if (TLI.isTypeLegal(intVT)) { 396 // Expand to a bitconvert of the value to the integer type of the 397 // same size, then a (misaligned) int store. 398 // FIXME: Does not handle truncating floating point stores! 399 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 400 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 401 SVOffset, ST->isVolatile(), Alignment); 402 } else { 403 // Do a (aligned) store to a stack slot, then copy from the stack slot 404 // to the final destination using (unaligned) integer loads and stores. 405 MVT StoredVT = ST->getMemoryVT(); 406 MVT RegVT = 407 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits())); 408 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 409 unsigned RegBytes = RegVT.getSizeInBits() / 8; 410 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 411 412 // Make sure the stack slot is also aligned for the register type. 413 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 414 415 // Perform the original store, only redirected to the stack slot. 416 SDValue Store = DAG.getTruncStore(Chain, dl, 417 Val, StackPtr, NULL, 0, StoredVT); 418 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 419 SmallVector<SDValue, 8> Stores; 420 unsigned Offset = 0; 421 422 // Do all but one copies using the full register width. 423 for (unsigned i = 1; i < NumRegs; i++) { 424 // Load one integer register's worth from the stack slot. 425 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0); 426 // Store it to the final location. Remember the store. 427 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 428 ST->getSrcValue(), SVOffset + Offset, 429 ST->isVolatile(), 430 MinAlign(ST->getAlignment(), Offset))); 431 // Increment the pointers. 432 Offset += RegBytes; 433 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 434 Increment); 435 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 436 } 437 438 // The last store may be partial. Do a truncating store. On big-endian 439 // machines this requires an extending load from the stack slot to ensure 440 // that the bits are in the right place. 441 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset)); 442 443 // Load from the stack slot. 444 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 445 NULL, 0, MemVT); 446 447 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 448 ST->getSrcValue(), SVOffset + Offset, 449 MemVT, ST->isVolatile(), 450 MinAlign(ST->getAlignment(), Offset))); 451 // The order of the stores doesn't matter - say it with a TokenFactor. 452 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 453 Stores.size()); 454 } 455 } 456 assert(ST->getMemoryVT().isInteger() && 457 !ST->getMemoryVT().isVector() && 458 "Unaligned store of unknown type."); 459 // Get the half-size VT 460 MVT NewStoredVT = 461 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 462 int NumBits = NewStoredVT.getSizeInBits(); 463 int IncrementSize = NumBits / 8; 464 465 // Divide the stored value in two parts. 466 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 467 SDValue Lo = Val; 468 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 469 470 // Store the two parts 471 SDValue Store1, Store2; 472 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 473 ST->getSrcValue(), SVOffset, NewStoredVT, 474 ST->isVolatile(), Alignment); 475 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 476 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 477 Alignment = MinAlign(Alignment, IncrementSize); 478 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 479 ST->getSrcValue(), SVOffset + IncrementSize, 480 NewStoredVT, ST->isVolatile(), Alignment); 481 482 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 483} 484 485/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 486static 487SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 488 const TargetLowering &TLI) { 489 int SVOffset = LD->getSrcValueOffset(); 490 SDValue Chain = LD->getChain(); 491 SDValue Ptr = LD->getBasePtr(); 492 MVT VT = LD->getValueType(0); 493 MVT LoadedVT = LD->getMemoryVT(); 494 DebugLoc dl = LD->getDebugLoc(); 495 if (VT.isFloatingPoint() || VT.isVector()) { 496 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits()); 497 if (TLI.isTypeLegal(intVT)) { 498 // Expand to a (misaligned) integer load of the same size, 499 // then bitconvert to floating point or vector. 500 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 501 SVOffset, LD->isVolatile(), 502 LD->getAlignment()); 503 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 504 if (VT.isFloatingPoint() && LoadedVT != VT) 505 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 506 507 SDValue Ops[] = { Result, Chain }; 508 return DAG.getMergeValues(Ops, 2, dl); 509 } else { 510 // Copy the value to a (aligned) stack slot using (unaligned) integer 511 // loads and stores, then do a (aligned) load from the stack slot. 512 MVT RegVT = TLI.getRegisterType(intVT); 513 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 514 unsigned RegBytes = RegVT.getSizeInBits() / 8; 515 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 516 517 // Make sure the stack slot is also aligned for the register type. 518 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 519 520 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 521 SmallVector<SDValue, 8> Stores; 522 SDValue StackPtr = StackBase; 523 unsigned Offset = 0; 524 525 // Do all but one copies using the full register width. 526 for (unsigned i = 1; i < NumRegs; i++) { 527 // Load one integer register's worth from the original location. 528 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 529 SVOffset + Offset, LD->isVolatile(), 530 MinAlign(LD->getAlignment(), Offset)); 531 // Follow the load with a store to the stack slot. Remember the store. 532 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 533 NULL, 0)); 534 // Increment the pointers. 535 Offset += RegBytes; 536 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 537 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 538 Increment); 539 } 540 541 // The last copy may be partial. Do an extending load. 542 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset)); 543 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 544 LD->getSrcValue(), SVOffset + Offset, 545 MemVT, LD->isVolatile(), 546 MinAlign(LD->getAlignment(), Offset)); 547 // Follow the load with a store to the stack slot. Remember the store. 548 // On big-endian machines this requires a truncating store to ensure 549 // that the bits end up in the right place. 550 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 551 NULL, 0, MemVT)); 552 553 // The order of the stores doesn't matter - say it with a TokenFactor. 554 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 555 Stores.size()); 556 557 // Finally, perform the original load only redirected to the stack slot. 558 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 559 NULL, 0, LoadedVT); 560 561 // Callers expect a MERGE_VALUES node. 562 SDValue Ops[] = { Load, TF }; 563 return DAG.getMergeValues(Ops, 2, dl); 564 } 565 } 566 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 567 "Unaligned load of unsupported type."); 568 569 // Compute the new VT that is half the size of the old one. This is an 570 // integer MVT. 571 unsigned NumBits = LoadedVT.getSizeInBits(); 572 MVT NewLoadedVT; 573 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 574 NumBits >>= 1; 575 576 unsigned Alignment = LD->getAlignment(); 577 unsigned IncrementSize = NumBits / 8; 578 ISD::LoadExtType HiExtType = LD->getExtensionType(); 579 580 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 581 if (HiExtType == ISD::NON_EXTLOAD) 582 HiExtType = ISD::ZEXTLOAD; 583 584 // Load the value in two parts 585 SDValue Lo, Hi; 586 if (TLI.isLittleEndian()) { 587 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 588 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 589 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 590 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 591 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 592 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 593 MinAlign(Alignment, IncrementSize)); 594 } else { 595 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 596 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 597 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 598 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 599 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 600 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 601 MinAlign(Alignment, IncrementSize)); 602 } 603 604 // aggregate the two parts 605 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 606 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 607 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 608 609 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 610 Hi.getValue(1)); 611 612 SDValue Ops[] = { Result, TF }; 613 return DAG.getMergeValues(Ops, 2, dl); 614} 615 616/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 617/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 618/// is necessary to spill the vector being inserted into to memory, perform 619/// the insert there, and then read the result back. 620SDValue SelectionDAGLegalize:: 621PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 622 DebugLoc dl) { 623 SDValue Tmp1 = Vec; 624 SDValue Tmp2 = Val; 625 SDValue Tmp3 = Idx; 626 627 // If the target doesn't support this, we have to spill the input vector 628 // to a temporary stack slot, update the element, then reload it. This is 629 // badness. We could also load the value into a vector register (either 630 // with a "move to register" or "extload into register" instruction, then 631 // permute it into place, if the idx is a constant and if the idx is 632 // supported by the target. 633 MVT VT = Tmp1.getValueType(); 634 MVT EltVT = VT.getVectorElementType(); 635 MVT IdxVT = Tmp3.getValueType(); 636 MVT PtrVT = TLI.getPointerTy(); 637 SDValue StackPtr = DAG.CreateStackTemporary(VT); 638 639 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 640 641 // Store the vector. 642 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 643 PseudoSourceValue::getFixedStack(SPFI), 0); 644 645 // Truncate or zero extend offset to target pointer type. 646 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 647 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 648 // Add the offset to the index. 649 unsigned EltSize = EltVT.getSizeInBits()/8; 650 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 651 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 652 // Store the scalar value. 653 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 654 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 655 // Load the updated vector. 656 return DAG.getLoad(VT, dl, Ch, StackPtr, 657 PseudoSourceValue::getFixedStack(SPFI), 0); 658} 659 660 661SDValue SelectionDAGLegalize:: 662ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 663 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 664 // SCALAR_TO_VECTOR requires that the type of the value being inserted 665 // match the element type of the vector being created, except for 666 // integers in which case the inserted value can be over width. 667 MVT EltVT = Vec.getValueType().getVectorElementType(); 668 if (Val.getValueType() == EltVT || 669 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 670 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 671 Vec.getValueType(), Val); 672 673 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 674 // We generate a shuffle of InVec and ScVec, so the shuffle mask 675 // should be 0,1,2,3,4,5... with the appropriate element replaced with 676 // elt 0 of the RHS. 677 SmallVector<int, 8> ShufOps; 678 for (unsigned i = 0; i != NumElts; ++i) 679 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 680 681 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 682 &ShufOps[0]); 683 } 684 } 685 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 686} 687 688SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 689 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 690 // FIXME: We shouldn't do this for TargetConstantFP's. 691 // FIXME: move this to the DAG Combiner! Note that we can't regress due 692 // to phase ordering between legalized code and the dag combiner. This 693 // probably means that we need to integrate dag combiner and legalizer 694 // together. 695 // We generally can't do this one for long doubles. 696 SDValue Tmp1 = ST->getChain(); 697 SDValue Tmp2 = ST->getBasePtr(); 698 SDValue Tmp3; 699 int SVOffset = ST->getSrcValueOffset(); 700 unsigned Alignment = ST->getAlignment(); 701 bool isVolatile = ST->isVolatile(); 702 DebugLoc dl = ST->getDebugLoc(); 703 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 704 if (CFP->getValueType(0) == MVT::f32 && 705 getTypeAction(MVT::i32) == Legal) { 706 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 707 bitcastToAPInt().zextOrTrunc(32), 708 MVT::i32); 709 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 710 SVOffset, isVolatile, Alignment); 711 } else if (CFP->getValueType(0) == MVT::f64) { 712 // If this target supports 64-bit registers, do a single 64-bit store. 713 if (getTypeAction(MVT::i64) == Legal) { 714 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 715 zextOrTrunc(64), MVT::i64); 716 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 717 SVOffset, isVolatile, Alignment); 718 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 719 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 720 // stores. If the target supports neither 32- nor 64-bits, this 721 // xform is certainly not worth it. 722 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 723 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 724 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 725 if (TLI.isBigEndian()) std::swap(Lo, Hi); 726 727 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 728 SVOffset, isVolatile, Alignment); 729 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 730 DAG.getIntPtrConstant(4)); 731 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 732 isVolatile, MinAlign(Alignment, 4U)); 733 734 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 735 } 736 } 737 } 738 return SDValue(); 739} 740 741/// LegalizeOp - We know that the specified value has a legal type, and 742/// that its operands are legal. Now ensure that the operation itself 743/// is legal, recursively ensuring that the operands' operations remain 744/// legal. 745SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 746 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 747 return Op; 748 749 SDNode *Node = Op.getNode(); 750 DebugLoc dl = Node->getDebugLoc(); 751 752 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 753 assert(getTypeAction(Node->getValueType(i)) == Legal && 754 "Unexpected illegal type!"); 755 756 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 757 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 758 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 759 "Unexpected illegal type!"); 760 761 // Note that LegalizeOp may be reentered even from single-use nodes, which 762 // means that we always must cache transformed nodes. 763 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 764 if (I != LegalizedNodes.end()) return I->second; 765 766 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 767 SDValue Result = Op; 768 bool isCustom = false; 769 770 // Figure out the correct action; the way to query this varies by opcode 771 TargetLowering::LegalizeAction Action; 772 bool SimpleFinishLegalizing = true; 773 switch (Node->getOpcode()) { 774 case ISD::INTRINSIC_W_CHAIN: 775 case ISD::INTRINSIC_WO_CHAIN: 776 case ISD::INTRINSIC_VOID: 777 case ISD::VAARG: 778 case ISD::STACKSAVE: 779 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 780 break; 781 case ISD::SINT_TO_FP: 782 case ISD::UINT_TO_FP: 783 case ISD::EXTRACT_VECTOR_ELT: 784 Action = TLI.getOperationAction(Node->getOpcode(), 785 Node->getOperand(0).getValueType()); 786 break; 787 case ISD::FP_ROUND_INREG: 788 case ISD::SIGN_EXTEND_INREG: { 789 MVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 790 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 791 break; 792 } 793 case ISD::SELECT_CC: 794 case ISD::SETCC: 795 case ISD::BR_CC: { 796 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 797 Node->getOpcode() == ISD::SETCC ? 2 : 1; 798 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 799 MVT OpVT = Node->getOperand(CompareOperand).getValueType(); 800 ISD::CondCode CCCode = 801 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 802 Action = TLI.getCondCodeAction(CCCode, OpVT); 803 if (Action == TargetLowering::Legal) { 804 if (Node->getOpcode() == ISD::SELECT_CC) 805 Action = TLI.getOperationAction(Node->getOpcode(), 806 Node->getValueType(0)); 807 else 808 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 809 } 810 break; 811 } 812 case ISD::LOAD: 813 case ISD::STORE: 814 // FIXME: Model these properly. LOAD and STORE are complicated, and 815 // STORE expects the unlegalized operand in some cases. 816 SimpleFinishLegalizing = false; 817 break; 818 case ISD::CALLSEQ_START: 819 case ISD::CALLSEQ_END: 820 // FIXME: This shouldn't be necessary. These nodes have special properties 821 // dealing with the recursive nature of legalization. Removing this 822 // special case should be done as part of making LegalizeDAG non-recursive. 823 SimpleFinishLegalizing = false; 824 break; 825 case ISD::CALL: 826 // FIXME: Legalization for calls requires custom-lowering the call before 827 // legalizing the operands! (I haven't looked into precisely why.) 828 SimpleFinishLegalizing = false; 829 break; 830 case ISD::EXTRACT_ELEMENT: 831 case ISD::FLT_ROUNDS_: 832 case ISD::SADDO: 833 case ISD::SSUBO: 834 case ISD::UADDO: 835 case ISD::USUBO: 836 case ISD::SMULO: 837 case ISD::UMULO: 838 case ISD::FPOWI: 839 case ISD::MERGE_VALUES: 840 case ISD::EH_RETURN: 841 case ISD::FRAME_TO_ARGS_OFFSET: 842 // These operations lie about being legal: when they claim to be legal, 843 // they should actually be expanded. 844 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 845 if (Action == TargetLowering::Legal) 846 Action = TargetLowering::Expand; 847 break; 848 case ISD::TRAMPOLINE: 849 case ISD::FRAMEADDR: 850 case ISD::RETURNADDR: 851 case ISD::FORMAL_ARGUMENTS: 852 // These operations lie about being legal: when they claim to be legal, 853 // they should actually be custom-lowered. 854 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 855 if (Action == TargetLowering::Legal) 856 Action = TargetLowering::Custom; 857 break; 858 case ISD::BUILD_VECTOR: 859 // A weird case: legalization for BUILD_VECTOR never legalizes the 860 // operands! 861 // FIXME: This really sucks... changing it isn't semantically incorrect, 862 // but it massively pessimizes the code for floating-point BUILD_VECTORs 863 // because ConstantFP operands get legalized into constant pool loads 864 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 865 // though, because BUILD_VECTORS usually get lowered into other nodes 866 // which get legalized properly. 867 SimpleFinishLegalizing = false; 868 break; 869 default: 870 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 871 Action = TargetLowering::Legal; 872 } else { 873 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 874 } 875 break; 876 } 877 878 if (SimpleFinishLegalizing) { 879 SmallVector<SDValue, 8> Ops, ResultVals; 880 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 881 Ops.push_back(LegalizeOp(Node->getOperand(i))); 882 switch (Node->getOpcode()) { 883 default: break; 884 case ISD::BR: 885 case ISD::BRIND: 886 case ISD::BR_JT: 887 case ISD::BR_CC: 888 case ISD::BRCOND: 889 case ISD::RET: 890 // Branches tweak the chain to include LastCALLSEQ_END 891 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 892 LastCALLSEQ_END); 893 Ops[0] = LegalizeOp(Ops[0]); 894 LastCALLSEQ_END = DAG.getEntryNode(); 895 break; 896 case ISD::SHL: 897 case ISD::SRL: 898 case ISD::SRA: 899 case ISD::ROTL: 900 case ISD::ROTR: 901 // Legalizing shifts/rotates requires adjusting the shift amount 902 // to the appropriate width. 903 if (!Ops[1].getValueType().isVector()) 904 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 905 break; 906 } 907 908 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(), 909 Ops.size()); 910 switch (Action) { 911 case TargetLowering::Legal: 912 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 913 ResultVals.push_back(Result.getValue(i)); 914 break; 915 case TargetLowering::Custom: 916 // FIXME: The handling for custom lowering with multiple results is 917 // a complete mess. 918 Tmp1 = TLI.LowerOperation(Result, DAG); 919 if (Tmp1.getNode()) { 920 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 921 if (e == 1) 922 ResultVals.push_back(Tmp1); 923 else 924 ResultVals.push_back(Tmp1.getValue(i)); 925 } 926 break; 927 } 928 929 // FALL THROUGH 930 case TargetLowering::Expand: 931 ExpandNode(Result.getNode(), ResultVals); 932 break; 933 case TargetLowering::Promote: 934 PromoteNode(Result.getNode(), ResultVals); 935 break; 936 } 937 if (!ResultVals.empty()) { 938 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 939 if (ResultVals[i] != SDValue(Node, i)) 940 ResultVals[i] = LegalizeOp(ResultVals[i]); 941 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 942 } 943 return ResultVals[Op.getResNo()]; 944 } 945 } 946 947 switch (Node->getOpcode()) { 948 default: 949#ifndef NDEBUG 950 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 951#endif 952 LLVM_UNREACHABLE("Do not know how to legalize this operator!"); 953 case ISD::CALL: 954 // The only option for this is to custom lower it. 955 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 956 assert(Tmp3.getNode() && "Target didn't custom lower this node!"); 957 // A call within a calling sequence must be legalized to something 958 // other than the normal CALLSEQ_END. Violating this gets Legalize 959 // into an infinite loop. 960 assert ((!IsLegalizingCall || 961 Node->getOpcode() != ISD::CALL || 962 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) && 963 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 964 965 // The number of incoming and outgoing values should match; unless the final 966 // outgoing value is a flag. 967 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || 968 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 && 969 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == 970 MVT::Flag)) && 971 "Lowering call/formal_arguments produced unexpected # results!"); 972 973 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 974 // remember that we legalized all of them, so it doesn't get relegalized. 975 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) { 976 if (Tmp3.getNode()->getValueType(i) == MVT::Flag) 977 continue; 978 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 979 if (Op.getResNo() == i) 980 Tmp2 = Tmp1; 981 AddLegalizedOperand(SDValue(Node, i), Tmp1); 982 } 983 return Tmp2; 984 case ISD::BUILD_VECTOR: 985 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 986 default: assert(0 && "This action is not supported yet!"); 987 case TargetLowering::Custom: 988 Tmp3 = TLI.LowerOperation(Result, DAG); 989 if (Tmp3.getNode()) { 990 Result = Tmp3; 991 break; 992 } 993 // FALLTHROUGH 994 case TargetLowering::Expand: 995 Result = ExpandBUILD_VECTOR(Result.getNode()); 996 break; 997 } 998 break; 999 case ISD::CALLSEQ_START: { 1000 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1001 1002 // Recursively Legalize all of the inputs of the call end that do not lead 1003 // to this call start. This ensures that any libcalls that need be inserted 1004 // are inserted *before* the CALLSEQ_START. 1005 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1006 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1007 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1008 NodesLeadingTo); 1009 } 1010 1011 // Now that we legalized all of the inputs (which may have inserted 1012 // libcalls) create the new CALLSEQ_START node. 1013 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1014 1015 // Merge in the last call, to ensure that this call start after the last 1016 // call ended. 1017 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1018 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1019 Tmp1, LastCALLSEQ_END); 1020 Tmp1 = LegalizeOp(Tmp1); 1021 } 1022 1023 // Do not try to legalize the target-specific arguments (#1+). 1024 if (Tmp1 != Node->getOperand(0)) { 1025 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1026 Ops[0] = Tmp1; 1027 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1028 } 1029 1030 // Remember that the CALLSEQ_START is legalized. 1031 AddLegalizedOperand(Op.getValue(0), Result); 1032 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1033 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1034 1035 // Now that the callseq_start and all of the non-call nodes above this call 1036 // sequence have been legalized, legalize the call itself. During this 1037 // process, no libcalls can/will be inserted, guaranteeing that no calls 1038 // can overlap. 1039 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1040 // Note that we are selecting this call! 1041 LastCALLSEQ_END = SDValue(CallEnd, 0); 1042 IsLegalizingCall = true; 1043 1044 // Legalize the call, starting from the CALLSEQ_END. 1045 LegalizeOp(LastCALLSEQ_END); 1046 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1047 return Result; 1048 } 1049 case ISD::CALLSEQ_END: 1050 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1051 // will cause this node to be legalized as well as handling libcalls right. 1052 if (LastCALLSEQ_END.getNode() != Node) { 1053 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1054 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1055 assert(I != LegalizedNodes.end() && 1056 "Legalizing the call start should have legalized this node!"); 1057 return I->second; 1058 } 1059 1060 // Otherwise, the call start has been legalized and everything is going 1061 // according to plan. Just legalize ourselves normally here. 1062 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1063 // Do not try to legalize the target-specific arguments (#1+), except for 1064 // an optional flag input. 1065 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1066 if (Tmp1 != Node->getOperand(0)) { 1067 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1068 Ops[0] = Tmp1; 1069 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1070 } 1071 } else { 1072 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1073 if (Tmp1 != Node->getOperand(0) || 1074 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1075 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1076 Ops[0] = Tmp1; 1077 Ops.back() = Tmp2; 1078 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1079 } 1080 } 1081 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1082 // This finishes up call legalization. 1083 IsLegalizingCall = false; 1084 1085 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1086 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1087 if (Node->getNumValues() == 2) 1088 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1089 return Result.getValue(Op.getResNo()); 1090 case ISD::LOAD: { 1091 LoadSDNode *LD = cast<LoadSDNode>(Node); 1092 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1093 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1094 1095 ISD::LoadExtType ExtType = LD->getExtensionType(); 1096 if (ExtType == ISD::NON_EXTLOAD) { 1097 MVT VT = Node->getValueType(0); 1098 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1099 Tmp3 = Result.getValue(0); 1100 Tmp4 = Result.getValue(1); 1101 1102 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1103 default: assert(0 && "This action is not supported yet!"); 1104 case TargetLowering::Legal: 1105 // If this is an unaligned load and the target doesn't support it, 1106 // expand it. 1107 if (!TLI.allowsUnalignedMemoryAccesses()) { 1108 unsigned ABIAlignment = TLI.getTargetData()-> 1109 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT( 1110 *DAG.getContext())); 1111 if (LD->getAlignment() < ABIAlignment){ 1112 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 1113 TLI); 1114 Tmp3 = Result.getOperand(0); 1115 Tmp4 = Result.getOperand(1); 1116 Tmp3 = LegalizeOp(Tmp3); 1117 Tmp4 = LegalizeOp(Tmp4); 1118 } 1119 } 1120 break; 1121 case TargetLowering::Custom: 1122 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1123 if (Tmp1.getNode()) { 1124 Tmp3 = LegalizeOp(Tmp1); 1125 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1126 } 1127 break; 1128 case TargetLowering::Promote: { 1129 // Only promote a load of vector type to another. 1130 assert(VT.isVector() && "Cannot promote this load!"); 1131 // Change base type to a different vector type. 1132 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1133 1134 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1135 LD->getSrcValueOffset(), 1136 LD->isVolatile(), LD->getAlignment()); 1137 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1138 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1139 break; 1140 } 1141 } 1142 // Since loads produce two values, make sure to remember that we 1143 // legalized both of them. 1144 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1145 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1146 return Op.getResNo() ? Tmp4 : Tmp3; 1147 } else { 1148 MVT SrcVT = LD->getMemoryVT(); 1149 unsigned SrcWidth = SrcVT.getSizeInBits(); 1150 int SVOffset = LD->getSrcValueOffset(); 1151 unsigned Alignment = LD->getAlignment(); 1152 bool isVolatile = LD->isVolatile(); 1153 1154 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1155 // Some targets pretend to have an i1 loading operation, and actually 1156 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1157 // bits are guaranteed to be zero; it helps the optimizers understand 1158 // that these bits are zero. It is also useful for EXTLOAD, since it 1159 // tells the optimizers that those bits are undefined. It would be 1160 // nice to have an effective generic way of getting these benefits... 1161 // Until such a way is found, don't insist on promoting i1 here. 1162 (SrcVT != MVT::i1 || 1163 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1164 // Promote to a byte-sized load if not loading an integral number of 1165 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1166 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1167 MVT NVT = MVT::getIntegerVT(NewWidth); 1168 SDValue Ch; 1169 1170 // The extra bits are guaranteed to be zero, since we stored them that 1171 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1172 1173 ISD::LoadExtType NewExtType = 1174 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1175 1176 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 1177 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1178 NVT, isVolatile, Alignment); 1179 1180 Ch = Result.getValue(1); // The chain. 1181 1182 if (ExtType == ISD::SEXTLOAD) 1183 // Having the top bits zero doesn't help when sign extending. 1184 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1185 Result.getValueType(), 1186 Result, DAG.getValueType(SrcVT)); 1187 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1188 // All the top bits are guaranteed to be zero - inform the optimizers. 1189 Result = DAG.getNode(ISD::AssertZext, dl, 1190 Result.getValueType(), Result, 1191 DAG.getValueType(SrcVT)); 1192 1193 Tmp1 = LegalizeOp(Result); 1194 Tmp2 = LegalizeOp(Ch); 1195 } else if (SrcWidth & (SrcWidth - 1)) { 1196 // If not loading a power-of-2 number of bits, expand as two loads. 1197 assert(SrcVT.isExtended() && !SrcVT.isVector() && 1198 "Unsupported extload!"); 1199 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1200 assert(RoundWidth < SrcWidth); 1201 unsigned ExtraWidth = SrcWidth - RoundWidth; 1202 assert(ExtraWidth < RoundWidth); 1203 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1204 "Load size not an integral number of bytes!"); 1205 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 1206 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 1207 SDValue Lo, Hi, Ch; 1208 unsigned IncrementSize; 1209 1210 if (TLI.isLittleEndian()) { 1211 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1212 // Load the bottom RoundWidth bits. 1213 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1214 Node->getValueType(0), Tmp1, Tmp2, 1215 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1216 Alignment); 1217 1218 // Load the remaining ExtraWidth bits. 1219 IncrementSize = RoundWidth / 8; 1220 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1221 DAG.getIntPtrConstant(IncrementSize)); 1222 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1223 LD->getSrcValue(), SVOffset + IncrementSize, 1224 ExtraVT, isVolatile, 1225 MinAlign(Alignment, IncrementSize)); 1226 1227 // Build a factor node to remember that this load is independent of the 1228 // other one. 1229 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1230 Hi.getValue(1)); 1231 1232 // Move the top bits to the right place. 1233 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1234 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1235 1236 // Join the hi and lo parts. 1237 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1238 } else { 1239 // Big endian - avoid unaligned loads. 1240 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1241 // Load the top RoundWidth bits. 1242 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1243 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1244 Alignment); 1245 1246 // Load the remaining ExtraWidth bits. 1247 IncrementSize = RoundWidth / 8; 1248 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1249 DAG.getIntPtrConstant(IncrementSize)); 1250 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1251 Node->getValueType(0), Tmp1, Tmp2, 1252 LD->getSrcValue(), SVOffset + IncrementSize, 1253 ExtraVT, isVolatile, 1254 MinAlign(Alignment, IncrementSize)); 1255 1256 // Build a factor node to remember that this load is independent of the 1257 // other one. 1258 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1259 Hi.getValue(1)); 1260 1261 // Move the top bits to the right place. 1262 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1263 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1264 1265 // Join the hi and lo parts. 1266 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1267 } 1268 1269 Tmp1 = LegalizeOp(Result); 1270 Tmp2 = LegalizeOp(Ch); 1271 } else { 1272 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1273 default: assert(0 && "This action is not supported yet!"); 1274 case TargetLowering::Custom: 1275 isCustom = true; 1276 // FALLTHROUGH 1277 case TargetLowering::Legal: 1278 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1279 Tmp1 = Result.getValue(0); 1280 Tmp2 = Result.getValue(1); 1281 1282 if (isCustom) { 1283 Tmp3 = TLI.LowerOperation(Result, DAG); 1284 if (Tmp3.getNode()) { 1285 Tmp1 = LegalizeOp(Tmp3); 1286 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1287 } 1288 } else { 1289 // If this is an unaligned load and the target doesn't support it, 1290 // expand it. 1291 if (!TLI.allowsUnalignedMemoryAccesses()) { 1292 unsigned ABIAlignment = TLI.getTargetData()-> 1293 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT( 1294 *DAG.getContext())); 1295 if (LD->getAlignment() < ABIAlignment){ 1296 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 1297 TLI); 1298 Tmp1 = Result.getOperand(0); 1299 Tmp2 = Result.getOperand(1); 1300 Tmp1 = LegalizeOp(Tmp1); 1301 Tmp2 = LegalizeOp(Tmp2); 1302 } 1303 } 1304 } 1305 break; 1306 case TargetLowering::Expand: 1307 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1308 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1309 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1310 LD->getSrcValueOffset(), 1311 LD->isVolatile(), LD->getAlignment()); 1312 Result = DAG.getNode(ISD::FP_EXTEND, dl, 1313 Node->getValueType(0), Load); 1314 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1315 Tmp2 = LegalizeOp(Load.getValue(1)); 1316 break; 1317 } 1318 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1319 // Turn the unsupported load into an EXTLOAD followed by an explicit 1320 // zero/sign extend inreg. 1321 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1322 Tmp1, Tmp2, LD->getSrcValue(), 1323 LD->getSrcValueOffset(), SrcVT, 1324 LD->isVolatile(), LD->getAlignment()); 1325 SDValue ValRes; 1326 if (ExtType == ISD::SEXTLOAD) 1327 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1328 Result.getValueType(), 1329 Result, DAG.getValueType(SrcVT)); 1330 else 1331 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1332 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1333 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1334 break; 1335 } 1336 } 1337 1338 // Since loads produce two values, make sure to remember that we legalized 1339 // both of them. 1340 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1341 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1342 return Op.getResNo() ? Tmp2 : Tmp1; 1343 } 1344 } 1345 case ISD::STORE: { 1346 StoreSDNode *ST = cast<StoreSDNode>(Node); 1347 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1348 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1349 int SVOffset = ST->getSrcValueOffset(); 1350 unsigned Alignment = ST->getAlignment(); 1351 bool isVolatile = ST->isVolatile(); 1352 1353 if (!ST->isTruncatingStore()) { 1354 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1355 Result = SDValue(OptStore, 0); 1356 break; 1357 } 1358 1359 { 1360 Tmp3 = LegalizeOp(ST->getValue()); 1361 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1362 ST->getOffset()); 1363 1364 MVT VT = Tmp3.getValueType(); 1365 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1366 default: assert(0 && "This action is not supported yet!"); 1367 case TargetLowering::Legal: 1368 // If this is an unaligned store and the target doesn't support it, 1369 // expand it. 1370 if (!TLI.allowsUnalignedMemoryAccesses()) { 1371 unsigned ABIAlignment = TLI.getTargetData()-> 1372 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT( 1373 *DAG.getContext())); 1374 if (ST->getAlignment() < ABIAlignment) 1375 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 1376 TLI); 1377 } 1378 break; 1379 case TargetLowering::Custom: 1380 Tmp1 = TLI.LowerOperation(Result, DAG); 1381 if (Tmp1.getNode()) Result = Tmp1; 1382 break; 1383 case TargetLowering::Promote: 1384 assert(VT.isVector() && "Unknown legal promote case!"); 1385 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1386 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1387 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1388 ST->getSrcValue(), SVOffset, isVolatile, 1389 Alignment); 1390 break; 1391 } 1392 break; 1393 } 1394 } else { 1395 Tmp3 = LegalizeOp(ST->getValue()); 1396 1397 MVT StVT = ST->getMemoryVT(); 1398 unsigned StWidth = StVT.getSizeInBits(); 1399 1400 if (StWidth != StVT.getStoreSizeInBits()) { 1401 // Promote to a byte-sized store with upper bits zero if not 1402 // storing an integral number of bytes. For example, promote 1403 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1404 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 1405 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1406 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1407 SVOffset, NVT, isVolatile, Alignment); 1408 } else if (StWidth & (StWidth - 1)) { 1409 // If not storing a power-of-2 number of bits, expand as two stores. 1410 assert(StVT.isExtended() && !StVT.isVector() && 1411 "Unsupported truncstore!"); 1412 unsigned RoundWidth = 1 << Log2_32(StWidth); 1413 assert(RoundWidth < StWidth); 1414 unsigned ExtraWidth = StWidth - RoundWidth; 1415 assert(ExtraWidth < RoundWidth); 1416 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1417 "Store size not an integral number of bytes!"); 1418 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 1419 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 1420 SDValue Lo, Hi; 1421 unsigned IncrementSize; 1422 1423 if (TLI.isLittleEndian()) { 1424 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1425 // Store the bottom RoundWidth bits. 1426 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1427 SVOffset, RoundVT, 1428 isVolatile, Alignment); 1429 1430 // Store the remaining ExtraWidth bits. 1431 IncrementSize = RoundWidth / 8; 1432 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1433 DAG.getIntPtrConstant(IncrementSize)); 1434 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1435 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1436 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1437 SVOffset + IncrementSize, ExtraVT, isVolatile, 1438 MinAlign(Alignment, IncrementSize)); 1439 } else { 1440 // Big endian - avoid unaligned stores. 1441 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1442 // Store the top RoundWidth bits. 1443 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1444 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1445 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1446 SVOffset, RoundVT, isVolatile, Alignment); 1447 1448 // Store the remaining ExtraWidth bits. 1449 IncrementSize = RoundWidth / 8; 1450 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1451 DAG.getIntPtrConstant(IncrementSize)); 1452 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1453 SVOffset + IncrementSize, ExtraVT, isVolatile, 1454 MinAlign(Alignment, IncrementSize)); 1455 } 1456 1457 // The order of the stores doesn't matter. 1458 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1459 } else { 1460 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1461 Tmp2 != ST->getBasePtr()) 1462 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1463 ST->getOffset()); 1464 1465 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1466 default: assert(0 && "This action is not supported yet!"); 1467 case TargetLowering::Legal: 1468 // If this is an unaligned store and the target doesn't support it, 1469 // expand it. 1470 if (!TLI.allowsUnalignedMemoryAccesses()) { 1471 unsigned ABIAlignment = TLI.getTargetData()-> 1472 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT( 1473 *DAG.getContext())); 1474 if (ST->getAlignment() < ABIAlignment) 1475 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 1476 TLI); 1477 } 1478 break; 1479 case TargetLowering::Custom: 1480 Result = TLI.LowerOperation(Result, DAG); 1481 break; 1482 case Expand: 1483 // TRUNCSTORE:i16 i32 -> STORE i16 1484 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1485 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1486 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1487 SVOffset, isVolatile, Alignment); 1488 break; 1489 } 1490 } 1491 } 1492 break; 1493 } 1494 } 1495 assert(Result.getValueType() == Op.getValueType() && 1496 "Bad legalization!"); 1497 1498 // Make sure that the generated code is itself legal. 1499 if (Result != Op) 1500 Result = LegalizeOp(Result); 1501 1502 // Note that LegalizeOp may be reentered even from single-use nodes, which 1503 // means that we always must cache transformed nodes. 1504 AddLegalizedOperand(Op, Result); 1505 return Result; 1506} 1507 1508SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1509 SDValue Vec = Op.getOperand(0); 1510 SDValue Idx = Op.getOperand(1); 1511 DebugLoc dl = Op.getDebugLoc(); 1512 // Store the value to a temporary stack slot, then LOAD the returned part. 1513 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1514 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0); 1515 1516 // Add the offset to the index. 1517 unsigned EltSize = 1518 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1519 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1520 DAG.getConstant(EltSize, Idx.getValueType())); 1521 1522 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1523 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1524 else 1525 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1526 1527 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1528 1529 if (Op.getValueType().isVector()) 1530 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0); 1531 else 1532 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1533 NULL, 0, Vec.getValueType().getVectorElementType()); 1534} 1535 1536SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1537 // We can't handle this case efficiently. Allocate a sufficiently 1538 // aligned object on the stack, store each element into it, then load 1539 // the result as a vector. 1540 // Create the stack frame object. 1541 MVT VT = Node->getValueType(0); 1542 MVT OpVT = Node->getOperand(0).getValueType(); 1543 DebugLoc dl = Node->getDebugLoc(); 1544 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1545 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1546 const Value *SV = PseudoSourceValue::getFixedStack(FI); 1547 1548 // Emit a store of each element to the stack slot. 1549 SmallVector<SDValue, 8> Stores; 1550 unsigned TypeByteSize = OpVT.getSizeInBits() / 8; 1551 // Store (in the right endianness) the elements to memory. 1552 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1553 // Ignore undef elements. 1554 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1555 1556 unsigned Offset = TypeByteSize*i; 1557 1558 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1559 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1560 1561 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i), 1562 Idx, SV, Offset)); 1563 } 1564 1565 SDValue StoreChain; 1566 if (!Stores.empty()) // Not all undef elements? 1567 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1568 &Stores[0], Stores.size()); 1569 else 1570 StoreChain = DAG.getEntryNode(); 1571 1572 // Result is a load from the stack slot. 1573 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0); 1574} 1575 1576SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1577 DebugLoc dl = Node->getDebugLoc(); 1578 SDValue Tmp1 = Node->getOperand(0); 1579 SDValue Tmp2 = Node->getOperand(1); 1580 assert((Tmp2.getValueType() == MVT::f32 || 1581 Tmp2.getValueType() == MVT::f64) && 1582 "Ugly special-cased code!"); 1583 // Get the sign bit of the RHS. 1584 SDValue SignBit; 1585 MVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32; 1586 if (isTypeLegal(IVT)) { 1587 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1588 } else { 1589 assert(isTypeLegal(TLI.getPointerTy()) && 1590 (TLI.getPointerTy() == MVT::i32 || 1591 TLI.getPointerTy() == MVT::i64) && 1592 "Legal type for load?!"); 1593 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType()); 1594 SDValue StorePtr = StackPtr, LoadPtr = StackPtr; 1595 SDValue Ch = 1596 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0); 1597 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian()) 1598 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), 1599 LoadPtr, DAG.getIntPtrConstant(4)); 1600 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(), 1601 Ch, LoadPtr, NULL, 0, MVT::i32); 1602 } 1603 SignBit = 1604 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1605 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1606 ISD::SETLT); 1607 // Get the absolute value of the result. 1608 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1609 // Select between the nabs and abs value based on the sign bit of 1610 // the input. 1611 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1612 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1613 AbsVal); 1614} 1615 1616SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) { 1617 DebugLoc dl = Node->getDebugLoc(); 1618 DwarfWriter *DW = DAG.getDwarfWriter(); 1619 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, 1620 MVT::Other); 1621 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); 1622 1623 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1624 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit()); 1625 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) { 1626 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit())); 1627 1628 unsigned Line = DSP->getLine(); 1629 unsigned Col = DSP->getColumn(); 1630 1631 if (OptLevel == CodeGenOpt::None) { 1632 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it 1633 // won't hurt anything. 1634 if (useDEBUG_LOC) { 1635 return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0), 1636 DAG.getConstant(Line, MVT::i32), 1637 DAG.getConstant(Col, MVT::i32), 1638 DAG.getSrcValue(CU.getGV())); 1639 } else { 1640 unsigned ID = DW->RecordSourceLine(Line, Col, CU); 1641 return DAG.getLabel(ISD::DBG_LABEL, dl, Node->getOperand(0), ID); 1642 } 1643 } 1644 } 1645 return Node->getOperand(0); 1646} 1647 1648void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1649 SmallVectorImpl<SDValue> &Results) { 1650 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1651 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1652 " not tell us which reg is the stack pointer!"); 1653 DebugLoc dl = Node->getDebugLoc(); 1654 MVT VT = Node->getValueType(0); 1655 SDValue Tmp1 = SDValue(Node, 0); 1656 SDValue Tmp2 = SDValue(Node, 1); 1657 SDValue Tmp3 = Node->getOperand(2); 1658 SDValue Chain = Tmp1.getOperand(0); 1659 1660 // Chain the dynamic stack allocation so that it doesn't modify the stack 1661 // pointer when other instructions are using the stack. 1662 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1663 1664 SDValue Size = Tmp2.getOperand(1); 1665 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1666 Chain = SP.getValue(1); 1667 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1668 unsigned StackAlign = 1669 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1670 if (Align > StackAlign) 1671 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1672 DAG.getConstant(-(uint64_t)Align, VT)); 1673 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1674 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1675 1676 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1677 DAG.getIntPtrConstant(0, true), SDValue()); 1678 1679 Results.push_back(Tmp1); 1680 Results.push_back(Tmp2); 1681} 1682 1683/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1684/// condition code CC on the current target. This routine assumes LHS and rHS 1685/// have already been legalized by LegalizeSetCCOperands. It expands SETCC with 1686/// illegal condition code into AND / OR of multiple SETCC values. 1687void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, 1688 SDValue &LHS, SDValue &RHS, 1689 SDValue &CC, 1690 DebugLoc dl) { 1691 MVT OpVT = LHS.getValueType(); 1692 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1693 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1694 default: assert(0 && "Unknown condition code action!"); 1695 case TargetLowering::Legal: 1696 // Nothing to do. 1697 break; 1698 case TargetLowering::Expand: { 1699 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1700 unsigned Opc = 0; 1701 switch (CCCode) { 1702 default: LLVM_UNREACHABLE("Don't know how to expand this condition!"); 1703 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1704 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1705 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1706 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1707 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1708 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1709 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1710 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1711 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1712 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1713 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1714 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1715 // FIXME: Implement more expansions. 1716 } 1717 1718 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1719 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1720 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1721 RHS = SDValue(); 1722 CC = SDValue(); 1723 break; 1724 } 1725 } 1726} 1727 1728/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1729/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1730/// a load from the stack slot to DestVT, extending it if needed. 1731/// The resultant code need not be legal. 1732SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1733 MVT SlotVT, 1734 MVT DestVT, 1735 DebugLoc dl) { 1736 // Create the stack frame object. 1737 unsigned SrcAlign = 1738 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1739 getTypeForMVT(*DAG.getContext())); 1740 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1741 1742 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1743 int SPFI = StackPtrFI->getIndex(); 1744 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1745 1746 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1747 unsigned SlotSize = SlotVT.getSizeInBits(); 1748 unsigned DestSize = DestVT.getSizeInBits(); 1749 unsigned DestAlign = 1750 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT( 1751 *DAG.getContext())); 1752 1753 // Emit a store to the stack slot. Use a truncstore if the input value is 1754 // later than DestVT. 1755 SDValue Store; 1756 1757 if (SrcSize > SlotSize) 1758 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1759 SV, 0, SlotVT, false, SrcAlign); 1760 else { 1761 assert(SrcSize == SlotSize && "Invalid store"); 1762 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1763 SV, 0, false, SrcAlign); 1764 } 1765 1766 // Result is a load from the stack slot. 1767 if (SlotSize == DestSize) 1768 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign); 1769 1770 assert(SlotSize < DestSize && "Unknown extension!"); 1771 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, 1772 false, DestAlign); 1773} 1774 1775SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1776 DebugLoc dl = Node->getDebugLoc(); 1777 // Create a vector sized/aligned stack slot, store the value to element #0, 1778 // then load the whole vector back out. 1779 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1780 1781 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1782 int SPFI = StackPtrFI->getIndex(); 1783 1784 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1785 StackPtr, 1786 PseudoSourceValue::getFixedStack(SPFI), 0, 1787 Node->getValueType(0).getVectorElementType()); 1788 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1789 PseudoSourceValue::getFixedStack(SPFI), 0); 1790} 1791 1792 1793/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1794/// support the operation, but do support the resultant vector type. 1795SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1796 unsigned NumElems = Node->getNumOperands(); 1797 SDValue Value1, Value2; 1798 DebugLoc dl = Node->getDebugLoc(); 1799 MVT VT = Node->getValueType(0); 1800 MVT OpVT = Node->getOperand(0).getValueType(); 1801 MVT EltVT = VT.getVectorElementType(); 1802 1803 // If the only non-undef value is the low element, turn this into a 1804 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1805 bool isOnlyLowElement = true; 1806 bool MoreThanTwoValues = false; 1807 bool isConstant = true; 1808 for (unsigned i = 0; i < NumElems; ++i) { 1809 SDValue V = Node->getOperand(i); 1810 if (V.getOpcode() == ISD::UNDEF) 1811 continue; 1812 if (i > 0) 1813 isOnlyLowElement = false; 1814 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1815 isConstant = false; 1816 1817 if (!Value1.getNode()) { 1818 Value1 = V; 1819 } else if (!Value2.getNode()) { 1820 if (V != Value1) 1821 Value2 = V; 1822 } else if (V != Value1 && V != Value2) { 1823 MoreThanTwoValues = true; 1824 } 1825 } 1826 1827 if (!Value1.getNode()) 1828 return DAG.getUNDEF(VT); 1829 1830 if (isOnlyLowElement) 1831 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1832 1833 // If all elements are constants, create a load from the constant pool. 1834 if (isConstant) { 1835 std::vector<Constant*> CV; 1836 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1837 if (ConstantFPSDNode *V = 1838 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1839 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1840 } else if (ConstantSDNode *V = 1841 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1842 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1843 } else { 1844 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1845 const Type *OpNTy = OpVT.getTypeForMVT(*DAG.getContext()); 1846 CV.push_back(UndefValue::get(OpNTy)); 1847 } 1848 } 1849 Constant *CP = ConstantVector::get(CV); 1850 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1851 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1852 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1853 PseudoSourceValue::getConstantPool(), 0, 1854 false, Alignment); 1855 } 1856 1857 if (!MoreThanTwoValues) { 1858 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1859 for (unsigned i = 0; i < NumElems; ++i) { 1860 SDValue V = Node->getOperand(i); 1861 if (V.getOpcode() == ISD::UNDEF) 1862 continue; 1863 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1864 } 1865 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1866 // Get the splatted value into the low element of a vector register. 1867 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1868 SDValue Vec2; 1869 if (Value2.getNode()) 1870 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1871 else 1872 Vec2 = DAG.getUNDEF(VT); 1873 1874 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1875 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1876 } 1877 } 1878 1879 // Otherwise, we can't handle this case efficiently. 1880 return ExpandVectorBuildThroughStack(Node); 1881} 1882 1883// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1884// does not fit into a register, return the lo part and set the hi part to the 1885// by-reg argument. If it does fit into a single register, return the result 1886// and leave the Hi part unset. 1887SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1888 bool isSigned) { 1889 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1890 // The input chain to this libcall is the entry node of the function. 1891 // Legalizing the call will automatically add the previous call to the 1892 // dependence. 1893 SDValue InChain = DAG.getEntryNode(); 1894 1895 TargetLowering::ArgListTy Args; 1896 TargetLowering::ArgListEntry Entry; 1897 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1898 MVT ArgVT = Node->getOperand(i).getValueType(); 1899 const Type *ArgTy = ArgVT.getTypeForMVT(*DAG.getContext()); 1900 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1901 Entry.isSExt = isSigned; 1902 Entry.isZExt = !isSigned; 1903 Args.push_back(Entry); 1904 } 1905 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1906 TLI.getPointerTy()); 1907 1908 // Splice the libcall in wherever FindInputOutputChains tells us to. 1909 const Type *RetTy = Node->getValueType(0).getTypeForMVT(*DAG.getContext()); 1910 std::pair<SDValue, SDValue> CallInfo = 1911 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1912 0, CallingConv::C, false, Callee, Args, DAG, 1913 Node->getDebugLoc()); 1914 1915 // Legalize the call sequence, starting with the chain. This will advance 1916 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1917 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1918 LegalizeOp(CallInfo.second); 1919 return CallInfo.first; 1920} 1921 1922SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1923 RTLIB::Libcall Call_F32, 1924 RTLIB::Libcall Call_F64, 1925 RTLIB::Libcall Call_F80, 1926 RTLIB::Libcall Call_PPCF128) { 1927 RTLIB::Libcall LC; 1928 switch (Node->getValueType(0).getSimpleVT()) { 1929 default: assert(0 && "Unexpected request for libcall!"); 1930 case MVT::f32: LC = Call_F32; break; 1931 case MVT::f64: LC = Call_F64; break; 1932 case MVT::f80: LC = Call_F80; break; 1933 case MVT::ppcf128: LC = Call_PPCF128; break; 1934 } 1935 return ExpandLibCall(LC, Node, false); 1936} 1937 1938SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 1939 RTLIB::Libcall Call_I16, 1940 RTLIB::Libcall Call_I32, 1941 RTLIB::Libcall Call_I64, 1942 RTLIB::Libcall Call_I128) { 1943 RTLIB::Libcall LC; 1944 switch (Node->getValueType(0).getSimpleVT()) { 1945 default: assert(0 && "Unexpected request for libcall!"); 1946 case MVT::i16: LC = Call_I16; break; 1947 case MVT::i32: LC = Call_I32; break; 1948 case MVT::i64: LC = Call_I64; break; 1949 case MVT::i128: LC = Call_I128; break; 1950 } 1951 return ExpandLibCall(LC, Node, isSigned); 1952} 1953 1954/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 1955/// INT_TO_FP operation of the specified operand when the target requests that 1956/// we expand it. At this point, we know that the result and operand types are 1957/// legal for the target. 1958SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 1959 SDValue Op0, 1960 MVT DestVT, 1961 DebugLoc dl) { 1962 if (Op0.getValueType() == MVT::i32) { 1963 // simple 32-bit [signed|unsigned] integer to float/double expansion 1964 1965 // Get the stack frame index of a 8 byte buffer. 1966 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 1967 1968 // word offset constant for Hi/Lo address computation 1969 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 1970 // set up Hi and Lo (into buffer) address based on endian 1971 SDValue Hi = StackSlot; 1972 SDValue Lo = DAG.getNode(ISD::ADD, dl, 1973 TLI.getPointerTy(), StackSlot, WordOff); 1974 if (TLI.isLittleEndian()) 1975 std::swap(Hi, Lo); 1976 1977 // if signed map to unsigned space 1978 SDValue Op0Mapped; 1979 if (isSigned) { 1980 // constant used to invert sign bit (signed to unsigned mapping) 1981 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 1982 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 1983 } else { 1984 Op0Mapped = Op0; 1985 } 1986 // store the lo of the constructed double - based on integer input 1987 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 1988 Op0Mapped, Lo, NULL, 0); 1989 // initial hi portion of constructed double 1990 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 1991 // store the hi of the constructed double - biased exponent 1992 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0); 1993 // load the constructed double 1994 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0); 1995 // FP constant to bias correct the final result 1996 SDValue Bias = DAG.getConstantFP(isSigned ? 1997 BitsToDouble(0x4330000080000000ULL) : 1998 BitsToDouble(0x4330000000000000ULL), 1999 MVT::f64); 2000 // subtract the bias 2001 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2002 // final result 2003 SDValue Result; 2004 // handle final rounding 2005 if (DestVT == MVT::f64) { 2006 // do nothing 2007 Result = Sub; 2008 } else if (DestVT.bitsLT(MVT::f64)) { 2009 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2010 DAG.getIntPtrConstant(0)); 2011 } else if (DestVT.bitsGT(MVT::f64)) { 2012 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2013 } 2014 return Result; 2015 } 2016 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2017 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2018 2019 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2020 Op0, DAG.getConstant(0, Op0.getValueType()), 2021 ISD::SETLT); 2022 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2023 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2024 SignSet, Four, Zero); 2025 2026 // If the sign bit of the integer is set, the large number will be treated 2027 // as a negative number. To counteract this, the dynamic code adds an 2028 // offset depending on the data type. 2029 uint64_t FF; 2030 switch (Op0.getValueType().getSimpleVT()) { 2031 default: assert(0 && "Unsupported integer type!"); 2032 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2033 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2034 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2035 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2036 } 2037 if (TLI.isLittleEndian()) FF <<= 32; 2038 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 2039 2040 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2041 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2042 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2043 Alignment = std::min(Alignment, 4u); 2044 SDValue FudgeInReg; 2045 if (DestVT == MVT::f32) 2046 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2047 PseudoSourceValue::getConstantPool(), 0, 2048 false, Alignment); 2049 else { 2050 FudgeInReg = 2051 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2052 DAG.getEntryNode(), CPIdx, 2053 PseudoSourceValue::getConstantPool(), 0, 2054 MVT::f32, false, Alignment)); 2055 } 2056 2057 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2058} 2059 2060/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2061/// *INT_TO_FP operation of the specified operand when the target requests that 2062/// we promote it. At this point, we know that the result and operand types are 2063/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2064/// operation that takes a larger input. 2065SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2066 MVT DestVT, 2067 bool isSigned, 2068 DebugLoc dl) { 2069 // First step, figure out the appropriate *INT_TO_FP operation to use. 2070 MVT NewInTy = LegalOp.getValueType(); 2071 2072 unsigned OpToUse = 0; 2073 2074 // Scan for the appropriate larger type to use. 2075 while (1) { 2076 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 2077 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2078 2079 // If the target supports SINT_TO_FP of this type, use it. 2080 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2081 OpToUse = ISD::SINT_TO_FP; 2082 break; 2083 } 2084 if (isSigned) continue; 2085 2086 // If the target supports UINT_TO_FP of this type, use it. 2087 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2088 OpToUse = ISD::UINT_TO_FP; 2089 break; 2090 } 2091 2092 // Otherwise, try a larger type. 2093 } 2094 2095 // Okay, we found the operation and type to use. Zero extend our input to the 2096 // desired type then run the operation on it. 2097 return DAG.getNode(OpToUse, dl, DestVT, 2098 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2099 dl, NewInTy, LegalOp)); 2100} 2101 2102/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2103/// FP_TO_*INT operation of the specified operand when the target requests that 2104/// we promote it. At this point, we know that the result and operand types are 2105/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2106/// operation that returns a larger result. 2107SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2108 MVT DestVT, 2109 bool isSigned, 2110 DebugLoc dl) { 2111 // First step, figure out the appropriate FP_TO*INT operation to use. 2112 MVT NewOutTy = DestVT; 2113 2114 unsigned OpToUse = 0; 2115 2116 // Scan for the appropriate larger type to use. 2117 while (1) { 2118 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 2119 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2120 2121 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2122 OpToUse = ISD::FP_TO_SINT; 2123 break; 2124 } 2125 2126 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2127 OpToUse = ISD::FP_TO_UINT; 2128 break; 2129 } 2130 2131 // Otherwise, try a larger type. 2132 } 2133 2134 2135 // Okay, we found the operation and type to use. 2136 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2137 2138 // Truncate the result of the extended FP_TO_*INT operation to the desired 2139 // size. 2140 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2141} 2142 2143/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2144/// 2145SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2146 MVT VT = Op.getValueType(); 2147 MVT SHVT = TLI.getShiftAmountTy(); 2148 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2149 switch (VT.getSimpleVT()) { 2150 default: LLVM_UNREACHABLE("Unhandled Expand type in BSWAP!"); 2151 case MVT::i16: 2152 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2153 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2154 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2155 case MVT::i32: 2156 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2157 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2158 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2159 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2160 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2161 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2162 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2163 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2164 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2165 case MVT::i64: 2166 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2167 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2168 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2169 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2170 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2171 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2172 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2173 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2174 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2175 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2176 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2177 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2178 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2179 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2180 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2181 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2182 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2183 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2184 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2185 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2186 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2187 } 2188} 2189 2190/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2191/// 2192SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2193 DebugLoc dl) { 2194 switch (Opc) { 2195 default: assert(0 && "Cannot expand this yet!"); 2196 case ISD::CTPOP: { 2197 static const uint64_t mask[6] = { 2198 0x5555555555555555ULL, 0x3333333333333333ULL, 2199 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2200 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2201 }; 2202 MVT VT = Op.getValueType(); 2203 MVT ShVT = TLI.getShiftAmountTy(); 2204 unsigned len = VT.getSizeInBits(); 2205 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2206 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2207 unsigned EltSize = VT.isVector() ? 2208 VT.getVectorElementType().getSizeInBits() : len; 2209 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2210 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2211 Op = DAG.getNode(ISD::ADD, dl, VT, 2212 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2213 DAG.getNode(ISD::AND, dl, VT, 2214 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2215 Tmp2)); 2216 } 2217 return Op; 2218 } 2219 case ISD::CTLZ: { 2220 // for now, we do this: 2221 // x = x | (x >> 1); 2222 // x = x | (x >> 2); 2223 // ... 2224 // x = x | (x >>16); 2225 // x = x | (x >>32); // for 64-bit input 2226 // return popcount(~x); 2227 // 2228 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2229 MVT VT = Op.getValueType(); 2230 MVT ShVT = TLI.getShiftAmountTy(); 2231 unsigned len = VT.getSizeInBits(); 2232 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2233 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2234 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2235 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2236 } 2237 Op = DAG.getNOT(dl, Op, VT); 2238 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2239 } 2240 case ISD::CTTZ: { 2241 // for now, we use: { return popcount(~x & (x - 1)); } 2242 // unless the target has ctlz but not ctpop, in which case we use: 2243 // { return 32 - nlz(~x & (x-1)); } 2244 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2245 MVT VT = Op.getValueType(); 2246 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2247 DAG.getNOT(dl, Op, VT), 2248 DAG.getNode(ISD::SUB, dl, VT, Op, 2249 DAG.getConstant(1, VT))); 2250 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2251 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2252 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2253 return DAG.getNode(ISD::SUB, dl, VT, 2254 DAG.getConstant(VT.getSizeInBits(), VT), 2255 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2256 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2257 } 2258 } 2259} 2260 2261void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2262 SmallVectorImpl<SDValue> &Results) { 2263 DebugLoc dl = Node->getDebugLoc(); 2264 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2265 switch (Node->getOpcode()) { 2266 case ISD::CTPOP: 2267 case ISD::CTLZ: 2268 case ISD::CTTZ: 2269 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2270 Results.push_back(Tmp1); 2271 break; 2272 case ISD::BSWAP: 2273 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2274 break; 2275 case ISD::FRAMEADDR: 2276 case ISD::RETURNADDR: 2277 case ISD::FRAME_TO_ARGS_OFFSET: 2278 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2279 break; 2280 case ISD::FLT_ROUNDS_: 2281 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2282 break; 2283 case ISD::EH_RETURN: 2284 case ISD::DECLARE: 2285 case ISD::DBG_LABEL: 2286 case ISD::EH_LABEL: 2287 case ISD::PREFETCH: 2288 case ISD::MEMBARRIER: 2289 case ISD::VAEND: 2290 Results.push_back(Node->getOperand(0)); 2291 break; 2292 case ISD::DBG_STOPPOINT: 2293 Results.push_back(ExpandDBG_STOPPOINT(Node)); 2294 break; 2295 case ISD::DYNAMIC_STACKALLOC: 2296 ExpandDYNAMIC_STACKALLOC(Node, Results); 2297 break; 2298 case ISD::MERGE_VALUES: 2299 for (unsigned i = 0; i < Node->getNumValues(); i++) 2300 Results.push_back(Node->getOperand(i)); 2301 break; 2302 case ISD::UNDEF: { 2303 MVT VT = Node->getValueType(0); 2304 if (VT.isInteger()) 2305 Results.push_back(DAG.getConstant(0, VT)); 2306 else if (VT.isFloatingPoint()) 2307 Results.push_back(DAG.getConstantFP(0, VT)); 2308 else 2309 assert(0 && "Unknown value type!"); 2310 break; 2311 } 2312 case ISD::TRAP: { 2313 // If this operation is not supported, lower it to 'abort()' call 2314 TargetLowering::ArgListTy Args; 2315 std::pair<SDValue, SDValue> CallResult = 2316 TLI.LowerCallTo(Node->getOperand(0), Type::VoidTy, 2317 false, false, false, false, 0, CallingConv::C, false, 2318 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2319 Args, DAG, dl); 2320 Results.push_back(CallResult.second); 2321 break; 2322 } 2323 case ISD::FP_ROUND: 2324 case ISD::BIT_CONVERT: 2325 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2326 Node->getValueType(0), dl); 2327 Results.push_back(Tmp1); 2328 break; 2329 case ISD::FP_EXTEND: 2330 Tmp1 = EmitStackConvert(Node->getOperand(0), 2331 Node->getOperand(0).getValueType(), 2332 Node->getValueType(0), dl); 2333 Results.push_back(Tmp1); 2334 break; 2335 case ISD::SIGN_EXTEND_INREG: { 2336 // NOTE: we could fall back on load/store here too for targets without 2337 // SAR. However, it is doubtful that any exist. 2338 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2339 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 2340 ExtraVT.getSizeInBits(); 2341 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2342 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2343 Node->getOperand(0), ShiftCst); 2344 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2345 Results.push_back(Tmp1); 2346 break; 2347 } 2348 case ISD::FP_ROUND_INREG: { 2349 // The only way we can lower this is to turn it into a TRUNCSTORE, 2350 // EXTLOAD pair, targetting a temporary location (a stack slot). 2351 2352 // NOTE: there is a choice here between constantly creating new stack 2353 // slots and always reusing the same one. We currently always create 2354 // new ones, as reuse may inhibit scheduling. 2355 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2356 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2357 Node->getValueType(0), dl); 2358 Results.push_back(Tmp1); 2359 break; 2360 } 2361 case ISD::SINT_TO_FP: 2362 case ISD::UINT_TO_FP: 2363 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2364 Node->getOperand(0), Node->getValueType(0), dl); 2365 Results.push_back(Tmp1); 2366 break; 2367 case ISD::FP_TO_UINT: { 2368 SDValue True, False; 2369 MVT VT = Node->getOperand(0).getValueType(); 2370 MVT NVT = Node->getValueType(0); 2371 const uint64_t zero[] = {0, 0}; 2372 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2373 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2374 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2375 Tmp1 = DAG.getConstantFP(apf, VT); 2376 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2377 Node->getOperand(0), 2378 Tmp1, ISD::SETLT); 2379 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2380 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2381 DAG.getNode(ISD::FSUB, dl, VT, 2382 Node->getOperand(0), Tmp1)); 2383 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2384 DAG.getConstant(x, NVT)); 2385 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2386 Results.push_back(Tmp1); 2387 break; 2388 } 2389 case ISD::VAARG: { 2390 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2391 MVT VT = Node->getValueType(0); 2392 Tmp1 = Node->getOperand(0); 2393 Tmp2 = Node->getOperand(1); 2394 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0); 2395 // Increment the pointer, VAList, to the next vaarg 2396 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2397 DAG.getConstant(TLI.getTargetData()-> 2398 getTypeAllocSize(VT.getTypeForMVT( 2399 *DAG.getContext())), 2400 TLI.getPointerTy())); 2401 // Store the incremented VAList to the legalized pointer 2402 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0); 2403 // Load the actual argument out of the pointer VAList 2404 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0)); 2405 Results.push_back(Results[0].getValue(1)); 2406 break; 2407 } 2408 case ISD::VACOPY: { 2409 // This defaults to loading a pointer from the input and storing it to the 2410 // output, returning the chain. 2411 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2412 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2413 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2414 Node->getOperand(2), VS, 0); 2415 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0); 2416 Results.push_back(Tmp1); 2417 break; 2418 } 2419 case ISD::EXTRACT_VECTOR_ELT: 2420 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2421 // This must be an access of the only element. Return it. 2422 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2423 Node->getOperand(0)); 2424 else 2425 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2426 Results.push_back(Tmp1); 2427 break; 2428 case ISD::EXTRACT_SUBVECTOR: 2429 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2430 break; 2431 case ISD::CONCAT_VECTORS: { 2432 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2433 break; 2434 } 2435 case ISD::SCALAR_TO_VECTOR: 2436 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2437 break; 2438 case ISD::INSERT_VECTOR_ELT: 2439 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2440 Node->getOperand(1), 2441 Node->getOperand(2), dl)); 2442 break; 2443 case ISD::VECTOR_SHUFFLE: { 2444 SmallVector<int, 8> Mask; 2445 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2446 2447 MVT VT = Node->getValueType(0); 2448 MVT EltVT = VT.getVectorElementType(); 2449 unsigned NumElems = VT.getVectorNumElements(); 2450 SmallVector<SDValue, 8> Ops; 2451 for (unsigned i = 0; i != NumElems; ++i) { 2452 if (Mask[i] < 0) { 2453 Ops.push_back(DAG.getUNDEF(EltVT)); 2454 continue; 2455 } 2456 unsigned Idx = Mask[i]; 2457 if (Idx < NumElems) 2458 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2459 Node->getOperand(0), 2460 DAG.getIntPtrConstant(Idx))); 2461 else 2462 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2463 Node->getOperand(1), 2464 DAG.getIntPtrConstant(Idx - NumElems))); 2465 } 2466 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2467 Results.push_back(Tmp1); 2468 break; 2469 } 2470 case ISD::EXTRACT_ELEMENT: { 2471 MVT OpTy = Node->getOperand(0).getValueType(); 2472 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2473 // 1 -> Hi 2474 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2475 DAG.getConstant(OpTy.getSizeInBits()/2, 2476 TLI.getShiftAmountTy())); 2477 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2478 } else { 2479 // 0 -> Lo 2480 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2481 Node->getOperand(0)); 2482 } 2483 Results.push_back(Tmp1); 2484 break; 2485 } 2486 case ISD::STACKSAVE: 2487 // Expand to CopyFromReg if the target set 2488 // StackPointerRegisterToSaveRestore. 2489 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2490 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2491 Node->getValueType(0))); 2492 Results.push_back(Results[0].getValue(1)); 2493 } else { 2494 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2495 Results.push_back(Node->getOperand(0)); 2496 } 2497 break; 2498 case ISD::STACKRESTORE: 2499 // Expand to CopyToReg if the target set 2500 // StackPointerRegisterToSaveRestore. 2501 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2502 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2503 Node->getOperand(1))); 2504 } else { 2505 Results.push_back(Node->getOperand(0)); 2506 } 2507 break; 2508 case ISD::FCOPYSIGN: 2509 Results.push_back(ExpandFCOPYSIGN(Node)); 2510 break; 2511 case ISD::FNEG: 2512 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2513 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2514 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2515 Node->getOperand(0)); 2516 Results.push_back(Tmp1); 2517 break; 2518 case ISD::FABS: { 2519 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2520 MVT VT = Node->getValueType(0); 2521 Tmp1 = Node->getOperand(0); 2522 Tmp2 = DAG.getConstantFP(0.0, VT); 2523 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2524 Tmp1, Tmp2, ISD::SETUGT); 2525 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2526 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2527 Results.push_back(Tmp1); 2528 break; 2529 } 2530 case ISD::FSQRT: 2531 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2532 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2533 break; 2534 case ISD::FSIN: 2535 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2536 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2537 break; 2538 case ISD::FCOS: 2539 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2540 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2541 break; 2542 case ISD::FLOG: 2543 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2544 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2545 break; 2546 case ISD::FLOG2: 2547 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2548 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2549 break; 2550 case ISD::FLOG10: 2551 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2552 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2553 break; 2554 case ISD::FEXP: 2555 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2556 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2557 break; 2558 case ISD::FEXP2: 2559 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2560 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2561 break; 2562 case ISD::FTRUNC: 2563 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2564 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2565 break; 2566 case ISD::FFLOOR: 2567 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2568 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2569 break; 2570 case ISD::FCEIL: 2571 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2572 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2573 break; 2574 case ISD::FRINT: 2575 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2576 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2577 break; 2578 case ISD::FNEARBYINT: 2579 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2580 RTLIB::NEARBYINT_F64, 2581 RTLIB::NEARBYINT_F80, 2582 RTLIB::NEARBYINT_PPCF128)); 2583 break; 2584 case ISD::FPOWI: 2585 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2586 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2587 break; 2588 case ISD::FPOW: 2589 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2590 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2591 break; 2592 case ISD::FDIV: 2593 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2594 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2595 break; 2596 case ISD::FREM: 2597 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2598 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2599 break; 2600 case ISD::ConstantFP: { 2601 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2602 // Check to see if this FP immediate is already legal. 2603 bool isLegal = false; 2604 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 2605 E = TLI.legal_fpimm_end(); I != E; ++I) { 2606 if (CFP->isExactlyValue(*I)) { 2607 isLegal = true; 2608 break; 2609 } 2610 } 2611 // If this is a legal constant, turn it into a TargetConstantFP node. 2612 if (isLegal) 2613 Results.push_back(SDValue(Node, 0)); 2614 else 2615 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2616 break; 2617 } 2618 case ISD::EHSELECTION: { 2619 unsigned Reg = TLI.getExceptionSelectorRegister(); 2620 assert(Reg && "Can't expand to unknown register!"); 2621 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2622 Node->getValueType(0))); 2623 Results.push_back(Results[0].getValue(1)); 2624 break; 2625 } 2626 case ISD::EXCEPTIONADDR: { 2627 unsigned Reg = TLI.getExceptionAddressRegister(); 2628 assert(Reg && "Can't expand to unknown register!"); 2629 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2630 Node->getValueType(0))); 2631 Results.push_back(Results[0].getValue(1)); 2632 break; 2633 } 2634 case ISD::SUB: { 2635 MVT VT = Node->getValueType(0); 2636 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2637 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2638 "Don't know how to expand this subtraction!"); 2639 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2640 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2641 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2642 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2643 break; 2644 } 2645 case ISD::UREM: 2646 case ISD::SREM: { 2647 MVT VT = Node->getValueType(0); 2648 SDVTList VTs = DAG.getVTList(VT, VT); 2649 bool isSigned = Node->getOpcode() == ISD::SREM; 2650 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2651 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2652 Tmp2 = Node->getOperand(0); 2653 Tmp3 = Node->getOperand(1); 2654 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2655 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2656 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2657 // X % Y -> X-X/Y*Y 2658 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2659 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2660 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2661 } else if (isSigned) { 2662 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SREM_I16, RTLIB::SREM_I32, 2663 RTLIB::SREM_I64, RTLIB::SREM_I128); 2664 } else { 2665 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UREM_I16, RTLIB::UREM_I32, 2666 RTLIB::UREM_I64, RTLIB::UREM_I128); 2667 } 2668 Results.push_back(Tmp1); 2669 break; 2670 } 2671 case ISD::UDIV: 2672 case ISD::SDIV: { 2673 bool isSigned = Node->getOpcode() == ISD::SDIV; 2674 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2675 MVT VT = Node->getValueType(0); 2676 SDVTList VTs = DAG.getVTList(VT, VT); 2677 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2678 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2679 Node->getOperand(1)); 2680 else if (isSigned) 2681 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2682 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2683 else 2684 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2685 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2686 Results.push_back(Tmp1); 2687 break; 2688 } 2689 case ISD::MULHU: 2690 case ISD::MULHS: { 2691 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2692 ISD::SMUL_LOHI; 2693 MVT VT = Node->getValueType(0); 2694 SDVTList VTs = DAG.getVTList(VT, VT); 2695 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2696 "If this wasn't legal, it shouldn't have been created!"); 2697 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 2698 Node->getOperand(1)); 2699 Results.push_back(Tmp1.getValue(1)); 2700 break; 2701 } 2702 case ISD::MUL: { 2703 MVT VT = Node->getValueType(0); 2704 SDVTList VTs = DAG.getVTList(VT, VT); 2705 // See if multiply or divide can be lowered using two-result operations. 2706 // We just need the low half of the multiply; try both the signed 2707 // and unsigned forms. If the target supports both SMUL_LOHI and 2708 // UMUL_LOHI, form a preference by checking which forms of plain 2709 // MULH it supports. 2710 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 2711 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 2712 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 2713 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 2714 unsigned OpToUse = 0; 2715 if (HasSMUL_LOHI && !HasMULHS) { 2716 OpToUse = ISD::SMUL_LOHI; 2717 } else if (HasUMUL_LOHI && !HasMULHU) { 2718 OpToUse = ISD::UMUL_LOHI; 2719 } else if (HasSMUL_LOHI) { 2720 OpToUse = ISD::SMUL_LOHI; 2721 } else if (HasUMUL_LOHI) { 2722 OpToUse = ISD::UMUL_LOHI; 2723 } 2724 if (OpToUse) { 2725 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 2726 Node->getOperand(1))); 2727 break; 2728 } 2729 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::MUL_I16, RTLIB::MUL_I32, 2730 RTLIB::MUL_I64, RTLIB::MUL_I128); 2731 Results.push_back(Tmp1); 2732 break; 2733 } 2734 case ISD::SADDO: 2735 case ISD::SSUBO: { 2736 SDValue LHS = Node->getOperand(0); 2737 SDValue RHS = Node->getOperand(1); 2738 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 2739 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2740 LHS, RHS); 2741 Results.push_back(Sum); 2742 MVT OType = Node->getValueType(1); 2743 2744 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 2745 2746 // LHSSign -> LHS >= 0 2747 // RHSSign -> RHS >= 0 2748 // SumSign -> Sum >= 0 2749 // 2750 // Add: 2751 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 2752 // Sub: 2753 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 2754 // 2755 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 2756 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 2757 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 2758 Node->getOpcode() == ISD::SADDO ? 2759 ISD::SETEQ : ISD::SETNE); 2760 2761 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 2762 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 2763 2764 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 2765 Results.push_back(Cmp); 2766 break; 2767 } 2768 case ISD::UADDO: 2769 case ISD::USUBO: { 2770 SDValue LHS = Node->getOperand(0); 2771 SDValue RHS = Node->getOperand(1); 2772 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 2773 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2774 LHS, RHS); 2775 Results.push_back(Sum); 2776 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 2777 Node->getOpcode () == ISD::UADDO ? 2778 ISD::SETULT : ISD::SETUGT)); 2779 break; 2780 } 2781 case ISD::UMULO: 2782 case ISD::SMULO: { 2783 MVT VT = Node->getValueType(0); 2784 SDValue LHS = Node->getOperand(0); 2785 SDValue RHS = Node->getOperand(1); 2786 SDValue BottomHalf; 2787 SDValue TopHalf; 2788 static unsigned Ops[2][3] = 2789 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 2790 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 2791 bool isSigned = Node->getOpcode() == ISD::SMULO; 2792 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 2793 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 2794 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 2795 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 2796 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 2797 RHS); 2798 TopHalf = BottomHalf.getValue(1); 2799 } else if (TLI.isTypeLegal(MVT::getIntegerVT(VT.getSizeInBits() * 2))) { 2800 MVT WideVT = MVT::getIntegerVT(VT.getSizeInBits() * 2); 2801 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 2802 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 2803 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 2804 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2805 DAG.getIntPtrConstant(0)); 2806 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2807 DAG.getIntPtrConstant(1)); 2808 } else { 2809 // FIXME: We should be able to fall back to a libcall with an illegal 2810 // type in some cases cases. 2811 // Also, we can fall back to a division in some cases, but that's a big 2812 // performance hit in the general case. 2813 assert(0 && "Don't know how to expand this operation yet!"); 2814 } 2815 if (isSigned) { 2816 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); 2817 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 2818 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 2819 ISD::SETNE); 2820 } else { 2821 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 2822 DAG.getConstant(0, VT), ISD::SETNE); 2823 } 2824 Results.push_back(BottomHalf); 2825 Results.push_back(TopHalf); 2826 break; 2827 } 2828 case ISD::BUILD_PAIR: { 2829 MVT PairTy = Node->getValueType(0); 2830 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 2831 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 2832 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 2833 DAG.getConstant(PairTy.getSizeInBits()/2, 2834 TLI.getShiftAmountTy())); 2835 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 2836 break; 2837 } 2838 case ISD::SELECT: 2839 Tmp1 = Node->getOperand(0); 2840 Tmp2 = Node->getOperand(1); 2841 Tmp3 = Node->getOperand(2); 2842 if (Tmp1.getOpcode() == ISD::SETCC) { 2843 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 2844 Tmp2, Tmp3, 2845 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2846 } else { 2847 Tmp1 = DAG.getSelectCC(dl, Tmp1, 2848 DAG.getConstant(0, Tmp1.getValueType()), 2849 Tmp2, Tmp3, ISD::SETNE); 2850 } 2851 Results.push_back(Tmp1); 2852 break; 2853 case ISD::BR_JT: { 2854 SDValue Chain = Node->getOperand(0); 2855 SDValue Table = Node->getOperand(1); 2856 SDValue Index = Node->getOperand(2); 2857 2858 MVT PTy = TLI.getPointerTy(); 2859 MachineFunction &MF = DAG.getMachineFunction(); 2860 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 2861 Index= DAG.getNode(ISD::MUL, dl, PTy, 2862 Index, DAG.getConstant(EntrySize, PTy)); 2863 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2864 2865 MVT MemVT = MVT::getIntegerVT(EntrySize * 8); 2866 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 2867 PseudoSourceValue::getJumpTable(), 0, MemVT); 2868 Addr = LD; 2869 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2870 // For PIC, the sequence is: 2871 // BRIND(load(Jumptable + index) + RelocBase) 2872 // RelocBase can be JumpTable, GOT or some sort of global base. 2873 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 2874 TLI.getPICJumpTableRelocBase(Table, DAG)); 2875 } 2876 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 2877 Results.push_back(Tmp1); 2878 break; 2879 } 2880 case ISD::BRCOND: 2881 // Expand brcond's setcc into its constituent parts and create a BR_CC 2882 // Node. 2883 Tmp1 = Node->getOperand(0); 2884 Tmp2 = Node->getOperand(1); 2885 if (Tmp2.getOpcode() == ISD::SETCC) { 2886 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 2887 Tmp1, Tmp2.getOperand(2), 2888 Tmp2.getOperand(0), Tmp2.getOperand(1), 2889 Node->getOperand(2)); 2890 } else { 2891 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 2892 DAG.getCondCode(ISD::SETNE), Tmp2, 2893 DAG.getConstant(0, Tmp2.getValueType()), 2894 Node->getOperand(2)); 2895 } 2896 Results.push_back(Tmp1); 2897 break; 2898 case ISD::SETCC: { 2899 Tmp1 = Node->getOperand(0); 2900 Tmp2 = Node->getOperand(1); 2901 Tmp3 = Node->getOperand(2); 2902 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 2903 2904 // If we expanded the SETCC into an AND/OR, return the new node 2905 if (Tmp2.getNode() == 0) { 2906 Results.push_back(Tmp1); 2907 break; 2908 } 2909 2910 // Otherwise, SETCC for the given comparison type must be completely 2911 // illegal; expand it into a SELECT_CC. 2912 MVT VT = Node->getValueType(0); 2913 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 2914 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 2915 Results.push_back(Tmp1); 2916 break; 2917 } 2918 case ISD::SELECT_CC: { 2919 Tmp1 = Node->getOperand(0); // LHS 2920 Tmp2 = Node->getOperand(1); // RHS 2921 Tmp3 = Node->getOperand(2); // True 2922 Tmp4 = Node->getOperand(3); // False 2923 SDValue CC = Node->getOperand(4); 2924 2925 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 2926 Tmp1, Tmp2, CC, dl); 2927 2928 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 2929 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2930 CC = DAG.getCondCode(ISD::SETNE); 2931 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 2932 Tmp3, Tmp4, CC); 2933 Results.push_back(Tmp1); 2934 break; 2935 } 2936 case ISD::BR_CC: { 2937 Tmp1 = Node->getOperand(0); // Chain 2938 Tmp2 = Node->getOperand(2); // LHS 2939 Tmp3 = Node->getOperand(3); // RHS 2940 Tmp4 = Node->getOperand(1); // CC 2941 2942 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 2943 Tmp2, Tmp3, Tmp4, dl); 2944 LastCALLSEQ_END = DAG.getEntryNode(); 2945 2946 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 2947 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 2948 Tmp4 = DAG.getCondCode(ISD::SETNE); 2949 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 2950 Tmp3, Node->getOperand(4)); 2951 Results.push_back(Tmp1); 2952 break; 2953 } 2954 case ISD::GLOBAL_OFFSET_TABLE: 2955 case ISD::GlobalAddress: 2956 case ISD::GlobalTLSAddress: 2957 case ISD::ExternalSymbol: 2958 case ISD::ConstantPool: 2959 case ISD::JumpTable: 2960 case ISD::INTRINSIC_W_CHAIN: 2961 case ISD::INTRINSIC_WO_CHAIN: 2962 case ISD::INTRINSIC_VOID: 2963 // FIXME: Custom lowering for these operations shouldn't return null! 2964 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2965 Results.push_back(SDValue(Node, i)); 2966 break; 2967 } 2968} 2969void SelectionDAGLegalize::PromoteNode(SDNode *Node, 2970 SmallVectorImpl<SDValue> &Results) { 2971 MVT OVT = Node->getValueType(0); 2972 if (Node->getOpcode() == ISD::UINT_TO_FP || 2973 Node->getOpcode() == ISD::SINT_TO_FP) { 2974 OVT = Node->getOperand(0).getValueType(); 2975 } 2976 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2977 DebugLoc dl = Node->getDebugLoc(); 2978 SDValue Tmp1, Tmp2, Tmp3; 2979 switch (Node->getOpcode()) { 2980 case ISD::CTTZ: 2981 case ISD::CTLZ: 2982 case ISD::CTPOP: 2983 // Zero extend the argument. 2984 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 2985 // Perform the larger operation. 2986 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1); 2987 if (Node->getOpcode() == ISD::CTTZ) { 2988 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2989 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2990 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 2991 ISD::SETEQ); 2992 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 2993 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 2994 } else if (Node->getOpcode() == ISD::CTLZ) { 2995 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2996 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 2997 DAG.getConstant(NVT.getSizeInBits() - 2998 OVT.getSizeInBits(), NVT)); 2999 } 3000 Results.push_back(Tmp1); 3001 break; 3002 case ISD::BSWAP: { 3003 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3004 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); 3005 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3006 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3007 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3008 Results.push_back(Tmp1); 3009 break; 3010 } 3011 case ISD::FP_TO_UINT: 3012 case ISD::FP_TO_SINT: 3013 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3014 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3015 Results.push_back(Tmp1); 3016 break; 3017 case ISD::UINT_TO_FP: 3018 case ISD::SINT_TO_FP: 3019 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3020 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3021 Results.push_back(Tmp1); 3022 break; 3023 case ISD::AND: 3024 case ISD::OR: 3025 case ISD::XOR: 3026 assert(OVT.isVector() && "Don't know how to promote scalar logic ops"); 3027 // Bit convert each of the values to the new type. 3028 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3029 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3030 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3031 // Bit convert the result back the original type. 3032 Results.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1)); 3033 break; 3034 case ISD::SELECT: 3035 unsigned ExtOp, TruncOp; 3036 if (Node->getValueType(0).isVector()) { 3037 ExtOp = ISD::BIT_CONVERT; 3038 TruncOp = ISD::BIT_CONVERT; 3039 } else if (Node->getValueType(0).isInteger()) { 3040 ExtOp = ISD::ANY_EXTEND; 3041 TruncOp = ISD::TRUNCATE; 3042 } else { 3043 ExtOp = ISD::FP_EXTEND; 3044 TruncOp = ISD::FP_ROUND; 3045 } 3046 Tmp1 = Node->getOperand(0); 3047 // Promote each of the values to the new type. 3048 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3049 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3050 // Perform the larger operation, then round down. 3051 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3052 if (TruncOp != ISD::FP_ROUND) 3053 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3054 else 3055 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3056 DAG.getIntPtrConstant(0)); 3057 Results.push_back(Tmp1); 3058 break; 3059 case ISD::VECTOR_SHUFFLE: { 3060 SmallVector<int, 8> Mask; 3061 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3062 3063 // Cast the two input vectors. 3064 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3065 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3066 3067 // Convert the shuffle mask to the right # elements. 3068 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3069 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3070 Results.push_back(Tmp1); 3071 break; 3072 } 3073 case ISD::SETCC: { 3074 // First step, figure out the appropriate operation to use. 3075 // Allow SETCC to not be supported for all legal data types 3076 // Mostly this targets FP 3077 MVT NewInTy = Node->getOperand(0).getValueType(); 3078 MVT OldVT = NewInTy; OldVT = OldVT; 3079 3080 // Scan for the appropriate larger type to use. 3081 while (1) { 3082 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 3083 3084 assert(NewInTy.isInteger() == OldVT.isInteger() && 3085 "Fell off of the edge of the integer world"); 3086 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 3087 "Fell off of the edge of the floating point world"); 3088 3089 // If the target supports SETCC of this type, use it. 3090 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy)) 3091 break; 3092 } 3093 if (NewInTy.isInteger()) 3094 assert(0 && "Cannot promote Legal Integer SETCC yet"); 3095 else { 3096 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1); 3097 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2); 3098 } 3099 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3100 Tmp1, Tmp2, Node->getOperand(2))); 3101 break; 3102 } 3103 } 3104} 3105 3106// SelectionDAG::Legalize - This is the entry point for the file. 3107// 3108void SelectionDAG::Legalize(bool TypesNeedLegalizing, 3109 CodeGenOpt::Level OptLevel) { 3110 /// run - This is the main entry point to this class. 3111 /// 3112 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3113} 3114 3115