LegalizeDAG.cpp revision ddb45ea7c3b1b064b732f37ae4fea58e9299058d
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/DwarfWriter.h" 20#include "llvm/Analysis/DebugInfo.h" 21#include "llvm/CodeGen/PseudoSourceValue.h" 22#include "llvm/Target/TargetFrameInfo.h" 23#include "llvm/Target/TargetLowering.h" 24#include "llvm/Target/TargetData.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Target/TargetSubtarget.h" 28#include "llvm/CallingConv.h" 29#include "llvm/Constants.h" 30#include "llvm/DerivedTypes.h" 31#include "llvm/Function.h" 32#include "llvm/GlobalVariable.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Compiler.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/ADT/DenseMap.h" 37#include "llvm/ADT/SmallVector.h" 38#include "llvm/ADT/SmallPtrSet.h" 39#include <map> 40using namespace llvm; 41 42//===----------------------------------------------------------------------===// 43/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 44/// hacks on it until the target machine can handle it. This involves 45/// eliminating value sizes the machine cannot handle (promoting small sizes to 46/// large sizes or splitting up large values into small values) as well as 47/// eliminating operations the machine cannot handle. 48/// 49/// This code also does a small amount of optimization and recognition of idioms 50/// as part of its processing. For example, if a target does not support a 51/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 52/// will attempt merge setcc and brc instructions into brcc's. 53/// 54namespace { 55class VISIBILITY_HIDDEN SelectionDAGLegalize { 56 TargetLowering &TLI; 57 SelectionDAG &DAG; 58 CodeGenOpt::Level OptLevel; 59 60 // Libcall insertion helpers. 61 62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 63 /// legalized. We use this to ensure that calls are properly serialized 64 /// against each other, including inserted libcalls. 65 SDValue LastCALLSEQ_END; 66 67 /// IsLegalizingCall - This member is used *only* for purposes of providing 68 /// helpful assertions that a libcall isn't created while another call is 69 /// being legalized (which could lead to non-serialized call sequences). 70 bool IsLegalizingCall; 71 72 enum LegalizeAction { 73 Legal, // The target natively supports this operation. 74 Promote, // This operation should be executed in a larger type. 75 Expand // Try to expand this to other ops, otherwise use a libcall. 76 }; 77 78 /// ValueTypeActions - This is a bitvector that contains two bits for each 79 /// value type, where the two bits correspond to the LegalizeAction enum. 80 /// This can be queried with "getTypeAction(VT)". 81 TargetLowering::ValueTypeActionImpl ValueTypeActions; 82 83 /// LegalizedNodes - For nodes that are of legal width, and that have more 84 /// than one use, this map indicates what regularized operand to use. This 85 /// allows us to avoid legalizing the same thing more than once. 86 DenseMap<SDValue, SDValue> LegalizedNodes; 87 88 void AddLegalizedOperand(SDValue From, SDValue To) { 89 LegalizedNodes.insert(std::make_pair(From, To)); 90 // If someone requests legalization of the new node, return itself. 91 if (From != To) 92 LegalizedNodes.insert(std::make_pair(To, To)); 93 } 94 95public: 96 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 97 98 /// getTypeAction - Return how we should legalize values of this type, either 99 /// it is already legal or we need to expand it into multiple registers of 100 /// smaller integer type, or we need to promote it to a larger type. 101 LegalizeAction getTypeAction(MVT VT) const { 102 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 103 } 104 105 /// isTypeLegal - Return true if this type is legal on this target. 106 /// 107 bool isTypeLegal(MVT VT) const { 108 return getTypeAction(VT) == Legal; 109 } 110 111 void LegalizeDAG(); 112 113private: 114 /// HandleOp - Legalize, Promote, or Expand the specified operand as 115 /// appropriate for its type. 116 void HandleOp(SDValue Op); 117 118 /// LegalizeOp - We know that the specified value has a legal type. 119 /// Recursively ensure that the operands have legal types, then return the 120 /// result. 121 SDValue LegalizeOp(SDValue O); 122 123 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 124 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 125 /// is necessary to spill the vector being inserted into to memory, perform 126 /// the insert there, and then read the result back. 127 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 128 SDValue Idx, DebugLoc dl); 129 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 130 SDValue Idx, DebugLoc dl); 131 132 /// Useful 16 element vector type that is used to pass operands for widening. 133 typedef SmallVector<SDValue, 16> SDValueVector; 134 135 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 136 /// performs the same shuffe in terms of order or result bytes, but on a type 137 /// whose vector element type is narrower than the original shuffle type. 138 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 139 SDValue ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl, 140 SDValue N1, SDValue N2, 141 SmallVectorImpl<int> &Mask) const; 142 143 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 144 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 145 146 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC, 147 DebugLoc dl); 148 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 149 DebugLoc dl); 150 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 151 DebugLoc dl) { 152 LegalizeSetCCOperands(LHS, RHS, CC, dl); 153 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl); 154 } 155 156 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 157 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 158 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 159 RTLIB::Libcall Call_PPCF128); 160 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, RTLIB::Libcall Call_I16, 161 RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64, 162 RTLIB::Libcall Call_I128); 163 164 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl); 165 SDValue ExpandBUILD_VECTOR(SDNode *Node); 166 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 167 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT, 168 DebugLoc dl); 169 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned, 170 DebugLoc dl); 171 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned, 172 DebugLoc dl); 173 174 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 175 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 176 177 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 178 179 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 180 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 181}; 182} 183 184/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 185/// performs the same shuffe in terms of order or result bytes, but on a type 186/// whose vector element type is narrower than the original shuffle type. 187/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 188SDValue 189SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl, 190 SDValue N1, SDValue N2, 191 SmallVectorImpl<int> &Mask) const { 192 MVT EltVT = NVT.getVectorElementType(); 193 unsigned NumMaskElts = VT.getVectorNumElements(); 194 unsigned NumDestElts = NVT.getVectorNumElements(); 195 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 196 197 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 198 199 if (NumEltsGrowth == 1) 200 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 201 202 SmallVector<int, 8> NewMask; 203 for (unsigned i = 0; i != NumMaskElts; ++i) { 204 int Idx = Mask[i]; 205 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 206 if (Idx < 0) 207 NewMask.push_back(-1); 208 else 209 NewMask.push_back(Idx * NumEltsGrowth + j); 210 } 211 } 212 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 213 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 214 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 215} 216 217SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 218 CodeGenOpt::Level ol) 219 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), 220 ValueTypeActions(TLI.getValueTypeActions()) { 221 assert(MVT::LAST_VALUETYPE <= 32 && 222 "Too many value types for ValueTypeActions to hold!"); 223} 224 225void SelectionDAGLegalize::LegalizeDAG() { 226 LastCALLSEQ_END = DAG.getEntryNode(); 227 IsLegalizingCall = false; 228 229 // The legalize process is inherently a bottom-up recursive process (users 230 // legalize their uses before themselves). Given infinite stack space, we 231 // could just start legalizing on the root and traverse the whole graph. In 232 // practice however, this causes us to run out of stack space on large basic 233 // blocks. To avoid this problem, compute an ordering of the nodes where each 234 // node is only legalized after all of its operands are legalized. 235 DAG.AssignTopologicalOrder(); 236 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 237 E = prior(DAG.allnodes_end()); I != next(E); ++I) 238 HandleOp(SDValue(I, 0)); 239 240 // Finally, it's possible the root changed. Get the new root. 241 SDValue OldRoot = DAG.getRoot(); 242 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 243 DAG.setRoot(LegalizedNodes[OldRoot]); 244 245 LegalizedNodes.clear(); 246 247 // Remove dead nodes now. 248 DAG.RemoveDeadNodes(); 249} 250 251 252/// FindCallEndFromCallStart - Given a chained node that is part of a call 253/// sequence, find the CALLSEQ_END node that terminates the call sequence. 254static SDNode *FindCallEndFromCallStart(SDNode *Node) { 255 if (Node->getOpcode() == ISD::CALLSEQ_END) 256 return Node; 257 if (Node->use_empty()) 258 return 0; // No CallSeqEnd 259 260 // The chain is usually at the end. 261 SDValue TheChain(Node, Node->getNumValues()-1); 262 if (TheChain.getValueType() != MVT::Other) { 263 // Sometimes it's at the beginning. 264 TheChain = SDValue(Node, 0); 265 if (TheChain.getValueType() != MVT::Other) { 266 // Otherwise, hunt for it. 267 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 268 if (Node->getValueType(i) == MVT::Other) { 269 TheChain = SDValue(Node, i); 270 break; 271 } 272 273 // Otherwise, we walked into a node without a chain. 274 if (TheChain.getValueType() != MVT::Other) 275 return 0; 276 } 277 } 278 279 for (SDNode::use_iterator UI = Node->use_begin(), 280 E = Node->use_end(); UI != E; ++UI) { 281 282 // Make sure to only follow users of our token chain. 283 SDNode *User = *UI; 284 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 285 if (User->getOperand(i) == TheChain) 286 if (SDNode *Result = FindCallEndFromCallStart(User)) 287 return Result; 288 } 289 return 0; 290} 291 292/// FindCallStartFromCallEnd - Given a chained node that is part of a call 293/// sequence, find the CALLSEQ_START node that initiates the call sequence. 294static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 295 assert(Node && "Didn't find callseq_start for a call??"); 296 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 297 298 assert(Node->getOperand(0).getValueType() == MVT::Other && 299 "Node doesn't have a token chain argument!"); 300 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 301} 302 303/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 304/// see if any uses can reach Dest. If no dest operands can get to dest, 305/// legalize them, legalize ourself, and return false, otherwise, return true. 306/// 307/// Keep track of the nodes we fine that actually do lead to Dest in 308/// NodesLeadingTo. This avoids retraversing them exponential number of times. 309/// 310bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 311 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 312 if (N == Dest) return true; // N certainly leads to Dest :) 313 314 // If we've already processed this node and it does lead to Dest, there is no 315 // need to reprocess it. 316 if (NodesLeadingTo.count(N)) return true; 317 318 // If the first result of this node has been already legalized, then it cannot 319 // reach N. 320 if (LegalizedNodes.count(SDValue(N, 0))) return false; 321 322 // Okay, this node has not already been legalized. Check and legalize all 323 // operands. If none lead to Dest, then we can legalize this node. 324 bool OperandsLeadToDest = false; 325 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 326 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 327 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 328 329 if (OperandsLeadToDest) { 330 NodesLeadingTo.insert(N); 331 return true; 332 } 333 334 // Okay, this node looks safe, legalize it and return false. 335 HandleOp(SDValue(N, 0)); 336 return false; 337} 338 339/// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as 340/// appropriate for its type. 341void SelectionDAGLegalize::HandleOp(SDValue Op) { 342 // Don't touch TargetConstants 343 if (Op.getOpcode() == ISD::TargetConstant) 344 return; 345 MVT VT = Op.getValueType(); 346 // We should never see any illegal result types here. 347 assert(isTypeLegal(VT) && "Illegal type introduced after type legalization?"); 348 (void)LegalizeOp(Op); 349} 350 351/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 352/// a load from the constant pool. 353static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 354 SelectionDAG &DAG, const TargetLowering &TLI) { 355 bool Extend = false; 356 DebugLoc dl = CFP->getDebugLoc(); 357 358 // If a FP immediate is precise when represented as a float and if the 359 // target can do an extending load from float to double, we put it into 360 // the constant pool as a float, even if it's is statically typed as a 361 // double. This shrinks FP constants and canonicalizes them for targets where 362 // an FP extending load is the same cost as a normal load (such as on the x87 363 // fp stack or PPC FP unit). 364 MVT VT = CFP->getValueType(0); 365 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 366 if (!UseCP) { 367 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 368 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 369 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 370 } 371 372 MVT OrigVT = VT; 373 MVT SVT = VT; 374 while (SVT != MVT::f32) { 375 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 376 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 377 // Only do this if the target has a native EXTLOAD instruction from 378 // smaller type. 379 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 380 TLI.ShouldShrinkFPConstant(OrigVT)) { 381 const Type *SType = SVT.getTypeForMVT(); 382 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 383 VT = SVT; 384 Extend = true; 385 } 386 } 387 388 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 389 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 390 if (Extend) 391 return DAG.getExtLoad(ISD::EXTLOAD, dl, 392 OrigVT, DAG.getEntryNode(), 393 CPIdx, PseudoSourceValue::getConstantPool(), 394 0, VT, false, Alignment); 395 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 396 PseudoSourceValue::getConstantPool(), 0, false, Alignment); 397} 398 399/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 400static 401SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 402 const TargetLowering &TLI) { 403 SDValue Chain = ST->getChain(); 404 SDValue Ptr = ST->getBasePtr(); 405 SDValue Val = ST->getValue(); 406 MVT VT = Val.getValueType(); 407 int Alignment = ST->getAlignment(); 408 int SVOffset = ST->getSrcValueOffset(); 409 DebugLoc dl = ST->getDebugLoc(); 410 if (ST->getMemoryVT().isFloatingPoint() || 411 ST->getMemoryVT().isVector()) { 412 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits()); 413 if (TLI.isTypeLegal(intVT)) { 414 // Expand to a bitconvert of the value to the integer type of the 415 // same size, then a (misaligned) int store. 416 // FIXME: Does not handle truncating floating point stores! 417 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 418 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 419 SVOffset, ST->isVolatile(), Alignment); 420 } else { 421 // Do a (aligned) store to a stack slot, then copy from the stack slot 422 // to the final destination using (unaligned) integer loads and stores. 423 MVT StoredVT = ST->getMemoryVT(); 424 MVT RegVT = 425 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits())); 426 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 427 unsigned RegBytes = RegVT.getSizeInBits() / 8; 428 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 429 430 // Make sure the stack slot is also aligned for the register type. 431 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 432 433 // Perform the original store, only redirected to the stack slot. 434 SDValue Store = DAG.getTruncStore(Chain, dl, 435 Val, StackPtr, NULL, 0, StoredVT); 436 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 437 SmallVector<SDValue, 8> Stores; 438 unsigned Offset = 0; 439 440 // Do all but one copies using the full register width. 441 for (unsigned i = 1; i < NumRegs; i++) { 442 // Load one integer register's worth from the stack slot. 443 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0); 444 // Store it to the final location. Remember the store. 445 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 446 ST->getSrcValue(), SVOffset + Offset, 447 ST->isVolatile(), 448 MinAlign(ST->getAlignment(), Offset))); 449 // Increment the pointers. 450 Offset += RegBytes; 451 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 452 Increment); 453 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 454 } 455 456 // The last store may be partial. Do a truncating store. On big-endian 457 // machines this requires an extending load from the stack slot to ensure 458 // that the bits are in the right place. 459 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset)); 460 461 // Load from the stack slot. 462 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 463 NULL, 0, MemVT); 464 465 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 466 ST->getSrcValue(), SVOffset + Offset, 467 MemVT, ST->isVolatile(), 468 MinAlign(ST->getAlignment(), Offset))); 469 // The order of the stores doesn't matter - say it with a TokenFactor. 470 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 471 Stores.size()); 472 } 473 } 474 assert(ST->getMemoryVT().isInteger() && 475 !ST->getMemoryVT().isVector() && 476 "Unaligned store of unknown type."); 477 // Get the half-size VT 478 MVT NewStoredVT = 479 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 480 int NumBits = NewStoredVT.getSizeInBits(); 481 int IncrementSize = NumBits / 8; 482 483 // Divide the stored value in two parts. 484 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 485 SDValue Lo = Val; 486 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 487 488 // Store the two parts 489 SDValue Store1, Store2; 490 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 491 ST->getSrcValue(), SVOffset, NewStoredVT, 492 ST->isVolatile(), Alignment); 493 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 494 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 495 Alignment = MinAlign(Alignment, IncrementSize); 496 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 497 ST->getSrcValue(), SVOffset + IncrementSize, 498 NewStoredVT, ST->isVolatile(), Alignment); 499 500 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 501} 502 503/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 504static 505SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 506 const TargetLowering &TLI) { 507 int SVOffset = LD->getSrcValueOffset(); 508 SDValue Chain = LD->getChain(); 509 SDValue Ptr = LD->getBasePtr(); 510 MVT VT = LD->getValueType(0); 511 MVT LoadedVT = LD->getMemoryVT(); 512 DebugLoc dl = LD->getDebugLoc(); 513 if (VT.isFloatingPoint() || VT.isVector()) { 514 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits()); 515 if (TLI.isTypeLegal(intVT)) { 516 // Expand to a (misaligned) integer load of the same size, 517 // then bitconvert to floating point or vector. 518 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 519 SVOffset, LD->isVolatile(), 520 LD->getAlignment()); 521 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 522 if (VT.isFloatingPoint() && LoadedVT != VT) 523 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 524 525 SDValue Ops[] = { Result, Chain }; 526 return DAG.getMergeValues(Ops, 2, dl); 527 } else { 528 // Copy the value to a (aligned) stack slot using (unaligned) integer 529 // loads and stores, then do a (aligned) load from the stack slot. 530 MVT RegVT = TLI.getRegisterType(intVT); 531 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 532 unsigned RegBytes = RegVT.getSizeInBits() / 8; 533 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 534 535 // Make sure the stack slot is also aligned for the register type. 536 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 537 538 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 539 SmallVector<SDValue, 8> Stores; 540 SDValue StackPtr = StackBase; 541 unsigned Offset = 0; 542 543 // Do all but one copies using the full register width. 544 for (unsigned i = 1; i < NumRegs; i++) { 545 // Load one integer register's worth from the original location. 546 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 547 SVOffset + Offset, LD->isVolatile(), 548 MinAlign(LD->getAlignment(), Offset)); 549 // Follow the load with a store to the stack slot. Remember the store. 550 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 551 NULL, 0)); 552 // Increment the pointers. 553 Offset += RegBytes; 554 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 555 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 556 Increment); 557 } 558 559 // The last copy may be partial. Do an extending load. 560 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset)); 561 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 562 LD->getSrcValue(), SVOffset + Offset, 563 MemVT, LD->isVolatile(), 564 MinAlign(LD->getAlignment(), Offset)); 565 // Follow the load with a store to the stack slot. Remember the store. 566 // On big-endian machines this requires a truncating store to ensure 567 // that the bits end up in the right place. 568 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 569 NULL, 0, MemVT)); 570 571 // The order of the stores doesn't matter - say it with a TokenFactor. 572 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 573 Stores.size()); 574 575 // Finally, perform the original load only redirected to the stack slot. 576 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 577 NULL, 0, LoadedVT); 578 579 // Callers expect a MERGE_VALUES node. 580 SDValue Ops[] = { Load, TF }; 581 return DAG.getMergeValues(Ops, 2, dl); 582 } 583 } 584 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 585 "Unaligned load of unsupported type."); 586 587 // Compute the new VT that is half the size of the old one. This is an 588 // integer MVT. 589 unsigned NumBits = LoadedVT.getSizeInBits(); 590 MVT NewLoadedVT; 591 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 592 NumBits >>= 1; 593 594 unsigned Alignment = LD->getAlignment(); 595 unsigned IncrementSize = NumBits / 8; 596 ISD::LoadExtType HiExtType = LD->getExtensionType(); 597 598 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 599 if (HiExtType == ISD::NON_EXTLOAD) 600 HiExtType = ISD::ZEXTLOAD; 601 602 // Load the value in two parts 603 SDValue Lo, Hi; 604 if (TLI.isLittleEndian()) { 605 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 606 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 607 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 608 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 609 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 610 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 611 MinAlign(Alignment, IncrementSize)); 612 } else { 613 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 614 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 615 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 616 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 617 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 618 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 619 MinAlign(Alignment, IncrementSize)); 620 } 621 622 // aggregate the two parts 623 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 624 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 625 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 626 627 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 628 Hi.getValue(1)); 629 630 SDValue Ops[] = { Result, TF }; 631 return DAG.getMergeValues(Ops, 2, dl); 632} 633 634/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 635/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 636/// is necessary to spill the vector being inserted into to memory, perform 637/// the insert there, and then read the result back. 638SDValue SelectionDAGLegalize:: 639PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 640 DebugLoc dl) { 641 SDValue Tmp1 = Vec; 642 SDValue Tmp2 = Val; 643 SDValue Tmp3 = Idx; 644 645 // If the target doesn't support this, we have to spill the input vector 646 // to a temporary stack slot, update the element, then reload it. This is 647 // badness. We could also load the value into a vector register (either 648 // with a "move to register" or "extload into register" instruction, then 649 // permute it into place, if the idx is a constant and if the idx is 650 // supported by the target. 651 MVT VT = Tmp1.getValueType(); 652 MVT EltVT = VT.getVectorElementType(); 653 MVT IdxVT = Tmp3.getValueType(); 654 MVT PtrVT = TLI.getPointerTy(); 655 SDValue StackPtr = DAG.CreateStackTemporary(VT); 656 657 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 658 659 // Store the vector. 660 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 661 PseudoSourceValue::getFixedStack(SPFI), 0); 662 663 // Truncate or zero extend offset to target pointer type. 664 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 665 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 666 // Add the offset to the index. 667 unsigned EltSize = EltVT.getSizeInBits()/8; 668 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 669 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 670 // Store the scalar value. 671 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 672 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 673 // Load the updated vector. 674 return DAG.getLoad(VT, dl, Ch, StackPtr, 675 PseudoSourceValue::getFixedStack(SPFI), 0); 676} 677 678 679SDValue SelectionDAGLegalize:: 680ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 681 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 682 // SCALAR_TO_VECTOR requires that the type of the value being inserted 683 // match the element type of the vector being created, except for 684 // integers in which case the inserted value can be over width. 685 MVT EltVT = Vec.getValueType().getVectorElementType(); 686 if (Val.getValueType() == EltVT || 687 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 688 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 689 Vec.getValueType(), Val); 690 691 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 692 // We generate a shuffle of InVec and ScVec, so the shuffle mask 693 // should be 0,1,2,3,4,5... with the appropriate element replaced with 694 // elt 0 of the RHS. 695 SmallVector<int, 8> ShufOps; 696 for (unsigned i = 0; i != NumElts; ++i) 697 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 698 699 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 700 &ShufOps[0]); 701 } 702 } 703 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 704} 705 706/// LegalizeOp - We know that the specified value has a legal type, and 707/// that its operands are legal. Now ensure that the operation itself 708/// is legal, recursively ensuring that the operands' operations remain 709/// legal. 710SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 711 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 712 return Op; 713 714 SDNode *Node = Op.getNode(); 715 DebugLoc dl = Node->getDebugLoc(); 716 717 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 718 assert(getTypeAction(Node->getValueType(i)) == Legal && 719 "Unexpected illegal type!"); 720 721 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 722 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 723 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 724 "Unexpected illegal type!"); 725 726 // Note that LegalizeOp may be reentered even from single-use nodes, which 727 // means that we always must cache transformed nodes. 728 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 729 if (I != LegalizedNodes.end()) return I->second; 730 731 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 732 SDValue Result = Op; 733 bool isCustom = false; 734 735 // Figure out the correct action; the way to query this varies by opcode 736 TargetLowering::LegalizeAction Action; 737 bool SimpleFinishLegalizing = true; 738 switch (Node->getOpcode()) { 739 case ISD::INTRINSIC_W_CHAIN: 740 case ISD::INTRINSIC_WO_CHAIN: 741 case ISD::INTRINSIC_VOID: 742 case ISD::VAARG: 743 case ISD::STACKSAVE: 744 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 745 break; 746 case ISD::SINT_TO_FP: 747 case ISD::UINT_TO_FP: 748 case ISD::EXTRACT_VECTOR_ELT: 749 Action = TLI.getOperationAction(Node->getOpcode(), 750 Node->getOperand(0).getValueType()); 751 break; 752 case ISD::FP_ROUND_INREG: 753 case ISD::SIGN_EXTEND_INREG: { 754 MVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 755 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 756 break; 757 } 758 case ISD::LOAD: 759 case ISD::STORE: 760 case ISD::BR_CC: 761 case ISD::FORMAL_ARGUMENTS: 762 case ISD::CALL: 763 case ISD::CALLSEQ_START: 764 case ISD::CALLSEQ_END: 765 case ISD::SELECT_CC: 766 case ISD::SETCC: 767 // These instructions have properties that aren't modeled in the 768 // generic codepath 769 SimpleFinishLegalizing = false; 770 break; 771 case ISD::EXTRACT_ELEMENT: 772 case ISD::FLT_ROUNDS_: 773 case ISD::SADDO: 774 case ISD::SSUBO: 775 case ISD::UADDO: 776 case ISD::USUBO: 777 case ISD::SMULO: 778 case ISD::UMULO: 779 case ISD::FPOWI: 780 case ISD::MERGE_VALUES: 781 case ISD::EH_RETURN: 782 case ISD::FRAME_TO_ARGS_OFFSET: 783 // These operations lie about being legal: when they claim to be legal, 784 // they should actually be expanded. 785 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 786 if (Action == TargetLowering::Legal) 787 Action = TargetLowering::Expand; 788 break; 789 case ISD::TRAMPOLINE: 790 case ISD::FRAMEADDR: 791 case ISD::RETURNADDR: 792 // These operations lie about being legal: they must always be 793 // custom-lowered. 794 Action = TargetLowering::Custom; 795 break; 796 case ISD::BUILD_VECTOR: 797 // A weird case: when a BUILD_VECTOR is custom-lowered, it doesn't legalize 798 // its operands first! 799 SimpleFinishLegalizing = false; 800 break; 801 default: 802 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 803 Action = TargetLowering::Legal; 804 } else { 805 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 806 } 807 break; 808 } 809 810 if (SimpleFinishLegalizing) { 811 SmallVector<SDValue, 8> Ops, ResultVals; 812 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 813 Ops.push_back(LegalizeOp(Node->getOperand(i))); 814 switch (Node->getOpcode()) { 815 default: break; 816 case ISD::BR: 817 case ISD::BRIND: 818 case ISD::BR_JT: 819 case ISD::BR_CC: 820 case ISD::BRCOND: 821 case ISD::RET: 822 // Branches tweak the chain to include LastCALLSEQ_END 823 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 824 LastCALLSEQ_END); 825 Ops[0] = LegalizeOp(Ops[0]); 826 LastCALLSEQ_END = DAG.getEntryNode(); 827 break; 828 case ISD::SHL: 829 case ISD::SRL: 830 case ISD::SRA: 831 case ISD::ROTL: 832 case ISD::ROTR: 833 // Legalizing shifts/rotates requires adjusting the shift amount 834 // to the appropriate width. 835 if (!Ops[1].getValueType().isVector()) 836 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 837 break; 838 } 839 840 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(), 841 Ops.size()); 842 switch (Action) { 843 case TargetLowering::Legal: 844 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 845 ResultVals.push_back(Result.getValue(i)); 846 break; 847 case TargetLowering::Custom: 848 // FIXME: The handling for custom lowering with multiple results is 849 // a complete mess. 850 Tmp1 = TLI.LowerOperation(Result, DAG); 851 if (Tmp1.getNode()) { 852 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 853 if (e == 1) 854 ResultVals.push_back(Tmp1); 855 else 856 ResultVals.push_back(Tmp1.getValue(i)); 857 } 858 break; 859 } 860 861 // FALL THROUGH 862 case TargetLowering::Expand: 863 ExpandNode(Result.getNode(), ResultVals); 864 break; 865 case TargetLowering::Promote: 866 PromoteNode(Result.getNode(), ResultVals); 867 break; 868 } 869 if (!ResultVals.empty()) { 870 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 871 if (ResultVals[i] != SDValue(Node, i)) 872 ResultVals[i] = LegalizeOp(ResultVals[i]); 873 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 874 } 875 return ResultVals[Op.getResNo()]; 876 } 877 } 878 879 switch (Node->getOpcode()) { 880 default: 881#ifndef NDEBUG 882 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 883#endif 884 assert(0 && "Do not know how to legalize this operator!"); 885 abort(); 886 case ISD::DBG_STOPPOINT: 887 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!"); 888 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 889 890 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) { 891 case TargetLowering::Promote: 892 default: assert(0 && "This action is not supported yet!"); 893 case TargetLowering::Expand: { 894 DwarfWriter *DW = DAG.getDwarfWriter(); 895 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, 896 MVT::Other); 897 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); 898 899 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 900 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit()); 901 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) { 902 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit())); 903 904 unsigned Line = DSP->getLine(); 905 unsigned Col = DSP->getColumn(); 906 907 if (OptLevel == CodeGenOpt::None) { 908 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it 909 // won't hurt anything. 910 if (useDEBUG_LOC) { 911 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), 912 DAG.getConstant(Col, MVT::i32), 913 DAG.getSrcValue(CU.getGV()) }; 914 Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4); 915 } else { 916 unsigned ID = DW->RecordSourceLine(Line, Col, CU); 917 Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID); 918 } 919 } else { 920 Result = Tmp1; // chain 921 } 922 } else { 923 Result = Tmp1; // chain 924 } 925 break; 926 } 927 case TargetLowering::Custom: 928 Result = TLI.LowerOperation(Op, DAG); 929 if (Result.getNode()) 930 break; 931 case TargetLowering::Legal: { 932 if (Tmp1 == Node->getOperand(0)) 933 break; 934 935 SmallVector<SDValue, 8> Ops; 936 Ops.push_back(Tmp1); 937 Ops.push_back(Node->getOperand(1)); // line # must be legal. 938 Ops.push_back(Node->getOperand(2)); // col # must be legal. 939 Ops.push_back(Node->getOperand(3)); // filename must be legal. 940 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 941 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 942 break; 943 } 944 } 945 break; 946 case ISD::ConstantFP: { 947 // Spill FP immediates to the constant pool if the target cannot directly 948 // codegen them. Targets often have some immediate values that can be 949 // efficiently generated into an FP register without a load. We explicitly 950 // leave these constants as ConstantFP nodes for the target to deal with. 951 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 952 953 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 954 default: assert(0 && "This action is not supported yet!"); 955 case TargetLowering::Legal: 956 break; 957 case TargetLowering::Custom: 958 Tmp3 = TLI.LowerOperation(Result, DAG); 959 if (Tmp3.getNode()) { 960 Result = Tmp3; 961 break; 962 } 963 // FALLTHROUGH 964 case TargetLowering::Expand: { 965 // Check to see if this FP immediate is already legal. 966 bool isLegal = false; 967 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 968 E = TLI.legal_fpimm_end(); I != E; ++I) { 969 if (CFP->isExactlyValue(*I)) { 970 isLegal = true; 971 break; 972 } 973 } 974 // If this is a legal constant, turn it into a TargetConstantFP node. 975 if (isLegal) 976 break; 977 Result = ExpandConstantFP(CFP, true, DAG, TLI); 978 } 979 } 980 break; 981 } 982 case ISD::FORMAL_ARGUMENTS: 983 case ISD::CALL: 984 // The only option for this is to custom lower it. 985 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 986 assert(Tmp3.getNode() && "Target didn't custom lower this node!"); 987 // A call within a calling sequence must be legalized to something 988 // other than the normal CALLSEQ_END. Violating this gets Legalize 989 // into an infinite loop. 990 assert ((!IsLegalizingCall || 991 Node->getOpcode() != ISD::CALL || 992 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) && 993 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 994 995 // The number of incoming and outgoing values should match; unless the final 996 // outgoing value is a flag. 997 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || 998 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 && 999 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == 1000 MVT::Flag)) && 1001 "Lowering call/formal_arguments produced unexpected # results!"); 1002 1003 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1004 // remember that we legalized all of them, so it doesn't get relegalized. 1005 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) { 1006 if (Tmp3.getNode()->getValueType(i) == MVT::Flag) 1007 continue; 1008 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1009 if (Op.getResNo() == i) 1010 Tmp2 = Tmp1; 1011 AddLegalizedOperand(SDValue(Node, i), Tmp1); 1012 } 1013 return Tmp2; 1014 case ISD::BUILD_VECTOR: 1015 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1016 default: assert(0 && "This action is not supported yet!"); 1017 case TargetLowering::Custom: 1018 Tmp3 = TLI.LowerOperation(Result, DAG); 1019 if (Tmp3.getNode()) { 1020 Result = Tmp3; 1021 break; 1022 } 1023 // FALLTHROUGH 1024 case TargetLowering::Expand: 1025 Result = ExpandBUILD_VECTOR(Result.getNode()); 1026 break; 1027 } 1028 break; 1029 case ISD::VECTOR_SHUFFLE: { 1030 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1031 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1032 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1033 MVT VT = Result.getValueType(); 1034 1035 // Copy the Mask to a local SmallVector for use with isShuffleMaskLegal. 1036 SmallVector<int, 8> Mask; 1037 cast<ShuffleVectorSDNode>(Result)->getMask(Mask); 1038 1039 // Allow targets to custom lower the SHUFFLEs they support. 1040 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 1041 default: assert(0 && "Unknown operation action!"); 1042 case TargetLowering::Legal: 1043 assert(TLI.isShuffleMaskLegal(Mask, VT) && 1044 "vector shuffle should not be created if not legal!"); 1045 break; 1046 case TargetLowering::Custom: 1047 Tmp3 = TLI.LowerOperation(Result, DAG); 1048 if (Tmp3.getNode()) { 1049 Result = Tmp3; 1050 break; 1051 } 1052 // FALLTHROUGH 1053 case TargetLowering::Expand: { 1054 MVT EltVT = VT.getVectorElementType(); 1055 unsigned NumElems = VT.getVectorNumElements(); 1056 SmallVector<SDValue, 8> Ops; 1057 for (unsigned i = 0; i != NumElems; ++i) { 1058 if (Mask[i] < 0) { 1059 Ops.push_back(DAG.getUNDEF(EltVT)); 1060 continue; 1061 } 1062 unsigned Idx = Mask[i]; 1063 if (Idx < NumElems) 1064 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1, 1065 DAG.getIntPtrConstant(Idx))); 1066 else 1067 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2, 1068 DAG.getIntPtrConstant(Idx - NumElems))); 1069 } 1070 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 1071 break; 1072 } 1073 case TargetLowering::Promote: { 1074 // Change base type to a different vector type. 1075 MVT OVT = Node->getValueType(0); 1076 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1077 1078 // Cast the two input vectors. 1079 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1); 1080 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2); 1081 1082 // Convert the shuffle mask to the right # elements. 1083 Result = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 1084 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result); 1085 break; 1086 } 1087 } 1088 break; 1089 } 1090 case ISD::CONCAT_VECTORS: { 1091 // Legalize the operands. 1092 SmallVector<SDValue, 8> Ops; 1093 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1094 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1095 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1096 1097 switch (TLI.getOperationAction(ISD::CONCAT_VECTORS, 1098 Node->getValueType(0))) { 1099 default: assert(0 && "Unknown operation action!"); 1100 case TargetLowering::Legal: 1101 break; 1102 case TargetLowering::Custom: 1103 Tmp3 = TLI.LowerOperation(Result, DAG); 1104 if (Tmp3.getNode()) { 1105 Result = Tmp3; 1106 break; 1107 } 1108 // FALLTHROUGH 1109 case TargetLowering::Expand: { 1110 // Use extract/insert/build vector for now. We might try to be 1111 // more clever later. 1112 MVT PtrVT = TLI.getPointerTy(); 1113 SmallVector<SDValue, 8> Ops; 1114 unsigned NumOperands = Node->getNumOperands(); 1115 for (unsigned i=0; i < NumOperands; ++i) { 1116 SDValue SubOp = Node->getOperand(i); 1117 MVT VVT = SubOp.getNode()->getValueType(0); 1118 MVT EltVT = VVT.getVectorElementType(); 1119 unsigned NumSubElem = VVT.getVectorNumElements(); 1120 for (unsigned j=0; j < NumSubElem; ++j) { 1121 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, 1122 DAG.getConstant(j, PtrVT))); 1123 } 1124 } 1125 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, dl, 1126 Node->getValueType(0), 1127 &Ops[0], Ops.size())); 1128 } 1129 } 1130 break; 1131 } 1132 1133 case ISD::CALLSEQ_START: { 1134 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1135 1136 // Recursively Legalize all of the inputs of the call end that do not lead 1137 // to this call start. This ensures that any libcalls that need be inserted 1138 // are inserted *before* the CALLSEQ_START. 1139 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1140 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1141 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1142 NodesLeadingTo); 1143 } 1144 1145 // Now that we legalized all of the inputs (which may have inserted 1146 // libcalls) create the new CALLSEQ_START node. 1147 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1148 1149 // Merge in the last call, to ensure that this call start after the last 1150 // call ended. 1151 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1152 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1153 Tmp1, LastCALLSEQ_END); 1154 Tmp1 = LegalizeOp(Tmp1); 1155 } 1156 1157 // Do not try to legalize the target-specific arguments (#1+). 1158 if (Tmp1 != Node->getOperand(0)) { 1159 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1160 Ops[0] = Tmp1; 1161 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1162 } 1163 1164 // Remember that the CALLSEQ_START is legalized. 1165 AddLegalizedOperand(Op.getValue(0), Result); 1166 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1167 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1168 1169 // Now that the callseq_start and all of the non-call nodes above this call 1170 // sequence have been legalized, legalize the call itself. During this 1171 // process, no libcalls can/will be inserted, guaranteeing that no calls 1172 // can overlap. 1173 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1174 // Note that we are selecting this call! 1175 LastCALLSEQ_END = SDValue(CallEnd, 0); 1176 IsLegalizingCall = true; 1177 1178 // Legalize the call, starting from the CALLSEQ_END. 1179 LegalizeOp(LastCALLSEQ_END); 1180 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1181 return Result; 1182 } 1183 case ISD::CALLSEQ_END: 1184 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1185 // will cause this node to be legalized as well as handling libcalls right. 1186 if (LastCALLSEQ_END.getNode() != Node) { 1187 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1188 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1189 assert(I != LegalizedNodes.end() && 1190 "Legalizing the call start should have legalized this node!"); 1191 return I->second; 1192 } 1193 1194 // Otherwise, the call start has been legalized and everything is going 1195 // according to plan. Just legalize ourselves normally here. 1196 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1197 // Do not try to legalize the target-specific arguments (#1+), except for 1198 // an optional flag input. 1199 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1200 if (Tmp1 != Node->getOperand(0)) { 1201 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1202 Ops[0] = Tmp1; 1203 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1204 } 1205 } else { 1206 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1207 if (Tmp1 != Node->getOperand(0) || 1208 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1209 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1210 Ops[0] = Tmp1; 1211 Ops.back() = Tmp2; 1212 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1213 } 1214 } 1215 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1216 // This finishes up call legalization. 1217 IsLegalizingCall = false; 1218 1219 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1220 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1221 if (Node->getNumValues() == 2) 1222 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1223 return Result.getValue(Op.getResNo()); 1224 case ISD::DYNAMIC_STACKALLOC: { 1225 MVT VT = Node->getValueType(0); 1226 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1227 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1228 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1229 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1230 1231 Tmp1 = Result.getValue(0); 1232 Tmp2 = Result.getValue(1); 1233 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1234 default: assert(0 && "This action is not supported yet!"); 1235 case TargetLowering::Expand: { 1236 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1237 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1238 " not tell us which reg is the stack pointer!"); 1239 SDValue Chain = Tmp1.getOperand(0); 1240 1241 // Chain the dynamic stack allocation so that it doesn't modify the stack 1242 // pointer when other instructions are using the stack. 1243 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1244 1245 SDValue Size = Tmp2.getOperand(1); 1246 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1247 Chain = SP.getValue(1); 1248 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1249 unsigned StackAlign = 1250 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1251 if (Align > StackAlign) 1252 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1253 DAG.getConstant(-(uint64_t)Align, VT)); 1254 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1255 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1256 1257 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1258 DAG.getIntPtrConstant(0, true), SDValue()); 1259 1260 Tmp1 = LegalizeOp(Tmp1); 1261 Tmp2 = LegalizeOp(Tmp2); 1262 break; 1263 } 1264 case TargetLowering::Custom: 1265 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1266 if (Tmp3.getNode()) { 1267 Tmp1 = LegalizeOp(Tmp3); 1268 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1269 } 1270 break; 1271 case TargetLowering::Legal: 1272 break; 1273 } 1274 // Since this op produce two values, make sure to remember that we 1275 // legalized both of them. 1276 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1277 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1278 return Op.getResNo() ? Tmp2 : Tmp1; 1279 } 1280 case ISD::BR_JT: 1281 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1282 // Ensure that libcalls are emitted before a branch. 1283 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 1284 Tmp1 = LegalizeOp(Tmp1); 1285 LastCALLSEQ_END = DAG.getEntryNode(); 1286 1287 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1288 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1289 1290 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1291 default: assert(0 && "This action is not supported yet!"); 1292 case TargetLowering::Legal: break; 1293 case TargetLowering::Custom: 1294 Tmp1 = TLI.LowerOperation(Result, DAG); 1295 if (Tmp1.getNode()) Result = Tmp1; 1296 break; 1297 case TargetLowering::Expand: { 1298 SDValue Chain = Result.getOperand(0); 1299 SDValue Table = Result.getOperand(1); 1300 SDValue Index = Result.getOperand(2); 1301 1302 MVT PTy = TLI.getPointerTy(); 1303 MachineFunction &MF = DAG.getMachineFunction(); 1304 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1305 Index= DAG.getNode(ISD::MUL, dl, PTy, 1306 Index, DAG.getConstant(EntrySize, PTy)); 1307 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 1308 1309 MVT MemVT = MVT::getIntegerVT(EntrySize * 8); 1310 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 1311 PseudoSourceValue::getJumpTable(), 0, MemVT); 1312 Addr = LD; 1313 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1314 // For PIC, the sequence is: 1315 // BRIND(load(Jumptable + index) + RelocBase) 1316 // RelocBase can be JumpTable, GOT or some sort of global base. 1317 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 1318 TLI.getPICJumpTableRelocBase(Table, DAG)); 1319 } 1320 Result = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 1321 } 1322 } 1323 break; 1324 case ISD::BRCOND: 1325 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1326 // Ensure that libcalls are emitted before a return. 1327 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 1328 Tmp1 = LegalizeOp(Tmp1); 1329 LastCALLSEQ_END = DAG.getEntryNode(); 1330 1331 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1332 1333 // Basic block destination (Op#2) is always legal. 1334 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1335 1336 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1337 default: assert(0 && "This action is not supported yet!"); 1338 case TargetLowering::Legal: break; 1339 case TargetLowering::Custom: 1340 Tmp1 = TLI.LowerOperation(Result, DAG); 1341 if (Tmp1.getNode()) Result = Tmp1; 1342 break; 1343 case TargetLowering::Expand: 1344 // Expand brcond's setcc into its constituent parts and create a BR_CC 1345 // Node. 1346 if (Tmp2.getOpcode() == ISD::SETCC) { 1347 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 1348 Tmp1, Tmp2.getOperand(2), 1349 Tmp2.getOperand(0), Tmp2.getOperand(1), 1350 Node->getOperand(2)); 1351 } else { 1352 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 1353 DAG.getCondCode(ISD::SETNE), Tmp2, 1354 DAG.getConstant(0, Tmp2.getValueType()), 1355 Node->getOperand(2)); 1356 } 1357 break; 1358 } 1359 break; 1360 case ISD::BR_CC: 1361 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1362 // Ensure that libcalls are emitted before a branch. 1363 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END); 1364 Tmp1 = LegalizeOp(Tmp1); 1365 Tmp2 = Node->getOperand(2); // LHS 1366 Tmp3 = Node->getOperand(3); // RHS 1367 Tmp4 = Node->getOperand(1); // CC 1368 1369 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()), 1370 Tmp2, Tmp3, Tmp4, dl); 1371 LastCALLSEQ_END = DAG.getEntryNode(); 1372 1373 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 1374 // the LHS is a legal SETCC itself. In this case, we need to compare 1375 // the result against zero to select between true and false values. 1376 if (Tmp3.getNode() == 0) { 1377 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1378 Tmp4 = DAG.getCondCode(ISD::SETNE); 1379 } 1380 1381 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1382 Node->getOperand(4)); 1383 1384 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1385 default: assert(0 && "Unexpected action for BR_CC!"); 1386 case TargetLowering::Legal: break; 1387 case TargetLowering::Custom: 1388 Tmp4 = TLI.LowerOperation(Result, DAG); 1389 if (Tmp4.getNode()) Result = Tmp4; 1390 break; 1391 } 1392 break; 1393 case ISD::LOAD: { 1394 LoadSDNode *LD = cast<LoadSDNode>(Node); 1395 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1396 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1397 1398 ISD::LoadExtType ExtType = LD->getExtensionType(); 1399 if (ExtType == ISD::NON_EXTLOAD) { 1400 MVT VT = Node->getValueType(0); 1401 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1402 Tmp3 = Result.getValue(0); 1403 Tmp4 = Result.getValue(1); 1404 1405 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1406 default: assert(0 && "This action is not supported yet!"); 1407 case TargetLowering::Legal: 1408 // If this is an unaligned load and the target doesn't support it, 1409 // expand it. 1410 if (!TLI.allowsUnalignedMemoryAccesses()) { 1411 unsigned ABIAlignment = TLI.getTargetData()-> 1412 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 1413 if (LD->getAlignment() < ABIAlignment){ 1414 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 1415 TLI); 1416 Tmp3 = Result.getOperand(0); 1417 Tmp4 = Result.getOperand(1); 1418 Tmp3 = LegalizeOp(Tmp3); 1419 Tmp4 = LegalizeOp(Tmp4); 1420 } 1421 } 1422 break; 1423 case TargetLowering::Custom: 1424 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1425 if (Tmp1.getNode()) { 1426 Tmp3 = LegalizeOp(Tmp1); 1427 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1428 } 1429 break; 1430 case TargetLowering::Promote: { 1431 // Only promote a load of vector type to another. 1432 assert(VT.isVector() && "Cannot promote this load!"); 1433 // Change base type to a different vector type. 1434 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1435 1436 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1437 LD->getSrcValueOffset(), 1438 LD->isVolatile(), LD->getAlignment()); 1439 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1440 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1441 break; 1442 } 1443 } 1444 // Since loads produce two values, make sure to remember that we 1445 // legalized both of them. 1446 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1447 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1448 return Op.getResNo() ? Tmp4 : Tmp3; 1449 } else { 1450 MVT SrcVT = LD->getMemoryVT(); 1451 unsigned SrcWidth = SrcVT.getSizeInBits(); 1452 int SVOffset = LD->getSrcValueOffset(); 1453 unsigned Alignment = LD->getAlignment(); 1454 bool isVolatile = LD->isVolatile(); 1455 1456 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1457 // Some targets pretend to have an i1 loading operation, and actually 1458 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1459 // bits are guaranteed to be zero; it helps the optimizers understand 1460 // that these bits are zero. It is also useful for EXTLOAD, since it 1461 // tells the optimizers that those bits are undefined. It would be 1462 // nice to have an effective generic way of getting these benefits... 1463 // Until such a way is found, don't insist on promoting i1 here. 1464 (SrcVT != MVT::i1 || 1465 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1466 // Promote to a byte-sized load if not loading an integral number of 1467 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1468 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1469 MVT NVT = MVT::getIntegerVT(NewWidth); 1470 SDValue Ch; 1471 1472 // The extra bits are guaranteed to be zero, since we stored them that 1473 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1474 1475 ISD::LoadExtType NewExtType = 1476 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1477 1478 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 1479 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1480 NVT, isVolatile, Alignment); 1481 1482 Ch = Result.getValue(1); // The chain. 1483 1484 if (ExtType == ISD::SEXTLOAD) 1485 // Having the top bits zero doesn't help when sign extending. 1486 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1487 Result.getValueType(), 1488 Result, DAG.getValueType(SrcVT)); 1489 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1490 // All the top bits are guaranteed to be zero - inform the optimizers. 1491 Result = DAG.getNode(ISD::AssertZext, dl, 1492 Result.getValueType(), Result, 1493 DAG.getValueType(SrcVT)); 1494 1495 Tmp1 = LegalizeOp(Result); 1496 Tmp2 = LegalizeOp(Ch); 1497 } else if (SrcWidth & (SrcWidth - 1)) { 1498 // If not loading a power-of-2 number of bits, expand as two loads. 1499 assert(SrcVT.isExtended() && !SrcVT.isVector() && 1500 "Unsupported extload!"); 1501 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1502 assert(RoundWidth < SrcWidth); 1503 unsigned ExtraWidth = SrcWidth - RoundWidth; 1504 assert(ExtraWidth < RoundWidth); 1505 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1506 "Load size not an integral number of bytes!"); 1507 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 1508 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 1509 SDValue Lo, Hi, Ch; 1510 unsigned IncrementSize; 1511 1512 if (TLI.isLittleEndian()) { 1513 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1514 // Load the bottom RoundWidth bits. 1515 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1516 Node->getValueType(0), Tmp1, Tmp2, 1517 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1518 Alignment); 1519 1520 // Load the remaining ExtraWidth bits. 1521 IncrementSize = RoundWidth / 8; 1522 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1523 DAG.getIntPtrConstant(IncrementSize)); 1524 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1525 LD->getSrcValue(), SVOffset + IncrementSize, 1526 ExtraVT, isVolatile, 1527 MinAlign(Alignment, IncrementSize)); 1528 1529 // Build a factor node to remember that this load is independent of the 1530 // other one. 1531 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1532 Hi.getValue(1)); 1533 1534 // Move the top bits to the right place. 1535 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1536 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1537 1538 // Join the hi and lo parts. 1539 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1540 } else { 1541 // Big endian - avoid unaligned loads. 1542 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1543 // Load the top RoundWidth bits. 1544 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1545 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1546 Alignment); 1547 1548 // Load the remaining ExtraWidth bits. 1549 IncrementSize = RoundWidth / 8; 1550 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1551 DAG.getIntPtrConstant(IncrementSize)); 1552 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1553 Node->getValueType(0), Tmp1, Tmp2, 1554 LD->getSrcValue(), SVOffset + IncrementSize, 1555 ExtraVT, isVolatile, 1556 MinAlign(Alignment, IncrementSize)); 1557 1558 // Build a factor node to remember that this load is independent of the 1559 // other one. 1560 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1561 Hi.getValue(1)); 1562 1563 // Move the top bits to the right place. 1564 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1565 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1566 1567 // Join the hi and lo parts. 1568 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1569 } 1570 1571 Tmp1 = LegalizeOp(Result); 1572 Tmp2 = LegalizeOp(Ch); 1573 } else { 1574 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1575 default: assert(0 && "This action is not supported yet!"); 1576 case TargetLowering::Custom: 1577 isCustom = true; 1578 // FALLTHROUGH 1579 case TargetLowering::Legal: 1580 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1581 Tmp1 = Result.getValue(0); 1582 Tmp2 = Result.getValue(1); 1583 1584 if (isCustom) { 1585 Tmp3 = TLI.LowerOperation(Result, DAG); 1586 if (Tmp3.getNode()) { 1587 Tmp1 = LegalizeOp(Tmp3); 1588 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1589 } 1590 } else { 1591 // If this is an unaligned load and the target doesn't support it, 1592 // expand it. 1593 if (!TLI.allowsUnalignedMemoryAccesses()) { 1594 unsigned ABIAlignment = TLI.getTargetData()-> 1595 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 1596 if (LD->getAlignment() < ABIAlignment){ 1597 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 1598 TLI); 1599 Tmp1 = Result.getOperand(0); 1600 Tmp2 = Result.getOperand(1); 1601 Tmp1 = LegalizeOp(Tmp1); 1602 Tmp2 = LegalizeOp(Tmp2); 1603 } 1604 } 1605 } 1606 break; 1607 case TargetLowering::Expand: 1608 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1609 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1610 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1611 LD->getSrcValueOffset(), 1612 LD->isVolatile(), LD->getAlignment()); 1613 Result = DAG.getNode(ISD::FP_EXTEND, dl, 1614 Node->getValueType(0), Load); 1615 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1616 Tmp2 = LegalizeOp(Load.getValue(1)); 1617 break; 1618 } 1619 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1620 // Turn the unsupported load into an EXTLOAD followed by an explicit 1621 // zero/sign extend inreg. 1622 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1623 Tmp1, Tmp2, LD->getSrcValue(), 1624 LD->getSrcValueOffset(), SrcVT, 1625 LD->isVolatile(), LD->getAlignment()); 1626 SDValue ValRes; 1627 if (ExtType == ISD::SEXTLOAD) 1628 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1629 Result.getValueType(), 1630 Result, DAG.getValueType(SrcVT)); 1631 else 1632 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1633 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1634 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1635 break; 1636 } 1637 } 1638 1639 // Since loads produce two values, make sure to remember that we legalized 1640 // both of them. 1641 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1642 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1643 return Op.getResNo() ? Tmp2 : Tmp1; 1644 } 1645 } 1646 case ISD::STORE: { 1647 StoreSDNode *ST = cast<StoreSDNode>(Node); 1648 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1649 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1650 int SVOffset = ST->getSrcValueOffset(); 1651 unsigned Alignment = ST->getAlignment(); 1652 bool isVolatile = ST->isVolatile(); 1653 1654 if (!ST->isTruncatingStore()) { 1655 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1656 // FIXME: We shouldn't do this for TargetConstantFP's. 1657 // FIXME: move this to the DAG Combiner! Note that we can't regress due 1658 // to phase ordering between legalized code and the dag combiner. This 1659 // probably means that we need to integrate dag combiner and legalizer 1660 // together. 1661 // We generally can't do this one for long doubles. 1662 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 1663 if (CFP->getValueType(0) == MVT::f32 && 1664 getTypeAction(MVT::i32) == Legal) { 1665 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 1666 bitcastToAPInt().zextOrTrunc(32), 1667 MVT::i32); 1668 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1669 SVOffset, isVolatile, Alignment); 1670 break; 1671 } else if (CFP->getValueType(0) == MVT::f64) { 1672 // If this target supports 64-bit registers, do a single 64-bit store. 1673 if (getTypeAction(MVT::i64) == Legal) { 1674 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 1675 zextOrTrunc(64), MVT::i64); 1676 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1677 SVOffset, isVolatile, Alignment); 1678 break; 1679 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 1680 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 1681 // stores. If the target supports neither 32- nor 64-bits, this 1682 // xform is certainly not worth it. 1683 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 1684 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 1685 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 1686 if (TLI.isBigEndian()) std::swap(Lo, Hi); 1687 1688 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 1689 SVOffset, isVolatile, Alignment); 1690 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1691 DAG.getIntPtrConstant(4)); 1692 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 1693 isVolatile, MinAlign(Alignment, 4U)); 1694 1695 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1696 break; 1697 } 1698 } 1699 } 1700 1701 { 1702 Tmp3 = LegalizeOp(ST->getValue()); 1703 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1704 ST->getOffset()); 1705 1706 MVT VT = Tmp3.getValueType(); 1707 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1708 default: assert(0 && "This action is not supported yet!"); 1709 case TargetLowering::Legal: 1710 // If this is an unaligned store and the target doesn't support it, 1711 // expand it. 1712 if (!TLI.allowsUnalignedMemoryAccesses()) { 1713 unsigned ABIAlignment = TLI.getTargetData()-> 1714 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 1715 if (ST->getAlignment() < ABIAlignment) 1716 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 1717 TLI); 1718 } 1719 break; 1720 case TargetLowering::Custom: 1721 Tmp1 = TLI.LowerOperation(Result, DAG); 1722 if (Tmp1.getNode()) Result = Tmp1; 1723 break; 1724 case TargetLowering::Promote: 1725 assert(VT.isVector() && "Unknown legal promote case!"); 1726 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1727 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1728 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1729 ST->getSrcValue(), SVOffset, isVolatile, 1730 Alignment); 1731 break; 1732 } 1733 break; 1734 } 1735 } else { 1736 Tmp3 = LegalizeOp(ST->getValue()); 1737 1738 MVT StVT = ST->getMemoryVT(); 1739 unsigned StWidth = StVT.getSizeInBits(); 1740 1741 if (StWidth != StVT.getStoreSizeInBits()) { 1742 // Promote to a byte-sized store with upper bits zero if not 1743 // storing an integral number of bytes. For example, promote 1744 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1745 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 1746 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1747 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1748 SVOffset, NVT, isVolatile, Alignment); 1749 } else if (StWidth & (StWidth - 1)) { 1750 // If not storing a power-of-2 number of bits, expand as two stores. 1751 assert(StVT.isExtended() && !StVT.isVector() && 1752 "Unsupported truncstore!"); 1753 unsigned RoundWidth = 1 << Log2_32(StWidth); 1754 assert(RoundWidth < StWidth); 1755 unsigned ExtraWidth = StWidth - RoundWidth; 1756 assert(ExtraWidth < RoundWidth); 1757 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1758 "Store size not an integral number of bytes!"); 1759 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 1760 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 1761 SDValue Lo, Hi; 1762 unsigned IncrementSize; 1763 1764 if (TLI.isLittleEndian()) { 1765 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1766 // Store the bottom RoundWidth bits. 1767 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1768 SVOffset, RoundVT, 1769 isVolatile, Alignment); 1770 1771 // Store the remaining ExtraWidth bits. 1772 IncrementSize = RoundWidth / 8; 1773 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1774 DAG.getIntPtrConstant(IncrementSize)); 1775 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1776 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1777 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1778 SVOffset + IncrementSize, ExtraVT, isVolatile, 1779 MinAlign(Alignment, IncrementSize)); 1780 } else { 1781 // Big endian - avoid unaligned stores. 1782 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1783 // Store the top RoundWidth bits. 1784 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1785 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1786 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1787 SVOffset, RoundVT, isVolatile, Alignment); 1788 1789 // Store the remaining ExtraWidth bits. 1790 IncrementSize = RoundWidth / 8; 1791 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1792 DAG.getIntPtrConstant(IncrementSize)); 1793 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1794 SVOffset + IncrementSize, ExtraVT, isVolatile, 1795 MinAlign(Alignment, IncrementSize)); 1796 } 1797 1798 // The order of the stores doesn't matter. 1799 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1800 } else { 1801 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1802 Tmp2 != ST->getBasePtr()) 1803 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1804 ST->getOffset()); 1805 1806 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1807 default: assert(0 && "This action is not supported yet!"); 1808 case TargetLowering::Legal: 1809 // If this is an unaligned store and the target doesn't support it, 1810 // expand it. 1811 if (!TLI.allowsUnalignedMemoryAccesses()) { 1812 unsigned ABIAlignment = TLI.getTargetData()-> 1813 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 1814 if (ST->getAlignment() < ABIAlignment) 1815 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 1816 TLI); 1817 } 1818 break; 1819 case TargetLowering::Custom: 1820 Result = TLI.LowerOperation(Result, DAG); 1821 break; 1822 case Expand: 1823 // TRUNCSTORE:i16 i32 -> STORE i16 1824 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1825 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1826 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1827 SVOffset, isVolatile, Alignment); 1828 break; 1829 } 1830 } 1831 } 1832 break; 1833 } 1834 case ISD::SELECT: 1835 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1836 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1837 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1838 1839 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1840 1841 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1842 default: assert(0 && "This action is not supported yet!"); 1843 case TargetLowering::Legal: break; 1844 case TargetLowering::Custom: { 1845 Tmp1 = TLI.LowerOperation(Result, DAG); 1846 if (Tmp1.getNode()) Result = Tmp1; 1847 break; 1848 } 1849 case TargetLowering::Expand: 1850 if (Tmp1.getOpcode() == ISD::SETCC) { 1851 Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 1852 Tmp2, Tmp3, 1853 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1854 } else { 1855 Result = DAG.getSelectCC(dl, Tmp1, 1856 DAG.getConstant(0, Tmp1.getValueType()), 1857 Tmp2, Tmp3, ISD::SETNE); 1858 } 1859 break; 1860 case TargetLowering::Promote: { 1861 MVT NVT = 1862 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1863 unsigned ExtOp, TruncOp; 1864 if (Tmp2.getValueType().isVector()) { 1865 ExtOp = ISD::BIT_CONVERT; 1866 TruncOp = ISD::BIT_CONVERT; 1867 } else if (Tmp2.getValueType().isInteger()) { 1868 ExtOp = ISD::ANY_EXTEND; 1869 TruncOp = ISD::TRUNCATE; 1870 } else { 1871 ExtOp = ISD::FP_EXTEND; 1872 TruncOp = ISD::FP_ROUND; 1873 } 1874 // Promote each of the values to the new type. 1875 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2); 1876 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3); 1877 // Perform the larger operation, then round down. 1878 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 1879 if (TruncOp != ISD::FP_ROUND) 1880 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result); 1881 else 1882 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result, 1883 DAG.getIntPtrConstant(0)); 1884 break; 1885 } 1886 } 1887 break; 1888 case ISD::SELECT_CC: { 1889 Tmp1 = Node->getOperand(0); // LHS 1890 Tmp2 = Node->getOperand(1); // RHS 1891 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1892 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1893 SDValue CC = Node->getOperand(4); 1894 1895 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()), 1896 Tmp1, Tmp2, CC, dl); 1897 1898 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 1899 // the LHS is a legal SETCC itself. In this case, we need to compare 1900 // the result against zero to select between true and false values. 1901 if (Tmp2.getNode() == 0) { 1902 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1903 CC = DAG.getCondCode(ISD::SETNE); 1904 } 1905 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 1906 1907 // Everything is legal, see if we should expand this op or something. 1908 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 1909 default: assert(0 && "This action is not supported yet!"); 1910 case TargetLowering::Legal: break; 1911 case TargetLowering::Custom: 1912 Tmp1 = TLI.LowerOperation(Result, DAG); 1913 if (Tmp1.getNode()) Result = Tmp1; 1914 break; 1915 } 1916 break; 1917 } 1918 case ISD::SETCC: 1919 Tmp1 = Node->getOperand(0); 1920 Tmp2 = Node->getOperand(1); 1921 Tmp3 = Node->getOperand(2); 1922 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 1923 1924 // If we had to Expand the SetCC operands into a SELECT node, then it may 1925 // not always be possible to return a true LHS & RHS. In this case, just 1926 // return the value we legalized, returned in the LHS 1927 if (Tmp2.getNode() == 0) { 1928 Result = Tmp1; 1929 break; 1930 } 1931 1932 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 1933 default: assert(0 && "Cannot handle this action for SETCC yet!"); 1934 case TargetLowering::Custom: 1935 isCustom = true; 1936 // FALLTHROUGH. 1937 case TargetLowering::Legal: 1938 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1939 if (isCustom) { 1940 Tmp4 = TLI.LowerOperation(Result, DAG); 1941 if (Tmp4.getNode()) Result = Tmp4; 1942 } 1943 break; 1944 case TargetLowering::Promote: { 1945 // First step, figure out the appropriate operation to use. 1946 // Allow SETCC to not be supported for all legal data types 1947 // Mostly this targets FP 1948 MVT NewInTy = Node->getOperand(0).getValueType(); 1949 MVT OldVT = NewInTy; OldVT = OldVT; 1950 1951 // Scan for the appropriate larger type to use. 1952 while (1) { 1953 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 1954 1955 assert(NewInTy.isInteger() == OldVT.isInteger() && 1956 "Fell off of the edge of the integer world"); 1957 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 1958 "Fell off of the edge of the floating point world"); 1959 1960 // If the target supports SETCC of this type, use it. 1961 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy)) 1962 break; 1963 } 1964 if (NewInTy.isInteger()) 1965 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1966 else { 1967 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1); 1968 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2); 1969 } 1970 Tmp1 = LegalizeOp(Tmp1); 1971 Tmp2 = LegalizeOp(Tmp2); 1972 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1973 Result = LegalizeOp(Result); 1974 break; 1975 } 1976 case TargetLowering::Expand: 1977 // Expand a setcc node into a select_cc of the same condition, lhs, and 1978 // rhs that selects between const 1 (true) and const 0 (false). 1979 MVT VT = Node->getValueType(0); 1980 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 1981 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1982 Tmp3); 1983 break; 1984 } 1985 break; 1986 1987 // Binary operators 1988 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 1989 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1990 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1991 1992 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1993 1994 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1995 default: assert(0 && "Operation not supported"); 1996 case TargetLowering::Custom: 1997 Tmp1 = TLI.LowerOperation(Result, DAG); 1998 if (Tmp1.getNode()) Result = Tmp1; 1999 break; 2000 case TargetLowering::Legal: break; 2001 case TargetLowering::Expand: { 2002 assert((Tmp2.getValueType() == MVT::f32 || 2003 Tmp2.getValueType() == MVT::f64) && 2004 "Ugly special-cased code!"); 2005 // Get the sign bit of the RHS. 2006 SDValue SignBit; 2007 MVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32; 2008 if (isTypeLegal(IVT)) { 2009 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 2010 } else { 2011 assert(isTypeLegal(TLI.getPointerTy()) && 2012 (TLI.getPointerTy() == MVT::i32 || 2013 TLI.getPointerTy() == MVT::i64) && 2014 "Legal type for load?!"); 2015 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType()); 2016 SDValue StorePtr = StackPtr, LoadPtr = StackPtr; 2017 SDValue Ch = 2018 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0); 2019 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian()) 2020 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), 2021 LoadPtr, DAG.getIntPtrConstant(4)); 2022 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(), 2023 Ch, LoadPtr, NULL, 0, MVT::i32); 2024 } 2025 SignBit = 2026 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 2027 SignBit, DAG.getConstant(0, SignBit.getValueType()), 2028 ISD::SETLT); 2029 // Get the absolute value of the result. 2030 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 2031 // Select between the nabs and abs value based on the sign bit of 2032 // the input. 2033 Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 2034 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), 2035 AbsVal), 2036 AbsVal); 2037 Result = LegalizeOp(Result); 2038 break; 2039 } 2040 } 2041 break; 2042 case ISD::BUILD_PAIR: { 2043 MVT PairTy = Node->getValueType(0); 2044 // TODO: handle the case where the Lo and Hi operands are not of legal type 2045 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2046 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2047 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2048 case TargetLowering::Promote: 2049 case TargetLowering::Custom: 2050 assert(0 && "Cannot promote/custom this yet!"); 2051 case TargetLowering::Legal: 2052 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2053 Result = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Tmp1, Tmp2); 2054 break; 2055 case TargetLowering::Expand: 2056 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Tmp1); 2057 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Tmp2); 2058 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 2059 DAG.getConstant(PairTy.getSizeInBits()/2, 2060 TLI.getShiftAmountTy())); 2061 Result = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2); 2062 break; 2063 } 2064 break; 2065 } 2066 2067 case ISD::UREM: 2068 case ISD::SREM: 2069 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2070 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2071 2072 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2073 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2074 case TargetLowering::Custom: 2075 isCustom = true; 2076 // FALLTHROUGH 2077 case TargetLowering::Legal: 2078 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2079 if (isCustom) { 2080 Tmp1 = TLI.LowerOperation(Result, DAG); 2081 if (Tmp1.getNode()) Result = Tmp1; 2082 } 2083 break; 2084 case TargetLowering::Expand: { 2085 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2086 bool isSigned = DivOpc == ISD::SDIV; 2087 MVT VT = Node->getValueType(0); 2088 2089 // See if remainder can be lowered using two-result operations. 2090 SDVTList VTs = DAG.getVTList(VT, VT); 2091 if (Node->getOpcode() == ISD::SREM && 2092 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) { 2093 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl, 2094 VTs, Tmp1, Tmp2).getNode(), 1); 2095 break; 2096 } 2097 if (Node->getOpcode() == ISD::UREM && 2098 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) { 2099 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl, 2100 VTs, Tmp1, Tmp2).getNode(), 1); 2101 break; 2102 } 2103 2104 if (VT.isInteger() && 2105 TLI.getOperationAction(DivOpc, VT) == TargetLowering::Legal) { 2106 // X % Y -> X-X/Y*Y 2107 Result = DAG.getNode(DivOpc, dl, VT, Tmp1, Tmp2); 2108 Result = DAG.getNode(ISD::MUL, dl, VT, Result, Tmp2); 2109 Result = DAG.getNode(ISD::SUB, dl, VT, Tmp1, Result); 2110 break; 2111 } 2112 2113 // Check to see if we have a libcall for this operator. 2114 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2115 switch (Node->getOpcode()) { 2116 default: break; 2117 case ISD::UREM: 2118 case ISD::SREM: 2119 if (VT == MVT::i16) 2120 LC = (isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16); 2121 else if (VT == MVT::i32) 2122 LC = (isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32); 2123 else if (VT == MVT::i64) 2124 LC = (isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64); 2125 else if (VT == MVT::i128) 2126 LC = (isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128); 2127 break; 2128 } 2129 2130 if (LC != RTLIB::UNKNOWN_LIBCALL) { 2131 Result = ExpandLibCall(LC, Node, isSigned); 2132 break; 2133 } 2134 2135 assert(0 && "Cannot expand this binary operator!"); 2136 break; 2137 } 2138 } 2139 break; 2140 case ISD::VAARG: { 2141 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2142 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2143 2144 MVT VT = Node->getValueType(0); 2145 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2146 default: assert(0 && "This action is not supported yet!"); 2147 case TargetLowering::Custom: 2148 isCustom = true; 2149 // FALLTHROUGH 2150 case TargetLowering::Legal: 2151 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2152 Result = Result.getValue(0); 2153 Tmp1 = Result.getValue(1); 2154 2155 if (isCustom) { 2156 Tmp2 = TLI.LowerOperation(Result, DAG); 2157 if (Tmp2.getNode()) { 2158 Result = LegalizeOp(Tmp2); 2159 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2160 } 2161 } 2162 break; 2163 case TargetLowering::Expand: { 2164 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2165 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0); 2166 // Increment the pointer, VAList, to the next vaarg 2167 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2168 DAG.getConstant(TLI.getTargetData()-> 2169 getTypeAllocSize(VT.getTypeForMVT()), 2170 TLI.getPointerTy())); 2171 // Store the incremented VAList to the legalized pointer 2172 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0); 2173 // Load the actual argument out of the pointer VAList 2174 Result = DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0); 2175 Tmp1 = LegalizeOp(Result.getValue(1)); 2176 Result = LegalizeOp(Result); 2177 break; 2178 } 2179 } 2180 // Since VAARG produces two values, make sure to remember that we 2181 // legalized both of them. 2182 AddLegalizedOperand(SDValue(Node, 0), Result); 2183 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 2184 return Op.getResNo() ? Tmp1 : Result; 2185 } 2186 case ISD::SADDO: 2187 case ISD::SSUBO: { 2188 MVT VT = Node->getValueType(0); 2189 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 2190 default: assert(0 && "This action not supported for this op yet!"); 2191 case TargetLowering::Custom: 2192 Result = TLI.LowerOperation(Op, DAG); 2193 if (Result.getNode()) break; 2194 // FALLTHROUGH 2195 case TargetLowering::Legal: { 2196 SDValue LHS = LegalizeOp(Node->getOperand(0)); 2197 SDValue RHS = LegalizeOp(Node->getOperand(1)); 2198 2199 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 2200 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2201 LHS, RHS); 2202 MVT OType = Node->getValueType(1); 2203 2204 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 2205 2206 // LHSSign -> LHS >= 0 2207 // RHSSign -> RHS >= 0 2208 // SumSign -> Sum >= 0 2209 // 2210 // Add: 2211 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 2212 // Sub: 2213 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 2214 // 2215 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 2216 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 2217 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 2218 Node->getOpcode() == ISD::SADDO ? 2219 ISD::SETEQ : ISD::SETNE); 2220 2221 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 2222 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 2223 2224 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 2225 2226 MVT ValueVTs[] = { LHS.getValueType(), OType }; 2227 SDValue Ops[] = { Sum, Cmp }; 2228 2229 Result = DAG.getNode(ISD::MERGE_VALUES, dl, 2230 DAG.getVTList(&ValueVTs[0], 2), 2231 &Ops[0], 2); 2232 SDNode *RNode = Result.getNode(); 2233 DAG.ReplaceAllUsesWith(Node, RNode); 2234 break; 2235 } 2236 } 2237 2238 break; 2239 } 2240 case ISD::UADDO: 2241 case ISD::USUBO: { 2242 MVT VT = Node->getValueType(0); 2243 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 2244 default: assert(0 && "This action not supported for this op yet!"); 2245 case TargetLowering::Custom: 2246 Result = TLI.LowerOperation(Op, DAG); 2247 if (Result.getNode()) break; 2248 // FALLTHROUGH 2249 case TargetLowering::Legal: { 2250 SDValue LHS = LegalizeOp(Node->getOperand(0)); 2251 SDValue RHS = LegalizeOp(Node->getOperand(1)); 2252 2253 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 2254 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2255 LHS, RHS); 2256 MVT OType = Node->getValueType(1); 2257 SDValue Cmp = DAG.getSetCC(dl, OType, Sum, LHS, 2258 Node->getOpcode () == ISD::UADDO ? 2259 ISD::SETULT : ISD::SETUGT); 2260 2261 MVT ValueVTs[] = { LHS.getValueType(), OType }; 2262 SDValue Ops[] = { Sum, Cmp }; 2263 2264 Result = DAG.getNode(ISD::MERGE_VALUES, dl, 2265 DAG.getVTList(&ValueVTs[0], 2), 2266 &Ops[0], 2); 2267 SDNode *RNode = Result.getNode(); 2268 DAG.ReplaceAllUsesWith(Node, RNode); 2269 break; 2270 } 2271 } 2272 2273 break; 2274 } 2275 } 2276 2277 assert(Result.getValueType() == Op.getValueType() && 2278 "Bad legalization!"); 2279 2280 // Make sure that the generated code is itself legal. 2281 if (Result != Op) 2282 Result = LegalizeOp(Result); 2283 2284 // Note that LegalizeOp may be reentered even from single-use nodes, which 2285 // means that we always must cache transformed nodes. 2286 AddLegalizedOperand(Op, Result); 2287 return Result; 2288} 2289 2290SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 2291 SDValue Vec = Op.getOperand(0); 2292 SDValue Idx = Op.getOperand(1); 2293 DebugLoc dl = Op.getDebugLoc(); 2294 // Store the value to a temporary stack slot, then LOAD the returned part. 2295 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 2296 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0); 2297 2298 // Add the offset to the index. 2299 unsigned EltSize = 2300 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 2301 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 2302 DAG.getConstant(EltSize, Idx.getValueType())); 2303 2304 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 2305 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 2306 else 2307 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 2308 2309 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 2310 2311 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0); 2312} 2313 2314/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 2315/// with condition CC on the current target. This usually involves legalizing 2316/// or promoting the arguments. In the case where LHS and RHS must be expanded, 2317/// there may be no choice but to create a new SetCC node to represent the 2318/// legalized value of setcc lhs, rhs. In this case, the value is returned in 2319/// LHS, and the SDValue returned in RHS has a nil SDNode value. 2320void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS, 2321 SDValue &RHS, 2322 SDValue &CC, 2323 DebugLoc dl) { 2324 LHS = LegalizeOp(LHS); 2325 RHS = LegalizeOp(RHS); 2326} 2327 2328/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 2329/// condition code CC on the current target. This routine assumes LHS and rHS 2330/// have already been legalized by LegalizeSetCCOperands. It expands SETCC with 2331/// illegal condition code into AND / OR of multiple SETCC values. 2332void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, 2333 SDValue &LHS, SDValue &RHS, 2334 SDValue &CC, 2335 DebugLoc dl) { 2336 MVT OpVT = LHS.getValueType(); 2337 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 2338 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 2339 default: assert(0 && "Unknown condition code action!"); 2340 case TargetLowering::Legal: 2341 // Nothing to do. 2342 break; 2343 case TargetLowering::Expand: { 2344 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 2345 unsigned Opc = 0; 2346 switch (CCCode) { 2347 default: assert(0 && "Don't know how to expand this condition!"); abort(); 2348 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 2349 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 2350 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 2351 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 2352 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 2353 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 2354 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 2355 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 2356 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 2357 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 2358 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 2359 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 2360 // FIXME: Implement more expansions. 2361 } 2362 2363 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 2364 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 2365 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 2366 RHS = SDValue(); 2367 CC = SDValue(); 2368 break; 2369 } 2370 } 2371} 2372 2373/// EmitStackConvert - Emit a store/load combination to the stack. This stores 2374/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 2375/// a load from the stack slot to DestVT, extending it if needed. 2376/// The resultant code need not be legal. 2377SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 2378 MVT SlotVT, 2379 MVT DestVT, 2380 DebugLoc dl) { 2381 // Create the stack frame object. 2382 unsigned SrcAlign = 2383 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 2384 getTypeForMVT()); 2385 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 2386 2387 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 2388 int SPFI = StackPtrFI->getIndex(); 2389 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 2390 2391 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 2392 unsigned SlotSize = SlotVT.getSizeInBits(); 2393 unsigned DestSize = DestVT.getSizeInBits(); 2394 unsigned DestAlign = 2395 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT()); 2396 2397 // Emit a store to the stack slot. Use a truncstore if the input value is 2398 // later than DestVT. 2399 SDValue Store; 2400 2401 if (SrcSize > SlotSize) 2402 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 2403 SV, 0, SlotVT, false, SrcAlign); 2404 else { 2405 assert(SrcSize == SlotSize && "Invalid store"); 2406 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 2407 SV, 0, false, SrcAlign); 2408 } 2409 2410 // Result is a load from the stack slot. 2411 if (SlotSize == DestSize) 2412 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign); 2413 2414 assert(SlotSize < DestSize && "Unknown extension!"); 2415 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, 2416 false, DestAlign); 2417} 2418 2419SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 2420 DebugLoc dl = Node->getDebugLoc(); 2421 // Create a vector sized/aligned stack slot, store the value to element #0, 2422 // then load the whole vector back out. 2423 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 2424 2425 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 2426 int SPFI = StackPtrFI->getIndex(); 2427 2428 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 2429 StackPtr, 2430 PseudoSourceValue::getFixedStack(SPFI), 0, 2431 Node->getValueType(0).getVectorElementType()); 2432 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 2433 PseudoSourceValue::getFixedStack(SPFI), 0); 2434} 2435 2436 2437/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 2438/// support the operation, but do support the resultant vector type. 2439SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 2440 unsigned NumElems = Node->getNumOperands(); 2441 SDValue SplatValue = Node->getOperand(0); 2442 DebugLoc dl = Node->getDebugLoc(); 2443 MVT VT = Node->getValueType(0); 2444 MVT OpVT = SplatValue.getValueType(); 2445 MVT EltVT = VT.getVectorElementType(); 2446 2447 // If the only non-undef value is the low element, turn this into a 2448 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 2449 bool isOnlyLowElement = true; 2450 2451 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t> 2452 // and use a bitmask instead of a list of elements. 2453 // FIXME: this doesn't treat <0, u, 0, u> for example, as a splat. 2454 std::map<SDValue, std::vector<unsigned> > Values; 2455 Values[SplatValue].push_back(0); 2456 bool isConstant = true; 2457 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 2458 SplatValue.getOpcode() != ISD::UNDEF) 2459 isConstant = false; 2460 2461 for (unsigned i = 1; i < NumElems; ++i) { 2462 SDValue V = Node->getOperand(i); 2463 Values[V].push_back(i); 2464 if (V.getOpcode() != ISD::UNDEF) 2465 isOnlyLowElement = false; 2466 if (SplatValue != V) 2467 SplatValue = SDValue(0, 0); 2468 2469 // If this isn't a constant element or an undef, we can't use a constant 2470 // pool load. 2471 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 2472 V.getOpcode() != ISD::UNDEF) 2473 isConstant = false; 2474 } 2475 2476 if (isOnlyLowElement) { 2477 // If the low element is an undef too, then this whole things is an undef. 2478 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 2479 return DAG.getUNDEF(VT); 2480 // Otherwise, turn this into a scalar_to_vector node. 2481 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 2482 } 2483 2484 // If all elements are constants, create a load from the constant pool. 2485 if (isConstant) { 2486 std::vector<Constant*> CV; 2487 for (unsigned i = 0, e = NumElems; i != e; ++i) { 2488 if (ConstantFPSDNode *V = 2489 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 2490 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 2491 } else if (ConstantSDNode *V = 2492 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 2493 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 2494 } else { 2495 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 2496 const Type *OpNTy = OpVT.getTypeForMVT(); 2497 CV.push_back(UndefValue::get(OpNTy)); 2498 } 2499 } 2500 Constant *CP = ConstantVector::get(CV); 2501 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 2502 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2503 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 2504 PseudoSourceValue::getConstantPool(), 0, 2505 false, Alignment); 2506 } 2507 2508 if (SplatValue.getNode()) { // Splat of one value? 2509 // Build the shuffle constant vector: <0, 0, 0, 0> 2510 SmallVector<int, 8> ZeroVec(NumElems, 0); 2511 2512 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 2513 if (TLI.isShuffleMaskLegal(ZeroVec, Node->getValueType(0))) { 2514 // Get the splatted value into the low element of a vector register. 2515 SDValue LowValVec = 2516 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, SplatValue); 2517 2518 // Return shuffle(LowValVec, undef, <0,0,0,0>) 2519 return DAG.getVectorShuffle(VT, dl, LowValVec, DAG.getUNDEF(VT), 2520 &ZeroVec[0]); 2521 } 2522 } 2523 2524 // If there are only two unique elements, we may be able to turn this into a 2525 // vector shuffle. 2526 if (Values.size() == 2) { 2527 // Get the two values in deterministic order. 2528 SDValue Val1 = Node->getOperand(1); 2529 SDValue Val2; 2530 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin(); 2531 if (MI->first != Val1) 2532 Val2 = MI->first; 2533 else 2534 Val2 = (++MI)->first; 2535 2536 // If Val1 is an undef, make sure it ends up as Val2, to ensure that our 2537 // vector shuffle has the undef vector on the RHS. 2538 if (Val1.getOpcode() == ISD::UNDEF) 2539 std::swap(Val1, Val2); 2540 2541 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 2542 SmallVector<int, 8> ShuffleMask(NumElems, -1); 2543 2544 // Set elements of the shuffle mask for Val1. 2545 std::vector<unsigned> &Val1Elts = Values[Val1]; 2546 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 2547 ShuffleMask[Val1Elts[i]] = 0; 2548 2549 // Set elements of the shuffle mask for Val2. 2550 std::vector<unsigned> &Val2Elts = Values[Val2]; 2551 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 2552 if (Val2.getOpcode() != ISD::UNDEF) 2553 ShuffleMask[Val2Elts[i]] = NumElems; 2554 2555 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 2556 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, VT) && 2557 TLI.isShuffleMaskLegal(ShuffleMask, VT)) { 2558 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val1); 2559 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val2); 2560 return DAG.getVectorShuffle(VT, dl, Val1, Val2, &ShuffleMask[0]); 2561 } 2562 } 2563 2564 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 2565 // aligned object on the stack, store each element into it, then load 2566 // the result as a vector. 2567 // Create the stack frame object. 2568 SDValue FIPtr = DAG.CreateStackTemporary(VT); 2569 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 2570 const Value *SV = PseudoSourceValue::getFixedStack(FI); 2571 2572 // Emit a store of each element to the stack slot. 2573 SmallVector<SDValue, 8> Stores; 2574 unsigned TypeByteSize = OpVT.getSizeInBits() / 8; 2575 // Store (in the right endianness) the elements to memory. 2576 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2577 // Ignore undef elements. 2578 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 2579 2580 unsigned Offset = TypeByteSize*i; 2581 2582 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 2583 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 2584 2585 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i), 2586 Idx, SV, Offset)); 2587 } 2588 2589 SDValue StoreChain; 2590 if (!Stores.empty()) // Not all undef elements? 2591 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2592 &Stores[0], Stores.size()); 2593 else 2594 StoreChain = DAG.getEntryNode(); 2595 2596 // Result is a load from the stack slot. 2597 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0); 2598} 2599 2600// ExpandLibCall - Expand a node into a call to a libcall. If the result value 2601// does not fit into a register, return the lo part and set the hi part to the 2602// by-reg argument. If it does fit into a single register, return the result 2603// and leave the Hi part unset. 2604SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 2605 bool isSigned) { 2606 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 2607 // The input chain to this libcall is the entry node of the function. 2608 // Legalizing the call will automatically add the previous call to the 2609 // dependence. 2610 SDValue InChain = DAG.getEntryNode(); 2611 2612 TargetLowering::ArgListTy Args; 2613 TargetLowering::ArgListEntry Entry; 2614 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2615 MVT ArgVT = Node->getOperand(i).getValueType(); 2616 const Type *ArgTy = ArgVT.getTypeForMVT(); 2617 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 2618 Entry.isSExt = isSigned; 2619 Entry.isZExt = !isSigned; 2620 Args.push_back(Entry); 2621 } 2622 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 2623 TLI.getPointerTy()); 2624 2625 // Splice the libcall in wherever FindInputOutputChains tells us to. 2626 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 2627 std::pair<SDValue, SDValue> CallInfo = 2628 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 2629 CallingConv::C, false, Callee, Args, DAG, 2630 Node->getDebugLoc()); 2631 2632 // Legalize the call sequence, starting with the chain. This will advance 2633 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 2634 // was added by LowerCallTo (guaranteeing proper serialization of calls). 2635 LegalizeOp(CallInfo.second); 2636 return CallInfo.first; 2637} 2638 2639SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 2640 RTLIB::Libcall Call_F32, 2641 RTLIB::Libcall Call_F64, 2642 RTLIB::Libcall Call_F80, 2643 RTLIB::Libcall Call_PPCF128) { 2644 RTLIB::Libcall LC; 2645 switch (Node->getValueType(0).getSimpleVT()) { 2646 default: assert(0 && "Unexpected request for libcall!"); 2647 case MVT::f32: LC = Call_F32; break; 2648 case MVT::f64: LC = Call_F64; break; 2649 case MVT::f80: LC = Call_F80; break; 2650 case MVT::ppcf128: LC = Call_PPCF128; break; 2651 } 2652 return ExpandLibCall(LC, Node, false); 2653} 2654 2655SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 2656 RTLIB::Libcall Call_I16, 2657 RTLIB::Libcall Call_I32, 2658 RTLIB::Libcall Call_I64, 2659 RTLIB::Libcall Call_I128) { 2660 RTLIB::Libcall LC; 2661 switch (Node->getValueType(0).getSimpleVT()) { 2662 default: assert(0 && "Unexpected request for libcall!"); 2663 case MVT::i16: LC = Call_I16; break; 2664 case MVT::i32: LC = Call_I32; break; 2665 case MVT::i64: LC = Call_I64; break; 2666 case MVT::i128: LC = Call_I128; break; 2667 } 2668 return ExpandLibCall(LC, Node, isSigned); 2669} 2670 2671/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 2672/// INT_TO_FP operation of the specified operand when the target requests that 2673/// we expand it. At this point, we know that the result and operand types are 2674/// legal for the target. 2675SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 2676 SDValue Op0, 2677 MVT DestVT, 2678 DebugLoc dl) { 2679 if (Op0.getValueType() == MVT::i32) { 2680 // simple 32-bit [signed|unsigned] integer to float/double expansion 2681 2682 // Get the stack frame index of a 8 byte buffer. 2683 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 2684 2685 // word offset constant for Hi/Lo address computation 2686 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 2687 // set up Hi and Lo (into buffer) address based on endian 2688 SDValue Hi = StackSlot; 2689 SDValue Lo = DAG.getNode(ISD::ADD, dl, 2690 TLI.getPointerTy(), StackSlot, WordOff); 2691 if (TLI.isLittleEndian()) 2692 std::swap(Hi, Lo); 2693 2694 // if signed map to unsigned space 2695 SDValue Op0Mapped; 2696 if (isSigned) { 2697 // constant used to invert sign bit (signed to unsigned mapping) 2698 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 2699 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 2700 } else { 2701 Op0Mapped = Op0; 2702 } 2703 // store the lo of the constructed double - based on integer input 2704 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 2705 Op0Mapped, Lo, NULL, 0); 2706 // initial hi portion of constructed double 2707 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2708 // store the hi of the constructed double - biased exponent 2709 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0); 2710 // load the constructed double 2711 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0); 2712 // FP constant to bias correct the final result 2713 SDValue Bias = DAG.getConstantFP(isSigned ? 2714 BitsToDouble(0x4330000080000000ULL) : 2715 BitsToDouble(0x4330000000000000ULL), 2716 MVT::f64); 2717 // subtract the bias 2718 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2719 // final result 2720 SDValue Result; 2721 // handle final rounding 2722 if (DestVT == MVT::f64) { 2723 // do nothing 2724 Result = Sub; 2725 } else if (DestVT.bitsLT(MVT::f64)) { 2726 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2727 DAG.getIntPtrConstant(0)); 2728 } else if (DestVT.bitsGT(MVT::f64)) { 2729 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2730 } 2731 return Result; 2732 } 2733 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2734 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2735 2736 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2737 Op0, DAG.getConstant(0, Op0.getValueType()), 2738 ISD::SETLT); 2739 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2740 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2741 SignSet, Four, Zero); 2742 2743 // If the sign bit of the integer is set, the large number will be treated 2744 // as a negative number. To counteract this, the dynamic code adds an 2745 // offset depending on the data type. 2746 uint64_t FF; 2747 switch (Op0.getValueType().getSimpleVT()) { 2748 default: assert(0 && "Unsupported integer type!"); 2749 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2750 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2751 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2752 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2753 } 2754 if (TLI.isLittleEndian()) FF <<= 32; 2755 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 2756 2757 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2758 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2759 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2760 Alignment = std::min(Alignment, 4u); 2761 SDValue FudgeInReg; 2762 if (DestVT == MVT::f32) 2763 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2764 PseudoSourceValue::getConstantPool(), 0, 2765 false, Alignment); 2766 else { 2767 FudgeInReg = 2768 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2769 DAG.getEntryNode(), CPIdx, 2770 PseudoSourceValue::getConstantPool(), 0, 2771 MVT::f32, false, Alignment)); 2772 } 2773 2774 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2775} 2776 2777/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2778/// *INT_TO_FP operation of the specified operand when the target requests that 2779/// we promote it. At this point, we know that the result and operand types are 2780/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2781/// operation that takes a larger input. 2782SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2783 MVT DestVT, 2784 bool isSigned, 2785 DebugLoc dl) { 2786 // First step, figure out the appropriate *INT_TO_FP operation to use. 2787 MVT NewInTy = LegalOp.getValueType(); 2788 2789 unsigned OpToUse = 0; 2790 2791 // Scan for the appropriate larger type to use. 2792 while (1) { 2793 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 2794 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2795 2796 // If the target supports SINT_TO_FP of this type, use it. 2797 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 2798 default: break; 2799 case TargetLowering::Legal: 2800 if (!TLI.isTypeLegal(NewInTy)) 2801 break; // Can't use this datatype. 2802 // FALL THROUGH. 2803 case TargetLowering::Custom: 2804 OpToUse = ISD::SINT_TO_FP; 2805 break; 2806 } 2807 if (OpToUse) break; 2808 if (isSigned) continue; 2809 2810 // If the target supports UINT_TO_FP of this type, use it. 2811 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 2812 default: break; 2813 case TargetLowering::Legal: 2814 if (!TLI.isTypeLegal(NewInTy)) 2815 break; // Can't use this datatype. 2816 // FALL THROUGH. 2817 case TargetLowering::Custom: 2818 OpToUse = ISD::UINT_TO_FP; 2819 break; 2820 } 2821 if (OpToUse) break; 2822 2823 // Otherwise, try a larger type. 2824 } 2825 2826 // Okay, we found the operation and type to use. Zero extend our input to the 2827 // desired type then run the operation on it. 2828 return DAG.getNode(OpToUse, dl, DestVT, 2829 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2830 dl, NewInTy, LegalOp)); 2831} 2832 2833/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2834/// FP_TO_*INT operation of the specified operand when the target requests that 2835/// we promote it. At this point, we know that the result and operand types are 2836/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2837/// operation that returns a larger result. 2838SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2839 MVT DestVT, 2840 bool isSigned, 2841 DebugLoc dl) { 2842 // First step, figure out the appropriate FP_TO*INT operation to use. 2843 MVT NewOutTy = DestVT; 2844 2845 unsigned OpToUse = 0; 2846 2847 // Scan for the appropriate larger type to use. 2848 while (1) { 2849 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 2850 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2851 2852 // If the target supports FP_TO_SINT returning this type, use it. 2853 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 2854 default: break; 2855 case TargetLowering::Legal: 2856 if (!TLI.isTypeLegal(NewOutTy)) 2857 break; // Can't use this datatype. 2858 // FALL THROUGH. 2859 case TargetLowering::Custom: 2860 OpToUse = ISD::FP_TO_SINT; 2861 break; 2862 } 2863 if (OpToUse) break; 2864 2865 // If the target supports FP_TO_UINT of this type, use it. 2866 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 2867 default: break; 2868 case TargetLowering::Legal: 2869 if (!TLI.isTypeLegal(NewOutTy)) 2870 break; // Can't use this datatype. 2871 // FALL THROUGH. 2872 case TargetLowering::Custom: 2873 OpToUse = ISD::FP_TO_UINT; 2874 break; 2875 } 2876 if (OpToUse) break; 2877 2878 // Otherwise, try a larger type. 2879 } 2880 2881 2882 // Okay, we found the operation and type to use. 2883 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2884 2885 // If the operation produces an invalid type, it must be custom lowered. Use 2886 // the target lowering hooks to expand it. Just keep the low part of the 2887 // expanded operation, we know that we're truncating anyway. 2888 if (getTypeAction(NewOutTy) == Expand) { 2889 SmallVector<SDValue, 2> Results; 2890 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG); 2891 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!"); 2892 Operation = Results[0]; 2893 } 2894 2895 // Truncate the result of the extended FP_TO_*INT operation to the desired 2896 // size. 2897 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2898} 2899 2900/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2901/// 2902SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2903 MVT VT = Op.getValueType(); 2904 MVT SHVT = TLI.getShiftAmountTy(); 2905 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2906 switch (VT.getSimpleVT()) { 2907 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 2908 case MVT::i16: 2909 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2910 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2911 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2912 case MVT::i32: 2913 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2914 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2915 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2916 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2917 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2918 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2919 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2920 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2921 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2922 case MVT::i64: 2923 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2924 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2925 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2926 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2927 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2928 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2929 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2930 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2931 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2932 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2933 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2934 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2935 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2936 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2937 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2938 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2939 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2940 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2941 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2942 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2943 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2944 } 2945} 2946 2947/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2948/// 2949SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2950 DebugLoc dl) { 2951 switch (Opc) { 2952 default: assert(0 && "Cannot expand this yet!"); 2953 case ISD::CTPOP: { 2954 static const uint64_t mask[6] = { 2955 0x5555555555555555ULL, 0x3333333333333333ULL, 2956 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2957 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2958 }; 2959 MVT VT = Op.getValueType(); 2960 MVT ShVT = TLI.getShiftAmountTy(); 2961 unsigned len = VT.getSizeInBits(); 2962 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2963 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2964 unsigned EltSize = VT.isVector() ? 2965 VT.getVectorElementType().getSizeInBits() : len; 2966 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2967 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2968 Op = DAG.getNode(ISD::ADD, dl, VT, 2969 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2970 DAG.getNode(ISD::AND, dl, VT, 2971 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2972 Tmp2)); 2973 } 2974 return Op; 2975 } 2976 case ISD::CTLZ: { 2977 // for now, we do this: 2978 // x = x | (x >> 1); 2979 // x = x | (x >> 2); 2980 // ... 2981 // x = x | (x >>16); 2982 // x = x | (x >>32); // for 64-bit input 2983 // return popcount(~x); 2984 // 2985 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2986 MVT VT = Op.getValueType(); 2987 MVT ShVT = TLI.getShiftAmountTy(); 2988 unsigned len = VT.getSizeInBits(); 2989 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2990 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2991 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2992 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2993 } 2994 Op = DAG.getNOT(dl, Op, VT); 2995 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2996 } 2997 case ISD::CTTZ: { 2998 // for now, we use: { return popcount(~x & (x - 1)); } 2999 // unless the target has ctlz but not ctpop, in which case we use: 3000 // { return 32 - nlz(~x & (x-1)); } 3001 // see also http://www.hackersdelight.org/HDcode/ntz.cc 3002 MVT VT = Op.getValueType(); 3003 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 3004 DAG.getNOT(dl, Op, VT), 3005 DAG.getNode(ISD::SUB, dl, VT, Op, 3006 DAG.getConstant(1, VT))); 3007 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 3008 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 3009 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 3010 return DAG.getNode(ISD::SUB, dl, VT, 3011 DAG.getConstant(VT.getSizeInBits(), VT), 3012 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 3013 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 3014 } 3015 } 3016} 3017 3018void SelectionDAGLegalize::ExpandNode(SDNode *Node, 3019 SmallVectorImpl<SDValue> &Results) { 3020 DebugLoc dl = Node->getDebugLoc(); 3021 SDValue Tmp1, Tmp2, Tmp3; 3022 switch (Node->getOpcode()) { 3023 case ISD::CTPOP: 3024 case ISD::CTLZ: 3025 case ISD::CTTZ: 3026 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 3027 Results.push_back(Tmp1); 3028 break; 3029 case ISD::BSWAP: 3030 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 3031 break; 3032 case ISD::FRAMEADDR: 3033 case ISD::RETURNADDR: 3034 case ISD::FRAME_TO_ARGS_OFFSET: 3035 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 3036 break; 3037 case ISD::FLT_ROUNDS_: 3038 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 3039 break; 3040 case ISD::EH_RETURN: 3041 case ISD::DECLARE: 3042 case ISD::DBG_LABEL: 3043 case ISD::EH_LABEL: 3044 case ISD::PREFETCH: 3045 case ISD::MEMBARRIER: 3046 case ISD::VAEND: 3047 Results.push_back(Node->getOperand(0)); 3048 break; 3049 case ISD::MERGE_VALUES: 3050 for (unsigned i = 0; i < Node->getNumValues(); i++) 3051 Results.push_back(Node->getOperand(i)); 3052 break; 3053 case ISD::UNDEF: { 3054 MVT VT = Node->getValueType(0); 3055 if (VT.isInteger()) 3056 Results.push_back(DAG.getConstant(0, VT)); 3057 else if (VT.isFloatingPoint()) 3058 Results.push_back(DAG.getConstantFP(0, VT)); 3059 else 3060 assert(0 && "Unknown value type!"); 3061 break; 3062 } 3063 case ISD::TRAP: { 3064 // If this operation is not supported, lower it to 'abort()' call 3065 TargetLowering::ArgListTy Args; 3066 std::pair<SDValue, SDValue> CallResult = 3067 TLI.LowerCallTo(Node->getOperand(0), Type::VoidTy, 3068 false, false, false, false, CallingConv::C, false, 3069 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 3070 Args, DAG, dl); 3071 Results.push_back(CallResult.second); 3072 break; 3073 } 3074 case ISD::FP_ROUND: 3075 case ISD::BIT_CONVERT: 3076 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3077 Node->getValueType(0), dl); 3078 Results.push_back(Tmp1); 3079 break; 3080 case ISD::FP_EXTEND: 3081 Tmp1 = EmitStackConvert(Node->getOperand(0), 3082 Node->getOperand(0).getValueType(), 3083 Node->getValueType(0), dl); 3084 Results.push_back(Tmp1); 3085 break; 3086 case ISD::SIGN_EXTEND_INREG: { 3087 // NOTE: we could fall back on load/store here too for targets without 3088 // SAR. However, it is doubtful that any exist. 3089 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3090 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 3091 ExtraVT.getSizeInBits(); 3092 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3093 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 3094 Node->getOperand(0), ShiftCst); 3095 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 3096 Results.push_back(Tmp1); 3097 break; 3098 } 3099 case ISD::FP_ROUND_INREG: { 3100 // The only way we can lower this is to turn it into a TRUNCSTORE, 3101 // EXTLOAD pair, targetting a temporary location (a stack slot). 3102 3103 // NOTE: there is a choice here between constantly creating new stack 3104 // slots and always reusing the same one. We currently always create 3105 // new ones, as reuse may inhibit scheduling. 3106 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3107 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 3108 Node->getValueType(0), dl); 3109 Results.push_back(Tmp1); 3110 break; 3111 } 3112 case ISD::SINT_TO_FP: 3113 case ISD::UINT_TO_FP: 3114 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 3115 Node->getOperand(0), Node->getValueType(0), dl); 3116 Results.push_back(Tmp1); 3117 break; 3118 case ISD::FP_TO_UINT: { 3119 SDValue True, False; 3120 MVT VT = Node->getOperand(0).getValueType(); 3121 MVT NVT = Node->getValueType(0); 3122 const uint64_t zero[] = {0, 0}; 3123 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 3124 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 3125 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 3126 Tmp1 = DAG.getConstantFP(apf, VT); 3127 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 3128 Node->getOperand(0), 3129 Tmp1, ISD::SETLT); 3130 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 3131 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 3132 DAG.getNode(ISD::FSUB, dl, VT, 3133 Node->getOperand(0), Tmp1)); 3134 False = DAG.getNode(ISD::XOR, dl, NVT, False, 3135 DAG.getConstant(x, NVT)); 3136 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 3137 Results.push_back(Tmp1); 3138 break; 3139 } 3140 case ISD::VACOPY: { 3141 // This defaults to loading a pointer from the input and storing it to the 3142 // output, returning the chain. 3143 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3144 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3145 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 3146 Node->getOperand(2), VS, 0); 3147 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0); 3148 Results.push_back(Tmp1); 3149 break; 3150 } 3151 case ISD::EXTRACT_VECTOR_ELT: 3152 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 3153 // This must be an access of the only element. Return it. 3154 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 3155 Node->getOperand(0)); 3156 else 3157 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 3158 Results.push_back(Tmp1); 3159 break; 3160 case ISD::EXTRACT_SUBVECTOR: 3161 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 3162 break; 3163 case ISD::SCALAR_TO_VECTOR: 3164 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 3165 break; 3166 case ISD::INSERT_VECTOR_ELT: 3167 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 3168 Node->getOperand(1), 3169 Node->getOperand(2), dl)); 3170 break; 3171 case ISD::EXTRACT_ELEMENT: { 3172 MVT OpTy = Node->getOperand(0).getValueType(); 3173 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 3174 // 1 -> Hi 3175 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 3176 DAG.getConstant(OpTy.getSizeInBits()/2, 3177 TLI.getShiftAmountTy())); 3178 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 3179 } else { 3180 // 0 -> Lo 3181 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 3182 Node->getOperand(0)); 3183 } 3184 Results.push_back(Tmp1); 3185 break; 3186 } 3187 case ISD::STACKSAVE: 3188 // Expand to CopyFromReg if the target set 3189 // StackPointerRegisterToSaveRestore. 3190 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 3191 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 3192 Node->getValueType(0))); 3193 Results.push_back(Results[0].getValue(1)); 3194 } else { 3195 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 3196 Results.push_back(Node->getOperand(0)); 3197 } 3198 break; 3199 case ISD::STACKRESTORE: 3200 // Expand to CopyToReg if the target set 3201 // StackPointerRegisterToSaveRestore. 3202 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 3203 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 3204 Node->getOperand(1))); 3205 } else { 3206 Results.push_back(Node->getOperand(0)); 3207 } 3208 break; 3209 case ISD::FNEG: 3210 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3211 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3212 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 3213 Node->getOperand(0)); 3214 Results.push_back(Tmp1); 3215 break; 3216 case ISD::FABS: { 3217 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3218 MVT VT = Node->getValueType(0); 3219 Tmp1 = Node->getOperand(0); 3220 Tmp2 = DAG.getConstantFP(0.0, VT); 3221 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 3222 Tmp1, Tmp2, ISD::SETUGT); 3223 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 3224 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 3225 Results.push_back(Tmp1); 3226 break; 3227 } 3228 case ISD::FSQRT: 3229 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3230 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 3231 break; 3232 case ISD::FSIN: 3233 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 3234 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 3235 break; 3236 case ISD::FCOS: 3237 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 3238 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 3239 break; 3240 case ISD::FLOG: 3241 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 3242 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 3243 break; 3244 case ISD::FLOG2: 3245 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 3246 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 3247 break; 3248 case ISD::FLOG10: 3249 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 3250 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 3251 break; 3252 case ISD::FEXP: 3253 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 3254 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 3255 break; 3256 case ISD::FEXP2: 3257 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 3258 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 3259 break; 3260 case ISD::FTRUNC: 3261 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 3262 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 3263 break; 3264 case ISD::FFLOOR: 3265 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 3266 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 3267 break; 3268 case ISD::FCEIL: 3269 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 3270 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 3271 break; 3272 case ISD::FRINT: 3273 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 3274 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 3275 break; 3276 case ISD::FNEARBYINT: 3277 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 3278 RTLIB::NEARBYINT_F64, 3279 RTLIB::NEARBYINT_F80, 3280 RTLIB::NEARBYINT_PPCF128)); 3281 break; 3282 case ISD::FPOWI: 3283 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 3284 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 3285 break; 3286 case ISD::FPOW: 3287 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 3288 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 3289 break; 3290 case ISD::FDIV: 3291 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 3292 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 3293 break; 3294 case ISD::FREM: 3295 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 3296 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 3297 break; 3298 case ISD::EHSELECTION: { 3299 unsigned Reg = TLI.getExceptionSelectorRegister(); 3300 assert(Reg && "Can't expand to unknown register!"); 3301 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 3302 Node->getValueType(0))); 3303 Results.push_back(Results[0].getValue(1)); 3304 break; 3305 } 3306 case ISD::EXCEPTIONADDR: { 3307 unsigned Reg = TLI.getExceptionAddressRegister(); 3308 assert(Reg && "Can't expand to unknown register!"); 3309 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 3310 Node->getValueType(0))); 3311 Results.push_back(Results[0].getValue(1)); 3312 break; 3313 } 3314 case ISD::SUB: { 3315 MVT VT = Node->getValueType(0); 3316 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 3317 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 3318 "Don't know how to expand this subtraction!"); 3319 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 3320 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 3321 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 3322 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 3323 break; 3324 } 3325 case ISD::UDIV: 3326 case ISD::UREM: { 3327 bool isRem = Node->getOpcode() == ISD::UREM; 3328 MVT VT = Node->getValueType(0); 3329 SDVTList VTs = DAG.getVTList(VT, VT); 3330 if (TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) 3331 Tmp1 = DAG.getNode(ISD::UDIVREM, dl, VTs, Node->getOperand(0), 3332 Node->getOperand(1)).getValue(isRem); 3333 else if (isRem) 3334 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UREM_I16, RTLIB::UREM_I32, 3335 RTLIB::UREM_I64, RTLIB::UREM_I128); 3336 else 3337 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UDIV_I16, RTLIB::UDIV_I32, 3338 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 3339 Results.push_back(Tmp1); 3340 break; 3341 } 3342 case ISD::SDIV: 3343 case ISD::SREM: { 3344 bool isRem = Node->getOpcode() == ISD::SREM; 3345 MVT VT = Node->getValueType(0); 3346 SDVTList VTs = DAG.getVTList(VT, VT); 3347 if (TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) 3348 Tmp1 = DAG.getNode(ISD::SDIVREM, dl, VTs, Node->getOperand(0), 3349 Node->getOperand(1)).getValue(isRem); 3350 else if (isRem) 3351 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SREM_I16, RTLIB::SREM_I32, 3352 RTLIB::SREM_I64, RTLIB::SREM_I128); 3353 else 3354 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SDIV_I16, RTLIB::SDIV_I32, 3355 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 3356 Results.push_back(Tmp1); 3357 break; 3358 } 3359 case ISD::MULHU: 3360 case ISD::MULHS: { 3361 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 3362 ISD::SMUL_LOHI; 3363 MVT VT = Node->getValueType(0); 3364 SDVTList VTs = DAG.getVTList(VT, VT); 3365 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 3366 "If this wasn't legal, it shouldn't have been created!"); 3367 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 3368 Node->getOperand(1)); 3369 Results.push_back(Tmp1.getValue(1)); 3370 break; 3371 } 3372 case ISD::MUL: { 3373 MVT VT = Node->getValueType(0); 3374 SDVTList VTs = DAG.getVTList(VT, VT); 3375 // See if multiply or divide can be lowered using two-result operations. 3376 // We just need the low half of the multiply; try both the signed 3377 // and unsigned forms. If the target supports both SMUL_LOHI and 3378 // UMUL_LOHI, form a preference by checking which forms of plain 3379 // MULH it supports. 3380 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 3381 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 3382 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 3383 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 3384 unsigned OpToUse = 0; 3385 if (HasSMUL_LOHI && !HasMULHS) { 3386 OpToUse = ISD::SMUL_LOHI; 3387 } else if (HasUMUL_LOHI && !HasMULHU) { 3388 OpToUse = ISD::UMUL_LOHI; 3389 } else if (HasSMUL_LOHI) { 3390 OpToUse = ISD::SMUL_LOHI; 3391 } else if (HasUMUL_LOHI) { 3392 OpToUse = ISD::UMUL_LOHI; 3393 } 3394 if (OpToUse) { 3395 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2)); 3396 break; 3397 } 3398 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::MUL_I16, RTLIB::MUL_I32, 3399 RTLIB::MUL_I64, RTLIB::MUL_I128); 3400 Results.push_back(Tmp1); 3401 break; 3402 } 3403 case ISD::GLOBAL_OFFSET_TABLE: 3404 case ISD::GlobalAddress: 3405 case ISD::GlobalTLSAddress: 3406 case ISD::ExternalSymbol: 3407 case ISD::ConstantPool: 3408 case ISD::JumpTable: 3409 case ISD::INTRINSIC_W_CHAIN: 3410 case ISD::INTRINSIC_WO_CHAIN: 3411 case ISD::INTRINSIC_VOID: 3412 // FIXME: Custom lowering for these operations shouldn't return null! 3413 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3414 Results.push_back(SDValue(Node, i)); 3415 break; 3416 } 3417} 3418void SelectionDAGLegalize::PromoteNode(SDNode *Node, 3419 SmallVectorImpl<SDValue> &Results) { 3420 MVT OVT = Node->getValueType(0); 3421 if (Node->getOpcode() == ISD::UINT_TO_FP || 3422 Node->getOpcode() == ISD::SINT_TO_FP) { 3423 OVT = Node->getOperand(0).getValueType(); 3424 } 3425 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3426 DebugLoc dl = Node->getDebugLoc(); 3427 SDValue Tmp1, Tmp2; 3428 switch (Node->getOpcode()) { 3429 case ISD::CTTZ: 3430 case ISD::CTLZ: 3431 case ISD::CTPOP: 3432 // Zero extend the argument. 3433 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3434 // Perform the larger operation. 3435 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1); 3436 if (Node->getOpcode() == ISD::CTTZ) { 3437 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3438 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 3439 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3440 ISD::SETEQ); 3441 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3442 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3443 } else if (Node->getOpcode() == ISD::CTLZ) { 3444 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3445 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3446 DAG.getConstant(NVT.getSizeInBits() - 3447 OVT.getSizeInBits(), NVT)); 3448 } 3449 Results.push_back(Tmp1); 3450 break; 3451 case ISD::BSWAP: { 3452 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3453 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1); 3454 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3455 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3456 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3457 Results.push_back(Tmp1); 3458 break; 3459 } 3460 case ISD::FP_TO_UINT: 3461 case ISD::FP_TO_SINT: 3462 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3463 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3464 Results.push_back(Tmp1); 3465 break; 3466 case ISD::UINT_TO_FP: 3467 case ISD::SINT_TO_FP: 3468 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3469 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3470 Results.push_back(Tmp1); 3471 break; 3472 case ISD::AND: 3473 case ISD::OR: 3474 case ISD::XOR: 3475 assert(OVT.isVector() && "Don't know how to promote scalar logic ops"); 3476 // Bit convert each of the values to the new type. 3477 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3478 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3479 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3480 // Bit convert the result back the original type. 3481 Results.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1)); 3482 break; 3483 } 3484} 3485 3486// SelectionDAG::Legalize - This is the entry point for the file. 3487// 3488void SelectionDAG::Legalize(bool TypesNeedLegalizing, 3489 CodeGenOpt::Level OptLevel) { 3490 /// run - This is the main entry point to this class. 3491 /// 3492 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3493} 3494 3495