LegalizeDAG.cpp revision df7096f01384c4e8a8ac9e42c2b784e54c53da8e
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/Analysis/DebugInfo.h" 20#include "llvm/CodeGen/PseudoSourceValue.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetOptions.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Function.h" 30#include "llvm/GlobalVariable.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/ADT/DenseMap.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/SmallPtrSet.h" 40using namespace llvm; 41 42//===----------------------------------------------------------------------===// 43/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 44/// hacks on it until the target machine can handle it. This involves 45/// eliminating value sizes the machine cannot handle (promoting small sizes to 46/// large sizes or splitting up large values into small values) as well as 47/// eliminating operations the machine cannot handle. 48/// 49/// This code also does a small amount of optimization and recognition of idioms 50/// as part of its processing. For example, if a target does not support a 51/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 52/// will attempt merge setcc and brc instructions into brcc's. 53/// 54namespace { 55class SelectionDAGLegalize { 56 const TargetMachine &TM; 57 const TargetLowering &TLI; 58 SelectionDAG &DAG; 59 CodeGenOpt::Level OptLevel; 60 61 // Libcall insertion helpers. 62 63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 64 /// legalized. We use this to ensure that calls are properly serialized 65 /// against each other, including inserted libcalls. 66 SDValue LastCALLSEQ_END; 67 68 /// IsLegalizingCall - This member is used *only* for purposes of providing 69 /// helpful assertions that a libcall isn't created while another call is 70 /// being legalized (which could lead to non-serialized call sequences). 71 bool IsLegalizingCall; 72 73 enum LegalizeAction { 74 Legal, // The target natively supports this operation. 75 Promote, // This operation should be executed in a larger type. 76 Expand // Try to expand this to other ops, otherwise use a libcall. 77 }; 78 79 /// ValueTypeActions - This is a bitvector that contains two bits for each 80 /// value type, where the two bits correspond to the LegalizeAction enum. 81 /// This can be queried with "getTypeAction(VT)". 82 TargetLowering::ValueTypeActionImpl ValueTypeActions; 83 84 /// LegalizedNodes - For nodes that are of legal width, and that have more 85 /// than one use, this map indicates what regularized operand to use. This 86 /// allows us to avoid legalizing the same thing more than once. 87 DenseMap<SDValue, SDValue> LegalizedNodes; 88 89 void AddLegalizedOperand(SDValue From, SDValue To) { 90 LegalizedNodes.insert(std::make_pair(From, To)); 91 // If someone requests legalization of the new node, return itself. 92 if (From != To) 93 LegalizedNodes.insert(std::make_pair(To, To)); 94 } 95 96public: 97 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 98 99 /// getTypeAction - Return how we should legalize values of this type, either 100 /// it is already legal or we need to expand it into multiple registers of 101 /// smaller integer type, or we need to promote it to a larger type. 102 LegalizeAction getTypeAction(EVT VT) const { 103 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 104 } 105 106 /// isTypeLegal - Return true if this type is legal on this target. 107 /// 108 bool isTypeLegal(EVT VT) const { 109 return getTypeAction(VT) == Legal; 110 } 111 112 void LegalizeDAG(); 113 114private: 115 /// LegalizeOp - We know that the specified value has a legal type. 116 /// Recursively ensure that the operands have legal types, then return the 117 /// result. 118 SDValue LegalizeOp(SDValue O); 119 120 SDValue OptimizeFloatStore(StoreSDNode *ST); 121 122 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 123 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 124 /// is necessary to spill the vector being inserted into to memory, perform 125 /// the insert there, and then read the result back. 126 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 127 SDValue Idx, DebugLoc dl); 128 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 129 SDValue Idx, DebugLoc dl); 130 131 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 132 /// performs the same shuffe in terms of order or result bytes, but on a type 133 /// whose vector element type is narrower than the original shuffle type. 134 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 135 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 136 SDValue N1, SDValue N2, 137 SmallVectorImpl<int> &Mask) const; 138 139 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 140 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 141 142 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 143 DebugLoc dl); 144 145 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 146 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC, 147 SDNode *Node, bool isSigned); 148 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 149 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 150 RTLIB::Libcall Call_PPCF128); 151 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 152 RTLIB::Libcall Call_I8, 153 RTLIB::Libcall Call_I16, 154 RTLIB::Libcall Call_I32, 155 RTLIB::Libcall Call_I64, 156 RTLIB::Libcall Call_I128); 157 158 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 159 SDValue ExpandBUILD_VECTOR(SDNode *Node); 160 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 161 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 162 SmallVectorImpl<SDValue> &Results); 163 SDValue ExpandFCOPYSIGN(SDNode *Node); 164 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 165 DebugLoc dl); 166 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 167 DebugLoc dl); 168 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 169 DebugLoc dl); 170 171 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 172 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 173 174 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 175 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 176 177 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node); 178 179 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 180 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 181}; 182} 183 184/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 185/// performs the same shuffe in terms of order or result bytes, but on a type 186/// whose vector element type is narrower than the original shuffle type. 187/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 188SDValue 189SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 190 SDValue N1, SDValue N2, 191 SmallVectorImpl<int> &Mask) const { 192 unsigned NumMaskElts = VT.getVectorNumElements(); 193 unsigned NumDestElts = NVT.getVectorNumElements(); 194 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 195 196 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 197 198 if (NumEltsGrowth == 1) 199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 200 201 SmallVector<int, 8> NewMask; 202 for (unsigned i = 0; i != NumMaskElts; ++i) { 203 int Idx = Mask[i]; 204 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 205 if (Idx < 0) 206 NewMask.push_back(-1); 207 else 208 NewMask.push_back(Idx * NumEltsGrowth + j); 209 } 210 } 211 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 212 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 213 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 214} 215 216SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 217 CodeGenOpt::Level ol) 218 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 219 DAG(dag), OptLevel(ol), 220 ValueTypeActions(TLI.getValueTypeActions()) { 221 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 222 "Too many value types for ValueTypeActions to hold!"); 223} 224 225void SelectionDAGLegalize::LegalizeDAG() { 226 LastCALLSEQ_END = DAG.getEntryNode(); 227 IsLegalizingCall = false; 228 229 // The legalize process is inherently a bottom-up recursive process (users 230 // legalize their uses before themselves). Given infinite stack space, we 231 // could just start legalizing on the root and traverse the whole graph. In 232 // practice however, this causes us to run out of stack space on large basic 233 // blocks. To avoid this problem, compute an ordering of the nodes where each 234 // node is only legalized after all of its operands are legalized. 235 DAG.AssignTopologicalOrder(); 236 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 237 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 238 LegalizeOp(SDValue(I, 0)); 239 240 // Finally, it's possible the root changed. Get the new root. 241 SDValue OldRoot = DAG.getRoot(); 242 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 243 DAG.setRoot(LegalizedNodes[OldRoot]); 244 245 LegalizedNodes.clear(); 246 247 // Remove dead nodes now. 248 DAG.RemoveDeadNodes(); 249} 250 251 252/// FindCallEndFromCallStart - Given a chained node that is part of a call 253/// sequence, find the CALLSEQ_END node that terminates the call sequence. 254static SDNode *FindCallEndFromCallStart(SDNode *Node) { 255 if (Node->getOpcode() == ISD::CALLSEQ_END) 256 return Node; 257 if (Node->use_empty()) 258 return 0; // No CallSeqEnd 259 260 // The chain is usually at the end. 261 SDValue TheChain(Node, Node->getNumValues()-1); 262 if (TheChain.getValueType() != MVT::Other) { 263 // Sometimes it's at the beginning. 264 TheChain = SDValue(Node, 0); 265 if (TheChain.getValueType() != MVT::Other) { 266 // Otherwise, hunt for it. 267 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 268 if (Node->getValueType(i) == MVT::Other) { 269 TheChain = SDValue(Node, i); 270 break; 271 } 272 273 // Otherwise, we walked into a node without a chain. 274 if (TheChain.getValueType() != MVT::Other) 275 return 0; 276 } 277 } 278 279 for (SDNode::use_iterator UI = Node->use_begin(), 280 E = Node->use_end(); UI != E; ++UI) { 281 282 // Make sure to only follow users of our token chain. 283 SDNode *User = *UI; 284 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 285 if (User->getOperand(i) == TheChain) 286 if (SDNode *Result = FindCallEndFromCallStart(User)) 287 return Result; 288 } 289 return 0; 290} 291 292/// FindCallStartFromCallEnd - Given a chained node that is part of a call 293/// sequence, find the CALLSEQ_START node that initiates the call sequence. 294static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 295 assert(Node && "Didn't find callseq_start for a call??"); 296 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 297 298 assert(Node->getOperand(0).getValueType() == MVT::Other && 299 "Node doesn't have a token chain argument!"); 300 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 301} 302 303/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 304/// see if any uses can reach Dest. If no dest operands can get to dest, 305/// legalize them, legalize ourself, and return false, otherwise, return true. 306/// 307/// Keep track of the nodes we fine that actually do lead to Dest in 308/// NodesLeadingTo. This avoids retraversing them exponential number of times. 309/// 310bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 311 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 312 if (N == Dest) return true; // N certainly leads to Dest :) 313 314 // If we've already processed this node and it does lead to Dest, there is no 315 // need to reprocess it. 316 if (NodesLeadingTo.count(N)) return true; 317 318 // If the first result of this node has been already legalized, then it cannot 319 // reach N. 320 if (LegalizedNodes.count(SDValue(N, 0))) return false; 321 322 // Okay, this node has not already been legalized. Check and legalize all 323 // operands. If none lead to Dest, then we can legalize this node. 324 bool OperandsLeadToDest = false; 325 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 326 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 327 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, 328 NodesLeadingTo); 329 330 if (OperandsLeadToDest) { 331 NodesLeadingTo.insert(N); 332 return true; 333 } 334 335 // Okay, this node looks safe, legalize it and return false. 336 LegalizeOp(SDValue(N, 0)); 337 return false; 338} 339 340/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 341/// a load from the constant pool. 342static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 343 SelectionDAG &DAG, const TargetLowering &TLI) { 344 bool Extend = false; 345 DebugLoc dl = CFP->getDebugLoc(); 346 347 // If a FP immediate is precise when represented as a float and if the 348 // target can do an extending load from float to double, we put it into 349 // the constant pool as a float, even if it's is statically typed as a 350 // double. This shrinks FP constants and canonicalizes them for targets where 351 // an FP extending load is the same cost as a normal load (such as on the x87 352 // fp stack or PPC FP unit). 353 EVT VT = CFP->getValueType(0); 354 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 355 if (!UseCP) { 356 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 357 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 358 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 359 } 360 361 EVT OrigVT = VT; 362 EVT SVT = VT; 363 while (SVT != MVT::f32) { 364 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 365 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) && 366 // Only do this if the target has a native EXTLOAD instruction from 367 // smaller type. 368 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 369 TLI.ShouldShrinkFPConstant(OrigVT)) { 370 const Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 371 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 372 VT = SVT; 373 Extend = true; 374 } 375 } 376 377 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 378 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 379 if (Extend) 380 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, dl, 381 DAG.getEntryNode(), 382 CPIdx, MachinePointerInfo::getConstantPool(), 383 VT, false, false, Alignment); 384 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 385 MachinePointerInfo::getConstantPool(), false, false, 386 Alignment); 387} 388 389/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 390static 391SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 392 const TargetLowering &TLI) { 393 SDValue Chain = ST->getChain(); 394 SDValue Ptr = ST->getBasePtr(); 395 SDValue Val = ST->getValue(); 396 EVT VT = Val.getValueType(); 397 int Alignment = ST->getAlignment(); 398 int SVOffset = ST->getSrcValueOffset(); 399 DebugLoc dl = ST->getDebugLoc(); 400 if (ST->getMemoryVT().isFloatingPoint() || 401 ST->getMemoryVT().isVector()) { 402 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 403 if (TLI.isTypeLegal(intVT)) { 404 // Expand to a bitconvert of the value to the integer type of the 405 // same size, then a (misaligned) int store. 406 // FIXME: Does not handle truncating floating point stores! 407 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 408 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 409 SVOffset, ST->isVolatile(), ST->isNonTemporal(), 410 Alignment); 411 } else { 412 // Do a (aligned) store to a stack slot, then copy from the stack slot 413 // to the final destination using (unaligned) integer loads and stores. 414 EVT StoredVT = ST->getMemoryVT(); 415 EVT RegVT = 416 TLI.getRegisterType(*DAG.getContext(), 417 EVT::getIntegerVT(*DAG.getContext(), 418 StoredVT.getSizeInBits())); 419 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 420 unsigned RegBytes = RegVT.getSizeInBits() / 8; 421 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 422 423 // Make sure the stack slot is also aligned for the register type. 424 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 425 426 // Perform the original store, only redirected to the stack slot. 427 SDValue Store = DAG.getTruncStore(Chain, dl, 428 Val, StackPtr, MachinePointerInfo(), 429 StoredVT, false, false, 0); 430 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 431 SmallVector<SDValue, 8> Stores; 432 unsigned Offset = 0; 433 434 // Do all but one copies using the full register width. 435 for (unsigned i = 1; i < NumRegs; i++) { 436 // Load one integer register's worth from the stack slot. 437 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, 438 MachinePointerInfo(), 439 false, false, 0); 440 // Store it to the final location. Remember the store. 441 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 442 ST->getPointerInfo().getWithOffset(Offset), 443 ST->isVolatile(), ST->isNonTemporal(), 444 MinAlign(ST->getAlignment(), Offset))); 445 // Increment the pointers. 446 Offset += RegBytes; 447 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 448 Increment); 449 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 450 } 451 452 // The last store may be partial. Do a truncating store. On big-endian 453 // machines this requires an extending load from the stack slot to ensure 454 // that the bits are in the right place. 455 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 456 8 * (StoredBytes - Offset)); 457 458 // Load from the stack slot. 459 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Store, StackPtr, 460 NULL, 0, MemVT, false, false, 0); 461 462 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 463 ST->getSrcValue(), SVOffset + Offset, 464 MemVT, ST->isVolatile(), 465 ST->isNonTemporal(), 466 MinAlign(ST->getAlignment(), Offset))); 467 // The order of the stores doesn't matter - say it with a TokenFactor. 468 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 469 Stores.size()); 470 } 471 } 472 assert(ST->getMemoryVT().isInteger() && 473 !ST->getMemoryVT().isVector() && 474 "Unaligned store of unknown type."); 475 // Get the half-size VT 476 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 477 int NumBits = NewStoredVT.getSizeInBits(); 478 int IncrementSize = NumBits / 8; 479 480 // Divide the stored value in two parts. 481 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 482 SDValue Lo = Val; 483 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 484 485 // Store the two parts 486 SDValue Store1, Store2; 487 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 488 ST->getSrcValue(), SVOffset, NewStoredVT, 489 ST->isVolatile(), ST->isNonTemporal(), Alignment); 490 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 491 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 492 Alignment = MinAlign(Alignment, IncrementSize); 493 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 494 ST->getSrcValue(), SVOffset + IncrementSize, 495 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 496 Alignment); 497 498 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 499} 500 501/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 502static 503SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 504 const TargetLowering &TLI) { 505 SDValue Chain = LD->getChain(); 506 SDValue Ptr = LD->getBasePtr(); 507 EVT VT = LD->getValueType(0); 508 EVT LoadedVT = LD->getMemoryVT(); 509 DebugLoc dl = LD->getDebugLoc(); 510 if (VT.isFloatingPoint() || VT.isVector()) { 511 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 512 if (TLI.isTypeLegal(intVT)) { 513 // Expand to a (misaligned) integer load of the same size, 514 // then bitconvert to floating point or vector. 515 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(), 516 LD->isVolatile(), 517 LD->isNonTemporal(), LD->getAlignment()); 518 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 519 if (VT.isFloatingPoint() && LoadedVT != VT) 520 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 521 522 SDValue Ops[] = { Result, Chain }; 523 return DAG.getMergeValues(Ops, 2, dl); 524 } 525 526 // Copy the value to a (aligned) stack slot using (unaligned) integer 527 // loads and stores, then do a (aligned) load from the stack slot. 528 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 529 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 530 unsigned RegBytes = RegVT.getSizeInBits() / 8; 531 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 532 533 // Make sure the stack slot is also aligned for the register type. 534 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 535 536 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 537 SmallVector<SDValue, 8> Stores; 538 SDValue StackPtr = StackBase; 539 unsigned Offset = 0; 540 541 // Do all but one copies using the full register width. 542 for (unsigned i = 1; i < NumRegs; i++) { 543 // Load one integer register's worth from the original location. 544 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, 545 LD->getPointerInfo().getWithOffset(Offset), 546 LD->isVolatile(), LD->isNonTemporal(), 547 MinAlign(LD->getAlignment(), Offset)); 548 // Follow the load with a store to the stack slot. Remember the store. 549 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 550 NULL, 0, false, false, 0)); 551 // Increment the pointers. 552 Offset += RegBytes; 553 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 554 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 555 Increment); 556 } 557 558 // The last copy may be partial. Do an extending load. 559 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 560 8 * (LoadedBytes - Offset)); 561 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Chain, Ptr, 562 LD->getPointerInfo().getWithOffset(Offset), 563 MemVT, LD->isVolatile(), 564 LD->isNonTemporal(), 565 MinAlign(LD->getAlignment(), Offset)); 566 // Follow the load with a store to the stack slot. Remember the store. 567 // On big-endian machines this requires a truncating store to ensure 568 // that the bits end up in the right place. 569 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 570 MachinePointerInfo(), MemVT, 571 false, false, 0)); 572 573 // The order of the stores doesn't matter - say it with a TokenFactor. 574 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 575 Stores.size()); 576 577 // Finally, perform the original load only redirected to the stack slot. 578 Load = DAG.getExtLoad(LD->getExtensionType(), VT, dl, TF, StackBase, 579 MachinePointerInfo(), LoadedVT, false, false, 0); 580 581 // Callers expect a MERGE_VALUES node. 582 SDValue Ops[] = { Load, TF }; 583 return DAG.getMergeValues(Ops, 2, dl); 584 } 585 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 586 "Unaligned load of unsupported type."); 587 588 // Compute the new VT that is half the size of the old one. This is an 589 // integer MVT. 590 unsigned NumBits = LoadedVT.getSizeInBits(); 591 EVT NewLoadedVT; 592 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 593 NumBits >>= 1; 594 595 unsigned Alignment = LD->getAlignment(); 596 unsigned IncrementSize = NumBits / 8; 597 ISD::LoadExtType HiExtType = LD->getExtensionType(); 598 599 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 600 if (HiExtType == ISD::NON_EXTLOAD) 601 HiExtType = ISD::ZEXTLOAD; 602 603 // Load the value in two parts 604 SDValue Lo, Hi; 605 if (TLI.isLittleEndian()) { 606 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getPointerInfo(), 607 NewLoadedVT, LD->isVolatile(), 608 LD->isNonTemporal(), Alignment); 609 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 610 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 611 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, 612 LD->getPointerInfo().getWithOffset(IncrementSize), 613 NewLoadedVT, LD->isVolatile(), 614 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 615 } else { 616 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getPointerInfo(), 617 NewLoadedVT, LD->isVolatile(), 618 LD->isNonTemporal(), Alignment); 619 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 620 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 621 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, 622 LD->getPointerInfo().getWithOffset(IncrementSize), 623 NewLoadedVT, LD->isVolatile(), 624 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 625 } 626 627 // aggregate the two parts 628 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 629 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 630 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 631 632 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 633 Hi.getValue(1)); 634 635 SDValue Ops[] = { Result, TF }; 636 return DAG.getMergeValues(Ops, 2, dl); 637} 638 639/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 640/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 641/// is necessary to spill the vector being inserted into to memory, perform 642/// the insert there, and then read the result back. 643SDValue SelectionDAGLegalize:: 644PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 645 DebugLoc dl) { 646 SDValue Tmp1 = Vec; 647 SDValue Tmp2 = Val; 648 SDValue Tmp3 = Idx; 649 650 // If the target doesn't support this, we have to spill the input vector 651 // to a temporary stack slot, update the element, then reload it. This is 652 // badness. We could also load the value into a vector register (either 653 // with a "move to register" or "extload into register" instruction, then 654 // permute it into place, if the idx is a constant and if the idx is 655 // supported by the target. 656 EVT VT = Tmp1.getValueType(); 657 EVT EltVT = VT.getVectorElementType(); 658 EVT IdxVT = Tmp3.getValueType(); 659 EVT PtrVT = TLI.getPointerTy(); 660 SDValue StackPtr = DAG.CreateStackTemporary(VT); 661 662 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 663 664 // Store the vector. 665 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 666 MachinePointerInfo::getFixedStack(SPFI), 667 false, false, 0); 668 669 // Truncate or zero extend offset to target pointer type. 670 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 671 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 672 // Add the offset to the index. 673 unsigned EltSize = EltVT.getSizeInBits()/8; 674 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 675 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 676 // Store the scalar value. 677 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT, 678 false, false, 0); 679 // Load the updated vector. 680 return DAG.getLoad(VT, dl, Ch, StackPtr, 681 MachinePointerInfo::getFixedStack(SPFI), false, false, 0); 682} 683 684 685SDValue SelectionDAGLegalize:: 686ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 687 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 688 // SCALAR_TO_VECTOR requires that the type of the value being inserted 689 // match the element type of the vector being created, except for 690 // integers in which case the inserted value can be over width. 691 EVT EltVT = Vec.getValueType().getVectorElementType(); 692 if (Val.getValueType() == EltVT || 693 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 694 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 695 Vec.getValueType(), Val); 696 697 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 698 // We generate a shuffle of InVec and ScVec, so the shuffle mask 699 // should be 0,1,2,3,4,5... with the appropriate element replaced with 700 // elt 0 of the RHS. 701 SmallVector<int, 8> ShufOps; 702 for (unsigned i = 0; i != NumElts; ++i) 703 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 704 705 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 706 &ShufOps[0]); 707 } 708 } 709 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 710} 711 712SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 713 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 714 // FIXME: We shouldn't do this for TargetConstantFP's. 715 // FIXME: move this to the DAG Combiner! Note that we can't regress due 716 // to phase ordering between legalized code and the dag combiner. This 717 // probably means that we need to integrate dag combiner and legalizer 718 // together. 719 // We generally can't do this one for long doubles. 720 SDValue Tmp1 = ST->getChain(); 721 SDValue Tmp2 = ST->getBasePtr(); 722 SDValue Tmp3; 723 int SVOffset = ST->getSrcValueOffset(); 724 unsigned Alignment = ST->getAlignment(); 725 bool isVolatile = ST->isVolatile(); 726 bool isNonTemporal = ST->isNonTemporal(); 727 DebugLoc dl = ST->getDebugLoc(); 728 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 729 if (CFP->getValueType(0) == MVT::f32 && 730 getTypeAction(MVT::i32) == Legal) { 731 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 732 bitcastToAPInt().zextOrTrunc(32), 733 MVT::i32); 734 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 735 SVOffset, isVolatile, isNonTemporal, Alignment); 736 } else if (CFP->getValueType(0) == MVT::f64) { 737 // If this target supports 64-bit registers, do a single 64-bit store. 738 if (getTypeAction(MVT::i64) == Legal) { 739 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 740 zextOrTrunc(64), MVT::i64); 741 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 742 SVOffset, isVolatile, isNonTemporal, Alignment); 743 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 744 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 745 // stores. If the target supports neither 32- nor 64-bits, this 746 // xform is certainly not worth it. 747 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 748 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 749 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 750 if (TLI.isBigEndian()) std::swap(Lo, Hi); 751 752 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 753 SVOffset, isVolatile, isNonTemporal, Alignment); 754 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 755 DAG.getIntPtrConstant(4)); 756 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 757 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 758 759 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 760 } 761 } 762 } 763 return SDValue(); 764} 765 766/// LegalizeOp - We know that the specified value has a legal type, and 767/// that its operands are legal. Now ensure that the operation itself 768/// is legal, recursively ensuring that the operands' operations remain 769/// legal. 770SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 771 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 772 return Op; 773 774 SDNode *Node = Op.getNode(); 775 DebugLoc dl = Node->getDebugLoc(); 776 777 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 778 assert(getTypeAction(Node->getValueType(i)) == Legal && 779 "Unexpected illegal type!"); 780 781 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 782 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 783 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 784 "Unexpected illegal type!"); 785 786 // Note that LegalizeOp may be reentered even from single-use nodes, which 787 // means that we always must cache transformed nodes. 788 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 789 if (I != LegalizedNodes.end()) return I->second; 790 791 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 792 SDValue Result = Op; 793 bool isCustom = false; 794 795 // Figure out the correct action; the way to query this varies by opcode 796 TargetLowering::LegalizeAction Action; 797 bool SimpleFinishLegalizing = true; 798 switch (Node->getOpcode()) { 799 case ISD::INTRINSIC_W_CHAIN: 800 case ISD::INTRINSIC_WO_CHAIN: 801 case ISD::INTRINSIC_VOID: 802 case ISD::VAARG: 803 case ISD::STACKSAVE: 804 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 805 break; 806 case ISD::SINT_TO_FP: 807 case ISD::UINT_TO_FP: 808 case ISD::EXTRACT_VECTOR_ELT: 809 Action = TLI.getOperationAction(Node->getOpcode(), 810 Node->getOperand(0).getValueType()); 811 break; 812 case ISD::FP_ROUND_INREG: 813 case ISD::SIGN_EXTEND_INREG: { 814 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 815 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 816 break; 817 } 818 case ISD::SELECT_CC: 819 case ISD::SETCC: 820 case ISD::BR_CC: { 821 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 822 Node->getOpcode() == ISD::SETCC ? 2 : 1; 823 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 824 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 825 ISD::CondCode CCCode = 826 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 827 Action = TLI.getCondCodeAction(CCCode, OpVT); 828 if (Action == TargetLowering::Legal) { 829 if (Node->getOpcode() == ISD::SELECT_CC) 830 Action = TLI.getOperationAction(Node->getOpcode(), 831 Node->getValueType(0)); 832 else 833 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 834 } 835 break; 836 } 837 case ISD::LOAD: 838 case ISD::STORE: 839 // FIXME: Model these properly. LOAD and STORE are complicated, and 840 // STORE expects the unlegalized operand in some cases. 841 SimpleFinishLegalizing = false; 842 break; 843 case ISD::CALLSEQ_START: 844 case ISD::CALLSEQ_END: 845 // FIXME: This shouldn't be necessary. These nodes have special properties 846 // dealing with the recursive nature of legalization. Removing this 847 // special case should be done as part of making LegalizeDAG non-recursive. 848 SimpleFinishLegalizing = false; 849 break; 850 case ISD::EXTRACT_ELEMENT: 851 case ISD::FLT_ROUNDS_: 852 case ISD::SADDO: 853 case ISD::SSUBO: 854 case ISD::UADDO: 855 case ISD::USUBO: 856 case ISD::SMULO: 857 case ISD::UMULO: 858 case ISD::FPOWI: 859 case ISD::MERGE_VALUES: 860 case ISD::EH_RETURN: 861 case ISD::FRAME_TO_ARGS_OFFSET: 862 case ISD::EH_SJLJ_SETJMP: 863 case ISD::EH_SJLJ_LONGJMP: 864 // These operations lie about being legal: when they claim to be legal, 865 // they should actually be expanded. 866 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 867 if (Action == TargetLowering::Legal) 868 Action = TargetLowering::Expand; 869 break; 870 case ISD::TRAMPOLINE: 871 case ISD::FRAMEADDR: 872 case ISD::RETURNADDR: 873 // These operations lie about being legal: when they claim to be legal, 874 // they should actually be custom-lowered. 875 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 876 if (Action == TargetLowering::Legal) 877 Action = TargetLowering::Custom; 878 break; 879 case ISD::BUILD_VECTOR: 880 // A weird case: legalization for BUILD_VECTOR never legalizes the 881 // operands! 882 // FIXME: This really sucks... changing it isn't semantically incorrect, 883 // but it massively pessimizes the code for floating-point BUILD_VECTORs 884 // because ConstantFP operands get legalized into constant pool loads 885 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 886 // though, because BUILD_VECTORS usually get lowered into other nodes 887 // which get legalized properly. 888 SimpleFinishLegalizing = false; 889 break; 890 default: 891 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 892 Action = TargetLowering::Legal; 893 } else { 894 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 895 } 896 break; 897 } 898 899 if (SimpleFinishLegalizing) { 900 SmallVector<SDValue, 8> Ops, ResultVals; 901 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 902 Ops.push_back(LegalizeOp(Node->getOperand(i))); 903 switch (Node->getOpcode()) { 904 default: break; 905 case ISD::BR: 906 case ISD::BRIND: 907 case ISD::BR_JT: 908 case ISD::BR_CC: 909 case ISD::BRCOND: 910 // Branches tweak the chain to include LastCALLSEQ_END 911 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 912 LastCALLSEQ_END); 913 Ops[0] = LegalizeOp(Ops[0]); 914 LastCALLSEQ_END = DAG.getEntryNode(); 915 break; 916 case ISD::SHL: 917 case ISD::SRL: 918 case ISD::SRA: 919 case ISD::ROTL: 920 case ISD::ROTR: 921 // Legalizing shifts/rotates requires adjusting the shift amount 922 // to the appropriate width. 923 if (!Ops[1].getValueType().isVector()) 924 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 925 break; 926 case ISD::SRL_PARTS: 927 case ISD::SRA_PARTS: 928 case ISD::SHL_PARTS: 929 // Legalizing shifts/rotates requires adjusting the shift amount 930 // to the appropriate width. 931 if (!Ops[2].getValueType().isVector()) 932 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2])); 933 break; 934 } 935 936 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(), 937 Ops.size()), 0); 938 switch (Action) { 939 case TargetLowering::Legal: 940 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 941 ResultVals.push_back(Result.getValue(i)); 942 break; 943 case TargetLowering::Custom: 944 // FIXME: The handling for custom lowering with multiple results is 945 // a complete mess. 946 Tmp1 = TLI.LowerOperation(Result, DAG); 947 if (Tmp1.getNode()) { 948 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 949 if (e == 1) 950 ResultVals.push_back(Tmp1); 951 else 952 ResultVals.push_back(Tmp1.getValue(i)); 953 } 954 break; 955 } 956 957 // FALL THROUGH 958 case TargetLowering::Expand: 959 ExpandNode(Result.getNode(), ResultVals); 960 break; 961 case TargetLowering::Promote: 962 PromoteNode(Result.getNode(), ResultVals); 963 break; 964 } 965 if (!ResultVals.empty()) { 966 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 967 if (ResultVals[i] != SDValue(Node, i)) 968 ResultVals[i] = LegalizeOp(ResultVals[i]); 969 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 970 } 971 return ResultVals[Op.getResNo()]; 972 } 973 } 974 975 switch (Node->getOpcode()) { 976 default: 977#ifndef NDEBUG 978 dbgs() << "NODE: "; 979 Node->dump( &DAG); 980 dbgs() << "\n"; 981#endif 982 assert(0 && "Do not know how to legalize this operator!"); 983 984 case ISD::BUILD_VECTOR: 985 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 986 default: assert(0 && "This action is not supported yet!"); 987 case TargetLowering::Custom: 988 Tmp3 = TLI.LowerOperation(Result, DAG); 989 if (Tmp3.getNode()) { 990 Result = Tmp3; 991 break; 992 } 993 // FALLTHROUGH 994 case TargetLowering::Expand: 995 Result = ExpandBUILD_VECTOR(Result.getNode()); 996 break; 997 } 998 break; 999 case ISD::CALLSEQ_START: { 1000 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1001 1002 // Recursively Legalize all of the inputs of the call end that do not lead 1003 // to this call start. This ensures that any libcalls that need be inserted 1004 // are inserted *before* the CALLSEQ_START. 1005 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1006 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1007 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1008 NodesLeadingTo); 1009 } 1010 1011 // Now that we have legalized all of the inputs (which may have inserted 1012 // libcalls), create the new CALLSEQ_START node. 1013 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1014 1015 // Merge in the last call to ensure that this call starts after the last 1016 // call ended. 1017 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1018 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1019 Tmp1, LastCALLSEQ_END); 1020 Tmp1 = LegalizeOp(Tmp1); 1021 } 1022 1023 // Do not try to legalize the target-specific arguments (#1+). 1024 if (Tmp1 != Node->getOperand(0)) { 1025 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1026 Ops[0] = Tmp1; 1027 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0], 1028 Ops.size()), Result.getResNo()); 1029 } 1030 1031 // Remember that the CALLSEQ_START is legalized. 1032 AddLegalizedOperand(Op.getValue(0), Result); 1033 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1034 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1035 1036 // Now that the callseq_start and all of the non-call nodes above this call 1037 // sequence have been legalized, legalize the call itself. During this 1038 // process, no libcalls can/will be inserted, guaranteeing that no calls 1039 // can overlap. 1040 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1041 // Note that we are selecting this call! 1042 LastCALLSEQ_END = SDValue(CallEnd, 0); 1043 IsLegalizingCall = true; 1044 1045 // Legalize the call, starting from the CALLSEQ_END. 1046 LegalizeOp(LastCALLSEQ_END); 1047 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1048 return Result; 1049 } 1050 case ISD::CALLSEQ_END: 1051 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1052 // will cause this node to be legalized as well as handling libcalls right. 1053 if (LastCALLSEQ_END.getNode() != Node) { 1054 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1055 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1056 assert(I != LegalizedNodes.end() && 1057 "Legalizing the call start should have legalized this node!"); 1058 return I->second; 1059 } 1060 1061 // Otherwise, the call start has been legalized and everything is going 1062 // according to plan. Just legalize ourselves normally here. 1063 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1064 // Do not try to legalize the target-specific arguments (#1+), except for 1065 // an optional flag input. 1066 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1067 if (Tmp1 != Node->getOperand(0)) { 1068 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1069 Ops[0] = Tmp1; 1070 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1071 &Ops[0], Ops.size()), 1072 Result.getResNo()); 1073 } 1074 } else { 1075 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1076 if (Tmp1 != Node->getOperand(0) || 1077 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1078 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1079 Ops[0] = Tmp1; 1080 Ops.back() = Tmp2; 1081 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1082 &Ops[0], Ops.size()), 1083 Result.getResNo()); 1084 } 1085 } 1086 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1087 // This finishes up call legalization. 1088 IsLegalizingCall = false; 1089 1090 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1091 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1092 if (Node->getNumValues() == 2) 1093 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1094 return Result.getValue(Op.getResNo()); 1095 case ISD::LOAD: { 1096 LoadSDNode *LD = cast<LoadSDNode>(Node); 1097 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1098 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1099 1100 ISD::LoadExtType ExtType = LD->getExtensionType(); 1101 if (ExtType == ISD::NON_EXTLOAD) { 1102 EVT VT = Node->getValueType(0); 1103 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1104 Tmp1, Tmp2, LD->getOffset()), 1105 Result.getResNo()); 1106 Tmp3 = Result.getValue(0); 1107 Tmp4 = Result.getValue(1); 1108 1109 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1110 default: assert(0 && "This action is not supported yet!"); 1111 case TargetLowering::Legal: 1112 // If this is an unaligned load and the target doesn't support it, 1113 // expand it. 1114 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1115 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1116 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1117 if (LD->getAlignment() < ABIAlignment){ 1118 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1119 DAG, TLI); 1120 Tmp3 = Result.getOperand(0); 1121 Tmp4 = Result.getOperand(1); 1122 Tmp3 = LegalizeOp(Tmp3); 1123 Tmp4 = LegalizeOp(Tmp4); 1124 } 1125 } 1126 break; 1127 case TargetLowering::Custom: 1128 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1129 if (Tmp1.getNode()) { 1130 Tmp3 = LegalizeOp(Tmp1); 1131 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1132 } 1133 break; 1134 case TargetLowering::Promote: { 1135 // Only promote a load of vector type to another. 1136 assert(VT.isVector() && "Cannot promote this load!"); 1137 // Change base type to a different vector type. 1138 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1139 1140 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(), 1141 LD->isVolatile(), LD->isNonTemporal(), 1142 LD->getAlignment()); 1143 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1144 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1145 break; 1146 } 1147 } 1148 // Since loads produce two values, make sure to remember that we 1149 // legalized both of them. 1150 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1151 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1152 return Op.getResNo() ? Tmp4 : Tmp3; 1153 } else { 1154 EVT SrcVT = LD->getMemoryVT(); 1155 unsigned SrcWidth = SrcVT.getSizeInBits(); 1156 int SVOffset = LD->getSrcValueOffset(); 1157 unsigned Alignment = LD->getAlignment(); 1158 bool isVolatile = LD->isVolatile(); 1159 bool isNonTemporal = LD->isNonTemporal(); 1160 1161 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1162 // Some targets pretend to have an i1 loading operation, and actually 1163 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1164 // bits are guaranteed to be zero; it helps the optimizers understand 1165 // that these bits are zero. It is also useful for EXTLOAD, since it 1166 // tells the optimizers that those bits are undefined. It would be 1167 // nice to have an effective generic way of getting these benefits... 1168 // Until such a way is found, don't insist on promoting i1 here. 1169 (SrcVT != MVT::i1 || 1170 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1171 // Promote to a byte-sized load if not loading an integral number of 1172 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1173 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1174 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 1175 SDValue Ch; 1176 1177 // The extra bits are guaranteed to be zero, since we stored them that 1178 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1179 1180 ISD::LoadExtType NewExtType = 1181 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1182 1183 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), dl, 1184 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1185 NVT, isVolatile, isNonTemporal, Alignment); 1186 1187 Ch = Result.getValue(1); // The chain. 1188 1189 if (ExtType == ISD::SEXTLOAD) 1190 // Having the top bits zero doesn't help when sign extending. 1191 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1192 Result.getValueType(), 1193 Result, DAG.getValueType(SrcVT)); 1194 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1195 // All the top bits are guaranteed to be zero - inform the optimizers. 1196 Result = DAG.getNode(ISD::AssertZext, dl, 1197 Result.getValueType(), Result, 1198 DAG.getValueType(SrcVT)); 1199 1200 Tmp1 = LegalizeOp(Result); 1201 Tmp2 = LegalizeOp(Ch); 1202 } else if (SrcWidth & (SrcWidth - 1)) { 1203 // If not loading a power-of-2 number of bits, expand as two loads. 1204 assert(!SrcVT.isVector() && "Unsupported extload!"); 1205 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1206 assert(RoundWidth < SrcWidth); 1207 unsigned ExtraWidth = SrcWidth - RoundWidth; 1208 assert(ExtraWidth < RoundWidth); 1209 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1210 "Load size not an integral number of bytes!"); 1211 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1212 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1213 SDValue Lo, Hi, Ch; 1214 unsigned IncrementSize; 1215 1216 if (TLI.isLittleEndian()) { 1217 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1218 // Load the bottom RoundWidth bits. 1219 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), dl, 1220 Tmp1, Tmp2, 1221 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1222 isNonTemporal, Alignment); 1223 1224 // Load the remaining ExtraWidth bits. 1225 IncrementSize = RoundWidth / 8; 1226 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1227 DAG.getIntPtrConstant(IncrementSize)); 1228 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2, 1229 LD->getSrcValue(), SVOffset + IncrementSize, 1230 ExtraVT, isVolatile, isNonTemporal, 1231 MinAlign(Alignment, IncrementSize)); 1232 1233 // Build a factor node to remember that this load is independent of 1234 // the other one. 1235 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1236 Hi.getValue(1)); 1237 1238 // Move the top bits to the right place. 1239 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1240 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1241 1242 // Join the hi and lo parts. 1243 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1244 } else { 1245 // Big endian - avoid unaligned loads. 1246 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1247 // Load the top RoundWidth bits. 1248 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2, 1249 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1250 isNonTemporal, Alignment); 1251 1252 // Load the remaining ExtraWidth bits. 1253 IncrementSize = RoundWidth / 8; 1254 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1255 DAG.getIntPtrConstant(IncrementSize)); 1256 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, 1257 Node->getValueType(0), dl, Tmp1, Tmp2, 1258 LD->getSrcValue(), SVOffset + IncrementSize, 1259 ExtraVT, isVolatile, isNonTemporal, 1260 MinAlign(Alignment, IncrementSize)); 1261 1262 // Build a factor node to remember that this load is independent of 1263 // the other one. 1264 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1265 Hi.getValue(1)); 1266 1267 // Move the top bits to the right place. 1268 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1269 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1270 1271 // Join the hi and lo parts. 1272 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1273 } 1274 1275 Tmp1 = LegalizeOp(Result); 1276 Tmp2 = LegalizeOp(Ch); 1277 } else { 1278 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1279 default: assert(0 && "This action is not supported yet!"); 1280 case TargetLowering::Custom: 1281 isCustom = true; 1282 // FALLTHROUGH 1283 case TargetLowering::Legal: 1284 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1285 Tmp1, Tmp2, LD->getOffset()), 1286 Result.getResNo()); 1287 Tmp1 = Result.getValue(0); 1288 Tmp2 = Result.getValue(1); 1289 1290 if (isCustom) { 1291 Tmp3 = TLI.LowerOperation(Result, DAG); 1292 if (Tmp3.getNode()) { 1293 Tmp1 = LegalizeOp(Tmp3); 1294 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1295 } 1296 } else { 1297 // If this is an unaligned load and the target doesn't support it, 1298 // expand it. 1299 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1300 const Type *Ty = 1301 LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1302 unsigned ABIAlignment = 1303 TLI.getTargetData()->getABITypeAlignment(Ty); 1304 if (LD->getAlignment() < ABIAlignment){ 1305 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1306 DAG, TLI); 1307 Tmp1 = Result.getOperand(0); 1308 Tmp2 = Result.getOperand(1); 1309 Tmp1 = LegalizeOp(Tmp1); 1310 Tmp2 = LegalizeOp(Tmp2); 1311 } 1312 } 1313 } 1314 break; 1315 case TargetLowering::Expand: 1316 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) { 1317 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, 1318 LD->getPointerInfo(), 1319 LD->isVolatile(), LD->isNonTemporal(), 1320 LD->getAlignment()); 1321 unsigned ExtendOp; 1322 switch (ExtType) { 1323 case ISD::EXTLOAD: 1324 ExtendOp = (SrcVT.isFloatingPoint() ? 1325 ISD::FP_EXTEND : ISD::ANY_EXTEND); 1326 break; 1327 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break; 1328 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break; 1329 default: llvm_unreachable("Unexpected extend load type!"); 1330 } 1331 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load); 1332 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1333 Tmp2 = LegalizeOp(Load.getValue(1)); 1334 break; 1335 } 1336 // FIXME: This does not work for vectors on most targets. Sign- and 1337 // zero-extend operations are currently folded into extending loads, 1338 // whether they are legal or not, and then we end up here without any 1339 // support for legalizing them. 1340 assert(ExtType != ISD::EXTLOAD && 1341 "EXTLOAD should always be supported!"); 1342 // Turn the unsupported load into an EXTLOAD followed by an explicit 1343 // zero/sign extend inreg. 1344 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), dl, 1345 Tmp1, Tmp2, LD->getSrcValue(), 1346 LD->getSrcValueOffset(), SrcVT, 1347 LD->isVolatile(), LD->isNonTemporal(), 1348 LD->getAlignment()); 1349 SDValue ValRes; 1350 if (ExtType == ISD::SEXTLOAD) 1351 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1352 Result.getValueType(), 1353 Result, DAG.getValueType(SrcVT)); 1354 else 1355 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1356 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1357 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1358 break; 1359 } 1360 } 1361 1362 // Since loads produce two values, make sure to remember that we legalized 1363 // both of them. 1364 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1365 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1366 return Op.getResNo() ? Tmp2 : Tmp1; 1367 } 1368 } 1369 case ISD::STORE: { 1370 StoreSDNode *ST = cast<StoreSDNode>(Node); 1371 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1372 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1373 int SVOffset = ST->getSrcValueOffset(); 1374 unsigned Alignment = ST->getAlignment(); 1375 bool isVolatile = ST->isVolatile(); 1376 bool isNonTemporal = ST->isNonTemporal(); 1377 1378 if (!ST->isTruncatingStore()) { 1379 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1380 Result = SDValue(OptStore, 0); 1381 break; 1382 } 1383 1384 { 1385 Tmp3 = LegalizeOp(ST->getValue()); 1386 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1387 Tmp1, Tmp3, Tmp2, 1388 ST->getOffset()), 1389 Result.getResNo()); 1390 1391 EVT VT = Tmp3.getValueType(); 1392 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1393 default: assert(0 && "This action is not supported yet!"); 1394 case TargetLowering::Legal: 1395 // If this is an unaligned store and the target doesn't support it, 1396 // expand it. 1397 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1398 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1399 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1400 if (ST->getAlignment() < ABIAlignment) 1401 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1402 DAG, TLI); 1403 } 1404 break; 1405 case TargetLowering::Custom: 1406 Tmp1 = TLI.LowerOperation(Result, DAG); 1407 if (Tmp1.getNode()) Result = Tmp1; 1408 break; 1409 case TargetLowering::Promote: 1410 assert(VT.isVector() && "Unknown legal promote case!"); 1411 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1412 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1413 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1414 ST->getSrcValue(), SVOffset, isVolatile, 1415 isNonTemporal, Alignment); 1416 break; 1417 } 1418 break; 1419 } 1420 } else { 1421 Tmp3 = LegalizeOp(ST->getValue()); 1422 1423 EVT StVT = ST->getMemoryVT(); 1424 unsigned StWidth = StVT.getSizeInBits(); 1425 1426 if (StWidth != StVT.getStoreSizeInBits()) { 1427 // Promote to a byte-sized store with upper bits zero if not 1428 // storing an integral number of bytes. For example, promote 1429 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1430 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), 1431 StVT.getStoreSizeInBits()); 1432 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1433 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1434 SVOffset, NVT, isVolatile, isNonTemporal, 1435 Alignment); 1436 } else if (StWidth & (StWidth - 1)) { 1437 // If not storing a power-of-2 number of bits, expand as two stores. 1438 assert(!StVT.isVector() && "Unsupported truncstore!"); 1439 unsigned RoundWidth = 1 << Log2_32(StWidth); 1440 assert(RoundWidth < StWidth); 1441 unsigned ExtraWidth = StWidth - RoundWidth; 1442 assert(ExtraWidth < RoundWidth); 1443 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1444 "Store size not an integral number of bytes!"); 1445 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1446 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1447 SDValue Lo, Hi; 1448 unsigned IncrementSize; 1449 1450 if (TLI.isLittleEndian()) { 1451 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1452 // Store the bottom RoundWidth bits. 1453 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1454 SVOffset, RoundVT, 1455 isVolatile, isNonTemporal, Alignment); 1456 1457 // Store the remaining ExtraWidth bits. 1458 IncrementSize = RoundWidth / 8; 1459 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1460 DAG.getIntPtrConstant(IncrementSize)); 1461 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1462 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1463 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1464 SVOffset + IncrementSize, ExtraVT, isVolatile, 1465 isNonTemporal, 1466 MinAlign(Alignment, IncrementSize)); 1467 } else { 1468 // Big endian - avoid unaligned stores. 1469 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1470 // Store the top RoundWidth bits. 1471 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1472 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1473 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1474 SVOffset, RoundVT, isVolatile, isNonTemporal, 1475 Alignment); 1476 1477 // Store the remaining ExtraWidth bits. 1478 IncrementSize = RoundWidth / 8; 1479 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1480 DAG.getIntPtrConstant(IncrementSize)); 1481 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1482 SVOffset + IncrementSize, ExtraVT, isVolatile, 1483 isNonTemporal, 1484 MinAlign(Alignment, IncrementSize)); 1485 } 1486 1487 // The order of the stores doesn't matter. 1488 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1489 } else { 1490 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1491 Tmp2 != ST->getBasePtr()) 1492 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1493 Tmp1, Tmp3, Tmp2, 1494 ST->getOffset()), 1495 Result.getResNo()); 1496 1497 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1498 default: assert(0 && "This action is not supported yet!"); 1499 case TargetLowering::Legal: 1500 // If this is an unaligned store and the target doesn't support it, 1501 // expand it. 1502 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1503 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1504 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1505 if (ST->getAlignment() < ABIAlignment) 1506 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1507 DAG, TLI); 1508 } 1509 break; 1510 case TargetLowering::Custom: 1511 Result = TLI.LowerOperation(Result, DAG); 1512 break; 1513 case Expand: 1514 // TRUNCSTORE:i16 i32 -> STORE i16 1515 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1516 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1517 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1518 SVOffset, isVolatile, isNonTemporal, 1519 Alignment); 1520 break; 1521 } 1522 } 1523 } 1524 break; 1525 } 1526 } 1527 assert(Result.getValueType() == Op.getValueType() && 1528 "Bad legalization!"); 1529 1530 // Make sure that the generated code is itself legal. 1531 if (Result != Op) 1532 Result = LegalizeOp(Result); 1533 1534 // Note that LegalizeOp may be reentered even from single-use nodes, which 1535 // means that we always must cache transformed nodes. 1536 AddLegalizedOperand(Op, Result); 1537 return Result; 1538} 1539 1540SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1541 SDValue Vec = Op.getOperand(0); 1542 SDValue Idx = Op.getOperand(1); 1543 DebugLoc dl = Op.getDebugLoc(); 1544 // Store the value to a temporary stack slot, then LOAD the returned part. 1545 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1546 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0, 1547 false, false, 0); 1548 1549 // Add the offset to the index. 1550 unsigned EltSize = 1551 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1552 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1553 DAG.getConstant(EltSize, Idx.getValueType())); 1554 1555 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1556 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1557 else 1558 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1559 1560 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1561 1562 if (Op.getValueType().isVector()) 1563 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(), 1564 false, false, 0); 1565 else 1566 return DAG.getExtLoad(ISD::EXTLOAD, Op.getValueType(), dl, Ch, StackPtr, 1567 MachinePointerInfo(), 1568 Vec.getValueType().getVectorElementType(), 1569 false, false, 0); 1570} 1571 1572SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1573 // We can't handle this case efficiently. Allocate a sufficiently 1574 // aligned object on the stack, store each element into it, then load 1575 // the result as a vector. 1576 // Create the stack frame object. 1577 EVT VT = Node->getValueType(0); 1578 EVT EltVT = VT.getVectorElementType(); 1579 DebugLoc dl = Node->getDebugLoc(); 1580 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1581 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1582 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI); 1583 1584 // Emit a store of each element to the stack slot. 1585 SmallVector<SDValue, 8> Stores; 1586 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1587 // Store (in the right endianness) the elements to memory. 1588 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1589 // Ignore undef elements. 1590 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1591 1592 unsigned Offset = TypeByteSize*i; 1593 1594 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1595 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1596 1597 // If the destination vector element type is narrower than the source 1598 // element type, only store the bits necessary. 1599 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1600 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1601 Node->getOperand(i), Idx, 1602 PtrInfo.getWithOffset(Offset), 1603 EltVT, false, false, 0)); 1604 } else 1605 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1606 Node->getOperand(i), Idx, 1607 PtrInfo.getWithOffset(Offset), 1608 false, false, 0)); 1609 } 1610 1611 SDValue StoreChain; 1612 if (!Stores.empty()) // Not all undef elements? 1613 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1614 &Stores[0], Stores.size()); 1615 else 1616 StoreChain = DAG.getEntryNode(); 1617 1618 // Result is a load from the stack slot. 1619 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0); 1620} 1621 1622SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1623 DebugLoc dl = Node->getDebugLoc(); 1624 SDValue Tmp1 = Node->getOperand(0); 1625 SDValue Tmp2 = Node->getOperand(1); 1626 1627 // Get the sign bit of the RHS. First obtain a value that has the same 1628 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1629 SDValue SignBit; 1630 EVT FloatVT = Tmp2.getValueType(); 1631 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1632 if (isTypeLegal(IVT)) { 1633 // Convert to an integer with the same sign bit. 1634 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1635 } else { 1636 // Store the float to memory, then load the sign part out as an integer. 1637 MVT LoadTy = TLI.getPointerTy(); 1638 // First create a temporary that is aligned for both the load and store. 1639 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1640 // Then store the float to it. 1641 SDValue Ch = 1642 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL, 0, 1643 false, false, 0); 1644 if (TLI.isBigEndian()) { 1645 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1646 // Load out a legal integer with the same sign bit as the float. 1647 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(), 1648 false, false, 0); 1649 } else { // Little endian 1650 SDValue LoadPtr = StackPtr; 1651 // The float may be wider than the integer we are going to load. Advance 1652 // the pointer so that the loaded integer will contain the sign bit. 1653 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1654 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1655 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1656 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1657 // Load a legal integer containing the sign bit. 1658 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(), 1659 false, false, 0); 1660 // Move the sign bit to the top bit of the loaded integer. 1661 unsigned BitShift = LoadTy.getSizeInBits() - 1662 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1663 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1664 if (BitShift) 1665 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1666 DAG.getConstant(BitShift,TLI.getShiftAmountTy())); 1667 } 1668 } 1669 // Now get the sign bit proper, by seeing whether the value is negative. 1670 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1671 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1672 ISD::SETLT); 1673 // Get the absolute value of the result. 1674 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1675 // Select between the nabs and abs value based on the sign bit of 1676 // the input. 1677 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1678 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1679 AbsVal); 1680} 1681 1682void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1683 SmallVectorImpl<SDValue> &Results) { 1684 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1685 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1686 " not tell us which reg is the stack pointer!"); 1687 DebugLoc dl = Node->getDebugLoc(); 1688 EVT VT = Node->getValueType(0); 1689 SDValue Tmp1 = SDValue(Node, 0); 1690 SDValue Tmp2 = SDValue(Node, 1); 1691 SDValue Tmp3 = Node->getOperand(2); 1692 SDValue Chain = Tmp1.getOperand(0); 1693 1694 // Chain the dynamic stack allocation so that it doesn't modify the stack 1695 // pointer when other instructions are using the stack. 1696 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1697 1698 SDValue Size = Tmp2.getOperand(1); 1699 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1700 Chain = SP.getValue(1); 1701 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1702 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); 1703 if (Align > StackAlign) 1704 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1705 DAG.getConstant(-(uint64_t)Align, VT)); 1706 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1707 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1708 1709 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1710 DAG.getIntPtrConstant(0, true), SDValue()); 1711 1712 Results.push_back(Tmp1); 1713 Results.push_back(Tmp2); 1714} 1715 1716/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1717/// condition code CC on the current target. This routine expands SETCC with 1718/// illegal condition code into AND / OR of multiple SETCC values. 1719void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1720 SDValue &LHS, SDValue &RHS, 1721 SDValue &CC, 1722 DebugLoc dl) { 1723 EVT OpVT = LHS.getValueType(); 1724 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1725 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1726 default: assert(0 && "Unknown condition code action!"); 1727 case TargetLowering::Legal: 1728 // Nothing to do. 1729 break; 1730 case TargetLowering::Expand: { 1731 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1732 unsigned Opc = 0; 1733 switch (CCCode) { 1734 default: assert(0 && "Don't know how to expand this condition!"); 1735 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1736 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1737 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1738 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1739 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1740 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1741 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1742 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1743 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1744 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1745 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1746 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1747 // FIXME: Implement more expansions. 1748 } 1749 1750 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1751 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1752 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1753 RHS = SDValue(); 1754 CC = SDValue(); 1755 break; 1756 } 1757 } 1758} 1759 1760/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1761/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1762/// a load from the stack slot to DestVT, extending it if needed. 1763/// The resultant code need not be legal. 1764SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1765 EVT SlotVT, 1766 EVT DestVT, 1767 DebugLoc dl) { 1768 // Create the stack frame object. 1769 unsigned SrcAlign = 1770 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1771 getTypeForEVT(*DAG.getContext())); 1772 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1773 1774 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1775 int SPFI = StackPtrFI->getIndex(); 1776 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1777 1778 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1779 unsigned SlotSize = SlotVT.getSizeInBits(); 1780 unsigned DestSize = DestVT.getSizeInBits(); 1781 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); 1782 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType); 1783 1784 // Emit a store to the stack slot. Use a truncstore if the input value is 1785 // later than DestVT. 1786 SDValue Store; 1787 1788 if (SrcSize > SlotSize) 1789 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1790 SV, 0, SlotVT, false, false, SrcAlign); 1791 else { 1792 assert(SrcSize == SlotSize && "Invalid store"); 1793 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1794 SV, 0, false, false, SrcAlign); 1795 } 1796 1797 // Result is a load from the stack slot. 1798 if (SlotSize == DestSize) 1799 return DAG.getLoad(DestVT, dl, Store, FIPtr, MachinePointerInfo(SV), 1800 false, false, DestAlign); 1801 1802 assert(SlotSize < DestSize && "Unknown extension!"); 1803 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, Store, FIPtr, 1804 MachinePointerInfo(SV), SlotVT, 1805 false, false, DestAlign); 1806} 1807 1808SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1809 DebugLoc dl = Node->getDebugLoc(); 1810 // Create a vector sized/aligned stack slot, store the value to element #0, 1811 // then load the whole vector back out. 1812 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1813 1814 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1815 int SPFI = StackPtrFI->getIndex(); 1816 1817 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1818 StackPtr, 1819 MachinePointerInfo::getFixedStack(SPFI), 1820 Node->getValueType(0).getVectorElementType(), 1821 false, false, 0); 1822 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1823 MachinePointerInfo::getFixedStack(SPFI), 1824 false, false, 0); 1825} 1826 1827 1828/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1829/// support the operation, but do support the resultant vector type. 1830SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1831 unsigned NumElems = Node->getNumOperands(); 1832 SDValue Value1, Value2; 1833 DebugLoc dl = Node->getDebugLoc(); 1834 EVT VT = Node->getValueType(0); 1835 EVT OpVT = Node->getOperand(0).getValueType(); 1836 EVT EltVT = VT.getVectorElementType(); 1837 1838 // If the only non-undef value is the low element, turn this into a 1839 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1840 bool isOnlyLowElement = true; 1841 bool MoreThanTwoValues = false; 1842 bool isConstant = true; 1843 for (unsigned i = 0; i < NumElems; ++i) { 1844 SDValue V = Node->getOperand(i); 1845 if (V.getOpcode() == ISD::UNDEF) 1846 continue; 1847 if (i > 0) 1848 isOnlyLowElement = false; 1849 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1850 isConstant = false; 1851 1852 if (!Value1.getNode()) { 1853 Value1 = V; 1854 } else if (!Value2.getNode()) { 1855 if (V != Value1) 1856 Value2 = V; 1857 } else if (V != Value1 && V != Value2) { 1858 MoreThanTwoValues = true; 1859 } 1860 } 1861 1862 if (!Value1.getNode()) 1863 return DAG.getUNDEF(VT); 1864 1865 if (isOnlyLowElement) 1866 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1867 1868 // If all elements are constants, create a load from the constant pool. 1869 if (isConstant) { 1870 std::vector<Constant*> CV; 1871 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1872 if (ConstantFPSDNode *V = 1873 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1874 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1875 } else if (ConstantSDNode *V = 1876 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1877 if (OpVT==EltVT) 1878 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1879 else { 1880 // If OpVT and EltVT don't match, EltVT is not legal and the 1881 // element values have been promoted/truncated earlier. Undo this; 1882 // we don't want a v16i8 to become a v16i32 for example. 1883 const ConstantInt *CI = V->getConstantIntValue(); 1884 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1885 CI->getZExtValue())); 1886 } 1887 } else { 1888 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1889 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1890 CV.push_back(UndefValue::get(OpNTy)); 1891 } 1892 } 1893 Constant *CP = ConstantVector::get(CV); 1894 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1895 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1896 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1897 MachinePointerInfo::getConstantPool(), 1898 false, false, Alignment); 1899 } 1900 1901 if (!MoreThanTwoValues) { 1902 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1903 for (unsigned i = 0; i < NumElems; ++i) { 1904 SDValue V = Node->getOperand(i); 1905 if (V.getOpcode() == ISD::UNDEF) 1906 continue; 1907 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1908 } 1909 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1910 // Get the splatted value into the low element of a vector register. 1911 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1912 SDValue Vec2; 1913 if (Value2.getNode()) 1914 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1915 else 1916 Vec2 = DAG.getUNDEF(VT); 1917 1918 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1919 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1920 } 1921 } 1922 1923 // Otherwise, we can't handle this case efficiently. 1924 return ExpandVectorBuildThroughStack(Node); 1925} 1926 1927// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1928// does not fit into a register, return the lo part and set the hi part to the 1929// by-reg argument. If it does fit into a single register, return the result 1930// and leave the Hi part unset. 1931SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1932 bool isSigned) { 1933 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1934 // The input chain to this libcall is the entry node of the function. 1935 // Legalizing the call will automatically add the previous call to the 1936 // dependence. 1937 SDValue InChain = DAG.getEntryNode(); 1938 1939 TargetLowering::ArgListTy Args; 1940 TargetLowering::ArgListEntry Entry; 1941 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1942 EVT ArgVT = Node->getOperand(i).getValueType(); 1943 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1944 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1945 Entry.isSExt = isSigned; 1946 Entry.isZExt = !isSigned; 1947 Args.push_back(Entry); 1948 } 1949 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1950 TLI.getPointerTy()); 1951 1952 // Splice the libcall in wherever FindInputOutputChains tells us to. 1953 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1954 std::pair<SDValue, SDValue> CallInfo = 1955 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1956 0, TLI.getLibcallCallingConv(LC), false, 1957 /*isReturnValueUsed=*/true, 1958 Callee, Args, DAG, Node->getDebugLoc()); 1959 1960 // Legalize the call sequence, starting with the chain. This will advance 1961 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1962 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1963 LegalizeOp(CallInfo.second); 1964 return CallInfo.first; 1965} 1966 1967// ExpandChainLibCall - Expand a node into a call to a libcall. Similar to 1968// ExpandLibCall except that the first operand is the in-chain. 1969std::pair<SDValue, SDValue> 1970SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC, 1971 SDNode *Node, 1972 bool isSigned) { 1973 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1974 SDValue InChain = Node->getOperand(0); 1975 1976 TargetLowering::ArgListTy Args; 1977 TargetLowering::ArgListEntry Entry; 1978 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) { 1979 EVT ArgVT = Node->getOperand(i).getValueType(); 1980 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1981 Entry.Node = Node->getOperand(i); 1982 Entry.Ty = ArgTy; 1983 Entry.isSExt = isSigned; 1984 Entry.isZExt = !isSigned; 1985 Args.push_back(Entry); 1986 } 1987 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1988 TLI.getPointerTy()); 1989 1990 // Splice the libcall in wherever FindInputOutputChains tells us to. 1991 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1992 std::pair<SDValue, SDValue> CallInfo = 1993 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1994 0, TLI.getLibcallCallingConv(LC), false, 1995 /*isReturnValueUsed=*/true, 1996 Callee, Args, DAG, Node->getDebugLoc()); 1997 1998 // Legalize the call sequence, starting with the chain. This will advance 1999 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 2000 // was added by LowerCallTo (guaranteeing proper serialization of calls). 2001 LegalizeOp(CallInfo.second); 2002 return CallInfo; 2003} 2004 2005SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 2006 RTLIB::Libcall Call_F32, 2007 RTLIB::Libcall Call_F64, 2008 RTLIB::Libcall Call_F80, 2009 RTLIB::Libcall Call_PPCF128) { 2010 RTLIB::Libcall LC; 2011 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2012 default: assert(0 && "Unexpected request for libcall!"); 2013 case MVT::f32: LC = Call_F32; break; 2014 case MVT::f64: LC = Call_F64; break; 2015 case MVT::f80: LC = Call_F80; break; 2016 case MVT::ppcf128: LC = Call_PPCF128; break; 2017 } 2018 return ExpandLibCall(LC, Node, false); 2019} 2020 2021SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 2022 RTLIB::Libcall Call_I8, 2023 RTLIB::Libcall Call_I16, 2024 RTLIB::Libcall Call_I32, 2025 RTLIB::Libcall Call_I64, 2026 RTLIB::Libcall Call_I128) { 2027 RTLIB::Libcall LC; 2028 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2029 default: assert(0 && "Unexpected request for libcall!"); 2030 case MVT::i8: LC = Call_I8; break; 2031 case MVT::i16: LC = Call_I16; break; 2032 case MVT::i32: LC = Call_I32; break; 2033 case MVT::i64: LC = Call_I64; break; 2034 case MVT::i128: LC = Call_I128; break; 2035 } 2036 return ExpandLibCall(LC, Node, isSigned); 2037} 2038 2039/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 2040/// INT_TO_FP operation of the specified operand when the target requests that 2041/// we expand it. At this point, we know that the result and operand types are 2042/// legal for the target. 2043SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 2044 SDValue Op0, 2045 EVT DestVT, 2046 DebugLoc dl) { 2047 if (Op0.getValueType() == MVT::i32) { 2048 // simple 32-bit [signed|unsigned] integer to float/double expansion 2049 2050 // Get the stack frame index of a 8 byte buffer. 2051 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 2052 2053 // word offset constant for Hi/Lo address computation 2054 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 2055 // set up Hi and Lo (into buffer) address based on endian 2056 SDValue Hi = StackSlot; 2057 SDValue Lo = DAG.getNode(ISD::ADD, dl, 2058 TLI.getPointerTy(), StackSlot, WordOff); 2059 if (TLI.isLittleEndian()) 2060 std::swap(Hi, Lo); 2061 2062 // if signed map to unsigned space 2063 SDValue Op0Mapped; 2064 if (isSigned) { 2065 // constant used to invert sign bit (signed to unsigned mapping) 2066 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 2067 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 2068 } else { 2069 Op0Mapped = Op0; 2070 } 2071 // store the lo of the constructed double - based on integer input 2072 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 2073 Op0Mapped, Lo, NULL, 0, 2074 false, false, 0); 2075 // initial hi portion of constructed double 2076 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2077 // store the hi of the constructed double - biased exponent 2078 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0, 2079 false, false, 0); 2080 // load the constructed double 2081 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, 2082 MachinePointerInfo(), false, false, 0); 2083 // FP constant to bias correct the final result 2084 SDValue Bias = DAG.getConstantFP(isSigned ? 2085 BitsToDouble(0x4330000080000000ULL) : 2086 BitsToDouble(0x4330000000000000ULL), 2087 MVT::f64); 2088 // subtract the bias 2089 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2090 // final result 2091 SDValue Result; 2092 // handle final rounding 2093 if (DestVT == MVT::f64) { 2094 // do nothing 2095 Result = Sub; 2096 } else if (DestVT.bitsLT(MVT::f64)) { 2097 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2098 DAG.getIntPtrConstant(0)); 2099 } else if (DestVT.bitsGT(MVT::f64)) { 2100 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2101 } 2102 return Result; 2103 } 2104 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2105 // Code below here assumes !isSigned without checking again. 2106 2107 // Implementation of unsigned i64 to f64 following the algorithm in 2108 // __floatundidf in compiler_rt. This implementation has the advantage 2109 // of performing rounding correctly, both in the default rounding mode 2110 // and in all alternate rounding modes. 2111 // TODO: Generalize this for use with other types. 2112 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2113 SDValue TwoP52 = 2114 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2115 SDValue TwoP84PlusTwoP52 = 2116 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2117 SDValue TwoP84 = 2118 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2119 2120 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2121 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2122 DAG.getConstant(32, MVT::i64)); 2123 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2124 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2125 SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr); 2126 SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr); 2127 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, 2128 TwoP84PlusTwoP52); 2129 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2130 } 2131 2132 // Implementation of unsigned i64 to f32. This implementation has the 2133 // advantage of performing rounding correctly. 2134 // TODO: Generalize this for use with other types. 2135 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { 2136 EVT SHVT = TLI.getShiftAmountTy(); 2137 2138 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2139 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64)); 2140 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, 2141 DAG.getConstant(UINT64_C(0x800), MVT::i64)); 2142 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2143 DAG.getConstant(UINT64_C(0x7ff), MVT::i64)); 2144 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2145 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); 2146 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0); 2147 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2148 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64), 2149 ISD::SETUGE); 2150 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0); 2151 2152 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2153 DAG.getConstant(32, SHVT)); 2154 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); 2155 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); 2156 SDValue TwoP32 = 2157 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64); 2158 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); 2159 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); 2160 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); 2161 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); 2162 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, 2163 DAG.getIntPtrConstant(0)); 2164 2165 } 2166 2167 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2168 2169 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2170 Op0, DAG.getConstant(0, Op0.getValueType()), 2171 ISD::SETLT); 2172 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2173 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2174 SignSet, Four, Zero); 2175 2176 // If the sign bit of the integer is set, the large number will be treated 2177 // as a negative number. To counteract this, the dynamic code adds an 2178 // offset depending on the data type. 2179 uint64_t FF; 2180 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2181 default: assert(0 && "Unsupported integer type!"); 2182 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2183 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2184 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2185 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2186 } 2187 if (TLI.isLittleEndian()) FF <<= 32; 2188 Constant *FudgeFactor = ConstantInt::get( 2189 Type::getInt64Ty(*DAG.getContext()), FF); 2190 2191 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2192 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2193 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2194 Alignment = std::min(Alignment, 4u); 2195 SDValue FudgeInReg; 2196 if (DestVT == MVT::f32) 2197 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2198 MachinePointerInfo::getConstantPool(), 2199 false, false, Alignment); 2200 else { 2201 FudgeInReg = 2202 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, 2203 DAG.getEntryNode(), CPIdx, 2204 MachinePointerInfo::getConstantPool(), 2205 MVT::f32, false, false, Alignment)); 2206 } 2207 2208 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2209} 2210 2211/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2212/// *INT_TO_FP operation of the specified operand when the target requests that 2213/// we promote it. At this point, we know that the result and operand types are 2214/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2215/// operation that takes a larger input. 2216SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2217 EVT DestVT, 2218 bool isSigned, 2219 DebugLoc dl) { 2220 // First step, figure out the appropriate *INT_TO_FP operation to use. 2221 EVT NewInTy = LegalOp.getValueType(); 2222 2223 unsigned OpToUse = 0; 2224 2225 // Scan for the appropriate larger type to use. 2226 while (1) { 2227 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2228 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2229 2230 // If the target supports SINT_TO_FP of this type, use it. 2231 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2232 OpToUse = ISD::SINT_TO_FP; 2233 break; 2234 } 2235 if (isSigned) continue; 2236 2237 // If the target supports UINT_TO_FP of this type, use it. 2238 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2239 OpToUse = ISD::UINT_TO_FP; 2240 break; 2241 } 2242 2243 // Otherwise, try a larger type. 2244 } 2245 2246 // Okay, we found the operation and type to use. Zero extend our input to the 2247 // desired type then run the operation on it. 2248 return DAG.getNode(OpToUse, dl, DestVT, 2249 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2250 dl, NewInTy, LegalOp)); 2251} 2252 2253/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2254/// FP_TO_*INT operation of the specified operand when the target requests that 2255/// we promote it. At this point, we know that the result and operand types are 2256/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2257/// operation that returns a larger result. 2258SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2259 EVT DestVT, 2260 bool isSigned, 2261 DebugLoc dl) { 2262 // First step, figure out the appropriate FP_TO*INT operation to use. 2263 EVT NewOutTy = DestVT; 2264 2265 unsigned OpToUse = 0; 2266 2267 // Scan for the appropriate larger type to use. 2268 while (1) { 2269 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2270 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2271 2272 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2273 OpToUse = ISD::FP_TO_SINT; 2274 break; 2275 } 2276 2277 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2278 OpToUse = ISD::FP_TO_UINT; 2279 break; 2280 } 2281 2282 // Otherwise, try a larger type. 2283 } 2284 2285 2286 // Okay, we found the operation and type to use. 2287 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2288 2289 // Truncate the result of the extended FP_TO_*INT operation to the desired 2290 // size. 2291 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2292} 2293 2294/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2295/// 2296SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2297 EVT VT = Op.getValueType(); 2298 EVT SHVT = TLI.getShiftAmountTy(); 2299 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2300 switch (VT.getSimpleVT().SimpleTy) { 2301 default: assert(0 && "Unhandled Expand type in BSWAP!"); 2302 case MVT::i16: 2303 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2304 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2305 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2306 case MVT::i32: 2307 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2308 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2309 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2310 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2311 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2312 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2313 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2314 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2315 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2316 case MVT::i64: 2317 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2318 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2319 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2320 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2321 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2322 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2323 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2324 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2325 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2326 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2327 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2328 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2329 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2330 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2331 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2332 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2333 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2334 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2335 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2336 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2337 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2338 } 2339} 2340 2341/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2342/// 2343SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2344 DebugLoc dl) { 2345 switch (Opc) { 2346 default: assert(0 && "Cannot expand this yet!"); 2347 case ISD::CTPOP: { 2348 static const uint64_t mask[6] = { 2349 0x5555555555555555ULL, 0x3333333333333333ULL, 2350 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2351 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2352 }; 2353 EVT VT = Op.getValueType(); 2354 EVT ShVT = TLI.getShiftAmountTy(); 2355 unsigned len = VT.getSizeInBits(); 2356 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2357 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2358 unsigned EltSize = VT.isVector() ? 2359 VT.getVectorElementType().getSizeInBits() : len; 2360 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2361 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2362 Op = DAG.getNode(ISD::ADD, dl, VT, 2363 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2364 DAG.getNode(ISD::AND, dl, VT, 2365 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2366 Tmp2)); 2367 } 2368 return Op; 2369 } 2370 case ISD::CTLZ: { 2371 // for now, we do this: 2372 // x = x | (x >> 1); 2373 // x = x | (x >> 2); 2374 // ... 2375 // x = x | (x >>16); 2376 // x = x | (x >>32); // for 64-bit input 2377 // return popcount(~x); 2378 // 2379 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2380 EVT VT = Op.getValueType(); 2381 EVT ShVT = TLI.getShiftAmountTy(); 2382 unsigned len = VT.getSizeInBits(); 2383 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2384 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2385 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2386 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2387 } 2388 Op = DAG.getNOT(dl, Op, VT); 2389 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2390 } 2391 case ISD::CTTZ: { 2392 // for now, we use: { return popcount(~x & (x - 1)); } 2393 // unless the target has ctlz but not ctpop, in which case we use: 2394 // { return 32 - nlz(~x & (x-1)); } 2395 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2396 EVT VT = Op.getValueType(); 2397 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2398 DAG.getNOT(dl, Op, VT), 2399 DAG.getNode(ISD::SUB, dl, VT, Op, 2400 DAG.getConstant(1, VT))); 2401 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2402 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2403 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2404 return DAG.getNode(ISD::SUB, dl, VT, 2405 DAG.getConstant(VT.getSizeInBits(), VT), 2406 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2407 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2408 } 2409 } 2410} 2411 2412std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) { 2413 unsigned Opc = Node->getOpcode(); 2414 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 2415 RTLIB::Libcall LC; 2416 2417 switch (Opc) { 2418 default: 2419 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 2420 break; 2421 case ISD::ATOMIC_SWAP: 2422 switch (VT.SimpleTy) { 2423 default: llvm_unreachable("Unexpected value type for atomic!"); 2424 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 2425 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 2426 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 2427 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 2428 } 2429 break; 2430 case ISD::ATOMIC_CMP_SWAP: 2431 switch (VT.SimpleTy) { 2432 default: llvm_unreachable("Unexpected value type for atomic!"); 2433 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 2434 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 2435 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 2436 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 2437 } 2438 break; 2439 case ISD::ATOMIC_LOAD_ADD: 2440 switch (VT.SimpleTy) { 2441 default: llvm_unreachable("Unexpected value type for atomic!"); 2442 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 2443 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 2444 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 2445 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 2446 } 2447 break; 2448 case ISD::ATOMIC_LOAD_SUB: 2449 switch (VT.SimpleTy) { 2450 default: llvm_unreachable("Unexpected value type for atomic!"); 2451 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 2452 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 2453 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 2454 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 2455 } 2456 break; 2457 case ISD::ATOMIC_LOAD_AND: 2458 switch (VT.SimpleTy) { 2459 default: llvm_unreachable("Unexpected value type for atomic!"); 2460 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 2461 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 2462 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 2463 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 2464 } 2465 break; 2466 case ISD::ATOMIC_LOAD_OR: 2467 switch (VT.SimpleTy) { 2468 default: llvm_unreachable("Unexpected value type for atomic!"); 2469 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 2470 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 2471 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 2472 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 2473 } 2474 break; 2475 case ISD::ATOMIC_LOAD_XOR: 2476 switch (VT.SimpleTy) { 2477 default: llvm_unreachable("Unexpected value type for atomic!"); 2478 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 2479 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 2480 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 2481 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 2482 } 2483 break; 2484 case ISD::ATOMIC_LOAD_NAND: 2485 switch (VT.SimpleTy) { 2486 default: llvm_unreachable("Unexpected value type for atomic!"); 2487 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 2488 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 2489 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 2490 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 2491 } 2492 break; 2493 } 2494 2495 return ExpandChainLibCall(LC, Node, false); 2496} 2497 2498void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2499 SmallVectorImpl<SDValue> &Results) { 2500 DebugLoc dl = Node->getDebugLoc(); 2501 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2502 switch (Node->getOpcode()) { 2503 case ISD::CTPOP: 2504 case ISD::CTLZ: 2505 case ISD::CTTZ: 2506 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2507 Results.push_back(Tmp1); 2508 break; 2509 case ISD::BSWAP: 2510 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2511 break; 2512 case ISD::FRAMEADDR: 2513 case ISD::RETURNADDR: 2514 case ISD::FRAME_TO_ARGS_OFFSET: 2515 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2516 break; 2517 case ISD::FLT_ROUNDS_: 2518 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2519 break; 2520 case ISD::EH_RETURN: 2521 case ISD::EH_LABEL: 2522 case ISD::PREFETCH: 2523 case ISD::VAEND: 2524 case ISD::EH_SJLJ_LONGJMP: 2525 Results.push_back(Node->getOperand(0)); 2526 break; 2527 case ISD::EH_SJLJ_SETJMP: 2528 Results.push_back(DAG.getConstant(0, MVT::i32)); 2529 Results.push_back(Node->getOperand(0)); 2530 break; 2531 case ISD::MEMBARRIER: { 2532 // If the target didn't lower this, lower it to '__sync_synchronize()' call 2533 TargetLowering::ArgListTy Args; 2534 std::pair<SDValue, SDValue> CallResult = 2535 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2536 false, false, false, false, 0, CallingConv::C, false, 2537 /*isReturnValueUsed=*/true, 2538 DAG.getExternalSymbol("__sync_synchronize", 2539 TLI.getPointerTy()), 2540 Args, DAG, dl); 2541 Results.push_back(CallResult.second); 2542 break; 2543 } 2544 // By default, atomic intrinsics are marked Legal and lowered. Targets 2545 // which don't support them directly, however, may want libcalls, in which 2546 // case they mark them Expand, and we get here. 2547 // FIXME: Unimplemented for now. Add libcalls. 2548 case ISD::ATOMIC_SWAP: 2549 case ISD::ATOMIC_LOAD_ADD: 2550 case ISD::ATOMIC_LOAD_SUB: 2551 case ISD::ATOMIC_LOAD_AND: 2552 case ISD::ATOMIC_LOAD_OR: 2553 case ISD::ATOMIC_LOAD_XOR: 2554 case ISD::ATOMIC_LOAD_NAND: 2555 case ISD::ATOMIC_LOAD_MIN: 2556 case ISD::ATOMIC_LOAD_MAX: 2557 case ISD::ATOMIC_LOAD_UMIN: 2558 case ISD::ATOMIC_LOAD_UMAX: 2559 case ISD::ATOMIC_CMP_SWAP: { 2560 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node); 2561 Results.push_back(Tmp.first); 2562 Results.push_back(Tmp.second); 2563 break; 2564 } 2565 case ISD::DYNAMIC_STACKALLOC: 2566 ExpandDYNAMIC_STACKALLOC(Node, Results); 2567 break; 2568 case ISD::MERGE_VALUES: 2569 for (unsigned i = 0; i < Node->getNumValues(); i++) 2570 Results.push_back(Node->getOperand(i)); 2571 break; 2572 case ISD::UNDEF: { 2573 EVT VT = Node->getValueType(0); 2574 if (VT.isInteger()) 2575 Results.push_back(DAG.getConstant(0, VT)); 2576 else { 2577 assert(VT.isFloatingPoint() && "Unknown value type!"); 2578 Results.push_back(DAG.getConstantFP(0, VT)); 2579 } 2580 break; 2581 } 2582 case ISD::TRAP: { 2583 // If this operation is not supported, lower it to 'abort()' call 2584 TargetLowering::ArgListTy Args; 2585 std::pair<SDValue, SDValue> CallResult = 2586 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2587 false, false, false, false, 0, CallingConv::C, false, 2588 /*isReturnValueUsed=*/true, 2589 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2590 Args, DAG, dl); 2591 Results.push_back(CallResult.second); 2592 break; 2593 } 2594 case ISD::FP_ROUND: 2595 case ISD::BIT_CONVERT: 2596 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2597 Node->getValueType(0), dl); 2598 Results.push_back(Tmp1); 2599 break; 2600 case ISD::FP_EXTEND: 2601 Tmp1 = EmitStackConvert(Node->getOperand(0), 2602 Node->getOperand(0).getValueType(), 2603 Node->getValueType(0), dl); 2604 Results.push_back(Tmp1); 2605 break; 2606 case ISD::SIGN_EXTEND_INREG: { 2607 // NOTE: we could fall back on load/store here too for targets without 2608 // SAR. However, it is doubtful that any exist. 2609 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2610 EVT VT = Node->getValueType(0); 2611 EVT ShiftAmountTy = TLI.getShiftAmountTy(); 2612 if (VT.isVector()) 2613 ShiftAmountTy = VT; 2614 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2615 ExtraVT.getScalarType().getSizeInBits(); 2616 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2617 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2618 Node->getOperand(0), ShiftCst); 2619 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2620 Results.push_back(Tmp1); 2621 break; 2622 } 2623 case ISD::FP_ROUND_INREG: { 2624 // The only way we can lower this is to turn it into a TRUNCSTORE, 2625 // EXTLOAD pair, targetting a temporary location (a stack slot). 2626 2627 // NOTE: there is a choice here between constantly creating new stack 2628 // slots and always reusing the same one. We currently always create 2629 // new ones, as reuse may inhibit scheduling. 2630 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2631 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2632 Node->getValueType(0), dl); 2633 Results.push_back(Tmp1); 2634 break; 2635 } 2636 case ISD::SINT_TO_FP: 2637 case ISD::UINT_TO_FP: 2638 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2639 Node->getOperand(0), Node->getValueType(0), dl); 2640 Results.push_back(Tmp1); 2641 break; 2642 case ISD::FP_TO_UINT: { 2643 SDValue True, False; 2644 EVT VT = Node->getOperand(0).getValueType(); 2645 EVT NVT = Node->getValueType(0); 2646 const uint64_t zero[] = {0, 0}; 2647 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2648 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2649 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2650 Tmp1 = DAG.getConstantFP(apf, VT); 2651 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2652 Node->getOperand(0), 2653 Tmp1, ISD::SETLT); 2654 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2655 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2656 DAG.getNode(ISD::FSUB, dl, VT, 2657 Node->getOperand(0), Tmp1)); 2658 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2659 DAG.getConstant(x, NVT)); 2660 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2661 Results.push_back(Tmp1); 2662 break; 2663 } 2664 case ISD::VAARG: { 2665 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2666 EVT VT = Node->getValueType(0); 2667 Tmp1 = Node->getOperand(0); 2668 Tmp2 = Node->getOperand(1); 2669 unsigned Align = Node->getConstantOperandVal(3); 2670 2671 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, 2672 MachinePointerInfo(V), false, false, 0); 2673 SDValue VAList = VAListLoad; 2674 2675 if (Align > TLI.getMinStackArgumentAlignment()) { 2676 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2677 2678 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2679 DAG.getConstant(Align - 1, 2680 TLI.getPointerTy())); 2681 2682 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList, 2683 DAG.getConstant(-Align, 2684 TLI.getPointerTy())); 2685 } 2686 2687 // Increment the pointer, VAList, to the next vaarg 2688 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2689 DAG.getConstant(TLI.getTargetData()-> 2690 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2691 TLI.getPointerTy())); 2692 // Store the incremented VAList to the legalized pointer 2693 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, V, 0, 2694 false, false, 0); 2695 // Load the actual argument out of the pointer VAList 2696 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(), 2697 false, false, 0)); 2698 Results.push_back(Results[0].getValue(1)); 2699 break; 2700 } 2701 case ISD::VACOPY: { 2702 // This defaults to loading a pointer from the input and storing it to the 2703 // output, returning the chain. 2704 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2705 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2706 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2707 Node->getOperand(2), MachinePointerInfo(VS), 2708 false, false, 0); 2709 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), 2710 MachinePointerInfo(VD), false, false, 0); 2711 Results.push_back(Tmp1); 2712 break; 2713 } 2714 case ISD::EXTRACT_VECTOR_ELT: 2715 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2716 // This must be an access of the only element. Return it. 2717 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2718 Node->getOperand(0)); 2719 else 2720 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2721 Results.push_back(Tmp1); 2722 break; 2723 case ISD::EXTRACT_SUBVECTOR: 2724 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2725 break; 2726 case ISD::CONCAT_VECTORS: { 2727 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2728 break; 2729 } 2730 case ISD::SCALAR_TO_VECTOR: 2731 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2732 break; 2733 case ISD::INSERT_VECTOR_ELT: 2734 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2735 Node->getOperand(1), 2736 Node->getOperand(2), dl)); 2737 break; 2738 case ISD::VECTOR_SHUFFLE: { 2739 SmallVector<int, 8> Mask; 2740 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2741 2742 EVT VT = Node->getValueType(0); 2743 EVT EltVT = VT.getVectorElementType(); 2744 if (getTypeAction(EltVT) == Promote) 2745 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT); 2746 unsigned NumElems = VT.getVectorNumElements(); 2747 SmallVector<SDValue, 8> Ops; 2748 for (unsigned i = 0; i != NumElems; ++i) { 2749 if (Mask[i] < 0) { 2750 Ops.push_back(DAG.getUNDEF(EltVT)); 2751 continue; 2752 } 2753 unsigned Idx = Mask[i]; 2754 if (Idx < NumElems) 2755 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2756 Node->getOperand(0), 2757 DAG.getIntPtrConstant(Idx))); 2758 else 2759 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2760 Node->getOperand(1), 2761 DAG.getIntPtrConstant(Idx - NumElems))); 2762 } 2763 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2764 Results.push_back(Tmp1); 2765 break; 2766 } 2767 case ISD::EXTRACT_ELEMENT: { 2768 EVT OpTy = Node->getOperand(0).getValueType(); 2769 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2770 // 1 -> Hi 2771 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2772 DAG.getConstant(OpTy.getSizeInBits()/2, 2773 TLI.getShiftAmountTy())); 2774 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2775 } else { 2776 // 0 -> Lo 2777 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2778 Node->getOperand(0)); 2779 } 2780 Results.push_back(Tmp1); 2781 break; 2782 } 2783 case ISD::STACKSAVE: 2784 // Expand to CopyFromReg if the target set 2785 // StackPointerRegisterToSaveRestore. 2786 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2787 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2788 Node->getValueType(0))); 2789 Results.push_back(Results[0].getValue(1)); 2790 } else { 2791 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2792 Results.push_back(Node->getOperand(0)); 2793 } 2794 break; 2795 case ISD::STACKRESTORE: 2796 // Expand to CopyToReg if the target set 2797 // StackPointerRegisterToSaveRestore. 2798 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2799 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2800 Node->getOperand(1))); 2801 } else { 2802 Results.push_back(Node->getOperand(0)); 2803 } 2804 break; 2805 case ISD::FCOPYSIGN: 2806 Results.push_back(ExpandFCOPYSIGN(Node)); 2807 break; 2808 case ISD::FNEG: 2809 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2810 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2811 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2812 Node->getOperand(0)); 2813 Results.push_back(Tmp1); 2814 break; 2815 case ISD::FABS: { 2816 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2817 EVT VT = Node->getValueType(0); 2818 Tmp1 = Node->getOperand(0); 2819 Tmp2 = DAG.getConstantFP(0.0, VT); 2820 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2821 Tmp1, Tmp2, ISD::SETUGT); 2822 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2823 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2824 Results.push_back(Tmp1); 2825 break; 2826 } 2827 case ISD::FSQRT: 2828 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2829 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2830 break; 2831 case ISD::FSIN: 2832 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2833 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2834 break; 2835 case ISD::FCOS: 2836 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2837 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2838 break; 2839 case ISD::FLOG: 2840 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2841 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2842 break; 2843 case ISD::FLOG2: 2844 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2845 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2846 break; 2847 case ISD::FLOG10: 2848 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2849 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2850 break; 2851 case ISD::FEXP: 2852 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2853 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2854 break; 2855 case ISD::FEXP2: 2856 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2857 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2858 break; 2859 case ISD::FTRUNC: 2860 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2861 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2862 break; 2863 case ISD::FFLOOR: 2864 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2865 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2866 break; 2867 case ISD::FCEIL: 2868 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2869 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2870 break; 2871 case ISD::FRINT: 2872 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2873 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2874 break; 2875 case ISD::FNEARBYINT: 2876 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2877 RTLIB::NEARBYINT_F64, 2878 RTLIB::NEARBYINT_F80, 2879 RTLIB::NEARBYINT_PPCF128)); 2880 break; 2881 case ISD::FPOWI: 2882 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2883 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2884 break; 2885 case ISD::FPOW: 2886 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2887 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2888 break; 2889 case ISD::FDIV: 2890 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2891 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2892 break; 2893 case ISD::FREM: 2894 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2895 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2896 break; 2897 case ISD::FP16_TO_FP32: 2898 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 2899 break; 2900 case ISD::FP32_TO_FP16: 2901 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 2902 break; 2903 case ISD::ConstantFP: { 2904 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2905 // Check to see if this FP immediate is already legal. 2906 // If this is a legal constant, turn it into a TargetConstantFP node. 2907 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 2908 Results.push_back(SDValue(Node, 0)); 2909 else 2910 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2911 break; 2912 } 2913 case ISD::EHSELECTION: { 2914 unsigned Reg = TLI.getExceptionSelectorRegister(); 2915 assert(Reg && "Can't expand to unknown register!"); 2916 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2917 Node->getValueType(0))); 2918 Results.push_back(Results[0].getValue(1)); 2919 break; 2920 } 2921 case ISD::EXCEPTIONADDR: { 2922 unsigned Reg = TLI.getExceptionAddressRegister(); 2923 assert(Reg && "Can't expand to unknown register!"); 2924 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2925 Node->getValueType(0))); 2926 Results.push_back(Results[0].getValue(1)); 2927 break; 2928 } 2929 case ISD::SUB: { 2930 EVT VT = Node->getValueType(0); 2931 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2932 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2933 "Don't know how to expand this subtraction!"); 2934 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2935 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2936 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2937 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2938 break; 2939 } 2940 case ISD::UREM: 2941 case ISD::SREM: { 2942 EVT VT = Node->getValueType(0); 2943 SDVTList VTs = DAG.getVTList(VT, VT); 2944 bool isSigned = Node->getOpcode() == ISD::SREM; 2945 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2946 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2947 Tmp2 = Node->getOperand(0); 2948 Tmp3 = Node->getOperand(1); 2949 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2950 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2951 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2952 // X % Y -> X-X/Y*Y 2953 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2954 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2955 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2956 } else if (isSigned) { 2957 Tmp1 = ExpandIntLibCall(Node, true, 2958 RTLIB::SREM_I8, 2959 RTLIB::SREM_I16, RTLIB::SREM_I32, 2960 RTLIB::SREM_I64, RTLIB::SREM_I128); 2961 } else { 2962 Tmp1 = ExpandIntLibCall(Node, false, 2963 RTLIB::UREM_I8, 2964 RTLIB::UREM_I16, RTLIB::UREM_I32, 2965 RTLIB::UREM_I64, RTLIB::UREM_I128); 2966 } 2967 Results.push_back(Tmp1); 2968 break; 2969 } 2970 case ISD::UDIV: 2971 case ISD::SDIV: { 2972 bool isSigned = Node->getOpcode() == ISD::SDIV; 2973 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2974 EVT VT = Node->getValueType(0); 2975 SDVTList VTs = DAG.getVTList(VT, VT); 2976 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2977 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2978 Node->getOperand(1)); 2979 else if (isSigned) 2980 Tmp1 = ExpandIntLibCall(Node, true, 2981 RTLIB::SDIV_I8, 2982 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2983 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2984 else 2985 Tmp1 = ExpandIntLibCall(Node, false, 2986 RTLIB::UDIV_I8, 2987 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2988 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2989 Results.push_back(Tmp1); 2990 break; 2991 } 2992 case ISD::MULHU: 2993 case ISD::MULHS: { 2994 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2995 ISD::SMUL_LOHI; 2996 EVT VT = Node->getValueType(0); 2997 SDVTList VTs = DAG.getVTList(VT, VT); 2998 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2999 "If this wasn't legal, it shouldn't have been created!"); 3000 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 3001 Node->getOperand(1)); 3002 Results.push_back(Tmp1.getValue(1)); 3003 break; 3004 } 3005 case ISD::MUL: { 3006 EVT VT = Node->getValueType(0); 3007 SDVTList VTs = DAG.getVTList(VT, VT); 3008 // See if multiply or divide can be lowered using two-result operations. 3009 // We just need the low half of the multiply; try both the signed 3010 // and unsigned forms. If the target supports both SMUL_LOHI and 3011 // UMUL_LOHI, form a preference by checking which forms of plain 3012 // MULH it supports. 3013 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 3014 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 3015 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 3016 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 3017 unsigned OpToUse = 0; 3018 if (HasSMUL_LOHI && !HasMULHS) { 3019 OpToUse = ISD::SMUL_LOHI; 3020 } else if (HasUMUL_LOHI && !HasMULHU) { 3021 OpToUse = ISD::UMUL_LOHI; 3022 } else if (HasSMUL_LOHI) { 3023 OpToUse = ISD::SMUL_LOHI; 3024 } else if (HasUMUL_LOHI) { 3025 OpToUse = ISD::UMUL_LOHI; 3026 } 3027 if (OpToUse) { 3028 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 3029 Node->getOperand(1))); 3030 break; 3031 } 3032 Tmp1 = ExpandIntLibCall(Node, false, 3033 RTLIB::MUL_I8, 3034 RTLIB::MUL_I16, RTLIB::MUL_I32, 3035 RTLIB::MUL_I64, RTLIB::MUL_I128); 3036 Results.push_back(Tmp1); 3037 break; 3038 } 3039 case ISD::SADDO: 3040 case ISD::SSUBO: { 3041 SDValue LHS = Node->getOperand(0); 3042 SDValue RHS = Node->getOperand(1); 3043 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 3044 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3045 LHS, RHS); 3046 Results.push_back(Sum); 3047 EVT OType = Node->getValueType(1); 3048 3049 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 3050 3051 // LHSSign -> LHS >= 0 3052 // RHSSign -> RHS >= 0 3053 // SumSign -> Sum >= 0 3054 // 3055 // Add: 3056 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 3057 // Sub: 3058 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 3059 // 3060 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 3061 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 3062 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 3063 Node->getOpcode() == ISD::SADDO ? 3064 ISD::SETEQ : ISD::SETNE); 3065 3066 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 3067 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 3068 3069 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 3070 Results.push_back(Cmp); 3071 break; 3072 } 3073 case ISD::UADDO: 3074 case ISD::USUBO: { 3075 SDValue LHS = Node->getOperand(0); 3076 SDValue RHS = Node->getOperand(1); 3077 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 3078 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3079 LHS, RHS); 3080 Results.push_back(Sum); 3081 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 3082 Node->getOpcode () == ISD::UADDO ? 3083 ISD::SETULT : ISD::SETUGT)); 3084 break; 3085 } 3086 case ISD::UMULO: 3087 case ISD::SMULO: { 3088 EVT VT = Node->getValueType(0); 3089 SDValue LHS = Node->getOperand(0); 3090 SDValue RHS = Node->getOperand(1); 3091 SDValue BottomHalf; 3092 SDValue TopHalf; 3093 static const unsigned Ops[2][3] = 3094 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 3095 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 3096 bool isSigned = Node->getOpcode() == ISD::SMULO; 3097 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 3098 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 3099 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 3100 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 3101 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 3102 RHS); 3103 TopHalf = BottomHalf.getValue(1); 3104 } else { 3105 // FIXME: We should be able to fall back to a libcall with an illegal 3106 // type in some cases. 3107 // Also, we can fall back to a division in some cases, but that's a big 3108 // performance hit in the general case. 3109 assert(TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), 3110 VT.getSizeInBits() * 2)) && 3111 "Don't know how to expand this operation yet!"); 3112 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 3113 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 3114 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 3115 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 3116 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3117 DAG.getIntPtrConstant(0)); 3118 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3119 DAG.getIntPtrConstant(1)); 3120 } 3121 if (isSigned) { 3122 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); 3123 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 3124 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 3125 ISD::SETNE); 3126 } else { 3127 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 3128 DAG.getConstant(0, VT), ISD::SETNE); 3129 } 3130 Results.push_back(BottomHalf); 3131 Results.push_back(TopHalf); 3132 break; 3133 } 3134 case ISD::BUILD_PAIR: { 3135 EVT PairTy = Node->getValueType(0); 3136 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 3137 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 3138 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 3139 DAG.getConstant(PairTy.getSizeInBits()/2, 3140 TLI.getShiftAmountTy())); 3141 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 3142 break; 3143 } 3144 case ISD::SELECT: 3145 Tmp1 = Node->getOperand(0); 3146 Tmp2 = Node->getOperand(1); 3147 Tmp3 = Node->getOperand(2); 3148 if (Tmp1.getOpcode() == ISD::SETCC) { 3149 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 3150 Tmp2, Tmp3, 3151 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 3152 } else { 3153 Tmp1 = DAG.getSelectCC(dl, Tmp1, 3154 DAG.getConstant(0, Tmp1.getValueType()), 3155 Tmp2, Tmp3, ISD::SETNE); 3156 } 3157 Results.push_back(Tmp1); 3158 break; 3159 case ISD::BR_JT: { 3160 SDValue Chain = Node->getOperand(0); 3161 SDValue Table = Node->getOperand(1); 3162 SDValue Index = Node->getOperand(2); 3163 3164 EVT PTy = TLI.getPointerTy(); 3165 3166 const TargetData &TD = *TLI.getTargetData(); 3167 unsigned EntrySize = 3168 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 3169 3170 Index = DAG.getNode(ISD::MUL, dl, PTy, 3171 Index, DAG.getConstant(EntrySize, PTy)); 3172 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 3173 3174 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 3175 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, dl, Chain, Addr, 3176 MachinePointerInfo::getJumpTable(), MemVT, 3177 false, false, 0); 3178 Addr = LD; 3179 if (TM.getRelocationModel() == Reloc::PIC_) { 3180 // For PIC, the sequence is: 3181 // BRIND(load(Jumptable + index) + RelocBase) 3182 // RelocBase can be JumpTable, GOT or some sort of global base. 3183 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 3184 TLI.getPICJumpTableRelocBase(Table, DAG)); 3185 } 3186 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 3187 Results.push_back(Tmp1); 3188 break; 3189 } 3190 case ISD::BRCOND: 3191 // Expand brcond's setcc into its constituent parts and create a BR_CC 3192 // Node. 3193 Tmp1 = Node->getOperand(0); 3194 Tmp2 = Node->getOperand(1); 3195 if (Tmp2.getOpcode() == ISD::SETCC) { 3196 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 3197 Tmp1, Tmp2.getOperand(2), 3198 Tmp2.getOperand(0), Tmp2.getOperand(1), 3199 Node->getOperand(2)); 3200 } else { 3201 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 3202 DAG.getCondCode(ISD::SETNE), Tmp2, 3203 DAG.getConstant(0, Tmp2.getValueType()), 3204 Node->getOperand(2)); 3205 } 3206 Results.push_back(Tmp1); 3207 break; 3208 case ISD::SETCC: { 3209 Tmp1 = Node->getOperand(0); 3210 Tmp2 = Node->getOperand(1); 3211 Tmp3 = Node->getOperand(2); 3212 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 3213 3214 // If we expanded the SETCC into an AND/OR, return the new node 3215 if (Tmp2.getNode() == 0) { 3216 Results.push_back(Tmp1); 3217 break; 3218 } 3219 3220 // Otherwise, SETCC for the given comparison type must be completely 3221 // illegal; expand it into a SELECT_CC. 3222 EVT VT = Node->getValueType(0); 3223 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3224 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 3225 Results.push_back(Tmp1); 3226 break; 3227 } 3228 case ISD::SELECT_CC: { 3229 Tmp1 = Node->getOperand(0); // LHS 3230 Tmp2 = Node->getOperand(1); // RHS 3231 Tmp3 = Node->getOperand(2); // True 3232 Tmp4 = Node->getOperand(3); // False 3233 SDValue CC = Node->getOperand(4); 3234 3235 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 3236 Tmp1, Tmp2, CC, dl); 3237 3238 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 3239 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3240 CC = DAG.getCondCode(ISD::SETNE); 3241 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 3242 Tmp3, Tmp4, CC); 3243 Results.push_back(Tmp1); 3244 break; 3245 } 3246 case ISD::BR_CC: { 3247 Tmp1 = Node->getOperand(0); // Chain 3248 Tmp2 = Node->getOperand(2); // LHS 3249 Tmp3 = Node->getOperand(3); // RHS 3250 Tmp4 = Node->getOperand(1); // CC 3251 3252 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 3253 Tmp2, Tmp3, Tmp4, dl); 3254 LastCALLSEQ_END = DAG.getEntryNode(); 3255 3256 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 3257 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 3258 Tmp4 = DAG.getCondCode(ISD::SETNE); 3259 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3260 Tmp3, Node->getOperand(4)); 3261 Results.push_back(Tmp1); 3262 break; 3263 } 3264 case ISD::GLOBAL_OFFSET_TABLE: 3265 case ISD::GlobalAddress: 3266 case ISD::GlobalTLSAddress: 3267 case ISD::ExternalSymbol: 3268 case ISD::ConstantPool: 3269 case ISD::JumpTable: 3270 case ISD::INTRINSIC_W_CHAIN: 3271 case ISD::INTRINSIC_WO_CHAIN: 3272 case ISD::INTRINSIC_VOID: 3273 // FIXME: Custom lowering for these operations shouldn't return null! 3274 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3275 Results.push_back(SDValue(Node, i)); 3276 break; 3277 } 3278} 3279void SelectionDAGLegalize::PromoteNode(SDNode *Node, 3280 SmallVectorImpl<SDValue> &Results) { 3281 EVT OVT = Node->getValueType(0); 3282 if (Node->getOpcode() == ISD::UINT_TO_FP || 3283 Node->getOpcode() == ISD::SINT_TO_FP || 3284 Node->getOpcode() == ISD::SETCC) { 3285 OVT = Node->getOperand(0).getValueType(); 3286 } 3287 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3288 DebugLoc dl = Node->getDebugLoc(); 3289 SDValue Tmp1, Tmp2, Tmp3; 3290 switch (Node->getOpcode()) { 3291 case ISD::CTTZ: 3292 case ISD::CTLZ: 3293 case ISD::CTPOP: 3294 // Zero extend the argument. 3295 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3296 // Perform the larger operation. 3297 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3298 if (Node->getOpcode() == ISD::CTTZ) { 3299 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3300 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3301 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3302 ISD::SETEQ); 3303 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3304 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3305 } else if (Node->getOpcode() == ISD::CTLZ) { 3306 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3307 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3308 DAG.getConstant(NVT.getSizeInBits() - 3309 OVT.getSizeInBits(), NVT)); 3310 } 3311 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3312 break; 3313 case ISD::BSWAP: { 3314 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3315 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3316 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3317 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3318 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3319 Results.push_back(Tmp1); 3320 break; 3321 } 3322 case ISD::FP_TO_UINT: 3323 case ISD::FP_TO_SINT: 3324 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3325 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3326 Results.push_back(Tmp1); 3327 break; 3328 case ISD::UINT_TO_FP: 3329 case ISD::SINT_TO_FP: 3330 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3331 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3332 Results.push_back(Tmp1); 3333 break; 3334 case ISD::AND: 3335 case ISD::OR: 3336 case ISD::XOR: { 3337 unsigned ExtOp, TruncOp; 3338 if (OVT.isVector()) { 3339 ExtOp = ISD::BIT_CONVERT; 3340 TruncOp = ISD::BIT_CONVERT; 3341 } else { 3342 assert(OVT.isInteger() && "Cannot promote logic operation"); 3343 ExtOp = ISD::ANY_EXTEND; 3344 TruncOp = ISD::TRUNCATE; 3345 } 3346 // Promote each of the values to the new type. 3347 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3348 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3349 // Perform the larger operation, then convert back 3350 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3351 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3352 break; 3353 } 3354 case ISD::SELECT: { 3355 unsigned ExtOp, TruncOp; 3356 if (Node->getValueType(0).isVector()) { 3357 ExtOp = ISD::BIT_CONVERT; 3358 TruncOp = ISD::BIT_CONVERT; 3359 } else if (Node->getValueType(0).isInteger()) { 3360 ExtOp = ISD::ANY_EXTEND; 3361 TruncOp = ISD::TRUNCATE; 3362 } else { 3363 ExtOp = ISD::FP_EXTEND; 3364 TruncOp = ISD::FP_ROUND; 3365 } 3366 Tmp1 = Node->getOperand(0); 3367 // Promote each of the values to the new type. 3368 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3369 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3370 // Perform the larger operation, then round down. 3371 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3372 if (TruncOp != ISD::FP_ROUND) 3373 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3374 else 3375 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3376 DAG.getIntPtrConstant(0)); 3377 Results.push_back(Tmp1); 3378 break; 3379 } 3380 case ISD::VECTOR_SHUFFLE: { 3381 SmallVector<int, 8> Mask; 3382 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3383 3384 // Cast the two input vectors. 3385 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3386 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3387 3388 // Convert the shuffle mask to the right # elements. 3389 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3390 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3391 Results.push_back(Tmp1); 3392 break; 3393 } 3394 case ISD::SETCC: { 3395 unsigned ExtOp = ISD::FP_EXTEND; 3396 if (NVT.isInteger()) { 3397 ISD::CondCode CCCode = 3398 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3399 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3400 } 3401 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3402 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3403 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3404 Tmp1, Tmp2, Node->getOperand(2))); 3405 break; 3406 } 3407 } 3408} 3409 3410// SelectionDAG::Legalize - This is the entry point for the file. 3411// 3412void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) { 3413 /// run - This is the main entry point to this class. 3414 /// 3415 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3416} 3417 3418