LegalizeDAG.cpp revision e326332acd5fefb9854118603b4d07d4e44b64c5
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetFrameInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/CallingConv.h" 26#include "llvm/Constants.h" 27#include "llvm/DerivedTypes.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Compiler.h" 30#include "llvm/Support/MathExtras.h" 31#include "llvm/ADT/DenseMap.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/SmallPtrSet.h" 34#include <map> 35using namespace llvm; 36 37#ifndef NDEBUG 38static cl::opt<bool> 39ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 40 cl::desc("Pop up a window to show dags before legalize")); 41#else 42static const bool ViewLegalizeDAGs = 0; 43#endif 44 45//===----------------------------------------------------------------------===// 46/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 47/// hacks on it until the target machine can handle it. This involves 48/// eliminating value sizes the machine cannot handle (promoting small sizes to 49/// large sizes or splitting up large values into small values) as well as 50/// eliminating operations the machine cannot handle. 51/// 52/// This code also does a small amount of optimization and recognition of idioms 53/// as part of its processing. For example, if a target does not support a 54/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 55/// will attempt merge setcc and brc instructions into brcc's. 56/// 57namespace { 58class VISIBILITY_HIDDEN SelectionDAGLegalize { 59 TargetLowering &TLI; 60 SelectionDAG &DAG; 61 62 // Libcall insertion helpers. 63 64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 65 /// legalized. We use this to ensure that calls are properly serialized 66 /// against each other, including inserted libcalls. 67 SDOperand LastCALLSEQ_END; 68 69 /// IsLegalizingCall - This member is used *only* for purposes of providing 70 /// helpful assertions that a libcall isn't created while another call is 71 /// being legalized (which could lead to non-serialized call sequences). 72 bool IsLegalizingCall; 73 74 enum LegalizeAction { 75 Legal, // The target natively supports this operation. 76 Promote, // This operation should be executed in a larger type. 77 Expand // Try to expand this to other ops, otherwise use a libcall. 78 }; 79 80 /// ValueTypeActions - This is a bitvector that contains two bits for each 81 /// value type, where the two bits correspond to the LegalizeAction enum. 82 /// This can be queried with "getTypeAction(VT)". 83 TargetLowering::ValueTypeActionImpl ValueTypeActions; 84 85 /// LegalizedNodes - For nodes that are of legal width, and that have more 86 /// than one use, this map indicates what regularized operand to use. This 87 /// allows us to avoid legalizing the same thing more than once. 88 DenseMap<SDOperandImpl, SDOperand> LegalizedNodes; 89 90 /// PromotedNodes - For nodes that are below legal width, and that have more 91 /// than one use, this map indicates what promoted value to use. This allows 92 /// us to avoid promoting the same thing more than once. 93 DenseMap<SDOperandImpl, SDOperand> PromotedNodes; 94 95 /// ExpandedNodes - For nodes that need to be expanded this map indicates 96 /// which which operands are the expanded version of the input. This allows 97 /// us to avoid expanding the same node more than once. 98 DenseMap<SDOperandImpl, std::pair<SDOperand, SDOperand> > ExpandedNodes; 99 100 /// SplitNodes - For vector nodes that need to be split, this map indicates 101 /// which which operands are the split version of the input. This allows us 102 /// to avoid splitting the same node more than once. 103 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 104 105 /// ScalarizedNodes - For nodes that need to be converted from vector types to 106 /// scalar types, this contains the mapping of ones we have already 107 /// processed to the result. 108 std::map<SDOperand, SDOperand> ScalarizedNodes; 109 110 void AddLegalizedOperand(SDOperand From, SDOperand To) { 111 LegalizedNodes.insert(std::make_pair(From, To)); 112 // If someone requests legalization of the new node, return itself. 113 if (From != To) 114 LegalizedNodes.insert(std::make_pair(To, To)); 115 } 116 void AddPromotedOperand(SDOperand From, SDOperand To) { 117 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 118 assert(isNew && "Got into the map somehow?"); 119 // If someone requests legalization of the new node, return itself. 120 LegalizedNodes.insert(std::make_pair(To, To)); 121 } 122 123public: 124 125 SelectionDAGLegalize(SelectionDAG &DAG); 126 127 /// getTypeAction - Return how we should legalize values of this type, either 128 /// it is already legal or we need to expand it into multiple registers of 129 /// smaller integer type, or we need to promote it to a larger type. 130 LegalizeAction getTypeAction(MVT::ValueType VT) const { 131 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 132 } 133 134 /// isTypeLegal - Return true if this type is legal on this target. 135 /// 136 bool isTypeLegal(MVT::ValueType VT) const { 137 return getTypeAction(VT) == Legal; 138 } 139 140 void LegalizeDAG(); 141 142private: 143 /// HandleOp - Legalize, Promote, or Expand the specified operand as 144 /// appropriate for its type. 145 void HandleOp(SDOperand Op); 146 147 /// LegalizeOp - We know that the specified value has a legal type. 148 /// Recursively ensure that the operands have legal types, then return the 149 /// result. 150 SDOperand LegalizeOp(SDOperand O); 151 152 /// UnrollVectorOp - We know that the given vector has a legal type, however 153 /// the operation it performs is not legal and is an operation that we have 154 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 155 /// operating on each element individually. 156 SDOperand UnrollVectorOp(SDOperand O); 157 158 /// PromoteOp - Given an operation that produces a value in an invalid type, 159 /// promote it to compute the value into a larger type. The produced value 160 /// will have the correct bits for the low portion of the register, but no 161 /// guarantee is made about the top bits: it may be zero, sign-extended, or 162 /// garbage. 163 SDOperand PromoteOp(SDOperand O); 164 165 /// ExpandOp - Expand the specified SDOperand into its two component pieces 166 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 167 /// the LegalizeNodes map is filled in for any results that are not expanded, 168 /// the ExpandedNodes map is filled in for any results that are expanded, and 169 /// the Lo/Hi values are returned. This applies to integer types and Vector 170 /// types. 171 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 172 173 /// SplitVectorOp - Given an operand of vector type, break it down into 174 /// two smaller values. 175 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 176 177 /// ScalarizeVectorOp - Given an operand of single-element vector type 178 /// (e.g. v1f32), convert it into the equivalent operation that returns a 179 /// scalar (e.g. f32) value. 180 SDOperand ScalarizeVectorOp(SDOperand O); 181 182 /// isShuffleLegal - Return true if a vector shuffle is legal with the 183 /// specified mask and type. Targets can specify exactly which masks they 184 /// support and the code generator is tasked with not creating illegal masks. 185 /// 186 /// Note that this will also return true for shuffles that are promoted to a 187 /// different type. 188 /// 189 /// If this is a legal shuffle, this method returns the (possibly promoted) 190 /// build_vector Mask. If it's not a legal shuffle, it returns null. 191 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 192 193 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 194 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 195 196 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 197 198 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 199 SDOperand &Hi); 200 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 201 SDOperand Source); 202 203 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT, 204 MVT::ValueType DestVT); 205 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 206 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 207 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 208 SDOperand LegalOp, 209 MVT::ValueType DestVT); 210 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 211 bool isSigned); 212 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 213 bool isSigned); 214 215 SDOperand ExpandBSWAP(SDOperand Op); 216 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 217 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 218 SDOperand &Lo, SDOperand &Hi); 219 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 220 SDOperand &Lo, SDOperand &Hi); 221 222 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 223 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 224}; 225} 226 227/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 228/// specified mask and type. Targets can specify exactly which masks they 229/// support and the code generator is tasked with not creating illegal masks. 230/// 231/// Note that this will also return true for shuffles that are promoted to a 232/// different type. 233SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 234 SDOperand Mask) const { 235 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 236 default: return 0; 237 case TargetLowering::Legal: 238 case TargetLowering::Custom: 239 break; 240 case TargetLowering::Promote: { 241 // If this is promoted to a different type, convert the shuffle mask and 242 // ask if it is legal in the promoted type! 243 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 244 245 // If we changed # elements, change the shuffle mask. 246 unsigned NumEltsGrowth = 247 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 248 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 249 if (NumEltsGrowth > 1) { 250 // Renumber the elements. 251 SmallVector<SDOperand, 8> Ops; 252 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 253 SDOperand InOp = Mask.getOperand(i); 254 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 255 if (InOp.getOpcode() == ISD::UNDEF) 256 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 257 else { 258 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 259 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 260 } 261 } 262 } 263 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 264 } 265 VT = NVT; 266 break; 267 } 268 } 269 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 270} 271 272SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 273 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 274 ValueTypeActions(TLI.getValueTypeActions()) { 275 assert(MVT::LAST_VALUETYPE <= 32 && 276 "Too many value types for ValueTypeActions to hold!"); 277} 278 279/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 280/// contains all of a nodes operands before it contains the node. 281static void ComputeTopDownOrdering(SelectionDAG &DAG, 282 SmallVector<SDNode*, 64> &Order) { 283 284 DenseMap<SDNode*, unsigned> Visited; 285 std::vector<SDNode*> Worklist; 286 Worklist.reserve(128); 287 288 // Compute ordering from all of the leaves in the graphs, those (like the 289 // entry node) that have no operands. 290 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 291 E = DAG.allnodes_end(); I != E; ++I) { 292 if (I->getNumOperands() == 0) { 293 Visited[I] = 0 - 1U; 294 Worklist.push_back(I); 295 } 296 } 297 298 while (!Worklist.empty()) { 299 SDNode *N = Worklist.back(); 300 Worklist.pop_back(); 301 302 if (++Visited[N] != N->getNumOperands()) 303 continue; // Haven't visited all operands yet 304 305 Order.push_back(N); 306 307 // Now that we have N in, add anything that uses it if all of their operands 308 // are now done. 309 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 310 UI != E; ++UI) 311 Worklist.push_back(UI->getUser()); 312 } 313 314 assert(Order.size() == Visited.size() && 315 Order.size() == 316 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 317 "Error: DAG is cyclic!"); 318} 319 320 321void SelectionDAGLegalize::LegalizeDAG() { 322 LastCALLSEQ_END = DAG.getEntryNode(); 323 IsLegalizingCall = false; 324 325 // The legalize process is inherently a bottom-up recursive process (users 326 // legalize their uses before themselves). Given infinite stack space, we 327 // could just start legalizing on the root and traverse the whole graph. In 328 // practice however, this causes us to run out of stack space on large basic 329 // blocks. To avoid this problem, compute an ordering of the nodes where each 330 // node is only legalized after all of its operands are legalized. 331 SmallVector<SDNode*, 64> Order; 332 ComputeTopDownOrdering(DAG, Order); 333 334 for (unsigned i = 0, e = Order.size(); i != e; ++i) 335 HandleOp(SDOperand(Order[i], 0)); 336 337 // Finally, it's possible the root changed. Get the new root. 338 SDOperand OldRoot = DAG.getRoot(); 339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 340 DAG.setRoot(LegalizedNodes[OldRoot]); 341 342 ExpandedNodes.clear(); 343 LegalizedNodes.clear(); 344 PromotedNodes.clear(); 345 SplitNodes.clear(); 346 ScalarizedNodes.clear(); 347 348 // Remove dead nodes now. 349 DAG.RemoveDeadNodes(); 350} 351 352 353/// FindCallEndFromCallStart - Given a chained node that is part of a call 354/// sequence, find the CALLSEQ_END node that terminates the call sequence. 355static SDNode *FindCallEndFromCallStart(SDNode *Node) { 356 if (Node->getOpcode() == ISD::CALLSEQ_END) 357 return Node; 358 if (Node->use_empty()) 359 return 0; // No CallSeqEnd 360 361 // The chain is usually at the end. 362 SDOperand TheChain(Node, Node->getNumValues()-1); 363 if (TheChain.getValueType() != MVT::Other) { 364 // Sometimes it's at the beginning. 365 TheChain = SDOperand(Node, 0); 366 if (TheChain.getValueType() != MVT::Other) { 367 // Otherwise, hunt for it. 368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 369 if (Node->getValueType(i) == MVT::Other) { 370 TheChain = SDOperand(Node, i); 371 break; 372 } 373 374 // Otherwise, we walked into a node without a chain. 375 if (TheChain.getValueType() != MVT::Other) 376 return 0; 377 } 378 } 379 380 for (SDNode::use_iterator UI = Node->use_begin(), 381 E = Node->use_end(); UI != E; ++UI) { 382 383 // Make sure to only follow users of our token chain. 384 SDNode *User = UI->getUser(); 385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 386 if (User->getOperand(i) == TheChain) 387 if (SDNode *Result = FindCallEndFromCallStart(User)) 388 return Result; 389 } 390 return 0; 391} 392 393/// FindCallStartFromCallEnd - Given a chained node that is part of a call 394/// sequence, find the CALLSEQ_START node that initiates the call sequence. 395static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 396 assert(Node && "Didn't find callseq_start for a call??"); 397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 398 399 assert(Node->getOperand(0).getValueType() == MVT::Other && 400 "Node doesn't have a token chain argument!"); 401 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 402} 403 404/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 405/// see if any uses can reach Dest. If no dest operands can get to dest, 406/// legalize them, legalize ourself, and return false, otherwise, return true. 407/// 408/// Keep track of the nodes we fine that actually do lead to Dest in 409/// NodesLeadingTo. This avoids retraversing them exponential number of times. 410/// 411bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 413 if (N == Dest) return true; // N certainly leads to Dest :) 414 415 // If we've already processed this node and it does lead to Dest, there is no 416 // need to reprocess it. 417 if (NodesLeadingTo.count(N)) return true; 418 419 // If the first result of this node has been already legalized, then it cannot 420 // reach N. 421 switch (getTypeAction(N->getValueType(0))) { 422 case Legal: 423 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 424 break; 425 case Promote: 426 if (PromotedNodes.count(SDOperand(N, 0))) return false; 427 break; 428 case Expand: 429 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 430 break; 431 } 432 433 // Okay, this node has not already been legalized. Check and legalize all 434 // operands. If none lead to Dest, then we can legalize this node. 435 bool OperandsLeadToDest = false; 436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 437 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 439 440 if (OperandsLeadToDest) { 441 NodesLeadingTo.insert(N); 442 return true; 443 } 444 445 // Okay, this node looks safe, legalize it and return false. 446 HandleOp(SDOperand(N, 0)); 447 return false; 448} 449 450/// HandleOp - Legalize, Promote, or Expand the specified operand as 451/// appropriate for its type. 452void SelectionDAGLegalize::HandleOp(SDOperand Op) { 453 MVT::ValueType VT = Op.getValueType(); 454 switch (getTypeAction(VT)) { 455 default: assert(0 && "Bad type action!"); 456 case Legal: (void)LegalizeOp(Op); break; 457 case Promote: (void)PromoteOp(Op); break; 458 case Expand: 459 if (!MVT::isVector(VT)) { 460 // If this is an illegal scalar, expand it into its two component 461 // pieces. 462 SDOperand X, Y; 463 if (Op.getOpcode() == ISD::TargetConstant) 464 break; // Allow illegal target nodes. 465 ExpandOp(Op, X, Y); 466 } else if (MVT::getVectorNumElements(VT) == 1) { 467 // If this is an illegal single element vector, convert it to a 468 // scalar operation. 469 (void)ScalarizeVectorOp(Op); 470 } else { 471 // Otherwise, this is an illegal multiple element vector. 472 // Split it in half and legalize both parts. 473 SDOperand X, Y; 474 SplitVectorOp(Op, X, Y); 475 } 476 break; 477 } 478} 479 480/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 481/// a load from the constant pool. 482static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 483 SelectionDAG &DAG, TargetLowering &TLI) { 484 bool Extend = false; 485 486 // If a FP immediate is precise when represented as a float and if the 487 // target can do an extending load from float to double, we put it into 488 // the constant pool as a float, even if it's is statically typed as a 489 // double. This shrinks FP constants and canonicalizes them for targets where 490 // an FP extending load is the same cost as a normal load (such as on the x87 491 // fp stack or PPC FP unit). 492 MVT::ValueType VT = CFP->getValueType(0); 493 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT), 494 CFP->getValueAPF()); 495 if (!UseCP) { 496 if (VT!=MVT::f64 && VT!=MVT::f32) 497 assert(0 && "Invalid type expansion"); 498 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(), 499 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 500 } 501 502 MVT::ValueType OrigVT = VT; 503 MVT::ValueType SVT = VT; 504 while (SVT != MVT::f32) { 505 SVT = (unsigned)SVT - 1; 506 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 507 // Only do this if the target has a native EXTLOAD instruction from 508 // smaller type. 509 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && 510 TLI.ShouldShrinkFPConstant(OrigVT)) { 511 const Type *SType = MVT::getTypeForValueType(SVT); 512 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 513 VT = SVT; 514 Extend = true; 515 } 516 } 517 518 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 519 if (Extend) 520 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), 521 CPIdx, PseudoSourceValue::getConstantPool(), 522 0, VT); 523 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 524 PseudoSourceValue::getConstantPool(), 0); 525} 526 527 528/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 529/// operations. 530static 531SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 532 SelectionDAG &DAG, TargetLowering &TLI) { 533 MVT::ValueType VT = Node->getValueType(0); 534 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 535 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 536 "fcopysign expansion only supported for f32 and f64"); 537 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 538 539 // First get the sign bit of second operand. 540 SDOperand Mask1 = (SrcVT == MVT::f64) 541 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 542 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 543 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 544 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 545 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 546 // Shift right or sign-extend it if the two operands have different types. 547 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 548 if (SizeDiff > 0) { 549 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 550 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 551 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 552 } else if (SizeDiff < 0) 553 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 554 555 // Clear the sign bit of first operand. 556 SDOperand Mask2 = (VT == MVT::f64) 557 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 558 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 559 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 560 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 561 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 562 563 // Or the value with the sign bit. 564 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 565 return Result; 566} 567 568/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 569static 570SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 571 TargetLowering &TLI) { 572 SDOperand Chain = ST->getChain(); 573 SDOperand Ptr = ST->getBasePtr(); 574 SDOperand Val = ST->getValue(); 575 MVT::ValueType VT = Val.getValueType(); 576 int Alignment = ST->getAlignment(); 577 int SVOffset = ST->getSrcValueOffset(); 578 if (MVT::isFloatingPoint(ST->getMemoryVT()) || 579 MVT::isVector(ST->getMemoryVT())) { 580 // Expand to a bitconvert of the value to the integer type of the 581 // same size, then a (misaligned) int store. 582 MVT::ValueType intVT; 583 if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128) 584 intVT = MVT::i128; 585 else if (MVT::is64BitVector(VT) || VT==MVT::f64) 586 intVT = MVT::i64; 587 else if (VT==MVT::f32) 588 intVT = MVT::i32; 589 else 590 assert(0 && "Unaligned store of unsupported type"); 591 592 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 593 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 594 SVOffset, ST->isVolatile(), Alignment); 595 } 596 assert(MVT::isInteger(ST->getMemoryVT()) && 597 !MVT::isVector(ST->getMemoryVT()) && 598 "Unaligned store of unknown type."); 599 // Get the half-size VT 600 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1; 601 int NumBits = MVT::getSizeInBits(NewStoredVT); 602 int IncrementSize = NumBits / 8; 603 604 // Divide the stored value in two parts. 605 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 606 SDOperand Lo = Val; 607 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 608 609 // Store the two parts 610 SDOperand Store1, Store2; 611 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 612 ST->getSrcValue(), SVOffset, NewStoredVT, 613 ST->isVolatile(), Alignment); 614 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 615 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 616 Alignment = MinAlign(Alignment, IncrementSize); 617 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 618 ST->getSrcValue(), SVOffset + IncrementSize, 619 NewStoredVT, ST->isVolatile(), Alignment); 620 621 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 622} 623 624/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 625static 626SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 627 TargetLowering &TLI) { 628 int SVOffset = LD->getSrcValueOffset(); 629 SDOperand Chain = LD->getChain(); 630 SDOperand Ptr = LD->getBasePtr(); 631 MVT::ValueType VT = LD->getValueType(0); 632 MVT::ValueType LoadedVT = LD->getMemoryVT(); 633 if (MVT::isFloatingPoint(VT) || MVT::isVector(VT)) { 634 // Expand to a (misaligned) integer load of the same size, 635 // then bitconvert to floating point or vector. 636 MVT::ValueType intVT; 637 if (MVT::is128BitVector(LoadedVT) || 638 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128) 639 intVT = MVT::i128; 640 else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64) 641 intVT = MVT::i64; 642 else if (LoadedVT == MVT::f32) 643 intVT = MVT::i32; 644 else 645 assert(0 && "Unaligned load of unsupported type"); 646 647 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 648 SVOffset, LD->isVolatile(), 649 LD->getAlignment()); 650 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 651 if (MVT::isFloatingPoint(VT) && LoadedVT != VT) 652 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 653 654 SDOperand Ops[] = { Result, Chain }; 655 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 656 Ops, 2); 657 } 658 assert(MVT::isInteger(LoadedVT) && !MVT::isVector(LoadedVT) && 659 "Unaligned load of unsupported type."); 660 661 // Compute the new VT that is half the size of the old one. This is an 662 // integer MVT. 663 unsigned NumBits = MVT::getSizeInBits(LoadedVT); 664 MVT::ValueType NewLoadedVT; 665 NewLoadedVT = MVT::getIntegerType(NumBits/2); 666 NumBits >>= 1; 667 668 unsigned Alignment = LD->getAlignment(); 669 unsigned IncrementSize = NumBits / 8; 670 ISD::LoadExtType HiExtType = LD->getExtensionType(); 671 672 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 673 if (HiExtType == ISD::NON_EXTLOAD) 674 HiExtType = ISD::ZEXTLOAD; 675 676 // Load the value in two parts 677 SDOperand Lo, Hi; 678 if (TLI.isLittleEndian()) { 679 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 680 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 681 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 682 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 683 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 684 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 685 MinAlign(Alignment, IncrementSize)); 686 } else { 687 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 688 NewLoadedVT,LD->isVolatile(), Alignment); 689 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 690 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 691 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 692 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 693 MinAlign(Alignment, IncrementSize)); 694 } 695 696 // aggregate the two parts 697 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 698 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 699 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 700 701 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 702 Hi.getValue(1)); 703 704 SDOperand Ops[] = { Result, TF }; 705 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 706} 707 708/// UnrollVectorOp - We know that the given vector has a legal type, however 709/// the operation it performs is not legal and is an operation that we have 710/// no way of lowering. "Unroll" the vector, splitting out the scalars and 711/// operating on each element individually. 712SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 713 MVT::ValueType VT = Op.getValueType(); 714 assert(isTypeLegal(VT) && 715 "Caller should expand or promote operands that are not legal!"); 716 assert(Op.Val->getNumValues() == 1 && 717 "Can't unroll a vector with multiple results!"); 718 unsigned NE = MVT::getVectorNumElements(VT); 719 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 720 721 SmallVector<SDOperand, 8> Scalars; 722 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 723 for (unsigned i = 0; i != NE; ++i) { 724 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 725 SDOperand Operand = Op.getOperand(j); 726 MVT::ValueType OperandVT = Operand.getValueType(); 727 if (MVT::isVector(OperandVT)) { 728 // A vector operand; extract a single element. 729 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT); 730 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 731 OperandEltVT, 732 Operand, 733 DAG.getConstant(i, MVT::i32)); 734 } else { 735 // A scalar operand; just use it as is. 736 Operands[j] = Operand; 737 } 738 } 739 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 740 &Operands[0], Operands.size())); 741 } 742 743 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 744} 745 746/// GetFPLibCall - Return the right libcall for the given floating point type. 747static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT, 748 RTLIB::Libcall Call_F32, 749 RTLIB::Libcall Call_F64, 750 RTLIB::Libcall Call_F80, 751 RTLIB::Libcall Call_PPCF128) { 752 return 753 VT == MVT::f32 ? Call_F32 : 754 VT == MVT::f64 ? Call_F64 : 755 VT == MVT::f80 ? Call_F80 : 756 VT == MVT::ppcf128 ? Call_PPCF128 : 757 RTLIB::UNKNOWN_LIBCALL; 758} 759 760/// LegalizeOp - We know that the specified value has a legal type, and 761/// that its operands are legal. Now ensure that the operation itself 762/// is legal, recursively ensuring that the operands' operations remain 763/// legal. 764SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 765 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 766 return Op; 767 768 assert(isTypeLegal(Op.getValueType()) && 769 "Caller should expand or promote operands that are not legal!"); 770 SDNode *Node = Op.Val; 771 772 // If this operation defines any values that cannot be represented in a 773 // register on this target, make sure to expand or promote them. 774 if (Node->getNumValues() > 1) { 775 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 776 if (getTypeAction(Node->getValueType(i)) != Legal) { 777 HandleOp(Op.getValue(i)); 778 assert(LegalizedNodes.count(Op) && 779 "Handling didn't add legal operands!"); 780 return LegalizedNodes[Op]; 781 } 782 } 783 784 // Note that LegalizeOp may be reentered even from single-use nodes, which 785 // means that we always must cache transformed nodes. 786 DenseMap<SDOperandImpl, SDOperand>::iterator I = LegalizedNodes.find(Op); 787 if (I != LegalizedNodes.end()) return I->second; 788 789 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 790 SDOperand Result = Op; 791 bool isCustom = false; 792 793 switch (Node->getOpcode()) { 794 case ISD::FrameIndex: 795 case ISD::EntryToken: 796 case ISD::Register: 797 case ISD::BasicBlock: 798 case ISD::TargetFrameIndex: 799 case ISD::TargetJumpTable: 800 case ISD::TargetConstant: 801 case ISD::TargetConstantFP: 802 case ISD::TargetConstantPool: 803 case ISD::TargetGlobalAddress: 804 case ISD::TargetGlobalTLSAddress: 805 case ISD::TargetExternalSymbol: 806 case ISD::VALUETYPE: 807 case ISD::SRCVALUE: 808 case ISD::MEMOPERAND: 809 case ISD::STRING: 810 case ISD::CONDCODE: 811 case ISD::ARG_FLAGS: 812 // Primitives must all be legal. 813 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 814 "This must be legal!"); 815 break; 816 default: 817 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 818 // If this is a target node, legalize it by legalizing the operands then 819 // passing it through. 820 SmallVector<SDOperand, 8> Ops; 821 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 822 Ops.push_back(LegalizeOp(Node->getOperand(i))); 823 824 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 825 826 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 827 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 828 return Result.getValue(Op.ResNo); 829 } 830 // Otherwise this is an unhandled builtin node. splat. 831#ifndef NDEBUG 832 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 833#endif 834 assert(0 && "Do not know how to legalize this operator!"); 835 abort(); 836 case ISD::GLOBAL_OFFSET_TABLE: 837 case ISD::GlobalAddress: 838 case ISD::GlobalTLSAddress: 839 case ISD::ExternalSymbol: 840 case ISD::ConstantPool: 841 case ISD::JumpTable: // Nothing to do. 842 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 843 default: assert(0 && "This action is not supported yet!"); 844 case TargetLowering::Custom: 845 Tmp1 = TLI.LowerOperation(Op, DAG); 846 if (Tmp1.Val) Result = Tmp1; 847 // FALLTHROUGH if the target doesn't want to lower this op after all. 848 case TargetLowering::Legal: 849 break; 850 } 851 break; 852 case ISD::FRAMEADDR: 853 case ISD::RETURNADDR: 854 // The only option for these nodes is to custom lower them. If the target 855 // does not custom lower them, then return zero. 856 Tmp1 = TLI.LowerOperation(Op, DAG); 857 if (Tmp1.Val) 858 Result = Tmp1; 859 else 860 Result = DAG.getConstant(0, TLI.getPointerTy()); 861 break; 862 case ISD::FRAME_TO_ARGS_OFFSET: { 863 MVT::ValueType VT = Node->getValueType(0); 864 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 865 default: assert(0 && "This action is not supported yet!"); 866 case TargetLowering::Custom: 867 Result = TLI.LowerOperation(Op, DAG); 868 if (Result.Val) break; 869 // Fall Thru 870 case TargetLowering::Legal: 871 Result = DAG.getConstant(0, VT); 872 break; 873 } 874 } 875 break; 876 case ISD::EXCEPTIONADDR: { 877 Tmp1 = LegalizeOp(Node->getOperand(0)); 878 MVT::ValueType VT = Node->getValueType(0); 879 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 880 default: assert(0 && "This action is not supported yet!"); 881 case TargetLowering::Expand: { 882 unsigned Reg = TLI.getExceptionAddressRegister(); 883 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 884 } 885 break; 886 case TargetLowering::Custom: 887 Result = TLI.LowerOperation(Op, DAG); 888 if (Result.Val) break; 889 // Fall Thru 890 case TargetLowering::Legal: { 891 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 892 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 893 Ops, 2); 894 break; 895 } 896 } 897 } 898 if (Result.Val->getNumValues() == 1) break; 899 900 assert(Result.Val->getNumValues() == 2 && 901 "Cannot return more than two values!"); 902 903 // Since we produced two values, make sure to remember that we 904 // legalized both of them. 905 Tmp1 = LegalizeOp(Result); 906 Tmp2 = LegalizeOp(Result.getValue(1)); 907 AddLegalizedOperand(Op.getValue(0), Tmp1); 908 AddLegalizedOperand(Op.getValue(1), Tmp2); 909 return Op.ResNo ? Tmp2 : Tmp1; 910 case ISD::EHSELECTION: { 911 Tmp1 = LegalizeOp(Node->getOperand(0)); 912 Tmp2 = LegalizeOp(Node->getOperand(1)); 913 MVT::ValueType VT = Node->getValueType(0); 914 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 915 default: assert(0 && "This action is not supported yet!"); 916 case TargetLowering::Expand: { 917 unsigned Reg = TLI.getExceptionSelectorRegister(); 918 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 919 } 920 break; 921 case TargetLowering::Custom: 922 Result = TLI.LowerOperation(Op, DAG); 923 if (Result.Val) break; 924 // Fall Thru 925 case TargetLowering::Legal: { 926 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 927 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 928 Ops, 2); 929 break; 930 } 931 } 932 } 933 if (Result.Val->getNumValues() == 1) break; 934 935 assert(Result.Val->getNumValues() == 2 && 936 "Cannot return more than two values!"); 937 938 // Since we produced two values, make sure to remember that we 939 // legalized both of them. 940 Tmp1 = LegalizeOp(Result); 941 Tmp2 = LegalizeOp(Result.getValue(1)); 942 AddLegalizedOperand(Op.getValue(0), Tmp1); 943 AddLegalizedOperand(Op.getValue(1), Tmp2); 944 return Op.ResNo ? Tmp2 : Tmp1; 945 case ISD::EH_RETURN: { 946 MVT::ValueType VT = Node->getValueType(0); 947 // The only "good" option for this node is to custom lower it. 948 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 949 default: assert(0 && "This action is not supported at all!"); 950 case TargetLowering::Custom: 951 Result = TLI.LowerOperation(Op, DAG); 952 if (Result.Val) break; 953 // Fall Thru 954 case TargetLowering::Legal: 955 // Target does not know, how to lower this, lower to noop 956 Result = LegalizeOp(Node->getOperand(0)); 957 break; 958 } 959 } 960 break; 961 case ISD::AssertSext: 962 case ISD::AssertZext: 963 Tmp1 = LegalizeOp(Node->getOperand(0)); 964 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 965 break; 966 case ISD::MERGE_VALUES: 967 // Legalize eliminates MERGE_VALUES nodes. 968 Result = Node->getOperand(Op.ResNo); 969 break; 970 case ISD::CopyFromReg: 971 Tmp1 = LegalizeOp(Node->getOperand(0)); 972 Result = Op.getValue(0); 973 if (Node->getNumValues() == 2) { 974 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 975 } else { 976 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 977 if (Node->getNumOperands() == 3) { 978 Tmp2 = LegalizeOp(Node->getOperand(2)); 979 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 980 } else { 981 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 982 } 983 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 984 } 985 // Since CopyFromReg produces two values, make sure to remember that we 986 // legalized both of them. 987 AddLegalizedOperand(Op.getValue(0), Result); 988 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 989 return Result.getValue(Op.ResNo); 990 case ISD::UNDEF: { 991 MVT::ValueType VT = Op.getValueType(); 992 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 993 default: assert(0 && "This action is not supported yet!"); 994 case TargetLowering::Expand: 995 if (MVT::isInteger(VT)) 996 Result = DAG.getConstant(0, VT); 997 else if (MVT::isFloatingPoint(VT)) 998 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)), 999 VT); 1000 else 1001 assert(0 && "Unknown value type!"); 1002 break; 1003 case TargetLowering::Legal: 1004 break; 1005 } 1006 break; 1007 } 1008 1009 case ISD::INTRINSIC_W_CHAIN: 1010 case ISD::INTRINSIC_WO_CHAIN: 1011 case ISD::INTRINSIC_VOID: { 1012 SmallVector<SDOperand, 8> Ops; 1013 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1014 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1015 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1016 1017 // Allow the target to custom lower its intrinsics if it wants to. 1018 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1019 TargetLowering::Custom) { 1020 Tmp3 = TLI.LowerOperation(Result, DAG); 1021 if (Tmp3.Val) Result = Tmp3; 1022 } 1023 1024 if (Result.Val->getNumValues() == 1) break; 1025 1026 // Must have return value and chain result. 1027 assert(Result.Val->getNumValues() == 2 && 1028 "Cannot return more than two values!"); 1029 1030 // Since loads produce two values, make sure to remember that we 1031 // legalized both of them. 1032 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1033 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1034 return Result.getValue(Op.ResNo); 1035 } 1036 1037 case ISD::LOCATION: 1038 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 1039 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1040 1041 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 1042 case TargetLowering::Promote: 1043 default: assert(0 && "This action is not supported yet!"); 1044 case TargetLowering::Expand: { 1045 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1046 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1047 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 1048 1049 if (MMI && (useDEBUG_LOC || useLABEL)) { 1050 const std::string &FName = 1051 cast<StringSDNode>(Node->getOperand(3))->getValue(); 1052 const std::string &DirName = 1053 cast<StringSDNode>(Node->getOperand(4))->getValue(); 1054 unsigned SrcFile = MMI->RecordSource(DirName, FName); 1055 1056 SmallVector<SDOperand, 8> Ops; 1057 Ops.push_back(Tmp1); // chain 1058 SDOperand LineOp = Node->getOperand(1); 1059 SDOperand ColOp = Node->getOperand(2); 1060 1061 if (useDEBUG_LOC) { 1062 Ops.push_back(LineOp); // line # 1063 Ops.push_back(ColOp); // col # 1064 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1065 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1066 } else { 1067 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 1068 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 1069 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 1070 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 1071 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label 1072 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size()); 1073 } 1074 } else { 1075 Result = Tmp1; // chain 1076 } 1077 break; 1078 } 1079 case TargetLowering::Legal: 1080 if (Tmp1 != Node->getOperand(0) || 1081 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1082 SmallVector<SDOperand, 8> Ops; 1083 Ops.push_back(Tmp1); 1084 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1085 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1086 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1087 } else { 1088 // Otherwise promote them. 1089 Ops.push_back(PromoteOp(Node->getOperand(1))); 1090 Ops.push_back(PromoteOp(Node->getOperand(2))); 1091 } 1092 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1093 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1094 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1095 } 1096 break; 1097 } 1098 break; 1099 1100 case ISD::DECLARE: 1101 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1102 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1103 default: assert(0 && "This action is not supported yet!"); 1104 case TargetLowering::Legal: 1105 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1106 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1107 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1108 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1109 break; 1110 case TargetLowering::Expand: 1111 Result = LegalizeOp(Node->getOperand(0)); 1112 break; 1113 } 1114 break; 1115 1116 case ISD::DEBUG_LOC: 1117 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1118 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1119 default: assert(0 && "This action is not supported yet!"); 1120 case TargetLowering::Legal: 1121 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1122 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1123 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1124 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1125 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1126 break; 1127 } 1128 break; 1129 1130 case ISD::LABEL: 1131 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!"); 1132 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1133 default: assert(0 && "This action is not supported yet!"); 1134 case TargetLowering::Legal: 1135 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1136 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1137 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand. 1138 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1139 break; 1140 case TargetLowering::Expand: 1141 Result = LegalizeOp(Node->getOperand(0)); 1142 break; 1143 } 1144 break; 1145 1146 case ISD::PREFETCH: 1147 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1148 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1149 default: assert(0 && "This action is not supported yet!"); 1150 case TargetLowering::Legal: 1151 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1152 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1153 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1154 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1155 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1156 break; 1157 case TargetLowering::Expand: 1158 // It's a noop. 1159 Result = LegalizeOp(Node->getOperand(0)); 1160 break; 1161 } 1162 break; 1163 1164 case ISD::MEMBARRIER: { 1165 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1166 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1167 default: assert(0 && "This action is not supported yet!"); 1168 case TargetLowering::Legal: { 1169 SDOperand Ops[6]; 1170 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1171 for (int x = 1; x < 6; ++x) { 1172 Ops[x] = Node->getOperand(x); 1173 if (!isTypeLegal(Ops[x].getValueType())) 1174 Ops[x] = PromoteOp(Ops[x]); 1175 } 1176 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1177 break; 1178 } 1179 case TargetLowering::Expand: 1180 //There is no libgcc call for this op 1181 Result = Node->getOperand(0); // Noop 1182 break; 1183 } 1184 break; 1185 } 1186 1187 case ISD::ATOMIC_LCS: 1188 case ISD::ATOMIC_LAS: 1189 case ISD::ATOMIC_SWAP: { 1190 assert(((Node->getNumOperands() == 4 && Node->getOpcode() == ISD::ATOMIC_LCS) || 1191 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_LAS) || 1192 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_SWAP)) && 1193 "Invalid Atomic node!"); 1194 int num = Node->getOpcode() == ISD::ATOMIC_LCS ? 4 : 3; 1195 SDOperand Ops[4]; 1196 for (int x = 0; x < num; ++x) 1197 Ops[x] = LegalizeOp(Node->getOperand(x)); 1198 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num); 1199 1200 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1201 default: assert(0 && "This action is not supported yet!"); 1202 case TargetLowering::Custom: 1203 Result = TLI.LowerOperation(Result, DAG); 1204 break; 1205 case TargetLowering::Legal: 1206 break; 1207 } 1208 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1209 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1210 return Result.getValue(Op.ResNo); 1211 } 1212 1213 case ISD::Constant: { 1214 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1215 unsigned opAction = 1216 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1217 1218 // We know we don't need to expand constants here, constants only have one 1219 // value and we check that it is fine above. 1220 1221 if (opAction == TargetLowering::Custom) { 1222 Tmp1 = TLI.LowerOperation(Result, DAG); 1223 if (Tmp1.Val) 1224 Result = Tmp1; 1225 } 1226 break; 1227 } 1228 case ISD::ConstantFP: { 1229 // Spill FP immediates to the constant pool if the target cannot directly 1230 // codegen them. Targets often have some immediate values that can be 1231 // efficiently generated into an FP register without a load. We explicitly 1232 // leave these constants as ConstantFP nodes for the target to deal with. 1233 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1234 1235 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1236 default: assert(0 && "This action is not supported yet!"); 1237 case TargetLowering::Legal: 1238 break; 1239 case TargetLowering::Custom: 1240 Tmp3 = TLI.LowerOperation(Result, DAG); 1241 if (Tmp3.Val) { 1242 Result = Tmp3; 1243 break; 1244 } 1245 // FALLTHROUGH 1246 case TargetLowering::Expand: { 1247 // Check to see if this FP immediate is already legal. 1248 bool isLegal = false; 1249 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1250 E = TLI.legal_fpimm_end(); I != E; ++I) { 1251 if (CFP->isExactlyValue(*I)) { 1252 isLegal = true; 1253 break; 1254 } 1255 } 1256 // If this is a legal constant, turn it into a TargetConstantFP node. 1257 if (isLegal) 1258 break; 1259 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1260 } 1261 } 1262 break; 1263 } 1264 case ISD::TokenFactor: 1265 if (Node->getNumOperands() == 2) { 1266 Tmp1 = LegalizeOp(Node->getOperand(0)); 1267 Tmp2 = LegalizeOp(Node->getOperand(1)); 1268 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1269 } else if (Node->getNumOperands() == 3) { 1270 Tmp1 = LegalizeOp(Node->getOperand(0)); 1271 Tmp2 = LegalizeOp(Node->getOperand(1)); 1272 Tmp3 = LegalizeOp(Node->getOperand(2)); 1273 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1274 } else { 1275 SmallVector<SDOperand, 8> Ops; 1276 // Legalize the operands. 1277 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1278 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1279 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1280 } 1281 break; 1282 1283 case ISD::FORMAL_ARGUMENTS: 1284 case ISD::CALL: 1285 // The only option for this is to custom lower it. 1286 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1287 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1288 // A call within a calling sequence must be legalized to something 1289 // other than the normal CALLSEQ_END. Violating this gets Legalize 1290 // into an infinite loop. 1291 assert ((!IsLegalizingCall || 1292 Node->getOpcode() != ISD::CALL || 1293 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) && 1294 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1295 1296 // The number of incoming and outgoing values should match; unless the final 1297 // outgoing value is a flag. 1298 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1299 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1300 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1301 MVT::Flag)) && 1302 "Lowering call/formal_arguments produced unexpected # results!"); 1303 1304 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1305 // remember that we legalized all of them, so it doesn't get relegalized. 1306 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1307 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1308 continue; 1309 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1310 if (Op.ResNo == i) 1311 Tmp2 = Tmp1; 1312 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1313 } 1314 return Tmp2; 1315 case ISD::EXTRACT_SUBREG: { 1316 Tmp1 = LegalizeOp(Node->getOperand(0)); 1317 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1318 assert(idx && "Operand must be a constant"); 1319 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1320 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1321 } 1322 break; 1323 case ISD::INSERT_SUBREG: { 1324 Tmp1 = LegalizeOp(Node->getOperand(0)); 1325 Tmp2 = LegalizeOp(Node->getOperand(1)); 1326 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1327 assert(idx && "Operand must be a constant"); 1328 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1329 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1330 } 1331 break; 1332 case ISD::BUILD_VECTOR: 1333 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1334 default: assert(0 && "This action is not supported yet!"); 1335 case TargetLowering::Custom: 1336 Tmp3 = TLI.LowerOperation(Result, DAG); 1337 if (Tmp3.Val) { 1338 Result = Tmp3; 1339 break; 1340 } 1341 // FALLTHROUGH 1342 case TargetLowering::Expand: 1343 Result = ExpandBUILD_VECTOR(Result.Val); 1344 break; 1345 } 1346 break; 1347 case ISD::INSERT_VECTOR_ELT: 1348 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1349 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1350 1351 // The type of the value to insert may not be legal, even though the vector 1352 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1353 // here. 1354 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1355 default: assert(0 && "Cannot expand insert element operand"); 1356 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1357 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1358 } 1359 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1360 1361 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1362 Node->getValueType(0))) { 1363 default: assert(0 && "This action is not supported yet!"); 1364 case TargetLowering::Legal: 1365 break; 1366 case TargetLowering::Custom: 1367 Tmp4 = TLI.LowerOperation(Result, DAG); 1368 if (Tmp4.Val) { 1369 Result = Tmp4; 1370 break; 1371 } 1372 // FALLTHROUGH 1373 case TargetLowering::Expand: { 1374 // If the insert index is a constant, codegen this as a scalar_to_vector, 1375 // then a shuffle that inserts it into the right position in the vector. 1376 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1377 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1378 // match the element type of the vector being created. 1379 if (Tmp2.getValueType() == 1380 MVT::getVectorElementType(Op.getValueType())) { 1381 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1382 Tmp1.getValueType(), Tmp2); 1383 1384 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1385 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1386 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1387 1388 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1389 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1390 // elt 0 of the RHS. 1391 SmallVector<SDOperand, 8> ShufOps; 1392 for (unsigned i = 0; i != NumElts; ++i) { 1393 if (i != InsertPos->getValue()) 1394 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1395 else 1396 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1397 } 1398 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1399 &ShufOps[0], ShufOps.size()); 1400 1401 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1402 Tmp1, ScVec, ShufMask); 1403 Result = LegalizeOp(Result); 1404 break; 1405 } 1406 } 1407 1408 // If the target doesn't support this, we have to spill the input vector 1409 // to a temporary stack slot, update the element, then reload it. This is 1410 // badness. We could also load the value into a vector register (either 1411 // with a "move to register" or "extload into register" instruction, then 1412 // permute it into place, if the idx is a constant and if the idx is 1413 // supported by the target. 1414 MVT::ValueType VT = Tmp1.getValueType(); 1415 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1416 MVT::ValueType IdxVT = Tmp3.getValueType(); 1417 MVT::ValueType PtrVT = TLI.getPointerTy(); 1418 SDOperand StackPtr = DAG.CreateStackTemporary(VT); 1419 1420 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val); 1421 int SPFI = StackPtrFI->getIndex(); 1422 1423 // Store the vector. 1424 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, 1425 PseudoSourceValue::getFixedStack(), 1426 SPFI); 1427 1428 // Truncate or zero extend offset to target pointer type. 1429 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1430 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1431 // Add the offset to the index. 1432 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1433 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1434 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1435 // Store the scalar value. 1436 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, 1437 PseudoSourceValue::getFixedStack(), SPFI, EltVT); 1438 // Load the updated vector. 1439 Result = DAG.getLoad(VT, Ch, StackPtr, 1440 PseudoSourceValue::getFixedStack(), SPFI); 1441 break; 1442 } 1443 } 1444 break; 1445 case ISD::SCALAR_TO_VECTOR: 1446 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1447 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1448 break; 1449 } 1450 1451 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1452 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1453 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1454 Node->getValueType(0))) { 1455 default: assert(0 && "This action is not supported yet!"); 1456 case TargetLowering::Legal: 1457 break; 1458 case TargetLowering::Custom: 1459 Tmp3 = TLI.LowerOperation(Result, DAG); 1460 if (Tmp3.Val) { 1461 Result = Tmp3; 1462 break; 1463 } 1464 // FALLTHROUGH 1465 case TargetLowering::Expand: 1466 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1467 break; 1468 } 1469 break; 1470 case ISD::VECTOR_SHUFFLE: 1471 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1472 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1473 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1474 1475 // Allow targets to custom lower the SHUFFLEs they support. 1476 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1477 default: assert(0 && "Unknown operation action!"); 1478 case TargetLowering::Legal: 1479 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1480 "vector shuffle should not be created if not legal!"); 1481 break; 1482 case TargetLowering::Custom: 1483 Tmp3 = TLI.LowerOperation(Result, DAG); 1484 if (Tmp3.Val) { 1485 Result = Tmp3; 1486 break; 1487 } 1488 // FALLTHROUGH 1489 case TargetLowering::Expand: { 1490 MVT::ValueType VT = Node->getValueType(0); 1491 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1492 MVT::ValueType PtrVT = TLI.getPointerTy(); 1493 SDOperand Mask = Node->getOperand(2); 1494 unsigned NumElems = Mask.getNumOperands(); 1495 SmallVector<SDOperand,8> Ops; 1496 for (unsigned i = 0; i != NumElems; ++i) { 1497 SDOperand Arg = Mask.getOperand(i); 1498 if (Arg.getOpcode() == ISD::UNDEF) { 1499 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1500 } else { 1501 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1502 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1503 if (Idx < NumElems) 1504 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1505 DAG.getConstant(Idx, PtrVT))); 1506 else 1507 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1508 DAG.getConstant(Idx - NumElems, PtrVT))); 1509 } 1510 } 1511 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1512 break; 1513 } 1514 case TargetLowering::Promote: { 1515 // Change base type to a different vector type. 1516 MVT::ValueType OVT = Node->getValueType(0); 1517 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1518 1519 // Cast the two input vectors. 1520 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1521 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1522 1523 // Convert the shuffle mask to the right # elements. 1524 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1525 assert(Tmp3.Val && "Shuffle not legal?"); 1526 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1527 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1528 break; 1529 } 1530 } 1531 break; 1532 1533 case ISD::EXTRACT_VECTOR_ELT: 1534 Tmp1 = Node->getOperand(0); 1535 Tmp2 = LegalizeOp(Node->getOperand(1)); 1536 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1537 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1538 break; 1539 1540 case ISD::EXTRACT_SUBVECTOR: 1541 Tmp1 = Node->getOperand(0); 1542 Tmp2 = LegalizeOp(Node->getOperand(1)); 1543 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1544 Result = ExpandEXTRACT_SUBVECTOR(Result); 1545 break; 1546 1547 case ISD::CALLSEQ_START: { 1548 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1549 1550 // Recursively Legalize all of the inputs of the call end that do not lead 1551 // to this call start. This ensures that any libcalls that need be inserted 1552 // are inserted *before* the CALLSEQ_START. 1553 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1554 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1555 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1556 NodesLeadingTo); 1557 } 1558 1559 // Now that we legalized all of the inputs (which may have inserted 1560 // libcalls) create the new CALLSEQ_START node. 1561 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1562 1563 // Merge in the last call, to ensure that this call start after the last 1564 // call ended. 1565 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1566 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1567 Tmp1 = LegalizeOp(Tmp1); 1568 } 1569 1570 // Do not try to legalize the target-specific arguments (#1+). 1571 if (Tmp1 != Node->getOperand(0)) { 1572 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1573 Ops[0] = Tmp1; 1574 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1575 } 1576 1577 // Remember that the CALLSEQ_START is legalized. 1578 AddLegalizedOperand(Op.getValue(0), Result); 1579 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1580 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1581 1582 // Now that the callseq_start and all of the non-call nodes above this call 1583 // sequence have been legalized, legalize the call itself. During this 1584 // process, no libcalls can/will be inserted, guaranteeing that no calls 1585 // can overlap. 1586 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1587 SDOperand InCallSEQ = LastCALLSEQ_END; 1588 // Note that we are selecting this call! 1589 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1590 IsLegalizingCall = true; 1591 1592 // Legalize the call, starting from the CALLSEQ_END. 1593 LegalizeOp(LastCALLSEQ_END); 1594 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1595 return Result; 1596 } 1597 case ISD::CALLSEQ_END: 1598 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1599 // will cause this node to be legalized as well as handling libcalls right. 1600 if (LastCALLSEQ_END.Val != Node) { 1601 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1602 DenseMap<SDOperandImpl, SDOperand>::iterator I = LegalizedNodes.find(Op); 1603 assert(I != LegalizedNodes.end() && 1604 "Legalizing the call start should have legalized this node!"); 1605 return I->second; 1606 } 1607 1608 // Otherwise, the call start has been legalized and everything is going 1609 // according to plan. Just legalize ourselves normally here. 1610 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1611 // Do not try to legalize the target-specific arguments (#1+), except for 1612 // an optional flag input. 1613 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1614 if (Tmp1 != Node->getOperand(0)) { 1615 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1616 Ops[0] = Tmp1; 1617 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1618 } 1619 } else { 1620 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1621 if (Tmp1 != Node->getOperand(0) || 1622 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1623 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1624 Ops[0] = Tmp1; 1625 Ops.back() = Tmp2; 1626 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1627 } 1628 } 1629 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1630 // This finishes up call legalization. 1631 IsLegalizingCall = false; 1632 1633 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1634 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1635 if (Node->getNumValues() == 2) 1636 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1637 return Result.getValue(Op.ResNo); 1638 case ISD::DYNAMIC_STACKALLOC: { 1639 MVT::ValueType VT = Node->getValueType(0); 1640 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1641 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1642 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1643 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1644 1645 Tmp1 = Result.getValue(0); 1646 Tmp2 = Result.getValue(1); 1647 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1648 default: assert(0 && "This action is not supported yet!"); 1649 case TargetLowering::Expand: { 1650 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1651 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1652 " not tell us which reg is the stack pointer!"); 1653 SDOperand Chain = Tmp1.getOperand(0); 1654 1655 // Chain the dynamic stack allocation so that it doesn't modify the stack 1656 // pointer when other instructions are using the stack. 1657 Chain = DAG.getCALLSEQ_START(Chain, 1658 DAG.getConstant(0, TLI.getPointerTy())); 1659 1660 SDOperand Size = Tmp2.getOperand(1); 1661 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1662 Chain = SP.getValue(1); 1663 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1664 unsigned StackAlign = 1665 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1666 if (Align > StackAlign) 1667 SP = DAG.getNode(ISD::AND, VT, SP, 1668 DAG.getConstant(-(uint64_t)Align, VT)); 1669 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1670 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1671 1672 Tmp2 = 1673 DAG.getCALLSEQ_END(Chain, 1674 DAG.getConstant(0, TLI.getPointerTy()), 1675 DAG.getConstant(0, TLI.getPointerTy()), 1676 SDOperand()); 1677 1678 Tmp1 = LegalizeOp(Tmp1); 1679 Tmp2 = LegalizeOp(Tmp2); 1680 break; 1681 } 1682 case TargetLowering::Custom: 1683 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1684 if (Tmp3.Val) { 1685 Tmp1 = LegalizeOp(Tmp3); 1686 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1687 } 1688 break; 1689 case TargetLowering::Legal: 1690 break; 1691 } 1692 // Since this op produce two values, make sure to remember that we 1693 // legalized both of them. 1694 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1695 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1696 return Op.ResNo ? Tmp2 : Tmp1; 1697 } 1698 case ISD::INLINEASM: { 1699 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1700 bool Changed = false; 1701 // Legalize all of the operands of the inline asm, in case they are nodes 1702 // that need to be expanded or something. Note we skip the asm string and 1703 // all of the TargetConstant flags. 1704 SDOperand Op = LegalizeOp(Ops[0]); 1705 Changed = Op != Ops[0]; 1706 Ops[0] = Op; 1707 1708 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1709 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1710 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1711 for (++i; NumVals; ++i, --NumVals) { 1712 SDOperand Op = LegalizeOp(Ops[i]); 1713 if (Op != Ops[i]) { 1714 Changed = true; 1715 Ops[i] = Op; 1716 } 1717 } 1718 } 1719 1720 if (HasInFlag) { 1721 Op = LegalizeOp(Ops.back()); 1722 Changed |= Op != Ops.back(); 1723 Ops.back() = Op; 1724 } 1725 1726 if (Changed) 1727 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1728 1729 // INLINE asm returns a chain and flag, make sure to add both to the map. 1730 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1731 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1732 return Result.getValue(Op.ResNo); 1733 } 1734 case ISD::BR: 1735 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1736 // Ensure that libcalls are emitted before a branch. 1737 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1738 Tmp1 = LegalizeOp(Tmp1); 1739 LastCALLSEQ_END = DAG.getEntryNode(); 1740 1741 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1742 break; 1743 case ISD::BRIND: 1744 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1745 // Ensure that libcalls are emitted before a branch. 1746 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1747 Tmp1 = LegalizeOp(Tmp1); 1748 LastCALLSEQ_END = DAG.getEntryNode(); 1749 1750 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1751 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1752 case Legal: 1753 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1754 break; 1755 } 1756 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1757 break; 1758 case ISD::BR_JT: 1759 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1760 // Ensure that libcalls are emitted before a branch. 1761 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1762 Tmp1 = LegalizeOp(Tmp1); 1763 LastCALLSEQ_END = DAG.getEntryNode(); 1764 1765 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1766 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1767 1768 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1769 default: assert(0 && "This action is not supported yet!"); 1770 case TargetLowering::Legal: break; 1771 case TargetLowering::Custom: 1772 Tmp1 = TLI.LowerOperation(Result, DAG); 1773 if (Tmp1.Val) Result = Tmp1; 1774 break; 1775 case TargetLowering::Expand: { 1776 SDOperand Chain = Result.getOperand(0); 1777 SDOperand Table = Result.getOperand(1); 1778 SDOperand Index = Result.getOperand(2); 1779 1780 MVT::ValueType PTy = TLI.getPointerTy(); 1781 MachineFunction &MF = DAG.getMachineFunction(); 1782 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1783 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1784 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1785 1786 SDOperand LD; 1787 switch (EntrySize) { 1788 default: assert(0 && "Size of jump table not supported yet."); break; 1789 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, 1790 PseudoSourceValue::getJumpTable(), 0); break; 1791 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, 1792 PseudoSourceValue::getJumpTable(), 0); break; 1793 } 1794 1795 Addr = LD; 1796 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1797 // For PIC, the sequence is: 1798 // BRIND(load(Jumptable + index) + RelocBase) 1799 // RelocBase can be JumpTable, GOT or some sort of global base. 1800 if (PTy != MVT::i32) 1801 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1802 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1803 TLI.getPICJumpTableRelocBase(Table, DAG)); 1804 } 1805 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1806 } 1807 } 1808 break; 1809 case ISD::BRCOND: 1810 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1811 // Ensure that libcalls are emitted before a return. 1812 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1813 Tmp1 = LegalizeOp(Tmp1); 1814 LastCALLSEQ_END = DAG.getEntryNode(); 1815 1816 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1817 case Expand: assert(0 && "It's impossible to expand bools"); 1818 case Legal: 1819 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1820 break; 1821 case Promote: { 1822 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1823 1824 // The top bits of the promoted condition are not necessarily zero, ensure 1825 // that the value is properly zero extended. 1826 unsigned BitWidth = Tmp2.getValueSizeInBits(); 1827 if (!DAG.MaskedValueIsZero(Tmp2, 1828 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 1829 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1830 break; 1831 } 1832 } 1833 1834 // Basic block destination (Op#2) is always legal. 1835 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1836 1837 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1838 default: assert(0 && "This action is not supported yet!"); 1839 case TargetLowering::Legal: break; 1840 case TargetLowering::Custom: 1841 Tmp1 = TLI.LowerOperation(Result, DAG); 1842 if (Tmp1.Val) Result = Tmp1; 1843 break; 1844 case TargetLowering::Expand: 1845 // Expand brcond's setcc into its constituent parts and create a BR_CC 1846 // Node. 1847 if (Tmp2.getOpcode() == ISD::SETCC) { 1848 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1849 Tmp2.getOperand(0), Tmp2.getOperand(1), 1850 Node->getOperand(2)); 1851 } else { 1852 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1853 DAG.getCondCode(ISD::SETNE), Tmp2, 1854 DAG.getConstant(0, Tmp2.getValueType()), 1855 Node->getOperand(2)); 1856 } 1857 break; 1858 } 1859 break; 1860 case ISD::BR_CC: 1861 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1862 // Ensure that libcalls are emitted before a branch. 1863 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1864 Tmp1 = LegalizeOp(Tmp1); 1865 Tmp2 = Node->getOperand(2); // LHS 1866 Tmp3 = Node->getOperand(3); // RHS 1867 Tmp4 = Node->getOperand(1); // CC 1868 1869 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1870 LastCALLSEQ_END = DAG.getEntryNode(); 1871 1872 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1873 // the LHS is a legal SETCC itself. In this case, we need to compare 1874 // the result against zero to select between true and false values. 1875 if (Tmp3.Val == 0) { 1876 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1877 Tmp4 = DAG.getCondCode(ISD::SETNE); 1878 } 1879 1880 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1881 Node->getOperand(4)); 1882 1883 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1884 default: assert(0 && "Unexpected action for BR_CC!"); 1885 case TargetLowering::Legal: break; 1886 case TargetLowering::Custom: 1887 Tmp4 = TLI.LowerOperation(Result, DAG); 1888 if (Tmp4.Val) Result = Tmp4; 1889 break; 1890 } 1891 break; 1892 case ISD::LOAD: { 1893 LoadSDNode *LD = cast<LoadSDNode>(Node); 1894 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1895 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1896 1897 ISD::LoadExtType ExtType = LD->getExtensionType(); 1898 if (ExtType == ISD::NON_EXTLOAD) { 1899 MVT::ValueType VT = Node->getValueType(0); 1900 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1901 Tmp3 = Result.getValue(0); 1902 Tmp4 = Result.getValue(1); 1903 1904 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1905 default: assert(0 && "This action is not supported yet!"); 1906 case TargetLowering::Legal: 1907 // If this is an unaligned load and the target doesn't support it, 1908 // expand it. 1909 if (!TLI.allowsUnalignedMemoryAccesses()) { 1910 unsigned ABIAlignment = TLI.getTargetData()-> 1911 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT())); 1912 if (LD->getAlignment() < ABIAlignment){ 1913 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1914 TLI); 1915 Tmp3 = Result.getOperand(0); 1916 Tmp4 = Result.getOperand(1); 1917 Tmp3 = LegalizeOp(Tmp3); 1918 Tmp4 = LegalizeOp(Tmp4); 1919 } 1920 } 1921 break; 1922 case TargetLowering::Custom: 1923 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1924 if (Tmp1.Val) { 1925 Tmp3 = LegalizeOp(Tmp1); 1926 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1927 } 1928 break; 1929 case TargetLowering::Promote: { 1930 // Only promote a load of vector type to another. 1931 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1932 // Change base type to a different vector type. 1933 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1934 1935 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1936 LD->getSrcValueOffset(), 1937 LD->isVolatile(), LD->getAlignment()); 1938 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1939 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1940 break; 1941 } 1942 } 1943 // Since loads produce two values, make sure to remember that we 1944 // legalized both of them. 1945 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1946 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1947 return Op.ResNo ? Tmp4 : Tmp3; 1948 } else { 1949 MVT::ValueType SrcVT = LD->getMemoryVT(); 1950 unsigned SrcWidth = MVT::getSizeInBits(SrcVT); 1951 int SVOffset = LD->getSrcValueOffset(); 1952 unsigned Alignment = LD->getAlignment(); 1953 bool isVolatile = LD->isVolatile(); 1954 1955 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) && 1956 // Some targets pretend to have an i1 loading operation, and actually 1957 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1958 // bits are guaranteed to be zero; it helps the optimizers understand 1959 // that these bits are zero. It is also useful for EXTLOAD, since it 1960 // tells the optimizers that those bits are undefined. It would be 1961 // nice to have an effective generic way of getting these benefits... 1962 // Until such a way is found, don't insist on promoting i1 here. 1963 (SrcVT != MVT::i1 || 1964 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1965 // Promote to a byte-sized load if not loading an integral number of 1966 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1967 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT); 1968 MVT::ValueType NVT = MVT::getIntegerType(NewWidth); 1969 SDOperand Ch; 1970 1971 // The extra bits are guaranteed to be zero, since we stored them that 1972 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1973 1974 ISD::LoadExtType NewExtType = 1975 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1976 1977 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 1978 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1979 NVT, isVolatile, Alignment); 1980 1981 Ch = Result.getValue(1); // The chain. 1982 1983 if (ExtType == ISD::SEXTLOAD) 1984 // Having the top bits zero doesn't help when sign extending. 1985 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1986 Result, DAG.getValueType(SrcVT)); 1987 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1988 // All the top bits are guaranteed to be zero - inform the optimizers. 1989 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 1990 DAG.getValueType(SrcVT)); 1991 1992 Tmp1 = LegalizeOp(Result); 1993 Tmp2 = LegalizeOp(Ch); 1994 } else if (SrcWidth & (SrcWidth - 1)) { 1995 // If not loading a power-of-2 number of bits, expand as two loads. 1996 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) && 1997 "Unsupported extload!"); 1998 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1999 assert(RoundWidth < SrcWidth); 2000 unsigned ExtraWidth = SrcWidth - RoundWidth; 2001 assert(ExtraWidth < RoundWidth); 2002 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2003 "Load size not an integral number of bytes!"); 2004 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth); 2005 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth); 2006 SDOperand Lo, Hi, Ch; 2007 unsigned IncrementSize; 2008 2009 if (TLI.isLittleEndian()) { 2010 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2011 // Load the bottom RoundWidth bits. 2012 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2013 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2014 Alignment); 2015 2016 // Load the remaining ExtraWidth bits. 2017 IncrementSize = RoundWidth / 8; 2018 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2019 DAG.getIntPtrConstant(IncrementSize)); 2020 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2021 LD->getSrcValue(), SVOffset + IncrementSize, 2022 ExtraVT, isVolatile, 2023 MinAlign(Alignment, IncrementSize)); 2024 2025 // Build a factor node to remember that this load is independent of the 2026 // other one. 2027 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2028 Hi.getValue(1)); 2029 2030 // Move the top bits to the right place. 2031 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2032 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2033 2034 // Join the hi and lo parts. 2035 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2036 } else { 2037 // Big endian - avoid unaligned loads. 2038 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2039 // Load the top RoundWidth bits. 2040 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2041 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2042 Alignment); 2043 2044 // Load the remaining ExtraWidth bits. 2045 IncrementSize = RoundWidth / 8; 2046 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2047 DAG.getIntPtrConstant(IncrementSize)); 2048 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2049 LD->getSrcValue(), SVOffset + IncrementSize, 2050 ExtraVT, isVolatile, 2051 MinAlign(Alignment, IncrementSize)); 2052 2053 // Build a factor node to remember that this load is independent of the 2054 // other one. 2055 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2056 Hi.getValue(1)); 2057 2058 // Move the top bits to the right place. 2059 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2060 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2061 2062 // Join the hi and lo parts. 2063 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2064 } 2065 2066 Tmp1 = LegalizeOp(Result); 2067 Tmp2 = LegalizeOp(Ch); 2068 } else { 2069 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 2070 default: assert(0 && "This action is not supported yet!"); 2071 case TargetLowering::Custom: 2072 isCustom = true; 2073 // FALLTHROUGH 2074 case TargetLowering::Legal: 2075 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2076 Tmp1 = Result.getValue(0); 2077 Tmp2 = Result.getValue(1); 2078 2079 if (isCustom) { 2080 Tmp3 = TLI.LowerOperation(Result, DAG); 2081 if (Tmp3.Val) { 2082 Tmp1 = LegalizeOp(Tmp3); 2083 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2084 } 2085 } else { 2086 // If this is an unaligned load and the target doesn't support it, 2087 // expand it. 2088 if (!TLI.allowsUnalignedMemoryAccesses()) { 2089 unsigned ABIAlignment = TLI.getTargetData()-> 2090 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT())); 2091 if (LD->getAlignment() < ABIAlignment){ 2092 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 2093 TLI); 2094 Tmp1 = Result.getOperand(0); 2095 Tmp2 = Result.getOperand(1); 2096 Tmp1 = LegalizeOp(Tmp1); 2097 Tmp2 = LegalizeOp(Tmp2); 2098 } 2099 } 2100 } 2101 break; 2102 case TargetLowering::Expand: 2103 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2104 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2105 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2106 LD->getSrcValueOffset(), 2107 LD->isVolatile(), LD->getAlignment()); 2108 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2109 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2110 Tmp2 = LegalizeOp(Load.getValue(1)); 2111 break; 2112 } 2113 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2114 // Turn the unsupported load into an EXTLOAD followed by an explicit 2115 // zero/sign extend inreg. 2116 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2117 Tmp1, Tmp2, LD->getSrcValue(), 2118 LD->getSrcValueOffset(), SrcVT, 2119 LD->isVolatile(), LD->getAlignment()); 2120 SDOperand ValRes; 2121 if (ExtType == ISD::SEXTLOAD) 2122 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2123 Result, DAG.getValueType(SrcVT)); 2124 else 2125 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2126 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2127 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2128 break; 2129 } 2130 } 2131 2132 // Since loads produce two values, make sure to remember that we legalized 2133 // both of them. 2134 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2135 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2136 return Op.ResNo ? Tmp2 : Tmp1; 2137 } 2138 } 2139 case ISD::EXTRACT_ELEMENT: { 2140 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 2141 switch (getTypeAction(OpTy)) { 2142 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2143 case Legal: 2144 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 2145 // 1 -> Hi 2146 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2147 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 2148 TLI.getShiftAmountTy())); 2149 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2150 } else { 2151 // 0 -> Lo 2152 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2153 Node->getOperand(0)); 2154 } 2155 break; 2156 case Expand: 2157 // Get both the low and high parts. 2158 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2159 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 2160 Result = Tmp2; // 1 -> Hi 2161 else 2162 Result = Tmp1; // 0 -> Lo 2163 break; 2164 } 2165 break; 2166 } 2167 2168 case ISD::CopyToReg: 2169 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2170 2171 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2172 "Register type must be legal!"); 2173 // Legalize the incoming value (must be a legal type). 2174 Tmp2 = LegalizeOp(Node->getOperand(2)); 2175 if (Node->getNumValues() == 1) { 2176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2177 } else { 2178 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2179 if (Node->getNumOperands() == 4) { 2180 Tmp3 = LegalizeOp(Node->getOperand(3)); 2181 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2182 Tmp3); 2183 } else { 2184 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2185 } 2186 2187 // Since this produces two values, make sure to remember that we legalized 2188 // both of them. 2189 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2190 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2191 return Result; 2192 } 2193 break; 2194 2195 case ISD::RET: 2196 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2197 2198 // Ensure that libcalls are emitted before a return. 2199 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2200 Tmp1 = LegalizeOp(Tmp1); 2201 LastCALLSEQ_END = DAG.getEntryNode(); 2202 2203 switch (Node->getNumOperands()) { 2204 case 3: // ret val 2205 Tmp2 = Node->getOperand(1); 2206 Tmp3 = Node->getOperand(2); // Signness 2207 switch (getTypeAction(Tmp2.getValueType())) { 2208 case Legal: 2209 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2210 break; 2211 case Expand: 2212 if (!MVT::isVector(Tmp2.getValueType())) { 2213 SDOperand Lo, Hi; 2214 ExpandOp(Tmp2, Lo, Hi); 2215 2216 // Big endian systems want the hi reg first. 2217 if (TLI.isBigEndian()) 2218 std::swap(Lo, Hi); 2219 2220 if (Hi.Val) 2221 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2222 else 2223 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2224 Result = LegalizeOp(Result); 2225 } else { 2226 SDNode *InVal = Tmp2.Val; 2227 int InIx = Tmp2.ResNo; 2228 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 2229 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 2230 2231 // Figure out if there is a simple type corresponding to this Vector 2232 // type. If so, convert to the vector type. 2233 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2234 if (TLI.isTypeLegal(TVT)) { 2235 // Turn this into a return of the vector type. 2236 Tmp2 = LegalizeOp(Tmp2); 2237 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2238 } else if (NumElems == 1) { 2239 // Turn this into a return of the scalar type. 2240 Tmp2 = ScalarizeVectorOp(Tmp2); 2241 Tmp2 = LegalizeOp(Tmp2); 2242 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2243 2244 // FIXME: Returns of gcc generic vectors smaller than a legal type 2245 // should be returned in integer registers! 2246 2247 // The scalarized value type may not be legal, e.g. it might require 2248 // promotion or expansion. Relegalize the return. 2249 Result = LegalizeOp(Result); 2250 } else { 2251 // FIXME: Returns of gcc generic vectors larger than a legal vector 2252 // type should be returned by reference! 2253 SDOperand Lo, Hi; 2254 SplitVectorOp(Tmp2, Lo, Hi); 2255 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2256 Result = LegalizeOp(Result); 2257 } 2258 } 2259 break; 2260 case Promote: 2261 Tmp2 = PromoteOp(Node->getOperand(1)); 2262 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2263 Result = LegalizeOp(Result); 2264 break; 2265 } 2266 break; 2267 case 1: // ret void 2268 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2269 break; 2270 default: { // ret <values> 2271 SmallVector<SDOperand, 8> NewValues; 2272 NewValues.push_back(Tmp1); 2273 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2274 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2275 case Legal: 2276 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2277 NewValues.push_back(Node->getOperand(i+1)); 2278 break; 2279 case Expand: { 2280 SDOperand Lo, Hi; 2281 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && 2282 "FIXME: TODO: implement returning non-legal vector types!"); 2283 ExpandOp(Node->getOperand(i), Lo, Hi); 2284 NewValues.push_back(Lo); 2285 NewValues.push_back(Node->getOperand(i+1)); 2286 if (Hi.Val) { 2287 NewValues.push_back(Hi); 2288 NewValues.push_back(Node->getOperand(i+1)); 2289 } 2290 break; 2291 } 2292 case Promote: 2293 assert(0 && "Can't promote multiple return value yet!"); 2294 } 2295 2296 if (NewValues.size() == Node->getNumOperands()) 2297 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2298 else 2299 Result = DAG.getNode(ISD::RET, MVT::Other, 2300 &NewValues[0], NewValues.size()); 2301 break; 2302 } 2303 } 2304 2305 if (Result.getOpcode() == ISD::RET) { 2306 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2307 default: assert(0 && "This action is not supported yet!"); 2308 case TargetLowering::Legal: break; 2309 case TargetLowering::Custom: 2310 Tmp1 = TLI.LowerOperation(Result, DAG); 2311 if (Tmp1.Val) Result = Tmp1; 2312 break; 2313 } 2314 } 2315 break; 2316 case ISD::STORE: { 2317 StoreSDNode *ST = cast<StoreSDNode>(Node); 2318 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2319 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2320 int SVOffset = ST->getSrcValueOffset(); 2321 unsigned Alignment = ST->getAlignment(); 2322 bool isVolatile = ST->isVolatile(); 2323 2324 if (!ST->isTruncatingStore()) { 2325 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2326 // FIXME: We shouldn't do this for TargetConstantFP's. 2327 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2328 // to phase ordering between legalized code and the dag combiner. This 2329 // probably means that we need to integrate dag combiner and legalizer 2330 // together. 2331 // We generally can't do this one for long doubles. 2332 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2333 if (CFP->getValueType(0) == MVT::f32 && 2334 getTypeAction(MVT::i32) == Legal) { 2335 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2336 convertToAPInt().zextOrTrunc(32), 2337 MVT::i32); 2338 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2339 SVOffset, isVolatile, Alignment); 2340 break; 2341 } else if (CFP->getValueType(0) == MVT::f64) { 2342 // If this target supports 64-bit registers, do a single 64-bit store. 2343 if (getTypeAction(MVT::i64) == Legal) { 2344 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2345 zextOrTrunc(64), MVT::i64); 2346 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2347 SVOffset, isVolatile, Alignment); 2348 break; 2349 } else if (getTypeAction(MVT::i32) == Legal) { 2350 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2351 // stores. If the target supports neither 32- nor 64-bits, this 2352 // xform is certainly not worth it. 2353 const APInt &IntVal =CFP->getValueAPF().convertToAPInt(); 2354 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2355 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2356 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2357 2358 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2359 SVOffset, isVolatile, Alignment); 2360 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2361 DAG.getIntPtrConstant(4)); 2362 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2363 isVolatile, MinAlign(Alignment, 4U)); 2364 2365 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2366 break; 2367 } 2368 } 2369 } 2370 2371 switch (getTypeAction(ST->getMemoryVT())) { 2372 case Legal: { 2373 Tmp3 = LegalizeOp(ST->getValue()); 2374 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2375 ST->getOffset()); 2376 2377 MVT::ValueType VT = Tmp3.getValueType(); 2378 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2379 default: assert(0 && "This action is not supported yet!"); 2380 case TargetLowering::Legal: 2381 // If this is an unaligned store and the target doesn't support it, 2382 // expand it. 2383 if (!TLI.allowsUnalignedMemoryAccesses()) { 2384 unsigned ABIAlignment = TLI.getTargetData()-> 2385 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT())); 2386 if (ST->getAlignment() < ABIAlignment) 2387 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2388 TLI); 2389 } 2390 break; 2391 case TargetLowering::Custom: 2392 Tmp1 = TLI.LowerOperation(Result, DAG); 2393 if (Tmp1.Val) Result = Tmp1; 2394 break; 2395 case TargetLowering::Promote: 2396 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 2397 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2398 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2399 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2400 ST->getSrcValue(), SVOffset, isVolatile, 2401 Alignment); 2402 break; 2403 } 2404 break; 2405 } 2406 case Promote: 2407 // Truncate the value and store the result. 2408 Tmp3 = PromoteOp(ST->getValue()); 2409 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2410 SVOffset, ST->getMemoryVT(), 2411 isVolatile, Alignment); 2412 break; 2413 2414 case Expand: 2415 unsigned IncrementSize = 0; 2416 SDOperand Lo, Hi; 2417 2418 // If this is a vector type, then we have to calculate the increment as 2419 // the product of the element size in bytes, and the number of elements 2420 // in the high half of the vector. 2421 if (MVT::isVector(ST->getValue().getValueType())) { 2422 SDNode *InVal = ST->getValue().Val; 2423 int InIx = ST->getValue().ResNo; 2424 MVT::ValueType InVT = InVal->getValueType(InIx); 2425 unsigned NumElems = MVT::getVectorNumElements(InVT); 2426 MVT::ValueType EVT = MVT::getVectorElementType(InVT); 2427 2428 // Figure out if there is a simple type corresponding to this Vector 2429 // type. If so, convert to the vector type. 2430 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2431 if (TLI.isTypeLegal(TVT)) { 2432 // Turn this into a normal store of the vector type. 2433 Tmp3 = LegalizeOp(ST->getValue()); 2434 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2435 SVOffset, isVolatile, Alignment); 2436 Result = LegalizeOp(Result); 2437 break; 2438 } else if (NumElems == 1) { 2439 // Turn this into a normal store of the scalar type. 2440 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2441 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2442 SVOffset, isVolatile, Alignment); 2443 // The scalarized value type may not be legal, e.g. it might require 2444 // promotion or expansion. Relegalize the scalar store. 2445 Result = LegalizeOp(Result); 2446 break; 2447 } else { 2448 SplitVectorOp(ST->getValue(), Lo, Hi); 2449 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) * 2450 MVT::getSizeInBits(EVT)/8; 2451 } 2452 } else { 2453 ExpandOp(ST->getValue(), Lo, Hi); 2454 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 2455 2456 if (TLI.isBigEndian()) 2457 std::swap(Lo, Hi); 2458 } 2459 2460 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2461 SVOffset, isVolatile, Alignment); 2462 2463 if (Hi.Val == NULL) { 2464 // Must be int <-> float one-to-one expansion. 2465 Result = Lo; 2466 break; 2467 } 2468 2469 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2470 DAG.getIntPtrConstant(IncrementSize)); 2471 assert(isTypeLegal(Tmp2.getValueType()) && 2472 "Pointers must be legal!"); 2473 SVOffset += IncrementSize; 2474 Alignment = MinAlign(Alignment, IncrementSize); 2475 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2476 SVOffset, isVolatile, Alignment); 2477 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2478 break; 2479 } 2480 } else { 2481 switch (getTypeAction(ST->getValue().getValueType())) { 2482 case Legal: 2483 Tmp3 = LegalizeOp(ST->getValue()); 2484 break; 2485 case Promote: 2486 // We can promote the value, the truncstore will still take care of it. 2487 Tmp3 = PromoteOp(ST->getValue()); 2488 break; 2489 case Expand: 2490 // Just store the low part. This may become a non-trunc store, so make 2491 // sure to use getTruncStore, not UpdateNodeOperands below. 2492 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2493 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2494 SVOffset, MVT::i8, isVolatile, Alignment); 2495 } 2496 2497 MVT::ValueType StVT = ST->getMemoryVT(); 2498 unsigned StWidth = MVT::getSizeInBits(StVT); 2499 2500 if (StWidth != MVT::getStoreSizeInBits(StVT)) { 2501 // Promote to a byte-sized store with upper bits zero if not 2502 // storing an integral number of bytes. For example, promote 2503 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2504 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT)); 2505 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2506 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2507 SVOffset, NVT, isVolatile, Alignment); 2508 } else if (StWidth & (StWidth - 1)) { 2509 // If not storing a power-of-2 number of bits, expand as two stores. 2510 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) && 2511 "Unsupported truncstore!"); 2512 unsigned RoundWidth = 1 << Log2_32(StWidth); 2513 assert(RoundWidth < StWidth); 2514 unsigned ExtraWidth = StWidth - RoundWidth; 2515 assert(ExtraWidth < RoundWidth); 2516 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2517 "Store size not an integral number of bytes!"); 2518 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth); 2519 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth); 2520 SDOperand Lo, Hi; 2521 unsigned IncrementSize; 2522 2523 if (TLI.isLittleEndian()) { 2524 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2525 // Store the bottom RoundWidth bits. 2526 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2527 SVOffset, RoundVT, 2528 isVolatile, Alignment); 2529 2530 // Store the remaining ExtraWidth bits. 2531 IncrementSize = RoundWidth / 8; 2532 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2533 DAG.getIntPtrConstant(IncrementSize)); 2534 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2535 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2536 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2537 SVOffset + IncrementSize, ExtraVT, isVolatile, 2538 MinAlign(Alignment, IncrementSize)); 2539 } else { 2540 // Big endian - avoid unaligned stores. 2541 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2542 // Store the top RoundWidth bits. 2543 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2544 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2545 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2546 RoundVT, isVolatile, Alignment); 2547 2548 // Store the remaining ExtraWidth bits. 2549 IncrementSize = RoundWidth / 8; 2550 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2551 DAG.getIntPtrConstant(IncrementSize)); 2552 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2553 SVOffset + IncrementSize, ExtraVT, isVolatile, 2554 MinAlign(Alignment, IncrementSize)); 2555 } 2556 2557 // The order of the stores doesn't matter. 2558 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2559 } else { 2560 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2561 Tmp2 != ST->getBasePtr()) 2562 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2563 ST->getOffset()); 2564 2565 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2566 default: assert(0 && "This action is not supported yet!"); 2567 case TargetLowering::Legal: 2568 // If this is an unaligned store and the target doesn't support it, 2569 // expand it. 2570 if (!TLI.allowsUnalignedMemoryAccesses()) { 2571 unsigned ABIAlignment = TLI.getTargetData()-> 2572 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT())); 2573 if (ST->getAlignment() < ABIAlignment) 2574 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2575 TLI); 2576 } 2577 break; 2578 case TargetLowering::Custom: 2579 Result = TLI.LowerOperation(Result, DAG); 2580 break; 2581 case Expand: 2582 // TRUNCSTORE:i16 i32 -> STORE i16 2583 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2584 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2585 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2586 isVolatile, Alignment); 2587 break; 2588 } 2589 } 2590 } 2591 break; 2592 } 2593 case ISD::PCMARKER: 2594 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2595 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2596 break; 2597 case ISD::STACKSAVE: 2598 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2599 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2600 Tmp1 = Result.getValue(0); 2601 Tmp2 = Result.getValue(1); 2602 2603 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2604 default: assert(0 && "This action is not supported yet!"); 2605 case TargetLowering::Legal: break; 2606 case TargetLowering::Custom: 2607 Tmp3 = TLI.LowerOperation(Result, DAG); 2608 if (Tmp3.Val) { 2609 Tmp1 = LegalizeOp(Tmp3); 2610 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2611 } 2612 break; 2613 case TargetLowering::Expand: 2614 // Expand to CopyFromReg if the target set 2615 // StackPointerRegisterToSaveRestore. 2616 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2617 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2618 Node->getValueType(0)); 2619 Tmp2 = Tmp1.getValue(1); 2620 } else { 2621 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2622 Tmp2 = Node->getOperand(0); 2623 } 2624 break; 2625 } 2626 2627 // Since stacksave produce two values, make sure to remember that we 2628 // legalized both of them. 2629 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2630 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2631 return Op.ResNo ? Tmp2 : Tmp1; 2632 2633 case ISD::STACKRESTORE: 2634 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2635 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2636 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2637 2638 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2639 default: assert(0 && "This action is not supported yet!"); 2640 case TargetLowering::Legal: break; 2641 case TargetLowering::Custom: 2642 Tmp1 = TLI.LowerOperation(Result, DAG); 2643 if (Tmp1.Val) Result = Tmp1; 2644 break; 2645 case TargetLowering::Expand: 2646 // Expand to CopyToReg if the target set 2647 // StackPointerRegisterToSaveRestore. 2648 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2649 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2650 } else { 2651 Result = Tmp1; 2652 } 2653 break; 2654 } 2655 break; 2656 2657 case ISD::READCYCLECOUNTER: 2658 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2659 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2660 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2661 Node->getValueType(0))) { 2662 default: assert(0 && "This action is not supported yet!"); 2663 case TargetLowering::Legal: 2664 Tmp1 = Result.getValue(0); 2665 Tmp2 = Result.getValue(1); 2666 break; 2667 case TargetLowering::Custom: 2668 Result = TLI.LowerOperation(Result, DAG); 2669 Tmp1 = LegalizeOp(Result.getValue(0)); 2670 Tmp2 = LegalizeOp(Result.getValue(1)); 2671 break; 2672 } 2673 2674 // Since rdcc produce two values, make sure to remember that we legalized 2675 // both of them. 2676 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2677 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2678 return Result; 2679 2680 case ISD::SELECT: 2681 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2682 case Expand: assert(0 && "It's impossible to expand bools"); 2683 case Legal: 2684 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2685 break; 2686 case Promote: { 2687 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2688 // Make sure the condition is either zero or one. 2689 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2690 if (!DAG.MaskedValueIsZero(Tmp1, 2691 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2692 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2693 break; 2694 } 2695 } 2696 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2697 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2698 2699 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2700 2701 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2702 default: assert(0 && "This action is not supported yet!"); 2703 case TargetLowering::Legal: break; 2704 case TargetLowering::Custom: { 2705 Tmp1 = TLI.LowerOperation(Result, DAG); 2706 if (Tmp1.Val) Result = Tmp1; 2707 break; 2708 } 2709 case TargetLowering::Expand: 2710 if (Tmp1.getOpcode() == ISD::SETCC) { 2711 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2712 Tmp2, Tmp3, 2713 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2714 } else { 2715 Result = DAG.getSelectCC(Tmp1, 2716 DAG.getConstant(0, Tmp1.getValueType()), 2717 Tmp2, Tmp3, ISD::SETNE); 2718 } 2719 break; 2720 case TargetLowering::Promote: { 2721 MVT::ValueType NVT = 2722 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2723 unsigned ExtOp, TruncOp; 2724 if (MVT::isVector(Tmp2.getValueType())) { 2725 ExtOp = ISD::BIT_CONVERT; 2726 TruncOp = ISD::BIT_CONVERT; 2727 } else if (MVT::isInteger(Tmp2.getValueType())) { 2728 ExtOp = ISD::ANY_EXTEND; 2729 TruncOp = ISD::TRUNCATE; 2730 } else { 2731 ExtOp = ISD::FP_EXTEND; 2732 TruncOp = ISD::FP_ROUND; 2733 } 2734 // Promote each of the values to the new type. 2735 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2736 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2737 // Perform the larger operation, then round down. 2738 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2739 if (TruncOp != ISD::FP_ROUND) 2740 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2741 else 2742 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2743 DAG.getIntPtrConstant(0)); 2744 break; 2745 } 2746 } 2747 break; 2748 case ISD::SELECT_CC: { 2749 Tmp1 = Node->getOperand(0); // LHS 2750 Tmp2 = Node->getOperand(1); // RHS 2751 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2752 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2753 SDOperand CC = Node->getOperand(4); 2754 2755 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2756 2757 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2758 // the LHS is a legal SETCC itself. In this case, we need to compare 2759 // the result against zero to select between true and false values. 2760 if (Tmp2.Val == 0) { 2761 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2762 CC = DAG.getCondCode(ISD::SETNE); 2763 } 2764 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2765 2766 // Everything is legal, see if we should expand this op or something. 2767 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2768 default: assert(0 && "This action is not supported yet!"); 2769 case TargetLowering::Legal: break; 2770 case TargetLowering::Custom: 2771 Tmp1 = TLI.LowerOperation(Result, DAG); 2772 if (Tmp1.Val) Result = Tmp1; 2773 break; 2774 } 2775 break; 2776 } 2777 case ISD::SETCC: 2778 Tmp1 = Node->getOperand(0); 2779 Tmp2 = Node->getOperand(1); 2780 Tmp3 = Node->getOperand(2); 2781 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2782 2783 // If we had to Expand the SetCC operands into a SELECT node, then it may 2784 // not always be possible to return a true LHS & RHS. In this case, just 2785 // return the value we legalized, returned in the LHS 2786 if (Tmp2.Val == 0) { 2787 Result = Tmp1; 2788 break; 2789 } 2790 2791 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2792 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2793 case TargetLowering::Custom: 2794 isCustom = true; 2795 // FALLTHROUGH. 2796 case TargetLowering::Legal: 2797 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2798 if (isCustom) { 2799 Tmp4 = TLI.LowerOperation(Result, DAG); 2800 if (Tmp4.Val) Result = Tmp4; 2801 } 2802 break; 2803 case TargetLowering::Promote: { 2804 // First step, figure out the appropriate operation to use. 2805 // Allow SETCC to not be supported for all legal data types 2806 // Mostly this targets FP 2807 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2808 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2809 2810 // Scan for the appropriate larger type to use. 2811 while (1) { 2812 NewInTy = (MVT::ValueType)(NewInTy+1); 2813 2814 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2815 "Fell off of the edge of the integer world"); 2816 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2817 "Fell off of the edge of the floating point world"); 2818 2819 // If the target supports SETCC of this type, use it. 2820 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2821 break; 2822 } 2823 if (MVT::isInteger(NewInTy)) 2824 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2825 else { 2826 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2827 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2828 } 2829 Tmp1 = LegalizeOp(Tmp1); 2830 Tmp2 = LegalizeOp(Tmp2); 2831 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2832 Result = LegalizeOp(Result); 2833 break; 2834 } 2835 case TargetLowering::Expand: 2836 // Expand a setcc node into a select_cc of the same condition, lhs, and 2837 // rhs that selects between const 1 (true) and const 0 (false). 2838 MVT::ValueType VT = Node->getValueType(0); 2839 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2840 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2841 Tmp3); 2842 break; 2843 } 2844 break; 2845 case ISD::MEMSET: 2846 case ISD::MEMCPY: 2847 case ISD::MEMMOVE: { 2848 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2849 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2850 2851 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2852 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2853 case Expand: assert(0 && "Cannot expand a byte!"); 2854 case Legal: 2855 Tmp3 = LegalizeOp(Node->getOperand(2)); 2856 break; 2857 case Promote: 2858 Tmp3 = PromoteOp(Node->getOperand(2)); 2859 break; 2860 } 2861 } else { 2862 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2863 } 2864 2865 SDOperand Tmp4; 2866 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2867 case Expand: { 2868 // Length is too big, just take the lo-part of the length. 2869 SDOperand HiPart; 2870 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2871 break; 2872 } 2873 case Legal: 2874 Tmp4 = LegalizeOp(Node->getOperand(3)); 2875 break; 2876 case Promote: 2877 Tmp4 = PromoteOp(Node->getOperand(3)); 2878 break; 2879 } 2880 2881 SDOperand Tmp5; 2882 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2883 case Expand: assert(0 && "Cannot expand this yet!"); 2884 case Legal: 2885 Tmp5 = LegalizeOp(Node->getOperand(4)); 2886 break; 2887 case Promote: 2888 Tmp5 = PromoteOp(Node->getOperand(4)); 2889 break; 2890 } 2891 2892 SDOperand Tmp6; 2893 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool 2894 case Expand: assert(0 && "Cannot expand this yet!"); 2895 case Legal: 2896 Tmp6 = LegalizeOp(Node->getOperand(5)); 2897 break; 2898 case Promote: 2899 Tmp6 = PromoteOp(Node->getOperand(5)); 2900 break; 2901 } 2902 2903 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2904 default: assert(0 && "This action not implemented for this operation!"); 2905 case TargetLowering::Custom: 2906 isCustom = true; 2907 // FALLTHROUGH 2908 case TargetLowering::Legal: { 2909 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 }; 2910 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 2911 if (isCustom) { 2912 Tmp1 = TLI.LowerOperation(Result, DAG); 2913 if (Tmp1.Val) Result = Tmp1; 2914 } 2915 break; 2916 } 2917 case TargetLowering::Expand: { 2918 // Otherwise, the target does not support this operation. Lower the 2919 // operation to an explicit libcall as appropriate. 2920 MVT::ValueType IntPtr = TLI.getPointerTy(); 2921 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2922 TargetLowering::ArgListTy Args; 2923 TargetLowering::ArgListEntry Entry; 2924 2925 const char *FnName = 0; 2926 if (Node->getOpcode() == ISD::MEMSET) { 2927 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; 2928 Args.push_back(Entry); 2929 // Extend the (previously legalized) ubyte argument to be an int value 2930 // for the call. 2931 if (Tmp3.getValueType() > MVT::i32) 2932 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2933 else 2934 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2935 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 2936 Args.push_back(Entry); 2937 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false; 2938 Args.push_back(Entry); 2939 2940 FnName = "memset"; 2941 } else if (Node->getOpcode() == ISD::MEMCPY || 2942 Node->getOpcode() == ISD::MEMMOVE) { 2943 Entry.Ty = IntPtrTy; 2944 Entry.Node = Tmp2; Args.push_back(Entry); 2945 Entry.Node = Tmp3; Args.push_back(Entry); 2946 Entry.Node = Tmp4; Args.push_back(Entry); 2947 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2948 } else { 2949 assert(0 && "Unknown op!"); 2950 } 2951 2952 std::pair<SDOperand,SDOperand> CallResult = 2953 TLI.LowerCallTo(Tmp1, Type::VoidTy, 2954 false, false, false, CallingConv::C, false, 2955 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2956 Result = CallResult.second; 2957 break; 2958 } 2959 } 2960 break; 2961 } 2962 2963 case ISD::SHL_PARTS: 2964 case ISD::SRA_PARTS: 2965 case ISD::SRL_PARTS: { 2966 SmallVector<SDOperand, 8> Ops; 2967 bool Changed = false; 2968 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2969 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2970 Changed |= Ops.back() != Node->getOperand(i); 2971 } 2972 if (Changed) 2973 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2974 2975 switch (TLI.getOperationAction(Node->getOpcode(), 2976 Node->getValueType(0))) { 2977 default: assert(0 && "This action is not supported yet!"); 2978 case TargetLowering::Legal: break; 2979 case TargetLowering::Custom: 2980 Tmp1 = TLI.LowerOperation(Result, DAG); 2981 if (Tmp1.Val) { 2982 SDOperand Tmp2, RetVal(0, 0); 2983 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2984 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2985 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2986 if (i == Op.ResNo) 2987 RetVal = Tmp2; 2988 } 2989 assert(RetVal.Val && "Illegal result number"); 2990 return RetVal; 2991 } 2992 break; 2993 } 2994 2995 // Since these produce multiple values, make sure to remember that we 2996 // legalized all of them. 2997 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2998 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2999 return Result.getValue(Op.ResNo); 3000 } 3001 3002 // Binary operators 3003 case ISD::ADD: 3004 case ISD::SUB: 3005 case ISD::MUL: 3006 case ISD::MULHS: 3007 case ISD::MULHU: 3008 case ISD::UDIV: 3009 case ISD::SDIV: 3010 case ISD::AND: 3011 case ISD::OR: 3012 case ISD::XOR: 3013 case ISD::SHL: 3014 case ISD::SRL: 3015 case ISD::SRA: 3016 case ISD::FADD: 3017 case ISD::FSUB: 3018 case ISD::FMUL: 3019 case ISD::FDIV: 3020 case ISD::FPOW: 3021 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3022 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3023 case Expand: assert(0 && "Not possible"); 3024 case Legal: 3025 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3026 break; 3027 case Promote: 3028 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3029 break; 3030 } 3031 3032 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3033 3034 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3035 default: assert(0 && "BinOp legalize operation not supported"); 3036 case TargetLowering::Legal: break; 3037 case TargetLowering::Custom: 3038 Tmp1 = TLI.LowerOperation(Result, DAG); 3039 if (Tmp1.Val) Result = Tmp1; 3040 break; 3041 case TargetLowering::Expand: { 3042 MVT::ValueType VT = Op.getValueType(); 3043 3044 // See if multiply or divide can be lowered using two-result operations. 3045 SDVTList VTs = DAG.getVTList(VT, VT); 3046 if (Node->getOpcode() == ISD::MUL) { 3047 // We just need the low half of the multiply; try both the signed 3048 // and unsigned forms. If the target supports both SMUL_LOHI and 3049 // UMUL_LOHI, form a preference by checking which forms of plain 3050 // MULH it supports. 3051 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 3052 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 3053 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 3054 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 3055 unsigned OpToUse = 0; 3056 if (HasSMUL_LOHI && !HasMULHS) { 3057 OpToUse = ISD::SMUL_LOHI; 3058 } else if (HasUMUL_LOHI && !HasMULHU) { 3059 OpToUse = ISD::UMUL_LOHI; 3060 } else if (HasSMUL_LOHI) { 3061 OpToUse = ISD::SMUL_LOHI; 3062 } else if (HasUMUL_LOHI) { 3063 OpToUse = ISD::UMUL_LOHI; 3064 } 3065 if (OpToUse) { 3066 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 3067 break; 3068 } 3069 } 3070 if (Node->getOpcode() == ISD::MULHS && 3071 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 3072 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3073 break; 3074 } 3075 if (Node->getOpcode() == ISD::MULHU && 3076 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 3077 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3078 break; 3079 } 3080 if (Node->getOpcode() == ISD::SDIV && 3081 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3082 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3083 break; 3084 } 3085 if (Node->getOpcode() == ISD::UDIV && 3086 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3087 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3088 break; 3089 } 3090 3091 // Check to see if we have a libcall for this operator. 3092 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3093 bool isSigned = false; 3094 switch (Node->getOpcode()) { 3095 case ISD::UDIV: 3096 case ISD::SDIV: 3097 if (VT == MVT::i32) { 3098 LC = Node->getOpcode() == ISD::UDIV 3099 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3100 isSigned = Node->getOpcode() == ISD::SDIV; 3101 } 3102 break; 3103 case ISD::FPOW: 3104 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3105 RTLIB::POW_PPCF128); 3106 break; 3107 default: break; 3108 } 3109 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3110 SDOperand Dummy; 3111 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 3112 break; 3113 } 3114 3115 assert(MVT::isVector(Node->getValueType(0)) && 3116 "Cannot expand this binary operator!"); 3117 // Expand the operation into a bunch of nasty scalar code. 3118 Result = LegalizeOp(UnrollVectorOp(Op)); 3119 break; 3120 } 3121 case TargetLowering::Promote: { 3122 switch (Node->getOpcode()) { 3123 default: assert(0 && "Do not know how to promote this BinOp!"); 3124 case ISD::AND: 3125 case ISD::OR: 3126 case ISD::XOR: { 3127 MVT::ValueType OVT = Node->getValueType(0); 3128 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3129 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 3130 // Bit convert each of the values to the new type. 3131 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3132 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3133 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3134 // Bit convert the result back the original type. 3135 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3136 break; 3137 } 3138 } 3139 } 3140 } 3141 break; 3142 3143 case ISD::SMUL_LOHI: 3144 case ISD::UMUL_LOHI: 3145 case ISD::SDIVREM: 3146 case ISD::UDIVREM: 3147 // These nodes will only be produced by target-specific lowering, so 3148 // they shouldn't be here if they aren't legal. 3149 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3150 "This must be legal!"); 3151 3152 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3153 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3154 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3155 break; 3156 3157 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3158 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3159 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3160 case Expand: assert(0 && "Not possible"); 3161 case Legal: 3162 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3163 break; 3164 case Promote: 3165 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3166 break; 3167 } 3168 3169 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3170 3171 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3172 default: assert(0 && "Operation not supported"); 3173 case TargetLowering::Custom: 3174 Tmp1 = TLI.LowerOperation(Result, DAG); 3175 if (Tmp1.Val) Result = Tmp1; 3176 break; 3177 case TargetLowering::Legal: break; 3178 case TargetLowering::Expand: { 3179 // If this target supports fabs/fneg natively and select is cheap, 3180 // do this efficiently. 3181 if (!TLI.isSelectExpensive() && 3182 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3183 TargetLowering::Legal && 3184 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3185 TargetLowering::Legal) { 3186 // Get the sign bit of the RHS. 3187 MVT::ValueType IVT = 3188 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3189 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3190 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), 3191 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3192 // Get the absolute value of the result. 3193 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3194 // Select between the nabs and abs value based on the sign bit of 3195 // the input. 3196 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3197 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3198 AbsVal), 3199 AbsVal); 3200 Result = LegalizeOp(Result); 3201 break; 3202 } 3203 3204 // Otherwise, do bitwise ops! 3205 MVT::ValueType NVT = 3206 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3207 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3208 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3209 Result = LegalizeOp(Result); 3210 break; 3211 } 3212 } 3213 break; 3214 3215 case ISD::ADDC: 3216 case ISD::SUBC: 3217 Tmp1 = LegalizeOp(Node->getOperand(0)); 3218 Tmp2 = LegalizeOp(Node->getOperand(1)); 3219 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3220 // Since this produces two values, make sure to remember that we legalized 3221 // both of them. 3222 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3223 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3224 return Result; 3225 3226 case ISD::ADDE: 3227 case ISD::SUBE: 3228 Tmp1 = LegalizeOp(Node->getOperand(0)); 3229 Tmp2 = LegalizeOp(Node->getOperand(1)); 3230 Tmp3 = LegalizeOp(Node->getOperand(2)); 3231 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3232 // Since this produces two values, make sure to remember that we legalized 3233 // both of them. 3234 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3235 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3236 return Result; 3237 3238 case ISD::BUILD_PAIR: { 3239 MVT::ValueType PairTy = Node->getValueType(0); 3240 // TODO: handle the case where the Lo and Hi operands are not of legal type 3241 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3242 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3243 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3244 case TargetLowering::Promote: 3245 case TargetLowering::Custom: 3246 assert(0 && "Cannot promote/custom this yet!"); 3247 case TargetLowering::Legal: 3248 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3249 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3250 break; 3251 case TargetLowering::Expand: 3252 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3253 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3254 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3255 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 3256 TLI.getShiftAmountTy())); 3257 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3258 break; 3259 } 3260 break; 3261 } 3262 3263 case ISD::UREM: 3264 case ISD::SREM: 3265 case ISD::FREM: 3266 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3267 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3268 3269 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3270 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3271 case TargetLowering::Custom: 3272 isCustom = true; 3273 // FALLTHROUGH 3274 case TargetLowering::Legal: 3275 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3276 if (isCustom) { 3277 Tmp1 = TLI.LowerOperation(Result, DAG); 3278 if (Tmp1.Val) Result = Tmp1; 3279 } 3280 break; 3281 case TargetLowering::Expand: { 3282 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3283 bool isSigned = DivOpc == ISD::SDIV; 3284 MVT::ValueType VT = Node->getValueType(0); 3285 3286 // See if remainder can be lowered using two-result operations. 3287 SDVTList VTs = DAG.getVTList(VT, VT); 3288 if (Node->getOpcode() == ISD::SREM && 3289 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3290 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3291 break; 3292 } 3293 if (Node->getOpcode() == ISD::UREM && 3294 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3295 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3296 break; 3297 } 3298 3299 if (MVT::isInteger(VT)) { 3300 if (TLI.getOperationAction(DivOpc, VT) == 3301 TargetLowering::Legal) { 3302 // X % Y -> X-X/Y*Y 3303 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3304 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3305 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3306 } else if (MVT::isVector(VT)) { 3307 Result = LegalizeOp(UnrollVectorOp(Op)); 3308 } else { 3309 assert(VT == MVT::i32 && 3310 "Cannot expand this binary operator!"); 3311 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3312 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3313 SDOperand Dummy; 3314 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 3315 } 3316 } else { 3317 assert(MVT::isFloatingPoint(VT) && 3318 "remainder op must have integer or floating-point type"); 3319 if (MVT::isVector(VT)) { 3320 Result = LegalizeOp(UnrollVectorOp(Op)); 3321 } else { 3322 // Floating point mod -> fmod libcall. 3323 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3324 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3325 SDOperand Dummy; 3326 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3327 false/*sign irrelevant*/, Dummy); 3328 } 3329 } 3330 break; 3331 } 3332 } 3333 break; 3334 case ISD::VAARG: { 3335 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3336 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3337 3338 MVT::ValueType VT = Node->getValueType(0); 3339 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3340 default: assert(0 && "This action is not supported yet!"); 3341 case TargetLowering::Custom: 3342 isCustom = true; 3343 // FALLTHROUGH 3344 case TargetLowering::Legal: 3345 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3346 Result = Result.getValue(0); 3347 Tmp1 = Result.getValue(1); 3348 3349 if (isCustom) { 3350 Tmp2 = TLI.LowerOperation(Result, DAG); 3351 if (Tmp2.Val) { 3352 Result = LegalizeOp(Tmp2); 3353 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3354 } 3355 } 3356 break; 3357 case TargetLowering::Expand: { 3358 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3359 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3360 // Increment the pointer, VAList, to the next vaarg 3361 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3362 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3363 TLI.getPointerTy())); 3364 // Store the incremented VAList to the legalized pointer 3365 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3366 // Load the actual argument out of the pointer VAList 3367 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3368 Tmp1 = LegalizeOp(Result.getValue(1)); 3369 Result = LegalizeOp(Result); 3370 break; 3371 } 3372 } 3373 // Since VAARG produces two values, make sure to remember that we 3374 // legalized both of them. 3375 AddLegalizedOperand(SDOperand(Node, 0), Result); 3376 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3377 return Op.ResNo ? Tmp1 : Result; 3378 } 3379 3380 case ISD::VACOPY: 3381 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3382 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3383 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3384 3385 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3386 default: assert(0 && "This action is not supported yet!"); 3387 case TargetLowering::Custom: 3388 isCustom = true; 3389 // FALLTHROUGH 3390 case TargetLowering::Legal: 3391 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3392 Node->getOperand(3), Node->getOperand(4)); 3393 if (isCustom) { 3394 Tmp1 = TLI.LowerOperation(Result, DAG); 3395 if (Tmp1.Val) Result = Tmp1; 3396 } 3397 break; 3398 case TargetLowering::Expand: 3399 // This defaults to loading a pointer from the input and storing it to the 3400 // output, returning the chain. 3401 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3402 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3403 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0); 3404 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0); 3405 break; 3406 } 3407 break; 3408 3409 case ISD::VAEND: 3410 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3411 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3412 3413 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3414 default: assert(0 && "This action is not supported yet!"); 3415 case TargetLowering::Custom: 3416 isCustom = true; 3417 // FALLTHROUGH 3418 case TargetLowering::Legal: 3419 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3420 if (isCustom) { 3421 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3422 if (Tmp1.Val) Result = Tmp1; 3423 } 3424 break; 3425 case TargetLowering::Expand: 3426 Result = Tmp1; // Default to a no-op, return the chain 3427 break; 3428 } 3429 break; 3430 3431 case ISD::VASTART: 3432 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3433 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3434 3435 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3436 3437 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3438 default: assert(0 && "This action is not supported yet!"); 3439 case TargetLowering::Legal: break; 3440 case TargetLowering::Custom: 3441 Tmp1 = TLI.LowerOperation(Result, DAG); 3442 if (Tmp1.Val) Result = Tmp1; 3443 break; 3444 } 3445 break; 3446 3447 case ISD::ROTL: 3448 case ISD::ROTR: 3449 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3450 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3451 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3452 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3453 default: 3454 assert(0 && "ROTL/ROTR legalize operation not supported"); 3455 break; 3456 case TargetLowering::Legal: 3457 break; 3458 case TargetLowering::Custom: 3459 Tmp1 = TLI.LowerOperation(Result, DAG); 3460 if (Tmp1.Val) Result = Tmp1; 3461 break; 3462 case TargetLowering::Promote: 3463 assert(0 && "Do not know how to promote ROTL/ROTR"); 3464 break; 3465 case TargetLowering::Expand: 3466 assert(0 && "Do not know how to expand ROTL/ROTR"); 3467 break; 3468 } 3469 break; 3470 3471 case ISD::BSWAP: 3472 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3473 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3474 case TargetLowering::Custom: 3475 assert(0 && "Cannot custom legalize this yet!"); 3476 case TargetLowering::Legal: 3477 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3478 break; 3479 case TargetLowering::Promote: { 3480 MVT::ValueType OVT = Tmp1.getValueType(); 3481 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3482 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 3483 3484 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3485 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3486 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3487 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3488 break; 3489 } 3490 case TargetLowering::Expand: 3491 Result = ExpandBSWAP(Tmp1); 3492 break; 3493 } 3494 break; 3495 3496 case ISD::CTPOP: 3497 case ISD::CTTZ: 3498 case ISD::CTLZ: 3499 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3500 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3501 case TargetLowering::Custom: 3502 case TargetLowering::Legal: 3503 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3504 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3505 TargetLowering::Custom) { 3506 Tmp1 = TLI.LowerOperation(Result, DAG); 3507 if (Tmp1.Val) { 3508 Result = Tmp1; 3509 } 3510 } 3511 break; 3512 case TargetLowering::Promote: { 3513 MVT::ValueType OVT = Tmp1.getValueType(); 3514 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3515 3516 // Zero extend the argument. 3517 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3518 // Perform the larger operation, then subtract if needed. 3519 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3520 switch (Node->getOpcode()) { 3521 case ISD::CTPOP: 3522 Result = Tmp1; 3523 break; 3524 case ISD::CTTZ: 3525 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3526 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 3527 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3528 ISD::SETEQ); 3529 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3530 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 3531 break; 3532 case ISD::CTLZ: 3533 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3534 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3535 DAG.getConstant(MVT::getSizeInBits(NVT) - 3536 MVT::getSizeInBits(OVT), NVT)); 3537 break; 3538 } 3539 break; 3540 } 3541 case TargetLowering::Expand: 3542 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3543 break; 3544 } 3545 break; 3546 3547 // Unary operators 3548 case ISD::FABS: 3549 case ISD::FNEG: 3550 case ISD::FSQRT: 3551 case ISD::FSIN: 3552 case ISD::FCOS: 3553 Tmp1 = LegalizeOp(Node->getOperand(0)); 3554 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3555 case TargetLowering::Promote: 3556 case TargetLowering::Custom: 3557 isCustom = true; 3558 // FALLTHROUGH 3559 case TargetLowering::Legal: 3560 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3561 if (isCustom) { 3562 Tmp1 = TLI.LowerOperation(Result, DAG); 3563 if (Tmp1.Val) Result = Tmp1; 3564 } 3565 break; 3566 case TargetLowering::Expand: 3567 switch (Node->getOpcode()) { 3568 default: assert(0 && "Unreachable!"); 3569 case ISD::FNEG: 3570 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3571 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3572 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3573 break; 3574 case ISD::FABS: { 3575 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3576 MVT::ValueType VT = Node->getValueType(0); 3577 Tmp2 = DAG.getConstantFP(0.0, VT); 3578 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 3579 ISD::SETUGT); 3580 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3581 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3582 break; 3583 } 3584 case ISD::FSQRT: 3585 case ISD::FSIN: 3586 case ISD::FCOS: { 3587 MVT::ValueType VT = Node->getValueType(0); 3588 3589 // Expand unsupported unary vector operators by unrolling them. 3590 if (MVT::isVector(VT)) { 3591 Result = LegalizeOp(UnrollVectorOp(Op)); 3592 break; 3593 } 3594 3595 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3596 switch(Node->getOpcode()) { 3597 case ISD::FSQRT: 3598 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3599 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3600 break; 3601 case ISD::FSIN: 3602 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3603 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3604 break; 3605 case ISD::FCOS: 3606 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3607 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3608 break; 3609 default: assert(0 && "Unreachable!"); 3610 } 3611 SDOperand Dummy; 3612 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3613 false/*sign irrelevant*/, Dummy); 3614 break; 3615 } 3616 } 3617 break; 3618 } 3619 break; 3620 case ISD::FPOWI: { 3621 MVT::ValueType VT = Node->getValueType(0); 3622 3623 // Expand unsupported unary vector operators by unrolling them. 3624 if (MVT::isVector(VT)) { 3625 Result = LegalizeOp(UnrollVectorOp(Op)); 3626 break; 3627 } 3628 3629 // We always lower FPOWI into a libcall. No target support for it yet. 3630 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3631 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3632 SDOperand Dummy; 3633 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3634 false/*sign irrelevant*/, Dummy); 3635 break; 3636 } 3637 case ISD::BIT_CONVERT: 3638 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3639 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3640 Node->getValueType(0)); 3641 } else if (MVT::isVector(Op.getOperand(0).getValueType())) { 3642 // The input has to be a vector type, we have to either scalarize it, pack 3643 // it, or convert it based on whether the input vector type is legal. 3644 SDNode *InVal = Node->getOperand(0).Val; 3645 int InIx = Node->getOperand(0).ResNo; 3646 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 3647 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 3648 3649 // Figure out if there is a simple type corresponding to this Vector 3650 // type. If so, convert to the vector type. 3651 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3652 if (TLI.isTypeLegal(TVT)) { 3653 // Turn this into a bit convert of the vector input. 3654 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3655 LegalizeOp(Node->getOperand(0))); 3656 break; 3657 } else if (NumElems == 1) { 3658 // Turn this into a bit convert of the scalar input. 3659 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3660 ScalarizeVectorOp(Node->getOperand(0))); 3661 break; 3662 } else { 3663 // FIXME: UNIMP! Store then reload 3664 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3665 } 3666 } else { 3667 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3668 Node->getOperand(0).getValueType())) { 3669 default: assert(0 && "Unknown operation action!"); 3670 case TargetLowering::Expand: 3671 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3672 Node->getValueType(0)); 3673 break; 3674 case TargetLowering::Legal: 3675 Tmp1 = LegalizeOp(Node->getOperand(0)); 3676 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3677 break; 3678 } 3679 } 3680 break; 3681 3682 // Conversion operators. The source and destination have different types. 3683 case ISD::SINT_TO_FP: 3684 case ISD::UINT_TO_FP: { 3685 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3686 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3687 case Legal: 3688 switch (TLI.getOperationAction(Node->getOpcode(), 3689 Node->getOperand(0).getValueType())) { 3690 default: assert(0 && "Unknown operation action!"); 3691 case TargetLowering::Custom: 3692 isCustom = true; 3693 // FALLTHROUGH 3694 case TargetLowering::Legal: 3695 Tmp1 = LegalizeOp(Node->getOperand(0)); 3696 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3697 if (isCustom) { 3698 Tmp1 = TLI.LowerOperation(Result, DAG); 3699 if (Tmp1.Val) Result = Tmp1; 3700 } 3701 break; 3702 case TargetLowering::Expand: 3703 Result = ExpandLegalINT_TO_FP(isSigned, 3704 LegalizeOp(Node->getOperand(0)), 3705 Node->getValueType(0)); 3706 break; 3707 case TargetLowering::Promote: 3708 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3709 Node->getValueType(0), 3710 isSigned); 3711 break; 3712 } 3713 break; 3714 case Expand: 3715 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3716 Node->getValueType(0), Node->getOperand(0)); 3717 break; 3718 case Promote: 3719 Tmp1 = PromoteOp(Node->getOperand(0)); 3720 if (isSigned) { 3721 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3722 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3723 } else { 3724 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3725 Node->getOperand(0).getValueType()); 3726 } 3727 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3728 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3729 break; 3730 } 3731 break; 3732 } 3733 case ISD::TRUNCATE: 3734 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3735 case Legal: 3736 Tmp1 = LegalizeOp(Node->getOperand(0)); 3737 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3738 break; 3739 case Expand: 3740 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3741 3742 // Since the result is legal, we should just be able to truncate the low 3743 // part of the source. 3744 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3745 break; 3746 case Promote: 3747 Result = PromoteOp(Node->getOperand(0)); 3748 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3749 break; 3750 } 3751 break; 3752 3753 case ISD::FP_TO_SINT: 3754 case ISD::FP_TO_UINT: 3755 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3756 case Legal: 3757 Tmp1 = LegalizeOp(Node->getOperand(0)); 3758 3759 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3760 default: assert(0 && "Unknown operation action!"); 3761 case TargetLowering::Custom: 3762 isCustom = true; 3763 // FALLTHROUGH 3764 case TargetLowering::Legal: 3765 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3766 if (isCustom) { 3767 Tmp1 = TLI.LowerOperation(Result, DAG); 3768 if (Tmp1.Val) Result = Tmp1; 3769 } 3770 break; 3771 case TargetLowering::Promote: 3772 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3773 Node->getOpcode() == ISD::FP_TO_SINT); 3774 break; 3775 case TargetLowering::Expand: 3776 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3777 SDOperand True, False; 3778 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3779 MVT::ValueType NVT = Node->getValueType(0); 3780 const uint64_t zero[] = {0, 0}; 3781 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero)); 3782 APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT)); 3783 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 3784 Tmp2 = DAG.getConstantFP(apf, VT); 3785 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), 3786 Node->getOperand(0), Tmp2, ISD::SETLT); 3787 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3788 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3789 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3790 Tmp2)); 3791 False = DAG.getNode(ISD::XOR, NVT, False, 3792 DAG.getConstant(x, NVT)); 3793 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3794 break; 3795 } else { 3796 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3797 } 3798 break; 3799 } 3800 break; 3801 case Expand: { 3802 MVT::ValueType VT = Op.getValueType(); 3803 MVT::ValueType OVT = Node->getOperand(0).getValueType(); 3804 // Convert ppcf128 to i32 3805 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3806 if (Node->getOpcode() == ISD::FP_TO_SINT) { 3807 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 3808 Node->getOperand(0), DAG.getValueType(MVT::f64)); 3809 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 3810 DAG.getIntPtrConstant(1)); 3811 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 3812 } else { 3813 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3814 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3815 Tmp2 = DAG.getConstantFP(apf, OVT); 3816 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3817 // FIXME: generated code sucks. 3818 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3819 DAG.getNode(ISD::ADD, MVT::i32, 3820 DAG.getNode(ISD::FP_TO_SINT, VT, 3821 DAG.getNode(ISD::FSUB, OVT, 3822 Node->getOperand(0), Tmp2)), 3823 DAG.getConstant(0x80000000, MVT::i32)), 3824 DAG.getNode(ISD::FP_TO_SINT, VT, 3825 Node->getOperand(0)), 3826 DAG.getCondCode(ISD::SETGE)); 3827 } 3828 break; 3829 } 3830 // Convert f32 / f64 to i32 / i64 / i128. 3831 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3832 switch (Node->getOpcode()) { 3833 case ISD::FP_TO_SINT: { 3834 if (VT == MVT::i32) { 3835 if (OVT == MVT::f32) 3836 LC = RTLIB::FPTOSINT_F32_I32; 3837 else if (OVT == MVT::f64) 3838 LC = RTLIB::FPTOSINT_F64_I32; 3839 else 3840 assert(0 && "Unexpected i32-to-fp conversion!"); 3841 } else if (VT == MVT::i64) { 3842 if (OVT == MVT::f32) 3843 LC = RTLIB::FPTOSINT_F32_I64; 3844 else if (OVT == MVT::f64) 3845 LC = RTLIB::FPTOSINT_F64_I64; 3846 else if (OVT == MVT::f80) 3847 LC = RTLIB::FPTOSINT_F80_I64; 3848 else if (OVT == MVT::ppcf128) 3849 LC = RTLIB::FPTOSINT_PPCF128_I64; 3850 else 3851 assert(0 && "Unexpected i64-to-fp conversion!"); 3852 } else if (VT == MVT::i128) { 3853 if (OVT == MVT::f32) 3854 LC = RTLIB::FPTOSINT_F32_I128; 3855 else if (OVT == MVT::f64) 3856 LC = RTLIB::FPTOSINT_F64_I128; 3857 else if (OVT == MVT::f80) 3858 LC = RTLIB::FPTOSINT_F80_I128; 3859 else if (OVT == MVT::ppcf128) 3860 LC = RTLIB::FPTOSINT_PPCF128_I128; 3861 else 3862 assert(0 && "Unexpected i128-to-fp conversion!"); 3863 } else { 3864 assert(0 && "Unexpectd int-to-fp conversion!"); 3865 } 3866 break; 3867 } 3868 case ISD::FP_TO_UINT: { 3869 if (VT == MVT::i32) { 3870 if (OVT == MVT::f32) 3871 LC = RTLIB::FPTOUINT_F32_I32; 3872 else if (OVT == MVT::f64) 3873 LC = RTLIB::FPTOUINT_F64_I32; 3874 else if (OVT == MVT::f80) 3875 LC = RTLIB::FPTOUINT_F80_I32; 3876 else 3877 assert(0 && "Unexpected i32-to-fp conversion!"); 3878 } else if (VT == MVT::i64) { 3879 if (OVT == MVT::f32) 3880 LC = RTLIB::FPTOUINT_F32_I64; 3881 else if (OVT == MVT::f64) 3882 LC = RTLIB::FPTOUINT_F64_I64; 3883 else if (OVT == MVT::f80) 3884 LC = RTLIB::FPTOUINT_F80_I64; 3885 else if (OVT == MVT::ppcf128) 3886 LC = RTLIB::FPTOUINT_PPCF128_I64; 3887 else 3888 assert(0 && "Unexpected i64-to-fp conversion!"); 3889 } else if (VT == MVT::i128) { 3890 if (OVT == MVT::f32) 3891 LC = RTLIB::FPTOUINT_F32_I128; 3892 else if (OVT == MVT::f64) 3893 LC = RTLIB::FPTOUINT_F64_I128; 3894 else if (OVT == MVT::f80) 3895 LC = RTLIB::FPTOUINT_F80_I128; 3896 else if (OVT == MVT::ppcf128) 3897 LC = RTLIB::FPTOUINT_PPCF128_I128; 3898 else 3899 assert(0 && "Unexpected i128-to-fp conversion!"); 3900 } else { 3901 assert(0 && "Unexpectd int-to-fp conversion!"); 3902 } 3903 break; 3904 } 3905 default: assert(0 && "Unreachable!"); 3906 } 3907 SDOperand Dummy; 3908 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3909 false/*sign irrelevant*/, Dummy); 3910 break; 3911 } 3912 case Promote: 3913 Tmp1 = PromoteOp(Node->getOperand(0)); 3914 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3915 Result = LegalizeOp(Result); 3916 break; 3917 } 3918 break; 3919 3920 case ISD::FP_EXTEND: { 3921 MVT::ValueType DstVT = Op.getValueType(); 3922 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3923 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3924 // The only other way we can lower this is to turn it into a STORE, 3925 // LOAD pair, targetting a temporary location (a stack slot). 3926 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 3927 break; 3928 } 3929 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3930 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3931 case Legal: 3932 Tmp1 = LegalizeOp(Node->getOperand(0)); 3933 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3934 break; 3935 case Promote: 3936 Tmp1 = PromoteOp(Node->getOperand(0)); 3937 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3938 break; 3939 } 3940 break; 3941 } 3942 case ISD::FP_ROUND: { 3943 MVT::ValueType DstVT = Op.getValueType(); 3944 MVT::ValueType SrcVT = Op.getOperand(0).getValueType(); 3945 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3946 if (SrcVT == MVT::ppcf128) { 3947 SDOperand Lo; 3948 ExpandOp(Node->getOperand(0), Lo, Result); 3949 // Round it the rest of the way (e.g. to f32) if needed. 3950 if (DstVT!=MVT::f64) 3951 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 3952 break; 3953 } 3954 // The only other way we can lower this is to turn it into a STORE, 3955 // LOAD pair, targetting a temporary location (a stack slot). 3956 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 3957 break; 3958 } 3959 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3960 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3961 case Legal: 3962 Tmp1 = LegalizeOp(Node->getOperand(0)); 3963 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3964 break; 3965 case Promote: 3966 Tmp1 = PromoteOp(Node->getOperand(0)); 3967 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 3968 Node->getOperand(1)); 3969 break; 3970 } 3971 break; 3972 } 3973 case ISD::ANY_EXTEND: 3974 case ISD::ZERO_EXTEND: 3975 case ISD::SIGN_EXTEND: 3976 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3977 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3978 case Legal: 3979 Tmp1 = LegalizeOp(Node->getOperand(0)); 3980 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3981 TargetLowering::Custom) { 3982 Tmp2 = TLI.LowerOperation(Result, DAG); 3983 if (Tmp2.Val) { 3984 Tmp1 = Tmp2; 3985 } 3986 } 3987 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3988 break; 3989 case Promote: 3990 switch (Node->getOpcode()) { 3991 case ISD::ANY_EXTEND: 3992 Tmp1 = PromoteOp(Node->getOperand(0)); 3993 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3994 break; 3995 case ISD::ZERO_EXTEND: 3996 Result = PromoteOp(Node->getOperand(0)); 3997 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3998 Result = DAG.getZeroExtendInReg(Result, 3999 Node->getOperand(0).getValueType()); 4000 break; 4001 case ISD::SIGN_EXTEND: 4002 Result = PromoteOp(Node->getOperand(0)); 4003 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 4004 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4005 Result, 4006 DAG.getValueType(Node->getOperand(0).getValueType())); 4007 break; 4008 } 4009 } 4010 break; 4011 case ISD::FP_ROUND_INREG: 4012 case ISD::SIGN_EXTEND_INREG: { 4013 Tmp1 = LegalizeOp(Node->getOperand(0)); 4014 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 4015 4016 // If this operation is not supported, convert it to a shl/shr or load/store 4017 // pair. 4018 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 4019 default: assert(0 && "This action not supported for this op yet!"); 4020 case TargetLowering::Legal: 4021 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 4022 break; 4023 case TargetLowering::Expand: 4024 // If this is an integer extend and shifts are supported, do that. 4025 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 4026 // NOTE: we could fall back on load/store here too for targets without 4027 // SAR. However, it is doubtful that any exist. 4028 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 4029 MVT::getSizeInBits(ExtraVT); 4030 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 4031 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 4032 Node->getOperand(0), ShiftCst); 4033 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 4034 Result, ShiftCst); 4035 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 4036 // The only way we can lower this is to turn it into a TRUNCSTORE, 4037 // EXTLOAD pair, targetting a temporary location (a stack slot). 4038 4039 // NOTE: there is a choice here between constantly creating new stack 4040 // slots and always reusing the same one. We currently always create 4041 // new ones, as reuse may inhibit scheduling. 4042 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 4043 Node->getValueType(0)); 4044 } else { 4045 assert(0 && "Unknown op"); 4046 } 4047 break; 4048 } 4049 break; 4050 } 4051 case ISD::TRAMPOLINE: { 4052 SDOperand Ops[6]; 4053 for (unsigned i = 0; i != 6; ++i) 4054 Ops[i] = LegalizeOp(Node->getOperand(i)); 4055 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 4056 // The only option for this node is to custom lower it. 4057 Result = TLI.LowerOperation(Result, DAG); 4058 assert(Result.Val && "Should always custom lower!"); 4059 4060 // Since trampoline produces two values, make sure to remember that we 4061 // legalized both of them. 4062 Tmp1 = LegalizeOp(Result.getValue(1)); 4063 Result = LegalizeOp(Result); 4064 AddLegalizedOperand(SDOperand(Node, 0), Result); 4065 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 4066 return Op.ResNo ? Tmp1 : Result; 4067 } 4068 case ISD::FLT_ROUNDS_: { 4069 MVT::ValueType VT = Node->getValueType(0); 4070 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4071 default: assert(0 && "This action not supported for this op yet!"); 4072 case TargetLowering::Custom: 4073 Result = TLI.LowerOperation(Op, DAG); 4074 if (Result.Val) break; 4075 // Fall Thru 4076 case TargetLowering::Legal: 4077 // If this operation is not supported, lower it to constant 1 4078 Result = DAG.getConstant(1, VT); 4079 break; 4080 } 4081 } 4082 case ISD::TRAP: { 4083 MVT::ValueType VT = Node->getValueType(0); 4084 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4085 default: assert(0 && "This action not supported for this op yet!"); 4086 case TargetLowering::Legal: 4087 Tmp1 = LegalizeOp(Node->getOperand(0)); 4088 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4089 break; 4090 case TargetLowering::Custom: 4091 Result = TLI.LowerOperation(Op, DAG); 4092 if (Result.Val) break; 4093 // Fall Thru 4094 case TargetLowering::Expand: 4095 // If this operation is not supported, lower it to 'abort()' call 4096 Tmp1 = LegalizeOp(Node->getOperand(0)); 4097 TargetLowering::ArgListTy Args; 4098 std::pair<SDOperand,SDOperand> CallResult = 4099 TLI.LowerCallTo(Tmp1, Type::VoidTy, 4100 false, false, false, CallingConv::C, false, 4101 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 4102 Args, DAG); 4103 Result = CallResult.second; 4104 break; 4105 } 4106 break; 4107 } 4108 } 4109 4110 assert(Result.getValueType() == Op.getValueType() && 4111 "Bad legalization!"); 4112 4113 // Make sure that the generated code is itself legal. 4114 if (Result != Op) 4115 Result = LegalizeOp(Result); 4116 4117 // Note that LegalizeOp may be reentered even from single-use nodes, which 4118 // means that we always must cache transformed nodes. 4119 AddLegalizedOperand(Op, Result); 4120 return Result; 4121} 4122 4123/// PromoteOp - Given an operation that produces a value in an invalid type, 4124/// promote it to compute the value into a larger type. The produced value will 4125/// have the correct bits for the low portion of the register, but no guarantee 4126/// is made about the top bits: it may be zero, sign-extended, or garbage. 4127SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 4128 MVT::ValueType VT = Op.getValueType(); 4129 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4130 assert(getTypeAction(VT) == Promote && 4131 "Caller should expand or legalize operands that are not promotable!"); 4132 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 4133 "Cannot promote to smaller type!"); 4134 4135 SDOperand Tmp1, Tmp2, Tmp3; 4136 SDOperand Result; 4137 SDNode *Node = Op.Val; 4138 4139 DenseMap<SDOperandImpl, SDOperand>::iterator I = PromotedNodes.find(Op); 4140 if (I != PromotedNodes.end()) return I->second; 4141 4142 switch (Node->getOpcode()) { 4143 case ISD::CopyFromReg: 4144 assert(0 && "CopyFromReg must be legal!"); 4145 default: 4146#ifndef NDEBUG 4147 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4148#endif 4149 assert(0 && "Do not know how to promote this operator!"); 4150 abort(); 4151 case ISD::UNDEF: 4152 Result = DAG.getNode(ISD::UNDEF, NVT); 4153 break; 4154 case ISD::Constant: 4155 if (VT != MVT::i1) 4156 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4157 else 4158 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4159 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4160 break; 4161 case ISD::ConstantFP: 4162 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4163 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4164 break; 4165 4166 case ISD::SETCC: 4167 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0))) 4168 && "SetCC type is not legal??"); 4169 Result = DAG.getNode(ISD::SETCC, 4170 TLI.getSetCCResultType(Node->getOperand(0)), 4171 Node->getOperand(0), Node->getOperand(1), 4172 Node->getOperand(2)); 4173 break; 4174 4175 case ISD::TRUNCATE: 4176 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4177 case Legal: 4178 Result = LegalizeOp(Node->getOperand(0)); 4179 assert(Result.getValueType() >= NVT && 4180 "This truncation doesn't make sense!"); 4181 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 4182 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4183 break; 4184 case Promote: 4185 // The truncation is not required, because we don't guarantee anything 4186 // about high bits anyway. 4187 Result = PromoteOp(Node->getOperand(0)); 4188 break; 4189 case Expand: 4190 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4191 // Truncate the low part of the expanded value to the result type 4192 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4193 } 4194 break; 4195 case ISD::SIGN_EXTEND: 4196 case ISD::ZERO_EXTEND: 4197 case ISD::ANY_EXTEND: 4198 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4199 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4200 case Legal: 4201 // Input is legal? Just do extend all the way to the larger type. 4202 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4203 break; 4204 case Promote: 4205 // Promote the reg if it's smaller. 4206 Result = PromoteOp(Node->getOperand(0)); 4207 // The high bits are not guaranteed to be anything. Insert an extend. 4208 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4209 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4210 DAG.getValueType(Node->getOperand(0).getValueType())); 4211 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4212 Result = DAG.getZeroExtendInReg(Result, 4213 Node->getOperand(0).getValueType()); 4214 break; 4215 } 4216 break; 4217 case ISD::BIT_CONVERT: 4218 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4219 Node->getValueType(0)); 4220 Result = PromoteOp(Result); 4221 break; 4222 4223 case ISD::FP_EXTEND: 4224 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4225 case ISD::FP_ROUND: 4226 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4227 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4228 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4229 case Legal: 4230 if (Node->getConstantOperandVal(1) == 0) { 4231 // Input is legal? Do an FP_ROUND_INREG. 4232 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4233 DAG.getValueType(VT)); 4234 } else { 4235 // Just remove the truncate, it isn't affecting the value. 4236 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4237 Node->getOperand(1)); 4238 } 4239 break; 4240 } 4241 break; 4242 case ISD::SINT_TO_FP: 4243 case ISD::UINT_TO_FP: 4244 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4245 case Legal: 4246 // No extra round required here. 4247 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4248 break; 4249 4250 case Promote: 4251 Result = PromoteOp(Node->getOperand(0)); 4252 if (Node->getOpcode() == ISD::SINT_TO_FP) 4253 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4254 Result, 4255 DAG.getValueType(Node->getOperand(0).getValueType())); 4256 else 4257 Result = DAG.getZeroExtendInReg(Result, 4258 Node->getOperand(0).getValueType()); 4259 // No extra round required here. 4260 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4261 break; 4262 case Expand: 4263 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4264 Node->getOperand(0)); 4265 // Round if we cannot tolerate excess precision. 4266 if (NoExcessFPPrecision) 4267 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4268 DAG.getValueType(VT)); 4269 break; 4270 } 4271 break; 4272 4273 case ISD::SIGN_EXTEND_INREG: 4274 Result = PromoteOp(Node->getOperand(0)); 4275 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4276 Node->getOperand(1)); 4277 break; 4278 case ISD::FP_TO_SINT: 4279 case ISD::FP_TO_UINT: 4280 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4281 case Legal: 4282 case Expand: 4283 Tmp1 = Node->getOperand(0); 4284 break; 4285 case Promote: 4286 // The input result is prerounded, so we don't have to do anything 4287 // special. 4288 Tmp1 = PromoteOp(Node->getOperand(0)); 4289 break; 4290 } 4291 // If we're promoting a UINT to a larger size, check to see if the new node 4292 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4293 // we can use that instead. This allows us to generate better code for 4294 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4295 // legal, such as PowerPC. 4296 if (Node->getOpcode() == ISD::FP_TO_UINT && 4297 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 4298 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 4299 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4300 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4301 } else { 4302 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4303 } 4304 break; 4305 4306 case ISD::FABS: 4307 case ISD::FNEG: 4308 Tmp1 = PromoteOp(Node->getOperand(0)); 4309 assert(Tmp1.getValueType() == NVT); 4310 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4311 // NOTE: we do not have to do any extra rounding here for 4312 // NoExcessFPPrecision, because we know the input will have the appropriate 4313 // precision, and these operations don't modify precision at all. 4314 break; 4315 4316 case ISD::FSQRT: 4317 case ISD::FSIN: 4318 case ISD::FCOS: 4319 Tmp1 = PromoteOp(Node->getOperand(0)); 4320 assert(Tmp1.getValueType() == NVT); 4321 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4322 if (NoExcessFPPrecision) 4323 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4324 DAG.getValueType(VT)); 4325 break; 4326 4327 case ISD::FPOWI: { 4328 // Promote f32 powi to f64 powi. Note that this could insert a libcall 4329 // directly as well, which may be better. 4330 Tmp1 = PromoteOp(Node->getOperand(0)); 4331 assert(Tmp1.getValueType() == NVT); 4332 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 4333 if (NoExcessFPPrecision) 4334 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4335 DAG.getValueType(VT)); 4336 break; 4337 } 4338 4339 case ISD::ATOMIC_LCS: { 4340 Tmp2 = PromoteOp(Node->getOperand(2)); 4341 Tmp3 = PromoteOp(Node->getOperand(3)); 4342 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0), 4343 Node->getOperand(1), Tmp2, Tmp3, 4344 cast<AtomicSDNode>(Node)->getVT()); 4345 // Remember that we legalized the chain. 4346 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4347 break; 4348 } 4349 case ISD::ATOMIC_LAS: 4350 case ISD::ATOMIC_SWAP: { 4351 Tmp2 = PromoteOp(Node->getOperand(2)); 4352 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0), 4353 Node->getOperand(1), Tmp2, 4354 cast<AtomicSDNode>(Node)->getVT()); 4355 // Remember that we legalized the chain. 4356 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4357 break; 4358 } 4359 4360 case ISD::AND: 4361 case ISD::OR: 4362 case ISD::XOR: 4363 case ISD::ADD: 4364 case ISD::SUB: 4365 case ISD::MUL: 4366 // The input may have strange things in the top bits of the registers, but 4367 // these operations don't care. They may have weird bits going out, but 4368 // that too is okay if they are integer operations. 4369 Tmp1 = PromoteOp(Node->getOperand(0)); 4370 Tmp2 = PromoteOp(Node->getOperand(1)); 4371 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4372 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4373 break; 4374 case ISD::FADD: 4375 case ISD::FSUB: 4376 case ISD::FMUL: 4377 Tmp1 = PromoteOp(Node->getOperand(0)); 4378 Tmp2 = PromoteOp(Node->getOperand(1)); 4379 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4380 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4381 4382 // Floating point operations will give excess precision that we may not be 4383 // able to tolerate. If we DO allow excess precision, just leave it, 4384 // otherwise excise it. 4385 // FIXME: Why would we need to round FP ops more than integer ones? 4386 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4387 if (NoExcessFPPrecision) 4388 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4389 DAG.getValueType(VT)); 4390 break; 4391 4392 case ISD::SDIV: 4393 case ISD::SREM: 4394 // These operators require that their input be sign extended. 4395 Tmp1 = PromoteOp(Node->getOperand(0)); 4396 Tmp2 = PromoteOp(Node->getOperand(1)); 4397 if (MVT::isInteger(NVT)) { 4398 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4399 DAG.getValueType(VT)); 4400 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4401 DAG.getValueType(VT)); 4402 } 4403 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4404 4405 // Perform FP_ROUND: this is probably overly pessimistic. 4406 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 4407 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4408 DAG.getValueType(VT)); 4409 break; 4410 case ISD::FDIV: 4411 case ISD::FREM: 4412 case ISD::FCOPYSIGN: 4413 // These operators require that their input be fp extended. 4414 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4415 case Expand: assert(0 && "not implemented"); 4416 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4417 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4418 } 4419 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4420 case Expand: assert(0 && "not implemented"); 4421 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4422 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4423 } 4424 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4425 4426 // Perform FP_ROUND: this is probably overly pessimistic. 4427 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4428 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4429 DAG.getValueType(VT)); 4430 break; 4431 4432 case ISD::UDIV: 4433 case ISD::UREM: 4434 // These operators require that their input be zero extended. 4435 Tmp1 = PromoteOp(Node->getOperand(0)); 4436 Tmp2 = PromoteOp(Node->getOperand(1)); 4437 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 4438 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4439 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4440 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4441 break; 4442 4443 case ISD::SHL: 4444 Tmp1 = PromoteOp(Node->getOperand(0)); 4445 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4446 break; 4447 case ISD::SRA: 4448 // The input value must be properly sign extended. 4449 Tmp1 = PromoteOp(Node->getOperand(0)); 4450 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4451 DAG.getValueType(VT)); 4452 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4453 break; 4454 case ISD::SRL: 4455 // The input value must be properly zero extended. 4456 Tmp1 = PromoteOp(Node->getOperand(0)); 4457 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4458 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4459 break; 4460 4461 case ISD::VAARG: 4462 Tmp1 = Node->getOperand(0); // Get the chain. 4463 Tmp2 = Node->getOperand(1); // Get the pointer. 4464 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4465 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4466 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 4467 } else { 4468 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4469 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4470 // Increment the pointer, VAList, to the next vaarg 4471 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4472 DAG.getConstant(MVT::getSizeInBits(VT)/8, 4473 TLI.getPointerTy())); 4474 // Store the incremented VAList to the legalized pointer 4475 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4476 // Load the actual argument out of the pointer VAList 4477 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4478 } 4479 // Remember that we legalized the chain. 4480 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4481 break; 4482 4483 case ISD::LOAD: { 4484 LoadSDNode *LD = cast<LoadSDNode>(Node); 4485 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4486 ? ISD::EXTLOAD : LD->getExtensionType(); 4487 Result = DAG.getExtLoad(ExtType, NVT, 4488 LD->getChain(), LD->getBasePtr(), 4489 LD->getSrcValue(), LD->getSrcValueOffset(), 4490 LD->getMemoryVT(), 4491 LD->isVolatile(), 4492 LD->getAlignment()); 4493 // Remember that we legalized the chain. 4494 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4495 break; 4496 } 4497 case ISD::SELECT: 4498 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4499 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4500 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 4501 break; 4502 case ISD::SELECT_CC: 4503 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4504 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4505 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4506 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4507 break; 4508 case ISD::BSWAP: 4509 Tmp1 = Node->getOperand(0); 4510 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4511 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4512 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4513 DAG.getConstant(MVT::getSizeInBits(NVT) - 4514 MVT::getSizeInBits(VT), 4515 TLI.getShiftAmountTy())); 4516 break; 4517 case ISD::CTPOP: 4518 case ISD::CTTZ: 4519 case ISD::CTLZ: 4520 // Zero extend the argument 4521 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4522 // Perform the larger operation, then subtract if needed. 4523 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4524 switch(Node->getOpcode()) { 4525 case ISD::CTPOP: 4526 Result = Tmp1; 4527 break; 4528 case ISD::CTTZ: 4529 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4530 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 4531 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 4532 ISD::SETEQ); 4533 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4534 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 4535 break; 4536 case ISD::CTLZ: 4537 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4538 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4539 DAG.getConstant(MVT::getSizeInBits(NVT) - 4540 MVT::getSizeInBits(VT), NVT)); 4541 break; 4542 } 4543 break; 4544 case ISD::EXTRACT_SUBVECTOR: 4545 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4546 break; 4547 case ISD::EXTRACT_VECTOR_ELT: 4548 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4549 break; 4550 } 4551 4552 assert(Result.Val && "Didn't set a result!"); 4553 4554 // Make sure the result is itself legal. 4555 Result = LegalizeOp(Result); 4556 4557 // Remember that we promoted this! 4558 AddPromotedOperand(Op, Result); 4559 return Result; 4560} 4561 4562/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4563/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4564/// based on the vector type. The return type of this matches the element type 4565/// of the vector, which may not be legal for the target. 4566SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4567 // We know that operand #0 is the Vec vector. If the index is a constant 4568 // or if the invec is a supported hardware type, we can use it. Otherwise, 4569 // lower to a store then an indexed load. 4570 SDOperand Vec = Op.getOperand(0); 4571 SDOperand Idx = Op.getOperand(1); 4572 4573 MVT::ValueType TVT = Vec.getValueType(); 4574 unsigned NumElems = MVT::getVectorNumElements(TVT); 4575 4576 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4577 default: assert(0 && "This action is not supported yet!"); 4578 case TargetLowering::Custom: { 4579 Vec = LegalizeOp(Vec); 4580 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4581 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4582 if (Tmp3.Val) 4583 return Tmp3; 4584 break; 4585 } 4586 case TargetLowering::Legal: 4587 if (isTypeLegal(TVT)) { 4588 Vec = LegalizeOp(Vec); 4589 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4590 return Op; 4591 } 4592 break; 4593 case TargetLowering::Expand: 4594 break; 4595 } 4596 4597 if (NumElems == 1) { 4598 // This must be an access of the only element. Return it. 4599 Op = ScalarizeVectorOp(Vec); 4600 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4601 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 4602 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4603 SDOperand Lo, Hi; 4604 SplitVectorOp(Vec, Lo, Hi); 4605 if (CIdx->getValue() < NumLoElts) { 4606 Vec = Lo; 4607 } else { 4608 Vec = Hi; 4609 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts, 4610 Idx.getValueType()); 4611 } 4612 4613 // It's now an extract from the appropriate high or low part. Recurse. 4614 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4615 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4616 } else { 4617 // Store the value to a temporary stack slot, then LOAD the scalar 4618 // element back out. 4619 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4620 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4621 4622 // Add the offset to the index. 4623 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 4624 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4625 DAG.getConstant(EltSize, Idx.getValueType())); 4626 4627 if (MVT::getSizeInBits(Idx.getValueType()) > 4628 MVT::getSizeInBits(TLI.getPointerTy())) 4629 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4630 else 4631 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4632 4633 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4634 4635 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4636 } 4637 return Op; 4638} 4639 4640/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4641/// we assume the operation can be split if it is not already legal. 4642SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4643 // We know that operand #0 is the Vec vector. For now we assume the index 4644 // is a constant and that the extracted result is a supported hardware type. 4645 SDOperand Vec = Op.getOperand(0); 4646 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4647 4648 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); 4649 4650 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 4651 // This must be an access of the desired vector length. Return it. 4652 return Vec; 4653 } 4654 4655 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4656 SDOperand Lo, Hi; 4657 SplitVectorOp(Vec, Lo, Hi); 4658 if (CIdx->getValue() < NumElems/2) { 4659 Vec = Lo; 4660 } else { 4661 Vec = Hi; 4662 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4663 } 4664 4665 // It's now an extract from the appropriate high or low part. Recurse. 4666 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4667 return ExpandEXTRACT_SUBVECTOR(Op); 4668} 4669 4670/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4671/// with condition CC on the current target. This usually involves legalizing 4672/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4673/// there may be no choice but to create a new SetCC node to represent the 4674/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4675/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4676void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4677 SDOperand &RHS, 4678 SDOperand &CC) { 4679 SDOperand Tmp1, Tmp2, Tmp3, Result; 4680 4681 switch (getTypeAction(LHS.getValueType())) { 4682 case Legal: 4683 Tmp1 = LegalizeOp(LHS); // LHS 4684 Tmp2 = LegalizeOp(RHS); // RHS 4685 break; 4686 case Promote: 4687 Tmp1 = PromoteOp(LHS); // LHS 4688 Tmp2 = PromoteOp(RHS); // RHS 4689 4690 // If this is an FP compare, the operands have already been extended. 4691 if (MVT::isInteger(LHS.getValueType())) { 4692 MVT::ValueType VT = LHS.getValueType(); 4693 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4694 4695 // Otherwise, we have to insert explicit sign or zero extends. Note 4696 // that we could insert sign extends for ALL conditions, but zero extend 4697 // is cheaper on many machines (an AND instead of two shifts), so prefer 4698 // it. 4699 switch (cast<CondCodeSDNode>(CC)->get()) { 4700 default: assert(0 && "Unknown integer comparison!"); 4701 case ISD::SETEQ: 4702 case ISD::SETNE: 4703 case ISD::SETUGE: 4704 case ISD::SETUGT: 4705 case ISD::SETULE: 4706 case ISD::SETULT: 4707 // ALL of these operations will work if we either sign or zero extend 4708 // the operands (including the unsigned comparisons!). Zero extend is 4709 // usually a simpler/cheaper operation, so prefer it. 4710 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4711 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4712 break; 4713 case ISD::SETGE: 4714 case ISD::SETGT: 4715 case ISD::SETLT: 4716 case ISD::SETLE: 4717 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4718 DAG.getValueType(VT)); 4719 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4720 DAG.getValueType(VT)); 4721 break; 4722 } 4723 } 4724 break; 4725 case Expand: { 4726 MVT::ValueType VT = LHS.getValueType(); 4727 if (VT == MVT::f32 || VT == MVT::f64) { 4728 // Expand into one or more soft-fp libcall(s). 4729 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4730 switch (cast<CondCodeSDNode>(CC)->get()) { 4731 case ISD::SETEQ: 4732 case ISD::SETOEQ: 4733 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4734 break; 4735 case ISD::SETNE: 4736 case ISD::SETUNE: 4737 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4738 break; 4739 case ISD::SETGE: 4740 case ISD::SETOGE: 4741 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4742 break; 4743 case ISD::SETLT: 4744 case ISD::SETOLT: 4745 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4746 break; 4747 case ISD::SETLE: 4748 case ISD::SETOLE: 4749 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4750 break; 4751 case ISD::SETGT: 4752 case ISD::SETOGT: 4753 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4754 break; 4755 case ISD::SETUO: 4756 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4757 break; 4758 case ISD::SETO: 4759 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4760 break; 4761 default: 4762 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4763 switch (cast<CondCodeSDNode>(CC)->get()) { 4764 case ISD::SETONE: 4765 // SETONE = SETOLT | SETOGT 4766 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4767 // Fallthrough 4768 case ISD::SETUGT: 4769 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4770 break; 4771 case ISD::SETUGE: 4772 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4773 break; 4774 case ISD::SETULT: 4775 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4776 break; 4777 case ISD::SETULE: 4778 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4779 break; 4780 case ISD::SETUEQ: 4781 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4782 break; 4783 default: assert(0 && "Unsupported FP setcc!"); 4784 } 4785 } 4786 4787 SDOperand Dummy; 4788 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 4789 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4790 false /*sign irrelevant*/, Dummy); 4791 Tmp2 = DAG.getConstant(0, MVT::i32); 4792 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4793 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4794 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 4795 CC); 4796 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 4797 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4798 false /*sign irrelevant*/, Dummy); 4799 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, 4800 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4801 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4802 Tmp2 = SDOperand(); 4803 } 4804 LHS = Tmp1; 4805 RHS = Tmp2; 4806 return; 4807 } 4808 4809 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4810 ExpandOp(LHS, LHSLo, LHSHi); 4811 ExpandOp(RHS, RHSLo, RHSHi); 4812 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4813 4814 if (VT==MVT::ppcf128) { 4815 // FIXME: This generated code sucks. We want to generate 4816 // FCMP crN, hi1, hi2 4817 // BNE crN, L: 4818 // FCMP crN, lo1, lo2 4819 // The following can be improved, but not that much. 4820 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ); 4821 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode); 4822 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4823 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE); 4824 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode); 4825 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4826 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4827 Tmp2 = SDOperand(); 4828 break; 4829 } 4830 4831 switch (CCCode) { 4832 case ISD::SETEQ: 4833 case ISD::SETNE: 4834 if (RHSLo == RHSHi) 4835 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4836 if (RHSCST->isAllOnesValue()) { 4837 // Comparison to -1. 4838 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4839 Tmp2 = RHSLo; 4840 break; 4841 } 4842 4843 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4844 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4845 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4846 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4847 break; 4848 default: 4849 // If this is a comparison of the sign bit, just look at the top part. 4850 // X > -1, x < 0 4851 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4852 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4853 CST->isNullValue()) || // X < 0 4854 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4855 CST->isAllOnesValue())) { // X > -1 4856 Tmp1 = LHSHi; 4857 Tmp2 = RHSHi; 4858 break; 4859 } 4860 4861 // FIXME: This generated code sucks. 4862 ISD::CondCode LowCC; 4863 switch (CCCode) { 4864 default: assert(0 && "Unknown integer setcc!"); 4865 case ISD::SETLT: 4866 case ISD::SETULT: LowCC = ISD::SETULT; break; 4867 case ISD::SETGT: 4868 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4869 case ISD::SETLE: 4870 case ISD::SETULE: LowCC = ISD::SETULE; break; 4871 case ISD::SETGE: 4872 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4873 } 4874 4875 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4876 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4877 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4878 4879 // NOTE: on targets without efficient SELECT of bools, we can always use 4880 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4881 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4882 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, 4883 LowCC, false, DagCombineInfo); 4884 if (!Tmp1.Val) 4885 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 4886 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4887 CCCode, false, DagCombineInfo); 4888 if (!Tmp2.Val) 4889 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, 4890 RHSHi,CC); 4891 4892 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4893 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4894 if ((Tmp1C && Tmp1C->isNullValue()) || 4895 (Tmp2C && Tmp2C->isNullValue() && 4896 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4897 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4898 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 4899 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4900 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4901 // low part is known false, returns high part. 4902 // For LE / GE, if high part is known false, ignore the low part. 4903 // For LT / GT, if high part is known true, ignore the low part. 4904 Tmp1 = Tmp2; 4905 Tmp2 = SDOperand(); 4906 } else { 4907 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4908 ISD::SETEQ, false, DagCombineInfo); 4909 if (!Result.Val) 4910 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4911 ISD::SETEQ); 4912 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4913 Result, Tmp1, Tmp2)); 4914 Tmp1 = Result; 4915 Tmp2 = SDOperand(); 4916 } 4917 } 4918 } 4919 } 4920 LHS = Tmp1; 4921 RHS = Tmp2; 4922} 4923 4924/// EmitStackConvert - Emit a store/load combination to the stack. This stores 4925/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 4926/// a load from the stack slot to DestVT, extending it if needed. 4927/// The resultant code need not be legal. 4928SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, 4929 MVT::ValueType SlotVT, 4930 MVT::ValueType DestVT) { 4931 // Create the stack frame object. 4932 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); 4933 4934 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 4935 int SPFI = StackPtrFI->getIndex(); 4936 4937 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType()); 4938 unsigned SlotSize = MVT::getSizeInBits(SlotVT); 4939 unsigned DestSize = MVT::getSizeInBits(DestVT); 4940 4941 // Emit a store to the stack slot. Use a truncstore if the input value is 4942 // later than DestVT. 4943 SDOperand Store; 4944 if (SrcSize > SlotSize) 4945 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 4946 PseudoSourceValue::getFixedStack(), 4947 SPFI, SlotVT); 4948 else { 4949 assert(SrcSize == SlotSize && "Invalid store"); 4950 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 4951 PseudoSourceValue::getFixedStack(), 4952 SPFI, SlotVT); 4953 } 4954 4955 // Result is a load from the stack slot. 4956 if (SlotSize == DestSize) 4957 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4958 4959 assert(SlotSize < DestSize && "Unknown extension!"); 4960 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT); 4961} 4962 4963SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4964 // Create a vector sized/aligned stack slot, store the value to element #0, 4965 // then load the whole vector back out. 4966 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4967 4968 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 4969 int SPFI = StackPtrFI->getIndex(); 4970 4971 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4972 PseudoSourceValue::getFixedStack(), SPFI); 4973 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 4974 PseudoSourceValue::getFixedStack(), SPFI); 4975} 4976 4977 4978/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4979/// support the operation, but do support the resultant vector type. 4980SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4981 4982 // If the only non-undef value is the low element, turn this into a 4983 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4984 unsigned NumElems = Node->getNumOperands(); 4985 bool isOnlyLowElement = true; 4986 SDOperand SplatValue = Node->getOperand(0); 4987 4988 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t> 4989 // and use a bitmask instead of a list of elements. 4990 std::map<SDOperand, std::vector<unsigned> > Values; 4991 Values[SplatValue].push_back(0); 4992 bool isConstant = true; 4993 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4994 SplatValue.getOpcode() != ISD::UNDEF) 4995 isConstant = false; 4996 4997 for (unsigned i = 1; i < NumElems; ++i) { 4998 SDOperand V = Node->getOperand(i); 4999 Values[V].push_back(i); 5000 if (V.getOpcode() != ISD::UNDEF) 5001 isOnlyLowElement = false; 5002 if (SplatValue != V) 5003 SplatValue = SDOperand(0,0); 5004 5005 // If this isn't a constant element or an undef, we can't use a constant 5006 // pool load. 5007 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 5008 V.getOpcode() != ISD::UNDEF) 5009 isConstant = false; 5010 } 5011 5012 if (isOnlyLowElement) { 5013 // If the low element is an undef too, then this whole things is an undef. 5014 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 5015 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 5016 // Otherwise, turn this into a scalar_to_vector node. 5017 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 5018 Node->getOperand(0)); 5019 } 5020 5021 // If all elements are constants, create a load from the constant pool. 5022 if (isConstant) { 5023 MVT::ValueType VT = Node->getValueType(0); 5024 const Type *OpNTy = 5025 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 5026 std::vector<Constant*> CV; 5027 for (unsigned i = 0, e = NumElems; i != e; ++i) { 5028 if (ConstantFPSDNode *V = 5029 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 5030 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF())); 5031 } else if (ConstantSDNode *V = 5032 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 5033 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 5034 } else { 5035 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 5036 CV.push_back(UndefValue::get(OpNTy)); 5037 } 5038 } 5039 Constant *CP = ConstantVector::get(CV); 5040 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 5041 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 5042 PseudoSourceValue::getConstantPool(), 0); 5043 } 5044 5045 if (SplatValue.Val) { // Splat of one value? 5046 // Build the shuffle constant vector: <0, 0, 0, 0> 5047 MVT::ValueType MaskVT = 5048 MVT::getIntVectorWithNumElements(NumElems); 5049 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 5050 std::vector<SDOperand> ZeroVec(NumElems, Zero); 5051 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5052 &ZeroVec[0], ZeroVec.size()); 5053 5054 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 5055 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 5056 // Get the splatted value into the low element of a vector register. 5057 SDOperand LowValVec = 5058 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 5059 5060 // Return shuffle(LowValVec, undef, <0,0,0,0>) 5061 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 5062 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 5063 SplatMask); 5064 } 5065 } 5066 5067 // If there are only two unique elements, we may be able to turn this into a 5068 // vector shuffle. 5069 if (Values.size() == 2) { 5070 // Get the two values in deterministic order. 5071 SDOperand Val1 = Node->getOperand(1); 5072 SDOperand Val2; 5073 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin(); 5074 if (MI->first != Val1) 5075 Val2 = MI->first; 5076 else 5077 Val2 = (++MI)->first; 5078 5079 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 5080 // vector shuffle has the undef vector on the RHS. 5081 if (Val1.getOpcode() == ISD::UNDEF) 5082 std::swap(Val1, Val2); 5083 5084 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 5085 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5086 MVT::ValueType MaskEltVT = MVT::getVectorElementType(MaskVT); 5087 std::vector<SDOperand> MaskVec(NumElems); 5088 5089 // Set elements of the shuffle mask for Val1. 5090 std::vector<unsigned> &Val1Elts = Values[Val1]; 5091 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 5092 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 5093 5094 // Set elements of the shuffle mask for Val2. 5095 std::vector<unsigned> &Val2Elts = Values[Val2]; 5096 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 5097 if (Val2.getOpcode() != ISD::UNDEF) 5098 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 5099 else 5100 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); 5101 5102 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5103 &MaskVec[0], MaskVec.size()); 5104 5105 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 5106 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 5107 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 5108 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); 5109 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); 5110 SDOperand Ops[] = { Val1, Val2, ShuffleMask }; 5111 5112 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 5113 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); 5114 } 5115 } 5116 5117 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5118 // aligned object on the stack, store each element into it, then load 5119 // the result as a vector. 5120 MVT::ValueType VT = Node->getValueType(0); 5121 // Create the stack frame object. 5122 SDOperand FIPtr = DAG.CreateStackTemporary(VT); 5123 5124 // Emit a store of each element to the stack slot. 5125 SmallVector<SDOperand, 8> Stores; 5126 unsigned TypeByteSize = 5127 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 5128 // Store (in the right endianness) the elements to memory. 5129 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5130 // Ignore undef elements. 5131 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5132 5133 unsigned Offset = TypeByteSize*i; 5134 5135 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5136 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 5137 5138 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 5139 NULL, 0)); 5140 } 5141 5142 SDOperand StoreChain; 5143 if (!Stores.empty()) // Not all undef elements? 5144 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5145 &Stores[0], Stores.size()); 5146 else 5147 StoreChain = DAG.getEntryNode(); 5148 5149 // Result is a load from the stack slot. 5150 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 5151} 5152 5153void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5154 SDOperand Op, SDOperand Amt, 5155 SDOperand &Lo, SDOperand &Hi) { 5156 // Expand the subcomponents. 5157 SDOperand LHSL, LHSH; 5158 ExpandOp(Op, LHSL, LHSH); 5159 5160 SDOperand Ops[] = { LHSL, LHSH, Amt }; 5161 MVT::ValueType VT = LHSL.getValueType(); 5162 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5163 Hi = Lo.getValue(1); 5164} 5165 5166 5167/// ExpandShift - Try to find a clever way to expand this shift operation out to 5168/// smaller elements. If we can't find a way that is more efficient than a 5169/// libcall on this target, return false. Otherwise, return true with the 5170/// low-parts expanded into Lo and Hi. 5171bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 5172 SDOperand &Lo, SDOperand &Hi) { 5173 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5174 "This is not a shift!"); 5175 5176 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5177 SDOperand ShAmt = LegalizeOp(Amt); 5178 MVT::ValueType ShTy = ShAmt.getValueType(); 5179 unsigned ShBits = MVT::getSizeInBits(ShTy); 5180 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 5181 unsigned NVTBits = MVT::getSizeInBits(NVT); 5182 5183 // Handle the case when Amt is an immediate. 5184 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 5185 unsigned Cst = CN->getValue(); 5186 // Expand the incoming operand to be shifted, so that we have its parts 5187 SDOperand InL, InH; 5188 ExpandOp(Op, InL, InH); 5189 switch(Opc) { 5190 case ISD::SHL: 5191 if (Cst > VTBits) { 5192 Lo = DAG.getConstant(0, NVT); 5193 Hi = DAG.getConstant(0, NVT); 5194 } else if (Cst > NVTBits) { 5195 Lo = DAG.getConstant(0, NVT); 5196 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5197 } else if (Cst == NVTBits) { 5198 Lo = DAG.getConstant(0, NVT); 5199 Hi = InL; 5200 } else { 5201 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5202 Hi = DAG.getNode(ISD::OR, NVT, 5203 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5204 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5205 } 5206 return true; 5207 case ISD::SRL: 5208 if (Cst > VTBits) { 5209 Lo = DAG.getConstant(0, NVT); 5210 Hi = DAG.getConstant(0, NVT); 5211 } else if (Cst > NVTBits) { 5212 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5213 Hi = DAG.getConstant(0, NVT); 5214 } else if (Cst == NVTBits) { 5215 Lo = InH; 5216 Hi = DAG.getConstant(0, NVT); 5217 } else { 5218 Lo = DAG.getNode(ISD::OR, NVT, 5219 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5220 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5221 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5222 } 5223 return true; 5224 case ISD::SRA: 5225 if (Cst > VTBits) { 5226 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5227 DAG.getConstant(NVTBits-1, ShTy)); 5228 } else if (Cst > NVTBits) { 5229 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5230 DAG.getConstant(Cst-NVTBits, ShTy)); 5231 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5232 DAG.getConstant(NVTBits-1, ShTy)); 5233 } else if (Cst == NVTBits) { 5234 Lo = InH; 5235 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5236 DAG.getConstant(NVTBits-1, ShTy)); 5237 } else { 5238 Lo = DAG.getNode(ISD::OR, NVT, 5239 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5240 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5241 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5242 } 5243 return true; 5244 } 5245 } 5246 5247 // Okay, the shift amount isn't constant. However, if we can tell that it is 5248 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5249 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5250 APInt KnownZero, KnownOne; 5251 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5252 5253 // If we know that if any of the high bits of the shift amount are one, then 5254 // we can do this as a couple of simple shifts. 5255 if (KnownOne.intersects(Mask)) { 5256 // Mask out the high bit, which we know is set. 5257 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5258 DAG.getConstant(~Mask, Amt.getValueType())); 5259 5260 // Expand the incoming operand to be shifted, so that we have its parts 5261 SDOperand InL, InH; 5262 ExpandOp(Op, InL, InH); 5263 switch(Opc) { 5264 case ISD::SHL: 5265 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5266 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5267 return true; 5268 case ISD::SRL: 5269 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5270 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5271 return true; 5272 case ISD::SRA: 5273 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5274 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5275 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5276 return true; 5277 } 5278 } 5279 5280 // If we know that the high bits of the shift amount are all zero, then we can 5281 // do this as a couple of simple shifts. 5282 if ((KnownZero & Mask) == Mask) { 5283 // Compute 32-amt. 5284 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5285 DAG.getConstant(NVTBits, Amt.getValueType()), 5286 Amt); 5287 5288 // Expand the incoming operand to be shifted, so that we have its parts 5289 SDOperand InL, InH; 5290 ExpandOp(Op, InL, InH); 5291 switch(Opc) { 5292 case ISD::SHL: 5293 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5294 Hi = DAG.getNode(ISD::OR, NVT, 5295 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5296 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5297 return true; 5298 case ISD::SRL: 5299 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5300 Lo = DAG.getNode(ISD::OR, NVT, 5301 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5302 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5303 return true; 5304 case ISD::SRA: 5305 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5306 Lo = DAG.getNode(ISD::OR, NVT, 5307 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5308 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5309 return true; 5310 } 5311 } 5312 5313 return false; 5314} 5315 5316 5317// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5318// does not fit into a register, return the lo part and set the hi part to the 5319// by-reg argument. If it does fit into a single register, return the result 5320// and leave the Hi part unset. 5321SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 5322 bool isSigned, SDOperand &Hi) { 5323 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5324 // The input chain to this libcall is the entry node of the function. 5325 // Legalizing the call will automatically add the previous call to the 5326 // dependence. 5327 SDOperand InChain = DAG.getEntryNode(); 5328 5329 TargetLowering::ArgListTy Args; 5330 TargetLowering::ArgListEntry Entry; 5331 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5332 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 5333 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 5334 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5335 Entry.isSExt = isSigned; 5336 Entry.isZExt = !isSigned; 5337 Args.push_back(Entry); 5338 } 5339 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 5340 5341 // Splice the libcall in wherever FindInputOutputChains tells us to. 5342 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 5343 std::pair<SDOperand,SDOperand> CallInfo = 5344 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C, 5345 false, Callee, Args, DAG); 5346 5347 // Legalize the call sequence, starting with the chain. This will advance 5348 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5349 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5350 LegalizeOp(CallInfo.second); 5351 SDOperand Result; 5352 switch (getTypeAction(CallInfo.first.getValueType())) { 5353 default: assert(0 && "Unknown thing"); 5354 case Legal: 5355 Result = CallInfo.first; 5356 break; 5357 case Expand: 5358 ExpandOp(CallInfo.first, Result, Hi); 5359 break; 5360 } 5361 return Result; 5362} 5363 5364 5365/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5366/// 5367SDOperand SelectionDAGLegalize:: 5368ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 5369 MVT::ValueType SourceVT = Source.getValueType(); 5370 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5371 5372 if (!isSigned) { 5373 // The integer value loaded will be incorrectly if the 'sign bit' of the 5374 // incoming integer is set. To handle this, we dynamically test to see if 5375 // it is set, and, if so, add a fudge factor. 5376 SDOperand Hi; 5377 if (ExpandSource) { 5378 SDOperand Lo; 5379 ExpandOp(Source, Lo, Hi); 5380 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); 5381 } else { 5382 // The comparison for the sign bit will use the entire operand. 5383 Hi = Source; 5384 } 5385 5386 // If this is unsigned, and not supported, first perform the conversion to 5387 // signed, then adjust the result if the sign bit is set. 5388 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source); 5389 5390 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 5391 DAG.getConstant(0, Hi.getValueType()), 5392 ISD::SETLT); 5393 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5394 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5395 SignSet, Four, Zero); 5396 uint64_t FF = 0x5f800000ULL; 5397 if (TLI.isLittleEndian()) FF <<= 32; 5398 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5399 5400 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5401 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5402 SDOperand FudgeInReg; 5403 if (DestTy == MVT::f32) 5404 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5405 PseudoSourceValue::getConstantPool(), 0); 5406 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) 5407 // FIXME: Avoid the extend by construction the right constantpool? 5408 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5409 CPIdx, 5410 PseudoSourceValue::getConstantPool(), 0, 5411 MVT::f32); 5412 else 5413 assert(0 && "Unexpected conversion"); 5414 5415 MVT::ValueType SCVT = SignedConv.getValueType(); 5416 if (SCVT != DestTy) { 5417 // Destination type needs to be expanded as well. The FADD now we are 5418 // constructing will be expanded into a libcall. 5419 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 5420 assert(MVT::getSizeInBits(SCVT) * 2 == MVT::getSizeInBits(DestTy)); 5421 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, 5422 SignedConv, SignedConv.getValue(1)); 5423 } 5424 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5425 } 5426 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5427 } 5428 5429 // Check to see if the target has a custom way to lower this. If so, use it. 5430 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 5431 default: assert(0 && "This action not implemented for this operation!"); 5432 case TargetLowering::Legal: 5433 case TargetLowering::Expand: 5434 break; // This case is handled below. 5435 case TargetLowering::Custom: { 5436 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5437 Source), DAG); 5438 if (NV.Val) 5439 return LegalizeOp(NV); 5440 break; // The target decided this was legal after all 5441 } 5442 } 5443 5444 // Expand the source, then glue it back together for the call. We must expand 5445 // the source in case it is shared (this pass of legalize must traverse it). 5446 if (ExpandSource) { 5447 SDOperand SrcLo, SrcHi; 5448 ExpandOp(Source, SrcLo, SrcHi); 5449 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); 5450 } 5451 5452 RTLIB::Libcall LC; 5453 if (SourceVT == MVT::i64) { 5454 if (DestTy == MVT::f32) 5455 LC = RTLIB::SINTTOFP_I64_F32; 5456 else if (DestTy == MVT::f64) 5457 LC = RTLIB::SINTTOFP_I64_F64; 5458 else if (DestTy == MVT::f80) 5459 LC = RTLIB::SINTTOFP_I64_F80; 5460 else { 5461 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 5462 LC = RTLIB::SINTTOFP_I64_PPCF128; 5463 } 5464 } else if (SourceVT == MVT::i128) { 5465 if (DestTy == MVT::f32) 5466 LC = RTLIB::SINTTOFP_I128_F32; 5467 else if (DestTy == MVT::f64) 5468 LC = RTLIB::SINTTOFP_I128_F64; 5469 else if (DestTy == MVT::f80) 5470 LC = RTLIB::SINTTOFP_I128_F80; 5471 else { 5472 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 5473 LC = RTLIB::SINTTOFP_I128_PPCF128; 5474 } 5475 } else { 5476 assert(0 && "Unknown int value type"); 5477 } 5478 5479 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 5480 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5481 SDOperand HiPart; 5482 SDOperand Result = ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 5483 HiPart); 5484 if (Result.getValueType() != DestTy) 5485 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); 5486 return Result; 5487} 5488 5489/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5490/// INT_TO_FP operation of the specified operand when the target requests that 5491/// we expand it. At this point, we know that the result and operand types are 5492/// legal for the target. 5493SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5494 SDOperand Op0, 5495 MVT::ValueType DestVT) { 5496 if (Op0.getValueType() == MVT::i32) { 5497 // simple 32-bit [signed|unsigned] integer to float/double expansion 5498 5499 // Get the stack frame index of a 8 byte buffer. 5500 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64); 5501 5502 // word offset constant for Hi/Lo address computation 5503 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5504 // set up Hi and Lo (into buffer) address based on endian 5505 SDOperand Hi = StackSlot; 5506 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5507 if (TLI.isLittleEndian()) 5508 std::swap(Hi, Lo); 5509 5510 // if signed map to unsigned space 5511 SDOperand Op0Mapped; 5512 if (isSigned) { 5513 // constant used to invert sign bit (signed to unsigned mapping) 5514 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5515 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5516 } else { 5517 Op0Mapped = Op0; 5518 } 5519 // store the lo of the constructed double - based on integer input 5520 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 5521 Op0Mapped, Lo, NULL, 0); 5522 // initial hi portion of constructed double 5523 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5524 // store the hi of the constructed double - biased exponent 5525 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5526 // load the constructed double 5527 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5528 // FP constant to bias correct the final result 5529 SDOperand Bias = DAG.getConstantFP(isSigned ? 5530 BitsToDouble(0x4330000080000000ULL) 5531 : BitsToDouble(0x4330000000000000ULL), 5532 MVT::f64); 5533 // subtract the bias 5534 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5535 // final result 5536 SDOperand Result; 5537 // handle final rounding 5538 if (DestVT == MVT::f64) { 5539 // do nothing 5540 Result = Sub; 5541 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { 5542 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 5543 DAG.getIntPtrConstant(0)); 5544 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { 5545 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5546 } 5547 return Result; 5548 } 5549 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5550 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5551 5552 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0, 5553 DAG.getConstant(0, Op0.getValueType()), 5554 ISD::SETLT); 5555 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5556 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5557 SignSet, Four, Zero); 5558 5559 // If the sign bit of the integer is set, the large number will be treated 5560 // as a negative number. To counteract this, the dynamic code adds an 5561 // offset depending on the data type. 5562 uint64_t FF; 5563 switch (Op0.getValueType()) { 5564 default: assert(0 && "Unsupported integer type!"); 5565 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5566 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5567 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5568 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5569 } 5570 if (TLI.isLittleEndian()) FF <<= 32; 5571 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5572 5573 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5574 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5575 SDOperand FudgeInReg; 5576 if (DestVT == MVT::f32) 5577 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5578 PseudoSourceValue::getConstantPool(), 0); 5579 else { 5580 FudgeInReg = 5581 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5582 DAG.getEntryNode(), CPIdx, 5583 PseudoSourceValue::getConstantPool(), 0, 5584 MVT::f32)); 5585 } 5586 5587 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5588} 5589 5590/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5591/// *INT_TO_FP operation of the specified operand when the target requests that 5592/// we promote it. At this point, we know that the result and operand types are 5593/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5594/// operation that takes a larger input. 5595SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5596 MVT::ValueType DestVT, 5597 bool isSigned) { 5598 // First step, figure out the appropriate *INT_TO_FP operation to use. 5599 MVT::ValueType NewInTy = LegalOp.getValueType(); 5600 5601 unsigned OpToUse = 0; 5602 5603 // Scan for the appropriate larger type to use. 5604 while (1) { 5605 NewInTy = (MVT::ValueType)(NewInTy+1); 5606 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 5607 5608 // If the target supports SINT_TO_FP of this type, use it. 5609 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5610 default: break; 5611 case TargetLowering::Legal: 5612 if (!TLI.isTypeLegal(NewInTy)) 5613 break; // Can't use this datatype. 5614 // FALL THROUGH. 5615 case TargetLowering::Custom: 5616 OpToUse = ISD::SINT_TO_FP; 5617 break; 5618 } 5619 if (OpToUse) break; 5620 if (isSigned) continue; 5621 5622 // If the target supports UINT_TO_FP of this type, use it. 5623 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5624 default: break; 5625 case TargetLowering::Legal: 5626 if (!TLI.isTypeLegal(NewInTy)) 5627 break; // Can't use this datatype. 5628 // FALL THROUGH. 5629 case TargetLowering::Custom: 5630 OpToUse = ISD::UINT_TO_FP; 5631 break; 5632 } 5633 if (OpToUse) break; 5634 5635 // Otherwise, try a larger type. 5636 } 5637 5638 // Okay, we found the operation and type to use. Zero extend our input to the 5639 // desired type then run the operation on it. 5640 return DAG.getNode(OpToUse, DestVT, 5641 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5642 NewInTy, LegalOp)); 5643} 5644 5645/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5646/// FP_TO_*INT operation of the specified operand when the target requests that 5647/// we promote it. At this point, we know that the result and operand types are 5648/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5649/// operation that returns a larger result. 5650SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5651 MVT::ValueType DestVT, 5652 bool isSigned) { 5653 // First step, figure out the appropriate FP_TO*INT operation to use. 5654 MVT::ValueType NewOutTy = DestVT; 5655 5656 unsigned OpToUse = 0; 5657 5658 // Scan for the appropriate larger type to use. 5659 while (1) { 5660 NewOutTy = (MVT::ValueType)(NewOutTy+1); 5661 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 5662 5663 // If the target supports FP_TO_SINT returning this type, use it. 5664 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5665 default: break; 5666 case TargetLowering::Legal: 5667 if (!TLI.isTypeLegal(NewOutTy)) 5668 break; // Can't use this datatype. 5669 // FALL THROUGH. 5670 case TargetLowering::Custom: 5671 OpToUse = ISD::FP_TO_SINT; 5672 break; 5673 } 5674 if (OpToUse) break; 5675 5676 // If the target supports FP_TO_UINT of this type, use it. 5677 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5678 default: break; 5679 case TargetLowering::Legal: 5680 if (!TLI.isTypeLegal(NewOutTy)) 5681 break; // Can't use this datatype. 5682 // FALL THROUGH. 5683 case TargetLowering::Custom: 5684 OpToUse = ISD::FP_TO_UINT; 5685 break; 5686 } 5687 if (OpToUse) break; 5688 5689 // Otherwise, try a larger type. 5690 } 5691 5692 5693 // Okay, we found the operation and type to use. 5694 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5695 5696 // If the operation produces an invalid type, it must be custom lowered. Use 5697 // the target lowering hooks to expand it. Just keep the low part of the 5698 // expanded operation, we know that we're truncating anyway. 5699 if (getTypeAction(NewOutTy) == Expand) { 5700 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0); 5701 assert(Operation.Val && "Didn't return anything"); 5702 } 5703 5704 // Truncate the result of the extended FP_TO_*INT operation to the desired 5705 // size. 5706 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5707} 5708 5709/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5710/// 5711SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5712 MVT::ValueType VT = Op.getValueType(); 5713 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 5714 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5715 switch (VT) { 5716 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5717 case MVT::i16: 5718 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5719 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5720 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5721 case MVT::i32: 5722 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5723 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5724 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5725 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5726 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5727 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5728 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5729 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5730 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5731 case MVT::i64: 5732 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5733 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5734 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5735 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5736 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5737 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5738 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5739 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5740 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5741 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5742 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5743 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5744 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5745 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5746 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5747 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5748 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5749 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5750 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5751 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5752 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5753 } 5754} 5755 5756/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5757/// 5758SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5759 switch (Opc) { 5760 default: assert(0 && "Cannot expand this yet!"); 5761 case ISD::CTPOP: { 5762 static const uint64_t mask[6] = { 5763 0x5555555555555555ULL, 0x3333333333333333ULL, 5764 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5765 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5766 }; 5767 MVT::ValueType VT = Op.getValueType(); 5768 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5769 unsigned len = MVT::getSizeInBits(VT); 5770 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5771 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5772 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5773 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5774 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5775 DAG.getNode(ISD::AND, VT, 5776 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5777 } 5778 return Op; 5779 } 5780 case ISD::CTLZ: { 5781 // for now, we do this: 5782 // x = x | (x >> 1); 5783 // x = x | (x >> 2); 5784 // ... 5785 // x = x | (x >>16); 5786 // x = x | (x >>32); // for 64-bit input 5787 // return popcount(~x); 5788 // 5789 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5790 MVT::ValueType VT = Op.getValueType(); 5791 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5792 unsigned len = MVT::getSizeInBits(VT); 5793 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5794 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5795 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5796 } 5797 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5798 return DAG.getNode(ISD::CTPOP, VT, Op); 5799 } 5800 case ISD::CTTZ: { 5801 // for now, we use: { return popcount(~x & (x - 1)); } 5802 // unless the target has ctlz but not ctpop, in which case we use: 5803 // { return 32 - nlz(~x & (x-1)); } 5804 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5805 MVT::ValueType VT = Op.getValueType(); 5806 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5807 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5808 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5809 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5810 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5811 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5812 TLI.isOperationLegal(ISD::CTLZ, VT)) 5813 return DAG.getNode(ISD::SUB, VT, 5814 DAG.getConstant(MVT::getSizeInBits(VT), VT), 5815 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5816 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5817 } 5818 } 5819} 5820 5821/// ExpandOp - Expand the specified SDOperand into its two component pieces 5822/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5823/// LegalizeNodes map is filled in for any results that are not expanded, the 5824/// ExpandedNodes map is filled in for any results that are expanded, and the 5825/// Lo/Hi values are returned. 5826void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5827 MVT::ValueType VT = Op.getValueType(); 5828 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 5829 SDNode *Node = Op.Val; 5830 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5831 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 5832 MVT::isVector(VT)) && 5833 "Cannot expand to FP value or to larger int value!"); 5834 5835 // See if we already expanded it. 5836 DenseMap<SDOperandImpl, std::pair<SDOperand, SDOperand> >::iterator I 5837 = ExpandedNodes.find(Op); 5838 if (I != ExpandedNodes.end()) { 5839 Lo = I->second.first; 5840 Hi = I->second.second; 5841 return; 5842 } 5843 5844 switch (Node->getOpcode()) { 5845 case ISD::CopyFromReg: 5846 assert(0 && "CopyFromReg must be legal!"); 5847 case ISD::FP_ROUND_INREG: 5848 if (VT == MVT::ppcf128 && 5849 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5850 TargetLowering::Custom) { 5851 SDOperand SrcLo, SrcHi, Src; 5852 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5853 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5854 SDOperand Result = TLI.LowerOperation( 5855 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5856 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5857 Lo = Result.Val->getOperand(0); 5858 Hi = Result.Val->getOperand(1); 5859 break; 5860 } 5861 // fall through 5862 default: 5863#ifndef NDEBUG 5864 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5865#endif 5866 assert(0 && "Do not know how to expand this operator!"); 5867 abort(); 5868 case ISD::EXTRACT_ELEMENT: 5869 ExpandOp(Node->getOperand(0), Lo, Hi); 5870 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 5871 return ExpandOp(Hi, Lo, Hi); 5872 return ExpandOp(Lo, Lo, Hi); 5873 case ISD::EXTRACT_VECTOR_ELT: 5874 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5875 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5876 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5877 return ExpandOp(Lo, Lo, Hi); 5878 case ISD::UNDEF: 5879 NVT = TLI.getTypeToExpandTo(VT); 5880 Lo = DAG.getNode(ISD::UNDEF, NVT); 5881 Hi = DAG.getNode(ISD::UNDEF, NVT); 5882 break; 5883 case ISD::Constant: { 5884 unsigned NVTBits = MVT::getSizeInBits(NVT); 5885 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 5886 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 5887 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 5888 break; 5889 } 5890 case ISD::ConstantFP: { 5891 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5892 if (CFP->getValueType(0) == MVT::ppcf128) { 5893 APInt api = CFP->getValueAPF().convertToAPInt(); 5894 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5895 MVT::f64); 5896 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5897 MVT::f64); 5898 break; 5899 } 5900 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5901 if (getTypeAction(Lo.getValueType()) == Expand) 5902 ExpandOp(Lo, Lo, Hi); 5903 break; 5904 } 5905 case ISD::BUILD_PAIR: 5906 // Return the operands. 5907 Lo = Node->getOperand(0); 5908 Hi = Node->getOperand(1); 5909 break; 5910 5911 case ISD::MERGE_VALUES: 5912 if (Node->getNumValues() == 1) { 5913 ExpandOp(Op.getOperand(0), Lo, Hi); 5914 break; 5915 } 5916 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5917 assert(Op.ResNo == 0 && Node->getNumValues() == 2 && 5918 Op.getValue(1).getValueType() == MVT::Other && 5919 "unhandled MERGE_VALUES"); 5920 ExpandOp(Op.getOperand(0), Lo, Hi); 5921 // Remember that we legalized the chain. 5922 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5923 break; 5924 5925 case ISD::SIGN_EXTEND_INREG: 5926 ExpandOp(Node->getOperand(0), Lo, Hi); 5927 // sext_inreg the low part if needed. 5928 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5929 5930 // The high part gets the sign extension from the lo-part. This handles 5931 // things like sextinreg V:i64 from i8. 5932 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5933 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 5934 TLI.getShiftAmountTy())); 5935 break; 5936 5937 case ISD::BSWAP: { 5938 ExpandOp(Node->getOperand(0), Lo, Hi); 5939 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5940 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5941 Lo = TempLo; 5942 break; 5943 } 5944 5945 case ISD::CTPOP: 5946 ExpandOp(Node->getOperand(0), Lo, Hi); 5947 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5948 DAG.getNode(ISD::CTPOP, NVT, Lo), 5949 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5950 Hi = DAG.getConstant(0, NVT); 5951 break; 5952 5953 case ISD::CTLZ: { 5954 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5955 ExpandOp(Node->getOperand(0), Lo, Hi); 5956 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5957 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5958 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, 5959 ISD::SETNE); 5960 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5961 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5962 5963 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5964 Hi = DAG.getConstant(0, NVT); 5965 break; 5966 } 5967 5968 case ISD::CTTZ: { 5969 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5970 ExpandOp(Node->getOperand(0), Lo, Hi); 5971 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5972 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5973 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, 5974 ISD::SETNE); 5975 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5976 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5977 5978 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5979 Hi = DAG.getConstant(0, NVT); 5980 break; 5981 } 5982 5983 case ISD::VAARG: { 5984 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5985 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5986 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5987 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5988 5989 // Remember that we legalized the chain. 5990 Hi = LegalizeOp(Hi); 5991 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5992 if (TLI.isBigEndian()) 5993 std::swap(Lo, Hi); 5994 break; 5995 } 5996 5997 case ISD::LOAD: { 5998 LoadSDNode *LD = cast<LoadSDNode>(Node); 5999 SDOperand Ch = LD->getChain(); // Legalize the chain. 6000 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 6001 ISD::LoadExtType ExtType = LD->getExtensionType(); 6002 int SVOffset = LD->getSrcValueOffset(); 6003 unsigned Alignment = LD->getAlignment(); 6004 bool isVolatile = LD->isVolatile(); 6005 6006 if (ExtType == ISD::NON_EXTLOAD) { 6007 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 6008 isVolatile, Alignment); 6009 if (VT == MVT::f32 || VT == MVT::f64) { 6010 // f32->i32 or f64->i64 one to one expansion. 6011 // Remember that we legalized the chain. 6012 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 6013 // Recursively expand the new load. 6014 if (getTypeAction(NVT) == Expand) 6015 ExpandOp(Lo, Lo, Hi); 6016 break; 6017 } 6018 6019 // Increment the pointer to the other half. 6020 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 6021 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6022 DAG.getIntPtrConstant(IncrementSize)); 6023 SVOffset += IncrementSize; 6024 Alignment = MinAlign(Alignment, IncrementSize); 6025 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 6026 isVolatile, Alignment); 6027 6028 // Build a factor node to remember that this load is independent of the 6029 // other one. 6030 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6031 Hi.getValue(1)); 6032 6033 // Remember that we legalized the chain. 6034 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6035 if (TLI.isBigEndian()) 6036 std::swap(Lo, Hi); 6037 } else { 6038 MVT::ValueType EVT = LD->getMemoryVT(); 6039 6040 if ((VT == MVT::f64 && EVT == MVT::f32) || 6041 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 6042 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 6043 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 6044 SVOffset, isVolatile, Alignment); 6045 // Remember that we legalized the chain. 6046 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 6047 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 6048 break; 6049 } 6050 6051 if (EVT == NVT) 6052 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 6053 SVOffset, isVolatile, Alignment); 6054 else 6055 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 6056 SVOffset, EVT, isVolatile, 6057 Alignment); 6058 6059 // Remember that we legalized the chain. 6060 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 6061 6062 if (ExtType == ISD::SEXTLOAD) { 6063 // The high part is obtained by SRA'ing all but one of the bits of the 6064 // lo part. 6065 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 6066 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6067 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6068 } else if (ExtType == ISD::ZEXTLOAD) { 6069 // The high part is just a zero. 6070 Hi = DAG.getConstant(0, NVT); 6071 } else /* if (ExtType == ISD::EXTLOAD) */ { 6072 // The high part is undefined. 6073 Hi = DAG.getNode(ISD::UNDEF, NVT); 6074 } 6075 } 6076 break; 6077 } 6078 case ISD::AND: 6079 case ISD::OR: 6080 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6081 SDOperand LL, LH, RL, RH; 6082 ExpandOp(Node->getOperand(0), LL, LH); 6083 ExpandOp(Node->getOperand(1), RL, RH); 6084 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 6085 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 6086 break; 6087 } 6088 case ISD::SELECT: { 6089 SDOperand LL, LH, RL, RH; 6090 ExpandOp(Node->getOperand(1), LL, LH); 6091 ExpandOp(Node->getOperand(2), RL, RH); 6092 if (getTypeAction(NVT) == Expand) 6093 NVT = TLI.getTypeToExpandTo(NVT); 6094 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 6095 if (VT != MVT::f32) 6096 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 6097 break; 6098 } 6099 case ISD::SELECT_CC: { 6100 SDOperand TL, TH, FL, FH; 6101 ExpandOp(Node->getOperand(2), TL, TH); 6102 ExpandOp(Node->getOperand(3), FL, FH); 6103 if (getTypeAction(NVT) == Expand) 6104 NVT = TLI.getTypeToExpandTo(NVT); 6105 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6106 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6107 if (VT != MVT::f32) 6108 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6109 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6110 break; 6111 } 6112 case ISD::ANY_EXTEND: 6113 // The low part is any extension of the input (which degenerates to a copy). 6114 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 6115 // The high part is undefined. 6116 Hi = DAG.getNode(ISD::UNDEF, NVT); 6117 break; 6118 case ISD::SIGN_EXTEND: { 6119 // The low part is just a sign extension of the input (which degenerates to 6120 // a copy). 6121 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 6122 6123 // The high part is obtained by SRA'ing all but one of the bits of the lo 6124 // part. 6125 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 6126 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6127 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6128 break; 6129 } 6130 case ISD::ZERO_EXTEND: 6131 // The low part is just a zero extension of the input (which degenerates to 6132 // a copy). 6133 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 6134 6135 // The high part is just a zero. 6136 Hi = DAG.getConstant(0, NVT); 6137 break; 6138 6139 case ISD::TRUNCATE: { 6140 // The input value must be larger than this value. Expand *it*. 6141 SDOperand NewLo; 6142 ExpandOp(Node->getOperand(0), NewLo, Hi); 6143 6144 // The low part is now either the right size, or it is closer. If not the 6145 // right size, make an illegal truncate so we recursively expand it. 6146 if (NewLo.getValueType() != Node->getValueType(0)) 6147 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 6148 ExpandOp(NewLo, Lo, Hi); 6149 break; 6150 } 6151 6152 case ISD::BIT_CONVERT: { 6153 SDOperand Tmp; 6154 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6155 // If the target wants to, allow it to lower this itself. 6156 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6157 case Expand: assert(0 && "cannot expand FP!"); 6158 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6159 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6160 } 6161 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 6162 } 6163 6164 // f32 / f64 must be expanded to i32 / i64. 6165 if (VT == MVT::f32 || VT == MVT::f64) { 6166 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6167 if (getTypeAction(NVT) == Expand) 6168 ExpandOp(Lo, Lo, Hi); 6169 break; 6170 } 6171 6172 // If source operand will be expanded to the same type as VT, i.e. 6173 // i64 <- f64, i32 <- f32, expand the source operand instead. 6174 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 6175 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6176 ExpandOp(Node->getOperand(0), Lo, Hi); 6177 break; 6178 } 6179 6180 // Turn this into a load/store pair by default. 6181 if (Tmp.Val == 0) 6182 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 6183 6184 ExpandOp(Tmp, Lo, Hi); 6185 break; 6186 } 6187 6188 case ISD::READCYCLECOUNTER: { 6189 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6190 TargetLowering::Custom && 6191 "Must custom expand ReadCycleCounter"); 6192 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 6193 assert(Tmp.Val && "Node must be custom expanded!"); 6194 ExpandOp(Tmp.getValue(0), Lo, Hi); 6195 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6196 LegalizeOp(Tmp.getValue(1))); 6197 break; 6198 } 6199 6200 case ISD::ATOMIC_LCS: { 6201 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 6202 assert(Tmp.Val && "Node must be custom expanded!"); 6203 ExpandOp(Tmp.getValue(0), Lo, Hi); 6204 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6205 LegalizeOp(Tmp.getValue(1))); 6206 break; 6207 } 6208 6209 6210 6211 // These operators cannot be expanded directly, emit them as calls to 6212 // library functions. 6213 case ISD::FP_TO_SINT: { 6214 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6215 SDOperand Op; 6216 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6217 case Expand: assert(0 && "cannot expand FP!"); 6218 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6219 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6220 } 6221 6222 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6223 6224 // Now that the custom expander is done, expand the result, which is still 6225 // VT. 6226 if (Op.Val) { 6227 ExpandOp(Op, Lo, Hi); 6228 break; 6229 } 6230 } 6231 6232 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6233 if (VT == MVT::i64) { 6234 if (Node->getOperand(0).getValueType() == MVT::f32) 6235 LC = RTLIB::FPTOSINT_F32_I64; 6236 else if (Node->getOperand(0).getValueType() == MVT::f64) 6237 LC = RTLIB::FPTOSINT_F64_I64; 6238 else if (Node->getOperand(0).getValueType() == MVT::f80) 6239 LC = RTLIB::FPTOSINT_F80_I64; 6240 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6241 LC = RTLIB::FPTOSINT_PPCF128_I64; 6242 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 6243 false/*sign irrelevant*/, Hi); 6244 } else if (VT == MVT::i128) { 6245 if (Node->getOperand(0).getValueType() == MVT::f32) 6246 LC = RTLIB::FPTOSINT_F32_I128; 6247 else if (Node->getOperand(0).getValueType() == MVT::f64) 6248 LC = RTLIB::FPTOSINT_F64_I128; 6249 else if (Node->getOperand(0).getValueType() == MVT::f80) 6250 LC = RTLIB::FPTOSINT_F80_I128; 6251 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6252 LC = RTLIB::FPTOSINT_PPCF128_I128; 6253 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 6254 false/*sign irrelevant*/, Hi); 6255 } else { 6256 assert(0 && "Unexpected uint-to-fp conversion!"); 6257 } 6258 break; 6259 } 6260 6261 case ISD::FP_TO_UINT: { 6262 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6263 SDOperand Op; 6264 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6265 case Expand: assert(0 && "cannot expand FP!"); 6266 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6267 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6268 } 6269 6270 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6271 6272 // Now that the custom expander is done, expand the result. 6273 if (Op.Val) { 6274 ExpandOp(Op, Lo, Hi); 6275 break; 6276 } 6277 } 6278 6279 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6280 if (VT == MVT::i64) { 6281 if (Node->getOperand(0).getValueType() == MVT::f32) 6282 LC = RTLIB::FPTOUINT_F32_I64; 6283 else if (Node->getOperand(0).getValueType() == MVT::f64) 6284 LC = RTLIB::FPTOUINT_F64_I64; 6285 else if (Node->getOperand(0).getValueType() == MVT::f80) 6286 LC = RTLIB::FPTOUINT_F80_I64; 6287 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6288 LC = RTLIB::FPTOUINT_PPCF128_I64; 6289 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 6290 false/*sign irrelevant*/, Hi); 6291 } else if (VT == MVT::i128) { 6292 if (Node->getOperand(0).getValueType() == MVT::f32) 6293 LC = RTLIB::FPTOUINT_F32_I128; 6294 else if (Node->getOperand(0).getValueType() == MVT::f64) 6295 LC = RTLIB::FPTOUINT_F64_I128; 6296 else if (Node->getOperand(0).getValueType() == MVT::f80) 6297 LC = RTLIB::FPTOUINT_F80_I128; 6298 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6299 LC = RTLIB::FPTOUINT_PPCF128_I128; 6300 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 6301 false/*sign irrelevant*/, Hi); 6302 } else { 6303 assert(0 && "Unexpected uint-to-fp conversion!"); 6304 } 6305 break; 6306 } 6307 6308 case ISD::SHL: { 6309 // If the target wants custom lowering, do so. 6310 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6311 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6312 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6313 Op = TLI.LowerOperation(Op, DAG); 6314 if (Op.Val) { 6315 // Now that the custom expander is done, expand the result, which is 6316 // still VT. 6317 ExpandOp(Op, Lo, Hi); 6318 break; 6319 } 6320 } 6321 6322 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6323 // this X << 1 as X+X. 6324 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6325 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 6326 TLI.isOperationLegal(ISD::ADDE, NVT)) { 6327 SDOperand LoOps[2], HiOps[3]; 6328 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6329 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6330 LoOps[1] = LoOps[0]; 6331 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6332 6333 HiOps[1] = HiOps[0]; 6334 HiOps[2] = Lo.getValue(1); 6335 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6336 break; 6337 } 6338 } 6339 6340 // If we can emit an efficient shift operation, do so now. 6341 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6342 break; 6343 6344 // If this target supports SHL_PARTS, use it. 6345 TargetLowering::LegalizeAction Action = 6346 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6347 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6348 Action == TargetLowering::Custom) { 6349 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6350 break; 6351 } 6352 6353 // Otherwise, emit a libcall. 6354 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 6355 false/*left shift=unsigned*/, Hi); 6356 break; 6357 } 6358 6359 case ISD::SRA: { 6360 // If the target wants custom lowering, do so. 6361 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6362 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6363 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6364 Op = TLI.LowerOperation(Op, DAG); 6365 if (Op.Val) { 6366 // Now that the custom expander is done, expand the result, which is 6367 // still VT. 6368 ExpandOp(Op, Lo, Hi); 6369 break; 6370 } 6371 } 6372 6373 // If we can emit an efficient shift operation, do so now. 6374 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6375 break; 6376 6377 // If this target supports SRA_PARTS, use it. 6378 TargetLowering::LegalizeAction Action = 6379 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6380 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6381 Action == TargetLowering::Custom) { 6382 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6383 break; 6384 } 6385 6386 // Otherwise, emit a libcall. 6387 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 6388 true/*ashr is signed*/, Hi); 6389 break; 6390 } 6391 6392 case ISD::SRL: { 6393 // If the target wants custom lowering, do so. 6394 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6395 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6396 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6397 Op = TLI.LowerOperation(Op, DAG); 6398 if (Op.Val) { 6399 // Now that the custom expander is done, expand the result, which is 6400 // still VT. 6401 ExpandOp(Op, Lo, Hi); 6402 break; 6403 } 6404 } 6405 6406 // If we can emit an efficient shift operation, do so now. 6407 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6408 break; 6409 6410 // If this target supports SRL_PARTS, use it. 6411 TargetLowering::LegalizeAction Action = 6412 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6413 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6414 Action == TargetLowering::Custom) { 6415 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6416 break; 6417 } 6418 6419 // Otherwise, emit a libcall. 6420 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 6421 false/*lshr is unsigned*/, Hi); 6422 break; 6423 } 6424 6425 case ISD::ADD: 6426 case ISD::SUB: { 6427 // If the target wants to custom expand this, let them. 6428 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6429 TargetLowering::Custom) { 6430 Op = TLI.LowerOperation(Op, DAG); 6431 if (Op.Val) { 6432 ExpandOp(Op, Lo, Hi); 6433 break; 6434 } 6435 } 6436 6437 // Expand the subcomponents. 6438 SDOperand LHSL, LHSH, RHSL, RHSH; 6439 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6440 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6441 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6442 SDOperand LoOps[2], HiOps[3]; 6443 LoOps[0] = LHSL; 6444 LoOps[1] = RHSL; 6445 HiOps[0] = LHSH; 6446 HiOps[1] = RHSH; 6447 if (Node->getOpcode() == ISD::ADD) { 6448 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6449 HiOps[2] = Lo.getValue(1); 6450 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6451 } else { 6452 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6453 HiOps[2] = Lo.getValue(1); 6454 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6455 } 6456 break; 6457 } 6458 6459 case ISD::ADDC: 6460 case ISD::SUBC: { 6461 // Expand the subcomponents. 6462 SDOperand LHSL, LHSH, RHSL, RHSH; 6463 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6464 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6465 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6466 SDOperand LoOps[2] = { LHSL, RHSL }; 6467 SDOperand HiOps[3] = { LHSH, RHSH }; 6468 6469 if (Node->getOpcode() == ISD::ADDC) { 6470 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6471 HiOps[2] = Lo.getValue(1); 6472 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6473 } else { 6474 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6475 HiOps[2] = Lo.getValue(1); 6476 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6477 } 6478 // Remember that we legalized the flag. 6479 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6480 break; 6481 } 6482 case ISD::ADDE: 6483 case ISD::SUBE: { 6484 // Expand the subcomponents. 6485 SDOperand LHSL, LHSH, RHSL, RHSH; 6486 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6487 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6488 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6489 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 6490 SDOperand HiOps[3] = { LHSH, RHSH }; 6491 6492 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6493 HiOps[2] = Lo.getValue(1); 6494 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6495 6496 // Remember that we legalized the flag. 6497 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6498 break; 6499 } 6500 case ISD::MUL: { 6501 // If the target wants to custom expand this, let them. 6502 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6503 SDOperand New = TLI.LowerOperation(Op, DAG); 6504 if (New.Val) { 6505 ExpandOp(New, Lo, Hi); 6506 break; 6507 } 6508 } 6509 6510 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6511 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6512 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6513 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6514 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6515 SDOperand LL, LH, RL, RH; 6516 ExpandOp(Node->getOperand(0), LL, LH); 6517 ExpandOp(Node->getOperand(1), RL, RH); 6518 unsigned OuterBitSize = Op.getValueSizeInBits(); 6519 unsigned InnerBitSize = RH.getValueSizeInBits(); 6520 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6521 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6522 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 6523 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 6524 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 6525 // The inputs are both zero-extended. 6526 if (HasUMUL_LOHI) { 6527 // We can emit a umul_lohi. 6528 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6529 Hi = SDOperand(Lo.Val, 1); 6530 break; 6531 } 6532 if (HasMULHU) { 6533 // We can emit a mulhu+mul. 6534 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6535 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6536 break; 6537 } 6538 } 6539 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 6540 // The input values are both sign-extended. 6541 if (HasSMUL_LOHI) { 6542 // We can emit a smul_lohi. 6543 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6544 Hi = SDOperand(Lo.Val, 1); 6545 break; 6546 } 6547 if (HasMULHS) { 6548 // We can emit a mulhs+mul. 6549 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6550 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6551 break; 6552 } 6553 } 6554 if (HasUMUL_LOHI) { 6555 // Lo,Hi = umul LHS, RHS. 6556 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6557 DAG.getVTList(NVT, NVT), LL, RL); 6558 Lo = UMulLOHI; 6559 Hi = UMulLOHI.getValue(1); 6560 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6561 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6562 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6563 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6564 break; 6565 } 6566 if (HasMULHU) { 6567 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6568 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6569 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6570 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6571 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6572 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6573 break; 6574 } 6575 } 6576 6577 // If nothing else, we can make a libcall. 6578 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 6579 false/*sign irrelevant*/, Hi); 6580 break; 6581 } 6582 case ISD::SDIV: 6583 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 6584 break; 6585 case ISD::UDIV: 6586 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 6587 break; 6588 case ISD::SREM: 6589 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 6590 break; 6591 case ISD::UREM: 6592 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 6593 break; 6594 6595 case ISD::FADD: 6596 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32, 6597 RTLIB::ADD_F64, 6598 RTLIB::ADD_F80, 6599 RTLIB::ADD_PPCF128)), 6600 Node, false, Hi); 6601 break; 6602 case ISD::FSUB: 6603 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32, 6604 RTLIB::SUB_F64, 6605 RTLIB::SUB_F80, 6606 RTLIB::SUB_PPCF128)), 6607 Node, false, Hi); 6608 break; 6609 case ISD::FMUL: 6610 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32, 6611 RTLIB::MUL_F64, 6612 RTLIB::MUL_F80, 6613 RTLIB::MUL_PPCF128)), 6614 Node, false, Hi); 6615 break; 6616 case ISD::FDIV: 6617 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32, 6618 RTLIB::DIV_F64, 6619 RTLIB::DIV_F80, 6620 RTLIB::DIV_PPCF128)), 6621 Node, false, Hi); 6622 break; 6623 case ISD::FP_EXTEND: 6624 if (VT == MVT::ppcf128) { 6625 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6626 Node->getOperand(0).getValueType()==MVT::f64); 6627 const uint64_t zero = 0; 6628 if (Node->getOperand(0).getValueType()==MVT::f32) 6629 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6630 else 6631 Hi = Node->getOperand(0); 6632 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6633 break; 6634 } 6635 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 6636 break; 6637 case ISD::FP_ROUND: 6638 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 6639 break; 6640 case ISD::FPOWI: 6641 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32, 6642 RTLIB::POWI_F64, 6643 RTLIB::POWI_F80, 6644 RTLIB::POWI_PPCF128)), 6645 Node, false, Hi); 6646 break; 6647 case ISD::FSQRT: 6648 case ISD::FSIN: 6649 case ISD::FCOS: { 6650 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6651 switch(Node->getOpcode()) { 6652 case ISD::FSQRT: 6653 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6654 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6655 break; 6656 case ISD::FSIN: 6657 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6658 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6659 break; 6660 case ISD::FCOS: 6661 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6662 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6663 break; 6664 default: assert(0 && "Unreachable!"); 6665 } 6666 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 6667 break; 6668 } 6669 case ISD::FABS: { 6670 if (VT == MVT::ppcf128) { 6671 SDOperand Tmp; 6672 ExpandOp(Node->getOperand(0), Lo, Tmp); 6673 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6674 // lo = hi==fabs(hi) ? lo : -lo; 6675 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6676 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6677 DAG.getCondCode(ISD::SETEQ)); 6678 break; 6679 } 6680 SDOperand Mask = (VT == MVT::f64) 6681 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6682 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6683 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6684 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6685 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6686 if (getTypeAction(NVT) == Expand) 6687 ExpandOp(Lo, Lo, Hi); 6688 break; 6689 } 6690 case ISD::FNEG: { 6691 if (VT == MVT::ppcf128) { 6692 ExpandOp(Node->getOperand(0), Lo, Hi); 6693 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6694 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6695 break; 6696 } 6697 SDOperand Mask = (VT == MVT::f64) 6698 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6699 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6700 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6701 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6702 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6703 if (getTypeAction(NVT) == Expand) 6704 ExpandOp(Lo, Lo, Hi); 6705 break; 6706 } 6707 case ISD::FCOPYSIGN: { 6708 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6709 if (getTypeAction(NVT) == Expand) 6710 ExpandOp(Lo, Lo, Hi); 6711 break; 6712 } 6713 case ISD::SINT_TO_FP: 6714 case ISD::UINT_TO_FP: { 6715 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6716 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 6717 6718 // Promote the operand if needed. Do this before checking for 6719 // ppcf128 so conversions of i16 and i8 work. 6720 if (getTypeAction(SrcVT) == Promote) { 6721 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6722 Tmp = isSigned 6723 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6724 DAG.getValueType(SrcVT)) 6725 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6726 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6727 SrcVT = Node->getOperand(0).getValueType(); 6728 } 6729 6730 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 6731 static const uint64_t zero = 0; 6732 if (isSigned) { 6733 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6734 Node->getOperand(0))); 6735 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6736 } else { 6737 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6738 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6739 Node->getOperand(0))); 6740 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6741 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6742 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6743 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6744 DAG.getConstant(0, MVT::i32), 6745 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6746 DAG.getConstantFP( 6747 APFloat(APInt(128, 2, TwoE32)), 6748 MVT::ppcf128)), 6749 Hi, 6750 DAG.getCondCode(ISD::SETLT)), 6751 Lo, Hi); 6752 } 6753 break; 6754 } 6755 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6756 // si64->ppcf128 done by libcall, below 6757 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6758 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6759 Lo, Hi); 6760 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6761 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6762 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6763 DAG.getConstant(0, MVT::i64), 6764 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6765 DAG.getConstantFP( 6766 APFloat(APInt(128, 2, TwoE64)), 6767 MVT::ppcf128)), 6768 Hi, 6769 DAG.getCondCode(ISD::SETLT)), 6770 Lo, Hi); 6771 break; 6772 } 6773 6774 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6775 Node->getOperand(0)); 6776 ExpandOp(Lo, Lo, Hi); 6777 break; 6778 } 6779 } 6780 6781 // Make sure the resultant values have been legalized themselves, unless this 6782 // is a type that requires multi-step expansion. 6783 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6784 Lo = LegalizeOp(Lo); 6785 if (Hi.Val) 6786 // Don't legalize the high part if it is expanded to a single node. 6787 Hi = LegalizeOp(Hi); 6788 } 6789 6790 // Remember in a map if the values will be reused later. 6791 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6792 assert(isNew && "Value already expanded?!?"); 6793} 6794 6795/// SplitVectorOp - Given an operand of vector type, break it down into 6796/// two smaller values, still of vector type. 6797void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6798 SDOperand &Hi) { 6799 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); 6800 SDNode *Node = Op.Val; 6801 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType()); 6802 assert(NumElements > 1 && "Cannot split a single element vector!"); 6803 6804 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType()); 6805 6806 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6807 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6808 6809 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo); 6810 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi); 6811 6812 // See if we already split it. 6813 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6814 = SplitNodes.find(Op); 6815 if (I != SplitNodes.end()) { 6816 Lo = I->second.first; 6817 Hi = I->second.second; 6818 return; 6819 } 6820 6821 switch (Node->getOpcode()) { 6822 default: 6823#ifndef NDEBUG 6824 Node->dump(&DAG); 6825#endif 6826 assert(0 && "Unhandled operation in SplitVectorOp!"); 6827 case ISD::UNDEF: 6828 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6829 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6830 break; 6831 case ISD::BUILD_PAIR: 6832 Lo = Node->getOperand(0); 6833 Hi = Node->getOperand(1); 6834 break; 6835 case ISD::INSERT_VECTOR_ELT: { 6836 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6837 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 6838 SDOperand ScalarOp = Node->getOperand(1); 6839 if (Index < NewNumElts_Lo) 6840 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6841 DAG.getIntPtrConstant(Index)); 6842 else 6843 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6844 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 6845 break; 6846 } 6847 case ISD::VECTOR_SHUFFLE: { 6848 // Build the low part. 6849 SDOperand Mask = Node->getOperand(2); 6850 SmallVector<SDOperand, 8> Ops; 6851 MVT::ValueType PtrVT = TLI.getPointerTy(); 6852 6853 // Insert all of the elements from the input that are needed. We use 6854 // buildvector of extractelement here because the input vectors will have 6855 // to be legalized, so this makes the code simpler. 6856 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6857 SDOperand IdxNode = Mask.getOperand(i); 6858 if (IdxNode.getOpcode() == ISD::UNDEF) { 6859 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6860 continue; 6861 } 6862 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6863 SDOperand InVec = Node->getOperand(0); 6864 if (Idx >= NumElements) { 6865 InVec = Node->getOperand(1); 6866 Idx -= NumElements; 6867 } 6868 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6869 DAG.getConstant(Idx, PtrVT))); 6870 } 6871 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6872 Ops.clear(); 6873 6874 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6875 SDOperand IdxNode = Mask.getOperand(i); 6876 if (IdxNode.getOpcode() == ISD::UNDEF) { 6877 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6878 continue; 6879 } 6880 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6881 SDOperand InVec = Node->getOperand(0); 6882 if (Idx >= NumElements) { 6883 InVec = Node->getOperand(1); 6884 Idx -= NumElements; 6885 } 6886 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6887 DAG.getConstant(Idx, PtrVT))); 6888 } 6889 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6890 break; 6891 } 6892 case ISD::BUILD_VECTOR: { 6893 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6894 Node->op_begin()+NewNumElts_Lo); 6895 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6896 6897 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6898 Node->op_end()); 6899 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6900 break; 6901 } 6902 case ISD::CONCAT_VECTORS: { 6903 // FIXME: Handle non-power-of-two vectors? 6904 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6905 if (NewNumSubvectors == 1) { 6906 Lo = Node->getOperand(0); 6907 Hi = Node->getOperand(1); 6908 } else { 6909 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6910 Node->op_begin()+NewNumSubvectors); 6911 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6912 6913 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6914 Node->op_end()); 6915 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6916 } 6917 break; 6918 } 6919 case ISD::SELECT: { 6920 SDOperand Cond = Node->getOperand(0); 6921 6922 SDOperand LL, LH, RL, RH; 6923 SplitVectorOp(Node->getOperand(1), LL, LH); 6924 SplitVectorOp(Node->getOperand(2), RL, RH); 6925 6926 if (MVT::isVector(Cond.getValueType())) { 6927 // Handle a vector merge. 6928 SDOperand CL, CH; 6929 SplitVectorOp(Cond, CL, CH); 6930 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6931 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6932 } else { 6933 // Handle a simple select with vector operands. 6934 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6935 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6936 } 6937 break; 6938 } 6939 case ISD::ADD: 6940 case ISD::SUB: 6941 case ISD::MUL: 6942 case ISD::FADD: 6943 case ISD::FSUB: 6944 case ISD::FMUL: 6945 case ISD::SDIV: 6946 case ISD::UDIV: 6947 case ISD::FDIV: 6948 case ISD::FPOW: 6949 case ISD::AND: 6950 case ISD::OR: 6951 case ISD::XOR: 6952 case ISD::UREM: 6953 case ISD::SREM: 6954 case ISD::FREM: { 6955 SDOperand LL, LH, RL, RH; 6956 SplitVectorOp(Node->getOperand(0), LL, LH); 6957 SplitVectorOp(Node->getOperand(1), RL, RH); 6958 6959 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 6960 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 6961 break; 6962 } 6963 case ISD::FPOWI: { 6964 SDOperand L, H; 6965 SplitVectorOp(Node->getOperand(0), L, H); 6966 6967 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 6968 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 6969 break; 6970 } 6971 case ISD::CTTZ: 6972 case ISD::CTLZ: 6973 case ISD::CTPOP: 6974 case ISD::FNEG: 6975 case ISD::FABS: 6976 case ISD::FSQRT: 6977 case ISD::FSIN: 6978 case ISD::FCOS: 6979 case ISD::FP_TO_SINT: 6980 case ISD::FP_TO_UINT: 6981 case ISD::SINT_TO_FP: 6982 case ISD::UINT_TO_FP: { 6983 SDOperand L, H; 6984 SplitVectorOp(Node->getOperand(0), L, H); 6985 6986 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 6987 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 6988 break; 6989 } 6990 case ISD::LOAD: { 6991 LoadSDNode *LD = cast<LoadSDNode>(Node); 6992 SDOperand Ch = LD->getChain(); 6993 SDOperand Ptr = LD->getBasePtr(); 6994 const Value *SV = LD->getSrcValue(); 6995 int SVOffset = LD->getSrcValueOffset(); 6996 unsigned Alignment = LD->getAlignment(); 6997 bool isVolatile = LD->isVolatile(); 6998 6999 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 7000 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8; 7001 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 7002 DAG.getIntPtrConstant(IncrementSize)); 7003 SVOffset += IncrementSize; 7004 Alignment = MinAlign(Alignment, IncrementSize); 7005 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 7006 7007 // Build a factor node to remember that this load is independent of the 7008 // other one. 7009 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 7010 Hi.getValue(1)); 7011 7012 // Remember that we legalized the chain. 7013 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 7014 break; 7015 } 7016 case ISD::BIT_CONVERT: { 7017 // We know the result is a vector. The input may be either a vector or a 7018 // scalar value. 7019 SDOperand InOp = Node->getOperand(0); 7020 if (!MVT::isVector(InOp.getValueType()) || 7021 MVT::getVectorNumElements(InOp.getValueType()) == 1) { 7022 // The input is a scalar or single-element vector. 7023 // Lower to a store/load so that it can be split. 7024 // FIXME: this could be improved probably. 7025 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); 7026 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val); 7027 7028 SDOperand St = DAG.getStore(DAG.getEntryNode(), 7029 InOp, Ptr, 7030 PseudoSourceValue::getFixedStack(), 7031 FI->getIndex()); 7032 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 7033 PseudoSourceValue::getFixedStack(), 7034 FI->getIndex()); 7035 } 7036 // Split the vector and convert each of the pieces now. 7037 SplitVectorOp(InOp, Lo, Hi); 7038 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 7039 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 7040 break; 7041 } 7042 } 7043 7044 // Remember in a map if the values will be reused later. 7045 bool isNew = 7046 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7047 assert(isNew && "Value already split?!?"); 7048} 7049 7050 7051/// ScalarizeVectorOp - Given an operand of single-element vector type 7052/// (e.g. v1f32), convert it into the equivalent operation that returns a 7053/// scalar (e.g. f32) value. 7054SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 7055 assert(MVT::isVector(Op.getValueType()) && 7056 "Bad ScalarizeVectorOp invocation!"); 7057 SDNode *Node = Op.Val; 7058 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); 7059 assert(MVT::getVectorNumElements(Op.getValueType()) == 1); 7060 7061 // See if we already scalarized it. 7062 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 7063 if (I != ScalarizedNodes.end()) return I->second; 7064 7065 SDOperand Result; 7066 switch (Node->getOpcode()) { 7067 default: 7068#ifndef NDEBUG 7069 Node->dump(&DAG); cerr << "\n"; 7070#endif 7071 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7072 case ISD::ADD: 7073 case ISD::FADD: 7074 case ISD::SUB: 7075 case ISD::FSUB: 7076 case ISD::MUL: 7077 case ISD::FMUL: 7078 case ISD::SDIV: 7079 case ISD::UDIV: 7080 case ISD::FDIV: 7081 case ISD::SREM: 7082 case ISD::UREM: 7083 case ISD::FREM: 7084 case ISD::FPOW: 7085 case ISD::AND: 7086 case ISD::OR: 7087 case ISD::XOR: 7088 Result = DAG.getNode(Node->getOpcode(), 7089 NewVT, 7090 ScalarizeVectorOp(Node->getOperand(0)), 7091 ScalarizeVectorOp(Node->getOperand(1))); 7092 break; 7093 case ISD::FNEG: 7094 case ISD::FABS: 7095 case ISD::FSQRT: 7096 case ISD::FSIN: 7097 case ISD::FCOS: 7098 Result = DAG.getNode(Node->getOpcode(), 7099 NewVT, 7100 ScalarizeVectorOp(Node->getOperand(0))); 7101 break; 7102 case ISD::FPOWI: 7103 Result = DAG.getNode(Node->getOpcode(), 7104 NewVT, 7105 ScalarizeVectorOp(Node->getOperand(0)), 7106 Node->getOperand(1)); 7107 break; 7108 case ISD::LOAD: { 7109 LoadSDNode *LD = cast<LoadSDNode>(Node); 7110 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7111 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7112 7113 const Value *SV = LD->getSrcValue(); 7114 int SVOffset = LD->getSrcValueOffset(); 7115 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 7116 LD->isVolatile(), LD->getAlignment()); 7117 7118 // Remember that we legalized the chain. 7119 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7120 break; 7121 } 7122 case ISD::BUILD_VECTOR: 7123 Result = Node->getOperand(0); 7124 break; 7125 case ISD::INSERT_VECTOR_ELT: 7126 // Returning the inserted scalar element. 7127 Result = Node->getOperand(1); 7128 break; 7129 case ISD::CONCAT_VECTORS: 7130 assert(Node->getOperand(0).getValueType() == NewVT && 7131 "Concat of non-legal vectors not yet supported!"); 7132 Result = Node->getOperand(0); 7133 break; 7134 case ISD::VECTOR_SHUFFLE: { 7135 // Figure out if the scalar is the LHS or RHS and return it. 7136 SDOperand EltNum = Node->getOperand(2).getOperand(0); 7137 if (cast<ConstantSDNode>(EltNum)->getValue()) 7138 Result = ScalarizeVectorOp(Node->getOperand(1)); 7139 else 7140 Result = ScalarizeVectorOp(Node->getOperand(0)); 7141 break; 7142 } 7143 case ISD::EXTRACT_SUBVECTOR: 7144 Result = Node->getOperand(0); 7145 assert(Result.getValueType() == NewVT); 7146 break; 7147 case ISD::BIT_CONVERT: 7148 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 7149 break; 7150 case ISD::SELECT: 7151 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 7152 ScalarizeVectorOp(Op.getOperand(1)), 7153 ScalarizeVectorOp(Op.getOperand(2))); 7154 break; 7155 } 7156 7157 if (TLI.isTypeLegal(NewVT)) 7158 Result = LegalizeOp(Result); 7159 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7160 assert(isNew && "Value already scalarized?"); 7161 return Result; 7162} 7163 7164 7165// SelectionDAG::Legalize - This is the entry point for the file. 7166// 7167void SelectionDAG::Legalize() { 7168 if (ViewLegalizeDAGs) viewGraph(); 7169 7170 /// run - This is the main entry point to this class. 7171 /// 7172 SelectionDAGLegalize(*this).LegalizeDAG(); 7173} 7174 7175