LegalizeDAG.cpp revision e81aecbae69d4b3bd24523ec87673632d3b0beec
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned long long ValueTypeActions; 56 57 /// NeedsAnotherIteration - This is set when we expand a large integer 58 /// operation into smaller integer operations, but the smaller operations are 59 /// not set. This occurs only rarely in practice, for targets that don't have 60 /// 32-bit or larger integer registers. 61 bool NeedsAnotherIteration; 62 63 /// LegalizedNodes - For nodes that are of legal width, and that have more 64 /// than one use, this map indicates what regularized operand to use. This 65 /// allows us to avoid legalizing the same thing more than once. 66 std::map<SDOperand, SDOperand> LegalizedNodes; 67 68 /// PromotedNodes - For nodes that are below legal width, and that have more 69 /// than one use, this map indicates what promoted value to use. This allows 70 /// us to avoid promoting the same thing more than once. 71 std::map<SDOperand, SDOperand> PromotedNodes; 72 73 /// ExpandedNodes - For nodes that need to be expanded, and which have more 74 /// than one use, this map indicates which which operands are the expanded 75 /// version of the input. This allows us to avoid expanding the same node 76 /// more than once. 77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 78 79 void AddLegalizedOperand(SDOperand From, SDOperand To) { 80 LegalizedNodes.insert(std::make_pair(From, To)); 81 // If someone requests legalization of the new node, return itself. 82 if (From != To) 83 LegalizedNodes.insert(std::make_pair(To, To)); 84 } 85 void AddPromotedOperand(SDOperand From, SDOperand To) { 86 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 87 assert(isNew && "Got into the map somehow?"); 88 // If someone requests legalization of the new node, return itself. 89 LegalizedNodes.insert(std::make_pair(To, To)); 90 } 91 92public: 93 94 SelectionDAGLegalize(SelectionDAG &DAG); 95 96 /// Run - While there is still lowering to do, perform a pass over the DAG. 97 /// Most regularization can be done in a single pass, but targets that require 98 /// large values to be split into registers multiple times (e.g. i64 -> 4x 99 /// i16) require iteration for these values (the first iteration will demote 100 /// to i32, the second will demote to i16). 101 void Run() { 102 do { 103 NeedsAnotherIteration = false; 104 LegalizeDAG(); 105 } while (NeedsAnotherIteration); 106 } 107 108 /// getTypeAction - Return how we should legalize values of this type, either 109 /// it is already legal or we need to expand it into multiple registers of 110 /// smaller integer type, or we need to promote it to a larger type. 111 LegalizeAction getTypeAction(MVT::ValueType VT) const { 112 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 113 } 114 115 /// isTypeLegal - Return true if this type is legal on this target. 116 /// 117 bool isTypeLegal(MVT::ValueType VT) const { 118 return getTypeAction(VT) == Legal; 119 } 120 121private: 122 void LegalizeDAG(); 123 124 SDOperand LegalizeOp(SDOperand O); 125 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 126 SDOperand PromoteOp(SDOperand O); 127 128 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 129 SDOperand &Hi); 130 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 131 SDOperand Source); 132 133 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 134 SDOperand LegalOp, 135 MVT::ValueType DestVT); 136 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 137 bool isSigned); 138 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 139 bool isSigned); 140 141 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 142 SDOperand &Lo, SDOperand &Hi); 143 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 144 SDOperand &Lo, SDOperand &Hi); 145 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 146 SDOperand &Lo, SDOperand &Hi); 147 148 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 149 150 SDOperand getIntPtrConstant(uint64_t Val) { 151 return DAG.getConstant(Val, TLI.getPointerTy()); 152 } 153}; 154} 155 156static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 157 switch (VecOp) { 158 default: assert(0 && "Don't know how to scalarize this opcode!"); 159 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 160 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 161 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 162 } 163} 164 165SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 166 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 167 ValueTypeActions(TLI.getValueTypeActions()) { 168 assert(MVT::LAST_VALUETYPE <= 32 && 169 "Too many value types for ValueTypeActions to hold!"); 170} 171 172/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 173/// INT_TO_FP operation of the specified operand when the target requests that 174/// we expand it. At this point, we know that the result and operand types are 175/// legal for the target. 176SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 177 SDOperand Op0, 178 MVT::ValueType DestVT) { 179 if (Op0.getValueType() == MVT::i32) { 180 // simple 32-bit [signed|unsigned] integer to float/double expansion 181 182 // get the stack frame index of a 8 byte buffer 183 MachineFunction &MF = DAG.getMachineFunction(); 184 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 185 // get address of 8 byte buffer 186 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 187 // word offset constant for Hi/Lo address computation 188 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 189 // set up Hi and Lo (into buffer) address based on endian 190 SDOperand Hi, Lo; 191 if (TLI.isLittleEndian()) { 192 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 193 Lo = StackSlot; 194 } else { 195 Hi = StackSlot; 196 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 197 } 198 // if signed map to unsigned space 199 SDOperand Op0Mapped; 200 if (isSigned) { 201 // constant used to invert sign bit (signed to unsigned mapping) 202 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 203 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 204 } else { 205 Op0Mapped = Op0; 206 } 207 // store the lo of the constructed double - based on integer input 208 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 209 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 210 // initial hi portion of constructed double 211 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 212 // store the hi of the constructed double - biased exponent 213 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 214 InitialHi, Hi, DAG.getSrcValue(NULL)); 215 // load the constructed double 216 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 217 DAG.getSrcValue(NULL)); 218 // FP constant to bias correct the final result 219 SDOperand Bias = DAG.getConstantFP(isSigned ? 220 BitsToDouble(0x4330000080000000ULL) 221 : BitsToDouble(0x4330000000000000ULL), 222 MVT::f64); 223 // subtract the bias 224 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 225 // final result 226 SDOperand Result; 227 // handle final rounding 228 if (DestVT == MVT::f64) { 229 // do nothing 230 Result = Sub; 231 } else { 232 // if f32 then cast to f32 233 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 234 } 235 return LegalizeOp(Result); 236 } 237 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 238 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 239 240 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 241 DAG.getConstant(0, Op0.getValueType()), 242 ISD::SETLT); 243 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 244 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 245 SignSet, Four, Zero); 246 247 // If the sign bit of the integer is set, the large number will be treated 248 // as a negative number. To counteract this, the dynamic code adds an 249 // offset depending on the data type. 250 uint64_t FF; 251 switch (Op0.getValueType()) { 252 default: assert(0 && "Unsupported integer type!"); 253 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 254 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 255 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 256 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 257 } 258 if (TLI.isLittleEndian()) FF <<= 32; 259 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 260 261 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 262 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 263 SDOperand FudgeInReg; 264 if (DestVT == MVT::f32) 265 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 266 DAG.getSrcValue(NULL)); 267 else { 268 assert(DestVT == MVT::f64 && "Unexpected conversion"); 269 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 270 DAG.getEntryNode(), CPIdx, 271 DAG.getSrcValue(NULL), MVT::f32)); 272 } 273 274 return LegalizeOp(DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg)); 275} 276 277/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 278/// *INT_TO_FP operation of the specified operand when the target requests that 279/// we promote it. At this point, we know that the result and operand types are 280/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 281/// operation that takes a larger input. 282SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 283 MVT::ValueType DestVT, 284 bool isSigned) { 285 // First step, figure out the appropriate *INT_TO_FP operation to use. 286 MVT::ValueType NewInTy = LegalOp.getValueType(); 287 288 unsigned OpToUse = 0; 289 290 // Scan for the appropriate larger type to use. 291 while (1) { 292 NewInTy = (MVT::ValueType)(NewInTy+1); 293 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 294 295 // If the target supports SINT_TO_FP of this type, use it. 296 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 297 default: break; 298 case TargetLowering::Legal: 299 if (!TLI.isTypeLegal(NewInTy)) 300 break; // Can't use this datatype. 301 // FALL THROUGH. 302 case TargetLowering::Custom: 303 OpToUse = ISD::SINT_TO_FP; 304 break; 305 } 306 if (OpToUse) break; 307 if (isSigned) continue; 308 309 // If the target supports UINT_TO_FP of this type, use it. 310 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 311 default: break; 312 case TargetLowering::Legal: 313 if (!TLI.isTypeLegal(NewInTy)) 314 break; // Can't use this datatype. 315 // FALL THROUGH. 316 case TargetLowering::Custom: 317 OpToUse = ISD::UINT_TO_FP; 318 break; 319 } 320 if (OpToUse) break; 321 322 // Otherwise, try a larger type. 323 } 324 325 // Okay, we found the operation and type to use. Zero extend our input to the 326 // desired type then run the operation on it. 327 SDOperand N = DAG.getNode(OpToUse, DestVT, 328 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 329 NewInTy, LegalOp)); 330 // Make sure to legalize any nodes we create here. 331 return LegalizeOp(N); 332} 333 334/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 335/// FP_TO_*INT operation of the specified operand when the target requests that 336/// we promote it. At this point, we know that the result and operand types are 337/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 338/// operation that returns a larger result. 339SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 340 MVT::ValueType DestVT, 341 bool isSigned) { 342 // First step, figure out the appropriate FP_TO*INT operation to use. 343 MVT::ValueType NewOutTy = DestVT; 344 345 unsigned OpToUse = 0; 346 347 // Scan for the appropriate larger type to use. 348 while (1) { 349 NewOutTy = (MVT::ValueType)(NewOutTy+1); 350 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 351 352 // If the target supports FP_TO_SINT returning this type, use it. 353 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 354 default: break; 355 case TargetLowering::Legal: 356 if (!TLI.isTypeLegal(NewOutTy)) 357 break; // Can't use this datatype. 358 // FALL THROUGH. 359 case TargetLowering::Custom: 360 OpToUse = ISD::FP_TO_SINT; 361 break; 362 } 363 if (OpToUse) break; 364 365 // If the target supports FP_TO_UINT of this type, use it. 366 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 367 default: break; 368 case TargetLowering::Legal: 369 if (!TLI.isTypeLegal(NewOutTy)) 370 break; // Can't use this datatype. 371 // FALL THROUGH. 372 case TargetLowering::Custom: 373 OpToUse = ISD::FP_TO_UINT; 374 break; 375 } 376 if (OpToUse) break; 377 378 // Otherwise, try a larger type. 379 } 380 381 // Okay, we found the operation and type to use. Truncate the result of the 382 // extended FP_TO_*INT operation to the desired size. 383 SDOperand N = DAG.getNode(ISD::TRUNCATE, DestVT, 384 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 385 // Make sure to legalize any nodes we create here in the next pass. 386 return LegalizeOp(N); 387} 388 389/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 390/// not been visited yet and if all of its operands have already been visited. 391static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 392 std::map<SDNode*, unsigned> &Visited) { 393 if (++Visited[N] != N->getNumOperands()) 394 return; // Haven't visited all operands yet 395 396 Order.push_back(N); 397 398 if (N->hasOneUse()) { // Tail recurse in common case. 399 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 400 return; 401 } 402 403 // Now that we have N in, add anything that uses it if all of their operands 404 // are now done. 405 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 406 ComputeTopDownOrdering(*UI, Order, Visited); 407} 408 409 410void SelectionDAGLegalize::LegalizeDAG() { 411 // The legalize process is inherently a bottom-up recursive process (users 412 // legalize their uses before themselves). Given infinite stack space, we 413 // could just start legalizing on the root and traverse the whole graph. In 414 // practice however, this causes us to run out of stack space on large basic 415 // blocks. To avoid this problem, compute an ordering of the nodes where each 416 // node is only legalized after all of its operands are legalized. 417 std::map<SDNode*, unsigned> Visited; 418 std::vector<SDNode*> Order; 419 420 // Compute ordering from all of the leaves in the graphs, those (like the 421 // entry node) that have no operands. 422 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 423 E = DAG.allnodes_end(); I != E; ++I) { 424 if (I->getNumOperands() == 0) { 425 Visited[I] = 0 - 1U; 426 ComputeTopDownOrdering(I, Order, Visited); 427 } 428 } 429 430 assert(Order.size() == Visited.size() && 431 Order.size() == 432 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 433 "Error: DAG is cyclic!"); 434 Visited.clear(); 435 436 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 437 SDNode *N = Order[i]; 438 switch (getTypeAction(N->getValueType(0))) { 439 default: assert(0 && "Bad type action!"); 440 case Legal: 441 LegalizeOp(SDOperand(N, 0)); 442 break; 443 case Promote: 444 PromoteOp(SDOperand(N, 0)); 445 break; 446 case Expand: { 447 SDOperand X, Y; 448 ExpandOp(SDOperand(N, 0), X, Y); 449 break; 450 } 451 } 452 } 453 454 // Finally, it's possible the root changed. Get the new root. 455 SDOperand OldRoot = DAG.getRoot(); 456 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 457 DAG.setRoot(LegalizedNodes[OldRoot]); 458 459 ExpandedNodes.clear(); 460 LegalizedNodes.clear(); 461 PromotedNodes.clear(); 462 463 // Remove dead nodes now. 464 DAG.RemoveDeadNodes(OldRoot.Val); 465} 466 467SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 468 assert(isTypeLegal(Op.getValueType()) && 469 "Caller should expand or promote operands that are not legal!"); 470 SDNode *Node = Op.Val; 471 472 // If this operation defines any values that cannot be represented in a 473 // register on this target, make sure to expand or promote them. 474 if (Node->getNumValues() > 1) { 475 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 476 switch (getTypeAction(Node->getValueType(i))) { 477 case Legal: break; // Nothing to do. 478 case Expand: { 479 SDOperand T1, T2; 480 ExpandOp(Op.getValue(i), T1, T2); 481 assert(LegalizedNodes.count(Op) && 482 "Expansion didn't add legal operands!"); 483 return LegalizedNodes[Op]; 484 } 485 case Promote: 486 PromoteOp(Op.getValue(i)); 487 assert(LegalizedNodes.count(Op) && 488 "Expansion didn't add legal operands!"); 489 return LegalizedNodes[Op]; 490 } 491 } 492 493 // Note that LegalizeOp may be reentered even from single-use nodes, which 494 // means that we always must cache transformed nodes. 495 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 496 if (I != LegalizedNodes.end()) return I->second; 497 498 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 499 500 SDOperand Result = Op; 501 502 switch (Node->getOpcode()) { 503 default: 504 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 505 // If this is a target node, legalize it by legalizing the operands then 506 // passing it through. 507 std::vector<SDOperand> Ops; 508 bool Changed = false; 509 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 510 Ops.push_back(LegalizeOp(Node->getOperand(i))); 511 Changed = Changed || Node->getOperand(i) != Ops.back(); 512 } 513 if (Changed) 514 if (Node->getNumValues() == 1) 515 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 516 else { 517 std::vector<MVT::ValueType> VTs(Node->value_begin(), 518 Node->value_end()); 519 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 520 } 521 522 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 523 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 524 return Result.getValue(Op.ResNo); 525 } 526 // Otherwise this is an unhandled builtin node. splat. 527 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 528 assert(0 && "Do not know how to legalize this operator!"); 529 abort(); 530 case ISD::EntryToken: 531 case ISD::FrameIndex: 532 case ISD::TargetFrameIndex: 533 case ISD::Register: 534 case ISD::TargetConstant: 535 case ISD::TargetConstantPool: 536 case ISD::GlobalAddress: 537 case ISD::TargetGlobalAddress: 538 case ISD::ExternalSymbol: 539 case ISD::ConstantPool: // Nothing to do. 540 case ISD::BasicBlock: 541 case ISD::CONDCODE: 542 case ISD::VALUETYPE: 543 case ISD::SRCVALUE: 544 case ISD::STRING: 545 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 546 default: assert(0 && "This action is not supported yet!"); 547 case TargetLowering::Custom: { 548 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 549 if (Tmp.Val) { 550 Result = LegalizeOp(Tmp); 551 break; 552 } 553 } // FALLTHROUGH if the target doesn't want to lower this op after all. 554 case TargetLowering::Legal: 555 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!"); 556 break; 557 } 558 break; 559 case ISD::AssertSext: 560 case ISD::AssertZext: 561 Tmp1 = LegalizeOp(Node->getOperand(0)); 562 if (Tmp1 != Node->getOperand(0)) 563 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 564 Node->getOperand(1)); 565 break; 566 case ISD::MERGE_VALUES: 567 return LegalizeOp(Node->getOperand(Op.ResNo)); 568 case ISD::CopyFromReg: 569 Tmp1 = LegalizeOp(Node->getOperand(0)); 570 Result = Op.getValue(0); 571 if (Node->getNumValues() == 2) { 572 if (Tmp1 != Node->getOperand(0)) 573 Result = DAG.getCopyFromReg(Tmp1, 574 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 575 Node->getValueType(0)); 576 } else { 577 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 578 if (Node->getNumOperands() == 3) 579 Tmp2 = LegalizeOp(Node->getOperand(2)); 580 if (Tmp1 != Node->getOperand(0) || 581 (Node->getNumOperands() == 3 && Tmp2 != Node->getOperand(2))) 582 Result = DAG.getCopyFromReg(Tmp1, 583 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 584 Node->getValueType(0), Tmp2); 585 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 586 } 587 // Since CopyFromReg produces two values, make sure to remember that we 588 // legalized both of them. 589 AddLegalizedOperand(Op.getValue(0), Result); 590 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 591 return Result.getValue(Op.ResNo); 592 case ISD::ImplicitDef: 593 Tmp1 = LegalizeOp(Node->getOperand(0)); 594 if (Tmp1 != Node->getOperand(0)) 595 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other, 596 Tmp1, Node->getOperand(1)); 597 break; 598 case ISD::UNDEF: { 599 MVT::ValueType VT = Op.getValueType(); 600 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 601 default: assert(0 && "This action is not supported yet!"); 602 case TargetLowering::Expand: 603 case TargetLowering::Promote: 604 if (MVT::isInteger(VT)) 605 Result = DAG.getConstant(0, VT); 606 else if (MVT::isFloatingPoint(VT)) 607 Result = DAG.getConstantFP(0, VT); 608 else 609 assert(0 && "Unknown value type!"); 610 break; 611 case TargetLowering::Legal: 612 break; 613 } 614 break; 615 } 616 617 case ISD::LOCATION: 618 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 619 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 620 621 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 622 case TargetLowering::Promote: 623 default: assert(0 && "This action is not supported yet!"); 624 case TargetLowering::Expand: { 625 if (TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other)) { 626 MachineDebugInfo &DebugInfo = DAG.getMachineFunction().getDebugInfo(); 627 std::vector<SDOperand> Ops; 628 Ops.push_back(Tmp1); // chain 629 Ops.push_back(Node->getOperand(1)); // line # 630 Ops.push_back(Node->getOperand(2)); // col # 631 const std::string &fname = 632 cast<StringSDNode>(Node->getOperand(3))->getValue(); 633 const std::string &dirname = 634 cast<StringSDNode>(Node->getOperand(4))->getValue(); 635 unsigned id = DebugInfo.RecordSource(fname, dirname); 636 Ops.push_back(DAG.getConstant(id, MVT::i32)); // source file id 637 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops); 638 } else { 639 Result = Tmp1; // chain 640 } 641 Result = LegalizeOp(Result); // Relegalize new nodes. 642 break; 643 } 644 case TargetLowering::Legal: 645 if (Tmp1 != Node->getOperand(0) || 646 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 647 std::vector<SDOperand> Ops; 648 Ops.push_back(Tmp1); 649 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 650 Ops.push_back(Node->getOperand(1)); // line # must be legal. 651 Ops.push_back(Node->getOperand(2)); // col # must be legal. 652 } else { 653 // Otherwise promote them. 654 Ops.push_back(PromoteOp(Node->getOperand(1))); 655 Ops.push_back(PromoteOp(Node->getOperand(2))); 656 } 657 Ops.push_back(Node->getOperand(3)); // filename must be legal. 658 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 659 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops); 660 } 661 break; 662 } 663 break; 664 665 case ISD::DEBUG_LOC: 666 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 667 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 668 case TargetLowering::Promote: 669 case TargetLowering::Expand: 670 default: assert(0 && "This action is not supported yet!"); 671 case TargetLowering::Legal: 672 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 673 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 674 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 675 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 676 677 if (Tmp1 != Node->getOperand(0) || 678 Tmp2 != Node->getOperand(1) || 679 Tmp3 != Node->getOperand(2) || 680 Tmp4 != Node->getOperand(3)) { 681 Result = DAG.getNode(ISD::DEBUG_LOC,MVT::Other, Tmp1, Tmp2, Tmp3, Tmp4); 682 } 683 break; 684 } 685 break; 686 687 case ISD::Constant: 688 // We know we don't need to expand constants here, constants only have one 689 // value and we check that it is fine above. 690 691 // FIXME: Maybe we should handle things like targets that don't support full 692 // 32-bit immediates? 693 break; 694 case ISD::ConstantFP: { 695 // Spill FP immediates to the constant pool if the target cannot directly 696 // codegen them. Targets often have some immediate values that can be 697 // efficiently generated into an FP register without a load. We explicitly 698 // leave these constants as ConstantFP nodes for the target to deal with. 699 700 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 701 702 // Check to see if this FP immediate is already legal. 703 bool isLegal = false; 704 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 705 E = TLI.legal_fpimm_end(); I != E; ++I) 706 if (CFP->isExactlyValue(*I)) { 707 isLegal = true; 708 break; 709 } 710 711 if (!isLegal) { 712 // Otherwise we need to spill the constant to memory. 713 bool Extend = false; 714 715 // If a FP immediate is precise when represented as a float, we put it 716 // into the constant pool as a float, even if it's is statically typed 717 // as a double. 718 MVT::ValueType VT = CFP->getValueType(0); 719 bool isDouble = VT == MVT::f64; 720 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 721 Type::FloatTy, CFP->getValue()); 722 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 723 // Only do this if the target has a native EXTLOAD instruction from 724 // f32. 725 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 726 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 727 VT = MVT::f32; 728 Extend = true; 729 } 730 731 SDOperand CPIdx = 732 LegalizeOp(DAG.getConstantPool(LLVMC, TLI.getPointerTy())); 733 if (Extend) { 734 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 735 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 736 } else { 737 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 738 DAG.getSrcValue(NULL)); 739 } 740 } 741 break; 742 } 743 case ISD::ConstantVec: { 744 // We assume that vector constants are not legal, and will be immediately 745 // spilled to the constant pool. 746 // 747 // FIXME: revisit this when we have some kind of mechanism by which targets 748 // can decided legality of vector constants, of which there may be very 749 // many. 750 // 751 // Create a ConstantPacked, and put it in the constant pool. 752 std::vector<Constant*> CV; 753 MVT::ValueType VT = Node->getValueType(0); 754 for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) { 755 SDOperand OpN = Node->getOperand(I); 756 const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType()); 757 if (MVT::isFloatingPoint(VT)) 758 CV.push_back(ConstantFP::get(OpNTy, 759 cast<ConstantFPSDNode>(OpN)->getValue())); 760 else 761 CV.push_back(ConstantUInt::get(OpNTy, 762 cast<ConstantSDNode>(OpN)->getValue())); 763 } 764 Constant *CP = ConstantPacked::get(CV); 765 SDOperand CPIdx = LegalizeOp(DAG.getConstantPool(CP, TLI.getPointerTy())); 766 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL)); 767 break; 768 } 769 case ISD::TokenFactor: 770 if (Node->getNumOperands() == 2) { 771 bool Changed = false; 772 SDOperand Op0 = LegalizeOp(Node->getOperand(0)); 773 SDOperand Op1 = LegalizeOp(Node->getOperand(1)); 774 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1)) 775 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1); 776 } else { 777 std::vector<SDOperand> Ops; 778 bool Changed = false; 779 // Legalize the operands. 780 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 781 SDOperand Op = Node->getOperand(i); 782 Ops.push_back(LegalizeOp(Op)); 783 Changed |= Ops[i] != Op; 784 } 785 if (Changed) 786 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 787 } 788 break; 789 790 case ISD::CALLSEQ_START: 791 case ISD::CALLSEQ_END: 792 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 793 // Do not try to legalize the target-specific arguments (#1+) 794 Tmp2 = Node->getOperand(0); 795 if (Tmp1 != Tmp2) 796 Node->setAdjCallChain(Tmp1); 797 798 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These 799 // nodes are treated specially and are mutated in place. This makes the dag 800 // legalization process more efficient and also makes libcall insertion 801 // easier. 802 break; 803 case ISD::DYNAMIC_STACKALLOC: 804 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 805 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 806 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 807 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 808 Tmp3 != Node->getOperand(2)) { 809 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 810 std::vector<SDOperand> Ops; 811 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 812 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 813 } else 814 Result = Op.getValue(0); 815 816 // Since this op produces two values, make sure to remember that we 817 // legalized both of them. 818 AddLegalizedOperand(SDOperand(Node, 0), Result); 819 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 820 return Result.getValue(Op.ResNo); 821 822 case ISD::TAILCALL: 823 case ISD::CALL: { 824 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 825 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 826 827 bool Changed = false; 828 std::vector<SDOperand> Ops; 829 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 830 Ops.push_back(LegalizeOp(Node->getOperand(i))); 831 Changed |= Ops.back() != Node->getOperand(i); 832 } 833 834 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 835 std::vector<MVT::ValueType> RetTyVTs; 836 RetTyVTs.reserve(Node->getNumValues()); 837 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 838 RetTyVTs.push_back(Node->getValueType(i)); 839 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 840 Node->getOpcode() == ISD::TAILCALL), 0); 841 } else { 842 Result = Result.getValue(0); 843 } 844 // Since calls produce multiple values, make sure to remember that we 845 // legalized all of them. 846 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 847 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 848 return Result.getValue(Op.ResNo); 849 } 850 case ISD::BR: 851 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 852 if (Tmp1 != Node->getOperand(0)) 853 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 854 break; 855 856 case ISD::BRCOND: 857 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 858 859 switch (getTypeAction(Node->getOperand(1).getValueType())) { 860 case Expand: assert(0 && "It's impossible to expand bools"); 861 case Legal: 862 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 863 break; 864 case Promote: 865 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 866 break; 867 } 868 869 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 870 default: assert(0 && "This action is not supported yet!"); 871 case TargetLowering::Expand: 872 // Expand brcond's setcc into its constituent parts and create a BR_CC 873 // Node. 874 if (Tmp2.getOpcode() == ISD::SETCC) { 875 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 876 Tmp2.getOperand(0), Tmp2.getOperand(1), 877 Node->getOperand(2)); 878 } else { 879 // Make sure the condition is either zero or one. It may have been 880 // promoted from something else. 881 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 882 883 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 884 DAG.getCondCode(ISD::SETNE), Tmp2, 885 DAG.getConstant(0, Tmp2.getValueType()), 886 Node->getOperand(2)); 887 } 888 Result = LegalizeOp(Result); // Relegalize new nodes. 889 break; 890 case TargetLowering::Custom: { 891 SDOperand Tmp = 892 TLI.LowerOperation(DAG.getNode(ISD::BRCOND, Node->getValueType(0), 893 Tmp1, Tmp2, Node->getOperand(2)), DAG); 894 if (Tmp.Val) { 895 Result = LegalizeOp(Tmp); 896 break; 897 } 898 // FALLTHROUGH if the target thinks it is legal. 899 } 900 case TargetLowering::Legal: 901 // Basic block destination (Op#2) is always legal. 902 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 903 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 904 Node->getOperand(2)); 905 break; 906 } 907 break; 908 case ISD::BR_CC: 909 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 910 if (!isTypeLegal(Node->getOperand(2).getValueType())) { 911 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 912 Node->getOperand(2), // LHS 913 Node->getOperand(3), // RHS 914 Node->getOperand(1))); 915 // If we get a SETCC back from legalizing the SETCC node we just 916 // created, then use its LHS, RHS, and CC directly in creating a new 917 // node. Otherwise, select between the true and false value based on 918 // comparing the result of the legalized with zero. 919 if (Tmp2.getOpcode() == ISD::SETCC) { 920 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 921 Tmp2.getOperand(0), Tmp2.getOperand(1), 922 Node->getOperand(4)); 923 } else { 924 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 925 DAG.getCondCode(ISD::SETNE), 926 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 927 Node->getOperand(4)); 928 } 929 break; 930 } 931 932 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 933 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 934 935 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 936 default: assert(0 && "Unexpected action for BR_CC!"); 937 case TargetLowering::Custom: { 938 Tmp4 = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 939 Tmp2, Tmp3, Node->getOperand(4)); 940 Tmp4 = TLI.LowerOperation(Tmp4, DAG); 941 if (Tmp4.Val) { 942 Result = LegalizeOp(Tmp4); 943 break; 944 } 945 } // FALLTHROUGH if the target doesn't want to lower this op after all. 946 case TargetLowering::Legal: 947 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 948 Tmp3 != Node->getOperand(3)) { 949 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 950 Tmp2, Tmp3, Node->getOperand(4)); 951 } 952 break; 953 } 954 break; 955 case ISD::BRCONDTWOWAY: 956 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 957 switch (getTypeAction(Node->getOperand(1).getValueType())) { 958 case Expand: assert(0 && "It's impossible to expand bools"); 959 case Legal: 960 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 961 break; 962 case Promote: 963 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 964 break; 965 } 966 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 967 // pair. 968 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 969 case TargetLowering::Promote: 970 default: assert(0 && "This action is not supported yet!"); 971 case TargetLowering::Legal: 972 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 973 std::vector<SDOperand> Ops; 974 Ops.push_back(Tmp1); 975 Ops.push_back(Tmp2); 976 Ops.push_back(Node->getOperand(2)); 977 Ops.push_back(Node->getOperand(3)); 978 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 979 } 980 break; 981 case TargetLowering::Expand: 982 // If BRTWOWAY_CC is legal for this target, then simply expand this node 983 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 984 // BRCOND/BR pair. 985 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 986 if (Tmp2.getOpcode() == ISD::SETCC) { 987 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 988 Tmp2.getOperand(0), Tmp2.getOperand(1), 989 Node->getOperand(2), Node->getOperand(3)); 990 } else { 991 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 992 DAG.getConstant(0, Tmp2.getValueType()), 993 Node->getOperand(2), Node->getOperand(3)); 994 } 995 } else { 996 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 997 Node->getOperand(2)); 998 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 999 } 1000 Result = LegalizeOp(Result); // Relegalize new nodes. 1001 break; 1002 } 1003 break; 1004 case ISD::BRTWOWAY_CC: 1005 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1006 if (isTypeLegal(Node->getOperand(2).getValueType())) { 1007 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 1008 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 1009 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 1010 Tmp3 != Node->getOperand(3)) { 1011 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3, 1012 Node->getOperand(4), Node->getOperand(5)); 1013 } 1014 break; 1015 } else { 1016 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1017 Node->getOperand(2), // LHS 1018 Node->getOperand(3), // RHS 1019 Node->getOperand(1))); 1020 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 1021 // pair. 1022 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 1023 default: assert(0 && "This action is not supported yet!"); 1024 case TargetLowering::Legal: 1025 // If we get a SETCC back from legalizing the SETCC node we just 1026 // created, then use its LHS, RHS, and CC directly in creating a new 1027 // node. Otherwise, select between the true and false value based on 1028 // comparing the result of the legalized with zero. 1029 if (Tmp2.getOpcode() == ISD::SETCC) { 1030 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 1031 Tmp2.getOperand(0), Tmp2.getOperand(1), 1032 Node->getOperand(4), Node->getOperand(5)); 1033 } else { 1034 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 1035 DAG.getConstant(0, Tmp2.getValueType()), 1036 Node->getOperand(4), Node->getOperand(5)); 1037 } 1038 break; 1039 case TargetLowering::Expand: 1040 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 1041 Node->getOperand(4)); 1042 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 1043 break; 1044 } 1045 Result = LegalizeOp(Result); // Relegalize new nodes. 1046 } 1047 break; 1048 case ISD::LOAD: 1049 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1050 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1051 1052 if (Tmp1 != Node->getOperand(0) || 1053 Tmp2 != Node->getOperand(1)) 1054 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, 1055 Node->getOperand(2)); 1056 else 1057 Result = SDOperand(Node, 0); 1058 1059 // Since loads produce two values, make sure to remember that we legalized 1060 // both of them. 1061 AddLegalizedOperand(SDOperand(Node, 0), Result); 1062 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1063 return Result.getValue(Op.ResNo); 1064 1065 case ISD::EXTLOAD: 1066 case ISD::SEXTLOAD: 1067 case ISD::ZEXTLOAD: { 1068 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1069 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1070 1071 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 1072 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 1073 default: assert(0 && "This action is not supported yet!"); 1074 case TargetLowering::Promote: 1075 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 1076 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1077 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 1078 // Since loads produce two values, make sure to remember that we legalized 1079 // both of them. 1080 AddLegalizedOperand(SDOperand(Node, 0), Result); 1081 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1082 return Result.getValue(Op.ResNo); 1083 1084 case TargetLowering::Legal: 1085 if (Tmp1 != Node->getOperand(0) || 1086 Tmp2 != Node->getOperand(1)) 1087 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1088 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1089 else 1090 Result = SDOperand(Node, 0); 1091 1092 // Since loads produce two values, make sure to remember that we legalized 1093 // both of them. 1094 AddLegalizedOperand(SDOperand(Node, 0), Result); 1095 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1096 return Result.getValue(Op.ResNo); 1097 case TargetLowering::Expand: 1098 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1099 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1100 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 1101 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1102 Result = LegalizeOp(Result); // Relegalize new nodes. 1103 Load = LegalizeOp(Load); 1104 AddLegalizedOperand(SDOperand(Node, 0), Result); 1105 AddLegalizedOperand(SDOperand(Node, 1), Load.getValue(1)); 1106 if (Op.ResNo) 1107 return Load.getValue(1); 1108 return Result; 1109 } 1110 assert(Node->getOpcode() != ISD::EXTLOAD && 1111 "EXTLOAD should always be supported!"); 1112 // Turn the unsupported load into an EXTLOAD followed by an explicit 1113 // zero/sign extend inreg. 1114 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1115 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1116 SDOperand ValRes; 1117 if (Node->getOpcode() == ISD::SEXTLOAD) 1118 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1119 Result, DAG.getValueType(SrcVT)); 1120 else 1121 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1122 Result = LegalizeOp(Result); // Relegalize new nodes. 1123 ValRes = LegalizeOp(ValRes); // Relegalize new nodes. 1124 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 1125 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1126 if (Op.ResNo) 1127 return Result.getValue(1); 1128 return ValRes; 1129 } 1130 assert(0 && "Unreachable"); 1131 } 1132 case ISD::EXTRACT_ELEMENT: { 1133 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1134 switch (getTypeAction(OpTy)) { 1135 default: 1136 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1137 break; 1138 case Legal: 1139 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1140 // 1 -> Hi 1141 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1142 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1143 TLI.getShiftAmountTy())); 1144 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1145 } else { 1146 // 0 -> Lo 1147 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1148 Node->getOperand(0)); 1149 } 1150 Result = LegalizeOp(Result); 1151 break; 1152 case Expand: 1153 // Get both the low and high parts. 1154 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1155 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1156 Result = Tmp2; // 1 -> Hi 1157 else 1158 Result = Tmp1; // 0 -> Lo 1159 break; 1160 } 1161 break; 1162 } 1163 1164 case ISD::CopyToReg: 1165 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1166 1167 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1168 "Register type must be legal!"); 1169 // Legalize the incoming value (must be a legal type). 1170 Tmp2 = LegalizeOp(Node->getOperand(2)); 1171 if (Node->getNumValues() == 1) { 1172 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2)) 1173 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1, 1174 Node->getOperand(1), Tmp2); 1175 } else { 1176 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1177 if (Node->getNumOperands() == 4) 1178 Tmp3 = LegalizeOp(Node->getOperand(3)); 1179 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 1180 (Node->getNumOperands() == 4 && Tmp3 != Node->getOperand(3))) { 1181 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 1182 Result = DAG.getCopyToReg(Tmp1, Reg, Tmp2, Tmp3); 1183 } 1184 1185 // Since this produces two values, make sure to remember that we legalized 1186 // both of them. 1187 AddLegalizedOperand(SDOperand(Node, 0), Result); 1188 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1189 return Result.getValue(Op.ResNo); 1190 } 1191 break; 1192 1193 case ISD::RET: 1194 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1195 switch (Node->getNumOperands()) { 1196 case 2: // ret val 1197 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1198 case Legal: 1199 Tmp2 = LegalizeOp(Node->getOperand(1)); 1200 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1201 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1202 break; 1203 case Expand: { 1204 SDOperand Lo, Hi; 1205 ExpandOp(Node->getOperand(1), Lo, Hi); 1206 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1207 break; 1208 } 1209 case Promote: 1210 Tmp2 = PromoteOp(Node->getOperand(1)); 1211 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1212 break; 1213 } 1214 break; 1215 case 1: // ret void 1216 if (Tmp1 != Node->getOperand(0)) 1217 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 1218 break; 1219 default: { // ret <values> 1220 std::vector<SDOperand> NewValues; 1221 NewValues.push_back(Tmp1); 1222 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1223 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1224 case Legal: 1225 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1226 break; 1227 case Expand: { 1228 SDOperand Lo, Hi; 1229 ExpandOp(Node->getOperand(i), Lo, Hi); 1230 NewValues.push_back(Lo); 1231 NewValues.push_back(Hi); 1232 break; 1233 } 1234 case Promote: 1235 assert(0 && "Can't promote multiple return value yet!"); 1236 } 1237 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1238 break; 1239 } 1240 } 1241 break; 1242 case ISD::STORE: 1243 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1244 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1245 1246 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1247 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1248 if (CFP->getValueType(0) == MVT::f32) { 1249 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1250 DAG.getConstant(FloatToBits(CFP->getValue()), 1251 MVT::i32), 1252 Tmp2, 1253 Node->getOperand(3)); 1254 } else { 1255 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1256 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1257 DAG.getConstant(DoubleToBits(CFP->getValue()), 1258 MVT::i64), 1259 Tmp2, 1260 Node->getOperand(3)); 1261 } 1262 Node = Result.Val; 1263 } 1264 1265 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1266 case Legal: { 1267 SDOperand Val = LegalizeOp(Node->getOperand(1)); 1268 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 1269 Tmp2 != Node->getOperand(2)) 1270 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 1271 Node->getOperand(3)); 1272 break; 1273 } 1274 case Promote: 1275 // Truncate the value and store the result. 1276 Tmp3 = PromoteOp(Node->getOperand(1)); 1277 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1278 Node->getOperand(3), 1279 DAG.getValueType(Node->getOperand(1).getValueType())); 1280 break; 1281 1282 case Expand: 1283 SDOperand Lo, Hi; 1284 unsigned IncrementSize; 1285 ExpandOp(Node->getOperand(1), Lo, Hi); 1286 1287 if (!TLI.isLittleEndian()) 1288 std::swap(Lo, Hi); 1289 1290 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1291 Node->getOperand(3)); 1292 // If this is a vector type, then we have to calculate the increment as 1293 // the product of the element size in bytes, and the number of elements 1294 // in the high half of the vector. 1295 if (MVT::Vector == Hi.getValueType()) { 1296 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue(); 1297 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT(); 1298 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8; 1299 } else { 1300 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1301 } 1302 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1303 getIntPtrConstant(IncrementSize)); 1304 assert(isTypeLegal(Tmp2.getValueType()) && 1305 "Pointers must be legal!"); 1306 //Again, claiming both parts of the store came form the same Instr 1307 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1308 Node->getOperand(3)); 1309 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1310 break; 1311 } 1312 break; 1313 case ISD::PCMARKER: 1314 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1315 if (Tmp1 != Node->getOperand(0)) 1316 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 1317 break; 1318 case ISD::READCYCLECOUNTER: 1319 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1320 if (Tmp1 != Node->getOperand(0)) { 1321 std::vector<MVT::ValueType> rtypes; 1322 std::vector<SDOperand> rvals; 1323 rtypes.push_back(MVT::i64); 1324 rtypes.push_back(MVT::Other); 1325 rvals.push_back(Tmp1); 1326 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals); 1327 } 1328 1329 // Since rdcc produce two values, make sure to remember that we legalized 1330 // both of them. 1331 AddLegalizedOperand(SDOperand(Node, 0), Result); 1332 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1333 return Result.getValue(Op.ResNo); 1334 1335 case ISD::TRUNCSTORE: 1336 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1337 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1338 1339 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1340 case Legal: 1341 Tmp2 = LegalizeOp(Node->getOperand(1)); 1342 1343 // The only promote case we handle is TRUNCSTORE:i1 X into 1344 // -> TRUNCSTORE:i8 (and X, 1) 1345 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1346 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1347 TargetLowering::Promote) { 1348 // Promote the bool to a mask then store. 1349 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1350 DAG.getConstant(1, Tmp2.getValueType())); 1351 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1352 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1353 1354 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1355 Tmp3 != Node->getOperand(2)) { 1356 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1357 Node->getOperand(3), Node->getOperand(4)); 1358 } 1359 break; 1360 case Promote: 1361 case Expand: 1362 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 1363 } 1364 break; 1365 case ISD::SELECT: 1366 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1367 case Expand: assert(0 && "It's impossible to expand bools"); 1368 case Legal: 1369 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1370 break; 1371 case Promote: 1372 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1373 break; 1374 } 1375 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1376 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1377 1378 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1379 default: assert(0 && "This action is not supported yet!"); 1380 case TargetLowering::Expand: 1381 if (Tmp1.getOpcode() == ISD::SETCC) { 1382 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1383 Tmp2, Tmp3, 1384 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1385 } else { 1386 // Make sure the condition is either zero or one. It may have been 1387 // promoted from something else. 1388 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1389 Result = DAG.getSelectCC(Tmp1, 1390 DAG.getConstant(0, Tmp1.getValueType()), 1391 Tmp2, Tmp3, ISD::SETNE); 1392 } 1393 Result = LegalizeOp(Result); // Relegalize new nodes. 1394 break; 1395 case TargetLowering::Custom: { 1396 SDOperand Tmp = 1397 TLI.LowerOperation(DAG.getNode(ISD::SELECT, Node->getValueType(0), 1398 Tmp1, Tmp2, Tmp3), DAG); 1399 if (Tmp.Val) { 1400 Result = LegalizeOp(Tmp); 1401 break; 1402 } 1403 // FALLTHROUGH if the target thinks it is legal. 1404 } 1405 case TargetLowering::Legal: 1406 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1407 Tmp3 != Node->getOperand(2)) 1408 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 1409 Tmp1, Tmp2, Tmp3); 1410 break; 1411 case TargetLowering::Promote: { 1412 MVT::ValueType NVT = 1413 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1414 unsigned ExtOp, TruncOp; 1415 if (MVT::isInteger(Tmp2.getValueType())) { 1416 ExtOp = ISD::ANY_EXTEND; 1417 TruncOp = ISD::TRUNCATE; 1418 } else { 1419 ExtOp = ISD::FP_EXTEND; 1420 TruncOp = ISD::FP_ROUND; 1421 } 1422 // Promote each of the values to the new type. 1423 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1424 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1425 // Perform the larger operation, then round down. 1426 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1427 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1428 break; 1429 } 1430 } 1431 break; 1432 case ISD::SELECT_CC: 1433 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1434 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1435 1436 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1437 // Everything is legal, see if we should expand this op or something. 1438 switch (TLI.getOperationAction(ISD::SELECT_CC, 1439 Node->getOperand(0).getValueType())) { 1440 default: assert(0 && "This action is not supported yet!"); 1441 case TargetLowering::Custom: { 1442 SDOperand Tmp = 1443 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), 1444 Node->getOperand(0), 1445 Node->getOperand(1), Tmp3, Tmp4, 1446 Node->getOperand(4)), DAG); 1447 if (Tmp.Val) { 1448 Result = LegalizeOp(Tmp); 1449 break; 1450 } 1451 } // FALLTHROUGH if the target can't lower this operation after all. 1452 case TargetLowering::Legal: 1453 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1454 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1455 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1456 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { 1457 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2, 1458 Tmp3, Tmp4, Node->getOperand(4)); 1459 } 1460 break; 1461 } 1462 break; 1463 } else { 1464 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1465 Node->getOperand(0), // LHS 1466 Node->getOperand(1), // RHS 1467 Node->getOperand(4))); 1468 // If we get a SETCC back from legalizing the SETCC node we just 1469 // created, then use its LHS, RHS, and CC directly in creating a new 1470 // node. Otherwise, select between the true and false value based on 1471 // comparing the result of the legalized with zero. 1472 if (Tmp1.getOpcode() == ISD::SETCC) { 1473 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1474 Tmp1.getOperand(0), Tmp1.getOperand(1), 1475 Tmp3, Tmp4, Tmp1.getOperand(2)); 1476 } else { 1477 Result = DAG.getSelectCC(Tmp1, 1478 DAG.getConstant(0, Tmp1.getValueType()), 1479 Tmp3, Tmp4, ISD::SETNE); 1480 } 1481 } 1482 break; 1483 case ISD::SETCC: 1484 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1485 case Legal: 1486 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1487 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1488 break; 1489 case Promote: 1490 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1491 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1492 1493 // If this is an FP compare, the operands have already been extended. 1494 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1495 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1496 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1497 1498 // Otherwise, we have to insert explicit sign or zero extends. Note 1499 // that we could insert sign extends for ALL conditions, but zero extend 1500 // is cheaper on many machines (an AND instead of two shifts), so prefer 1501 // it. 1502 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1503 default: assert(0 && "Unknown integer comparison!"); 1504 case ISD::SETEQ: 1505 case ISD::SETNE: 1506 case ISD::SETUGE: 1507 case ISD::SETUGT: 1508 case ISD::SETULE: 1509 case ISD::SETULT: 1510 // ALL of these operations will work if we either sign or zero extend 1511 // the operands (including the unsigned comparisons!). Zero extend is 1512 // usually a simpler/cheaper operation, so prefer it. 1513 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1514 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1515 break; 1516 case ISD::SETGE: 1517 case ISD::SETGT: 1518 case ISD::SETLT: 1519 case ISD::SETLE: 1520 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1521 DAG.getValueType(VT)); 1522 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1523 DAG.getValueType(VT)); 1524 break; 1525 } 1526 } 1527 break; 1528 case Expand: 1529 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1530 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1531 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1532 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1533 case ISD::SETEQ: 1534 case ISD::SETNE: 1535 if (RHSLo == RHSHi) 1536 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1537 if (RHSCST->isAllOnesValue()) { 1538 // Comparison to -1. 1539 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1540 Tmp2 = RHSLo; 1541 break; 1542 } 1543 1544 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1545 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1546 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1547 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1548 break; 1549 default: 1550 // If this is a comparison of the sign bit, just look at the top part. 1551 // X > -1, x < 0 1552 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1553 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1554 CST->getValue() == 0) || // X < 0 1555 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1556 (CST->isAllOnesValue()))) { // X > -1 1557 Tmp1 = LHSHi; 1558 Tmp2 = RHSHi; 1559 break; 1560 } 1561 1562 // FIXME: This generated code sucks. 1563 ISD::CondCode LowCC; 1564 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1565 default: assert(0 && "Unknown integer setcc!"); 1566 case ISD::SETLT: 1567 case ISD::SETULT: LowCC = ISD::SETULT; break; 1568 case ISD::SETGT: 1569 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1570 case ISD::SETLE: 1571 case ISD::SETULE: LowCC = ISD::SETULE; break; 1572 case ISD::SETGE: 1573 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1574 } 1575 1576 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1577 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1578 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1579 1580 // NOTE: on targets without efficient SELECT of bools, we can always use 1581 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1582 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1583 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1584 Node->getOperand(2)); 1585 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1586 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1587 Result, Tmp1, Tmp2)); 1588 AddLegalizedOperand(SDOperand(Node, 0), Result); 1589 return Result; 1590 } 1591 } 1592 1593 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) { 1594 default: 1595 assert(0 && "Cannot handle this action for SETCC yet!"); 1596 break; 1597 case TargetLowering::Promote: { 1598 // First step, figure out the appropriate operation to use. 1599 // Allow SETCC to not be supported for all legal data types 1600 // Mostly this targets FP 1601 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1602 MVT::ValueType OldVT = NewInTy; 1603 1604 // Scan for the appropriate larger type to use. 1605 while (1) { 1606 NewInTy = (MVT::ValueType)(NewInTy+1); 1607 1608 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1609 "Fell off of the edge of the integer world"); 1610 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1611 "Fell off of the edge of the floating point world"); 1612 1613 // If the target supports SETCC of this type, use it. 1614 if (TLI.getOperationAction(ISD::SETCC, NewInTy) == TargetLowering::Legal) 1615 break; 1616 } 1617 if (MVT::isInteger(NewInTy)) 1618 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1619 else { 1620 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1621 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1622 } 1623 1624 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1625 Node->getOperand(2)); 1626 break; 1627 } 1628 case TargetLowering::Custom: { 1629 SDOperand Tmp = 1630 TLI.LowerOperation(DAG.getNode(ISD::SETCC, Node->getValueType(0), 1631 Tmp1, Tmp2, Node->getOperand(2)), DAG); 1632 if (Tmp.Val) { 1633 Result = LegalizeOp(Tmp); 1634 break; 1635 } 1636 // FALLTHROUGH if the target thinks it is legal. 1637 } 1638 case TargetLowering::Legal: 1639 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1640 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1641 Node->getOperand(2)); 1642 break; 1643 case TargetLowering::Expand: 1644 // Expand a setcc node into a select_cc of the same condition, lhs, and 1645 // rhs that selects between const 1 (true) and const 0 (false). 1646 MVT::ValueType VT = Node->getValueType(0); 1647 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1648 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1649 Node->getOperand(2)); 1650 Result = LegalizeOp(Result); 1651 break; 1652 } 1653 break; 1654 1655 case ISD::MEMSET: 1656 case ISD::MEMCPY: 1657 case ISD::MEMMOVE: { 1658 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1659 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1660 1661 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1662 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1663 case Expand: assert(0 && "Cannot expand a byte!"); 1664 case Legal: 1665 Tmp3 = LegalizeOp(Node->getOperand(2)); 1666 break; 1667 case Promote: 1668 Tmp3 = PromoteOp(Node->getOperand(2)); 1669 break; 1670 } 1671 } else { 1672 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1673 } 1674 1675 SDOperand Tmp4; 1676 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1677 case Expand: { 1678 // Length is too big, just take the lo-part of the length. 1679 SDOperand HiPart; 1680 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1681 break; 1682 } 1683 case Legal: 1684 Tmp4 = LegalizeOp(Node->getOperand(3)); 1685 break; 1686 case Promote: 1687 Tmp4 = PromoteOp(Node->getOperand(3)); 1688 break; 1689 } 1690 1691 SDOperand Tmp5; 1692 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1693 case Expand: assert(0 && "Cannot expand this yet!"); 1694 case Legal: 1695 Tmp5 = LegalizeOp(Node->getOperand(4)); 1696 break; 1697 case Promote: 1698 Tmp5 = PromoteOp(Node->getOperand(4)); 1699 break; 1700 } 1701 1702 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1703 default: assert(0 && "This action not implemented for this operation!"); 1704 case TargetLowering::Custom: { 1705 SDOperand Tmp = 1706 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 1707 Tmp2, Tmp3, Tmp4, Tmp5), DAG); 1708 if (Tmp.Val) { 1709 Result = LegalizeOp(Tmp); 1710 break; 1711 } 1712 // FALLTHROUGH if the target thinks it is legal. 1713 } 1714 case TargetLowering::Legal: 1715 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1716 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 1717 Tmp5 != Node->getOperand(4)) { 1718 std::vector<SDOperand> Ops; 1719 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 1720 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 1721 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 1722 } 1723 break; 1724 case TargetLowering::Expand: { 1725 // Otherwise, the target does not support this operation. Lower the 1726 // operation to an explicit libcall as appropriate. 1727 MVT::ValueType IntPtr = TLI.getPointerTy(); 1728 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1729 std::vector<std::pair<SDOperand, const Type*> > Args; 1730 1731 const char *FnName = 0; 1732 if (Node->getOpcode() == ISD::MEMSET) { 1733 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1734 // Extend the ubyte argument to be an int value for the call. 1735 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1736 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1737 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1738 1739 FnName = "memset"; 1740 } else if (Node->getOpcode() == ISD::MEMCPY || 1741 Node->getOpcode() == ISD::MEMMOVE) { 1742 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1743 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1744 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1745 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1746 } else { 1747 assert(0 && "Unknown op!"); 1748 } 1749 1750 std::pair<SDOperand,SDOperand> CallResult = 1751 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1752 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1753 Result = LegalizeOp(CallResult.second); 1754 break; 1755 } 1756 } 1757 break; 1758 } 1759 1760 case ISD::READPORT: 1761 Tmp1 = LegalizeOp(Node->getOperand(0)); 1762 Tmp2 = LegalizeOp(Node->getOperand(1)); 1763 1764 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1765 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1766 std::vector<SDOperand> Ops; 1767 Ops.push_back(Tmp1); 1768 Ops.push_back(Tmp2); 1769 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1770 } else 1771 Result = SDOperand(Node, 0); 1772 // Since these produce two values, make sure to remember that we legalized 1773 // both of them. 1774 AddLegalizedOperand(SDOperand(Node, 0), Result); 1775 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1776 return Result.getValue(Op.ResNo); 1777 case ISD::WRITEPORT: 1778 Tmp1 = LegalizeOp(Node->getOperand(0)); 1779 Tmp2 = LegalizeOp(Node->getOperand(1)); 1780 Tmp3 = LegalizeOp(Node->getOperand(2)); 1781 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1782 Tmp3 != Node->getOperand(2)) 1783 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1784 break; 1785 1786 case ISD::READIO: 1787 Tmp1 = LegalizeOp(Node->getOperand(0)); 1788 Tmp2 = LegalizeOp(Node->getOperand(1)); 1789 1790 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1791 case TargetLowering::Custom: 1792 default: assert(0 && "This action not implemented for this operation!"); 1793 case TargetLowering::Legal: 1794 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1795 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1796 std::vector<SDOperand> Ops; 1797 Ops.push_back(Tmp1); 1798 Ops.push_back(Tmp2); 1799 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1800 } else 1801 Result = SDOperand(Node, 0); 1802 break; 1803 case TargetLowering::Expand: 1804 // Replace this with a load from memory. 1805 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 1806 Node->getOperand(1), DAG.getSrcValue(NULL)); 1807 Result = LegalizeOp(Result); 1808 break; 1809 } 1810 1811 // Since these produce two values, make sure to remember that we legalized 1812 // both of them. 1813 AddLegalizedOperand(SDOperand(Node, 0), Result); 1814 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1815 return Result.getValue(Op.ResNo); 1816 1817 case ISD::WRITEIO: 1818 Tmp1 = LegalizeOp(Node->getOperand(0)); 1819 Tmp2 = LegalizeOp(Node->getOperand(1)); 1820 Tmp3 = LegalizeOp(Node->getOperand(2)); 1821 1822 switch (TLI.getOperationAction(Node->getOpcode(), 1823 Node->getOperand(1).getValueType())) { 1824 case TargetLowering::Custom: 1825 default: assert(0 && "This action not implemented for this operation!"); 1826 case TargetLowering::Legal: 1827 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1828 Tmp3 != Node->getOperand(2)) 1829 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1830 break; 1831 case TargetLowering::Expand: 1832 // Replace this with a store to memory. 1833 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 1834 Node->getOperand(1), Node->getOperand(2), 1835 DAG.getSrcValue(NULL)); 1836 Result = LegalizeOp(Result); 1837 break; 1838 } 1839 break; 1840 1841 case ISD::ADD_PARTS: 1842 case ISD::SUB_PARTS: 1843 case ISD::SHL_PARTS: 1844 case ISD::SRA_PARTS: 1845 case ISD::SRL_PARTS: { 1846 std::vector<SDOperand> Ops; 1847 bool Changed = false; 1848 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1849 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1850 Changed |= Ops.back() != Node->getOperand(i); 1851 } 1852 if (Changed) { 1853 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1854 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 1855 } 1856 1857 // Since these produce multiple values, make sure to remember that we 1858 // legalized all of them. 1859 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1860 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1861 return Result.getValue(Op.ResNo); 1862 } 1863 1864 // Binary operators 1865 case ISD::ADD: 1866 case ISD::SUB: 1867 case ISD::MUL: 1868 case ISD::MULHS: 1869 case ISD::MULHU: 1870 case ISD::UDIV: 1871 case ISD::SDIV: 1872 case ISD::AND: 1873 case ISD::OR: 1874 case ISD::XOR: 1875 case ISD::SHL: 1876 case ISD::SRL: 1877 case ISD::SRA: 1878 case ISD::FADD: 1879 case ISD::FSUB: 1880 case ISD::FMUL: 1881 case ISD::FDIV: 1882 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1883 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1884 case Expand: assert(0 && "Not possible"); 1885 case Legal: 1886 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1887 break; 1888 case Promote: 1889 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 1890 break; 1891 } 1892 if (Tmp1 != Node->getOperand(0) || 1893 Tmp2 != Node->getOperand(1)) 1894 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 1895 break; 1896 1897 case ISD::BUILD_PAIR: { 1898 MVT::ValueType PairTy = Node->getValueType(0); 1899 // TODO: handle the case where the Lo and Hi operands are not of legal type 1900 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 1901 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 1902 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 1903 case TargetLowering::Legal: 1904 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1905 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 1906 break; 1907 case TargetLowering::Promote: 1908 case TargetLowering::Custom: 1909 assert(0 && "Cannot promote/custom this yet!"); 1910 case TargetLowering::Expand: 1911 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 1912 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 1913 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 1914 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 1915 TLI.getShiftAmountTy())); 1916 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2)); 1917 break; 1918 } 1919 break; 1920 } 1921 1922 case ISD::UREM: 1923 case ISD::SREM: 1924 case ISD::FREM: 1925 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1926 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1927 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1928 case TargetLowering::Legal: 1929 if (Tmp1 != Node->getOperand(0) || 1930 Tmp2 != Node->getOperand(1)) 1931 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1932 Tmp2); 1933 break; 1934 case TargetLowering::Promote: 1935 case TargetLowering::Custom: 1936 assert(0 && "Cannot promote/custom handle this yet!"); 1937 case TargetLowering::Expand: 1938 if (MVT::isInteger(Node->getValueType(0))) { 1939 MVT::ValueType VT = Node->getValueType(0); 1940 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 1941 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 1942 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 1943 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 1944 } else { 1945 // Floating point mod -> fmod libcall. 1946 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 1947 SDOperand Dummy; 1948 Result = ExpandLibCall(FnName, Node, Dummy); 1949 } 1950 break; 1951 } 1952 break; 1953 1954 case ISD::CTPOP: 1955 case ISD::CTTZ: 1956 case ISD::CTLZ: 1957 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1958 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1959 case TargetLowering::Legal: 1960 if (Tmp1 != Node->getOperand(0)) 1961 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1962 break; 1963 case TargetLowering::Promote: { 1964 MVT::ValueType OVT = Tmp1.getValueType(); 1965 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1966 1967 // Zero extend the argument. 1968 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1969 // Perform the larger operation, then subtract if needed. 1970 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1971 switch(Node->getOpcode()) 1972 { 1973 case ISD::CTPOP: 1974 Result = Tmp1; 1975 break; 1976 case ISD::CTTZ: 1977 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 1978 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 1979 DAG.getConstant(getSizeInBits(NVT), NVT), 1980 ISD::SETEQ); 1981 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 1982 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 1983 break; 1984 case ISD::CTLZ: 1985 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 1986 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 1987 DAG.getConstant(getSizeInBits(NVT) - 1988 getSizeInBits(OVT), NVT)); 1989 break; 1990 } 1991 break; 1992 } 1993 case TargetLowering::Custom: 1994 assert(0 && "Cannot custom handle this yet!"); 1995 case TargetLowering::Expand: 1996 switch(Node->getOpcode()) 1997 { 1998 case ISD::CTPOP: { 1999 static const uint64_t mask[6] = { 2000 0x5555555555555555ULL, 0x3333333333333333ULL, 2001 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2002 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2003 }; 2004 MVT::ValueType VT = Tmp1.getValueType(); 2005 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 2006 unsigned len = getSizeInBits(VT); 2007 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2008 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2009 Tmp2 = DAG.getConstant(mask[i], VT); 2010 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2011 Tmp1 = DAG.getNode(ISD::ADD, VT, 2012 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 2013 DAG.getNode(ISD::AND, VT, 2014 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 2015 Tmp2)); 2016 } 2017 Result = Tmp1; 2018 break; 2019 } 2020 case ISD::CTLZ: { 2021 /* for now, we do this: 2022 x = x | (x >> 1); 2023 x = x | (x >> 2); 2024 ... 2025 x = x | (x >>16); 2026 x = x | (x >>32); // for 64-bit input 2027 return popcount(~x); 2028 2029 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ 2030 MVT::ValueType VT = Tmp1.getValueType(); 2031 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 2032 unsigned len = getSizeInBits(VT); 2033 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2034 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2035 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, 2036 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); 2037 } 2038 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); 2039 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 2040 break; 2041 } 2042 case ISD::CTTZ: { 2043 // for now, we use: { return popcount(~x & (x - 1)); } 2044 // unless the target has ctlz but not ctpop, in which case we use: 2045 // { return 32 - nlz(~x & (x-1)); } 2046 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2047 MVT::ValueType VT = Tmp1.getValueType(); 2048 Tmp2 = DAG.getConstant(~0ULL, VT); 2049 Tmp3 = DAG.getNode(ISD::AND, VT, 2050 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), 2051 DAG.getNode(ISD::SUB, VT, Tmp1, 2052 DAG.getConstant(1, VT))); 2053 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead 2054 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 2055 TLI.isOperationLegal(ISD::CTLZ, VT)) { 2056 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, 2057 DAG.getConstant(getSizeInBits(VT), VT), 2058 DAG.getNode(ISD::CTLZ, VT, Tmp3))); 2059 } else { 2060 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 2061 } 2062 break; 2063 } 2064 default: 2065 assert(0 && "Cannot expand this yet!"); 2066 break; 2067 } 2068 break; 2069 } 2070 break; 2071 2072 // Unary operators 2073 case ISD::FABS: 2074 case ISD::FNEG: 2075 case ISD::FSQRT: 2076 case ISD::FSIN: 2077 case ISD::FCOS: 2078 Tmp1 = LegalizeOp(Node->getOperand(0)); 2079 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2080 case TargetLowering::Legal: 2081 if (Tmp1 != Node->getOperand(0)) 2082 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2083 break; 2084 case TargetLowering::Promote: 2085 case TargetLowering::Custom: 2086 assert(0 && "Cannot promote/custom handle this yet!"); 2087 case TargetLowering::Expand: 2088 switch(Node->getOpcode()) { 2089 case ISD::FNEG: { 2090 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2091 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2092 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0), 2093 Tmp2, Tmp1)); 2094 break; 2095 } 2096 case ISD::FABS: { 2097 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2098 MVT::ValueType VT = Node->getValueType(0); 2099 Tmp2 = DAG.getConstantFP(0.0, VT); 2100 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2101 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2102 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2103 Result = LegalizeOp(Result); 2104 break; 2105 } 2106 case ISD::FSQRT: 2107 case ISD::FSIN: 2108 case ISD::FCOS: { 2109 MVT::ValueType VT = Node->getValueType(0); 2110 const char *FnName = 0; 2111 switch(Node->getOpcode()) { 2112 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 2113 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 2114 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 2115 default: assert(0 && "Unreachable!"); 2116 } 2117 SDOperand Dummy; 2118 Result = ExpandLibCall(FnName, Node, Dummy); 2119 break; 2120 } 2121 default: 2122 assert(0 && "Unreachable!"); 2123 } 2124 break; 2125 } 2126 break; 2127 2128 // Conversion operators. The source and destination have different types. 2129 case ISD::SINT_TO_FP: 2130 case ISD::UINT_TO_FP: { 2131 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2132 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2133 case Legal: 2134 switch (TLI.getOperationAction(Node->getOpcode(), 2135 Node->getOperand(0).getValueType())) { 2136 default: assert(0 && "Unknown operation action!"); 2137 case TargetLowering::Expand: 2138 Result = ExpandLegalINT_TO_FP(isSigned, 2139 LegalizeOp(Node->getOperand(0)), 2140 Node->getValueType(0)); 2141 AddLegalizedOperand(Op, Result); 2142 return Result; 2143 case TargetLowering::Promote: 2144 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2145 Node->getValueType(0), 2146 isSigned); 2147 AddLegalizedOperand(Op, Result); 2148 return Result; 2149 case TargetLowering::Legal: 2150 break; 2151 case TargetLowering::Custom: { 2152 Tmp1 = LegalizeOp(Node->getOperand(0)); 2153 SDOperand Tmp = 2154 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2155 Tmp = TLI.LowerOperation(Tmp, DAG); 2156 if (Tmp.Val) { 2157 Tmp = LegalizeOp(Tmp); // Relegalize input. 2158 AddLegalizedOperand(Op, Tmp); 2159 return Tmp; 2160 } else { 2161 assert(0 && "Target Must Lower this"); 2162 } 2163 } 2164 } 2165 2166 Tmp1 = LegalizeOp(Node->getOperand(0)); 2167 if (Tmp1 != Node->getOperand(0)) 2168 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2169 break; 2170 case Expand: 2171 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2172 Node->getValueType(0), Node->getOperand(0)); 2173 break; 2174 case Promote: 2175 if (isSigned) { 2176 Result = PromoteOp(Node->getOperand(0)); 2177 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2178 Result, DAG.getValueType(Node->getOperand(0).getValueType())); 2179 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 2180 } else { 2181 Result = PromoteOp(Node->getOperand(0)); 2182 Result = DAG.getZeroExtendInReg(Result, 2183 Node->getOperand(0).getValueType()); 2184 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 2185 } 2186 break; 2187 } 2188 break; 2189 } 2190 case ISD::TRUNCATE: 2191 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2192 case Legal: 2193 Tmp1 = LegalizeOp(Node->getOperand(0)); 2194 if (Tmp1 != Node->getOperand(0)) 2195 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2196 break; 2197 case Expand: 2198 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2199 2200 // Since the result is legal, we should just be able to truncate the low 2201 // part of the source. 2202 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2203 break; 2204 case Promote: 2205 Result = PromoteOp(Node->getOperand(0)); 2206 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2207 break; 2208 } 2209 break; 2210 2211 case ISD::FP_TO_SINT: 2212 case ISD::FP_TO_UINT: 2213 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2214 case Legal: 2215 Tmp1 = LegalizeOp(Node->getOperand(0)); 2216 2217 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2218 default: assert(0 && "Unknown operation action!"); 2219 case TargetLowering::Expand: 2220 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2221 SDOperand True, False; 2222 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2223 MVT::ValueType NVT = Node->getValueType(0); 2224 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2225 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2226 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2227 Node->getOperand(0), Tmp2, ISD::SETLT); 2228 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2229 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2230 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2231 Tmp2)); 2232 False = DAG.getNode(ISD::XOR, NVT, False, 2233 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2234 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False)); 2235 AddLegalizedOperand(SDOperand(Node, 0), Result); 2236 return Result; 2237 } else { 2238 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2239 } 2240 break; 2241 case TargetLowering::Promote: 2242 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2243 Node->getOpcode() == ISD::FP_TO_SINT); 2244 AddLegalizedOperand(Op, Result); 2245 return Result; 2246 case TargetLowering::Custom: { 2247 SDOperand Tmp = 2248 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2249 Tmp = TLI.LowerOperation(Tmp, DAG); 2250 if (Tmp.Val) { 2251 Tmp = LegalizeOp(Tmp); 2252 AddLegalizedOperand(Op, Tmp); 2253 return Tmp; 2254 } else { 2255 // The target thinks this is legal afterall. 2256 break; 2257 } 2258 } 2259 case TargetLowering::Legal: 2260 break; 2261 } 2262 2263 if (Tmp1 != Node->getOperand(0)) 2264 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2265 break; 2266 case Expand: 2267 assert(0 && "Shouldn't need to expand other operators here!"); 2268 case Promote: 2269 Result = PromoteOp(Node->getOperand(0)); 2270 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2271 break; 2272 } 2273 break; 2274 2275 case ISD::ANY_EXTEND: 2276 case ISD::ZERO_EXTEND: 2277 case ISD::SIGN_EXTEND: 2278 case ISD::FP_EXTEND: 2279 case ISD::FP_ROUND: 2280 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2281 case Legal: 2282 Tmp1 = LegalizeOp(Node->getOperand(0)); 2283 if (Tmp1 != Node->getOperand(0)) 2284 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2285 break; 2286 case Expand: 2287 assert(0 && "Shouldn't need to expand other operators here!"); 2288 2289 case Promote: 2290 switch (Node->getOpcode()) { 2291 case ISD::ANY_EXTEND: 2292 Result = PromoteOp(Node->getOperand(0)); 2293 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2294 break; 2295 case ISD::ZERO_EXTEND: 2296 Result = PromoteOp(Node->getOperand(0)); 2297 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2298 Result = DAG.getZeroExtendInReg(Result, 2299 Node->getOperand(0).getValueType()); 2300 break; 2301 case ISD::SIGN_EXTEND: 2302 Result = PromoteOp(Node->getOperand(0)); 2303 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2304 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2305 Result, 2306 DAG.getValueType(Node->getOperand(0).getValueType())); 2307 break; 2308 case ISD::FP_EXTEND: 2309 Result = PromoteOp(Node->getOperand(0)); 2310 if (Result.getValueType() != Op.getValueType()) 2311 // Dynamically dead while we have only 2 FP types. 2312 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2313 break; 2314 case ISD::FP_ROUND: 2315 Result = PromoteOp(Node->getOperand(0)); 2316 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2317 break; 2318 } 2319 } 2320 break; 2321 case ISD::FP_ROUND_INREG: 2322 case ISD::SIGN_EXTEND_INREG: { 2323 Tmp1 = LegalizeOp(Node->getOperand(0)); 2324 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2325 2326 // If this operation is not supported, convert it to a shl/shr or load/store 2327 // pair. 2328 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2329 default: assert(0 && "This action not supported for this op yet!"); 2330 case TargetLowering::Legal: 2331 if (Tmp1 != Node->getOperand(0)) 2332 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2333 DAG.getValueType(ExtraVT)); 2334 break; 2335 case TargetLowering::Expand: 2336 // If this is an integer extend and shifts are supported, do that. 2337 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2338 // NOTE: we could fall back on load/store here too for targets without 2339 // SAR. However, it is doubtful that any exist. 2340 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2341 MVT::getSizeInBits(ExtraVT); 2342 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2343 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2344 Node->getOperand(0), ShiftCst); 2345 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2346 Result, ShiftCst); 2347 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2348 // The only way we can lower this is to turn it into a STORETRUNC, 2349 // EXTLOAD pair, targetting a temporary location (a stack slot). 2350 2351 // NOTE: there is a choice here between constantly creating new stack 2352 // slots and always reusing the same one. We currently always create 2353 // new ones, as reuse may inhibit scheduling. 2354 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2355 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2356 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2357 MachineFunction &MF = DAG.getMachineFunction(); 2358 int SSFI = 2359 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2360 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2361 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2362 Node->getOperand(0), StackSlot, 2363 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2364 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2365 Result, StackSlot, DAG.getSrcValue(NULL), 2366 ExtraVT); 2367 } else { 2368 assert(0 && "Unknown op"); 2369 } 2370 Result = LegalizeOp(Result); 2371 break; 2372 } 2373 break; 2374 } 2375 } 2376 2377 // Note that LegalizeOp may be reentered even from single-use nodes, which 2378 // means that we always must cache transformed nodes. 2379 AddLegalizedOperand(Op, Result); 2380 return Result; 2381} 2382 2383/// PromoteOp - Given an operation that produces a value in an invalid type, 2384/// promote it to compute the value into a larger type. The produced value will 2385/// have the correct bits for the low portion of the register, but no guarantee 2386/// is made about the top bits: it may be zero, sign-extended, or garbage. 2387SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2388 MVT::ValueType VT = Op.getValueType(); 2389 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2390 assert(getTypeAction(VT) == Promote && 2391 "Caller should expand or legalize operands that are not promotable!"); 2392 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2393 "Cannot promote to smaller type!"); 2394 2395 SDOperand Tmp1, Tmp2, Tmp3; 2396 2397 SDOperand Result; 2398 SDNode *Node = Op.Val; 2399 2400 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2401 if (I != PromotedNodes.end()) return I->second; 2402 2403 // Promotion needs an optimization step to clean up after it, and is not 2404 // careful to avoid operations the target does not support. Make sure that 2405 // all generated operations are legalized in the next iteration. 2406 NeedsAnotherIteration = true; 2407 2408 switch (Node->getOpcode()) { 2409 case ISD::CopyFromReg: 2410 assert(0 && "CopyFromReg must be legal!"); 2411 default: 2412 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2413 assert(0 && "Do not know how to promote this operator!"); 2414 abort(); 2415 case ISD::UNDEF: 2416 Result = DAG.getNode(ISD::UNDEF, NVT); 2417 break; 2418 case ISD::Constant: 2419 if (VT != MVT::i1) 2420 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2421 else 2422 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2423 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2424 break; 2425 case ISD::ConstantFP: 2426 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2427 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2428 break; 2429 2430 case ISD::SETCC: 2431 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2432 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2433 Node->getOperand(1), Node->getOperand(2)); 2434 Result = LegalizeOp(Result); 2435 break; 2436 2437 case ISD::TRUNCATE: 2438 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2439 case Legal: 2440 Result = LegalizeOp(Node->getOperand(0)); 2441 assert(Result.getValueType() >= NVT && 2442 "This truncation doesn't make sense!"); 2443 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2444 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2445 break; 2446 case Promote: 2447 // The truncation is not required, because we don't guarantee anything 2448 // about high bits anyway. 2449 Result = PromoteOp(Node->getOperand(0)); 2450 break; 2451 case Expand: 2452 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2453 // Truncate the low part of the expanded value to the result type 2454 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2455 } 2456 break; 2457 case ISD::SIGN_EXTEND: 2458 case ISD::ZERO_EXTEND: 2459 case ISD::ANY_EXTEND: 2460 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2461 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2462 case Legal: 2463 // Input is legal? Just do extend all the way to the larger type. 2464 Result = LegalizeOp(Node->getOperand(0)); 2465 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2466 break; 2467 case Promote: 2468 // Promote the reg if it's smaller. 2469 Result = PromoteOp(Node->getOperand(0)); 2470 // The high bits are not guaranteed to be anything. Insert an extend. 2471 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2472 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2473 DAG.getValueType(Node->getOperand(0).getValueType())); 2474 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2475 Result = DAG.getZeroExtendInReg(Result, 2476 Node->getOperand(0).getValueType()); 2477 break; 2478 } 2479 break; 2480 2481 case ISD::FP_EXTEND: 2482 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2483 case ISD::FP_ROUND: 2484 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2485 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2486 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2487 case Legal: 2488 // Input is legal? Do an FP_ROUND_INREG. 2489 Result = LegalizeOp(Node->getOperand(0)); 2490 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2491 DAG.getValueType(VT)); 2492 break; 2493 } 2494 break; 2495 2496 case ISD::SINT_TO_FP: 2497 case ISD::UINT_TO_FP: 2498 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2499 case Legal: 2500 Result = LegalizeOp(Node->getOperand(0)); 2501 // No extra round required here. 2502 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2503 break; 2504 2505 case Promote: 2506 Result = PromoteOp(Node->getOperand(0)); 2507 if (Node->getOpcode() == ISD::SINT_TO_FP) 2508 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2509 Result, 2510 DAG.getValueType(Node->getOperand(0).getValueType())); 2511 else 2512 Result = DAG.getZeroExtendInReg(Result, 2513 Node->getOperand(0).getValueType()); 2514 // No extra round required here. 2515 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2516 break; 2517 case Expand: 2518 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2519 Node->getOperand(0)); 2520 // Round if we cannot tolerate excess precision. 2521 if (NoExcessFPPrecision) 2522 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2523 DAG.getValueType(VT)); 2524 break; 2525 } 2526 break; 2527 2528 case ISD::SIGN_EXTEND_INREG: 2529 Result = PromoteOp(Node->getOperand(0)); 2530 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2531 Node->getOperand(1)); 2532 break; 2533 case ISD::FP_TO_SINT: 2534 case ISD::FP_TO_UINT: 2535 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2536 case Legal: 2537 Tmp1 = LegalizeOp(Node->getOperand(0)); 2538 break; 2539 case Promote: 2540 // The input result is prerounded, so we don't have to do anything 2541 // special. 2542 Tmp1 = PromoteOp(Node->getOperand(0)); 2543 break; 2544 case Expand: 2545 assert(0 && "not implemented"); 2546 } 2547 // If we're promoting a UINT to a larger size, check to see if the new node 2548 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2549 // we can use that instead. This allows us to generate better code for 2550 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2551 // legal, such as PowerPC. 2552 if (Node->getOpcode() == ISD::FP_TO_UINT && 2553 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2554 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2555 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2556 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2557 } else { 2558 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2559 } 2560 break; 2561 2562 case ISD::FABS: 2563 case ISD::FNEG: 2564 Tmp1 = PromoteOp(Node->getOperand(0)); 2565 assert(Tmp1.getValueType() == NVT); 2566 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2567 // NOTE: we do not have to do any extra rounding here for 2568 // NoExcessFPPrecision, because we know the input will have the appropriate 2569 // precision, and these operations don't modify precision at all. 2570 break; 2571 2572 case ISD::FSQRT: 2573 case ISD::FSIN: 2574 case ISD::FCOS: 2575 Tmp1 = PromoteOp(Node->getOperand(0)); 2576 assert(Tmp1.getValueType() == NVT); 2577 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2578 if(NoExcessFPPrecision) 2579 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2580 DAG.getValueType(VT)); 2581 break; 2582 2583 case ISD::AND: 2584 case ISD::OR: 2585 case ISD::XOR: 2586 case ISD::ADD: 2587 case ISD::SUB: 2588 case ISD::MUL: 2589 // The input may have strange things in the top bits of the registers, but 2590 // these operations don't care. They may have weird bits going out, but 2591 // that too is okay if they are integer operations. 2592 Tmp1 = PromoteOp(Node->getOperand(0)); 2593 Tmp2 = PromoteOp(Node->getOperand(1)); 2594 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2595 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2596 break; 2597 case ISD::FADD: 2598 case ISD::FSUB: 2599 case ISD::FMUL: 2600 // The input may have strange things in the top bits of the registers, but 2601 // these operations don't care. 2602 Tmp1 = PromoteOp(Node->getOperand(0)); 2603 Tmp2 = PromoteOp(Node->getOperand(1)); 2604 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2605 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2606 2607 // Floating point operations will give excess precision that we may not be 2608 // able to tolerate. If we DO allow excess precision, just leave it, 2609 // otherwise excise it. 2610 // FIXME: Why would we need to round FP ops more than integer ones? 2611 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2612 if (NoExcessFPPrecision) 2613 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2614 DAG.getValueType(VT)); 2615 break; 2616 2617 case ISD::SDIV: 2618 case ISD::SREM: 2619 // These operators require that their input be sign extended. 2620 Tmp1 = PromoteOp(Node->getOperand(0)); 2621 Tmp2 = PromoteOp(Node->getOperand(1)); 2622 if (MVT::isInteger(NVT)) { 2623 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2624 DAG.getValueType(VT)); 2625 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2626 DAG.getValueType(VT)); 2627 } 2628 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2629 2630 // Perform FP_ROUND: this is probably overly pessimistic. 2631 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2632 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2633 DAG.getValueType(VT)); 2634 break; 2635 case ISD::FDIV: 2636 case ISD::FREM: 2637 // These operators require that their input be fp extended. 2638 Tmp1 = PromoteOp(Node->getOperand(0)); 2639 Tmp2 = PromoteOp(Node->getOperand(1)); 2640 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2641 2642 // Perform FP_ROUND: this is probably overly pessimistic. 2643 if (NoExcessFPPrecision) 2644 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2645 DAG.getValueType(VT)); 2646 break; 2647 2648 case ISD::UDIV: 2649 case ISD::UREM: 2650 // These operators require that their input be zero extended. 2651 Tmp1 = PromoteOp(Node->getOperand(0)); 2652 Tmp2 = PromoteOp(Node->getOperand(1)); 2653 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2654 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2655 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2656 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2657 break; 2658 2659 case ISD::SHL: 2660 Tmp1 = PromoteOp(Node->getOperand(0)); 2661 Tmp2 = LegalizeOp(Node->getOperand(1)); 2662 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 2663 break; 2664 case ISD::SRA: 2665 // The input value must be properly sign extended. 2666 Tmp1 = PromoteOp(Node->getOperand(0)); 2667 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2668 DAG.getValueType(VT)); 2669 Tmp2 = LegalizeOp(Node->getOperand(1)); 2670 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 2671 break; 2672 case ISD::SRL: 2673 // The input value must be properly zero extended. 2674 Tmp1 = PromoteOp(Node->getOperand(0)); 2675 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2676 Tmp2 = LegalizeOp(Node->getOperand(1)); 2677 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 2678 break; 2679 case ISD::LOAD: 2680 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2681 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2682 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2, 2683 Node->getOperand(2), VT); 2684 // Remember that we legalized the chain. 2685 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2686 break; 2687 case ISD::SEXTLOAD: 2688 case ISD::ZEXTLOAD: 2689 case ISD::EXTLOAD: 2690 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2691 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2692 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2, 2693 Node->getOperand(2), 2694 cast<VTSDNode>(Node->getOperand(3))->getVT()); 2695 // Remember that we legalized the chain. 2696 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2697 break; 2698 case ISD::SELECT: 2699 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2700 case Expand: assert(0 && "It's impossible to expand bools"); 2701 case Legal: 2702 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 2703 break; 2704 case Promote: 2705 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2706 break; 2707 } 2708 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 2709 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 2710 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 2711 break; 2712 case ISD::SELECT_CC: 2713 Tmp2 = PromoteOp(Node->getOperand(2)); // True 2714 Tmp3 = PromoteOp(Node->getOperand(3)); // False 2715 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 2716 Node->getOperand(1), Tmp2, Tmp3, 2717 Node->getOperand(4)); 2718 break; 2719 case ISD::TAILCALL: 2720 case ISD::CALL: { 2721 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2722 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 2723 2724 std::vector<SDOperand> Ops; 2725 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 2726 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2727 2728 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 2729 "Can only promote single result calls"); 2730 std::vector<MVT::ValueType> RetTyVTs; 2731 RetTyVTs.reserve(2); 2732 RetTyVTs.push_back(NVT); 2733 RetTyVTs.push_back(MVT::Other); 2734 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 2735 Node->getOpcode() == ISD::TAILCALL); 2736 Result = SDOperand(NC, 0); 2737 2738 // Insert the new chain mapping. 2739 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2740 break; 2741 } 2742 case ISD::CTPOP: 2743 case ISD::CTTZ: 2744 case ISD::CTLZ: 2745 Tmp1 = Node->getOperand(0); 2746 //Zero extend the argument 2747 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2748 // Perform the larger operation, then subtract if needed. 2749 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2750 switch(Node->getOpcode()) 2751 { 2752 case ISD::CTPOP: 2753 Result = Tmp1; 2754 break; 2755 case ISD::CTTZ: 2756 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2757 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2758 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 2759 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2760 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 2761 break; 2762 case ISD::CTLZ: 2763 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2764 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2765 DAG.getConstant(getSizeInBits(NVT) - 2766 getSizeInBits(VT), NVT)); 2767 break; 2768 } 2769 break; 2770 } 2771 2772 assert(Result.Val && "Didn't set a result!"); 2773 AddPromotedOperand(Op, Result); 2774 return Result; 2775} 2776 2777/// ExpandAddSub - Find a clever way to expand this add operation into 2778/// subcomponents. 2779void SelectionDAGLegalize:: 2780ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 2781 SDOperand &Lo, SDOperand &Hi) { 2782 // Expand the subcomponents. 2783 SDOperand LHSL, LHSH, RHSL, RHSH; 2784 ExpandOp(LHS, LHSL, LHSH); 2785 ExpandOp(RHS, RHSL, RHSH); 2786 2787 std::vector<SDOperand> Ops; 2788 Ops.push_back(LHSL); 2789 Ops.push_back(LHSH); 2790 Ops.push_back(RHSL); 2791 Ops.push_back(RHSH); 2792 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2793 Lo = DAG.getNode(NodeOp, VTs, Ops); 2794 Hi = Lo.getValue(1); 2795} 2796 2797void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 2798 SDOperand Op, SDOperand Amt, 2799 SDOperand &Lo, SDOperand &Hi) { 2800 // Expand the subcomponents. 2801 SDOperand LHSL, LHSH; 2802 ExpandOp(Op, LHSL, LHSH); 2803 2804 std::vector<SDOperand> Ops; 2805 Ops.push_back(LHSL); 2806 Ops.push_back(LHSH); 2807 Ops.push_back(Amt); 2808 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2809 Lo = DAG.getNode(NodeOp, VTs, Ops); 2810 Hi = Lo.getValue(1); 2811} 2812 2813 2814/// ExpandShift - Try to find a clever way to expand this shift operation out to 2815/// smaller elements. If we can't find a way that is more efficient than a 2816/// libcall on this target, return false. Otherwise, return true with the 2817/// low-parts expanded into Lo and Hi. 2818bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 2819 SDOperand &Lo, SDOperand &Hi) { 2820 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 2821 "This is not a shift!"); 2822 2823 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 2824 SDOperand ShAmt = LegalizeOp(Amt); 2825 MVT::ValueType ShTy = ShAmt.getValueType(); 2826 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 2827 unsigned NVTBits = MVT::getSizeInBits(NVT); 2828 2829 // Handle the case when Amt is an immediate. Other cases are currently broken 2830 // and are disabled. 2831 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 2832 unsigned Cst = CN->getValue(); 2833 // Expand the incoming operand to be shifted, so that we have its parts 2834 SDOperand InL, InH; 2835 ExpandOp(Op, InL, InH); 2836 switch(Opc) { 2837 case ISD::SHL: 2838 if (Cst > VTBits) { 2839 Lo = DAG.getConstant(0, NVT); 2840 Hi = DAG.getConstant(0, NVT); 2841 } else if (Cst > NVTBits) { 2842 Lo = DAG.getConstant(0, NVT); 2843 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 2844 } else if (Cst == NVTBits) { 2845 Lo = DAG.getConstant(0, NVT); 2846 Hi = InL; 2847 } else { 2848 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 2849 Hi = DAG.getNode(ISD::OR, NVT, 2850 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 2851 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 2852 } 2853 return true; 2854 case ISD::SRL: 2855 if (Cst > VTBits) { 2856 Lo = DAG.getConstant(0, NVT); 2857 Hi = DAG.getConstant(0, NVT); 2858 } else if (Cst > NVTBits) { 2859 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 2860 Hi = DAG.getConstant(0, NVT); 2861 } else if (Cst == NVTBits) { 2862 Lo = InH; 2863 Hi = DAG.getConstant(0, NVT); 2864 } else { 2865 Lo = DAG.getNode(ISD::OR, NVT, 2866 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2867 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2868 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 2869 } 2870 return true; 2871 case ISD::SRA: 2872 if (Cst > VTBits) { 2873 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 2874 DAG.getConstant(NVTBits-1, ShTy)); 2875 } else if (Cst > NVTBits) { 2876 Lo = DAG.getNode(ISD::SRA, NVT, InH, 2877 DAG.getConstant(Cst-NVTBits, ShTy)); 2878 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2879 DAG.getConstant(NVTBits-1, ShTy)); 2880 } else if (Cst == NVTBits) { 2881 Lo = InH; 2882 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2883 DAG.getConstant(NVTBits-1, ShTy)); 2884 } else { 2885 Lo = DAG.getNode(ISD::OR, NVT, 2886 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2887 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2888 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 2889 } 2890 return true; 2891 } 2892 } 2893 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 2894 // so disable it for now. Currently targets are handling this via SHL_PARTS 2895 // and friends. 2896 return false; 2897 2898 // If we have an efficient select operation (or if the selects will all fold 2899 // away), lower to some complex code, otherwise just emit the libcall. 2900 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt)) 2901 return false; 2902 2903 SDOperand InL, InH; 2904 ExpandOp(Op, InL, InH); 2905 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 2906 DAG.getConstant(NVTBits, ShTy), ShAmt); 2907 2908 // Compare the unmasked shift amount against 32. 2909 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt, 2910 DAG.getConstant(NVTBits, ShTy), ISD::SETGE); 2911 2912 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 2913 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 2914 DAG.getConstant(NVTBits-1, ShTy)); 2915 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 2916 DAG.getConstant(NVTBits-1, ShTy)); 2917 } 2918 2919 if (Opc == ISD::SHL) { 2920 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 2921 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 2922 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 2923 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 2924 2925 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2926 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 2927 } else { 2928 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 2929 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt, 2930 DAG.getConstant(32, ShTy), 2931 ISD::SETEQ), 2932 DAG.getConstant(0, NVT), 2933 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 2934 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 2935 HiLoPart, 2936 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 2937 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 2938 2939 SDOperand HiPart; 2940 if (Opc == ISD::SRA) 2941 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 2942 DAG.getConstant(NVTBits-1, ShTy)); 2943 else 2944 HiPart = DAG.getConstant(0, NVT); 2945 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2946 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 2947 } 2948 return true; 2949} 2950 2951/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 2952/// NodeDepth) node that is an CallSeqStart operation and occurs later than 2953/// Found. 2954static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) { 2955 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 2956 2957 // If we found an CALLSEQ_START, we already know this node occurs later 2958 // than the Found node. Just remember this node and return. 2959 if (Node->getOpcode() == ISD::CALLSEQ_START) { 2960 Found = Node; 2961 return; 2962 } 2963 2964 // Otherwise, scan the operands of Node to see if any of them is a call. 2965 assert(Node->getNumOperands() != 0 && 2966 "All leaves should have depth equal to the entry node!"); 2967 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 2968 FindLatestCallSeqStart(Node->getOperand(i).Val, Found); 2969 2970 // Tail recurse for the last iteration. 2971 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 2972 Found); 2973} 2974 2975 2976/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 2977/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 2978/// than Found. 2979static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 2980 std::set<SDNode*> &Visited) { 2981 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 2982 !Visited.insert(Node).second) return; 2983 2984 // If we found an CALLSEQ_END, we already know this node occurs earlier 2985 // than the Found node. Just remember this node and return. 2986 if (Node->getOpcode() == ISD::CALLSEQ_END) { 2987 Found = Node; 2988 return; 2989 } 2990 2991 // Otherwise, scan the operands of Node to see if any of them is a call. 2992 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 2993 if (UI == E) return; 2994 for (--E; UI != E; ++UI) 2995 FindEarliestCallSeqEnd(*UI, Found, Visited); 2996 2997 // Tail recurse for the last iteration. 2998 FindEarliestCallSeqEnd(*UI, Found, Visited); 2999} 3000 3001/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 3002/// find the CALLSEQ_END node that terminates the call sequence. 3003static SDNode *FindCallSeqEnd(SDNode *Node) { 3004 if (Node->getOpcode() == ISD::CALLSEQ_END) 3005 return Node; 3006 if (Node->use_empty()) 3007 return 0; // No CallSeqEnd 3008 3009 SDOperand TheChain(Node, Node->getNumValues()-1); 3010 if (TheChain.getValueType() != MVT::Other) 3011 TheChain = SDOperand(Node, 0); 3012 if (TheChain.getValueType() != MVT::Other) 3013 return 0; 3014 3015 for (SDNode::use_iterator UI = Node->use_begin(), 3016 E = Node->use_end(); UI != E; ++UI) { 3017 3018 // Make sure to only follow users of our token chain. 3019 SDNode *User = *UI; 3020 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 3021 if (User->getOperand(i) == TheChain) 3022 if (SDNode *Result = FindCallSeqEnd(User)) 3023 return Result; 3024 } 3025 return 0; 3026} 3027 3028/// FindCallSeqStart - Given a chained node that is part of a call sequence, 3029/// find the CALLSEQ_START node that initiates the call sequence. 3030static SDNode *FindCallSeqStart(SDNode *Node) { 3031 assert(Node && "Didn't find callseq_start for a call??"); 3032 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 3033 3034 assert(Node->getOperand(0).getValueType() == MVT::Other && 3035 "Node doesn't have a token chain argument!"); 3036 return FindCallSeqStart(Node->getOperand(0).Val); 3037} 3038 3039 3040/// FindInputOutputChains - If we are replacing an operation with a call we need 3041/// to find the call that occurs before and the call that occurs after it to 3042/// properly serialize the calls in the block. The returned operand is the 3043/// input chain value for the new call (e.g. the entry node or the previous 3044/// call), and OutChain is set to be the chain node to update to point to the 3045/// end of the call chain. 3046static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 3047 SDOperand Entry) { 3048 SDNode *LatestCallSeqStart = Entry.Val; 3049 SDNode *LatestCallSeqEnd = 0; 3050 FindLatestCallSeqStart(OpNode, LatestCallSeqStart); 3051 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 3052 3053 // It is possible that no ISD::CALLSEQ_START was found because there is no 3054 // previous call in the function. LatestCallStackDown may in that case be 3055 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 3056 // unless LatestCallStackDown is an CALLSEQ_START. 3057 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 3058 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 3059 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 3060 } else { 3061 LatestCallSeqEnd = Entry.Val; 3062 } 3063 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 3064 3065 // Finally, find the first call that this must come before, first we find the 3066 // CallSeqEnd that ends the call. 3067 OutChain = 0; 3068 std::set<SDNode*> Visited; 3069 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 3070 3071 // If we found one, translate from the adj up to the callseq_start. 3072 if (OutChain) 3073 OutChain = FindCallSeqStart(OutChain); 3074 3075 return SDOperand(LatestCallSeqEnd, 0); 3076} 3077 3078/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 3079void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 3080 SDNode *OutChain) { 3081 // Nothing to splice it into? 3082 if (OutChain == 0) return; 3083 3084 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 3085 //OutChain->dump(); 3086 3087 // Form a token factor node merging the old inval and the new inval. 3088 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 3089 OutChain->getOperand(0)); 3090 // Change the node to refer to the new token. 3091 OutChain->setAdjCallChain(InToken); 3092} 3093 3094 3095// ExpandLibCall - Expand a node into a call to a libcall. If the result value 3096// does not fit into a register, return the lo part and set the hi part to the 3097// by-reg argument. If it does fit into a single register, return the result 3098// and leave the Hi part unset. 3099SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 3100 SDOperand &Hi) { 3101 SDNode *OutChain; 3102 SDOperand InChain = FindInputOutputChains(Node, OutChain, 3103 DAG.getEntryNode()); 3104 if (InChain.Val == 0) 3105 InChain = DAG.getEntryNode(); 3106 3107 TargetLowering::ArgListTy Args; 3108 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3109 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 3110 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 3111 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 3112 } 3113 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 3114 3115 // Splice the libcall in wherever FindInputOutputChains tells us to. 3116 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 3117 std::pair<SDOperand,SDOperand> CallInfo = 3118 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 3119 Callee, Args, DAG); 3120 3121 SDOperand Result; 3122 switch (getTypeAction(CallInfo.first.getValueType())) { 3123 default: assert(0 && "Unknown thing"); 3124 case Legal: 3125 Result = CallInfo.first; 3126 break; 3127 case Promote: 3128 assert(0 && "Cannot promote this yet!"); 3129 case Expand: 3130 ExpandOp(CallInfo.first, Result, Hi); 3131 CallInfo.second = LegalizeOp(CallInfo.second); 3132 break; 3133 } 3134 3135 SpliceCallInto(CallInfo.second, OutChain); 3136 NeedsAnotherIteration = true; 3137 return Result; 3138} 3139 3140 3141/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 3142/// destination type is legal. 3143SDOperand SelectionDAGLegalize:: 3144ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 3145 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 3146 assert(getTypeAction(Source.getValueType()) == Expand && 3147 "This is not an expansion!"); 3148 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 3149 3150 if (!isSigned) { 3151 assert(Source.getValueType() == MVT::i64 && 3152 "This only works for 64-bit -> FP"); 3153 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 3154 // incoming integer is set. To handle this, we dynamically test to see if 3155 // it is set, and, if so, add a fudge factor. 3156 SDOperand Lo, Hi; 3157 ExpandOp(Source, Lo, Hi); 3158 3159 // If this is unsigned, and not supported, first perform the conversion to 3160 // signed, then adjust the result if the sign bit is set. 3161 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 3162 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 3163 3164 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 3165 DAG.getConstant(0, Hi.getValueType()), 3166 ISD::SETLT); 3167 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3168 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3169 SignSet, Four, Zero); 3170 uint64_t FF = 0x5f800000ULL; 3171 if (TLI.isLittleEndian()) FF <<= 32; 3172 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3173 3174 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3175 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3176 SDOperand FudgeInReg; 3177 if (DestTy == MVT::f32) 3178 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3179 DAG.getSrcValue(NULL)); 3180 else { 3181 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3182 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3183 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 3184 } 3185 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3186 } 3187 3188 // Check to see if the target has a custom way to lower this. If so, use it. 3189 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3190 default: assert(0 && "This action not implemented for this operation!"); 3191 case TargetLowering::Legal: 3192 case TargetLowering::Expand: 3193 break; // This case is handled below. 3194 case TargetLowering::Custom: { 3195 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3196 Source), DAG); 3197 if (NV.Val) 3198 return LegalizeOp(NV); 3199 break; // The target decided this was legal after all 3200 } 3201 } 3202 3203 // Expand the source, then glue it back together for the call. We must expand 3204 // the source in case it is shared (this pass of legalize must traverse it). 3205 SDOperand SrcLo, SrcHi; 3206 ExpandOp(Source, SrcLo, SrcHi); 3207 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3208 3209 SDNode *OutChain = 0; 3210 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 3211 DAG.getEntryNode()); 3212 const char *FnName = 0; 3213 if (DestTy == MVT::f32) 3214 FnName = "__floatdisf"; 3215 else { 3216 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3217 FnName = "__floatdidf"; 3218 } 3219 3220 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 3221 3222 TargetLowering::ArgListTy Args; 3223 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 3224 3225 Args.push_back(std::make_pair(Source, ArgTy)); 3226 3227 // We don't care about token chains for libcalls. We just use the entry 3228 // node as our input and ignore the output chain. This allows us to place 3229 // calls wherever we need them to satisfy data dependences. 3230 const Type *RetTy = MVT::getTypeForValueType(DestTy); 3231 3232 std::pair<SDOperand,SDOperand> CallResult = 3233 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 3234 Callee, Args, DAG); 3235 3236 SpliceCallInto(CallResult.second, OutChain); 3237 return CallResult.first; 3238} 3239 3240 3241 3242/// ExpandOp - Expand the specified SDOperand into its two component pieces 3243/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 3244/// LegalizeNodes map is filled in for any results that are not expanded, the 3245/// ExpandedNodes map is filled in for any results that are expanded, and the 3246/// Lo/Hi values are returned. 3247void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 3248 MVT::ValueType VT = Op.getValueType(); 3249 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3250 SDNode *Node = Op.Val; 3251 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 3252 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 3253 "Cannot expand FP values!"); 3254 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 3255 "Cannot expand to FP value or to larger int value!"); 3256 3257 // See if we already expanded it. 3258 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 3259 = ExpandedNodes.find(Op); 3260 if (I != ExpandedNodes.end()) { 3261 Lo = I->second.first; 3262 Hi = I->second.second; 3263 return; 3264 } 3265 3266 // Expanding to multiple registers needs to perform an optimization step, and 3267 // is not careful to avoid operations the target does not support. Make sure 3268 // that all generated operations are legalized in the next iteration. 3269 NeedsAnotherIteration = true; 3270 3271 switch (Node->getOpcode()) { 3272 case ISD::CopyFromReg: 3273 assert(0 && "CopyFromReg must be legal!"); 3274 default: 3275 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 3276 assert(0 && "Do not know how to expand this operator!"); 3277 abort(); 3278 case ISD::UNDEF: 3279 Lo = DAG.getNode(ISD::UNDEF, NVT); 3280 Hi = DAG.getNode(ISD::UNDEF, NVT); 3281 break; 3282 case ISD::Constant: { 3283 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 3284 Lo = DAG.getConstant(Cst, NVT); 3285 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3286 break; 3287 } 3288 case ISD::ConstantVec: { 3289 unsigned NumElements = Node->getNumOperands(); 3290 // If we only have two elements left in the constant vector, just break it 3291 // apart into the two scalar constants it contains. Otherwise, bisect the 3292 // ConstantVec, and return each half as a new ConstantVec. 3293 // FIXME: this is hard coded as big endian, it may have to change to support 3294 // SSE and Alpha MVI 3295 if (NumElements == 2) { 3296 Hi = Node->getOperand(0); 3297 Lo = Node->getOperand(1); 3298 } else { 3299 NumElements /= 2; 3300 std::vector<SDOperand> LoOps, HiOps; 3301 for (unsigned I = 0, E = NumElements; I < E; ++I) { 3302 HiOps.push_back(Node->getOperand(I)); 3303 LoOps.push_back(Node->getOperand(I+NumElements)); 3304 } 3305 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps); 3306 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps); 3307 } 3308 break; 3309 } 3310 3311 case ISD::BUILD_PAIR: 3312 // Legalize both operands. FIXME: in the future we should handle the case 3313 // where the two elements are not legal. 3314 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 3315 Lo = LegalizeOp(Node->getOperand(0)); 3316 Hi = LegalizeOp(Node->getOperand(1)); 3317 break; 3318 3319 case ISD::SIGN_EXTEND_INREG: 3320 ExpandOp(Node->getOperand(0), Lo, Hi); 3321 // Sign extend the lo-part. 3322 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 3323 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 3324 TLI.getShiftAmountTy())); 3325 // sext_inreg the low part if needed. 3326 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 3327 break; 3328 3329 case ISD::CTPOP: 3330 ExpandOp(Node->getOperand(0), Lo, Hi); 3331 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3332 DAG.getNode(ISD::CTPOP, NVT, Lo), 3333 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3334 Hi = DAG.getConstant(0, NVT); 3335 break; 3336 3337 case ISD::CTLZ: { 3338 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3339 ExpandOp(Node->getOperand(0), Lo, Hi); 3340 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3341 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3342 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3343 ISD::SETNE); 3344 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3345 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3346 3347 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3348 Hi = DAG.getConstant(0, NVT); 3349 break; 3350 } 3351 3352 case ISD::CTTZ: { 3353 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3354 ExpandOp(Node->getOperand(0), Lo, Hi); 3355 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3356 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3357 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3358 ISD::SETNE); 3359 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3360 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3361 3362 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3363 Hi = DAG.getConstant(0, NVT); 3364 break; 3365 } 3366 3367 case ISD::LOAD: { 3368 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3369 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3370 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3371 3372 // Increment the pointer to the other half. 3373 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3374 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3375 getIntPtrConstant(IncrementSize)); 3376 //Is this safe? declaring that the two parts of the split load 3377 //are from the same instruction? 3378 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3379 3380 // Build a factor node to remember that this load is independent of the 3381 // other one. 3382 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3383 Hi.getValue(1)); 3384 3385 // Remember that we legalized the chain. 3386 AddLegalizedOperand(Op.getValue(1), TF); 3387 if (!TLI.isLittleEndian()) 3388 std::swap(Lo, Hi); 3389 break; 3390 } 3391 case ISD::VLOAD: { 3392 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3393 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3394 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3395 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3396 3397 // If we only have two elements, turn into a pair of scalar loads. 3398 // FIXME: handle case where a vector of two elements is fine, such as 3399 // 2 x double on SSE2. 3400 if (NumElements == 2) { 3401 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3402 // Increment the pointer to the other half. 3403 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8; 3404 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3405 getIntPtrConstant(IncrementSize)); 3406 //Is this safe? declaring that the two parts of the split load 3407 //are from the same instruction? 3408 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3409 } else { 3410 NumElements /= 2; // Split the vector in half 3411 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3412 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8; 3413 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3414 getIntPtrConstant(IncrementSize)); 3415 //Is this safe? declaring that the two parts of the split load 3416 //are from the same instruction? 3417 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3418 } 3419 3420 // Build a factor node to remember that this load is independent of the 3421 // other one. 3422 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3423 Hi.getValue(1)); 3424 3425 // Remember that we legalized the chain. 3426 AddLegalizedOperand(Op.getValue(1), TF); 3427 if (!TLI.isLittleEndian()) 3428 std::swap(Lo, Hi); 3429 break; 3430 } 3431 case ISD::VADD: 3432 case ISD::VSUB: 3433 case ISD::VMUL: { 3434 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3435 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3436 SDOperand LL, LH, RL, RH; 3437 3438 ExpandOp(Node->getOperand(0), LL, LH); 3439 ExpandOp(Node->getOperand(1), RL, RH); 3440 3441 // If we only have two elements, turn into a pair of scalar loads. 3442 // FIXME: handle case where a vector of two elements is fine, such as 3443 // 2 x double on SSE2. 3444 if (NumElements == 2) { 3445 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT); 3446 Lo = DAG.getNode(Opc, EVT, LL, RL); 3447 Hi = DAG.getNode(Opc, EVT, LH, RH); 3448 } else { 3449 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2), 3450 LL.getOperand(3)); 3451 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2), 3452 LH.getOperand(3)); 3453 } 3454 break; 3455 } 3456 case ISD::TAILCALL: 3457 case ISD::CALL: { 3458 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3459 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 3460 3461 bool Changed = false; 3462 std::vector<SDOperand> Ops; 3463 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 3464 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3465 Changed |= Ops.back() != Node->getOperand(i); 3466 } 3467 3468 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 3469 "Can only expand a call once so far, not i64 -> i16!"); 3470 3471 std::vector<MVT::ValueType> RetTyVTs; 3472 RetTyVTs.reserve(3); 3473 RetTyVTs.push_back(NVT); 3474 RetTyVTs.push_back(NVT); 3475 RetTyVTs.push_back(MVT::Other); 3476 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops, 3477 Node->getOpcode() == ISD::TAILCALL); 3478 Lo = SDOperand(NC, 0); 3479 Hi = SDOperand(NC, 1); 3480 3481 // Insert the new chain mapping. 3482 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 3483 break; 3484 } 3485 case ISD::AND: 3486 case ISD::OR: 3487 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 3488 SDOperand LL, LH, RL, RH; 3489 ExpandOp(Node->getOperand(0), LL, LH); 3490 ExpandOp(Node->getOperand(1), RL, RH); 3491 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 3492 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 3493 break; 3494 } 3495 case ISD::SELECT: { 3496 SDOperand C, LL, LH, RL, RH; 3497 3498 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3499 case Expand: assert(0 && "It's impossible to expand bools"); 3500 case Legal: 3501 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 3502 break; 3503 case Promote: 3504 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 3505 break; 3506 } 3507 ExpandOp(Node->getOperand(1), LL, LH); 3508 ExpandOp(Node->getOperand(2), RL, RH); 3509 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 3510 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 3511 break; 3512 } 3513 case ISD::SELECT_CC: { 3514 SDOperand TL, TH, FL, FH; 3515 ExpandOp(Node->getOperand(2), TL, TH); 3516 ExpandOp(Node->getOperand(3), FL, FH); 3517 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3518 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3519 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3520 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3521 Lo = LegalizeOp(Lo); 3522 Hi = LegalizeOp(Hi); 3523 break; 3524 } 3525 case ISD::SEXTLOAD: { 3526 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3527 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3528 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3529 3530 if (EVT == NVT) 3531 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3532 else 3533 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3534 EVT); 3535 3536 // Remember that we legalized the chain. 3537 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3538 3539 // The high part is obtained by SRA'ing all but one of the bits of the lo 3540 // part. 3541 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3542 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3543 TLI.getShiftAmountTy())); 3544 Lo = LegalizeOp(Lo); 3545 Hi = LegalizeOp(Hi); 3546 break; 3547 } 3548 case ISD::ZEXTLOAD: { 3549 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3550 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3551 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3552 3553 if (EVT == NVT) 3554 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3555 else 3556 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3557 EVT); 3558 3559 // Remember that we legalized the chain. 3560 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3561 3562 // The high part is just a zero. 3563 Hi = LegalizeOp(DAG.getConstant(0, NVT)); 3564 Lo = LegalizeOp(Lo); 3565 break; 3566 } 3567 case ISD::EXTLOAD: { 3568 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3569 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3570 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3571 3572 if (EVT == NVT) 3573 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3574 else 3575 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3576 EVT); 3577 3578 // Remember that we legalized the chain. 3579 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3580 3581 // The high part is undefined. 3582 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT)); 3583 Lo = LegalizeOp(Lo); 3584 break; 3585 } 3586 case ISD::ANY_EXTEND: { 3587 SDOperand In; 3588 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3589 case Expand: assert(0 && "expand-expand not implemented yet!"); 3590 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3591 case Promote: 3592 In = PromoteOp(Node->getOperand(0)); 3593 break; 3594 } 3595 3596 // The low part is any extension of the input (which degenerates to a copy). 3597 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In); 3598 // The high part is undefined. 3599 Hi = DAG.getNode(ISD::UNDEF, NVT); 3600 break; 3601 } 3602 case ISD::SIGN_EXTEND: { 3603 SDOperand In; 3604 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3605 case Expand: assert(0 && "expand-expand not implemented yet!"); 3606 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3607 case Promote: 3608 In = PromoteOp(Node->getOperand(0)); 3609 // Emit the appropriate sign_extend_inreg to get the value we want. 3610 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 3611 DAG.getValueType(Node->getOperand(0).getValueType())); 3612 break; 3613 } 3614 3615 // The low part is just a sign extension of the input (which degenerates to 3616 // a copy). 3617 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 3618 3619 // The high part is obtained by SRA'ing all but one of the bits of the lo 3620 // part. 3621 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3622 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3623 TLI.getShiftAmountTy())); 3624 break; 3625 } 3626 case ISD::ZERO_EXTEND: { 3627 SDOperand In; 3628 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3629 case Expand: assert(0 && "expand-expand not implemented yet!"); 3630 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3631 case Promote: 3632 In = PromoteOp(Node->getOperand(0)); 3633 // Emit the appropriate zero_extend_inreg to get the value we want. 3634 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 3635 break; 3636 } 3637 3638 // The low part is just a zero extension of the input (which degenerates to 3639 // a copy). 3640 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 3641 3642 // The high part is just a zero. 3643 Hi = DAG.getConstant(0, NVT); 3644 break; 3645 } 3646 3647 case ISD::READCYCLECOUNTER: { 3648 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 3649 TargetLowering::Custom && 3650 "Must custom expand ReadCycleCounter"); 3651 SDOperand T = TLI.LowerOperation(Op, DAG); 3652 assert(T.Val && "Node must be custom expanded!"); 3653 Lo = LegalizeOp(T.getValue(0)); 3654 Hi = LegalizeOp(T.getValue(1)); 3655 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 3656 LegalizeOp(T.getValue(2))); 3657 break; 3658 } 3659 3660 // These operators cannot be expanded directly, emit them as calls to 3661 // library functions. 3662 case ISD::FP_TO_SINT: 3663 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 3664 SDOperand Op; 3665 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3666 case Expand: assert(0 && "cannot expand FP!"); 3667 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3668 case Promote: Op = PromoteOp(Node->getOperand(0)); break; 3669 } 3670 3671 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 3672 3673 // Now that the custom expander is done, expand the result, which is still 3674 // VT. 3675 if (Op.Val) { 3676 ExpandOp(Op, Lo, Hi); 3677 break; 3678 } 3679 } 3680 3681 if (Node->getOperand(0).getValueType() == MVT::f32) 3682 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 3683 else 3684 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 3685 break; 3686 3687 case ISD::FP_TO_UINT: 3688 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 3689 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, 3690 LegalizeOp(Node->getOperand(0))); 3691 // Now that the custom expander is done, expand the result, which is still 3692 // VT. 3693 Op = TLI.LowerOperation(Op, DAG); 3694 if (Op.Val) { 3695 ExpandOp(Op, Lo, Hi); 3696 break; 3697 } 3698 } 3699 3700 if (Node->getOperand(0).getValueType() == MVT::f32) 3701 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 3702 else 3703 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 3704 break; 3705 3706 case ISD::SHL: 3707 // If the target wants custom lowering, do so. 3708 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 3709 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), 3710 LegalizeOp(Node->getOperand(1))); 3711 Op = TLI.LowerOperation(Op, DAG); 3712 if (Op.Val) { 3713 // Now that the custom expander is done, expand the result, which is 3714 // still VT. 3715 ExpandOp(Op, Lo, Hi); 3716 break; 3717 } 3718 } 3719 3720 // If we can emit an efficient shift operation, do so now. 3721 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3722 break; 3723 3724 // If this target supports SHL_PARTS, use it. 3725 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) { 3726 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 3727 Lo, Hi); 3728 break; 3729 } 3730 3731 // Otherwise, emit a libcall. 3732 Lo = ExpandLibCall("__ashldi3", Node, Hi); 3733 break; 3734 3735 case ISD::SRA: 3736 // If the target wants custom lowering, do so. 3737 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 3738 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), 3739 LegalizeOp(Node->getOperand(1))); 3740 Op = TLI.LowerOperation(Op, DAG); 3741 if (Op.Val) { 3742 // Now that the custom expander is done, expand the result, which is 3743 // still VT. 3744 ExpandOp(Op, Lo, Hi); 3745 break; 3746 } 3747 } 3748 3749 // If we can emit an efficient shift operation, do so now. 3750 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3751 break; 3752 3753 // If this target supports SRA_PARTS, use it. 3754 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) { 3755 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 3756 Lo, Hi); 3757 break; 3758 } 3759 3760 // Otherwise, emit a libcall. 3761 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 3762 break; 3763 case ISD::SRL: 3764 // If the target wants custom lowering, do so. 3765 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 3766 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), 3767 LegalizeOp(Node->getOperand(1))); 3768 Op = TLI.LowerOperation(Op, DAG); 3769 if (Op.Val) { 3770 // Now that the custom expander is done, expand the result, which is 3771 // still VT. 3772 ExpandOp(Op, Lo, Hi); 3773 break; 3774 } 3775 } 3776 3777 // If we can emit an efficient shift operation, do so now. 3778 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3779 break; 3780 3781 // If this target supports SRL_PARTS, use it. 3782 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) { 3783 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 3784 Lo, Hi); 3785 break; 3786 } 3787 3788 // Otherwise, emit a libcall. 3789 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 3790 break; 3791 3792 case ISD::ADD: 3793 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 3794 Lo, Hi); 3795 break; 3796 case ISD::SUB: 3797 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 3798 Lo, Hi); 3799 break; 3800 case ISD::MUL: { 3801 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 3802 SDOperand LL, LH, RL, RH; 3803 ExpandOp(Node->getOperand(0), LL, LH); 3804 ExpandOp(Node->getOperand(1), RL, RH); 3805 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 3806 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 3807 // extended the sign bit of the low half through the upper half, and if so 3808 // emit a MULHS instead of the alternate sequence that is valid for any 3809 // i64 x i64 multiply. 3810 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 3811 // is RH an extension of the sign bit of RL? 3812 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 3813 RH.getOperand(1).getOpcode() == ISD::Constant && 3814 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 3815 // is LH an extension of the sign bit of LL? 3816 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 3817 LH.getOperand(1).getOpcode() == ISD::Constant && 3818 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 3819 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 3820 } else { 3821 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 3822 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 3823 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 3824 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 3825 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 3826 } 3827 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 3828 } else { 3829 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 3830 } 3831 break; 3832 } 3833 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 3834 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 3835 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 3836 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 3837 } 3838 3839 // Remember in a map if the values will be reused later. 3840 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 3841 std::make_pair(Lo, Hi))).second; 3842 assert(isNew && "Value already expanded?!?"); 3843 3844 // Make sure the resultant values have been legalized themselves, unless this 3845 // is a type that requires multi-step expansion. 3846 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 3847 Lo = LegalizeOp(Lo); 3848 Hi = LegalizeOp(Hi); 3849 } 3850} 3851 3852 3853// SelectionDAG::Legalize - This is the entry point for the file. 3854// 3855void SelectionDAG::Legalize() { 3856 /// run - This is the main entry point to this class. 3857 /// 3858 SelectionDAGLegalize(*this).Run(); 3859} 3860 3861