LegalizeDAG.cpp revision ec57fd91af6be26a29535e7dd3dcb63beb71d898
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Target/TargetLowering.h" 18#include "llvm/Target/TargetData.h" 19#include "llvm/Target/TargetOptions.h" 20#include "llvm/CallingConv.h" 21#include "llvm/Constants.h" 22#include "llvm/Support/MathExtras.h" 23#include "llvm/Support/CommandLine.h" 24#include <iostream> 25#include <map> 26using namespace llvm; 27 28#ifndef NDEBUG 29static cl::opt<bool> 30ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 31 cl::desc("Pop up a window to show dags before legalize")); 32#else 33static const bool ViewLegalizeDAGs = 0; 34#endif 35 36//===----------------------------------------------------------------------===// 37/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 38/// hacks on it until the target machine can handle it. This involves 39/// eliminating value sizes the machine cannot handle (promoting small sizes to 40/// large sizes or splitting up large values into small values) as well as 41/// eliminating operations the machine cannot handle. 42/// 43/// This code also does a small amount of optimization and recognition of idioms 44/// as part of its processing. For example, if a target does not support a 45/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 46/// will attempt merge setcc and brc instructions into brcc's. 47/// 48namespace { 49class SelectionDAGLegalize { 50 TargetLowering &TLI; 51 SelectionDAG &DAG; 52 53 // Libcall insertion helpers. 54 55 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 56 /// legalized. We use this to ensure that calls are properly serialized 57 /// against each other, including inserted libcalls. 58 SDOperand LastCALLSEQ_END; 59 60 /// IsLegalizingCall - This member is used *only* for purposes of providing 61 /// helpful assertions that a libcall isn't created while another call is 62 /// being legalized (which could lead to non-serialized call sequences). 63 bool IsLegalizingCall; 64 65 enum LegalizeAction { 66 Legal, // The target natively supports this operation. 67 Promote, // This operation should be executed in a larger type. 68 Expand, // Try to expand this to other ops, otherwise use a libcall. 69 }; 70 71 /// ValueTypeActions - This is a bitvector that contains two bits for each 72 /// value type, where the two bits correspond to the LegalizeAction enum. 73 /// This can be queried with "getTypeAction(VT)". 74 TargetLowering::ValueTypeActionImpl ValueTypeActions; 75 76 /// LegalizedNodes - For nodes that are of legal width, and that have more 77 /// than one use, this map indicates what regularized operand to use. This 78 /// allows us to avoid legalizing the same thing more than once. 79 std::map<SDOperand, SDOperand> LegalizedNodes; 80 81 /// PromotedNodes - For nodes that are below legal width, and that have more 82 /// than one use, this map indicates what promoted value to use. This allows 83 /// us to avoid promoting the same thing more than once. 84 std::map<SDOperand, SDOperand> PromotedNodes; 85 86 /// ExpandedNodes - For nodes that need to be expanded this map indicates 87 /// which which operands are the expanded version of the input. This allows 88 /// us to avoid expanding the same node more than once. 89 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 90 91 /// SplitNodes - For vector nodes that need to be split, this map indicates 92 /// which which operands are the split version of the input. This allows us 93 /// to avoid splitting the same node more than once. 94 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 95 96 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to 97 /// concrete packed types, this contains the mapping of ones we have already 98 /// processed to the result. 99 std::map<SDOperand, SDOperand> PackedNodes; 100 101 void AddLegalizedOperand(SDOperand From, SDOperand To) { 102 LegalizedNodes.insert(std::make_pair(From, To)); 103 // If someone requests legalization of the new node, return itself. 104 if (From != To) 105 LegalizedNodes.insert(std::make_pair(To, To)); 106 } 107 void AddPromotedOperand(SDOperand From, SDOperand To) { 108 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 109 assert(isNew && "Got into the map somehow?"); 110 // If someone requests legalization of the new node, return itself. 111 LegalizedNodes.insert(std::make_pair(To, To)); 112 } 113 114public: 115 116 SelectionDAGLegalize(SelectionDAG &DAG); 117 118 /// getTypeAction - Return how we should legalize values of this type, either 119 /// it is already legal or we need to expand it into multiple registers of 120 /// smaller integer type, or we need to promote it to a larger type. 121 LegalizeAction getTypeAction(MVT::ValueType VT) const { 122 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 123 } 124 125 /// isTypeLegal - Return true if this type is legal on this target. 126 /// 127 bool isTypeLegal(MVT::ValueType VT) const { 128 return getTypeAction(VT) == Legal; 129 } 130 131 void LegalizeDAG(); 132 133private: 134 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 135 /// appropriate for its type. 136 void HandleOp(SDOperand Op); 137 138 /// LegalizeOp - We know that the specified value has a legal type. 139 /// Recursively ensure that the operands have legal types, then return the 140 /// result. 141 SDOperand LegalizeOp(SDOperand O); 142 143 /// PromoteOp - Given an operation that produces a value in an invalid type, 144 /// promote it to compute the value into a larger type. The produced value 145 /// will have the correct bits for the low portion of the register, but no 146 /// guarantee is made about the top bits: it may be zero, sign-extended, or 147 /// garbage. 148 SDOperand PromoteOp(SDOperand O); 149 150 /// ExpandOp - Expand the specified SDOperand into its two component pieces 151 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 152 /// the LegalizeNodes map is filled in for any results that are not expanded, 153 /// the ExpandedNodes map is filled in for any results that are expanded, and 154 /// the Lo/Hi values are returned. This applies to integer types and Vector 155 /// types. 156 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 157 158 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 159 /// two smaller values of MVT::Vector type. 160 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 161 162 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 163 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When 164 /// this is called, we know that PackedVT is the right type for the result and 165 /// we know that this type is legal for the target. 166 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT); 167 168 /// isShuffleLegal - Return true if a vector shuffle is legal with the 169 /// specified mask and type. Targets can specify exactly which masks they 170 /// support and the code generator is tasked with not creating illegal masks. 171 /// 172 /// Note that this will also return true for shuffles that are promoted to a 173 /// different type. 174 /// 175 /// If this is a legal shuffle, this method returns the (possibly promoted) 176 /// build_vector Mask. If it's not a legal shuffle, it returns null. 177 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 178 179 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest); 180 181 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 182 183 SDOperand CreateStackTemporary(MVT::ValueType VT); 184 185 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 186 SDOperand &Hi); 187 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 188 SDOperand Source); 189 190 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 191 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 192 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 193 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 194 SDOperand LegalOp, 195 MVT::ValueType DestVT); 196 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 197 bool isSigned); 198 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 199 bool isSigned); 200 201 SDOperand ExpandBSWAP(SDOperand Op); 202 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 203 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 204 SDOperand &Lo, SDOperand &Hi); 205 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 206 SDOperand &Lo, SDOperand &Hi); 207 208 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op); 209 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 210 211 SDOperand getIntPtrConstant(uint64_t Val) { 212 return DAG.getConstant(Val, TLI.getPointerTy()); 213 } 214}; 215} 216 217/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 218/// specified mask and type. Targets can specify exactly which masks they 219/// support and the code generator is tasked with not creating illegal masks. 220/// 221/// Note that this will also return true for shuffles that are promoted to a 222/// different type. 223SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 224 SDOperand Mask) const { 225 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 226 default: return 0; 227 case TargetLowering::Legal: 228 case TargetLowering::Custom: 229 break; 230 case TargetLowering::Promote: { 231 // If this is promoted to a different type, convert the shuffle mask and 232 // ask if it is legal in the promoted type! 233 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 234 235 // If we changed # elements, change the shuffle mask. 236 unsigned NumEltsGrowth = 237 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 238 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 239 if (NumEltsGrowth > 1) { 240 // Renumber the elements. 241 std::vector<SDOperand> Ops; 242 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 243 SDOperand InOp = Mask.getOperand(i); 244 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 245 if (InOp.getOpcode() == ISD::UNDEF) 246 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 247 else { 248 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 249 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 250 } 251 } 252 } 253 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, Ops); 254 } 255 VT = NVT; 256 break; 257 } 258 } 259 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 260} 261 262/// getScalarizedOpcode - Return the scalar opcode that corresponds to the 263/// specified vector opcode. 264static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 265 switch (VecOp) { 266 default: assert(0 && "Don't know how to scalarize this opcode!"); 267 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 268 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 269 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 270 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV; 271 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV; 272 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0; 273 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0; 274 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0; 275 } 276} 277 278SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 279 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 280 ValueTypeActions(TLI.getValueTypeActions()) { 281 assert(MVT::LAST_VALUETYPE <= 32 && 282 "Too many value types for ValueTypeActions to hold!"); 283} 284 285/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 286/// not been visited yet and if all of its operands have already been visited. 287static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 288 std::map<SDNode*, unsigned> &Visited) { 289 if (++Visited[N] != N->getNumOperands()) 290 return; // Haven't visited all operands yet 291 292 Order.push_back(N); 293 294 if (N->hasOneUse()) { // Tail recurse in common case. 295 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 296 return; 297 } 298 299 // Now that we have N in, add anything that uses it if all of their operands 300 // are now done. 301 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 302 ComputeTopDownOrdering(*UI, Order, Visited); 303} 304 305 306void SelectionDAGLegalize::LegalizeDAG() { 307 LastCALLSEQ_END = DAG.getEntryNode(); 308 IsLegalizingCall = false; 309 310 // The legalize process is inherently a bottom-up recursive process (users 311 // legalize their uses before themselves). Given infinite stack space, we 312 // could just start legalizing on the root and traverse the whole graph. In 313 // practice however, this causes us to run out of stack space on large basic 314 // blocks. To avoid this problem, compute an ordering of the nodes where each 315 // node is only legalized after all of its operands are legalized. 316 std::map<SDNode*, unsigned> Visited; 317 std::vector<SDNode*> Order; 318 319 // Compute ordering from all of the leaves in the graphs, those (like the 320 // entry node) that have no operands. 321 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 322 E = DAG.allnodes_end(); I != E; ++I) { 323 if (I->getNumOperands() == 0) { 324 Visited[I] = 0 - 1U; 325 ComputeTopDownOrdering(I, Order, Visited); 326 } 327 } 328 329 assert(Order.size() == Visited.size() && 330 Order.size() == 331 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 332 "Error: DAG is cyclic!"); 333 Visited.clear(); 334 335 for (unsigned i = 0, e = Order.size(); i != e; ++i) 336 HandleOp(SDOperand(Order[i], 0)); 337 338 // Finally, it's possible the root changed. Get the new root. 339 SDOperand OldRoot = DAG.getRoot(); 340 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 341 DAG.setRoot(LegalizedNodes[OldRoot]); 342 343 ExpandedNodes.clear(); 344 LegalizedNodes.clear(); 345 PromotedNodes.clear(); 346 SplitNodes.clear(); 347 PackedNodes.clear(); 348 349 // Remove dead nodes now. 350 DAG.RemoveDeadNodes(OldRoot.Val); 351} 352 353 354/// FindCallEndFromCallStart - Given a chained node that is part of a call 355/// sequence, find the CALLSEQ_END node that terminates the call sequence. 356static SDNode *FindCallEndFromCallStart(SDNode *Node) { 357 if (Node->getOpcode() == ISD::CALLSEQ_END) 358 return Node; 359 if (Node->use_empty()) 360 return 0; // No CallSeqEnd 361 362 // The chain is usually at the end. 363 SDOperand TheChain(Node, Node->getNumValues()-1); 364 if (TheChain.getValueType() != MVT::Other) { 365 // Sometimes it's at the beginning. 366 TheChain = SDOperand(Node, 0); 367 if (TheChain.getValueType() != MVT::Other) { 368 // Otherwise, hunt for it. 369 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 370 if (Node->getValueType(i) == MVT::Other) { 371 TheChain = SDOperand(Node, i); 372 break; 373 } 374 375 // Otherwise, we walked into a node without a chain. 376 if (TheChain.getValueType() != MVT::Other) 377 return 0; 378 } 379 } 380 381 for (SDNode::use_iterator UI = Node->use_begin(), 382 E = Node->use_end(); UI != E; ++UI) { 383 384 // Make sure to only follow users of our token chain. 385 SDNode *User = *UI; 386 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 387 if (User->getOperand(i) == TheChain) 388 if (SDNode *Result = FindCallEndFromCallStart(User)) 389 return Result; 390 } 391 return 0; 392} 393 394/// FindCallStartFromCallEnd - Given a chained node that is part of a call 395/// sequence, find the CALLSEQ_START node that initiates the call sequence. 396static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 397 assert(Node && "Didn't find callseq_start for a call??"); 398 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 399 400 assert(Node->getOperand(0).getValueType() == MVT::Other && 401 "Node doesn't have a token chain argument!"); 402 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 403} 404 405/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 406/// see if any uses can reach Dest. If no dest operands can get to dest, 407/// legalize them, legalize ourself, and return false, otherwise, return true. 408bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, 409 SDNode *Dest) { 410 if (N == Dest) return true; // N certainly leads to Dest :) 411 412 // If the first result of this node has been already legalized, then it cannot 413 // reach N. 414 switch (getTypeAction(N->getValueType(0))) { 415 case Legal: 416 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 417 break; 418 case Promote: 419 if (PromotedNodes.count(SDOperand(N, 0))) return false; 420 break; 421 case Expand: 422 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 423 break; 424 } 425 426 // Okay, this node has not already been legalized. Check and legalize all 427 // operands. If none lead to Dest, then we can legalize this node. 428 bool OperandsLeadToDest = false; 429 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 430 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 431 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest); 432 433 if (OperandsLeadToDest) return true; 434 435 // Okay, this node looks safe, legalize it and return false. 436 HandleOp(SDOperand(N, 0)); 437 return false; 438} 439 440/// HandleOp - Legalize, Promote, Expand or Pack the specified operand as 441/// appropriate for its type. 442void SelectionDAGLegalize::HandleOp(SDOperand Op) { 443 switch (getTypeAction(Op.getValueType())) { 444 default: assert(0 && "Bad type action!"); 445 case Legal: LegalizeOp(Op); break; 446 case Promote: PromoteOp(Op); break; 447 case Expand: 448 if (Op.getValueType() != MVT::Vector) { 449 SDOperand X, Y; 450 ExpandOp(Op, X, Y); 451 } else { 452 SDNode *N = Op.Val; 453 unsigned NumOps = N->getNumOperands(); 454 unsigned NumElements = 455 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue(); 456 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT(); 457 MVT::ValueType PackedVT = getVectorType(EVT, NumElements); 458 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) { 459 // In the common case, this is a legal vector type, convert it to the 460 // packed operation and type now. 461 PackVectorOp(Op, PackedVT); 462 } else if (NumElements == 1) { 463 // Otherwise, if this is a single element vector, convert it to a 464 // scalar operation. 465 PackVectorOp(Op, EVT); 466 } else { 467 // Otherwise, this is a multiple element vector that isn't supported. 468 // Split it in half and legalize both parts. 469 SDOperand X, Y; 470 SplitVectorOp(Op, X, Y); 471 } 472 } 473 break; 474 } 475} 476 477 478/// LegalizeOp - We know that the specified value has a legal type. 479/// Recursively ensure that the operands have legal types, then return the 480/// result. 481SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 482 assert(isTypeLegal(Op.getValueType()) && 483 "Caller should expand or promote operands that are not legal!"); 484 SDNode *Node = Op.Val; 485 486 // If this operation defines any values that cannot be represented in a 487 // register on this target, make sure to expand or promote them. 488 if (Node->getNumValues() > 1) { 489 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 490 if (getTypeAction(Node->getValueType(i)) != Legal) { 491 HandleOp(Op.getValue(i)); 492 assert(LegalizedNodes.count(Op) && 493 "Handling didn't add legal operands!"); 494 return LegalizedNodes[Op]; 495 } 496 } 497 498 // Note that LegalizeOp may be reentered even from single-use nodes, which 499 // means that we always must cache transformed nodes. 500 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 501 if (I != LegalizedNodes.end()) return I->second; 502 503 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 504 SDOperand Result = Op; 505 bool isCustom = false; 506 507 switch (Node->getOpcode()) { 508 case ISD::FrameIndex: 509 case ISD::EntryToken: 510 case ISD::Register: 511 case ISD::BasicBlock: 512 case ISD::TargetFrameIndex: 513 case ISD::TargetJumpTable: 514 case ISD::TargetConstant: 515 case ISD::TargetConstantFP: 516 case ISD::TargetConstantPool: 517 case ISD::TargetGlobalAddress: 518 case ISD::TargetExternalSymbol: 519 case ISD::VALUETYPE: 520 case ISD::SRCVALUE: 521 case ISD::STRING: 522 case ISD::CONDCODE: 523 // Primitives must all be legal. 524 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) && 525 "This must be legal!"); 526 break; 527 default: 528 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 529 // If this is a target node, legalize it by legalizing the operands then 530 // passing it through. 531 std::vector<SDOperand> Ops; 532 bool Changed = false; 533 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 534 Ops.push_back(LegalizeOp(Node->getOperand(i))); 535 Changed = Changed || Node->getOperand(i) != Ops.back(); 536 } 537 if (Changed) 538 if (Node->getNumValues() == 1) 539 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 540 else { 541 std::vector<MVT::ValueType> VTs(Node->value_begin(), 542 Node->value_end()); 543 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 544 } 545 546 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 547 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 548 return Result.getValue(Op.ResNo); 549 } 550 // Otherwise this is an unhandled builtin node. splat. 551 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 552 assert(0 && "Do not know how to legalize this operator!"); 553 abort(); 554 case ISD::GlobalAddress: 555 case ISD::ExternalSymbol: 556 case ISD::ConstantPool: 557 case ISD::JumpTable: // Nothing to do. 558 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 559 default: assert(0 && "This action is not supported yet!"); 560 case TargetLowering::Custom: 561 Tmp1 = TLI.LowerOperation(Op, DAG); 562 if (Tmp1.Val) Result = Tmp1; 563 // FALLTHROUGH if the target doesn't want to lower this op after all. 564 case TargetLowering::Legal: 565 break; 566 } 567 break; 568 case ISD::AssertSext: 569 case ISD::AssertZext: 570 Tmp1 = LegalizeOp(Node->getOperand(0)); 571 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 572 break; 573 case ISD::MERGE_VALUES: 574 // Legalize eliminates MERGE_VALUES nodes. 575 Result = Node->getOperand(Op.ResNo); 576 break; 577 case ISD::CopyFromReg: 578 Tmp1 = LegalizeOp(Node->getOperand(0)); 579 Result = Op.getValue(0); 580 if (Node->getNumValues() == 2) { 581 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 582 } else { 583 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 584 if (Node->getNumOperands() == 3) { 585 Tmp2 = LegalizeOp(Node->getOperand(2)); 586 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 587 } else { 588 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 589 } 590 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 591 } 592 // Since CopyFromReg produces two values, make sure to remember that we 593 // legalized both of them. 594 AddLegalizedOperand(Op.getValue(0), Result); 595 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 596 return Result.getValue(Op.ResNo); 597 case ISD::UNDEF: { 598 MVT::ValueType VT = Op.getValueType(); 599 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 600 default: assert(0 && "This action is not supported yet!"); 601 case TargetLowering::Expand: 602 if (MVT::isInteger(VT)) 603 Result = DAG.getConstant(0, VT); 604 else if (MVT::isFloatingPoint(VT)) 605 Result = DAG.getConstantFP(0, VT); 606 else 607 assert(0 && "Unknown value type!"); 608 break; 609 case TargetLowering::Legal: 610 break; 611 } 612 break; 613 } 614 615 case ISD::INTRINSIC_W_CHAIN: 616 case ISD::INTRINSIC_WO_CHAIN: 617 case ISD::INTRINSIC_VOID: { 618 std::vector<SDOperand> Ops; 619 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 620 Ops.push_back(LegalizeOp(Node->getOperand(i))); 621 Result = DAG.UpdateNodeOperands(Result, Ops); 622 623 // Allow the target to custom lower its intrinsics if it wants to. 624 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 625 TargetLowering::Custom) { 626 Tmp3 = TLI.LowerOperation(Result, DAG); 627 if (Tmp3.Val) Result = Tmp3; 628 } 629 630 if (Result.Val->getNumValues() == 1) break; 631 632 // Must have return value and chain result. 633 assert(Result.Val->getNumValues() == 2 && 634 "Cannot return more than two values!"); 635 636 // Since loads produce two values, make sure to remember that we 637 // legalized both of them. 638 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 639 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 640 return Result.getValue(Op.ResNo); 641 } 642 643 case ISD::LOCATION: 644 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 645 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 646 647 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 648 case TargetLowering::Promote: 649 default: assert(0 && "This action is not supported yet!"); 650 case TargetLowering::Expand: { 651 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo(); 652 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 653 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other); 654 655 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) { 656 const std::string &FName = 657 cast<StringSDNode>(Node->getOperand(3))->getValue(); 658 const std::string &DirName = 659 cast<StringSDNode>(Node->getOperand(4))->getValue(); 660 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName); 661 662 std::vector<SDOperand> Ops; 663 Ops.push_back(Tmp1); // chain 664 SDOperand LineOp = Node->getOperand(1); 665 SDOperand ColOp = Node->getOperand(2); 666 667 if (useDEBUG_LOC) { 668 Ops.push_back(LineOp); // line # 669 Ops.push_back(ColOp); // col # 670 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 671 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops); 672 } else { 673 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 674 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 675 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile); 676 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 677 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops); 678 } 679 } else { 680 Result = Tmp1; // chain 681 } 682 break; 683 } 684 case TargetLowering::Legal: 685 if (Tmp1 != Node->getOperand(0) || 686 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 687 std::vector<SDOperand> Ops; 688 Ops.push_back(Tmp1); 689 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 690 Ops.push_back(Node->getOperand(1)); // line # must be legal. 691 Ops.push_back(Node->getOperand(2)); // col # must be legal. 692 } else { 693 // Otherwise promote them. 694 Ops.push_back(PromoteOp(Node->getOperand(1))); 695 Ops.push_back(PromoteOp(Node->getOperand(2))); 696 } 697 Ops.push_back(Node->getOperand(3)); // filename must be legal. 698 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 699 Result = DAG.UpdateNodeOperands(Result, Ops); 700 } 701 break; 702 } 703 break; 704 705 case ISD::DEBUG_LOC: 706 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 707 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 708 default: assert(0 && "This action is not supported yet!"); 709 case TargetLowering::Legal: 710 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 711 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 712 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 713 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 714 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 715 break; 716 } 717 break; 718 719 case ISD::DEBUG_LABEL: 720 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!"); 721 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) { 722 default: assert(0 && "This action is not supported yet!"); 723 case TargetLowering::Legal: 724 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 725 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 726 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 727 break; 728 } 729 break; 730 731 case ISD::Constant: 732 // We know we don't need to expand constants here, constants only have one 733 // value and we check that it is fine above. 734 735 // FIXME: Maybe we should handle things like targets that don't support full 736 // 32-bit immediates? 737 break; 738 case ISD::ConstantFP: { 739 // Spill FP immediates to the constant pool if the target cannot directly 740 // codegen them. Targets often have some immediate values that can be 741 // efficiently generated into an FP register without a load. We explicitly 742 // leave these constants as ConstantFP nodes for the target to deal with. 743 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 744 745 // Check to see if this FP immediate is already legal. 746 bool isLegal = false; 747 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 748 E = TLI.legal_fpimm_end(); I != E; ++I) 749 if (CFP->isExactlyValue(*I)) { 750 isLegal = true; 751 break; 752 } 753 754 // If this is a legal constant, turn it into a TargetConstantFP node. 755 if (isLegal) { 756 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0)); 757 break; 758 } 759 760 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 761 default: assert(0 && "This action is not supported yet!"); 762 case TargetLowering::Custom: 763 Tmp3 = TLI.LowerOperation(Result, DAG); 764 if (Tmp3.Val) { 765 Result = Tmp3; 766 break; 767 } 768 // FALLTHROUGH 769 case TargetLowering::Expand: 770 // Otherwise we need to spill the constant to memory. 771 bool Extend = false; 772 773 // If a FP immediate is precise when represented as a float and if the 774 // target can do an extending load from float to double, we put it into 775 // the constant pool as a float, even if it's is statically typed as a 776 // double. 777 MVT::ValueType VT = CFP->getValueType(0); 778 bool isDouble = VT == MVT::f64; 779 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 780 Type::FloatTy, CFP->getValue()); 781 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 782 // Only do this if the target has a native EXTLOAD instruction from 783 // f32. 784 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 785 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 786 VT = MVT::f32; 787 Extend = true; 788 } 789 790 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 791 if (Extend) { 792 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 793 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 794 } else { 795 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 796 DAG.getSrcValue(NULL)); 797 } 798 } 799 break; 800 } 801 case ISD::TokenFactor: 802 if (Node->getNumOperands() == 2) { 803 Tmp1 = LegalizeOp(Node->getOperand(0)); 804 Tmp2 = LegalizeOp(Node->getOperand(1)); 805 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 806 } else if (Node->getNumOperands() == 3) { 807 Tmp1 = LegalizeOp(Node->getOperand(0)); 808 Tmp2 = LegalizeOp(Node->getOperand(1)); 809 Tmp3 = LegalizeOp(Node->getOperand(2)); 810 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 811 } else { 812 std::vector<SDOperand> Ops; 813 // Legalize the operands. 814 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 815 Ops.push_back(LegalizeOp(Node->getOperand(i))); 816 Result = DAG.UpdateNodeOperands(Result, Ops); 817 } 818 break; 819 820 case ISD::FORMAL_ARGUMENTS: 821 // The only option for this is to custom lower it. 822 Result = TLI.LowerOperation(Result, DAG); 823 assert(Result.Val && "Target didn't custom lower ISD::FORMAL_ARGUMENTS!"); 824 break; 825 826 case ISD::BUILD_VECTOR: 827 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 828 default: assert(0 && "This action is not supported yet!"); 829 case TargetLowering::Custom: 830 Tmp3 = TLI.LowerOperation(Result, DAG); 831 if (Tmp3.Val) { 832 Result = Tmp3; 833 break; 834 } 835 // FALLTHROUGH 836 case TargetLowering::Expand: 837 Result = ExpandBUILD_VECTOR(Result.Val); 838 break; 839 } 840 break; 841 case ISD::INSERT_VECTOR_ELT: 842 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 843 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 844 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 845 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 846 847 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 848 Node->getValueType(0))) { 849 default: assert(0 && "This action is not supported yet!"); 850 case TargetLowering::Legal: 851 break; 852 case TargetLowering::Custom: 853 Tmp3 = TLI.LowerOperation(Result, DAG); 854 if (Tmp3.Val) { 855 Result = Tmp3; 856 break; 857 } 858 // FALLTHROUGH 859 case TargetLowering::Expand: { 860 // If the insert index is a constant, codegen this as a scalar_to_vector, 861 // then a shuffle that inserts it into the right position in the vector. 862 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 863 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 864 Tmp1.getValueType(), Tmp2); 865 866 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 867 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 868 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT); 869 870 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 871 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 872 // the RHS. 873 std::vector<SDOperand> ShufOps; 874 for (unsigned i = 0; i != NumElts; ++i) { 875 if (i != InsertPos->getValue()) 876 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 877 else 878 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 879 } 880 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,ShufOps); 881 882 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 883 Tmp1, ScVec, ShufMask); 884 Result = LegalizeOp(Result); 885 break; 886 } 887 888 // If the target doesn't support this, we have to spill the input vector 889 // to a temporary stack slot, update the element, then reload it. This is 890 // badness. We could also load the value into a vector register (either 891 // with a "move to register" or "extload into register" instruction, then 892 // permute it into place, if the idx is a constant and if the idx is 893 // supported by the target. 894 MVT::ValueType VT = Tmp1.getValueType(); 895 MVT::ValueType EltVT = Tmp2.getValueType(); 896 MVT::ValueType IdxVT = Tmp3.getValueType(); 897 MVT::ValueType PtrVT = TLI.getPointerTy(); 898 SDOperand StackPtr = CreateStackTemporary(VT); 899 // Store the vector. 900 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 901 Tmp1, StackPtr, DAG.getSrcValue(NULL)); 902 903 // Truncate or zero extend offset to target pointer type. 904 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 905 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 906 // Add the offset to the index. 907 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 908 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 909 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 910 // Store the scalar value. 911 Ch = DAG.getNode(ISD::STORE, MVT::Other, Ch, 912 Tmp2, StackPtr2, DAG.getSrcValue(NULL)); 913 // Load the updated vector. 914 Result = DAG.getLoad(VT, Ch, StackPtr, DAG.getSrcValue(NULL)); 915 break; 916 } 917 } 918 break; 919 case ISD::SCALAR_TO_VECTOR: 920 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 921 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 922 break; 923 } 924 925 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 926 Result = DAG.UpdateNodeOperands(Result, Tmp1); 927 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 928 Node->getValueType(0))) { 929 default: assert(0 && "This action is not supported yet!"); 930 case TargetLowering::Legal: 931 break; 932 case TargetLowering::Custom: 933 Tmp3 = TLI.LowerOperation(Result, DAG); 934 if (Tmp3.Val) { 935 Result = Tmp3; 936 break; 937 } 938 // FALLTHROUGH 939 case TargetLowering::Expand: 940 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 941 break; 942 } 943 break; 944 case ISD::VECTOR_SHUFFLE: 945 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 946 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 947 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 948 949 // Allow targets to custom lower the SHUFFLEs they support. 950 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 951 default: assert(0 && "Unknown operation action!"); 952 case TargetLowering::Legal: 953 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 954 "vector shuffle should not be created if not legal!"); 955 break; 956 case TargetLowering::Custom: 957 Tmp3 = TLI.LowerOperation(Result, DAG); 958 if (Tmp3.Val) { 959 Result = Tmp3; 960 break; 961 } 962 // FALLTHROUGH 963 case TargetLowering::Expand: { 964 MVT::ValueType VT = Node->getValueType(0); 965 MVT::ValueType EltVT = MVT::getVectorBaseType(VT); 966 MVT::ValueType PtrVT = TLI.getPointerTy(); 967 SDOperand Mask = Node->getOperand(2); 968 unsigned NumElems = Mask.getNumOperands(); 969 std::vector<SDOperand> Ops; 970 for (unsigned i = 0; i != NumElems; ++i) { 971 SDOperand Arg = Mask.getOperand(i); 972 if (Arg.getOpcode() == ISD::UNDEF) { 973 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 974 } else { 975 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 976 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 977 if (Idx < NumElems) 978 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 979 DAG.getConstant(Idx, PtrVT))); 980 else 981 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 982 DAG.getConstant(Idx - NumElems, PtrVT))); 983 } 984 } 985 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, Ops); 986 break; 987 } 988 case TargetLowering::Promote: { 989 // Change base type to a different vector type. 990 MVT::ValueType OVT = Node->getValueType(0); 991 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 992 993 // Cast the two input vectors. 994 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 995 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 996 997 // Convert the shuffle mask to the right # elements. 998 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 999 assert(Tmp3.Val && "Shuffle not legal?"); 1000 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1001 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1002 break; 1003 } 1004 } 1005 break; 1006 1007 case ISD::EXTRACT_VECTOR_ELT: 1008 Tmp1 = LegalizeOp(Node->getOperand(0)); 1009 Tmp2 = LegalizeOp(Node->getOperand(1)); 1010 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1011 1012 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, 1013 Tmp1.getValueType())) { 1014 default: assert(0 && "This action is not supported yet!"); 1015 case TargetLowering::Legal: 1016 break; 1017 case TargetLowering::Custom: 1018 Tmp3 = TLI.LowerOperation(Result, DAG); 1019 if (Tmp3.Val) { 1020 Result = Tmp3; 1021 break; 1022 } 1023 // FALLTHROUGH 1024 case TargetLowering::Expand: 1025 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1026 break; 1027 } 1028 break; 1029 1030 case ISD::VEXTRACT_VECTOR_ELT: 1031 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op)); 1032 break; 1033 1034 case ISD::CALLSEQ_START: { 1035 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1036 1037 // Recursively Legalize all of the inputs of the call end that do not lead 1038 // to this call start. This ensures that any libcalls that need be inserted 1039 // are inserted *before* the CALLSEQ_START. 1040 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1041 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node); 1042 1043 // Now that we legalized all of the inputs (which may have inserted 1044 // libcalls) create the new CALLSEQ_START node. 1045 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1046 1047 // Merge in the last call, to ensure that this call start after the last 1048 // call ended. 1049 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1050 Tmp1 = LegalizeOp(Tmp1); 1051 1052 // Do not try to legalize the target-specific arguments (#1+). 1053 if (Tmp1 != Node->getOperand(0)) { 1054 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 1055 Ops[0] = Tmp1; 1056 Result = DAG.UpdateNodeOperands(Result, Ops); 1057 } 1058 1059 // Remember that the CALLSEQ_START is legalized. 1060 AddLegalizedOperand(Op.getValue(0), Result); 1061 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1062 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1063 1064 // Now that the callseq_start and all of the non-call nodes above this call 1065 // sequence have been legalized, legalize the call itself. During this 1066 // process, no libcalls can/will be inserted, guaranteeing that no calls 1067 // can overlap. 1068 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1069 SDOperand InCallSEQ = LastCALLSEQ_END; 1070 // Note that we are selecting this call! 1071 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1072 IsLegalizingCall = true; 1073 1074 // Legalize the call, starting from the CALLSEQ_END. 1075 LegalizeOp(LastCALLSEQ_END); 1076 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1077 return Result; 1078 } 1079 case ISD::CALLSEQ_END: 1080 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1081 // will cause this node to be legalized as well as handling libcalls right. 1082 if (LastCALLSEQ_END.Val != Node) { 1083 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1084 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1085 assert(I != LegalizedNodes.end() && 1086 "Legalizing the call start should have legalized this node!"); 1087 return I->second; 1088 } 1089 1090 // Otherwise, the call start has been legalized and everything is going 1091 // according to plan. Just legalize ourselves normally here. 1092 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1093 // Do not try to legalize the target-specific arguments (#1+), except for 1094 // an optional flag input. 1095 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1096 if (Tmp1 != Node->getOperand(0)) { 1097 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 1098 Ops[0] = Tmp1; 1099 Result = DAG.UpdateNodeOperands(Result, Ops); 1100 } 1101 } else { 1102 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1103 if (Tmp1 != Node->getOperand(0) || 1104 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1105 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 1106 Ops[0] = Tmp1; 1107 Ops.back() = Tmp2; 1108 Result = DAG.UpdateNodeOperands(Result, Ops); 1109 } 1110 } 1111 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1112 // This finishes up call legalization. 1113 IsLegalizingCall = false; 1114 1115 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1116 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1117 if (Node->getNumValues() == 2) 1118 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1119 return Result.getValue(Op.ResNo); 1120 case ISD::DYNAMIC_STACKALLOC: { 1121 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1122 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1123 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1124 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1125 1126 Tmp1 = Result.getValue(0); 1127 Tmp2 = Result.getValue(1); 1128 switch (TLI.getOperationAction(Node->getOpcode(), 1129 Node->getValueType(0))) { 1130 default: assert(0 && "This action is not supported yet!"); 1131 case TargetLowering::Expand: { 1132 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1133 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1134 " not tell us which reg is the stack pointer!"); 1135 SDOperand Chain = Tmp1.getOperand(0); 1136 SDOperand Size = Tmp2.getOperand(1); 1137 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0)); 1138 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value 1139 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain 1140 Tmp1 = LegalizeOp(Tmp1); 1141 Tmp2 = LegalizeOp(Tmp2); 1142 break; 1143 } 1144 case TargetLowering::Custom: 1145 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1146 if (Tmp3.Val) { 1147 Tmp1 = LegalizeOp(Tmp3); 1148 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1149 } 1150 break; 1151 case TargetLowering::Legal: 1152 break; 1153 } 1154 // Since this op produce two values, make sure to remember that we 1155 // legalized both of them. 1156 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1157 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1158 return Op.ResNo ? Tmp2 : Tmp1; 1159 } 1160 case ISD::INLINEASM: 1161 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize Chain. 1162 Tmp2 = Node->getOperand(Node->getNumOperands()-1); 1163 if (Tmp2.getValueType() == MVT::Flag) // Legalize Flag if it exists. 1164 Tmp2 = Tmp3 = SDOperand(0, 0); 1165 else 1166 Tmp3 = LegalizeOp(Tmp2); 1167 1168 if (Tmp1 != Node->getOperand(0) || Tmp2 != Tmp3) { 1169 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()); 1170 Ops[0] = Tmp1; 1171 if (Tmp3.Val) Ops.back() = Tmp3; 1172 Result = DAG.UpdateNodeOperands(Result, Ops); 1173 } 1174 1175 // INLINE asm returns a chain and flag, make sure to add both to the map. 1176 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1177 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1178 return Result.getValue(Op.ResNo); 1179 case ISD::BR: 1180 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1181 // Ensure that libcalls are emitted before a branch. 1182 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1183 Tmp1 = LegalizeOp(Tmp1); 1184 LastCALLSEQ_END = DAG.getEntryNode(); 1185 1186 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1187 break; 1188 case ISD::BRIND: 1189 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1190 // Ensure that libcalls are emitted before a branch. 1191 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1192 Tmp1 = LegalizeOp(Tmp1); 1193 LastCALLSEQ_END = DAG.getEntryNode(); 1194 1195 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1196 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1197 case Legal: 1198 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1199 break; 1200 } 1201 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1202 break; 1203 case ISD::BRCOND: 1204 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1205 // Ensure that libcalls are emitted before a return. 1206 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1207 Tmp1 = LegalizeOp(Tmp1); 1208 LastCALLSEQ_END = DAG.getEntryNode(); 1209 1210 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1211 case Expand: assert(0 && "It's impossible to expand bools"); 1212 case Legal: 1213 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1214 break; 1215 case Promote: 1216 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1217 break; 1218 } 1219 1220 // Basic block destination (Op#2) is always legal. 1221 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1222 1223 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1224 default: assert(0 && "This action is not supported yet!"); 1225 case TargetLowering::Legal: break; 1226 case TargetLowering::Custom: 1227 Tmp1 = TLI.LowerOperation(Result, DAG); 1228 if (Tmp1.Val) Result = Tmp1; 1229 break; 1230 case TargetLowering::Expand: 1231 // Expand brcond's setcc into its constituent parts and create a BR_CC 1232 // Node. 1233 if (Tmp2.getOpcode() == ISD::SETCC) { 1234 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1235 Tmp2.getOperand(0), Tmp2.getOperand(1), 1236 Node->getOperand(2)); 1237 } else { 1238 // Make sure the condition is either zero or one. It may have been 1239 // promoted from something else. 1240 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType()); 1241 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1)) 1242 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1243 1244 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1245 DAG.getCondCode(ISD::SETNE), Tmp2, 1246 DAG.getConstant(0, Tmp2.getValueType()), 1247 Node->getOperand(2)); 1248 } 1249 break; 1250 } 1251 break; 1252 case ISD::BR_CC: 1253 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1254 // Ensure that libcalls are emitted before a branch. 1255 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1256 Tmp1 = LegalizeOp(Tmp1); 1257 LastCALLSEQ_END = DAG.getEntryNode(); 1258 1259 Tmp2 = Node->getOperand(2); // LHS 1260 Tmp3 = Node->getOperand(3); // RHS 1261 Tmp4 = Node->getOperand(1); // CC 1262 1263 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1264 1265 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1266 // the LHS is a legal SETCC itself. In this case, we need to compare 1267 // the result against zero to select between true and false values. 1268 if (Tmp3.Val == 0) { 1269 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1270 Tmp4 = DAG.getCondCode(ISD::SETNE); 1271 } 1272 1273 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1274 Node->getOperand(4)); 1275 1276 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1277 default: assert(0 && "Unexpected action for BR_CC!"); 1278 case TargetLowering::Legal: break; 1279 case TargetLowering::Custom: 1280 Tmp4 = TLI.LowerOperation(Result, DAG); 1281 if (Tmp4.Val) Result = Tmp4; 1282 break; 1283 } 1284 break; 1285 case ISD::LOAD: { 1286 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1287 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1288 1289 MVT::ValueType VT = Node->getValueType(0); 1290 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1291 Tmp3 = Result.getValue(0); 1292 Tmp4 = Result.getValue(1); 1293 1294 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1295 default: assert(0 && "This action is not supported yet!"); 1296 case TargetLowering::Legal: break; 1297 case TargetLowering::Custom: 1298 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1299 if (Tmp1.Val) { 1300 Tmp3 = LegalizeOp(Tmp1); 1301 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1302 } 1303 break; 1304 case TargetLowering::Promote: { 1305 // Only promote a load of vector type to another. 1306 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1307 // Change base type to a different vector type. 1308 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1309 1310 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, Node->getOperand(2)); 1311 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1312 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1313 break; 1314 } 1315 } 1316 // Since loads produce two values, make sure to remember that we 1317 // legalized both of them. 1318 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1319 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1320 return Op.ResNo ? Tmp4 : Tmp3; 1321 } 1322 case ISD::EXTLOAD: 1323 case ISD::SEXTLOAD: 1324 case ISD::ZEXTLOAD: { 1325 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1326 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1327 1328 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 1329 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 1330 default: assert(0 && "This action is not supported yet!"); 1331 case TargetLowering::Promote: 1332 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 1333 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), 1334 DAG.getValueType(MVT::i8)); 1335 Tmp1 = Result.getValue(0); 1336 Tmp2 = Result.getValue(1); 1337 break; 1338 case TargetLowering::Custom: 1339 isCustom = true; 1340 // FALLTHROUGH 1341 case TargetLowering::Legal: 1342 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2), 1343 Node->getOperand(3)); 1344 Tmp1 = Result.getValue(0); 1345 Tmp2 = Result.getValue(1); 1346 1347 if (isCustom) { 1348 Tmp3 = TLI.LowerOperation(Tmp3, DAG); 1349 if (Tmp3.Val) { 1350 Tmp1 = LegalizeOp(Tmp3); 1351 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1352 } 1353 } 1354 break; 1355 case TargetLowering::Expand: 1356 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1357 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1358 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 1359 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1360 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1361 Tmp2 = LegalizeOp(Load.getValue(1)); 1362 break; 1363 } 1364 assert(Node->getOpcode() != ISD::EXTLOAD && 1365 "EXTLOAD should always be supported!"); 1366 // Turn the unsupported load into an EXTLOAD followed by an explicit 1367 // zero/sign extend inreg. 1368 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1369 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1370 SDOperand ValRes; 1371 if (Node->getOpcode() == ISD::SEXTLOAD) 1372 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1373 Result, DAG.getValueType(SrcVT)); 1374 else 1375 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1376 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1377 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1378 break; 1379 } 1380 // Since loads produce two values, make sure to remember that we legalized 1381 // both of them. 1382 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1383 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1384 return Op.ResNo ? Tmp2 : Tmp1; 1385 } 1386 case ISD::EXTRACT_ELEMENT: { 1387 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1388 switch (getTypeAction(OpTy)) { 1389 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1390 case Legal: 1391 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1392 // 1 -> Hi 1393 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1394 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1395 TLI.getShiftAmountTy())); 1396 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1397 } else { 1398 // 0 -> Lo 1399 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1400 Node->getOperand(0)); 1401 } 1402 break; 1403 case Expand: 1404 // Get both the low and high parts. 1405 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1406 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1407 Result = Tmp2; // 1 -> Hi 1408 else 1409 Result = Tmp1; // 0 -> Lo 1410 break; 1411 } 1412 break; 1413 } 1414 1415 case ISD::CopyToReg: 1416 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1417 1418 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1419 "Register type must be legal!"); 1420 // Legalize the incoming value (must be a legal type). 1421 Tmp2 = LegalizeOp(Node->getOperand(2)); 1422 if (Node->getNumValues() == 1) { 1423 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1424 } else { 1425 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1426 if (Node->getNumOperands() == 4) { 1427 Tmp3 = LegalizeOp(Node->getOperand(3)); 1428 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1429 Tmp3); 1430 } else { 1431 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1432 } 1433 1434 // Since this produces two values, make sure to remember that we legalized 1435 // both of them. 1436 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1437 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1438 return Result; 1439 } 1440 break; 1441 1442 case ISD::RET: 1443 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1444 1445 // Ensure that libcalls are emitted before a return. 1446 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1447 Tmp1 = LegalizeOp(Tmp1); 1448 LastCALLSEQ_END = DAG.getEntryNode(); 1449 1450 switch (Node->getNumOperands()) { 1451 case 2: // ret val 1452 Tmp2 = Node->getOperand(1); 1453 switch (getTypeAction(Tmp2.getValueType())) { 1454 case Legal: 1455 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2)); 1456 break; 1457 case Expand: 1458 if (Tmp2.getValueType() != MVT::Vector) { 1459 SDOperand Lo, Hi; 1460 ExpandOp(Tmp2, Lo, Hi); 1461 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1462 } else { 1463 SDNode *InVal = Tmp2.Val; 1464 unsigned NumElems = 1465 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1466 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1467 1468 // Figure out if there is a Packed type corresponding to this Vector 1469 // type. If so, convert to the packed type. 1470 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1471 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1472 // Turn this into a return of the packed type. 1473 Tmp2 = PackVectorOp(Tmp2, TVT); 1474 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1475 } else if (NumElems == 1) { 1476 // Turn this into a return of the scalar type. 1477 Tmp2 = PackVectorOp(Tmp2, EVT); 1478 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1479 1480 // FIXME: Returns of gcc generic vectors smaller than a legal type 1481 // should be returned in integer registers! 1482 1483 // The scalarized value type may not be legal, e.g. it might require 1484 // promotion or expansion. Relegalize the return. 1485 Result = LegalizeOp(Result); 1486 } else { 1487 // FIXME: Returns of gcc generic vectors larger than a legal vector 1488 // type should be returned by reference! 1489 SDOperand Lo, Hi; 1490 SplitVectorOp(Tmp2, Lo, Hi); 1491 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1492 Result = LegalizeOp(Result); 1493 } 1494 } 1495 break; 1496 case Promote: 1497 Tmp2 = PromoteOp(Node->getOperand(1)); 1498 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1499 Result = LegalizeOp(Result); 1500 break; 1501 } 1502 break; 1503 case 1: // ret void 1504 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1505 break; 1506 default: { // ret <values> 1507 std::vector<SDOperand> NewValues; 1508 NewValues.push_back(Tmp1); 1509 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1510 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1511 case Legal: 1512 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1513 break; 1514 case Expand: { 1515 SDOperand Lo, Hi; 1516 assert(Node->getOperand(i).getValueType() != MVT::Vector && 1517 "FIXME: TODO: implement returning non-legal vector types!"); 1518 ExpandOp(Node->getOperand(i), Lo, Hi); 1519 NewValues.push_back(Lo); 1520 NewValues.push_back(Hi); 1521 break; 1522 } 1523 case Promote: 1524 assert(0 && "Can't promote multiple return value yet!"); 1525 } 1526 1527 if (NewValues.size() == Node->getNumOperands()) 1528 Result = DAG.UpdateNodeOperands(Result, NewValues); 1529 else 1530 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1531 break; 1532 } 1533 } 1534 1535 if (Result.getOpcode() == ISD::RET) { 1536 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 1537 default: assert(0 && "This action is not supported yet!"); 1538 case TargetLowering::Legal: break; 1539 case TargetLowering::Custom: 1540 Tmp1 = TLI.LowerOperation(Result, DAG); 1541 if (Tmp1.Val) Result = Tmp1; 1542 break; 1543 } 1544 } 1545 break; 1546 case ISD::STORE: { 1547 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1548 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1549 1550 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1551 // FIXME: We shouldn't do this for TargetConstantFP's. 1552 // FIXME: move this to the DAG Combiner! 1553 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1554 if (CFP->getValueType(0) == MVT::f32) { 1555 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 1556 } else { 1557 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1558 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 1559 } 1560 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1561 Node->getOperand(3)); 1562 break; 1563 } 1564 1565 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1566 case Legal: { 1567 Tmp3 = LegalizeOp(Node->getOperand(1)); 1568 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1569 Node->getOperand(3)); 1570 1571 MVT::ValueType VT = Tmp3.getValueType(); 1572 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1573 default: assert(0 && "This action is not supported yet!"); 1574 case TargetLowering::Legal: break; 1575 case TargetLowering::Custom: 1576 Tmp1 = TLI.LowerOperation(Result, DAG); 1577 if (Tmp1.Val) Result = Tmp1; 1578 break; 1579 case TargetLowering::Promote: 1580 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 1581 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 1582 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1583 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1584 Node->getOperand(3)); 1585 break; 1586 } 1587 break; 1588 } 1589 case Promote: 1590 // Truncate the value and store the result. 1591 Tmp3 = PromoteOp(Node->getOperand(1)); 1592 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1593 Node->getOperand(3), 1594 DAG.getValueType(Node->getOperand(1).getValueType())); 1595 break; 1596 1597 case Expand: 1598 unsigned IncrementSize = 0; 1599 SDOperand Lo, Hi; 1600 1601 // If this is a vector type, then we have to calculate the increment as 1602 // the product of the element size in bytes, and the number of elements 1603 // in the high half of the vector. 1604 if (Node->getOperand(1).getValueType() == MVT::Vector) { 1605 SDNode *InVal = Node->getOperand(1).Val; 1606 unsigned NumElems = 1607 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 1608 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 1609 1610 // Figure out if there is a Packed type corresponding to this Vector 1611 // type. If so, convert to the packed type. 1612 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1613 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 1614 // Turn this into a normal store of the packed type. 1615 Tmp3 = PackVectorOp(Node->getOperand(1), TVT); 1616 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1617 Node->getOperand(3)); 1618 Result = LegalizeOp(Result); 1619 break; 1620 } else if (NumElems == 1) { 1621 // Turn this into a normal store of the scalar type. 1622 Tmp3 = PackVectorOp(Node->getOperand(1), EVT); 1623 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1624 Node->getOperand(3)); 1625 // The scalarized value type may not be legal, e.g. it might require 1626 // promotion or expansion. Relegalize the scalar store. 1627 Result = LegalizeOp(Result); 1628 break; 1629 } else { 1630 SplitVectorOp(Node->getOperand(1), Lo, Hi); 1631 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8; 1632 } 1633 } else { 1634 ExpandOp(Node->getOperand(1), Lo, Hi); 1635 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1636 1637 if (!TLI.isLittleEndian()) 1638 std::swap(Lo, Hi); 1639 } 1640 1641 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1642 Node->getOperand(3)); 1643 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1644 getIntPtrConstant(IncrementSize)); 1645 assert(isTypeLegal(Tmp2.getValueType()) && 1646 "Pointers must be legal!"); 1647 // FIXME: This sets the srcvalue of both halves to be the same, which is 1648 // wrong. 1649 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1650 Node->getOperand(3)); 1651 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1652 break; 1653 } 1654 break; 1655 } 1656 case ISD::PCMARKER: 1657 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1658 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1659 break; 1660 case ISD::STACKSAVE: 1661 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1662 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1663 Tmp1 = Result.getValue(0); 1664 Tmp2 = Result.getValue(1); 1665 1666 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 1667 default: assert(0 && "This action is not supported yet!"); 1668 case TargetLowering::Legal: break; 1669 case TargetLowering::Custom: 1670 Tmp3 = TLI.LowerOperation(Result, DAG); 1671 if (Tmp3.Val) { 1672 Tmp1 = LegalizeOp(Tmp3); 1673 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1674 } 1675 break; 1676 case TargetLowering::Expand: 1677 // Expand to CopyFromReg if the target set 1678 // StackPointerRegisterToSaveRestore. 1679 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1680 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 1681 Node->getValueType(0)); 1682 Tmp2 = Tmp1.getValue(1); 1683 } else { 1684 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 1685 Tmp2 = Node->getOperand(0); 1686 } 1687 break; 1688 } 1689 1690 // Since stacksave produce two values, make sure to remember that we 1691 // legalized both of them. 1692 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1693 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1694 return Op.ResNo ? Tmp2 : Tmp1; 1695 1696 case ISD::STACKRESTORE: 1697 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1698 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1699 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1700 1701 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 1702 default: assert(0 && "This action is not supported yet!"); 1703 case TargetLowering::Legal: break; 1704 case TargetLowering::Custom: 1705 Tmp1 = TLI.LowerOperation(Result, DAG); 1706 if (Tmp1.Val) Result = Tmp1; 1707 break; 1708 case TargetLowering::Expand: 1709 // Expand to CopyToReg if the target set 1710 // StackPointerRegisterToSaveRestore. 1711 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 1712 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 1713 } else { 1714 Result = Tmp1; 1715 } 1716 break; 1717 } 1718 break; 1719 1720 case ISD::READCYCLECOUNTER: 1721 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1722 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1723 1724 // Since rdcc produce two values, make sure to remember that we legalized 1725 // both of them. 1726 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1727 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1728 return Result; 1729 1730 case ISD::TRUNCSTORE: { 1731 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1732 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1733 1734 assert(isTypeLegal(Node->getOperand(1).getValueType()) && 1735 "Cannot handle illegal TRUNCSTORE yet!"); 1736 Tmp2 = LegalizeOp(Node->getOperand(1)); 1737 1738 // The only promote case we handle is TRUNCSTORE:i1 X into 1739 // -> TRUNCSTORE:i8 (and X, 1) 1740 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1741 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1742 TargetLowering::Promote) { 1743 // Promote the bool to a mask then store. 1744 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1745 DAG.getConstant(1, Tmp2.getValueType())); 1746 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1747 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1748 1749 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1750 Tmp3 != Node->getOperand(2)) { 1751 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 1752 Node->getOperand(3), Node->getOperand(4)); 1753 } 1754 1755 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT(); 1756 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) { 1757 default: assert(0 && "This action is not supported yet!"); 1758 case TargetLowering::Legal: break; 1759 case TargetLowering::Custom: 1760 Tmp1 = TLI.LowerOperation(Result, DAG); 1761 if (Tmp1.Val) Result = Tmp1; 1762 break; 1763 } 1764 break; 1765 } 1766 case ISD::SELECT: 1767 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1768 case Expand: assert(0 && "It's impossible to expand bools"); 1769 case Legal: 1770 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1771 break; 1772 case Promote: 1773 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1774 break; 1775 } 1776 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1777 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1778 1779 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1780 1781 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1782 default: assert(0 && "This action is not supported yet!"); 1783 case TargetLowering::Legal: break; 1784 case TargetLowering::Custom: { 1785 Tmp1 = TLI.LowerOperation(Result, DAG); 1786 if (Tmp1.Val) Result = Tmp1; 1787 break; 1788 } 1789 case TargetLowering::Expand: 1790 if (Tmp1.getOpcode() == ISD::SETCC) { 1791 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1792 Tmp2, Tmp3, 1793 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1794 } else { 1795 // Make sure the condition is either zero or one. It may have been 1796 // promoted from something else. 1797 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType()); 1798 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1)) 1799 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1800 Result = DAG.getSelectCC(Tmp1, 1801 DAG.getConstant(0, Tmp1.getValueType()), 1802 Tmp2, Tmp3, ISD::SETNE); 1803 } 1804 break; 1805 case TargetLowering::Promote: { 1806 MVT::ValueType NVT = 1807 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1808 unsigned ExtOp, TruncOp; 1809 if (MVT::isVector(Tmp2.getValueType())) { 1810 ExtOp = ISD::BIT_CONVERT; 1811 TruncOp = ISD::BIT_CONVERT; 1812 } else if (MVT::isInteger(Tmp2.getValueType())) { 1813 ExtOp = ISD::ANY_EXTEND; 1814 TruncOp = ISD::TRUNCATE; 1815 } else { 1816 ExtOp = ISD::FP_EXTEND; 1817 TruncOp = ISD::FP_ROUND; 1818 } 1819 // Promote each of the values to the new type. 1820 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1821 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1822 // Perform the larger operation, then round down. 1823 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1824 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1825 break; 1826 } 1827 } 1828 break; 1829 case ISD::SELECT_CC: { 1830 Tmp1 = Node->getOperand(0); // LHS 1831 Tmp2 = Node->getOperand(1); // RHS 1832 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1833 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1834 SDOperand CC = Node->getOperand(4); 1835 1836 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 1837 1838 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1839 // the LHS is a legal SETCC itself. In this case, we need to compare 1840 // the result against zero to select between true and false values. 1841 if (Tmp2.Val == 0) { 1842 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1843 CC = DAG.getCondCode(ISD::SETNE); 1844 } 1845 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 1846 1847 // Everything is legal, see if we should expand this op or something. 1848 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 1849 default: assert(0 && "This action is not supported yet!"); 1850 case TargetLowering::Legal: break; 1851 case TargetLowering::Custom: 1852 Tmp1 = TLI.LowerOperation(Result, DAG); 1853 if (Tmp1.Val) Result = Tmp1; 1854 break; 1855 } 1856 break; 1857 } 1858 case ISD::SETCC: 1859 Tmp1 = Node->getOperand(0); 1860 Tmp2 = Node->getOperand(1); 1861 Tmp3 = Node->getOperand(2); 1862 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 1863 1864 // If we had to Expand the SetCC operands into a SELECT node, then it may 1865 // not always be possible to return a true LHS & RHS. In this case, just 1866 // return the value we legalized, returned in the LHS 1867 if (Tmp2.Val == 0) { 1868 Result = Tmp1; 1869 break; 1870 } 1871 1872 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 1873 default: assert(0 && "Cannot handle this action for SETCC yet!"); 1874 case TargetLowering::Custom: 1875 isCustom = true; 1876 // FALLTHROUGH. 1877 case TargetLowering::Legal: 1878 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1879 if (isCustom) { 1880 Tmp3 = TLI.LowerOperation(Result, DAG); 1881 if (Tmp3.Val) Result = Tmp3; 1882 } 1883 break; 1884 case TargetLowering::Promote: { 1885 // First step, figure out the appropriate operation to use. 1886 // Allow SETCC to not be supported for all legal data types 1887 // Mostly this targets FP 1888 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1889 MVT::ValueType OldVT = NewInTy; 1890 1891 // Scan for the appropriate larger type to use. 1892 while (1) { 1893 NewInTy = (MVT::ValueType)(NewInTy+1); 1894 1895 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1896 "Fell off of the edge of the integer world"); 1897 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1898 "Fell off of the edge of the floating point world"); 1899 1900 // If the target supports SETCC of this type, use it. 1901 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 1902 break; 1903 } 1904 if (MVT::isInteger(NewInTy)) 1905 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1906 else { 1907 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1908 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1909 } 1910 Tmp1 = LegalizeOp(Tmp1); 1911 Tmp2 = LegalizeOp(Tmp2); 1912 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1913 Result = LegalizeOp(Result); 1914 break; 1915 } 1916 case TargetLowering::Expand: 1917 // Expand a setcc node into a select_cc of the same condition, lhs, and 1918 // rhs that selects between const 1 (true) and const 0 (false). 1919 MVT::ValueType VT = Node->getValueType(0); 1920 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1921 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1922 Node->getOperand(2)); 1923 break; 1924 } 1925 break; 1926 case ISD::MEMSET: 1927 case ISD::MEMCPY: 1928 case ISD::MEMMOVE: { 1929 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1930 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1931 1932 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1933 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1934 case Expand: assert(0 && "Cannot expand a byte!"); 1935 case Legal: 1936 Tmp3 = LegalizeOp(Node->getOperand(2)); 1937 break; 1938 case Promote: 1939 Tmp3 = PromoteOp(Node->getOperand(2)); 1940 break; 1941 } 1942 } else { 1943 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1944 } 1945 1946 SDOperand Tmp4; 1947 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1948 case Expand: { 1949 // Length is too big, just take the lo-part of the length. 1950 SDOperand HiPart; 1951 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1952 break; 1953 } 1954 case Legal: 1955 Tmp4 = LegalizeOp(Node->getOperand(3)); 1956 break; 1957 case Promote: 1958 Tmp4 = PromoteOp(Node->getOperand(3)); 1959 break; 1960 } 1961 1962 SDOperand Tmp5; 1963 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1964 case Expand: assert(0 && "Cannot expand this yet!"); 1965 case Legal: 1966 Tmp5 = LegalizeOp(Node->getOperand(4)); 1967 break; 1968 case Promote: 1969 Tmp5 = PromoteOp(Node->getOperand(4)); 1970 break; 1971 } 1972 1973 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1974 default: assert(0 && "This action not implemented for this operation!"); 1975 case TargetLowering::Custom: 1976 isCustom = true; 1977 // FALLTHROUGH 1978 case TargetLowering::Legal: 1979 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5); 1980 if (isCustom) { 1981 Tmp1 = TLI.LowerOperation(Result, DAG); 1982 if (Tmp1.Val) Result = Tmp1; 1983 } 1984 break; 1985 case TargetLowering::Expand: { 1986 // Otherwise, the target does not support this operation. Lower the 1987 // operation to an explicit libcall as appropriate. 1988 MVT::ValueType IntPtr = TLI.getPointerTy(); 1989 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 1990 std::vector<std::pair<SDOperand, const Type*> > Args; 1991 1992 const char *FnName = 0; 1993 if (Node->getOpcode() == ISD::MEMSET) { 1994 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1995 // Extend the (previously legalized) ubyte argument to be an int value 1996 // for the call. 1997 if (Tmp3.getValueType() > MVT::i32) 1998 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 1999 else 2000 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2001 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 2002 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 2003 2004 FnName = "memset"; 2005 } else if (Node->getOpcode() == ISD::MEMCPY || 2006 Node->getOpcode() == ISD::MEMMOVE) { 2007 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 2008 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 2009 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 2010 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2011 } else { 2012 assert(0 && "Unknown op!"); 2013 } 2014 2015 std::pair<SDOperand,SDOperand> CallResult = 2016 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 2017 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2018 Result = CallResult.second; 2019 break; 2020 } 2021 } 2022 break; 2023 } 2024 2025 case ISD::SHL_PARTS: 2026 case ISD::SRA_PARTS: 2027 case ISD::SRL_PARTS: { 2028 std::vector<SDOperand> Ops; 2029 bool Changed = false; 2030 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2031 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2032 Changed |= Ops.back() != Node->getOperand(i); 2033 } 2034 if (Changed) 2035 Result = DAG.UpdateNodeOperands(Result, Ops); 2036 2037 switch (TLI.getOperationAction(Node->getOpcode(), 2038 Node->getValueType(0))) { 2039 default: assert(0 && "This action is not supported yet!"); 2040 case TargetLowering::Legal: break; 2041 case TargetLowering::Custom: 2042 Tmp1 = TLI.LowerOperation(Result, DAG); 2043 if (Tmp1.Val) { 2044 SDOperand Tmp2, RetVal(0, 0); 2045 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2046 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2047 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2048 if (i == Op.ResNo) 2049 RetVal = Tmp2; 2050 } 2051 assert(RetVal.Val && "Illegal result number"); 2052 return RetVal; 2053 } 2054 break; 2055 } 2056 2057 // Since these produce multiple values, make sure to remember that we 2058 // legalized all of them. 2059 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2060 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2061 return Result.getValue(Op.ResNo); 2062 } 2063 2064 // Binary operators 2065 case ISD::ADD: 2066 case ISD::SUB: 2067 case ISD::MUL: 2068 case ISD::MULHS: 2069 case ISD::MULHU: 2070 case ISD::UDIV: 2071 case ISD::SDIV: 2072 case ISD::AND: 2073 case ISD::OR: 2074 case ISD::XOR: 2075 case ISD::SHL: 2076 case ISD::SRL: 2077 case ISD::SRA: 2078 case ISD::FADD: 2079 case ISD::FSUB: 2080 case ISD::FMUL: 2081 case ISD::FDIV: 2082 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2083 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2084 case Expand: assert(0 && "Not possible"); 2085 case Legal: 2086 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2087 break; 2088 case Promote: 2089 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2090 break; 2091 } 2092 2093 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2094 2095 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2096 default: assert(0 && "BinOp legalize operation not supported"); 2097 case TargetLowering::Legal: break; 2098 case TargetLowering::Custom: 2099 Tmp1 = TLI.LowerOperation(Result, DAG); 2100 if (Tmp1.Val) Result = Tmp1; 2101 break; 2102 case TargetLowering::Expand: { 2103 assert(MVT::isVector(Node->getValueType(0)) && 2104 "Cannot expand this binary operator!"); 2105 // Expand the operation into a bunch of nasty scalar code. 2106 std::vector<SDOperand> Ops; 2107 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0)); 2108 MVT::ValueType PtrVT = TLI.getPointerTy(); 2109 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0)); 2110 i != e; ++i) { 2111 SDOperand Idx = DAG.getConstant(i, PtrVT); 2112 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx); 2113 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx); 2114 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS)); 2115 } 2116 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops); 2117 break; 2118 } 2119 case TargetLowering::Promote: { 2120 switch (Node->getOpcode()) { 2121 default: assert(0 && "Do not know how to promote this BinOp!"); 2122 case ISD::AND: 2123 case ISD::OR: 2124 case ISD::XOR: { 2125 MVT::ValueType OVT = Node->getValueType(0); 2126 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2127 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2128 // Bit convert each of the values to the new type. 2129 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2130 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2131 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2132 // Bit convert the result back the original type. 2133 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2134 break; 2135 } 2136 } 2137 } 2138 } 2139 break; 2140 2141 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2142 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2143 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2144 case Expand: assert(0 && "Not possible"); 2145 case Legal: 2146 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2147 break; 2148 case Promote: 2149 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2150 break; 2151 } 2152 2153 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2154 2155 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2156 default: assert(0 && "Operation not supported"); 2157 case TargetLowering::Custom: 2158 Tmp1 = TLI.LowerOperation(Result, DAG); 2159 if (Tmp1.Val) Result = Tmp1; 2160 break; 2161 case TargetLowering::Legal: break; 2162 case TargetLowering::Expand: 2163 // If this target supports fabs/fneg natively, do this efficiently. 2164 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) && 2165 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) { 2166 // Get the sign bit of the RHS. 2167 MVT::ValueType IVT = 2168 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2169 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2170 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2171 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2172 // Get the absolute value of the result. 2173 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2174 // Select between the nabs and abs value based on the sign bit of 2175 // the input. 2176 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2177 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2178 AbsVal), 2179 AbsVal); 2180 Result = LegalizeOp(Result); 2181 break; 2182 } 2183 2184 // Otherwise, do bitwise ops! 2185 2186 // copysign -> copysignf/copysign libcall. 2187 const char *FnName; 2188 if (Node->getValueType(0) == MVT::f32) { 2189 FnName = "copysignf"; 2190 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type. 2191 Result = DAG.UpdateNodeOperands(Result, Tmp1, 2192 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2)); 2193 } else { 2194 FnName = "copysign"; 2195 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type. 2196 Result = DAG.UpdateNodeOperands(Result, Tmp1, 2197 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2)); 2198 } 2199 SDOperand Dummy; 2200 Result = ExpandLibCall(FnName, Node, Dummy); 2201 break; 2202 } 2203 break; 2204 2205 case ISD::ADDC: 2206 case ISD::SUBC: 2207 Tmp1 = LegalizeOp(Node->getOperand(0)); 2208 Tmp2 = LegalizeOp(Node->getOperand(1)); 2209 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2210 // Since this produces two values, make sure to remember that we legalized 2211 // both of them. 2212 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2213 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2214 return Result; 2215 2216 case ISD::ADDE: 2217 case ISD::SUBE: 2218 Tmp1 = LegalizeOp(Node->getOperand(0)); 2219 Tmp2 = LegalizeOp(Node->getOperand(1)); 2220 Tmp3 = LegalizeOp(Node->getOperand(2)); 2221 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2222 // Since this produces two values, make sure to remember that we legalized 2223 // both of them. 2224 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2225 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2226 return Result; 2227 2228 case ISD::BUILD_PAIR: { 2229 MVT::ValueType PairTy = Node->getValueType(0); 2230 // TODO: handle the case where the Lo and Hi operands are not of legal type 2231 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2232 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2233 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2234 case TargetLowering::Promote: 2235 case TargetLowering::Custom: 2236 assert(0 && "Cannot promote/custom this yet!"); 2237 case TargetLowering::Legal: 2238 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2239 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2240 break; 2241 case TargetLowering::Expand: 2242 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2243 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2244 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2245 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2246 TLI.getShiftAmountTy())); 2247 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2248 break; 2249 } 2250 break; 2251 } 2252 2253 case ISD::UREM: 2254 case ISD::SREM: 2255 case ISD::FREM: 2256 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2257 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2258 2259 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2260 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2261 case TargetLowering::Custom: 2262 isCustom = true; 2263 // FALLTHROUGH 2264 case TargetLowering::Legal: 2265 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2266 if (isCustom) { 2267 Tmp1 = TLI.LowerOperation(Result, DAG); 2268 if (Tmp1.Val) Result = Tmp1; 2269 } 2270 break; 2271 case TargetLowering::Expand: 2272 if (MVT::isInteger(Node->getValueType(0))) { 2273 // X % Y -> X-X/Y*Y 2274 MVT::ValueType VT = Node->getValueType(0); 2275 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV; 2276 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 2277 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2278 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2279 } else { 2280 // Floating point mod -> fmod libcall. 2281 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 2282 SDOperand Dummy; 2283 Result = ExpandLibCall(FnName, Node, Dummy); 2284 } 2285 break; 2286 } 2287 break; 2288 case ISD::VAARG: { 2289 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2290 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2291 2292 MVT::ValueType VT = Node->getValueType(0); 2293 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2294 default: assert(0 && "This action is not supported yet!"); 2295 case TargetLowering::Custom: 2296 isCustom = true; 2297 // FALLTHROUGH 2298 case TargetLowering::Legal: 2299 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2300 Result = Result.getValue(0); 2301 Tmp1 = Result.getValue(1); 2302 2303 if (isCustom) { 2304 Tmp2 = TLI.LowerOperation(Result, DAG); 2305 if (Tmp2.Val) { 2306 Result = LegalizeOp(Tmp2); 2307 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 2308 } 2309 } 2310 break; 2311 case TargetLowering::Expand: { 2312 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 2313 Node->getOperand(2)); 2314 // Increment the pointer, VAList, to the next vaarg 2315 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 2316 DAG.getConstant(MVT::getSizeInBits(VT)/8, 2317 TLI.getPointerTy())); 2318 // Store the incremented VAList to the legalized pointer 2319 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 2320 Node->getOperand(2)); 2321 // Load the actual argument out of the pointer VAList 2322 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0)); 2323 Tmp1 = LegalizeOp(Result.getValue(1)); 2324 Result = LegalizeOp(Result); 2325 break; 2326 } 2327 } 2328 // Since VAARG produces two values, make sure to remember that we 2329 // legalized both of them. 2330 AddLegalizedOperand(SDOperand(Node, 0), Result); 2331 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 2332 return Op.ResNo ? Tmp1 : Result; 2333 } 2334 2335 case ISD::VACOPY: 2336 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2337 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 2338 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 2339 2340 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 2341 default: assert(0 && "This action is not supported yet!"); 2342 case TargetLowering::Custom: 2343 isCustom = true; 2344 // FALLTHROUGH 2345 case TargetLowering::Legal: 2346 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 2347 Node->getOperand(3), Node->getOperand(4)); 2348 if (isCustom) { 2349 Tmp1 = TLI.LowerOperation(Result, DAG); 2350 if (Tmp1.Val) Result = Tmp1; 2351 } 2352 break; 2353 case TargetLowering::Expand: 2354 // This defaults to loading a pointer from the input and storing it to the 2355 // output, returning the chain. 2356 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3)); 2357 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2, 2358 Node->getOperand(4)); 2359 break; 2360 } 2361 break; 2362 2363 case ISD::VAEND: 2364 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2365 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2366 2367 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 2368 default: assert(0 && "This action is not supported yet!"); 2369 case TargetLowering::Custom: 2370 isCustom = true; 2371 // FALLTHROUGH 2372 case TargetLowering::Legal: 2373 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2374 if (isCustom) { 2375 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 2376 if (Tmp1.Val) Result = Tmp1; 2377 } 2378 break; 2379 case TargetLowering::Expand: 2380 Result = Tmp1; // Default to a no-op, return the chain 2381 break; 2382 } 2383 break; 2384 2385 case ISD::VASTART: 2386 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2387 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2388 2389 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2390 2391 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 2392 default: assert(0 && "This action is not supported yet!"); 2393 case TargetLowering::Legal: break; 2394 case TargetLowering::Custom: 2395 Tmp1 = TLI.LowerOperation(Result, DAG); 2396 if (Tmp1.Val) Result = Tmp1; 2397 break; 2398 } 2399 break; 2400 2401 case ISD::ROTL: 2402 case ISD::ROTR: 2403 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2404 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2405 2406 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 2407 "Cannot handle this yet!"); 2408 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2409 break; 2410 2411 case ISD::BSWAP: 2412 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2413 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2414 case TargetLowering::Custom: 2415 assert(0 && "Cannot custom legalize this yet!"); 2416 case TargetLowering::Legal: 2417 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2418 break; 2419 case TargetLowering::Promote: { 2420 MVT::ValueType OVT = Tmp1.getValueType(); 2421 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2422 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT); 2423 2424 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2425 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 2426 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 2427 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 2428 break; 2429 } 2430 case TargetLowering::Expand: 2431 Result = ExpandBSWAP(Tmp1); 2432 break; 2433 } 2434 break; 2435 2436 case ISD::CTPOP: 2437 case ISD::CTTZ: 2438 case ISD::CTLZ: 2439 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 2440 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2441 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!"); 2442 case TargetLowering::Legal: 2443 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2444 break; 2445 case TargetLowering::Promote: { 2446 MVT::ValueType OVT = Tmp1.getValueType(); 2447 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2448 2449 // Zero extend the argument. 2450 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2451 // Perform the larger operation, then subtract if needed. 2452 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2453 switch (Node->getOpcode()) { 2454 case ISD::CTPOP: 2455 Result = Tmp1; 2456 break; 2457 case ISD::CTTZ: 2458 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2459 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2460 DAG.getConstant(getSizeInBits(NVT), NVT), 2461 ISD::SETEQ); 2462 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2463 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 2464 break; 2465 case ISD::CTLZ: 2466 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2467 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2468 DAG.getConstant(getSizeInBits(NVT) - 2469 getSizeInBits(OVT), NVT)); 2470 break; 2471 } 2472 break; 2473 } 2474 case TargetLowering::Expand: 2475 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 2476 break; 2477 } 2478 break; 2479 2480 // Unary operators 2481 case ISD::FABS: 2482 case ISD::FNEG: 2483 case ISD::FSQRT: 2484 case ISD::FSIN: 2485 case ISD::FCOS: 2486 Tmp1 = LegalizeOp(Node->getOperand(0)); 2487 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2488 case TargetLowering::Promote: 2489 case TargetLowering::Custom: 2490 isCustom = true; 2491 // FALLTHROUGH 2492 case TargetLowering::Legal: 2493 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2494 if (isCustom) { 2495 Tmp1 = TLI.LowerOperation(Result, DAG); 2496 if (Tmp1.Val) Result = Tmp1; 2497 } 2498 break; 2499 case TargetLowering::Expand: 2500 switch (Node->getOpcode()) { 2501 default: assert(0 && "Unreachable!"); 2502 case ISD::FNEG: 2503 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2504 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2505 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 2506 break; 2507 case ISD::FABS: { 2508 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2509 MVT::ValueType VT = Node->getValueType(0); 2510 Tmp2 = DAG.getConstantFP(0.0, VT); 2511 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2512 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2513 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2514 break; 2515 } 2516 case ISD::FSQRT: 2517 case ISD::FSIN: 2518 case ISD::FCOS: { 2519 MVT::ValueType VT = Node->getValueType(0); 2520 const char *FnName = 0; 2521 switch(Node->getOpcode()) { 2522 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 2523 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 2524 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 2525 default: assert(0 && "Unreachable!"); 2526 } 2527 SDOperand Dummy; 2528 Result = ExpandLibCall(FnName, Node, Dummy); 2529 break; 2530 } 2531 } 2532 break; 2533 } 2534 break; 2535 2536 case ISD::BIT_CONVERT: 2537 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 2538 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2539 } else { 2540 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2541 Node->getOperand(0).getValueType())) { 2542 default: assert(0 && "Unknown operation action!"); 2543 case TargetLowering::Expand: 2544 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2545 break; 2546 case TargetLowering::Legal: 2547 Tmp1 = LegalizeOp(Node->getOperand(0)); 2548 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2549 break; 2550 } 2551 } 2552 break; 2553 case ISD::VBIT_CONVERT: { 2554 assert(Op.getOperand(0).getValueType() == MVT::Vector && 2555 "Can only have VBIT_CONVERT where input or output is MVT::Vector!"); 2556 2557 // The input has to be a vector type, we have to either scalarize it, pack 2558 // it, or convert it based on whether the input vector type is legal. 2559 SDNode *InVal = Node->getOperand(0).Val; 2560 unsigned NumElems = 2561 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 2562 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 2563 2564 // Figure out if there is a Packed type corresponding to this Vector 2565 // type. If so, convert to the packed type. 2566 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2567 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 2568 // Turn this into a bit convert of the packed input. 2569 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2570 PackVectorOp(Node->getOperand(0), TVT)); 2571 break; 2572 } else if (NumElems == 1) { 2573 // Turn this into a bit convert of the scalar input. 2574 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 2575 PackVectorOp(Node->getOperand(0), EVT)); 2576 break; 2577 } else { 2578 // FIXME: UNIMP! Store then reload 2579 assert(0 && "Cast from unsupported vector type not implemented yet!"); 2580 } 2581 } 2582 2583 // Conversion operators. The source and destination have different types. 2584 case ISD::SINT_TO_FP: 2585 case ISD::UINT_TO_FP: { 2586 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2587 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2588 case Legal: 2589 switch (TLI.getOperationAction(Node->getOpcode(), 2590 Node->getOperand(0).getValueType())) { 2591 default: assert(0 && "Unknown operation action!"); 2592 case TargetLowering::Custom: 2593 isCustom = true; 2594 // FALLTHROUGH 2595 case TargetLowering::Legal: 2596 Tmp1 = LegalizeOp(Node->getOperand(0)); 2597 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2598 if (isCustom) { 2599 Tmp1 = TLI.LowerOperation(Result, DAG); 2600 if (Tmp1.Val) Result = Tmp1; 2601 } 2602 break; 2603 case TargetLowering::Expand: 2604 Result = ExpandLegalINT_TO_FP(isSigned, 2605 LegalizeOp(Node->getOperand(0)), 2606 Node->getValueType(0)); 2607 break; 2608 case TargetLowering::Promote: 2609 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2610 Node->getValueType(0), 2611 isSigned); 2612 break; 2613 } 2614 break; 2615 case Expand: 2616 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2617 Node->getValueType(0), Node->getOperand(0)); 2618 break; 2619 case Promote: 2620 Tmp1 = PromoteOp(Node->getOperand(0)); 2621 if (isSigned) { 2622 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 2623 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 2624 } else { 2625 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 2626 Node->getOperand(0).getValueType()); 2627 } 2628 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2629 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 2630 break; 2631 } 2632 break; 2633 } 2634 case ISD::TRUNCATE: 2635 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2636 case Legal: 2637 Tmp1 = LegalizeOp(Node->getOperand(0)); 2638 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2639 break; 2640 case Expand: 2641 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2642 2643 // Since the result is legal, we should just be able to truncate the low 2644 // part of the source. 2645 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2646 break; 2647 case Promote: 2648 Result = PromoteOp(Node->getOperand(0)); 2649 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2650 break; 2651 } 2652 break; 2653 2654 case ISD::FP_TO_SINT: 2655 case ISD::FP_TO_UINT: 2656 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2657 case Legal: 2658 Tmp1 = LegalizeOp(Node->getOperand(0)); 2659 2660 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2661 default: assert(0 && "Unknown operation action!"); 2662 case TargetLowering::Custom: 2663 isCustom = true; 2664 // FALLTHROUGH 2665 case TargetLowering::Legal: 2666 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2667 if (isCustom) { 2668 Tmp1 = TLI.LowerOperation(Result, DAG); 2669 if (Tmp1.Val) Result = Tmp1; 2670 } 2671 break; 2672 case TargetLowering::Promote: 2673 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2674 Node->getOpcode() == ISD::FP_TO_SINT); 2675 break; 2676 case TargetLowering::Expand: 2677 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2678 SDOperand True, False; 2679 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2680 MVT::ValueType NVT = Node->getValueType(0); 2681 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2682 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2683 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2684 Node->getOperand(0), Tmp2, ISD::SETLT); 2685 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2686 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2687 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2688 Tmp2)); 2689 False = DAG.getNode(ISD::XOR, NVT, False, 2690 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2691 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 2692 break; 2693 } else { 2694 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2695 } 2696 break; 2697 } 2698 break; 2699 case Expand: 2700 assert(0 && "Shouldn't need to expand other operators here!"); 2701 case Promote: 2702 Tmp1 = PromoteOp(Node->getOperand(0)); 2703 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 2704 Result = LegalizeOp(Result); 2705 break; 2706 } 2707 break; 2708 2709 case ISD::ANY_EXTEND: 2710 case ISD::ZERO_EXTEND: 2711 case ISD::SIGN_EXTEND: 2712 case ISD::FP_EXTEND: 2713 case ISD::FP_ROUND: 2714 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2715 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 2716 case Legal: 2717 Tmp1 = LegalizeOp(Node->getOperand(0)); 2718 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2719 break; 2720 case Promote: 2721 switch (Node->getOpcode()) { 2722 case ISD::ANY_EXTEND: 2723 Tmp1 = PromoteOp(Node->getOperand(0)); 2724 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 2725 break; 2726 case ISD::ZERO_EXTEND: 2727 Result = PromoteOp(Node->getOperand(0)); 2728 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2729 Result = DAG.getZeroExtendInReg(Result, 2730 Node->getOperand(0).getValueType()); 2731 break; 2732 case ISD::SIGN_EXTEND: 2733 Result = PromoteOp(Node->getOperand(0)); 2734 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2735 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2736 Result, 2737 DAG.getValueType(Node->getOperand(0).getValueType())); 2738 break; 2739 case ISD::FP_EXTEND: 2740 Result = PromoteOp(Node->getOperand(0)); 2741 if (Result.getValueType() != Op.getValueType()) 2742 // Dynamically dead while we have only 2 FP types. 2743 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2744 break; 2745 case ISD::FP_ROUND: 2746 Result = PromoteOp(Node->getOperand(0)); 2747 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2748 break; 2749 } 2750 } 2751 break; 2752 case ISD::FP_ROUND_INREG: 2753 case ISD::SIGN_EXTEND_INREG: { 2754 Tmp1 = LegalizeOp(Node->getOperand(0)); 2755 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2756 2757 // If this operation is not supported, convert it to a shl/shr or load/store 2758 // pair. 2759 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2760 default: assert(0 && "This action not supported for this op yet!"); 2761 case TargetLowering::Legal: 2762 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2763 break; 2764 case TargetLowering::Expand: 2765 // If this is an integer extend and shifts are supported, do that. 2766 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2767 // NOTE: we could fall back on load/store here too for targets without 2768 // SAR. However, it is doubtful that any exist. 2769 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2770 MVT::getSizeInBits(ExtraVT); 2771 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2772 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2773 Node->getOperand(0), ShiftCst); 2774 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2775 Result, ShiftCst); 2776 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2777 // The only way we can lower this is to turn it into a STORETRUNC, 2778 // EXTLOAD pair, targetting a temporary location (a stack slot). 2779 2780 // NOTE: there is a choice here between constantly creating new stack 2781 // slots and always reusing the same one. We currently always create 2782 // new ones, as reuse may inhibit scheduling. 2783 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2784 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty); 2785 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty); 2786 MachineFunction &MF = DAG.getMachineFunction(); 2787 int SSFI = 2788 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2789 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2790 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2791 Node->getOperand(0), StackSlot, 2792 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2793 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2794 Result, StackSlot, DAG.getSrcValue(NULL), 2795 ExtraVT); 2796 } else { 2797 assert(0 && "Unknown op"); 2798 } 2799 break; 2800 } 2801 break; 2802 } 2803 } 2804 2805 assert(Result.getValueType() == Op.getValueType() && 2806 "Bad legalization!"); 2807 2808 // Make sure that the generated code is itself legal. 2809 if (Result != Op) 2810 Result = LegalizeOp(Result); 2811 2812 // Note that LegalizeOp may be reentered even from single-use nodes, which 2813 // means that we always must cache transformed nodes. 2814 AddLegalizedOperand(Op, Result); 2815 return Result; 2816} 2817 2818/// PromoteOp - Given an operation that produces a value in an invalid type, 2819/// promote it to compute the value into a larger type. The produced value will 2820/// have the correct bits for the low portion of the register, but no guarantee 2821/// is made about the top bits: it may be zero, sign-extended, or garbage. 2822SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2823 MVT::ValueType VT = Op.getValueType(); 2824 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2825 assert(getTypeAction(VT) == Promote && 2826 "Caller should expand or legalize operands that are not promotable!"); 2827 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2828 "Cannot promote to smaller type!"); 2829 2830 SDOperand Tmp1, Tmp2, Tmp3; 2831 SDOperand Result; 2832 SDNode *Node = Op.Val; 2833 2834 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2835 if (I != PromotedNodes.end()) return I->second; 2836 2837 switch (Node->getOpcode()) { 2838 case ISD::CopyFromReg: 2839 assert(0 && "CopyFromReg must be legal!"); 2840 default: 2841 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2842 assert(0 && "Do not know how to promote this operator!"); 2843 abort(); 2844 case ISD::UNDEF: 2845 Result = DAG.getNode(ISD::UNDEF, NVT); 2846 break; 2847 case ISD::Constant: 2848 if (VT != MVT::i1) 2849 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2850 else 2851 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2852 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2853 break; 2854 case ISD::ConstantFP: 2855 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2856 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2857 break; 2858 2859 case ISD::SETCC: 2860 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2861 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2862 Node->getOperand(1), Node->getOperand(2)); 2863 break; 2864 2865 case ISD::TRUNCATE: 2866 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2867 case Legal: 2868 Result = LegalizeOp(Node->getOperand(0)); 2869 assert(Result.getValueType() >= NVT && 2870 "This truncation doesn't make sense!"); 2871 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2872 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2873 break; 2874 case Promote: 2875 // The truncation is not required, because we don't guarantee anything 2876 // about high bits anyway. 2877 Result = PromoteOp(Node->getOperand(0)); 2878 break; 2879 case Expand: 2880 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2881 // Truncate the low part of the expanded value to the result type 2882 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2883 } 2884 break; 2885 case ISD::SIGN_EXTEND: 2886 case ISD::ZERO_EXTEND: 2887 case ISD::ANY_EXTEND: 2888 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2889 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2890 case Legal: 2891 // Input is legal? Just do extend all the way to the larger type. 2892 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 2893 break; 2894 case Promote: 2895 // Promote the reg if it's smaller. 2896 Result = PromoteOp(Node->getOperand(0)); 2897 // The high bits are not guaranteed to be anything. Insert an extend. 2898 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2899 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2900 DAG.getValueType(Node->getOperand(0).getValueType())); 2901 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2902 Result = DAG.getZeroExtendInReg(Result, 2903 Node->getOperand(0).getValueType()); 2904 break; 2905 } 2906 break; 2907 case ISD::BIT_CONVERT: 2908 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2909 Result = PromoteOp(Result); 2910 break; 2911 2912 case ISD::FP_EXTEND: 2913 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2914 case ISD::FP_ROUND: 2915 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2916 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2917 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2918 case Legal: 2919 // Input is legal? Do an FP_ROUND_INREG. 2920 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 2921 DAG.getValueType(VT)); 2922 break; 2923 } 2924 break; 2925 2926 case ISD::SINT_TO_FP: 2927 case ISD::UINT_TO_FP: 2928 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2929 case Legal: 2930 // No extra round required here. 2931 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 2932 break; 2933 2934 case Promote: 2935 Result = PromoteOp(Node->getOperand(0)); 2936 if (Node->getOpcode() == ISD::SINT_TO_FP) 2937 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2938 Result, 2939 DAG.getValueType(Node->getOperand(0).getValueType())); 2940 else 2941 Result = DAG.getZeroExtendInReg(Result, 2942 Node->getOperand(0).getValueType()); 2943 // No extra round required here. 2944 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2945 break; 2946 case Expand: 2947 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2948 Node->getOperand(0)); 2949 // Round if we cannot tolerate excess precision. 2950 if (NoExcessFPPrecision) 2951 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2952 DAG.getValueType(VT)); 2953 break; 2954 } 2955 break; 2956 2957 case ISD::SIGN_EXTEND_INREG: 2958 Result = PromoteOp(Node->getOperand(0)); 2959 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2960 Node->getOperand(1)); 2961 break; 2962 case ISD::FP_TO_SINT: 2963 case ISD::FP_TO_UINT: 2964 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2965 case Legal: 2966 Tmp1 = Node->getOperand(0); 2967 break; 2968 case Promote: 2969 // The input result is prerounded, so we don't have to do anything 2970 // special. 2971 Tmp1 = PromoteOp(Node->getOperand(0)); 2972 break; 2973 case Expand: 2974 assert(0 && "not implemented"); 2975 } 2976 // If we're promoting a UINT to a larger size, check to see if the new node 2977 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2978 // we can use that instead. This allows us to generate better code for 2979 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2980 // legal, such as PowerPC. 2981 if (Node->getOpcode() == ISD::FP_TO_UINT && 2982 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2983 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2984 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2985 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2986 } else { 2987 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2988 } 2989 break; 2990 2991 case ISD::FABS: 2992 case ISD::FNEG: 2993 Tmp1 = PromoteOp(Node->getOperand(0)); 2994 assert(Tmp1.getValueType() == NVT); 2995 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2996 // NOTE: we do not have to do any extra rounding here for 2997 // NoExcessFPPrecision, because we know the input will have the appropriate 2998 // precision, and these operations don't modify precision at all. 2999 break; 3000 3001 case ISD::FSQRT: 3002 case ISD::FSIN: 3003 case ISD::FCOS: 3004 Tmp1 = PromoteOp(Node->getOperand(0)); 3005 assert(Tmp1.getValueType() == NVT); 3006 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3007 if (NoExcessFPPrecision) 3008 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3009 DAG.getValueType(VT)); 3010 break; 3011 3012 case ISD::AND: 3013 case ISD::OR: 3014 case ISD::XOR: 3015 // The input may have strange things in the top bits of the registers, but 3016 // these operations don't care. They may have weird bits going out, but 3017 // that too is okay if they are integer operations. 3018 Tmp1 = PromoteOp(Node->getOperand(0)); 3019 Tmp2 = PromoteOp(Node->getOperand(1)); 3020 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3021 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3022 break; 3023 case ISD::ADD: 3024 case ISD::SUB: 3025 case ISD::MUL: 3026 // The input may have strange things in the top bits of the registers, but 3027 // these operations don't care. They may have weird bits going out, but 3028 // that too is okay if they are integer operations. 3029 Tmp1 = PromoteOp(Node->getOperand(0)); 3030 Tmp2 = PromoteOp(Node->getOperand(1)); 3031 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3032 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3033 break; 3034 case ISD::FADD: 3035 case ISD::FSUB: 3036 case ISD::FMUL: 3037 Tmp1 = PromoteOp(Node->getOperand(0)); 3038 Tmp2 = PromoteOp(Node->getOperand(1)); 3039 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 3040 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3041 3042 // Floating point operations will give excess precision that we may not be 3043 // able to tolerate. If we DO allow excess precision, just leave it, 3044 // otherwise excise it. 3045 // FIXME: Why would we need to round FP ops more than integer ones? 3046 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 3047 if (NoExcessFPPrecision) 3048 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3049 DAG.getValueType(VT)); 3050 break; 3051 3052 case ISD::SDIV: 3053 case ISD::SREM: 3054 // These operators require that their input be sign extended. 3055 Tmp1 = PromoteOp(Node->getOperand(0)); 3056 Tmp2 = PromoteOp(Node->getOperand(1)); 3057 if (MVT::isInteger(NVT)) { 3058 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3059 DAG.getValueType(VT)); 3060 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3061 DAG.getValueType(VT)); 3062 } 3063 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3064 3065 // Perform FP_ROUND: this is probably overly pessimistic. 3066 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 3067 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3068 DAG.getValueType(VT)); 3069 break; 3070 case ISD::FDIV: 3071 case ISD::FREM: 3072 case ISD::FCOPYSIGN: 3073 // These operators require that their input be fp extended. 3074 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3075 case Legal: 3076 Tmp1 = LegalizeOp(Node->getOperand(0)); 3077 break; 3078 case Promote: 3079 Tmp1 = PromoteOp(Node->getOperand(0)); 3080 break; 3081 case Expand: 3082 assert(0 && "not implemented"); 3083 } 3084 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3085 case Legal: 3086 Tmp2 = LegalizeOp(Node->getOperand(1)); 3087 break; 3088 case Promote: 3089 Tmp2 = PromoteOp(Node->getOperand(1)); 3090 break; 3091 case Expand: 3092 assert(0 && "not implemented"); 3093 } 3094 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3095 3096 // Perform FP_ROUND: this is probably overly pessimistic. 3097 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 3098 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3099 DAG.getValueType(VT)); 3100 break; 3101 3102 case ISD::UDIV: 3103 case ISD::UREM: 3104 // These operators require that their input be zero extended. 3105 Tmp1 = PromoteOp(Node->getOperand(0)); 3106 Tmp2 = PromoteOp(Node->getOperand(1)); 3107 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 3108 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3109 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3110 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3111 break; 3112 3113 case ISD::SHL: 3114 Tmp1 = PromoteOp(Node->getOperand(0)); 3115 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 3116 break; 3117 case ISD::SRA: 3118 // The input value must be properly sign extended. 3119 Tmp1 = PromoteOp(Node->getOperand(0)); 3120 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3121 DAG.getValueType(VT)); 3122 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 3123 break; 3124 case ISD::SRL: 3125 // The input value must be properly zero extended. 3126 Tmp1 = PromoteOp(Node->getOperand(0)); 3127 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3128 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 3129 break; 3130 3131 case ISD::VAARG: 3132 Tmp1 = Node->getOperand(0); // Get the chain. 3133 Tmp2 = Node->getOperand(1); // Get the pointer. 3134 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 3135 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 3136 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 3137 } else { 3138 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3139 Node->getOperand(2)); 3140 // Increment the pointer, VAList, to the next vaarg 3141 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3142 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3143 TLI.getPointerTy())); 3144 // Store the incremented VAList to the legalized pointer 3145 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2, 3146 Node->getOperand(2)); 3147 // Load the actual argument out of the pointer VAList 3148 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, 3149 DAG.getSrcValue(0), VT); 3150 } 3151 // Remember that we legalized the chain. 3152 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3153 break; 3154 3155 case ISD::LOAD: 3156 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0), 3157 Node->getOperand(1), Node->getOperand(2), VT); 3158 // Remember that we legalized the chain. 3159 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3160 break; 3161 case ISD::SEXTLOAD: 3162 case ISD::ZEXTLOAD: 3163 case ISD::EXTLOAD: 3164 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0), 3165 Node->getOperand(1), Node->getOperand(2), 3166 cast<VTSDNode>(Node->getOperand(3))->getVT()); 3167 // Remember that we legalized the chain. 3168 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 3169 break; 3170 case ISD::SELECT: 3171 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 3172 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 3173 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 3174 break; 3175 case ISD::SELECT_CC: 3176 Tmp2 = PromoteOp(Node->getOperand(2)); // True 3177 Tmp3 = PromoteOp(Node->getOperand(3)); // False 3178 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3179 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 3180 break; 3181 case ISD::BSWAP: 3182 Tmp1 = Node->getOperand(0); 3183 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3184 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3185 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3186 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT), 3187 TLI.getShiftAmountTy())); 3188 break; 3189 case ISD::CTPOP: 3190 case ISD::CTTZ: 3191 case ISD::CTLZ: 3192 // Zero extend the argument 3193 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 3194 // Perform the larger operation, then subtract if needed. 3195 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3196 switch(Node->getOpcode()) { 3197 case ISD::CTPOP: 3198 Result = Tmp1; 3199 break; 3200 case ISD::CTTZ: 3201 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3202 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3203 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 3204 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3205 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1); 3206 break; 3207 case ISD::CTLZ: 3208 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3209 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3210 DAG.getConstant(getSizeInBits(NVT) - 3211 getSizeInBits(VT), NVT)); 3212 break; 3213 } 3214 break; 3215 case ISD::VEXTRACT_VECTOR_ELT: 3216 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op)); 3217 break; 3218 case ISD::EXTRACT_VECTOR_ELT: 3219 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 3220 break; 3221 } 3222 3223 assert(Result.Val && "Didn't set a result!"); 3224 3225 // Make sure the result is itself legal. 3226 Result = LegalizeOp(Result); 3227 3228 // Remember that we promoted this! 3229 AddPromotedOperand(Op, Result); 3230 return Result; 3231} 3232 3233/// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a 3234/// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based 3235/// on the vector type. The return type of this matches the element type of the 3236/// vector, which may not be legal for the target. 3237SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) { 3238 // We know that operand #0 is the Vec vector. If the index is a constant 3239 // or if the invec is a supported hardware type, we can use it. Otherwise, 3240 // lower to a store then an indexed load. 3241 SDOperand Vec = Op.getOperand(0); 3242 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 3243 3244 SDNode *InVal = Vec.Val; 3245 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 3246 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 3247 3248 // Figure out if there is a Packed type corresponding to this Vector 3249 // type. If so, convert to the packed type. 3250 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3251 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 3252 // Turn this into a packed extract_vector_elt operation. 3253 Vec = PackVectorOp(Vec, TVT); 3254 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx); 3255 } else if (NumElems == 1) { 3256 // This must be an access of the only element. Return it. 3257 return PackVectorOp(Vec, EVT); 3258 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) { 3259 SDOperand Lo, Hi; 3260 SplitVectorOp(Vec, Lo, Hi); 3261 if (CIdx->getValue() < NumElems/2) { 3262 Vec = Lo; 3263 } else { 3264 Vec = Hi; 3265 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 3266 } 3267 3268 // It's now an extract from the appropriate high or low part. Recurse. 3269 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 3270 return LowerVEXTRACT_VECTOR_ELT(Op); 3271 } else { 3272 // Variable index case for extract element. 3273 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!! 3274 assert(0 && "unimp!"); 3275 return SDOperand(); 3276 } 3277} 3278 3279/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 3280/// memory traffic. 3281SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 3282 SDOperand Vector = Op.getOperand(0); 3283 SDOperand Idx = Op.getOperand(1); 3284 3285 // If the target doesn't support this, store the value to a temporary 3286 // stack slot, then LOAD the scalar element back out. 3287 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType()); 3288 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3289 Vector, StackPtr, DAG.getSrcValue(NULL)); 3290 3291 // Add the offset to the index. 3292 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 3293 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 3294 DAG.getConstant(EltSize, Idx.getValueType())); 3295 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 3296 3297 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL)); 3298} 3299 3300 3301/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 3302/// with condition CC on the current target. This usually involves legalizing 3303/// or promoting the arguments. In the case where LHS and RHS must be expanded, 3304/// there may be no choice but to create a new SetCC node to represent the 3305/// legalized value of setcc lhs, rhs. In this case, the value is returned in 3306/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 3307void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 3308 SDOperand &RHS, 3309 SDOperand &CC) { 3310 SDOperand Tmp1, Tmp2, Result; 3311 3312 switch (getTypeAction(LHS.getValueType())) { 3313 case Legal: 3314 Tmp1 = LegalizeOp(LHS); // LHS 3315 Tmp2 = LegalizeOp(RHS); // RHS 3316 break; 3317 case Promote: 3318 Tmp1 = PromoteOp(LHS); // LHS 3319 Tmp2 = PromoteOp(RHS); // RHS 3320 3321 // If this is an FP compare, the operands have already been extended. 3322 if (MVT::isInteger(LHS.getValueType())) { 3323 MVT::ValueType VT = LHS.getValueType(); 3324 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3325 3326 // Otherwise, we have to insert explicit sign or zero extends. Note 3327 // that we could insert sign extends for ALL conditions, but zero extend 3328 // is cheaper on many machines (an AND instead of two shifts), so prefer 3329 // it. 3330 switch (cast<CondCodeSDNode>(CC)->get()) { 3331 default: assert(0 && "Unknown integer comparison!"); 3332 case ISD::SETEQ: 3333 case ISD::SETNE: 3334 case ISD::SETUGE: 3335 case ISD::SETUGT: 3336 case ISD::SETULE: 3337 case ISD::SETULT: 3338 // ALL of these operations will work if we either sign or zero extend 3339 // the operands (including the unsigned comparisons!). Zero extend is 3340 // usually a simpler/cheaper operation, so prefer it. 3341 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 3342 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 3343 break; 3344 case ISD::SETGE: 3345 case ISD::SETGT: 3346 case ISD::SETLT: 3347 case ISD::SETLE: 3348 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 3349 DAG.getValueType(VT)); 3350 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 3351 DAG.getValueType(VT)); 3352 break; 3353 } 3354 } 3355 break; 3356 case Expand: 3357 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 3358 ExpandOp(LHS, LHSLo, LHSHi); 3359 ExpandOp(RHS, RHSLo, RHSHi); 3360 switch (cast<CondCodeSDNode>(CC)->get()) { 3361 case ISD::SETEQ: 3362 case ISD::SETNE: 3363 if (RHSLo == RHSHi) 3364 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 3365 if (RHSCST->isAllOnesValue()) { 3366 // Comparison to -1. 3367 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 3368 Tmp2 = RHSLo; 3369 break; 3370 } 3371 3372 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 3373 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 3374 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 3375 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3376 break; 3377 default: 3378 // If this is a comparison of the sign bit, just look at the top part. 3379 // X > -1, x < 0 3380 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 3381 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 3382 CST->getValue() == 0) || // X < 0 3383 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 3384 CST->isAllOnesValue())) { // X > -1 3385 Tmp1 = LHSHi; 3386 Tmp2 = RHSHi; 3387 break; 3388 } 3389 3390 // FIXME: This generated code sucks. 3391 ISD::CondCode LowCC; 3392 switch (cast<CondCodeSDNode>(CC)->get()) { 3393 default: assert(0 && "Unknown integer setcc!"); 3394 case ISD::SETLT: 3395 case ISD::SETULT: LowCC = ISD::SETULT; break; 3396 case ISD::SETGT: 3397 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 3398 case ISD::SETLE: 3399 case ISD::SETULE: LowCC = ISD::SETULE; break; 3400 case ISD::SETGE: 3401 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 3402 } 3403 3404 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 3405 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 3406 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 3407 3408 // NOTE: on targets without efficient SELECT of bools, we can always use 3409 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 3410 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 3411 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC); 3412 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 3413 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 3414 Result, Tmp1, Tmp2)); 3415 Tmp1 = Result; 3416 Tmp2 = SDOperand(); 3417 } 3418 } 3419 LHS = Tmp1; 3420 RHS = Tmp2; 3421} 3422 3423/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 3424/// The resultant code need not be legal. Note that SrcOp is the input operand 3425/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 3426SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 3427 SDOperand SrcOp) { 3428 // Create the stack frame object. 3429 SDOperand FIPtr = CreateStackTemporary(DestVT); 3430 3431 // Emit a store to the stack slot. 3432 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3433 SrcOp, FIPtr, DAG.getSrcValue(NULL)); 3434 // Result is a load from the stack slot. 3435 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0)); 3436} 3437 3438SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 3439 // Create a vector sized/aligned stack slot, store the value to element #0, 3440 // then load the whole vector back out. 3441 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0)); 3442 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3443 Node->getOperand(0), StackPtr, 3444 DAG.getSrcValue(NULL)); 3445 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL)); 3446} 3447 3448 3449/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 3450/// support the operation, but do support the resultant packed vector type. 3451SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 3452 3453 // If the only non-undef value is the low element, turn this into a 3454 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 3455 unsigned NumElems = Node->getNumOperands(); 3456 bool isOnlyLowElement = true; 3457 SDOperand SplatValue = Node->getOperand(0); 3458 std::map<SDOperand, std::vector<unsigned> > Values; 3459 Values[SplatValue].push_back(0); 3460 bool isConstant = true; 3461 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 3462 SplatValue.getOpcode() != ISD::UNDEF) 3463 isConstant = false; 3464 3465 for (unsigned i = 1; i < NumElems; ++i) { 3466 SDOperand V = Node->getOperand(i); 3467 Values[V].push_back(i); 3468 if (V.getOpcode() != ISD::UNDEF) 3469 isOnlyLowElement = false; 3470 if (SplatValue != V) 3471 SplatValue = SDOperand(0,0); 3472 3473 // If this isn't a constant element or an undef, we can't use a constant 3474 // pool load. 3475 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 3476 V.getOpcode() != ISD::UNDEF) 3477 isConstant = false; 3478 } 3479 3480 if (isOnlyLowElement) { 3481 // If the low element is an undef too, then this whole things is an undef. 3482 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 3483 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 3484 // Otherwise, turn this into a scalar_to_vector node. 3485 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 3486 Node->getOperand(0)); 3487 } 3488 3489 // If all elements are constants, create a load from the constant pool. 3490 if (isConstant) { 3491 MVT::ValueType VT = Node->getValueType(0); 3492 const Type *OpNTy = 3493 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 3494 std::vector<Constant*> CV; 3495 for (unsigned i = 0, e = NumElems; i != e; ++i) { 3496 if (ConstantFPSDNode *V = 3497 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 3498 CV.push_back(ConstantFP::get(OpNTy, V->getValue())); 3499 } else if (ConstantSDNode *V = 3500 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 3501 CV.push_back(ConstantUInt::get(OpNTy, V->getValue())); 3502 } else { 3503 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 3504 CV.push_back(UndefValue::get(OpNTy)); 3505 } 3506 } 3507 Constant *CP = ConstantPacked::get(CV); 3508 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 3509 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 3510 DAG.getSrcValue(NULL)); 3511 } 3512 3513 if (SplatValue.Val) { // Splat of one value? 3514 // Build the shuffle constant vector: <0, 0, 0, 0> 3515 MVT::ValueType MaskVT = 3516 MVT::getIntVectorWithNumElements(NumElems); 3517 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT)); 3518 std::vector<SDOperand> ZeroVec(NumElems, Zero); 3519 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec); 3520 3521 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 3522 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 3523 // Get the splatted value into the low element of a vector register. 3524 SDOperand LowValVec = 3525 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 3526 3527 // Return shuffle(LowValVec, undef, <0,0,0,0>) 3528 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 3529 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 3530 SplatMask); 3531 } 3532 } 3533 3534 // If there are only two unique elements, we may be able to turn this into a 3535 // vector shuffle. 3536 if (Values.size() == 2) { 3537 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 3538 MVT::ValueType MaskVT = 3539 MVT::getIntVectorWithNumElements(NumElems); 3540 std::vector<SDOperand> MaskVec(NumElems); 3541 unsigned i = 0; 3542 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 3543 E = Values.end(); I != E; ++I) { 3544 for (std::vector<unsigned>::iterator II = I->second.begin(), 3545 EE = I->second.end(); II != EE; ++II) 3546 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT)); 3547 i += NumElems; 3548 } 3549 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec); 3550 3551 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 3552 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 3553 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 3554 std::vector<SDOperand> Ops; 3555 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 3556 E = Values.end(); I != E; ++I) { 3557 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 3558 I->first); 3559 Ops.push_back(Op); 3560 } 3561 Ops.push_back(ShuffleMask); 3562 3563 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 3564 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops); 3565 } 3566 } 3567 3568 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 3569 // aligned object on the stack, store each element into it, then load 3570 // the result as a vector. 3571 MVT::ValueType VT = Node->getValueType(0); 3572 // Create the stack frame object. 3573 SDOperand FIPtr = CreateStackTemporary(VT); 3574 3575 // Emit a store of each element to the stack slot. 3576 std::vector<SDOperand> Stores; 3577 unsigned TypeByteSize = 3578 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 3579 unsigned VectorSize = MVT::getSizeInBits(VT)/8; 3580 // Store (in the right endianness) the elements to memory. 3581 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3582 // Ignore undef elements. 3583 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3584 3585 unsigned Offset = TypeByteSize*i; 3586 3587 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 3588 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 3589 3590 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3591 Node->getOperand(i), Idx, 3592 DAG.getSrcValue(NULL))); 3593 } 3594 3595 SDOperand StoreChain; 3596 if (!Stores.empty()) // Not all undef elements? 3597 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 3598 else 3599 StoreChain = DAG.getEntryNode(); 3600 3601 // Result is a load from the stack slot. 3602 return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0)); 3603} 3604 3605/// CreateStackTemporary - Create a stack temporary, suitable for holding the 3606/// specified value type. 3607SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) { 3608 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 3609 unsigned ByteSize = MVT::getSizeInBits(VT)/8; 3610 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize); 3611 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 3612} 3613 3614void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 3615 SDOperand Op, SDOperand Amt, 3616 SDOperand &Lo, SDOperand &Hi) { 3617 // Expand the subcomponents. 3618 SDOperand LHSL, LHSH; 3619 ExpandOp(Op, LHSL, LHSH); 3620 3621 std::vector<SDOperand> Ops; 3622 Ops.push_back(LHSL); 3623 Ops.push_back(LHSH); 3624 Ops.push_back(Amt); 3625 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 3626 Lo = DAG.getNode(NodeOp, VTs, Ops); 3627 Hi = Lo.getValue(1); 3628} 3629 3630 3631/// ExpandShift - Try to find a clever way to expand this shift operation out to 3632/// smaller elements. If we can't find a way that is more efficient than a 3633/// libcall on this target, return false. Otherwise, return true with the 3634/// low-parts expanded into Lo and Hi. 3635bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 3636 SDOperand &Lo, SDOperand &Hi) { 3637 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 3638 "This is not a shift!"); 3639 3640 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 3641 SDOperand ShAmt = LegalizeOp(Amt); 3642 MVT::ValueType ShTy = ShAmt.getValueType(); 3643 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 3644 unsigned NVTBits = MVT::getSizeInBits(NVT); 3645 3646 // Handle the case when Amt is an immediate. Other cases are currently broken 3647 // and are disabled. 3648 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 3649 unsigned Cst = CN->getValue(); 3650 // Expand the incoming operand to be shifted, so that we have its parts 3651 SDOperand InL, InH; 3652 ExpandOp(Op, InL, InH); 3653 switch(Opc) { 3654 case ISD::SHL: 3655 if (Cst > VTBits) { 3656 Lo = DAG.getConstant(0, NVT); 3657 Hi = DAG.getConstant(0, NVT); 3658 } else if (Cst > NVTBits) { 3659 Lo = DAG.getConstant(0, NVT); 3660 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 3661 } else if (Cst == NVTBits) { 3662 Lo = DAG.getConstant(0, NVT); 3663 Hi = InL; 3664 } else { 3665 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 3666 Hi = DAG.getNode(ISD::OR, NVT, 3667 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 3668 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 3669 } 3670 return true; 3671 case ISD::SRL: 3672 if (Cst > VTBits) { 3673 Lo = DAG.getConstant(0, NVT); 3674 Hi = DAG.getConstant(0, NVT); 3675 } else if (Cst > NVTBits) { 3676 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 3677 Hi = DAG.getConstant(0, NVT); 3678 } else if (Cst == NVTBits) { 3679 Lo = InH; 3680 Hi = DAG.getConstant(0, NVT); 3681 } else { 3682 Lo = DAG.getNode(ISD::OR, NVT, 3683 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3684 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3685 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 3686 } 3687 return true; 3688 case ISD::SRA: 3689 if (Cst > VTBits) { 3690 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 3691 DAG.getConstant(NVTBits-1, ShTy)); 3692 } else if (Cst > NVTBits) { 3693 Lo = DAG.getNode(ISD::SRA, NVT, InH, 3694 DAG.getConstant(Cst-NVTBits, ShTy)); 3695 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3696 DAG.getConstant(NVTBits-1, ShTy)); 3697 } else if (Cst == NVTBits) { 3698 Lo = InH; 3699 Hi = DAG.getNode(ISD::SRA, NVT, InH, 3700 DAG.getConstant(NVTBits-1, ShTy)); 3701 } else { 3702 Lo = DAG.getNode(ISD::OR, NVT, 3703 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 3704 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 3705 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 3706 } 3707 return true; 3708 } 3709 } 3710 return false; 3711} 3712 3713 3714// ExpandLibCall - Expand a node into a call to a libcall. If the result value 3715// does not fit into a register, return the lo part and set the hi part to the 3716// by-reg argument. If it does fit into a single register, return the result 3717// and leave the Hi part unset. 3718SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 3719 SDOperand &Hi) { 3720 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 3721 // The input chain to this libcall is the entry node of the function. 3722 // Legalizing the call will automatically add the previous call to the 3723 // dependence. 3724 SDOperand InChain = DAG.getEntryNode(); 3725 3726 TargetLowering::ArgListTy Args; 3727 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3728 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 3729 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 3730 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 3731 } 3732 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 3733 3734 // Splice the libcall in wherever FindInputOutputChains tells us to. 3735 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 3736 std::pair<SDOperand,SDOperand> CallInfo = 3737 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 3738 Callee, Args, DAG); 3739 3740 // Legalize the call sequence, starting with the chain. This will advance 3741 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 3742 // was added by LowerCallTo (guaranteeing proper serialization of calls). 3743 LegalizeOp(CallInfo.second); 3744 SDOperand Result; 3745 switch (getTypeAction(CallInfo.first.getValueType())) { 3746 default: assert(0 && "Unknown thing"); 3747 case Legal: 3748 Result = CallInfo.first; 3749 break; 3750 case Expand: 3751 ExpandOp(CallInfo.first, Result, Hi); 3752 break; 3753 } 3754 return Result; 3755} 3756 3757 3758/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 3759/// destination type is legal. 3760SDOperand SelectionDAGLegalize:: 3761ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 3762 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 3763 assert(getTypeAction(Source.getValueType()) == Expand && 3764 "This is not an expansion!"); 3765 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 3766 3767 if (!isSigned) { 3768 assert(Source.getValueType() == MVT::i64 && 3769 "This only works for 64-bit -> FP"); 3770 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 3771 // incoming integer is set. To handle this, we dynamically test to see if 3772 // it is set, and, if so, add a fudge factor. 3773 SDOperand Lo, Hi; 3774 ExpandOp(Source, Lo, Hi); 3775 3776 // If this is unsigned, and not supported, first perform the conversion to 3777 // signed, then adjust the result if the sign bit is set. 3778 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 3779 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 3780 3781 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 3782 DAG.getConstant(0, Hi.getValueType()), 3783 ISD::SETLT); 3784 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3785 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3786 SignSet, Four, Zero); 3787 uint64_t FF = 0x5f800000ULL; 3788 if (TLI.isLittleEndian()) FF <<= 32; 3789 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3790 3791 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3792 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3793 SDOperand FudgeInReg; 3794 if (DestTy == MVT::f32) 3795 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3796 DAG.getSrcValue(NULL)); 3797 else { 3798 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3799 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3800 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 3801 } 3802 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3803 } 3804 3805 // Check to see if the target has a custom way to lower this. If so, use it. 3806 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3807 default: assert(0 && "This action not implemented for this operation!"); 3808 case TargetLowering::Legal: 3809 case TargetLowering::Expand: 3810 break; // This case is handled below. 3811 case TargetLowering::Custom: { 3812 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3813 Source), DAG); 3814 if (NV.Val) 3815 return LegalizeOp(NV); 3816 break; // The target decided this was legal after all 3817 } 3818 } 3819 3820 // Expand the source, then glue it back together for the call. We must expand 3821 // the source in case it is shared (this pass of legalize must traverse it). 3822 SDOperand SrcLo, SrcHi; 3823 ExpandOp(Source, SrcLo, SrcHi); 3824 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3825 3826 const char *FnName = 0; 3827 if (DestTy == MVT::f32) 3828 FnName = "__floatdisf"; 3829 else { 3830 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3831 FnName = "__floatdidf"; 3832 } 3833 3834 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 3835 SDOperand UnusedHiPart; 3836 return ExpandLibCall(FnName, Source.Val, UnusedHiPart); 3837} 3838 3839/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 3840/// INT_TO_FP operation of the specified operand when the target requests that 3841/// we expand it. At this point, we know that the result and operand types are 3842/// legal for the target. 3843SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 3844 SDOperand Op0, 3845 MVT::ValueType DestVT) { 3846 if (Op0.getValueType() == MVT::i32) { 3847 // simple 32-bit [signed|unsigned] integer to float/double expansion 3848 3849 // get the stack frame index of a 8 byte buffer 3850 MachineFunction &MF = DAG.getMachineFunction(); 3851 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 3852 // get address of 8 byte buffer 3853 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3854 // word offset constant for Hi/Lo address computation 3855 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 3856 // set up Hi and Lo (into buffer) address based on endian 3857 SDOperand Hi = StackSlot; 3858 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 3859 if (TLI.isLittleEndian()) 3860 std::swap(Hi, Lo); 3861 3862 // if signed map to unsigned space 3863 SDOperand Op0Mapped; 3864 if (isSigned) { 3865 // constant used to invert sign bit (signed to unsigned mapping) 3866 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 3867 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 3868 } else { 3869 Op0Mapped = Op0; 3870 } 3871 // store the lo of the constructed double - based on integer input 3872 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 3873 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 3874 // initial hi portion of constructed double 3875 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 3876 // store the hi of the constructed double - biased exponent 3877 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 3878 InitialHi, Hi, DAG.getSrcValue(NULL)); 3879 // load the constructed double 3880 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 3881 DAG.getSrcValue(NULL)); 3882 // FP constant to bias correct the final result 3883 SDOperand Bias = DAG.getConstantFP(isSigned ? 3884 BitsToDouble(0x4330000080000000ULL) 3885 : BitsToDouble(0x4330000000000000ULL), 3886 MVT::f64); 3887 // subtract the bias 3888 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 3889 // final result 3890 SDOperand Result; 3891 // handle final rounding 3892 if (DestVT == MVT::f64) { 3893 // do nothing 3894 Result = Sub; 3895 } else { 3896 // if f32 then cast to f32 3897 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 3898 } 3899 return Result; 3900 } 3901 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 3902 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 3903 3904 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 3905 DAG.getConstant(0, Op0.getValueType()), 3906 ISD::SETLT); 3907 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3908 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3909 SignSet, Four, Zero); 3910 3911 // If the sign bit of the integer is set, the large number will be treated 3912 // as a negative number. To counteract this, the dynamic code adds an 3913 // offset depending on the data type. 3914 uint64_t FF; 3915 switch (Op0.getValueType()) { 3916 default: assert(0 && "Unsupported integer type!"); 3917 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 3918 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 3919 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 3920 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 3921 } 3922 if (TLI.isLittleEndian()) FF <<= 32; 3923 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3924 3925 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3926 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3927 SDOperand FudgeInReg; 3928 if (DestVT == MVT::f32) 3929 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3930 DAG.getSrcValue(NULL)); 3931 else { 3932 assert(DestVT == MVT::f64 && "Unexpected conversion"); 3933 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 3934 DAG.getEntryNode(), CPIdx, 3935 DAG.getSrcValue(NULL), MVT::f32)); 3936 } 3937 3938 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 3939} 3940 3941/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 3942/// *INT_TO_FP operation of the specified operand when the target requests that 3943/// we promote it. At this point, we know that the result and operand types are 3944/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 3945/// operation that takes a larger input. 3946SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 3947 MVT::ValueType DestVT, 3948 bool isSigned) { 3949 // First step, figure out the appropriate *INT_TO_FP operation to use. 3950 MVT::ValueType NewInTy = LegalOp.getValueType(); 3951 3952 unsigned OpToUse = 0; 3953 3954 // Scan for the appropriate larger type to use. 3955 while (1) { 3956 NewInTy = (MVT::ValueType)(NewInTy+1); 3957 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 3958 3959 // If the target supports SINT_TO_FP of this type, use it. 3960 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 3961 default: break; 3962 case TargetLowering::Legal: 3963 if (!TLI.isTypeLegal(NewInTy)) 3964 break; // Can't use this datatype. 3965 // FALL THROUGH. 3966 case TargetLowering::Custom: 3967 OpToUse = ISD::SINT_TO_FP; 3968 break; 3969 } 3970 if (OpToUse) break; 3971 if (isSigned) continue; 3972 3973 // If the target supports UINT_TO_FP of this type, use it. 3974 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 3975 default: break; 3976 case TargetLowering::Legal: 3977 if (!TLI.isTypeLegal(NewInTy)) 3978 break; // Can't use this datatype. 3979 // FALL THROUGH. 3980 case TargetLowering::Custom: 3981 OpToUse = ISD::UINT_TO_FP; 3982 break; 3983 } 3984 if (OpToUse) break; 3985 3986 // Otherwise, try a larger type. 3987 } 3988 3989 // Okay, we found the operation and type to use. Zero extend our input to the 3990 // desired type then run the operation on it. 3991 return DAG.getNode(OpToUse, DestVT, 3992 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 3993 NewInTy, LegalOp)); 3994} 3995 3996/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 3997/// FP_TO_*INT operation of the specified operand when the target requests that 3998/// we promote it. At this point, we know that the result and operand types are 3999/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 4000/// operation that returns a larger result. 4001SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 4002 MVT::ValueType DestVT, 4003 bool isSigned) { 4004 // First step, figure out the appropriate FP_TO*INT operation to use. 4005 MVT::ValueType NewOutTy = DestVT; 4006 4007 unsigned OpToUse = 0; 4008 4009 // Scan for the appropriate larger type to use. 4010 while (1) { 4011 NewOutTy = (MVT::ValueType)(NewOutTy+1); 4012 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 4013 4014 // If the target supports FP_TO_SINT returning this type, use it. 4015 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 4016 default: break; 4017 case TargetLowering::Legal: 4018 if (!TLI.isTypeLegal(NewOutTy)) 4019 break; // Can't use this datatype. 4020 // FALL THROUGH. 4021 case TargetLowering::Custom: 4022 OpToUse = ISD::FP_TO_SINT; 4023 break; 4024 } 4025 if (OpToUse) break; 4026 4027 // If the target supports FP_TO_UINT of this type, use it. 4028 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 4029 default: break; 4030 case TargetLowering::Legal: 4031 if (!TLI.isTypeLegal(NewOutTy)) 4032 break; // Can't use this datatype. 4033 // FALL THROUGH. 4034 case TargetLowering::Custom: 4035 OpToUse = ISD::FP_TO_UINT; 4036 break; 4037 } 4038 if (OpToUse) break; 4039 4040 // Otherwise, try a larger type. 4041 } 4042 4043 // Okay, we found the operation and type to use. Truncate the result of the 4044 // extended FP_TO_*INT operation to the desired size. 4045 return DAG.getNode(ISD::TRUNCATE, DestVT, 4046 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 4047} 4048 4049/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 4050/// 4051SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 4052 MVT::ValueType VT = Op.getValueType(); 4053 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 4054 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 4055 switch (VT) { 4056 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 4057 case MVT::i16: 4058 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4059 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4060 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 4061 case MVT::i32: 4062 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4063 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4064 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4065 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4066 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 4067 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 4068 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4069 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4070 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4071 case MVT::i64: 4072 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 4073 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 4074 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 4075 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 4076 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 4077 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 4078 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 4079 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 4080 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 4081 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 4082 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 4083 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 4084 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 4085 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 4086 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 4087 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 4088 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 4089 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 4090 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 4091 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 4092 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 4093 } 4094} 4095 4096/// ExpandBitCount - Expand the specified bitcount instruction into operations. 4097/// 4098SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 4099 switch (Opc) { 4100 default: assert(0 && "Cannot expand this yet!"); 4101 case ISD::CTPOP: { 4102 static const uint64_t mask[6] = { 4103 0x5555555555555555ULL, 0x3333333333333333ULL, 4104 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 4105 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 4106 }; 4107 MVT::ValueType VT = Op.getValueType(); 4108 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4109 unsigned len = getSizeInBits(VT); 4110 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4111 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 4112 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 4113 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4114 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 4115 DAG.getNode(ISD::AND, VT, 4116 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 4117 } 4118 return Op; 4119 } 4120 case ISD::CTLZ: { 4121 // for now, we do this: 4122 // x = x | (x >> 1); 4123 // x = x | (x >> 2); 4124 // ... 4125 // x = x | (x >>16); 4126 // x = x | (x >>32); // for 64-bit input 4127 // return popcount(~x); 4128 // 4129 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 4130 MVT::ValueType VT = Op.getValueType(); 4131 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 4132 unsigned len = getSizeInBits(VT); 4133 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 4134 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 4135 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 4136 } 4137 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 4138 return DAG.getNode(ISD::CTPOP, VT, Op); 4139 } 4140 case ISD::CTTZ: { 4141 // for now, we use: { return popcount(~x & (x - 1)); } 4142 // unless the target has ctlz but not ctpop, in which case we use: 4143 // { return 32 - nlz(~x & (x-1)); } 4144 // see also http://www.hackersdelight.org/HDcode/ntz.cc 4145 MVT::ValueType VT = Op.getValueType(); 4146 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 4147 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 4148 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 4149 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 4150 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 4151 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 4152 TLI.isOperationLegal(ISD::CTLZ, VT)) 4153 return DAG.getNode(ISD::SUB, VT, 4154 DAG.getConstant(getSizeInBits(VT), VT), 4155 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 4156 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 4157 } 4158 } 4159} 4160 4161/// ExpandOp - Expand the specified SDOperand into its two component pieces 4162/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 4163/// LegalizeNodes map is filled in for any results that are not expanded, the 4164/// ExpandedNodes map is filled in for any results that are expanded, and the 4165/// Lo/Hi values are returned. 4166void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 4167 MVT::ValueType VT = Op.getValueType(); 4168 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4169 SDNode *Node = Op.Val; 4170 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 4171 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 4172 "Cannot expand FP values!"); 4173 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 4174 "Cannot expand to FP value or to larger int value!"); 4175 4176 // See if we already expanded it. 4177 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 4178 = ExpandedNodes.find(Op); 4179 if (I != ExpandedNodes.end()) { 4180 Lo = I->second.first; 4181 Hi = I->second.second; 4182 return; 4183 } 4184 4185 switch (Node->getOpcode()) { 4186 case ISD::CopyFromReg: 4187 assert(0 && "CopyFromReg must be legal!"); 4188 default: 4189 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 4190 assert(0 && "Do not know how to expand this operator!"); 4191 abort(); 4192 case ISD::UNDEF: 4193 Lo = DAG.getNode(ISD::UNDEF, NVT); 4194 Hi = DAG.getNode(ISD::UNDEF, NVT); 4195 break; 4196 case ISD::Constant: { 4197 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 4198 Lo = DAG.getConstant(Cst, NVT); 4199 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 4200 break; 4201 } 4202 case ISD::BUILD_PAIR: 4203 // Return the operands. 4204 Lo = Node->getOperand(0); 4205 Hi = Node->getOperand(1); 4206 break; 4207 4208 case ISD::SIGN_EXTEND_INREG: 4209 ExpandOp(Node->getOperand(0), Lo, Hi); 4210 // Sign extend the lo-part. 4211 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4212 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 4213 TLI.getShiftAmountTy())); 4214 // sext_inreg the low part if needed. 4215 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 4216 break; 4217 4218 case ISD::BSWAP: { 4219 ExpandOp(Node->getOperand(0), Lo, Hi); 4220 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 4221 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 4222 Lo = TempLo; 4223 break; 4224 } 4225 4226 case ISD::CTPOP: 4227 ExpandOp(Node->getOperand(0), Lo, Hi); 4228 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 4229 DAG.getNode(ISD::CTPOP, NVT, Lo), 4230 DAG.getNode(ISD::CTPOP, NVT, Hi)); 4231 Hi = DAG.getConstant(0, NVT); 4232 break; 4233 4234 case ISD::CTLZ: { 4235 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 4236 ExpandOp(Node->getOperand(0), Lo, Hi); 4237 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4238 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 4239 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 4240 ISD::SETNE); 4241 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 4242 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 4243 4244 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 4245 Hi = DAG.getConstant(0, NVT); 4246 break; 4247 } 4248 4249 case ISD::CTTZ: { 4250 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 4251 ExpandOp(Node->getOperand(0), Lo, Hi); 4252 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 4253 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 4254 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 4255 ISD::SETNE); 4256 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 4257 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 4258 4259 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 4260 Hi = DAG.getConstant(0, NVT); 4261 break; 4262 } 4263 4264 case ISD::VAARG: { 4265 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4266 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4267 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 4268 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 4269 4270 // Remember that we legalized the chain. 4271 Hi = LegalizeOp(Hi); 4272 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 4273 if (!TLI.isLittleEndian()) 4274 std::swap(Lo, Hi); 4275 break; 4276 } 4277 4278 case ISD::LOAD: { 4279 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4280 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4281 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 4282 4283 // Increment the pointer to the other half. 4284 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 4285 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4286 getIntPtrConstant(IncrementSize)); 4287 // FIXME: This creates a bogus srcvalue! 4288 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 4289 4290 // Build a factor node to remember that this load is independent of the 4291 // other one. 4292 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 4293 Hi.getValue(1)); 4294 4295 // Remember that we legalized the chain. 4296 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 4297 if (!TLI.isLittleEndian()) 4298 std::swap(Lo, Hi); 4299 break; 4300 } 4301 case ISD::AND: 4302 case ISD::OR: 4303 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 4304 SDOperand LL, LH, RL, RH; 4305 ExpandOp(Node->getOperand(0), LL, LH); 4306 ExpandOp(Node->getOperand(1), RL, RH); 4307 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 4308 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 4309 break; 4310 } 4311 case ISD::SELECT: { 4312 SDOperand LL, LH, RL, RH; 4313 ExpandOp(Node->getOperand(1), LL, LH); 4314 ExpandOp(Node->getOperand(2), RL, RH); 4315 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 4316 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 4317 break; 4318 } 4319 case ISD::SELECT_CC: { 4320 SDOperand TL, TH, FL, FH; 4321 ExpandOp(Node->getOperand(2), TL, TH); 4322 ExpandOp(Node->getOperand(3), FL, FH); 4323 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4324 Node->getOperand(1), TL, FL, Node->getOperand(4)); 4325 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4326 Node->getOperand(1), TH, FH, Node->getOperand(4)); 4327 break; 4328 } 4329 case ISD::SEXTLOAD: { 4330 SDOperand Chain = Node->getOperand(0); 4331 SDOperand Ptr = Node->getOperand(1); 4332 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4333 4334 if (EVT == NVT) 4335 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 4336 else 4337 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 4338 EVT); 4339 4340 // Remember that we legalized the chain. 4341 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4342 4343 // The high part is obtained by SRA'ing all but one of the bits of the lo 4344 // part. 4345 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4346 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 4347 TLI.getShiftAmountTy())); 4348 break; 4349 } 4350 case ISD::ZEXTLOAD: { 4351 SDOperand Chain = Node->getOperand(0); 4352 SDOperand Ptr = Node->getOperand(1); 4353 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4354 4355 if (EVT == NVT) 4356 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 4357 else 4358 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 4359 EVT); 4360 4361 // Remember that we legalized the chain. 4362 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4363 4364 // The high part is just a zero. 4365 Hi = DAG.getConstant(0, NVT); 4366 break; 4367 } 4368 case ISD::EXTLOAD: { 4369 SDOperand Chain = Node->getOperand(0); 4370 SDOperand Ptr = Node->getOperand(1); 4371 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 4372 4373 if (EVT == NVT) 4374 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 4375 else 4376 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 4377 EVT); 4378 4379 // Remember that we legalized the chain. 4380 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 4381 4382 // The high part is undefined. 4383 Hi = DAG.getNode(ISD::UNDEF, NVT); 4384 break; 4385 } 4386 case ISD::ANY_EXTEND: 4387 // The low part is any extension of the input (which degenerates to a copy). 4388 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 4389 // The high part is undefined. 4390 Hi = DAG.getNode(ISD::UNDEF, NVT); 4391 break; 4392 case ISD::SIGN_EXTEND: { 4393 // The low part is just a sign extension of the input (which degenerates to 4394 // a copy). 4395 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 4396 4397 // The high part is obtained by SRA'ing all but one of the bits of the lo 4398 // part. 4399 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 4400 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 4401 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 4402 break; 4403 } 4404 case ISD::ZERO_EXTEND: 4405 // The low part is just a zero extension of the input (which degenerates to 4406 // a copy). 4407 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4408 4409 // The high part is just a zero. 4410 Hi = DAG.getConstant(0, NVT); 4411 break; 4412 4413 case ISD::BIT_CONVERT: { 4414 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0), 4415 Node->getOperand(0)); 4416 ExpandOp(Tmp, Lo, Hi); 4417 break; 4418 } 4419 4420 case ISD::READCYCLECOUNTER: 4421 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 4422 TargetLowering::Custom && 4423 "Must custom expand ReadCycleCounter"); 4424 Lo = TLI.LowerOperation(Op, DAG); 4425 assert(Lo.Val && "Node must be custom expanded!"); 4426 Hi = Lo.getValue(1); 4427 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 4428 LegalizeOp(Lo.getValue(2))); 4429 break; 4430 4431 // These operators cannot be expanded directly, emit them as calls to 4432 // library functions. 4433 case ISD::FP_TO_SINT: 4434 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 4435 SDOperand Op; 4436 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4437 case Expand: assert(0 && "cannot expand FP!"); 4438 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 4439 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 4440 } 4441 4442 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 4443 4444 // Now that the custom expander is done, expand the result, which is still 4445 // VT. 4446 if (Op.Val) { 4447 ExpandOp(Op, Lo, Hi); 4448 break; 4449 } 4450 } 4451 4452 if (Node->getOperand(0).getValueType() == MVT::f32) 4453 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 4454 else 4455 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 4456 break; 4457 4458 case ISD::FP_TO_UINT: 4459 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 4460 SDOperand Op; 4461 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4462 case Expand: assert(0 && "cannot expand FP!"); 4463 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 4464 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 4465 } 4466 4467 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 4468 4469 // Now that the custom expander is done, expand the result. 4470 if (Op.Val) { 4471 ExpandOp(Op, Lo, Hi); 4472 break; 4473 } 4474 } 4475 4476 if (Node->getOperand(0).getValueType() == MVT::f32) 4477 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 4478 else 4479 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 4480 break; 4481 4482 case ISD::SHL: { 4483 // If the target wants custom lowering, do so. 4484 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4485 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 4486 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 4487 Op = TLI.LowerOperation(Op, DAG); 4488 if (Op.Val) { 4489 // Now that the custom expander is done, expand the result, which is 4490 // still VT. 4491 ExpandOp(Op, Lo, Hi); 4492 break; 4493 } 4494 } 4495 4496 // If we can emit an efficient shift operation, do so now. 4497 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4498 break; 4499 4500 // If this target supports SHL_PARTS, use it. 4501 TargetLowering::LegalizeAction Action = 4502 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 4503 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4504 Action == TargetLowering::Custom) { 4505 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4506 break; 4507 } 4508 4509 // Otherwise, emit a libcall. 4510 Lo = ExpandLibCall("__ashldi3", Node, Hi); 4511 break; 4512 } 4513 4514 case ISD::SRA: { 4515 // If the target wants custom lowering, do so. 4516 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4517 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 4518 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 4519 Op = TLI.LowerOperation(Op, DAG); 4520 if (Op.Val) { 4521 // Now that the custom expander is done, expand the result, which is 4522 // still VT. 4523 ExpandOp(Op, Lo, Hi); 4524 break; 4525 } 4526 } 4527 4528 // If we can emit an efficient shift operation, do so now. 4529 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4530 break; 4531 4532 // If this target supports SRA_PARTS, use it. 4533 TargetLowering::LegalizeAction Action = 4534 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 4535 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4536 Action == TargetLowering::Custom) { 4537 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4538 break; 4539 } 4540 4541 // Otherwise, emit a libcall. 4542 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 4543 break; 4544 } 4545 4546 case ISD::SRL: { 4547 // If the target wants custom lowering, do so. 4548 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 4549 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 4550 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 4551 Op = TLI.LowerOperation(Op, DAG); 4552 if (Op.Val) { 4553 // Now that the custom expander is done, expand the result, which is 4554 // still VT. 4555 ExpandOp(Op, Lo, Hi); 4556 break; 4557 } 4558 } 4559 4560 // If we can emit an efficient shift operation, do so now. 4561 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 4562 break; 4563 4564 // If this target supports SRL_PARTS, use it. 4565 TargetLowering::LegalizeAction Action = 4566 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 4567 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 4568 Action == TargetLowering::Custom) { 4569 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 4570 break; 4571 } 4572 4573 // Otherwise, emit a libcall. 4574 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 4575 break; 4576 } 4577 4578 case ISD::ADD: 4579 case ISD::SUB: { 4580 // If the target wants to custom expand this, let them. 4581 if (TLI.getOperationAction(Node->getOpcode(), VT) == 4582 TargetLowering::Custom) { 4583 Op = TLI.LowerOperation(Op, DAG); 4584 if (Op.Val) { 4585 ExpandOp(Op, Lo, Hi); 4586 break; 4587 } 4588 } 4589 4590 // Expand the subcomponents. 4591 SDOperand LHSL, LHSH, RHSL, RHSH; 4592 ExpandOp(Node->getOperand(0), LHSL, LHSH); 4593 ExpandOp(Node->getOperand(1), RHSL, RHSH); 4594 std::vector<MVT::ValueType> VTs; 4595 std::vector<SDOperand> LoOps, HiOps; 4596 VTs.push_back(LHSL.getValueType()); 4597 VTs.push_back(MVT::Flag); 4598 LoOps.push_back(LHSL); 4599 LoOps.push_back(RHSL); 4600 HiOps.push_back(LHSH); 4601 HiOps.push_back(RHSH); 4602 if (Node->getOpcode() == ISD::ADD) { 4603 Lo = DAG.getNode(ISD::ADDC, VTs, LoOps); 4604 HiOps.push_back(Lo.getValue(1)); 4605 Hi = DAG.getNode(ISD::ADDE, VTs, HiOps); 4606 } else { 4607 Lo = DAG.getNode(ISD::SUBC, VTs, LoOps); 4608 HiOps.push_back(Lo.getValue(1)); 4609 Hi = DAG.getNode(ISD::SUBE, VTs, HiOps); 4610 } 4611 break; 4612 } 4613 case ISD::MUL: { 4614 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 4615 SDOperand LL, LH, RL, RH; 4616 ExpandOp(Node->getOperand(0), LL, LH); 4617 ExpandOp(Node->getOperand(1), RL, RH); 4618 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 4619 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 4620 // extended the sign bit of the low half through the upper half, and if so 4621 // emit a MULHS instead of the alternate sequence that is valid for any 4622 // i64 x i64 multiply. 4623 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 4624 // is RH an extension of the sign bit of RL? 4625 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 4626 RH.getOperand(1).getOpcode() == ISD::Constant && 4627 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 4628 // is LH an extension of the sign bit of LL? 4629 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 4630 LH.getOperand(1).getOpcode() == ISD::Constant && 4631 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 4632 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 4633 } else { 4634 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 4635 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 4636 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 4637 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 4638 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 4639 } 4640 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 4641 } else { 4642 Lo = ExpandLibCall("__muldi3" , Node, Hi); 4643 } 4644 break; 4645 } 4646 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 4647 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 4648 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 4649 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 4650 } 4651 4652 // Make sure the resultant values have been legalized themselves, unless this 4653 // is a type that requires multi-step expansion. 4654 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 4655 Lo = LegalizeOp(Lo); 4656 Hi = LegalizeOp(Hi); 4657 } 4658 4659 // Remember in a map if the values will be reused later. 4660 bool isNew = 4661 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 4662 assert(isNew && "Value already expanded?!?"); 4663} 4664 4665/// SplitVectorOp - Given an operand of MVT::Vector type, break it down into 4666/// two smaller values of MVT::Vector type. 4667void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 4668 SDOperand &Hi) { 4669 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!"); 4670 SDNode *Node = Op.Val; 4671 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue(); 4672 assert(NumElements > 1 && "Cannot split a single element vector!"); 4673 unsigned NewNumElts = NumElements/2; 4674 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32); 4675 SDOperand TypeNode = *(Node->op_end()-1); 4676 4677 // See if we already split it. 4678 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 4679 = SplitNodes.find(Op); 4680 if (I != SplitNodes.end()) { 4681 Lo = I->second.first; 4682 Hi = I->second.second; 4683 return; 4684 } 4685 4686 switch (Node->getOpcode()) { 4687 default: Node->dump(); assert(0 && "Unhandled operation in SplitVectorOp!"); 4688 case ISD::VBUILD_VECTOR: { 4689 std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts); 4690 LoOps.push_back(NewNumEltsNode); 4691 LoOps.push_back(TypeNode); 4692 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps); 4693 4694 std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2); 4695 HiOps.push_back(NewNumEltsNode); 4696 HiOps.push_back(TypeNode); 4697 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps); 4698 break; 4699 } 4700 case ISD::VADD: 4701 case ISD::VSUB: 4702 case ISD::VMUL: 4703 case ISD::VSDIV: 4704 case ISD::VUDIV: 4705 case ISD::VAND: 4706 case ISD::VOR: 4707 case ISD::VXOR: { 4708 SDOperand LL, LH, RL, RH; 4709 SplitVectorOp(Node->getOperand(0), LL, LH); 4710 SplitVectorOp(Node->getOperand(1), RL, RH); 4711 4712 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, 4713 NewNumEltsNode, TypeNode); 4714 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, 4715 NewNumEltsNode, TypeNode); 4716 break; 4717 } 4718 case ISD::VLOAD: { 4719 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 4720 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 4721 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 4722 4723 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 4724 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8; 4725 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4726 getIntPtrConstant(IncrementSize)); 4727 // FIXME: This creates a bogus srcvalue! 4728 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2)); 4729 4730 // Build a factor node to remember that this load is independent of the 4731 // other one. 4732 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 4733 Hi.getValue(1)); 4734 4735 // Remember that we legalized the chain. 4736 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 4737 break; 4738 } 4739 case ISD::VBIT_CONVERT: { 4740 // We know the result is a vector. The input may be either a vector or a 4741 // scalar value. 4742 if (Op.getOperand(0).getValueType() != MVT::Vector) { 4743 // Lower to a store/load. FIXME: this could be improved probably. 4744 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType()); 4745 4746 SDOperand St = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 4747 Op.getOperand(0), Ptr, DAG.getSrcValue(0)); 4748 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT(); 4749 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0)); 4750 SplitVectorOp(St, Lo, Hi); 4751 } else { 4752 // If the input is a vector type, we have to either scalarize it, pack it 4753 // or convert it based on whether the input vector type is legal. 4754 SDNode *InVal = Node->getOperand(0).Val; 4755 unsigned NumElems = 4756 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 4757 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 4758 4759 // If the input is from a single element vector, scalarize the vector, 4760 // then treat like a scalar. 4761 if (NumElems == 1) { 4762 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT); 4763 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar, 4764 Op.getOperand(1), Op.getOperand(2)); 4765 SplitVectorOp(Scalar, Lo, Hi); 4766 } else { 4767 // Split the input vector. 4768 SplitVectorOp(Op.getOperand(0), Lo, Hi); 4769 4770 // Convert each of the pieces now. 4771 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo, 4772 NewNumEltsNode, TypeNode); 4773 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi, 4774 NewNumEltsNode, TypeNode); 4775 } 4776 break; 4777 } 4778 } 4779 } 4780 4781 // Remember in a map if the values will be reused later. 4782 bool isNew = 4783 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 4784 assert(isNew && "Value already expanded?!?"); 4785} 4786 4787 4788/// PackVectorOp - Given an operand of MVT::Vector type, convert it into the 4789/// equivalent operation that returns a scalar (e.g. F32) or packed value 4790/// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right 4791/// type for the result. 4792SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, 4793 MVT::ValueType NewVT) { 4794 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!"); 4795 SDNode *Node = Op.Val; 4796 4797 // See if we already packed it. 4798 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op); 4799 if (I != PackedNodes.end()) return I->second; 4800 4801 SDOperand Result; 4802 switch (Node->getOpcode()) { 4803 default: 4804 Node->dump(); std::cerr << "\n"; 4805 assert(0 && "Unknown vector operation in PackVectorOp!"); 4806 case ISD::VADD: 4807 case ISD::VSUB: 4808 case ISD::VMUL: 4809 case ISD::VSDIV: 4810 case ISD::VUDIV: 4811 case ISD::VAND: 4812 case ISD::VOR: 4813 case ISD::VXOR: 4814 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT), 4815 NewVT, 4816 PackVectorOp(Node->getOperand(0), NewVT), 4817 PackVectorOp(Node->getOperand(1), NewVT)); 4818 break; 4819 case ISD::VLOAD: { 4820 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 4821 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 4822 4823 Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2)); 4824 4825 // Remember that we legalized the chain. 4826 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4827 break; 4828 } 4829 case ISD::VBUILD_VECTOR: 4830 if (Node->getOperand(0).getValueType() == NewVT) { 4831 // Returning a scalar? 4832 Result = Node->getOperand(0); 4833 } else { 4834 // Returning a BUILD_VECTOR? 4835 4836 // If all elements of the build_vector are undefs, return an undef. 4837 bool AllUndef = true; 4838 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i) 4839 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) { 4840 AllUndef = false; 4841 break; 4842 } 4843 if (AllUndef) { 4844 Result = DAG.getNode(ISD::UNDEF, NewVT); 4845 } else { 4846 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2); 4847 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops); 4848 } 4849 } 4850 break; 4851 case ISD::VINSERT_VECTOR_ELT: 4852 if (!MVT::isVector(NewVT)) { 4853 // Returning a scalar? Must be the inserted element. 4854 Result = Node->getOperand(1); 4855 } else { 4856 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, 4857 PackVectorOp(Node->getOperand(0), NewVT), 4858 Node->getOperand(1), Node->getOperand(2)); 4859 } 4860 break; 4861 case ISD::VVECTOR_SHUFFLE: 4862 if (!MVT::isVector(NewVT)) { 4863 // Returning a scalar? Figure out if it is the LHS or RHS and return it. 4864 SDOperand EltNum = Node->getOperand(2).getOperand(0); 4865 if (cast<ConstantSDNode>(EltNum)->getValue()) 4866 Result = PackVectorOp(Node->getOperand(1), NewVT); 4867 else 4868 Result = PackVectorOp(Node->getOperand(0), NewVT); 4869 } else { 4870 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index 4871 // vector from a VBUILD_VECTOR to a BUILD_VECTOR. 4872 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(), 4873 Node->getOperand(2).Val->op_end()-2); 4874 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size()); 4875 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, BuildVecIdx); 4876 4877 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, 4878 PackVectorOp(Node->getOperand(0), NewVT), 4879 PackVectorOp(Node->getOperand(1), NewVT), BV); 4880 } 4881 break; 4882 case ISD::VBIT_CONVERT: 4883 if (Op.getOperand(0).getValueType() != MVT::Vector) 4884 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 4885 else { 4886 // If the input is a vector type, we have to either scalarize it, pack it 4887 // or convert it based on whether the input vector type is legal. 4888 SDNode *InVal = Node->getOperand(0).Val; 4889 unsigned NumElems = 4890 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue(); 4891 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT(); 4892 4893 // Figure out if there is a Packed type corresponding to this Vector 4894 // type. If so, convert to the packed type. 4895 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 4896 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) { 4897 // Turn this into a bit convert of the packed input. 4898 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 4899 PackVectorOp(Node->getOperand(0), TVT)); 4900 break; 4901 } else if (NumElems == 1) { 4902 // Turn this into a bit convert of the scalar input. 4903 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, 4904 PackVectorOp(Node->getOperand(0), EVT)); 4905 break; 4906 } else { 4907 // FIXME: UNIMP! 4908 assert(0 && "Cast from unsupported vector type not implemented yet!"); 4909 } 4910 } 4911 break; 4912 case ISD::VSELECT: 4913 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 4914 PackVectorOp(Op.getOperand(1), NewVT), 4915 PackVectorOp(Op.getOperand(2), NewVT)); 4916 break; 4917 } 4918 4919 if (TLI.isTypeLegal(NewVT)) 4920 Result = LegalizeOp(Result); 4921 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second; 4922 assert(isNew && "Value already packed?"); 4923 return Result; 4924} 4925 4926 4927// SelectionDAG::Legalize - This is the entry point for the file. 4928// 4929void SelectionDAG::Legalize() { 4930 if (ViewLegalizeDAGs) viewGraph(); 4931 4932 /// run - This is the main entry point to this class. 4933 /// 4934 SelectionDAGLegalize(*this).LegalizeDAG(); 4935} 4936 4937