LegalizeDAG.cpp revision ed7b5babfbdc708c564266052ad3b0ce0a5726c5
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/Support/MathExtras.h" 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/Target/TargetData.h" 20#include "llvm/Target/TargetOptions.h" 21#include "llvm/CallingConv.h" 22#include "llvm/Constants.h" 23#include <iostream> 24#include <set> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 29/// hacks on it until the target machine can handle it. This involves 30/// eliminating value sizes the machine cannot handle (promoting small sizes to 31/// large sizes or splitting up large values into small values) as well as 32/// eliminating operations the machine cannot handle. 33/// 34/// This code also does a small amount of optimization and recognition of idioms 35/// as part of its processing. For example, if a target does not support a 36/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 37/// will attempt merge setcc and brc instructions into brcc's. 38/// 39namespace { 40class SelectionDAGLegalize { 41 TargetLowering &TLI; 42 SelectionDAG &DAG; 43 44 /// LegalizeAction - This enum indicates what action we should take for each 45 /// value type the can occur in the program. 46 enum LegalizeAction { 47 Legal, // The target natively supports this value type. 48 Promote, // This should be promoted to the next larger type. 49 Expand, // This integer type should be broken into smaller pieces. 50 }; 51 52 /// ValueTypeActions - This is a bitvector that contains two bits for each 53 /// value type, where the two bits correspond to the LegalizeAction enum. 54 /// This can be queried with "getTypeAction(VT)". 55 unsigned long long ValueTypeActions; 56 57 /// NeedsAnotherIteration - This is set when we expand a large integer 58 /// operation into smaller integer operations, but the smaller operations are 59 /// not set. This occurs only rarely in practice, for targets that don't have 60 /// 32-bit or larger integer registers. 61 bool NeedsAnotherIteration; 62 63 /// LegalizedNodes - For nodes that are of legal width, and that have more 64 /// than one use, this map indicates what regularized operand to use. This 65 /// allows us to avoid legalizing the same thing more than once. 66 std::map<SDOperand, SDOperand> LegalizedNodes; 67 68 /// PromotedNodes - For nodes that are below legal width, and that have more 69 /// than one use, this map indicates what promoted value to use. This allows 70 /// us to avoid promoting the same thing more than once. 71 std::map<SDOperand, SDOperand> PromotedNodes; 72 73 /// ExpandedNodes - For nodes that need to be expanded, and which have more 74 /// than one use, this map indicates which which operands are the expanded 75 /// version of the input. This allows us to avoid expanding the same node 76 /// more than once. 77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 78 79 void AddLegalizedOperand(SDOperand From, SDOperand To) { 80 LegalizedNodes.insert(std::make_pair(From, To)); 81 // If someone requests legalization of the new node, return itself. 82 if (From != To) 83 LegalizedNodes.insert(std::make_pair(To, To)); 84 } 85 void AddPromotedOperand(SDOperand From, SDOperand To) { 86 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 87 assert(isNew && "Got into the map somehow?"); 88 // If someone requests legalization of the new node, return itself. 89 LegalizedNodes.insert(std::make_pair(To, To)); 90 } 91 92public: 93 94 SelectionDAGLegalize(SelectionDAG &DAG); 95 96 /// Run - While there is still lowering to do, perform a pass over the DAG. 97 /// Most regularization can be done in a single pass, but targets that require 98 /// large values to be split into registers multiple times (e.g. i64 -> 4x 99 /// i16) require iteration for these values (the first iteration will demote 100 /// to i32, the second will demote to i16). 101 void Run() { 102 do { 103 NeedsAnotherIteration = false; 104 LegalizeDAG(); 105 } while (NeedsAnotherIteration); 106 } 107 108 /// getTypeAction - Return how we should legalize values of this type, either 109 /// it is already legal or we need to expand it into multiple registers of 110 /// smaller integer type, or we need to promote it to a larger type. 111 LegalizeAction getTypeAction(MVT::ValueType VT) const { 112 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3); 113 } 114 115 /// isTypeLegal - Return true if this type is legal on this target. 116 /// 117 bool isTypeLegal(MVT::ValueType VT) const { 118 return getTypeAction(VT) == Legal; 119 } 120 121private: 122 void LegalizeDAG(); 123 124 SDOperand LegalizeOp(SDOperand O); 125 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 126 SDOperand PromoteOp(SDOperand O); 127 128 SDOperand ExpandLibCall(const char *Name, SDNode *Node, 129 SDOperand &Hi); 130 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 131 SDOperand Source); 132 133 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 134 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 135 SDOperand LegalOp, 136 MVT::ValueType DestVT); 137 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 138 bool isSigned); 139 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 140 bool isSigned); 141 142 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 143 SDOperand &Lo, SDOperand &Hi); 144 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 145 SDOperand &Lo, SDOperand &Hi); 146 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 147 SDOperand &Lo, SDOperand &Hi); 148 149 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain); 150 151 SDOperand getIntPtrConstant(uint64_t Val) { 152 return DAG.getConstant(Val, TLI.getPointerTy()); 153 } 154}; 155} 156 157static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) { 158 switch (VecOp) { 159 default: assert(0 && "Don't know how to scalarize this opcode!"); 160 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD; 161 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB; 162 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL; 163 } 164} 165 166SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 167 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 168 ValueTypeActions(TLI.getValueTypeActions()) { 169 assert(MVT::LAST_VALUETYPE <= 32 && 170 "Too many value types for ValueTypeActions to hold!"); 171} 172 173/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 174/// INT_TO_FP operation of the specified operand when the target requests that 175/// we expand it. At this point, we know that the result and operand types are 176/// legal for the target. 177SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 178 SDOperand Op0, 179 MVT::ValueType DestVT) { 180 if (Op0.getValueType() == MVT::i32) { 181 // simple 32-bit [signed|unsigned] integer to float/double expansion 182 183 // get the stack frame index of a 8 byte buffer 184 MachineFunction &MF = DAG.getMachineFunction(); 185 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); 186 // get address of 8 byte buffer 187 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 188 // word offset constant for Hi/Lo address computation 189 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 190 // set up Hi and Lo (into buffer) address based on endian 191 SDOperand Hi, Lo; 192 if (TLI.isLittleEndian()) { 193 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 194 Lo = StackSlot; 195 } else { 196 Hi = StackSlot; 197 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff); 198 } 199 // if signed map to unsigned space 200 SDOperand Op0Mapped; 201 if (isSigned) { 202 // constant used to invert sign bit (signed to unsigned mapping) 203 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 204 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 205 } else { 206 Op0Mapped = Op0; 207 } 208 // store the lo of the constructed double - based on integer input 209 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 210 Op0Mapped, Lo, DAG.getSrcValue(NULL)); 211 // initial hi portion of constructed double 212 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 213 // store the hi of the constructed double - biased exponent 214 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1, 215 InitialHi, Hi, DAG.getSrcValue(NULL)); 216 // load the constructed double 217 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, 218 DAG.getSrcValue(NULL)); 219 // FP constant to bias correct the final result 220 SDOperand Bias = DAG.getConstantFP(isSigned ? 221 BitsToDouble(0x4330000080000000ULL) 222 : BitsToDouble(0x4330000000000000ULL), 223 MVT::f64); 224 // subtract the bias 225 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 226 // final result 227 SDOperand Result; 228 // handle final rounding 229 if (DestVT == MVT::f64) { 230 // do nothing 231 Result = Sub; 232 } else { 233 // if f32 then cast to f32 234 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); 235 } 236 return LegalizeOp(Result); 237 } 238 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 239 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 240 241 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 242 DAG.getConstant(0, Op0.getValueType()), 243 ISD::SETLT); 244 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 245 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 246 SignSet, Four, Zero); 247 248 // If the sign bit of the integer is set, the large number will be treated 249 // as a negative number. To counteract this, the dynamic code adds an 250 // offset depending on the data type. 251 uint64_t FF; 252 switch (Op0.getValueType()) { 253 default: assert(0 && "Unsupported integer type!"); 254 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 255 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 256 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 257 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 258 } 259 if (TLI.isLittleEndian()) FF <<= 32; 260 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 261 262 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 263 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 264 SDOperand FudgeInReg; 265 if (DestVT == MVT::f32) 266 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 267 DAG.getSrcValue(NULL)); 268 else { 269 assert(DestVT == MVT::f64 && "Unexpected conversion"); 270 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, 271 DAG.getEntryNode(), CPIdx, 272 DAG.getSrcValue(NULL), MVT::f32)); 273 } 274 275 return LegalizeOp(DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg)); 276} 277 278/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 279/// *INT_TO_FP operation of the specified operand when the target requests that 280/// we promote it. At this point, we know that the result and operand types are 281/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 282/// operation that takes a larger input. 283SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 284 MVT::ValueType DestVT, 285 bool isSigned) { 286 // First step, figure out the appropriate *INT_TO_FP operation to use. 287 MVT::ValueType NewInTy = LegalOp.getValueType(); 288 289 unsigned OpToUse = 0; 290 291 // Scan for the appropriate larger type to use. 292 while (1) { 293 NewInTy = (MVT::ValueType)(NewInTy+1); 294 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 295 296 // If the target supports SINT_TO_FP of this type, use it. 297 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 298 default: break; 299 case TargetLowering::Legal: 300 if (!TLI.isTypeLegal(NewInTy)) 301 break; // Can't use this datatype. 302 // FALL THROUGH. 303 case TargetLowering::Custom: 304 OpToUse = ISD::SINT_TO_FP; 305 break; 306 } 307 if (OpToUse) break; 308 if (isSigned) continue; 309 310 // If the target supports UINT_TO_FP of this type, use it. 311 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 312 default: break; 313 case TargetLowering::Legal: 314 if (!TLI.isTypeLegal(NewInTy)) 315 break; // Can't use this datatype. 316 // FALL THROUGH. 317 case TargetLowering::Custom: 318 OpToUse = ISD::UINT_TO_FP; 319 break; 320 } 321 if (OpToUse) break; 322 323 // Otherwise, try a larger type. 324 } 325 326 // Okay, we found the operation and type to use. Zero extend our input to the 327 // desired type then run the operation on it. 328 SDOperand N = DAG.getNode(OpToUse, DestVT, 329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 330 NewInTy, LegalOp)); 331 // Make sure to legalize any nodes we create here. 332 return LegalizeOp(N); 333} 334 335/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 336/// FP_TO_*INT operation of the specified operand when the target requests that 337/// we promote it. At this point, we know that the result and operand types are 338/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 339/// operation that returns a larger result. 340SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 341 MVT::ValueType DestVT, 342 bool isSigned) { 343 // First step, figure out the appropriate FP_TO*INT operation to use. 344 MVT::ValueType NewOutTy = DestVT; 345 346 unsigned OpToUse = 0; 347 348 // Scan for the appropriate larger type to use. 349 while (1) { 350 NewOutTy = (MVT::ValueType)(NewOutTy+1); 351 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 352 353 // If the target supports FP_TO_SINT returning this type, use it. 354 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 355 default: break; 356 case TargetLowering::Legal: 357 if (!TLI.isTypeLegal(NewOutTy)) 358 break; // Can't use this datatype. 359 // FALL THROUGH. 360 case TargetLowering::Custom: 361 OpToUse = ISD::FP_TO_SINT; 362 break; 363 } 364 if (OpToUse) break; 365 366 // If the target supports FP_TO_UINT of this type, use it. 367 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 368 default: break; 369 case TargetLowering::Legal: 370 if (!TLI.isTypeLegal(NewOutTy)) 371 break; // Can't use this datatype. 372 // FALL THROUGH. 373 case TargetLowering::Custom: 374 OpToUse = ISD::FP_TO_UINT; 375 break; 376 } 377 if (OpToUse) break; 378 379 // Otherwise, try a larger type. 380 } 381 382 // Okay, we found the operation and type to use. Truncate the result of the 383 // extended FP_TO_*INT operation to the desired size. 384 SDOperand N = DAG.getNode(ISD::TRUNCATE, DestVT, 385 DAG.getNode(OpToUse, NewOutTy, LegalOp)); 386 // Make sure to legalize any nodes we create here in the next pass. 387 return LegalizeOp(N); 388} 389 390/// ComputeTopDownOrdering - Add the specified node to the Order list if it has 391/// not been visited yet and if all of its operands have already been visited. 392static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order, 393 std::map<SDNode*, unsigned> &Visited) { 394 if (++Visited[N] != N->getNumOperands()) 395 return; // Haven't visited all operands yet 396 397 Order.push_back(N); 398 399 if (N->hasOneUse()) { // Tail recurse in common case. 400 ComputeTopDownOrdering(*N->use_begin(), Order, Visited); 401 return; 402 } 403 404 // Now that we have N in, add anything that uses it if all of their operands 405 // are now done. 406 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI) 407 ComputeTopDownOrdering(*UI, Order, Visited); 408} 409 410 411void SelectionDAGLegalize::LegalizeDAG() { 412 // The legalize process is inherently a bottom-up recursive process (users 413 // legalize their uses before themselves). Given infinite stack space, we 414 // could just start legalizing on the root and traverse the whole graph. In 415 // practice however, this causes us to run out of stack space on large basic 416 // blocks. To avoid this problem, compute an ordering of the nodes where each 417 // node is only legalized after all of its operands are legalized. 418 std::map<SDNode*, unsigned> Visited; 419 std::vector<SDNode*> Order; 420 421 // Compute ordering from all of the leaves in the graphs, those (like the 422 // entry node) that have no operands. 423 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 424 E = DAG.allnodes_end(); I != E; ++I) { 425 if (I->getNumOperands() == 0) { 426 Visited[I] = 0 - 1U; 427 ComputeTopDownOrdering(I, Order, Visited); 428 } 429 } 430 431 assert(Order.size() == Visited.size() && 432 Order.size() == 433 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 434 "Error: DAG is cyclic!"); 435 Visited.clear(); 436 437 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 438 SDNode *N = Order[i]; 439 switch (getTypeAction(N->getValueType(0))) { 440 default: assert(0 && "Bad type action!"); 441 case Legal: 442 LegalizeOp(SDOperand(N, 0)); 443 break; 444 case Promote: 445 PromoteOp(SDOperand(N, 0)); 446 break; 447 case Expand: { 448 SDOperand X, Y; 449 ExpandOp(SDOperand(N, 0), X, Y); 450 break; 451 } 452 } 453 } 454 455 // Finally, it's possible the root changed. Get the new root. 456 SDOperand OldRoot = DAG.getRoot(); 457 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 458 DAG.setRoot(LegalizedNodes[OldRoot]); 459 460 ExpandedNodes.clear(); 461 LegalizedNodes.clear(); 462 PromotedNodes.clear(); 463 464 // Remove dead nodes now. 465 DAG.RemoveDeadNodes(OldRoot.Val); 466} 467 468SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 469 assert(isTypeLegal(Op.getValueType()) && 470 "Caller should expand or promote operands that are not legal!"); 471 SDNode *Node = Op.Val; 472 473 // If this operation defines any values that cannot be represented in a 474 // register on this target, make sure to expand or promote them. 475 if (Node->getNumValues() > 1) { 476 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 477 switch (getTypeAction(Node->getValueType(i))) { 478 case Legal: break; // Nothing to do. 479 case Expand: { 480 SDOperand T1, T2; 481 ExpandOp(Op.getValue(i), T1, T2); 482 assert(LegalizedNodes.count(Op) && 483 "Expansion didn't add legal operands!"); 484 return LegalizedNodes[Op]; 485 } 486 case Promote: 487 PromoteOp(Op.getValue(i)); 488 assert(LegalizedNodes.count(Op) && 489 "Expansion didn't add legal operands!"); 490 return LegalizedNodes[Op]; 491 } 492 } 493 494 // Note that LegalizeOp may be reentered even from single-use nodes, which 495 // means that we always must cache transformed nodes. 496 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 497 if (I != LegalizedNodes.end()) return I->second; 498 499 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 500 501 SDOperand Result = Op; 502 503 switch (Node->getOpcode()) { 504 default: 505 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 506 // If this is a target node, legalize it by legalizing the operands then 507 // passing it through. 508 std::vector<SDOperand> Ops; 509 bool Changed = false; 510 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 511 Ops.push_back(LegalizeOp(Node->getOperand(i))); 512 Changed = Changed || Node->getOperand(i) != Ops.back(); 513 } 514 if (Changed) 515 if (Node->getNumValues() == 1) 516 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops); 517 else { 518 std::vector<MVT::ValueType> VTs(Node->value_begin(), 519 Node->value_end()); 520 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 521 } 522 523 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 524 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 525 return Result.getValue(Op.ResNo); 526 } 527 // Otherwise this is an unhandled builtin node. splat. 528 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 529 assert(0 && "Do not know how to legalize this operator!"); 530 abort(); 531 case ISD::EntryToken: 532 case ISD::FrameIndex: 533 case ISD::TargetFrameIndex: 534 case ISD::Register: 535 case ISD::TargetConstant: 536 case ISD::TargetConstantPool: 537 case ISD::GlobalAddress: 538 case ISD::TargetGlobalAddress: 539 case ISD::ExternalSymbol: 540 case ISD::ConstantPool: // Nothing to do. 541 case ISD::BasicBlock: 542 case ISD::CONDCODE: 543 case ISD::VALUETYPE: 544 case ISD::SRCVALUE: 545 case ISD::STRING: 546 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 547 default: assert(0 && "This action is not supported yet!"); 548 case TargetLowering::Custom: { 549 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 550 if (Tmp.Val) { 551 Result = LegalizeOp(Tmp); 552 break; 553 } 554 } // FALLTHROUGH if the target doesn't want to lower this op after all. 555 case TargetLowering::Legal: 556 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!"); 557 break; 558 } 559 break; 560 case ISD::AssertSext: 561 case ISD::AssertZext: 562 Tmp1 = LegalizeOp(Node->getOperand(0)); 563 if (Tmp1 != Node->getOperand(0)) 564 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 565 Node->getOperand(1)); 566 break; 567 case ISD::MERGE_VALUES: 568 return LegalizeOp(Node->getOperand(Op.ResNo)); 569 case ISD::CopyFromReg: 570 Tmp1 = LegalizeOp(Node->getOperand(0)); 571 Result = Op.getValue(0); 572 if (Node->getNumValues() == 2) { 573 if (Tmp1 != Node->getOperand(0)) 574 Result = DAG.getCopyFromReg(Tmp1, 575 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 576 Node->getValueType(0)); 577 } else { 578 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 579 if (Node->getNumOperands() == 3) 580 Tmp2 = LegalizeOp(Node->getOperand(2)); 581 if (Tmp1 != Node->getOperand(0) || 582 (Node->getNumOperands() == 3 && Tmp2 != Node->getOperand(2))) 583 Result = DAG.getCopyFromReg(Tmp1, 584 cast<RegisterSDNode>(Node->getOperand(1))->getReg(), 585 Node->getValueType(0), Tmp2); 586 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 587 } 588 // Since CopyFromReg produces two values, make sure to remember that we 589 // legalized both of them. 590 AddLegalizedOperand(Op.getValue(0), Result); 591 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 592 return Result.getValue(Op.ResNo); 593 case ISD::UNDEF: { 594 MVT::ValueType VT = Op.getValueType(); 595 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 596 default: assert(0 && "This action is not supported yet!"); 597 case TargetLowering::Expand: 598 case TargetLowering::Promote: 599 if (MVT::isInteger(VT)) 600 Result = DAG.getConstant(0, VT); 601 else if (MVT::isFloatingPoint(VT)) 602 Result = DAG.getConstantFP(0, VT); 603 else 604 assert(0 && "Unknown value type!"); 605 break; 606 case TargetLowering::Legal: 607 break; 608 } 609 break; 610 } 611 612 case ISD::LOCATION: 613 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 614 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 615 616 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 617 case TargetLowering::Promote: 618 default: assert(0 && "This action is not supported yet!"); 619 case TargetLowering::Expand: { 620 if (TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other)) { 621 MachineDebugInfo &DebugInfo = DAG.getMachineFunction().getDebugInfo(); 622 std::vector<SDOperand> Ops; 623 Ops.push_back(Tmp1); // chain 624 Ops.push_back(Node->getOperand(1)); // line # 625 Ops.push_back(Node->getOperand(2)); // col # 626 const std::string &fname = 627 cast<StringSDNode>(Node->getOperand(3))->getValue(); 628 const std::string &dirname = 629 cast<StringSDNode>(Node->getOperand(4))->getValue(); 630 unsigned id = DebugInfo.RecordSource(fname, dirname); 631 Ops.push_back(DAG.getConstant(id, MVT::i32)); // source file id 632 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops); 633 } else { 634 Result = Tmp1; // chain 635 } 636 Result = LegalizeOp(Result); // Relegalize new nodes. 637 break; 638 } 639 case TargetLowering::Legal: 640 if (Tmp1 != Node->getOperand(0) || 641 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 642 std::vector<SDOperand> Ops; 643 Ops.push_back(Tmp1); 644 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 645 Ops.push_back(Node->getOperand(1)); // line # must be legal. 646 Ops.push_back(Node->getOperand(2)); // col # must be legal. 647 } else { 648 // Otherwise promote them. 649 Ops.push_back(PromoteOp(Node->getOperand(1))); 650 Ops.push_back(PromoteOp(Node->getOperand(2))); 651 } 652 Ops.push_back(Node->getOperand(3)); // filename must be legal. 653 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 654 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops); 655 } 656 break; 657 } 658 break; 659 660 case ISD::DEBUG_LOC: 661 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 662 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 663 case TargetLowering::Promote: 664 case TargetLowering::Expand: 665 default: assert(0 && "This action is not supported yet!"); 666 case TargetLowering::Legal: 667 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 668 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 669 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 670 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 671 672 if (Tmp1 != Node->getOperand(0) || 673 Tmp2 != Node->getOperand(1) || 674 Tmp3 != Node->getOperand(2) || 675 Tmp4 != Node->getOperand(3)) { 676 Result = DAG.getNode(ISD::DEBUG_LOC,MVT::Other, Tmp1, Tmp2, Tmp3, Tmp4); 677 } 678 break; 679 } 680 break; 681 682 case ISD::Constant: 683 // We know we don't need to expand constants here, constants only have one 684 // value and we check that it is fine above. 685 686 // FIXME: Maybe we should handle things like targets that don't support full 687 // 32-bit immediates? 688 break; 689 case ISD::ConstantFP: { 690 // Spill FP immediates to the constant pool if the target cannot directly 691 // codegen them. Targets often have some immediate values that can be 692 // efficiently generated into an FP register without a load. We explicitly 693 // leave these constants as ConstantFP nodes for the target to deal with. 694 695 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 696 697 // Check to see if this FP immediate is already legal. 698 bool isLegal = false; 699 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 700 E = TLI.legal_fpimm_end(); I != E; ++I) 701 if (CFP->isExactlyValue(*I)) { 702 isLegal = true; 703 break; 704 } 705 706 if (!isLegal) { 707 // Otherwise we need to spill the constant to memory. 708 bool Extend = false; 709 710 // If a FP immediate is precise when represented as a float, we put it 711 // into the constant pool as a float, even if it's is statically typed 712 // as a double. 713 MVT::ValueType VT = CFP->getValueType(0); 714 bool isDouble = VT == MVT::f64; 715 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy : 716 Type::FloatTy, CFP->getValue()); 717 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) && 718 // Only do this if the target has a native EXTLOAD instruction from 719 // f32. 720 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) { 721 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy)); 722 VT = MVT::f32; 723 Extend = true; 724 } 725 726 SDOperand CPIdx = 727 LegalizeOp(DAG.getConstantPool(LLVMC, TLI.getPointerTy())); 728 if (Extend) { 729 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 730 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 731 } else { 732 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 733 DAG.getSrcValue(NULL)); 734 } 735 } 736 break; 737 } 738 case ISD::ConstantVec: { 739 // We assume that vector constants are not legal, and will be immediately 740 // spilled to the constant pool. 741 // 742 // FIXME: revisit this when we have some kind of mechanism by which targets 743 // can decided legality of vector constants, of which there may be very 744 // many. 745 // 746 // Create a ConstantPacked, and put it in the constant pool. 747 std::vector<Constant*> CV; 748 MVT::ValueType VT = Node->getValueType(0); 749 for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) { 750 SDOperand OpN = Node->getOperand(I); 751 const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType()); 752 if (MVT::isFloatingPoint(VT)) 753 CV.push_back(ConstantFP::get(OpNTy, 754 cast<ConstantFPSDNode>(OpN)->getValue())); 755 else 756 CV.push_back(ConstantUInt::get(OpNTy, 757 cast<ConstantSDNode>(OpN)->getValue())); 758 } 759 Constant *CP = ConstantPacked::get(CV); 760 SDOperand CPIdx = LegalizeOp(DAG.getConstantPool(CP, TLI.getPointerTy())); 761 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL)); 762 break; 763 } 764 case ISD::TokenFactor: 765 if (Node->getNumOperands() == 2) { 766 bool Changed = false; 767 SDOperand Op0 = LegalizeOp(Node->getOperand(0)); 768 SDOperand Op1 = LegalizeOp(Node->getOperand(1)); 769 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1)) 770 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1); 771 } else { 772 std::vector<SDOperand> Ops; 773 bool Changed = false; 774 // Legalize the operands. 775 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 776 SDOperand Op = Node->getOperand(i); 777 Ops.push_back(LegalizeOp(Op)); 778 Changed |= Ops[i] != Op; 779 } 780 if (Changed) 781 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 782 } 783 break; 784 785 case ISD::CALLSEQ_START: 786 case ISD::CALLSEQ_END: 787 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 788 // Do not try to legalize the target-specific arguments (#1+) 789 Tmp2 = Node->getOperand(0); 790 if (Tmp1 != Tmp2) 791 Node->setAdjCallChain(Tmp1); 792 793 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These 794 // nodes are treated specially and are mutated in place. This makes the dag 795 // legalization process more efficient and also makes libcall insertion 796 // easier. 797 break; 798 case ISD::DYNAMIC_STACKALLOC: 799 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 800 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 801 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 802 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 803 Tmp3 != Node->getOperand(2)) { 804 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 805 std::vector<SDOperand> Ops; 806 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 807 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops); 808 } else 809 Result = Op.getValue(0); 810 811 // Since this op produces two values, make sure to remember that we 812 // legalized both of them. 813 AddLegalizedOperand(SDOperand(Node, 0), Result); 814 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 815 return Result.getValue(Op.ResNo); 816 817 case ISD::TAILCALL: 818 case ISD::CALL: { 819 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 820 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 821 822 bool Changed = false; 823 std::vector<SDOperand> Ops; 824 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 825 Ops.push_back(LegalizeOp(Node->getOperand(i))); 826 Changed |= Ops.back() != Node->getOperand(i); 827 } 828 829 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) { 830 std::vector<MVT::ValueType> RetTyVTs; 831 RetTyVTs.reserve(Node->getNumValues()); 832 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 833 RetTyVTs.push_back(Node->getValueType(i)); 834 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 835 Node->getOpcode() == ISD::TAILCALL), 0); 836 } else { 837 Result = Result.getValue(0); 838 } 839 // Since calls produce multiple values, make sure to remember that we 840 // legalized all of them. 841 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 842 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 843 return Result.getValue(Op.ResNo); 844 } 845 case ISD::BR: 846 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 847 if (Tmp1 != Node->getOperand(0)) 848 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1)); 849 break; 850 851 case ISD::BRCOND: 852 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 853 854 switch (getTypeAction(Node->getOperand(1).getValueType())) { 855 case Expand: assert(0 && "It's impossible to expand bools"); 856 case Legal: 857 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 858 break; 859 case Promote: 860 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 861 break; 862 } 863 864 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 865 default: assert(0 && "This action is not supported yet!"); 866 case TargetLowering::Expand: 867 // Expand brcond's setcc into its constituent parts and create a BR_CC 868 // Node. 869 if (Tmp2.getOpcode() == ISD::SETCC) { 870 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 871 Tmp2.getOperand(0), Tmp2.getOperand(1), 872 Node->getOperand(2)); 873 } else { 874 // Make sure the condition is either zero or one. It may have been 875 // promoted from something else. 876 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 877 878 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 879 DAG.getCondCode(ISD::SETNE), Tmp2, 880 DAG.getConstant(0, Tmp2.getValueType()), 881 Node->getOperand(2)); 882 } 883 Result = LegalizeOp(Result); // Relegalize new nodes. 884 break; 885 case TargetLowering::Custom: { 886 SDOperand Tmp = 887 TLI.LowerOperation(DAG.getNode(ISD::BRCOND, Node->getValueType(0), 888 Tmp1, Tmp2, Node->getOperand(2)), DAG); 889 if (Tmp.Val) { 890 Result = LegalizeOp(Tmp); 891 break; 892 } 893 // FALLTHROUGH if the target thinks it is legal. 894 } 895 case TargetLowering::Legal: 896 // Basic block destination (Op#2) is always legal. 897 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 898 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 899 Node->getOperand(2)); 900 break; 901 } 902 break; 903 case ISD::BR_CC: 904 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 905 if (!isTypeLegal(Node->getOperand(2).getValueType())) { 906 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 907 Node->getOperand(2), // LHS 908 Node->getOperand(3), // RHS 909 Node->getOperand(1))); 910 // If we get a SETCC back from legalizing the SETCC node we just 911 // created, then use its LHS, RHS, and CC directly in creating a new 912 // node. Otherwise, select between the true and false value based on 913 // comparing the result of the legalized with zero. 914 if (Tmp2.getOpcode() == ISD::SETCC) { 915 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 916 Tmp2.getOperand(0), Tmp2.getOperand(1), 917 Node->getOperand(4)); 918 } else { 919 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 920 DAG.getCondCode(ISD::SETNE), 921 Tmp2, DAG.getConstant(0, Tmp2.getValueType()), 922 Node->getOperand(4)); 923 } 924 break; 925 } 926 927 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 928 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 929 930 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 931 default: assert(0 && "Unexpected action for BR_CC!"); 932 case TargetLowering::Custom: { 933 Tmp4 = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 934 Tmp2, Tmp3, Node->getOperand(4)); 935 Tmp4 = TLI.LowerOperation(Tmp4, DAG); 936 if (Tmp4.Val) { 937 Result = LegalizeOp(Tmp4); 938 break; 939 } 940 } // FALLTHROUGH if the target doesn't want to lower this op after all. 941 case TargetLowering::Legal: 942 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 943 Tmp3 != Node->getOperand(3)) { 944 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1), 945 Tmp2, Tmp3, Node->getOperand(4)); 946 } 947 break; 948 } 949 break; 950 case ISD::BRCONDTWOWAY: 951 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 952 switch (getTypeAction(Node->getOperand(1).getValueType())) { 953 case Expand: assert(0 && "It's impossible to expand bools"); 954 case Legal: 955 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 956 break; 957 case Promote: 958 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 959 break; 960 } 961 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR 962 // pair. 963 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) { 964 case TargetLowering::Promote: 965 default: assert(0 && "This action is not supported yet!"); 966 case TargetLowering::Legal: 967 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 968 std::vector<SDOperand> Ops; 969 Ops.push_back(Tmp1); 970 Ops.push_back(Tmp2); 971 Ops.push_back(Node->getOperand(2)); 972 Ops.push_back(Node->getOperand(3)); 973 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops); 974 } 975 break; 976 case TargetLowering::Expand: 977 // If BRTWOWAY_CC is legal for this target, then simply expand this node 978 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a 979 // BRCOND/BR pair. 980 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 981 if (Tmp2.getOpcode() == ISD::SETCC) { 982 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 983 Tmp2.getOperand(0), Tmp2.getOperand(1), 984 Node->getOperand(2), Node->getOperand(3)); 985 } else { 986 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 987 DAG.getConstant(0, Tmp2.getValueType()), 988 Node->getOperand(2), Node->getOperand(3)); 989 } 990 } else { 991 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 992 Node->getOperand(2)); 993 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3)); 994 } 995 Result = LegalizeOp(Result); // Relegalize new nodes. 996 break; 997 } 998 break; 999 case ISD::BRTWOWAY_CC: 1000 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1001 if (isTypeLegal(Node->getOperand(2).getValueType())) { 1002 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS 1003 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS 1004 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 1005 Tmp3 != Node->getOperand(3)) { 1006 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3, 1007 Node->getOperand(4), Node->getOperand(5)); 1008 } 1009 break; 1010 } else { 1011 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1012 Node->getOperand(2), // LHS 1013 Node->getOperand(3), // RHS 1014 Node->getOperand(1))); 1015 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR 1016 // pair. 1017 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) { 1018 default: assert(0 && "This action is not supported yet!"); 1019 case TargetLowering::Legal: 1020 // If we get a SETCC back from legalizing the SETCC node we just 1021 // created, then use its LHS, RHS, and CC directly in creating a new 1022 // node. Otherwise, select between the true and false value based on 1023 // comparing the result of the legalized with zero. 1024 if (Tmp2.getOpcode() == ISD::SETCC) { 1025 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2), 1026 Tmp2.getOperand(0), Tmp2.getOperand(1), 1027 Node->getOperand(4), Node->getOperand(5)); 1028 } else { 1029 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, 1030 DAG.getConstant(0, Tmp2.getValueType()), 1031 Node->getOperand(4), Node->getOperand(5)); 1032 } 1033 break; 1034 case TargetLowering::Expand: 1035 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2, 1036 Node->getOperand(4)); 1037 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5)); 1038 break; 1039 } 1040 Result = LegalizeOp(Result); // Relegalize new nodes. 1041 } 1042 break; 1043 case ISD::LOAD: 1044 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1045 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1046 1047 if (Tmp1 != Node->getOperand(0) || 1048 Tmp2 != Node->getOperand(1)) 1049 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, 1050 Node->getOperand(2)); 1051 else 1052 Result = SDOperand(Node, 0); 1053 1054 // Since loads produce two values, make sure to remember that we legalized 1055 // both of them. 1056 AddLegalizedOperand(SDOperand(Node, 0), Result); 1057 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1058 return Result.getValue(Op.ResNo); 1059 1060 case ISD::EXTLOAD: 1061 case ISD::SEXTLOAD: 1062 case ISD::ZEXTLOAD: { 1063 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1064 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 1065 1066 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 1067 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) { 1068 default: assert(0 && "This action is not supported yet!"); 1069 case TargetLowering::Promote: 1070 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!"); 1071 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1072 Tmp1, Tmp2, Node->getOperand(2), MVT::i8); 1073 // Since loads produce two values, make sure to remember that we legalized 1074 // both of them. 1075 AddLegalizedOperand(SDOperand(Node, 0), Result); 1076 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1077 return Result.getValue(Op.ResNo); 1078 1079 case TargetLowering::Legal: 1080 if (Tmp1 != Node->getOperand(0) || 1081 Tmp2 != Node->getOperand(1)) 1082 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0), 1083 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1084 else 1085 Result = SDOperand(Node, 0); 1086 1087 // Since loads produce two values, make sure to remember that we legalized 1088 // both of them. 1089 AddLegalizedOperand(SDOperand(Node, 0), Result); 1090 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1091 return Result.getValue(Op.ResNo); 1092 case TargetLowering::Expand: 1093 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1094 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1095 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2)); 1096 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1097 Result = LegalizeOp(Result); // Relegalize new nodes. 1098 Load = LegalizeOp(Load); 1099 AddLegalizedOperand(SDOperand(Node, 0), Result); 1100 AddLegalizedOperand(SDOperand(Node, 1), Load.getValue(1)); 1101 if (Op.ResNo) 1102 return Load.getValue(1); 1103 return Result; 1104 } 1105 assert(Node->getOpcode() != ISD::EXTLOAD && 1106 "EXTLOAD should always be supported!"); 1107 // Turn the unsupported load into an EXTLOAD followed by an explicit 1108 // zero/sign extend inreg. 1109 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1110 Tmp1, Tmp2, Node->getOperand(2), SrcVT); 1111 SDOperand ValRes; 1112 if (Node->getOpcode() == ISD::SEXTLOAD) 1113 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1114 Result, DAG.getValueType(SrcVT)); 1115 else 1116 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1117 Result = LegalizeOp(Result); // Relegalize new nodes. 1118 ValRes = LegalizeOp(ValRes); // Relegalize new nodes. 1119 AddLegalizedOperand(SDOperand(Node, 0), ValRes); 1120 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1121 if (Op.ResNo) 1122 return Result.getValue(1); 1123 return ValRes; 1124 } 1125 assert(0 && "Unreachable"); 1126 } 1127 case ISD::EXTRACT_ELEMENT: { 1128 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1129 switch (getTypeAction(OpTy)) { 1130 default: 1131 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1132 break; 1133 case Legal: 1134 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1135 // 1 -> Hi 1136 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1137 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1138 TLI.getShiftAmountTy())); 1139 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1140 } else { 1141 // 0 -> Lo 1142 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1143 Node->getOperand(0)); 1144 } 1145 Result = LegalizeOp(Result); 1146 break; 1147 case Expand: 1148 // Get both the low and high parts. 1149 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1150 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1151 Result = Tmp2; // 1 -> Hi 1152 else 1153 Result = Tmp1; // 0 -> Lo 1154 break; 1155 } 1156 break; 1157 } 1158 1159 case ISD::CopyToReg: 1160 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1161 1162 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1163 "Register type must be legal!"); 1164 // Legalize the incoming value (must be a legal type). 1165 Tmp2 = LegalizeOp(Node->getOperand(2)); 1166 if (Node->getNumValues() == 1) { 1167 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2)) 1168 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1, 1169 Node->getOperand(1), Tmp2); 1170 } else { 1171 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1172 if (Node->getNumOperands() == 4) 1173 Tmp3 = LegalizeOp(Node->getOperand(3)); 1174 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) || 1175 (Node->getNumOperands() == 4 && Tmp3 != Node->getOperand(3))) { 1176 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 1177 Result = DAG.getCopyToReg(Tmp1, Reg, Tmp2, Tmp3); 1178 } 1179 1180 // Since this produces two values, make sure to remember that we legalized 1181 // both of them. 1182 AddLegalizedOperand(SDOperand(Node, 0), Result); 1183 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1184 return Result.getValue(Op.ResNo); 1185 } 1186 break; 1187 1188 case ISD::RET: 1189 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1190 switch (Node->getNumOperands()) { 1191 case 2: // ret val 1192 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1193 case Legal: 1194 Tmp2 = LegalizeOp(Node->getOperand(1)); 1195 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1196 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1197 break; 1198 case Expand: { 1199 SDOperand Lo, Hi; 1200 ExpandOp(Node->getOperand(1), Lo, Hi); 1201 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi); 1202 break; 1203 } 1204 case Promote: 1205 Tmp2 = PromoteOp(Node->getOperand(1)); 1206 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2); 1207 break; 1208 } 1209 break; 1210 case 1: // ret void 1211 if (Tmp1 != Node->getOperand(0)) 1212 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1); 1213 break; 1214 default: { // ret <values> 1215 std::vector<SDOperand> NewValues; 1216 NewValues.push_back(Tmp1); 1217 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 1218 switch (getTypeAction(Node->getOperand(i).getValueType())) { 1219 case Legal: 1220 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 1221 break; 1222 case Expand: { 1223 SDOperand Lo, Hi; 1224 ExpandOp(Node->getOperand(i), Lo, Hi); 1225 NewValues.push_back(Lo); 1226 NewValues.push_back(Hi); 1227 break; 1228 } 1229 case Promote: 1230 assert(0 && "Can't promote multiple return value yet!"); 1231 } 1232 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues); 1233 break; 1234 } 1235 } 1236 break; 1237 case ISD::STORE: 1238 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1239 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1240 1241 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 1242 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){ 1243 if (CFP->getValueType(0) == MVT::f32) { 1244 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1245 DAG.getConstant(FloatToBits(CFP->getValue()), 1246 MVT::i32), 1247 Tmp2, 1248 Node->getOperand(3)); 1249 } else { 1250 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!"); 1251 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, 1252 DAG.getConstant(DoubleToBits(CFP->getValue()), 1253 MVT::i64), 1254 Tmp2, 1255 Node->getOperand(3)); 1256 } 1257 Node = Result.Val; 1258 } 1259 1260 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1261 case Legal: { 1262 SDOperand Val = LegalizeOp(Node->getOperand(1)); 1263 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) || 1264 Tmp2 != Node->getOperand(2)) 1265 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, 1266 Node->getOperand(3)); 1267 break; 1268 } 1269 case Promote: 1270 // Truncate the value and store the result. 1271 Tmp3 = PromoteOp(Node->getOperand(1)); 1272 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2, 1273 Node->getOperand(3), 1274 DAG.getValueType(Node->getOperand(1).getValueType())); 1275 break; 1276 1277 case Expand: 1278 SDOperand Lo, Hi; 1279 unsigned IncrementSize; 1280 ExpandOp(Node->getOperand(1), Lo, Hi); 1281 1282 if (!TLI.isLittleEndian()) 1283 std::swap(Lo, Hi); 1284 1285 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2, 1286 Node->getOperand(3)); 1287 // If this is a vector type, then we have to calculate the increment as 1288 // the product of the element size in bytes, and the number of elements 1289 // in the high half of the vector. 1290 if (MVT::Vector == Hi.getValueType()) { 1291 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue(); 1292 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT(); 1293 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8; 1294 } else { 1295 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8; 1296 } 1297 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 1298 getIntPtrConstant(IncrementSize)); 1299 assert(isTypeLegal(Tmp2.getValueType()) && 1300 "Pointers must be legal!"); 1301 //Again, claiming both parts of the store came form the same Instr 1302 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, 1303 Node->getOperand(3)); 1304 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1305 break; 1306 } 1307 break; 1308 case ISD::PCMARKER: 1309 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1310 if (Tmp1 != Node->getOperand(0)) 1311 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1)); 1312 break; 1313 case ISD::READCYCLECOUNTER: 1314 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 1315 if (Tmp1 != Node->getOperand(0)) { 1316 std::vector<MVT::ValueType> rtypes; 1317 std::vector<SDOperand> rvals; 1318 rtypes.push_back(MVT::i64); 1319 rtypes.push_back(MVT::Other); 1320 rvals.push_back(Tmp1); 1321 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals); 1322 } 1323 1324 // Since rdcc produce two values, make sure to remember that we legalized 1325 // both of them. 1326 AddLegalizedOperand(SDOperand(Node, 0), Result); 1327 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1328 return Result.getValue(Op.ResNo); 1329 1330 case ISD::TRUNCSTORE: 1331 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1332 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer. 1333 1334 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1335 case Legal: 1336 Tmp2 = LegalizeOp(Node->getOperand(1)); 1337 1338 // The only promote case we handle is TRUNCSTORE:i1 X into 1339 // -> TRUNCSTORE:i8 (and X, 1) 1340 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 && 1341 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) == 1342 TargetLowering::Promote) { 1343 // Promote the bool to a mask then store. 1344 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2, 1345 DAG.getConstant(1, Tmp2.getValueType())); 1346 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1347 Node->getOperand(3), DAG.getValueType(MVT::i8)); 1348 1349 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1350 Tmp3 != Node->getOperand(2)) { 1351 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3, 1352 Node->getOperand(3), Node->getOperand(4)); 1353 } 1354 break; 1355 case Promote: 1356 case Expand: 1357 assert(0 && "Cannot handle illegal TRUNCSTORE yet!"); 1358 } 1359 break; 1360 case ISD::SELECT: 1361 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1362 case Expand: assert(0 && "It's impossible to expand bools"); 1363 case Legal: 1364 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 1365 break; 1366 case Promote: 1367 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 1368 break; 1369 } 1370 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 1371 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 1372 1373 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 1374 default: assert(0 && "This action is not supported yet!"); 1375 case TargetLowering::Expand: 1376 if (Tmp1.getOpcode() == ISD::SETCC) { 1377 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 1378 Tmp2, Tmp3, 1379 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 1380 } else { 1381 // Make sure the condition is either zero or one. It may have been 1382 // promoted from something else. 1383 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 1384 Result = DAG.getSelectCC(Tmp1, 1385 DAG.getConstant(0, Tmp1.getValueType()), 1386 Tmp2, Tmp3, ISD::SETNE); 1387 } 1388 Result = LegalizeOp(Result); // Relegalize new nodes. 1389 break; 1390 case TargetLowering::Custom: { 1391 SDOperand Tmp = 1392 TLI.LowerOperation(DAG.getNode(ISD::SELECT, Node->getValueType(0), 1393 Tmp1, Tmp2, Tmp3), DAG); 1394 if (Tmp.Val) { 1395 Result = LegalizeOp(Tmp); 1396 break; 1397 } 1398 // FALLTHROUGH if the target thinks it is legal. 1399 } 1400 case TargetLowering::Legal: 1401 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1402 Tmp3 != Node->getOperand(2)) 1403 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0), 1404 Tmp1, Tmp2, Tmp3); 1405 break; 1406 case TargetLowering::Promote: { 1407 MVT::ValueType NVT = 1408 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 1409 unsigned ExtOp, TruncOp; 1410 if (MVT::isInteger(Tmp2.getValueType())) { 1411 ExtOp = ISD::ANY_EXTEND; 1412 TruncOp = ISD::TRUNCATE; 1413 } else { 1414 ExtOp = ISD::FP_EXTEND; 1415 TruncOp = ISD::FP_ROUND; 1416 } 1417 // Promote each of the values to the new type. 1418 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 1419 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 1420 // Perform the larger operation, then round down. 1421 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 1422 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 1423 break; 1424 } 1425 } 1426 break; 1427 case ISD::SELECT_CC: 1428 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 1429 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 1430 1431 if (isTypeLegal(Node->getOperand(0).getValueType())) { 1432 // Everything is legal, see if we should expand this op or something. 1433 switch (TLI.getOperationAction(ISD::SELECT_CC, 1434 Node->getOperand(0).getValueType())) { 1435 default: assert(0 && "This action is not supported yet!"); 1436 case TargetLowering::Custom: { 1437 SDOperand Tmp = 1438 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), 1439 Node->getOperand(0), 1440 Node->getOperand(1), Tmp3, Tmp4, 1441 Node->getOperand(4)), DAG); 1442 if (Tmp.Val) { 1443 Result = LegalizeOp(Tmp); 1444 break; 1445 } 1446 } // FALLTHROUGH if the target can't lower this operation after all. 1447 case TargetLowering::Legal: 1448 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1449 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1450 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1451 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) { 1452 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1,Tmp2, 1453 Tmp3, Tmp4, Node->getOperand(4)); 1454 } 1455 break; 1456 } 1457 break; 1458 } else { 1459 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), 1460 Node->getOperand(0), // LHS 1461 Node->getOperand(1), // RHS 1462 Node->getOperand(4))); 1463 // If we get a SETCC back from legalizing the SETCC node we just 1464 // created, then use its LHS, RHS, and CC directly in creating a new 1465 // node. Otherwise, select between the true and false value based on 1466 // comparing the result of the legalized with zero. 1467 if (Tmp1.getOpcode() == ISD::SETCC) { 1468 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(), 1469 Tmp1.getOperand(0), Tmp1.getOperand(1), 1470 Tmp3, Tmp4, Tmp1.getOperand(2)); 1471 } else { 1472 Result = DAG.getSelectCC(Tmp1, 1473 DAG.getConstant(0, Tmp1.getValueType()), 1474 Tmp3, Tmp4, ISD::SETNE); 1475 } 1476 } 1477 break; 1478 case ISD::SETCC: 1479 switch (getTypeAction(Node->getOperand(0).getValueType())) { 1480 case Legal: 1481 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1482 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1483 break; 1484 case Promote: 1485 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS 1486 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS 1487 1488 // If this is an FP compare, the operands have already been extended. 1489 if (MVT::isInteger(Node->getOperand(0).getValueType())) { 1490 MVT::ValueType VT = Node->getOperand(0).getValueType(); 1491 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 1492 1493 // Otherwise, we have to insert explicit sign or zero extends. Note 1494 // that we could insert sign extends for ALL conditions, but zero extend 1495 // is cheaper on many machines (an AND instead of two shifts), so prefer 1496 // it. 1497 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1498 default: assert(0 && "Unknown integer comparison!"); 1499 case ISD::SETEQ: 1500 case ISD::SETNE: 1501 case ISD::SETUGE: 1502 case ISD::SETUGT: 1503 case ISD::SETULE: 1504 case ISD::SETULT: 1505 // ALL of these operations will work if we either sign or zero extend 1506 // the operands (including the unsigned comparisons!). Zero extend is 1507 // usually a simpler/cheaper operation, so prefer it. 1508 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 1509 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 1510 break; 1511 case ISD::SETGE: 1512 case ISD::SETGT: 1513 case ISD::SETLT: 1514 case ISD::SETLE: 1515 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 1516 DAG.getValueType(VT)); 1517 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 1518 DAG.getValueType(VT)); 1519 break; 1520 } 1521 } 1522 break; 1523 case Expand: 1524 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1525 ExpandOp(Node->getOperand(0), LHSLo, LHSHi); 1526 ExpandOp(Node->getOperand(1), RHSLo, RHSHi); 1527 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1528 case ISD::SETEQ: 1529 case ISD::SETNE: 1530 if (RHSLo == RHSHi) 1531 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 1532 if (RHSCST->isAllOnesValue()) { 1533 // Comparison to -1. 1534 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1535 Tmp2 = RHSLo; 1536 break; 1537 } 1538 1539 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1540 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1541 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 1542 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 1543 break; 1544 default: 1545 // If this is a comparison of the sign bit, just look at the top part. 1546 // X > -1, x < 0 1547 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1))) 1548 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT && 1549 CST->getValue() == 0) || // X < 0 1550 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT && 1551 (CST->isAllOnesValue()))) { // X > -1 1552 Tmp1 = LHSHi; 1553 Tmp2 = RHSHi; 1554 break; 1555 } 1556 1557 // FIXME: This generated code sucks. 1558 ISD::CondCode LowCC; 1559 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) { 1560 default: assert(0 && "Unknown integer setcc!"); 1561 case ISD::SETLT: 1562 case ISD::SETULT: LowCC = ISD::SETULT; break; 1563 case ISD::SETGT: 1564 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1565 case ISD::SETLE: 1566 case ISD::SETULE: LowCC = ISD::SETULE; break; 1567 case ISD::SETGE: 1568 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1569 } 1570 1571 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1572 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1573 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1574 1575 // NOTE: on targets without efficient SELECT of bools, we can always use 1576 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1577 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC); 1578 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi, 1579 Node->getOperand(2)); 1580 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ); 1581 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1582 Result, Tmp1, Tmp2)); 1583 AddLegalizedOperand(SDOperand(Node, 0), Result); 1584 return Result; 1585 } 1586 } 1587 1588 switch(TLI.getOperationAction(ISD::SETCC, 1589 Node->getOperand(0).getValueType())) { 1590 default: 1591 assert(0 && "Cannot handle this action for SETCC yet!"); 1592 break; 1593 case TargetLowering::Promote: { 1594 // First step, figure out the appropriate operation to use. 1595 // Allow SETCC to not be supported for all legal data types 1596 // Mostly this targets FP 1597 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 1598 MVT::ValueType OldVT = NewInTy; 1599 1600 // Scan for the appropriate larger type to use. 1601 while (1) { 1602 NewInTy = (MVT::ValueType)(NewInTy+1); 1603 1604 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 1605 "Fell off of the edge of the integer world"); 1606 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 1607 "Fell off of the edge of the floating point world"); 1608 1609 // If the target supports SETCC of this type, use it. 1610 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 1611 break; 1612 } 1613 if (MVT::isInteger(NewInTy)) 1614 assert(0 && "Cannot promote Legal Integer SETCC yet"); 1615 else { 1616 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 1617 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 1618 } 1619 1620 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1621 Node->getOperand(2)); 1622 break; 1623 } 1624 case TargetLowering::Custom: { 1625 SDOperand Tmp = 1626 TLI.LowerOperation(DAG.getNode(ISD::SETCC, Node->getValueType(0), 1627 Tmp1, Tmp2, Node->getOperand(2)), DAG); 1628 if (Tmp.Val) { 1629 Result = LegalizeOp(Tmp); 1630 break; 1631 } 1632 // FALLTHROUGH if the target thinks it is legal. 1633 } 1634 case TargetLowering::Legal: 1635 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1636 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2, 1637 Node->getOperand(2)); 1638 break; 1639 case TargetLowering::Expand: 1640 // Expand a setcc node into a select_cc of the same condition, lhs, and 1641 // rhs that selects between const 1 (true) and const 0 (false). 1642 MVT::ValueType VT = Node->getValueType(0); 1643 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 1644 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 1645 Node->getOperand(2)); 1646 Result = LegalizeOp(Result); 1647 break; 1648 } 1649 break; 1650 1651 case ISD::MEMSET: 1652 case ISD::MEMCPY: 1653 case ISD::MEMMOVE: { 1654 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 1655 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 1656 1657 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 1658 switch (getTypeAction(Node->getOperand(2).getValueType())) { 1659 case Expand: assert(0 && "Cannot expand a byte!"); 1660 case Legal: 1661 Tmp3 = LegalizeOp(Node->getOperand(2)); 1662 break; 1663 case Promote: 1664 Tmp3 = PromoteOp(Node->getOperand(2)); 1665 break; 1666 } 1667 } else { 1668 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 1669 } 1670 1671 SDOperand Tmp4; 1672 switch (getTypeAction(Node->getOperand(3).getValueType())) { 1673 case Expand: { 1674 // Length is too big, just take the lo-part of the length. 1675 SDOperand HiPart; 1676 ExpandOp(Node->getOperand(3), HiPart, Tmp4); 1677 break; 1678 } 1679 case Legal: 1680 Tmp4 = LegalizeOp(Node->getOperand(3)); 1681 break; 1682 case Promote: 1683 Tmp4 = PromoteOp(Node->getOperand(3)); 1684 break; 1685 } 1686 1687 SDOperand Tmp5; 1688 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 1689 case Expand: assert(0 && "Cannot expand this yet!"); 1690 case Legal: 1691 Tmp5 = LegalizeOp(Node->getOperand(4)); 1692 break; 1693 case Promote: 1694 Tmp5 = PromoteOp(Node->getOperand(4)); 1695 break; 1696 } 1697 1698 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1699 default: assert(0 && "This action not implemented for this operation!"); 1700 case TargetLowering::Custom: { 1701 SDOperand Tmp = 1702 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, 1703 Tmp2, Tmp3, Tmp4, Tmp5), DAG); 1704 if (Tmp.Val) { 1705 Result = LegalizeOp(Tmp); 1706 break; 1707 } 1708 // FALLTHROUGH if the target thinks it is legal. 1709 } 1710 case TargetLowering::Legal: 1711 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1712 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) || 1713 Tmp5 != Node->getOperand(4)) { 1714 std::vector<SDOperand> Ops; 1715 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3); 1716 Ops.push_back(Tmp4); Ops.push_back(Tmp5); 1717 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops); 1718 } 1719 break; 1720 case TargetLowering::Expand: { 1721 // Otherwise, the target does not support this operation. Lower the 1722 // operation to an explicit libcall as appropriate. 1723 MVT::ValueType IntPtr = TLI.getPointerTy(); 1724 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType(); 1725 std::vector<std::pair<SDOperand, const Type*> > Args; 1726 1727 const char *FnName = 0; 1728 if (Node->getOpcode() == ISD::MEMSET) { 1729 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1730 // Extend the ubyte argument to be an int value for the call. 1731 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 1732 Args.push_back(std::make_pair(Tmp3, Type::IntTy)); 1733 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1734 1735 FnName = "memset"; 1736 } else if (Node->getOpcode() == ISD::MEMCPY || 1737 Node->getOpcode() == ISD::MEMMOVE) { 1738 Args.push_back(std::make_pair(Tmp2, IntPtrTy)); 1739 Args.push_back(std::make_pair(Tmp3, IntPtrTy)); 1740 Args.push_back(std::make_pair(Tmp4, IntPtrTy)); 1741 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 1742 } else { 1743 assert(0 && "Unknown op!"); 1744 } 1745 1746 std::pair<SDOperand,SDOperand> CallResult = 1747 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false, 1748 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 1749 Result = LegalizeOp(CallResult.second); 1750 break; 1751 } 1752 } 1753 break; 1754 } 1755 1756 case ISD::READPORT: 1757 Tmp1 = LegalizeOp(Node->getOperand(0)); 1758 Tmp2 = LegalizeOp(Node->getOperand(1)); 1759 1760 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1761 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1762 std::vector<SDOperand> Ops; 1763 Ops.push_back(Tmp1); 1764 Ops.push_back(Tmp2); 1765 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1766 } else 1767 Result = SDOperand(Node, 0); 1768 // Since these produce two values, make sure to remember that we legalized 1769 // both of them. 1770 AddLegalizedOperand(SDOperand(Node, 0), Result); 1771 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1772 return Result.getValue(Op.ResNo); 1773 case ISD::WRITEPORT: 1774 Tmp1 = LegalizeOp(Node->getOperand(0)); 1775 Tmp2 = LegalizeOp(Node->getOperand(1)); 1776 Tmp3 = LegalizeOp(Node->getOperand(2)); 1777 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1778 Tmp3 != Node->getOperand(2)) 1779 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1780 break; 1781 1782 case ISD::READIO: 1783 Tmp1 = LegalizeOp(Node->getOperand(0)); 1784 Tmp2 = LegalizeOp(Node->getOperand(1)); 1785 1786 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1787 case TargetLowering::Custom: 1788 default: assert(0 && "This action not implemented for this operation!"); 1789 case TargetLowering::Legal: 1790 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) { 1791 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1792 std::vector<SDOperand> Ops; 1793 Ops.push_back(Tmp1); 1794 Ops.push_back(Tmp2); 1795 Result = DAG.getNode(ISD::READPORT, VTs, Ops); 1796 } else 1797 Result = SDOperand(Node, 0); 1798 break; 1799 case TargetLowering::Expand: 1800 // Replace this with a load from memory. 1801 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0), 1802 Node->getOperand(1), DAG.getSrcValue(NULL)); 1803 Result = LegalizeOp(Result); 1804 break; 1805 } 1806 1807 // Since these produce two values, make sure to remember that we legalized 1808 // both of them. 1809 AddLegalizedOperand(SDOperand(Node, 0), Result); 1810 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1811 return Result.getValue(Op.ResNo); 1812 1813 case ISD::WRITEIO: 1814 Tmp1 = LegalizeOp(Node->getOperand(0)); 1815 Tmp2 = LegalizeOp(Node->getOperand(1)); 1816 Tmp3 = LegalizeOp(Node->getOperand(2)); 1817 1818 switch (TLI.getOperationAction(Node->getOpcode(), 1819 Node->getOperand(1).getValueType())) { 1820 case TargetLowering::Custom: 1821 default: assert(0 && "This action not implemented for this operation!"); 1822 case TargetLowering::Legal: 1823 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || 1824 Tmp3 != Node->getOperand(2)) 1825 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3); 1826 break; 1827 case TargetLowering::Expand: 1828 // Replace this with a store to memory. 1829 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0), 1830 Node->getOperand(1), Node->getOperand(2), 1831 DAG.getSrcValue(NULL)); 1832 Result = LegalizeOp(Result); 1833 break; 1834 } 1835 break; 1836 1837 case ISD::ADD_PARTS: 1838 case ISD::SUB_PARTS: 1839 case ISD::SHL_PARTS: 1840 case ISD::SRA_PARTS: 1841 case ISD::SRL_PARTS: { 1842 std::vector<SDOperand> Ops; 1843 bool Changed = false; 1844 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1845 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1846 Changed |= Ops.back() != Node->getOperand(i); 1847 } 1848 if (Changed) { 1849 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end()); 1850 Result = DAG.getNode(Node->getOpcode(), VTs, Ops); 1851 } 1852 1853 // Since these produce multiple values, make sure to remember that we 1854 // legalized all of them. 1855 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1856 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 1857 return Result.getValue(Op.ResNo); 1858 } 1859 1860 // Binary operators 1861 case ISD::ADD: 1862 case ISD::SUB: 1863 case ISD::MUL: 1864 case ISD::MULHS: 1865 case ISD::MULHU: 1866 case ISD::UDIV: 1867 case ISD::SDIV: 1868 case ISD::AND: 1869 case ISD::OR: 1870 case ISD::XOR: 1871 case ISD::SHL: 1872 case ISD::SRL: 1873 case ISD::SRA: 1874 case ISD::FADD: 1875 case ISD::FSUB: 1876 case ISD::FMUL: 1877 case ISD::FDIV: 1878 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1879 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1880 case Expand: assert(0 && "Not possible"); 1881 case Legal: 1882 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 1883 break; 1884 case Promote: 1885 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 1886 break; 1887 } 1888 if (Tmp1 != Node->getOperand(0) || 1889 Tmp2 != Node->getOperand(1)) 1890 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); 1891 break; 1892 1893 case ISD::BUILD_PAIR: { 1894 MVT::ValueType PairTy = Node->getValueType(0); 1895 // TODO: handle the case where the Lo and Hi operands are not of legal type 1896 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 1897 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 1898 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 1899 case TargetLowering::Legal: 1900 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 1901 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 1902 break; 1903 case TargetLowering::Promote: 1904 case TargetLowering::Custom: 1905 assert(0 && "Cannot promote/custom this yet!"); 1906 case TargetLowering::Expand: 1907 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 1908 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 1909 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 1910 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 1911 TLI.getShiftAmountTy())); 1912 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2)); 1913 break; 1914 } 1915 break; 1916 } 1917 1918 case ISD::UREM: 1919 case ISD::SREM: 1920 case ISD::FREM: 1921 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 1922 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 1923 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1924 case TargetLowering::Legal: 1925 if (Tmp1 != Node->getOperand(0) || 1926 Tmp2 != Node->getOperand(1)) 1927 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 1928 Tmp2); 1929 break; 1930 case TargetLowering::Promote: 1931 case TargetLowering::Custom: 1932 assert(0 && "Cannot promote/custom handle this yet!"); 1933 case TargetLowering::Expand: 1934 if (MVT::isInteger(Node->getValueType(0))) { 1935 MVT::ValueType VT = Node->getValueType(0); 1936 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 1937 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2); 1938 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 1939 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 1940 } else { 1941 // Floating point mod -> fmod libcall. 1942 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod"; 1943 SDOperand Dummy; 1944 Result = ExpandLibCall(FnName, Node, Dummy); 1945 } 1946 break; 1947 } 1948 break; 1949 1950 case ISD::CTPOP: 1951 case ISD::CTTZ: 1952 case ISD::CTLZ: 1953 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 1954 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1955 case TargetLowering::Legal: 1956 if (Tmp1 != Node->getOperand(0)) 1957 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1958 break; 1959 case TargetLowering::Promote: { 1960 MVT::ValueType OVT = Tmp1.getValueType(); 1961 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1962 1963 // Zero extend the argument. 1964 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 1965 // Perform the larger operation, then subtract if needed. 1966 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 1967 switch(Node->getOpcode()) 1968 { 1969 case ISD::CTPOP: 1970 Result = Tmp1; 1971 break; 1972 case ISD::CTTZ: 1973 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 1974 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 1975 DAG.getConstant(getSizeInBits(NVT), NVT), 1976 ISD::SETEQ); 1977 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 1978 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1); 1979 break; 1980 case ISD::CTLZ: 1981 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 1982 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 1983 DAG.getConstant(getSizeInBits(NVT) - 1984 getSizeInBits(OVT), NVT)); 1985 break; 1986 } 1987 break; 1988 } 1989 case TargetLowering::Custom: 1990 assert(0 && "Cannot custom handle this yet!"); 1991 case TargetLowering::Expand: 1992 switch(Node->getOpcode()) 1993 { 1994 case ISD::CTPOP: { 1995 static const uint64_t mask[6] = { 1996 0x5555555555555555ULL, 0x3333333333333333ULL, 1997 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 1998 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 1999 }; 2000 MVT::ValueType VT = Tmp1.getValueType(); 2001 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 2002 unsigned len = getSizeInBits(VT); 2003 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2004 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2005 Tmp2 = DAG.getConstant(mask[i], VT); 2006 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2007 Tmp1 = DAG.getNode(ISD::ADD, VT, 2008 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2), 2009 DAG.getNode(ISD::AND, VT, 2010 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3), 2011 Tmp2)); 2012 } 2013 Result = Tmp1; 2014 break; 2015 } 2016 case ISD::CTLZ: { 2017 /* for now, we do this: 2018 x = x | (x >> 1); 2019 x = x | (x >> 2); 2020 ... 2021 x = x | (x >>16); 2022 x = x | (x >>32); // for 64-bit input 2023 return popcount(~x); 2024 2025 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */ 2026 MVT::ValueType VT = Tmp1.getValueType(); 2027 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 2028 unsigned len = getSizeInBits(VT); 2029 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2030 Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2031 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1, 2032 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3)); 2033 } 2034 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT)); 2035 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 2036 break; 2037 } 2038 case ISD::CTTZ: { 2039 // for now, we use: { return popcount(~x & (x - 1)); } 2040 // unless the target has ctlz but not ctpop, in which case we use: 2041 // { return 32 - nlz(~x & (x-1)); } 2042 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2043 MVT::ValueType VT = Tmp1.getValueType(); 2044 Tmp2 = DAG.getConstant(~0ULL, VT); 2045 Tmp3 = DAG.getNode(ISD::AND, VT, 2046 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2), 2047 DAG.getNode(ISD::SUB, VT, Tmp1, 2048 DAG.getConstant(1, VT))); 2049 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead 2050 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 2051 TLI.isOperationLegal(ISD::CTLZ, VT)) { 2052 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT, 2053 DAG.getConstant(getSizeInBits(VT), VT), 2054 DAG.getNode(ISD::CTLZ, VT, Tmp3))); 2055 } else { 2056 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3)); 2057 } 2058 break; 2059 } 2060 default: 2061 assert(0 && "Cannot expand this yet!"); 2062 break; 2063 } 2064 break; 2065 } 2066 break; 2067 2068 // Unary operators 2069 case ISD::FABS: 2070 case ISD::FNEG: 2071 case ISD::FSQRT: 2072 case ISD::FSIN: 2073 case ISD::FCOS: 2074 Tmp1 = LegalizeOp(Node->getOperand(0)); 2075 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2076 case TargetLowering::Legal: 2077 if (Tmp1 != Node->getOperand(0)) 2078 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2079 break; 2080 case TargetLowering::Promote: 2081 case TargetLowering::Custom: 2082 assert(0 && "Cannot promote/custom handle this yet!"); 2083 case TargetLowering::Expand: 2084 switch(Node->getOpcode()) { 2085 case ISD::FNEG: { 2086 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2087 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2088 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0), 2089 Tmp2, Tmp1)); 2090 break; 2091 } 2092 case ISD::FABS: { 2093 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2094 MVT::ValueType VT = Node->getValueType(0); 2095 Tmp2 = DAG.getConstantFP(0.0, VT); 2096 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 2097 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 2098 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 2099 Result = LegalizeOp(Result); 2100 break; 2101 } 2102 case ISD::FSQRT: 2103 case ISD::FSIN: 2104 case ISD::FCOS: { 2105 MVT::ValueType VT = Node->getValueType(0); 2106 const char *FnName = 0; 2107 switch(Node->getOpcode()) { 2108 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break; 2109 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break; 2110 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break; 2111 default: assert(0 && "Unreachable!"); 2112 } 2113 SDOperand Dummy; 2114 Result = ExpandLibCall(FnName, Node, Dummy); 2115 break; 2116 } 2117 default: 2118 assert(0 && "Unreachable!"); 2119 } 2120 break; 2121 } 2122 break; 2123 2124 case ISD::BIT_CONVERT: 2125 if (!isTypeLegal(Node->getOperand(0).getValueType())) 2126 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2127 else { 2128 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 2129 Node->getOperand(0).getValueType())) { 2130 default: assert(0 && "Unknown operation action!"); 2131 case TargetLowering::Expand: 2132 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2133 break; 2134 case TargetLowering::Legal: 2135 Tmp1 = LegalizeOp(Node->getOperand(0)); 2136 if (Tmp1 != Node->getOperand(0)) 2137 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Tmp1); 2138 break; 2139 } 2140 } 2141 break; 2142 // Conversion operators. The source and destination have different types. 2143 case ISD::SINT_TO_FP: 2144 case ISD::UINT_TO_FP: { 2145 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 2146 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2147 case Legal: 2148 switch (TLI.getOperationAction(Node->getOpcode(), 2149 Node->getOperand(0).getValueType())) { 2150 default: assert(0 && "Unknown operation action!"); 2151 case TargetLowering::Expand: 2152 Result = ExpandLegalINT_TO_FP(isSigned, 2153 LegalizeOp(Node->getOperand(0)), 2154 Node->getValueType(0)); 2155 AddLegalizedOperand(Op, Result); 2156 return Result; 2157 case TargetLowering::Promote: 2158 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 2159 Node->getValueType(0), 2160 isSigned); 2161 AddLegalizedOperand(Op, Result); 2162 return Result; 2163 case TargetLowering::Legal: 2164 break; 2165 case TargetLowering::Custom: { 2166 Tmp1 = LegalizeOp(Node->getOperand(0)); 2167 SDOperand Tmp = 2168 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2169 Tmp = TLI.LowerOperation(Tmp, DAG); 2170 if (Tmp.Val) { 2171 Tmp = LegalizeOp(Tmp); // Relegalize input. 2172 AddLegalizedOperand(Op, Tmp); 2173 return Tmp; 2174 } else { 2175 assert(0 && "Target Must Lower this"); 2176 } 2177 } 2178 } 2179 2180 Tmp1 = LegalizeOp(Node->getOperand(0)); 2181 if (Tmp1 != Node->getOperand(0)) 2182 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2183 break; 2184 case Expand: 2185 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 2186 Node->getValueType(0), Node->getOperand(0)); 2187 break; 2188 case Promote: 2189 if (isSigned) { 2190 Result = PromoteOp(Node->getOperand(0)); 2191 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2192 Result, DAG.getValueType(Node->getOperand(0).getValueType())); 2193 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result); 2194 } else { 2195 Result = PromoteOp(Node->getOperand(0)); 2196 Result = DAG.getZeroExtendInReg(Result, 2197 Node->getOperand(0).getValueType()); 2198 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result); 2199 } 2200 break; 2201 } 2202 break; 2203 } 2204 case ISD::TRUNCATE: 2205 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2206 case Legal: 2207 Tmp1 = LegalizeOp(Node->getOperand(0)); 2208 if (Tmp1 != Node->getOperand(0)) 2209 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2210 break; 2211 case Expand: 2212 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2213 2214 // Since the result is legal, we should just be able to truncate the low 2215 // part of the source. 2216 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 2217 break; 2218 case Promote: 2219 Result = PromoteOp(Node->getOperand(0)); 2220 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 2221 break; 2222 } 2223 break; 2224 2225 case ISD::FP_TO_SINT: 2226 case ISD::FP_TO_UINT: 2227 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2228 case Legal: 2229 Tmp1 = LegalizeOp(Node->getOperand(0)); 2230 2231 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 2232 default: assert(0 && "Unknown operation action!"); 2233 case TargetLowering::Expand: 2234 if (Node->getOpcode() == ISD::FP_TO_UINT) { 2235 SDOperand True, False; 2236 MVT::ValueType VT = Node->getOperand(0).getValueType(); 2237 MVT::ValueType NVT = Node->getValueType(0); 2238 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1; 2239 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT); 2240 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 2241 Node->getOperand(0), Tmp2, ISD::SETLT); 2242 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 2243 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 2244 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 2245 Tmp2)); 2246 False = DAG.getNode(ISD::XOR, NVT, False, 2247 DAG.getConstant(1ULL << ShiftAmt, NVT)); 2248 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False)); 2249 AddLegalizedOperand(SDOperand(Node, 0), Result); 2250 return Result; 2251 } else { 2252 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 2253 } 2254 break; 2255 case TargetLowering::Promote: 2256 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 2257 Node->getOpcode() == ISD::FP_TO_SINT); 2258 AddLegalizedOperand(Op, Result); 2259 return Result; 2260 case TargetLowering::Custom: { 2261 SDOperand Tmp = 2262 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2263 Tmp = TLI.LowerOperation(Tmp, DAG); 2264 if (Tmp.Val) { 2265 Tmp = LegalizeOp(Tmp); 2266 AddLegalizedOperand(Op, Tmp); 2267 return Tmp; 2268 } else { 2269 // The target thinks this is legal afterall. 2270 break; 2271 } 2272 } 2273 case TargetLowering::Legal: 2274 break; 2275 } 2276 2277 if (Tmp1 != Node->getOperand(0)) 2278 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2279 break; 2280 case Expand: 2281 assert(0 && "Shouldn't need to expand other operators here!"); 2282 case Promote: 2283 Result = PromoteOp(Node->getOperand(0)); 2284 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2285 break; 2286 } 2287 break; 2288 2289 case ISD::ANY_EXTEND: 2290 case ISD::ZERO_EXTEND: 2291 case ISD::SIGN_EXTEND: 2292 case ISD::FP_EXTEND: 2293 case ISD::FP_ROUND: 2294 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2295 case Legal: 2296 Tmp1 = LegalizeOp(Node->getOperand(0)); 2297 if (Tmp1 != Node->getOperand(0)) 2298 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 2299 break; 2300 case Expand: 2301 assert(0 && "Shouldn't need to expand other operators here!"); 2302 2303 case Promote: 2304 switch (Node->getOpcode()) { 2305 case ISD::ANY_EXTEND: 2306 Result = PromoteOp(Node->getOperand(0)); 2307 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2308 break; 2309 case ISD::ZERO_EXTEND: 2310 Result = PromoteOp(Node->getOperand(0)); 2311 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2312 Result = DAG.getZeroExtendInReg(Result, 2313 Node->getOperand(0).getValueType()); 2314 break; 2315 case ISD::SIGN_EXTEND: 2316 Result = PromoteOp(Node->getOperand(0)); 2317 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 2318 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2319 Result, 2320 DAG.getValueType(Node->getOperand(0).getValueType())); 2321 break; 2322 case ISD::FP_EXTEND: 2323 Result = PromoteOp(Node->getOperand(0)); 2324 if (Result.getValueType() != Op.getValueType()) 2325 // Dynamically dead while we have only 2 FP types. 2326 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result); 2327 break; 2328 case ISD::FP_ROUND: 2329 Result = PromoteOp(Node->getOperand(0)); 2330 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result); 2331 break; 2332 } 2333 } 2334 break; 2335 case ISD::FP_ROUND_INREG: 2336 case ISD::SIGN_EXTEND_INREG: { 2337 Tmp1 = LegalizeOp(Node->getOperand(0)); 2338 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2339 2340 // If this operation is not supported, convert it to a shl/shr or load/store 2341 // pair. 2342 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 2343 default: assert(0 && "This action not supported for this op yet!"); 2344 case TargetLowering::Legal: 2345 if (Tmp1 != Node->getOperand(0)) 2346 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, 2347 DAG.getValueType(ExtraVT)); 2348 break; 2349 case TargetLowering::Expand: 2350 // If this is an integer extend and shifts are supported, do that. 2351 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 2352 // NOTE: we could fall back on load/store here too for targets without 2353 // SAR. However, it is doubtful that any exist. 2354 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 2355 MVT::getSizeInBits(ExtraVT); 2356 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 2357 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 2358 Node->getOperand(0), ShiftCst); 2359 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 2360 Result, ShiftCst); 2361 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 2362 // The only way we can lower this is to turn it into a STORETRUNC, 2363 // EXTLOAD pair, targetting a temporary location (a stack slot). 2364 2365 // NOTE: there is a choice here between constantly creating new stack 2366 // slots and always reusing the same one. We currently always create 2367 // new ones, as reuse may inhibit scheduling. 2368 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 2369 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty); 2370 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty); 2371 MachineFunction &MF = DAG.getMachineFunction(); 2372 int SSFI = 2373 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align); 2374 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 2375 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(), 2376 Node->getOperand(0), StackSlot, 2377 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT)); 2378 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2379 Result, StackSlot, DAG.getSrcValue(NULL), 2380 ExtraVT); 2381 } else { 2382 assert(0 && "Unknown op"); 2383 } 2384 Result = LegalizeOp(Result); 2385 break; 2386 } 2387 break; 2388 } 2389 } 2390 2391 // Note that LegalizeOp may be reentered even from single-use nodes, which 2392 // means that we always must cache transformed nodes. 2393 AddLegalizedOperand(Op, Result); 2394 return Result; 2395} 2396 2397/// PromoteOp - Given an operation that produces a value in an invalid type, 2398/// promote it to compute the value into a larger type. The produced value will 2399/// have the correct bits for the low portion of the register, but no guarantee 2400/// is made about the top bits: it may be zero, sign-extended, or garbage. 2401SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 2402 MVT::ValueType VT = Op.getValueType(); 2403 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 2404 assert(getTypeAction(VT) == Promote && 2405 "Caller should expand or legalize operands that are not promotable!"); 2406 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 2407 "Cannot promote to smaller type!"); 2408 2409 SDOperand Tmp1, Tmp2, Tmp3; 2410 2411 SDOperand Result; 2412 SDNode *Node = Op.Val; 2413 2414 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 2415 if (I != PromotedNodes.end()) return I->second; 2416 2417 // Promotion needs an optimization step to clean up after it, and is not 2418 // careful to avoid operations the target does not support. Make sure that 2419 // all generated operations are legalized in the next iteration. 2420 NeedsAnotherIteration = true; 2421 2422 switch (Node->getOpcode()) { 2423 case ISD::CopyFromReg: 2424 assert(0 && "CopyFromReg must be legal!"); 2425 default: 2426 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 2427 assert(0 && "Do not know how to promote this operator!"); 2428 abort(); 2429 case ISD::UNDEF: 2430 Result = DAG.getNode(ISD::UNDEF, NVT); 2431 break; 2432 case ISD::Constant: 2433 if (VT != MVT::i1) 2434 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 2435 else 2436 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 2437 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 2438 break; 2439 case ISD::ConstantFP: 2440 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 2441 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 2442 break; 2443 2444 case ISD::SETCC: 2445 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 2446 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 2447 Node->getOperand(1), Node->getOperand(2)); 2448 Result = LegalizeOp(Result); 2449 break; 2450 2451 case ISD::TRUNCATE: 2452 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2453 case Legal: 2454 Result = LegalizeOp(Node->getOperand(0)); 2455 assert(Result.getValueType() >= NVT && 2456 "This truncation doesn't make sense!"); 2457 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 2458 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 2459 break; 2460 case Promote: 2461 // The truncation is not required, because we don't guarantee anything 2462 // about high bits anyway. 2463 Result = PromoteOp(Node->getOperand(0)); 2464 break; 2465 case Expand: 2466 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2467 // Truncate the low part of the expanded value to the result type 2468 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 2469 } 2470 break; 2471 case ISD::SIGN_EXTEND: 2472 case ISD::ZERO_EXTEND: 2473 case ISD::ANY_EXTEND: 2474 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2475 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 2476 case Legal: 2477 // Input is legal? Just do extend all the way to the larger type. 2478 Result = LegalizeOp(Node->getOperand(0)); 2479 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2480 break; 2481 case Promote: 2482 // Promote the reg if it's smaller. 2483 Result = PromoteOp(Node->getOperand(0)); 2484 // The high bits are not guaranteed to be anything. Insert an extend. 2485 if (Node->getOpcode() == ISD::SIGN_EXTEND) 2486 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2487 DAG.getValueType(Node->getOperand(0).getValueType())); 2488 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 2489 Result = DAG.getZeroExtendInReg(Result, 2490 Node->getOperand(0).getValueType()); 2491 break; 2492 } 2493 break; 2494 case ISD::BIT_CONVERT: 2495 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 2496 Result = PromoteOp(Result); 2497 break; 2498 2499 case ISD::FP_EXTEND: 2500 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 2501 case ISD::FP_ROUND: 2502 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2503 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 2504 case Promote: assert(0 && "Unreachable with 2 FP types!"); 2505 case Legal: 2506 // Input is legal? Do an FP_ROUND_INREG. 2507 Result = LegalizeOp(Node->getOperand(0)); 2508 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2509 DAG.getValueType(VT)); 2510 break; 2511 } 2512 break; 2513 2514 case ISD::SINT_TO_FP: 2515 case ISD::UINT_TO_FP: 2516 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2517 case Legal: 2518 Result = LegalizeOp(Node->getOperand(0)); 2519 // No extra round required here. 2520 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2521 break; 2522 2523 case Promote: 2524 Result = PromoteOp(Node->getOperand(0)); 2525 if (Node->getOpcode() == ISD::SINT_TO_FP) 2526 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2527 Result, 2528 DAG.getValueType(Node->getOperand(0).getValueType())); 2529 else 2530 Result = DAG.getZeroExtendInReg(Result, 2531 Node->getOperand(0).getValueType()); 2532 // No extra round required here. 2533 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 2534 break; 2535 case Expand: 2536 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 2537 Node->getOperand(0)); 2538 // Round if we cannot tolerate excess precision. 2539 if (NoExcessFPPrecision) 2540 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2541 DAG.getValueType(VT)); 2542 break; 2543 } 2544 break; 2545 2546 case ISD::SIGN_EXTEND_INREG: 2547 Result = PromoteOp(Node->getOperand(0)); 2548 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 2549 Node->getOperand(1)); 2550 break; 2551 case ISD::FP_TO_SINT: 2552 case ISD::FP_TO_UINT: 2553 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2554 case Legal: 2555 Tmp1 = LegalizeOp(Node->getOperand(0)); 2556 break; 2557 case Promote: 2558 // The input result is prerounded, so we don't have to do anything 2559 // special. 2560 Tmp1 = PromoteOp(Node->getOperand(0)); 2561 break; 2562 case Expand: 2563 assert(0 && "not implemented"); 2564 } 2565 // If we're promoting a UINT to a larger size, check to see if the new node 2566 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 2567 // we can use that instead. This allows us to generate better code for 2568 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 2569 // legal, such as PowerPC. 2570 if (Node->getOpcode() == ISD::FP_TO_UINT && 2571 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 2572 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 2573 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 2574 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 2575 } else { 2576 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2577 } 2578 break; 2579 2580 case ISD::FABS: 2581 case ISD::FNEG: 2582 Tmp1 = PromoteOp(Node->getOperand(0)); 2583 assert(Tmp1.getValueType() == NVT); 2584 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2585 // NOTE: we do not have to do any extra rounding here for 2586 // NoExcessFPPrecision, because we know the input will have the appropriate 2587 // precision, and these operations don't modify precision at all. 2588 break; 2589 2590 case ISD::FSQRT: 2591 case ISD::FSIN: 2592 case ISD::FCOS: 2593 Tmp1 = PromoteOp(Node->getOperand(0)); 2594 assert(Tmp1.getValueType() == NVT); 2595 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2596 if(NoExcessFPPrecision) 2597 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2598 DAG.getValueType(VT)); 2599 break; 2600 2601 case ISD::AND: 2602 case ISD::OR: 2603 case ISD::XOR: 2604 case ISD::ADD: 2605 case ISD::SUB: 2606 case ISD::MUL: 2607 // The input may have strange things in the top bits of the registers, but 2608 // these operations don't care. They may have weird bits going out, but 2609 // that too is okay if they are integer operations. 2610 Tmp1 = PromoteOp(Node->getOperand(0)); 2611 Tmp2 = PromoteOp(Node->getOperand(1)); 2612 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2613 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2614 break; 2615 case ISD::FADD: 2616 case ISD::FSUB: 2617 case ISD::FMUL: 2618 // The input may have strange things in the top bits of the registers, but 2619 // these operations don't care. 2620 Tmp1 = PromoteOp(Node->getOperand(0)); 2621 Tmp2 = PromoteOp(Node->getOperand(1)); 2622 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 2623 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2624 2625 // Floating point operations will give excess precision that we may not be 2626 // able to tolerate. If we DO allow excess precision, just leave it, 2627 // otherwise excise it. 2628 // FIXME: Why would we need to round FP ops more than integer ones? 2629 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 2630 if (NoExcessFPPrecision) 2631 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2632 DAG.getValueType(VT)); 2633 break; 2634 2635 case ISD::SDIV: 2636 case ISD::SREM: 2637 // These operators require that their input be sign extended. 2638 Tmp1 = PromoteOp(Node->getOperand(0)); 2639 Tmp2 = PromoteOp(Node->getOperand(1)); 2640 if (MVT::isInteger(NVT)) { 2641 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2642 DAG.getValueType(VT)); 2643 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 2644 DAG.getValueType(VT)); 2645 } 2646 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2647 2648 // Perform FP_ROUND: this is probably overly pessimistic. 2649 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 2650 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2651 DAG.getValueType(VT)); 2652 break; 2653 case ISD::FDIV: 2654 case ISD::FREM: 2655 // These operators require that their input be fp extended. 2656 Tmp1 = PromoteOp(Node->getOperand(0)); 2657 Tmp2 = PromoteOp(Node->getOperand(1)); 2658 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2659 2660 // Perform FP_ROUND: this is probably overly pessimistic. 2661 if (NoExcessFPPrecision) 2662 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 2663 DAG.getValueType(VT)); 2664 break; 2665 2666 case ISD::UDIV: 2667 case ISD::UREM: 2668 // These operators require that their input be zero extended. 2669 Tmp1 = PromoteOp(Node->getOperand(0)); 2670 Tmp2 = PromoteOp(Node->getOperand(1)); 2671 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 2672 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2673 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 2674 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2675 break; 2676 2677 case ISD::SHL: 2678 Tmp1 = PromoteOp(Node->getOperand(0)); 2679 Tmp2 = LegalizeOp(Node->getOperand(1)); 2680 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2); 2681 break; 2682 case ISD::SRA: 2683 // The input value must be properly sign extended. 2684 Tmp1 = PromoteOp(Node->getOperand(0)); 2685 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 2686 DAG.getValueType(VT)); 2687 Tmp2 = LegalizeOp(Node->getOperand(1)); 2688 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2); 2689 break; 2690 case ISD::SRL: 2691 // The input value must be properly zero extended. 2692 Tmp1 = PromoteOp(Node->getOperand(0)); 2693 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 2694 Tmp2 = LegalizeOp(Node->getOperand(1)); 2695 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2); 2696 break; 2697 case ISD::LOAD: 2698 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2699 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2700 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2, 2701 Node->getOperand(2), VT); 2702 // Remember that we legalized the chain. 2703 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2704 break; 2705 case ISD::SEXTLOAD: 2706 case ISD::ZEXTLOAD: 2707 case ISD::EXTLOAD: 2708 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2709 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2710 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2, 2711 Node->getOperand(2), 2712 cast<VTSDNode>(Node->getOperand(3))->getVT()); 2713 // Remember that we legalized the chain. 2714 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2715 break; 2716 case ISD::SELECT: 2717 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2718 case Expand: assert(0 && "It's impossible to expand bools"); 2719 case Legal: 2720 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition. 2721 break; 2722 case Promote: 2723 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2724 break; 2725 } 2726 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 2727 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 2728 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3); 2729 break; 2730 case ISD::SELECT_CC: 2731 Tmp2 = PromoteOp(Node->getOperand(2)); // True 2732 Tmp3 = PromoteOp(Node->getOperand(3)); // False 2733 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 2734 Node->getOperand(1), Tmp2, Tmp3, 2735 Node->getOperand(4)); 2736 break; 2737 case ISD::TAILCALL: 2738 case ISD::CALL: { 2739 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2740 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 2741 2742 std::vector<SDOperand> Ops; 2743 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) 2744 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2745 2746 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 2747 "Can only promote single result calls"); 2748 std::vector<MVT::ValueType> RetTyVTs; 2749 RetTyVTs.reserve(2); 2750 RetTyVTs.push_back(NVT); 2751 RetTyVTs.push_back(MVT::Other); 2752 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops, 2753 Node->getOpcode() == ISD::TAILCALL); 2754 Result = SDOperand(NC, 0); 2755 2756 // Insert the new chain mapping. 2757 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 2758 break; 2759 } 2760 case ISD::CTPOP: 2761 case ISD::CTTZ: 2762 case ISD::CTLZ: 2763 Tmp1 = Node->getOperand(0); 2764 //Zero extend the argument 2765 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 2766 // Perform the larger operation, then subtract if needed. 2767 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 2768 switch(Node->getOpcode()) 2769 { 2770 case ISD::CTPOP: 2771 Result = Tmp1; 2772 break; 2773 case ISD::CTTZ: 2774 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 2775 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 2776 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ); 2777 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 2778 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1); 2779 break; 2780 case ISD::CTLZ: 2781 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 2782 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 2783 DAG.getConstant(getSizeInBits(NVT) - 2784 getSizeInBits(VT), NVT)); 2785 break; 2786 } 2787 break; 2788 } 2789 2790 assert(Result.Val && "Didn't set a result!"); 2791 AddPromotedOperand(Op, Result); 2792 return Result; 2793} 2794 2795/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 2796/// The resultant code need not be legal. 2797SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 2798 SDOperand SrcOp) { 2799 // Create the stack frame object. 2800 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); 2801 unsigned ByteSize = MVT::getSizeInBits(DestVT)/8; 2802 int FrameIdx = FrameInfo->CreateFixedObject(ByteSize, ByteSize); 2803 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy()); 2804 2805 // Emit a store to the stack slot. 2806 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 2807 SrcOp, FIPtr, DAG.getSrcValue(NULL)); 2808 // Result is a load from the stack slot. 2809 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0)); 2810} 2811 2812/// ExpandAddSub - Find a clever way to expand this add operation into 2813/// subcomponents. 2814void SelectionDAGLegalize:: 2815ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS, 2816 SDOperand &Lo, SDOperand &Hi) { 2817 // Expand the subcomponents. 2818 SDOperand LHSL, LHSH, RHSL, RHSH; 2819 ExpandOp(LHS, LHSL, LHSH); 2820 ExpandOp(RHS, RHSL, RHSH); 2821 2822 std::vector<SDOperand> Ops; 2823 Ops.push_back(LHSL); 2824 Ops.push_back(LHSH); 2825 Ops.push_back(RHSL); 2826 Ops.push_back(RHSH); 2827 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2828 Lo = DAG.getNode(NodeOp, VTs, Ops); 2829 Hi = Lo.getValue(1); 2830} 2831 2832void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 2833 SDOperand Op, SDOperand Amt, 2834 SDOperand &Lo, SDOperand &Hi) { 2835 // Expand the subcomponents. 2836 SDOperand LHSL, LHSH; 2837 ExpandOp(Op, LHSL, LHSH); 2838 2839 std::vector<SDOperand> Ops; 2840 Ops.push_back(LHSL); 2841 Ops.push_back(LHSH); 2842 Ops.push_back(Amt); 2843 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType()); 2844 Lo = DAG.getNode(NodeOp, VTs, Ops); 2845 Hi = Lo.getValue(1); 2846} 2847 2848 2849/// ExpandShift - Try to find a clever way to expand this shift operation out to 2850/// smaller elements. If we can't find a way that is more efficient than a 2851/// libcall on this target, return false. Otherwise, return true with the 2852/// low-parts expanded into Lo and Hi. 2853bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 2854 SDOperand &Lo, SDOperand &Hi) { 2855 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 2856 "This is not a shift!"); 2857 2858 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 2859 SDOperand ShAmt = LegalizeOp(Amt); 2860 MVT::ValueType ShTy = ShAmt.getValueType(); 2861 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 2862 unsigned NVTBits = MVT::getSizeInBits(NVT); 2863 2864 // Handle the case when Amt is an immediate. Other cases are currently broken 2865 // and are disabled. 2866 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 2867 unsigned Cst = CN->getValue(); 2868 // Expand the incoming operand to be shifted, so that we have its parts 2869 SDOperand InL, InH; 2870 ExpandOp(Op, InL, InH); 2871 switch(Opc) { 2872 case ISD::SHL: 2873 if (Cst > VTBits) { 2874 Lo = DAG.getConstant(0, NVT); 2875 Hi = DAG.getConstant(0, NVT); 2876 } else if (Cst > NVTBits) { 2877 Lo = DAG.getConstant(0, NVT); 2878 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 2879 } else if (Cst == NVTBits) { 2880 Lo = DAG.getConstant(0, NVT); 2881 Hi = InL; 2882 } else { 2883 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 2884 Hi = DAG.getNode(ISD::OR, NVT, 2885 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 2886 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 2887 } 2888 return true; 2889 case ISD::SRL: 2890 if (Cst > VTBits) { 2891 Lo = DAG.getConstant(0, NVT); 2892 Hi = DAG.getConstant(0, NVT); 2893 } else if (Cst > NVTBits) { 2894 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 2895 Hi = DAG.getConstant(0, NVT); 2896 } else if (Cst == NVTBits) { 2897 Lo = InH; 2898 Hi = DAG.getConstant(0, NVT); 2899 } else { 2900 Lo = DAG.getNode(ISD::OR, NVT, 2901 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2902 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2903 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 2904 } 2905 return true; 2906 case ISD::SRA: 2907 if (Cst > VTBits) { 2908 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 2909 DAG.getConstant(NVTBits-1, ShTy)); 2910 } else if (Cst > NVTBits) { 2911 Lo = DAG.getNode(ISD::SRA, NVT, InH, 2912 DAG.getConstant(Cst-NVTBits, ShTy)); 2913 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2914 DAG.getConstant(NVTBits-1, ShTy)); 2915 } else if (Cst == NVTBits) { 2916 Lo = InH; 2917 Hi = DAG.getNode(ISD::SRA, NVT, InH, 2918 DAG.getConstant(NVTBits-1, ShTy)); 2919 } else { 2920 Lo = DAG.getNode(ISD::OR, NVT, 2921 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 2922 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 2923 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 2924 } 2925 return true; 2926 } 2927 } 2928 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy, 2929 // so disable it for now. Currently targets are handling this via SHL_PARTS 2930 // and friends. 2931 return false; 2932 2933 // If we have an efficient select operation (or if the selects will all fold 2934 // away), lower to some complex code, otherwise just emit the libcall. 2935 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt)) 2936 return false; 2937 2938 SDOperand InL, InH; 2939 ExpandOp(Op, InL, InH); 2940 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt 2941 DAG.getConstant(NVTBits, ShTy), ShAmt); 2942 2943 // Compare the unmasked shift amount against 32. 2944 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt, 2945 DAG.getConstant(NVTBits, ShTy), ISD::SETGE); 2946 2947 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) { 2948 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31 2949 DAG.getConstant(NVTBits-1, ShTy)); 2950 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31 2951 DAG.getConstant(NVTBits-1, ShTy)); 2952 } 2953 2954 if (Opc == ISD::SHL) { 2955 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt) 2956 DAG.getNode(ISD::SHL, NVT, InH, ShAmt), 2957 DAG.getNode(ISD::SRL, NVT, InL, NAmt)); 2958 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31 2959 2960 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2961 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2); 2962 } else { 2963 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT, 2964 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt, 2965 DAG.getConstant(32, ShTy), 2966 ISD::SETEQ), 2967 DAG.getConstant(0, NVT), 2968 DAG.getNode(ISD::SHL, NVT, InH, NAmt)); 2969 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt) 2970 HiLoPart, 2971 DAG.getNode(ISD::SRL, NVT, InL, ShAmt)); 2972 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31 2973 2974 SDOperand HiPart; 2975 if (Opc == ISD::SRA) 2976 HiPart = DAG.getNode(ISD::SRA, NVT, InH, 2977 DAG.getConstant(NVTBits-1, ShTy)); 2978 else 2979 HiPart = DAG.getConstant(0, NVT); 2980 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1); 2981 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2); 2982 } 2983 return true; 2984} 2985 2986/// FindLatestCallSeqStart - Scan up the dag to find the latest (highest 2987/// NodeDepth) node that is an CallSeqStart operation and occurs later than 2988/// Found. 2989static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) { 2990 if (Node->getNodeDepth() <= Found->getNodeDepth()) return; 2991 2992 // If we found an CALLSEQ_START, we already know this node occurs later 2993 // than the Found node. Just remember this node and return. 2994 if (Node->getOpcode() == ISD::CALLSEQ_START) { 2995 Found = Node; 2996 return; 2997 } 2998 2999 // Otherwise, scan the operands of Node to see if any of them is a call. 3000 assert(Node->getNumOperands() != 0 && 3001 "All leaves should have depth equal to the entry node!"); 3002 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i) 3003 FindLatestCallSeqStart(Node->getOperand(i).Val, Found); 3004 3005 // Tail recurse for the last iteration. 3006 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val, 3007 Found); 3008} 3009 3010 3011/// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest 3012/// NodeDepth) node that is an CallSeqEnd operation and occurs more recent 3013/// than Found. 3014static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found, 3015 std::set<SDNode*> &Visited) { 3016 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) || 3017 !Visited.insert(Node).second) return; 3018 3019 // If we found an CALLSEQ_END, we already know this node occurs earlier 3020 // than the Found node. Just remember this node and return. 3021 if (Node->getOpcode() == ISD::CALLSEQ_END) { 3022 Found = Node; 3023 return; 3024 } 3025 3026 // Otherwise, scan the operands of Node to see if any of them is a call. 3027 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end(); 3028 if (UI == E) return; 3029 for (--E; UI != E; ++UI) 3030 FindEarliestCallSeqEnd(*UI, Found, Visited); 3031 3032 // Tail recurse for the last iteration. 3033 FindEarliestCallSeqEnd(*UI, Found, Visited); 3034} 3035 3036/// FindCallSeqEnd - Given a chained node that is part of a call sequence, 3037/// find the CALLSEQ_END node that terminates the call sequence. 3038static SDNode *FindCallSeqEnd(SDNode *Node) { 3039 if (Node->getOpcode() == ISD::CALLSEQ_END) 3040 return Node; 3041 if (Node->use_empty()) 3042 return 0; // No CallSeqEnd 3043 3044 SDOperand TheChain(Node, Node->getNumValues()-1); 3045 if (TheChain.getValueType() != MVT::Other) 3046 TheChain = SDOperand(Node, 0); 3047 if (TheChain.getValueType() != MVT::Other) 3048 return 0; 3049 3050 for (SDNode::use_iterator UI = Node->use_begin(), 3051 E = Node->use_end(); UI != E; ++UI) { 3052 3053 // Make sure to only follow users of our token chain. 3054 SDNode *User = *UI; 3055 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 3056 if (User->getOperand(i) == TheChain) 3057 if (SDNode *Result = FindCallSeqEnd(User)) 3058 return Result; 3059 } 3060 return 0; 3061} 3062 3063/// FindCallSeqStart - Given a chained node that is part of a call sequence, 3064/// find the CALLSEQ_START node that initiates the call sequence. 3065static SDNode *FindCallSeqStart(SDNode *Node) { 3066 assert(Node && "Didn't find callseq_start for a call??"); 3067 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 3068 3069 assert(Node->getOperand(0).getValueType() == MVT::Other && 3070 "Node doesn't have a token chain argument!"); 3071 return FindCallSeqStart(Node->getOperand(0).Val); 3072} 3073 3074 3075/// FindInputOutputChains - If we are replacing an operation with a call we need 3076/// to find the call that occurs before and the call that occurs after it to 3077/// properly serialize the calls in the block. The returned operand is the 3078/// input chain value for the new call (e.g. the entry node or the previous 3079/// call), and OutChain is set to be the chain node to update to point to the 3080/// end of the call chain. 3081static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain, 3082 SDOperand Entry) { 3083 SDNode *LatestCallSeqStart = Entry.Val; 3084 SDNode *LatestCallSeqEnd = 0; 3085 FindLatestCallSeqStart(OpNode, LatestCallSeqStart); 3086 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n"; 3087 3088 // It is possible that no ISD::CALLSEQ_START was found because there is no 3089 // previous call in the function. LatestCallStackDown may in that case be 3090 // the entry node itself. Do not attempt to find a matching CALLSEQ_END 3091 // unless LatestCallStackDown is an CALLSEQ_START. 3092 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) { 3093 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart); 3094 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n"; 3095 } else { 3096 LatestCallSeqEnd = Entry.Val; 3097 } 3098 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd"); 3099 3100 // Finally, find the first call that this must come before, first we find the 3101 // CallSeqEnd that ends the call. 3102 OutChain = 0; 3103 std::set<SDNode*> Visited; 3104 FindEarliestCallSeqEnd(OpNode, OutChain, Visited); 3105 3106 // If we found one, translate from the adj up to the callseq_start. 3107 if (OutChain) 3108 OutChain = FindCallSeqStart(OutChain); 3109 3110 return SDOperand(LatestCallSeqEnd, 0); 3111} 3112 3113/// SpliceCallInto - Given the result chain of a libcall (CallResult), and a 3114void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult, 3115 SDNode *OutChain) { 3116 // Nothing to splice it into? 3117 if (OutChain == 0) return; 3118 3119 assert(OutChain->getOperand(0).getValueType() == MVT::Other); 3120 //OutChain->dump(); 3121 3122 // Form a token factor node merging the old inval and the new inval. 3123 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult, 3124 OutChain->getOperand(0)); 3125 // Change the node to refer to the new token. 3126 OutChain->setAdjCallChain(InToken); 3127} 3128 3129 3130// ExpandLibCall - Expand a node into a call to a libcall. If the result value 3131// does not fit into a register, return the lo part and set the hi part to the 3132// by-reg argument. If it does fit into a single register, return the result 3133// and leave the Hi part unset. 3134SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 3135 SDOperand &Hi) { 3136 SDNode *OutChain; 3137 SDOperand InChain = FindInputOutputChains(Node, OutChain, 3138 DAG.getEntryNode()); 3139 if (InChain.Val == 0) 3140 InChain = DAG.getEntryNode(); 3141 3142 TargetLowering::ArgListTy Args; 3143 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3144 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 3145 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 3146 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy)); 3147 } 3148 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 3149 3150 // Splice the libcall in wherever FindInputOutputChains tells us to. 3151 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 3152 std::pair<SDOperand,SDOperand> CallInfo = 3153 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false, 3154 Callee, Args, DAG); 3155 3156 SDOperand Result; 3157 switch (getTypeAction(CallInfo.first.getValueType())) { 3158 default: assert(0 && "Unknown thing"); 3159 case Legal: 3160 Result = CallInfo.first; 3161 break; 3162 case Promote: 3163 assert(0 && "Cannot promote this yet!"); 3164 case Expand: 3165 ExpandOp(CallInfo.first, Result, Hi); 3166 CallInfo.second = LegalizeOp(CallInfo.second); 3167 break; 3168 } 3169 3170 SpliceCallInto(CallInfo.second, OutChain); 3171 NeedsAnotherIteration = true; 3172 return Result; 3173} 3174 3175 3176/// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the 3177/// destination type is legal. 3178SDOperand SelectionDAGLegalize:: 3179ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 3180 assert(isTypeLegal(DestTy) && "Destination type is not legal!"); 3181 assert(getTypeAction(Source.getValueType()) == Expand && 3182 "This is not an expansion!"); 3183 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 3184 3185 if (!isSigned) { 3186 assert(Source.getValueType() == MVT::i64 && 3187 "This only works for 64-bit -> FP"); 3188 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 3189 // incoming integer is set. To handle this, we dynamically test to see if 3190 // it is set, and, if so, add a fudge factor. 3191 SDOperand Lo, Hi; 3192 ExpandOp(Source, Lo, Hi); 3193 3194 // If this is unsigned, and not supported, first perform the conversion to 3195 // signed, then adjust the result if the sign bit is set. 3196 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 3197 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 3198 3199 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 3200 DAG.getConstant(0, Hi.getValueType()), 3201 ISD::SETLT); 3202 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 3203 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 3204 SignSet, Four, Zero); 3205 uint64_t FF = 0x5f800000ULL; 3206 if (TLI.isLittleEndian()) FF <<= 32; 3207 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF); 3208 3209 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 3210 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 3211 SDOperand FudgeInReg; 3212 if (DestTy == MVT::f32) 3213 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 3214 DAG.getSrcValue(NULL)); 3215 else { 3216 assert(DestTy == MVT::f64 && "Unexpected conversion"); 3217 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 3218 CPIdx, DAG.getSrcValue(NULL), MVT::f32); 3219 } 3220 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 3221 } 3222 3223 // Check to see if the target has a custom way to lower this. If so, use it. 3224 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 3225 default: assert(0 && "This action not implemented for this operation!"); 3226 case TargetLowering::Legal: 3227 case TargetLowering::Expand: 3228 break; // This case is handled below. 3229 case TargetLowering::Custom: { 3230 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 3231 Source), DAG); 3232 if (NV.Val) 3233 return LegalizeOp(NV); 3234 break; // The target decided this was legal after all 3235 } 3236 } 3237 3238 // Expand the source, then glue it back together for the call. We must expand 3239 // the source in case it is shared (this pass of legalize must traverse it). 3240 SDOperand SrcLo, SrcHi; 3241 ExpandOp(Source, SrcLo, SrcHi); 3242 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 3243 3244 SDNode *OutChain = 0; 3245 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain, 3246 DAG.getEntryNode()); 3247 const char *FnName = 0; 3248 if (DestTy == MVT::f32) 3249 FnName = "__floatdisf"; 3250 else { 3251 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 3252 FnName = "__floatdidf"; 3253 } 3254 3255 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy()); 3256 3257 TargetLowering::ArgListTy Args; 3258 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType()); 3259 3260 Args.push_back(std::make_pair(Source, ArgTy)); 3261 3262 // We don't care about token chains for libcalls. We just use the entry 3263 // node as our input and ignore the output chain. This allows us to place 3264 // calls wherever we need them to satisfy data dependences. 3265 const Type *RetTy = MVT::getTypeForValueType(DestTy); 3266 3267 std::pair<SDOperand,SDOperand> CallResult = 3268 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true, 3269 Callee, Args, DAG); 3270 3271 SpliceCallInto(CallResult.second, OutChain); 3272 return CallResult.first; 3273} 3274 3275 3276 3277/// ExpandOp - Expand the specified SDOperand into its two component pieces 3278/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 3279/// LegalizeNodes map is filled in for any results that are not expanded, the 3280/// ExpandedNodes map is filled in for any results that are expanded, and the 3281/// Lo/Hi values are returned. 3282void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 3283 MVT::ValueType VT = Op.getValueType(); 3284 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3285 SDNode *Node = Op.Val; 3286 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 3287 assert((MVT::isInteger(VT) || VT == MVT::Vector) && 3288 "Cannot expand FP values!"); 3289 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) && 3290 "Cannot expand to FP value or to larger int value!"); 3291 3292 // See if we already expanded it. 3293 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 3294 = ExpandedNodes.find(Op); 3295 if (I != ExpandedNodes.end()) { 3296 Lo = I->second.first; 3297 Hi = I->second.second; 3298 return; 3299 } 3300 3301 // Expanding to multiple registers needs to perform an optimization step, and 3302 // is not careful to avoid operations the target does not support. Make sure 3303 // that all generated operations are legalized in the next iteration. 3304 NeedsAnotherIteration = true; 3305 3306 switch (Node->getOpcode()) { 3307 case ISD::CopyFromReg: 3308 assert(0 && "CopyFromReg must be legal!"); 3309 default: 3310 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n"; 3311 assert(0 && "Do not know how to expand this operator!"); 3312 abort(); 3313 case ISD::UNDEF: 3314 Lo = DAG.getNode(ISD::UNDEF, NVT); 3315 Hi = DAG.getNode(ISD::UNDEF, NVT); 3316 break; 3317 case ISD::Constant: { 3318 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 3319 Lo = DAG.getConstant(Cst, NVT); 3320 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 3321 break; 3322 } 3323 case ISD::ConstantVec: { 3324 unsigned NumElements = Node->getNumOperands(); 3325 // If we only have two elements left in the constant vector, just break it 3326 // apart into the two scalar constants it contains. Otherwise, bisect the 3327 // ConstantVec, and return each half as a new ConstantVec. 3328 // FIXME: this is hard coded as big endian, it may have to change to support 3329 // SSE and Alpha MVI 3330 if (NumElements == 2) { 3331 Hi = Node->getOperand(0); 3332 Lo = Node->getOperand(1); 3333 } else { 3334 NumElements /= 2; 3335 std::vector<SDOperand> LoOps, HiOps; 3336 for (unsigned I = 0, E = NumElements; I < E; ++I) { 3337 HiOps.push_back(Node->getOperand(I)); 3338 LoOps.push_back(Node->getOperand(I+NumElements)); 3339 } 3340 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps); 3341 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps); 3342 } 3343 break; 3344 } 3345 3346 case ISD::BUILD_PAIR: 3347 // Legalize both operands. FIXME: in the future we should handle the case 3348 // where the two elements are not legal. 3349 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!"); 3350 Lo = LegalizeOp(Node->getOperand(0)); 3351 Hi = LegalizeOp(Node->getOperand(1)); 3352 break; 3353 3354 case ISD::SIGN_EXTEND_INREG: 3355 ExpandOp(Node->getOperand(0), Lo, Hi); 3356 // Sign extend the lo-part. 3357 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 3358 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 3359 TLI.getShiftAmountTy())); 3360 // sext_inreg the low part if needed. 3361 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 3362 break; 3363 3364 case ISD::CTPOP: 3365 ExpandOp(Node->getOperand(0), Lo, Hi); 3366 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 3367 DAG.getNode(ISD::CTPOP, NVT, Lo), 3368 DAG.getNode(ISD::CTPOP, NVT, Hi)); 3369 Hi = DAG.getConstant(0, NVT); 3370 break; 3371 3372 case ISD::CTLZ: { 3373 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 3374 ExpandOp(Node->getOperand(0), Lo, Hi); 3375 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3376 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 3377 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 3378 ISD::SETNE); 3379 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 3380 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 3381 3382 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 3383 Hi = DAG.getConstant(0, NVT); 3384 break; 3385 } 3386 3387 case ISD::CTTZ: { 3388 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 3389 ExpandOp(Node->getOperand(0), Lo, Hi); 3390 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 3391 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 3392 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 3393 ISD::SETNE); 3394 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 3395 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 3396 3397 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 3398 Hi = DAG.getConstant(0, NVT); 3399 break; 3400 } 3401 3402 case ISD::LOAD: { 3403 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3404 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3405 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3406 3407 // Increment the pointer to the other half. 3408 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 3409 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3410 getIntPtrConstant(IncrementSize)); 3411 //Is this safe? declaring that the two parts of the split load 3412 //are from the same instruction? 3413 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2)); 3414 3415 // Build a factor node to remember that this load is independent of the 3416 // other one. 3417 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3418 Hi.getValue(1)); 3419 3420 // Remember that we legalized the chain. 3421 AddLegalizedOperand(Op.getValue(1), TF); 3422 if (!TLI.isLittleEndian()) 3423 std::swap(Lo, Hi); 3424 break; 3425 } 3426 case ISD::VLOAD: { 3427 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3428 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3429 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3430 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3431 3432 // If we only have two elements, turn into a pair of scalar loads. 3433 // FIXME: handle case where a vector of two elements is fine, such as 3434 // 2 x double on SSE2. 3435 if (NumElements == 2) { 3436 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3437 // Increment the pointer to the other half. 3438 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8; 3439 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3440 getIntPtrConstant(IncrementSize)); 3441 //Is this safe? declaring that the two parts of the split load 3442 //are from the same instruction? 3443 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4)); 3444 } else { 3445 NumElements /= 2; // Split the vector in half 3446 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3447 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8; 3448 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3449 getIntPtrConstant(IncrementSize)); 3450 //Is this safe? declaring that the two parts of the split load 3451 //are from the same instruction? 3452 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4)); 3453 } 3454 3455 // Build a factor node to remember that this load is independent of the 3456 // other one. 3457 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 3458 Hi.getValue(1)); 3459 3460 // Remember that we legalized the chain. 3461 AddLegalizedOperand(Op.getValue(1), TF); 3462 if (!TLI.isLittleEndian()) 3463 std::swap(Lo, Hi); 3464 break; 3465 } 3466 case ISD::VADD: 3467 case ISD::VSUB: 3468 case ISD::VMUL: { 3469 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 3470 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3471 SDOperand LL, LH, RL, RH; 3472 3473 ExpandOp(Node->getOperand(0), LL, LH); 3474 ExpandOp(Node->getOperand(1), RL, RH); 3475 3476 // If we only have two elements, turn into a pair of scalar loads. 3477 // FIXME: handle case where a vector of two elements is fine, such as 3478 // 2 x double on SSE2. 3479 if (NumElements == 2) { 3480 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT); 3481 Lo = DAG.getNode(Opc, EVT, LL, RL); 3482 Hi = DAG.getNode(Opc, EVT, LH, RH); 3483 } else { 3484 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2), 3485 LL.getOperand(3)); 3486 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2), 3487 LH.getOperand(3)); 3488 } 3489 break; 3490 } 3491 case ISD::TAILCALL: 3492 case ISD::CALL: { 3493 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3494 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee. 3495 3496 bool Changed = false; 3497 std::vector<SDOperand> Ops; 3498 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) { 3499 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3500 Changed |= Ops.back() != Node->getOperand(i); 3501 } 3502 3503 assert(Node->getNumValues() == 2 && Op.ResNo == 0 && 3504 "Can only expand a call once so far, not i64 -> i16!"); 3505 3506 std::vector<MVT::ValueType> RetTyVTs; 3507 RetTyVTs.reserve(3); 3508 RetTyVTs.push_back(NVT); 3509 RetTyVTs.push_back(NVT); 3510 RetTyVTs.push_back(MVT::Other); 3511 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops, 3512 Node->getOpcode() == ISD::TAILCALL); 3513 Lo = SDOperand(NC, 0); 3514 Hi = SDOperand(NC, 1); 3515 3516 // Insert the new chain mapping. 3517 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2)); 3518 break; 3519 } 3520 case ISD::AND: 3521 case ISD::OR: 3522 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 3523 SDOperand LL, LH, RL, RH; 3524 ExpandOp(Node->getOperand(0), LL, LH); 3525 ExpandOp(Node->getOperand(1), RL, RH); 3526 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 3527 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 3528 break; 3529 } 3530 case ISD::SELECT: { 3531 SDOperand C, LL, LH, RL, RH; 3532 3533 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3534 case Expand: assert(0 && "It's impossible to expand bools"); 3535 case Legal: 3536 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 3537 break; 3538 case Promote: 3539 C = PromoteOp(Node->getOperand(0)); // Promote the condition. 3540 break; 3541 } 3542 ExpandOp(Node->getOperand(1), LL, LH); 3543 ExpandOp(Node->getOperand(2), RL, RH); 3544 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL); 3545 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH); 3546 break; 3547 } 3548 case ISD::SELECT_CC: { 3549 SDOperand TL, TH, FL, FH; 3550 ExpandOp(Node->getOperand(2), TL, TH); 3551 ExpandOp(Node->getOperand(3), FL, FH); 3552 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3553 Node->getOperand(1), TL, FL, Node->getOperand(4)); 3554 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 3555 Node->getOperand(1), TH, FH, Node->getOperand(4)); 3556 Lo = LegalizeOp(Lo); 3557 Hi = LegalizeOp(Hi); 3558 break; 3559 } 3560 case ISD::SEXTLOAD: { 3561 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3562 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3563 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3564 3565 if (EVT == NVT) 3566 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3567 else 3568 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3569 EVT); 3570 3571 // Remember that we legalized the chain. 3572 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3573 3574 // The high part is obtained by SRA'ing all but one of the bits of the lo 3575 // part. 3576 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3577 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3578 TLI.getShiftAmountTy())); 3579 Lo = LegalizeOp(Lo); 3580 Hi = LegalizeOp(Hi); 3581 break; 3582 } 3583 case ISD::ZEXTLOAD: { 3584 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3585 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3586 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3587 3588 if (EVT == NVT) 3589 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3590 else 3591 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3592 EVT); 3593 3594 // Remember that we legalized the chain. 3595 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3596 3597 // The high part is just a zero. 3598 Hi = LegalizeOp(DAG.getConstant(0, NVT)); 3599 Lo = LegalizeOp(Lo); 3600 break; 3601 } 3602 case ISD::EXTLOAD: { 3603 SDOperand Chain = LegalizeOp(Node->getOperand(0)); 3604 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); 3605 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT(); 3606 3607 if (EVT == NVT) 3608 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2)); 3609 else 3610 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2), 3611 EVT); 3612 3613 // Remember that we legalized the chain. 3614 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1)); 3615 3616 // The high part is undefined. 3617 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT)); 3618 Lo = LegalizeOp(Lo); 3619 break; 3620 } 3621 case ISD::ANY_EXTEND: { 3622 SDOperand In; 3623 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3624 case Expand: assert(0 && "expand-expand not implemented yet!"); 3625 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3626 case Promote: 3627 In = PromoteOp(Node->getOperand(0)); 3628 break; 3629 } 3630 3631 // The low part is any extension of the input (which degenerates to a copy). 3632 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In); 3633 // The high part is undefined. 3634 Hi = DAG.getNode(ISD::UNDEF, NVT); 3635 break; 3636 } 3637 case ISD::SIGN_EXTEND: { 3638 SDOperand In; 3639 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3640 case Expand: assert(0 && "expand-expand not implemented yet!"); 3641 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3642 case Promote: 3643 In = PromoteOp(Node->getOperand(0)); 3644 // Emit the appropriate sign_extend_inreg to get the value we want. 3645 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In, 3646 DAG.getValueType(Node->getOperand(0).getValueType())); 3647 break; 3648 } 3649 3650 // The low part is just a sign extension of the input (which degenerates to 3651 // a copy). 3652 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In); 3653 3654 // The high part is obtained by SRA'ing all but one of the bits of the lo 3655 // part. 3656 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 3657 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, 3658 TLI.getShiftAmountTy())); 3659 break; 3660 } 3661 case ISD::ZERO_EXTEND: { 3662 SDOperand In; 3663 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3664 case Expand: assert(0 && "expand-expand not implemented yet!"); 3665 case Legal: In = LegalizeOp(Node->getOperand(0)); break; 3666 case Promote: 3667 In = PromoteOp(Node->getOperand(0)); 3668 // Emit the appropriate zero_extend_inreg to get the value we want. 3669 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType()); 3670 break; 3671 } 3672 3673 // The low part is just a zero extension of the input (which degenerates to 3674 // a copy). 3675 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In); 3676 3677 // The high part is just a zero. 3678 Hi = DAG.getConstant(0, NVT); 3679 break; 3680 } 3681 3682 case ISD::BIT_CONVERT: { 3683 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0), 3684 Node->getOperand(0)); 3685 ExpandOp(Tmp, Lo, Hi); 3686 break; 3687 } 3688 3689 case ISD::READCYCLECOUNTER: { 3690 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 3691 TargetLowering::Custom && 3692 "Must custom expand ReadCycleCounter"); 3693 SDOperand T = TLI.LowerOperation(Op, DAG); 3694 assert(T.Val && "Node must be custom expanded!"); 3695 Lo = LegalizeOp(T.getValue(0)); 3696 Hi = LegalizeOp(T.getValue(1)); 3697 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 3698 LegalizeOp(T.getValue(2))); 3699 break; 3700 } 3701 3702 // These operators cannot be expanded directly, emit them as calls to 3703 // library functions. 3704 case ISD::FP_TO_SINT: 3705 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 3706 SDOperand Op; 3707 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3708 case Expand: assert(0 && "cannot expand FP!"); 3709 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 3710 case Promote: Op = PromoteOp(Node->getOperand(0)); break; 3711 } 3712 3713 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 3714 3715 // Now that the custom expander is done, expand the result, which is still 3716 // VT. 3717 if (Op.Val) { 3718 ExpandOp(Op, Lo, Hi); 3719 break; 3720 } 3721 } 3722 3723 if (Node->getOperand(0).getValueType() == MVT::f32) 3724 Lo = ExpandLibCall("__fixsfdi", Node, Hi); 3725 else 3726 Lo = ExpandLibCall("__fixdfdi", Node, Hi); 3727 break; 3728 3729 case ISD::FP_TO_UINT: 3730 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 3731 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT, 3732 LegalizeOp(Node->getOperand(0))); 3733 // Now that the custom expander is done, expand the result, which is still 3734 // VT. 3735 Op = TLI.LowerOperation(Op, DAG); 3736 if (Op.Val) { 3737 ExpandOp(Op, Lo, Hi); 3738 break; 3739 } 3740 } 3741 3742 if (Node->getOperand(0).getValueType() == MVT::f32) 3743 Lo = ExpandLibCall("__fixunssfdi", Node, Hi); 3744 else 3745 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi); 3746 break; 3747 3748 case ISD::SHL: 3749 // If the target wants custom lowering, do so. 3750 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 3751 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), 3752 LegalizeOp(Node->getOperand(1))); 3753 Op = TLI.LowerOperation(Op, DAG); 3754 if (Op.Val) { 3755 // Now that the custom expander is done, expand the result, which is 3756 // still VT. 3757 ExpandOp(Op, Lo, Hi); 3758 break; 3759 } 3760 } 3761 3762 // If we can emit an efficient shift operation, do so now. 3763 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3764 break; 3765 3766 // If this target supports SHL_PARTS, use it. 3767 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) { 3768 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1), 3769 Lo, Hi); 3770 break; 3771 } 3772 3773 // Otherwise, emit a libcall. 3774 Lo = ExpandLibCall("__ashldi3", Node, Hi); 3775 break; 3776 3777 case ISD::SRA: 3778 // If the target wants custom lowering, do so. 3779 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 3780 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), 3781 LegalizeOp(Node->getOperand(1))); 3782 Op = TLI.LowerOperation(Op, DAG); 3783 if (Op.Val) { 3784 // Now that the custom expander is done, expand the result, which is 3785 // still VT. 3786 ExpandOp(Op, Lo, Hi); 3787 break; 3788 } 3789 } 3790 3791 // If we can emit an efficient shift operation, do so now. 3792 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3793 break; 3794 3795 // If this target supports SRA_PARTS, use it. 3796 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) { 3797 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1), 3798 Lo, Hi); 3799 break; 3800 } 3801 3802 // Otherwise, emit a libcall. 3803 Lo = ExpandLibCall("__ashrdi3", Node, Hi); 3804 break; 3805 case ISD::SRL: 3806 // If the target wants custom lowering, do so. 3807 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 3808 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), 3809 LegalizeOp(Node->getOperand(1))); 3810 Op = TLI.LowerOperation(Op, DAG); 3811 if (Op.Val) { 3812 // Now that the custom expander is done, expand the result, which is 3813 // still VT. 3814 ExpandOp(Op, Lo, Hi); 3815 break; 3816 } 3817 } 3818 3819 // If we can emit an efficient shift operation, do so now. 3820 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi)) 3821 break; 3822 3823 // If this target supports SRL_PARTS, use it. 3824 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) { 3825 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1), 3826 Lo, Hi); 3827 break; 3828 } 3829 3830 // Otherwise, emit a libcall. 3831 Lo = ExpandLibCall("__lshrdi3", Node, Hi); 3832 break; 3833 3834 case ISD::ADD: 3835 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1), 3836 Lo, Hi); 3837 break; 3838 case ISD::SUB: 3839 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1), 3840 Lo, Hi); 3841 break; 3842 case ISD::MUL: { 3843 if (TLI.isOperationLegal(ISD::MULHU, NVT)) { 3844 SDOperand LL, LH, RL, RH; 3845 ExpandOp(Node->getOperand(0), LL, LH); 3846 ExpandOp(Node->getOperand(1), RL, RH); 3847 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1; 3848 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp 3849 // extended the sign bit of the low half through the upper half, and if so 3850 // emit a MULHS instead of the alternate sequence that is valid for any 3851 // i64 x i64 multiply. 3852 if (TLI.isOperationLegal(ISD::MULHS, NVT) && 3853 // is RH an extension of the sign bit of RL? 3854 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL && 3855 RH.getOperand(1).getOpcode() == ISD::Constant && 3856 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH && 3857 // is LH an extension of the sign bit of LL? 3858 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL && 3859 LH.getOperand(1).getOpcode() == ISD::Constant && 3860 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) { 3861 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 3862 } else { 3863 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 3864 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 3865 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 3866 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 3867 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 3868 } 3869 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 3870 } else { 3871 Lo = ExpandLibCall("__muldi3" , Node, Hi); break; 3872 } 3873 break; 3874 } 3875 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break; 3876 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break; 3877 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break; 3878 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break; 3879 } 3880 3881 // Remember in a map if the values will be reused later. 3882 bool isNew = ExpandedNodes.insert(std::make_pair(Op, 3883 std::make_pair(Lo, Hi))).second; 3884 assert(isNew && "Value already expanded?!?"); 3885 3886 // Make sure the resultant values have been legalized themselves, unless this 3887 // is a type that requires multi-step expansion. 3888 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 3889 Lo = LegalizeOp(Lo); 3890 Hi = LegalizeOp(Hi); 3891 } 3892} 3893 3894 3895// SelectionDAG::Legalize - This is the entry point for the file. 3896// 3897void SelectionDAG::Legalize() { 3898 /// run - This is the main entry point to this class. 3899 /// 3900 SelectionDAGLegalize(*this).Run(); 3901} 3902 3903