LegalizeDAG.cpp revision f089358a6614476111863ca914f7f07a1a8c69b2
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/Analysis/DebugInfo.h" 20#include "llvm/CodeGen/PseudoSourceValue.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetOptions.h" 26#include "llvm/Target/TargetSubtarget.h" 27#include "llvm/CallingConv.h" 28#include "llvm/Constants.h" 29#include "llvm/DerivedTypes.h" 30#include "llvm/Function.h" 31#include "llvm/GlobalVariable.h" 32#include "llvm/LLVMContext.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/ADT/DenseMap.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/SmallPtrSet.h" 40using namespace llvm; 41 42//===----------------------------------------------------------------------===// 43/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 44/// hacks on it until the target machine can handle it. This involves 45/// eliminating value sizes the machine cannot handle (promoting small sizes to 46/// large sizes or splitting up large values into small values) as well as 47/// eliminating operations the machine cannot handle. 48/// 49/// This code also does a small amount of optimization and recognition of idioms 50/// as part of its processing. For example, if a target does not support a 51/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 52/// will attempt merge setcc and brc instructions into brcc's. 53/// 54namespace { 55class SelectionDAGLegalize { 56 TargetLowering &TLI; 57 SelectionDAG &DAG; 58 CodeGenOpt::Level OptLevel; 59 60 // Libcall insertion helpers. 61 62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 63 /// legalized. We use this to ensure that calls are properly serialized 64 /// against each other, including inserted libcalls. 65 SDValue LastCALLSEQ_END; 66 67 /// IsLegalizingCall - This member is used *only* for purposes of providing 68 /// helpful assertions that a libcall isn't created while another call is 69 /// being legalized (which could lead to non-serialized call sequences). 70 bool IsLegalizingCall; 71 72 enum LegalizeAction { 73 Legal, // The target natively supports this operation. 74 Promote, // This operation should be executed in a larger type. 75 Expand // Try to expand this to other ops, otherwise use a libcall. 76 }; 77 78 /// ValueTypeActions - This is a bitvector that contains two bits for each 79 /// value type, where the two bits correspond to the LegalizeAction enum. 80 /// This can be queried with "getTypeAction(VT)". 81 TargetLowering::ValueTypeActionImpl ValueTypeActions; 82 83 /// LegalizedNodes - For nodes that are of legal width, and that have more 84 /// than one use, this map indicates what regularized operand to use. This 85 /// allows us to avoid legalizing the same thing more than once. 86 DenseMap<SDValue, SDValue> LegalizedNodes; 87 88 void AddLegalizedOperand(SDValue From, SDValue To) { 89 LegalizedNodes.insert(std::make_pair(From, To)); 90 // If someone requests legalization of the new node, return itself. 91 if (From != To) 92 LegalizedNodes.insert(std::make_pair(To, To)); 93 } 94 95public: 96 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 97 98 /// getTypeAction - Return how we should legalize values of this type, either 99 /// it is already legal or we need to expand it into multiple registers of 100 /// smaller integer type, or we need to promote it to a larger type. 101 LegalizeAction getTypeAction(EVT VT) const { 102 return 103 (LegalizeAction)ValueTypeActions.getTypeAction(*DAG.getContext(), VT); 104 } 105 106 /// isTypeLegal - Return true if this type is legal on this target. 107 /// 108 bool isTypeLegal(EVT VT) const { 109 return getTypeAction(VT) == Legal; 110 } 111 112 void LegalizeDAG(); 113 114private: 115 /// LegalizeOp - We know that the specified value has a legal type. 116 /// Recursively ensure that the operands have legal types, then return the 117 /// result. 118 SDValue LegalizeOp(SDValue O); 119 120 SDValue OptimizeFloatStore(StoreSDNode *ST); 121 122 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 123 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 124 /// is necessary to spill the vector being inserted into to memory, perform 125 /// the insert there, and then read the result back. 126 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 127 SDValue Idx, DebugLoc dl); 128 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 129 SDValue Idx, DebugLoc dl); 130 131 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 132 /// performs the same shuffe in terms of order or result bytes, but on a type 133 /// whose vector element type is narrower than the original shuffle type. 134 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 135 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 136 SDValue N1, SDValue N2, 137 SmallVectorImpl<int> &Mask) const; 138 139 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 140 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 141 142 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 143 DebugLoc dl); 144 145 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 146 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 147 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 148 RTLIB::Libcall Call_PPCF128); 149 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 150 RTLIB::Libcall Call_I8, 151 RTLIB::Libcall Call_I16, 152 RTLIB::Libcall Call_I32, 153 RTLIB::Libcall Call_I64, 154 RTLIB::Libcall Call_I128); 155 156 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 157 SDValue ExpandBUILD_VECTOR(SDNode *Node); 158 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 159 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 160 SmallVectorImpl<SDValue> &Results); 161 SDValue ExpandFCOPYSIGN(SDNode *Node); 162 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 163 DebugLoc dl); 164 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 165 DebugLoc dl); 166 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 167 DebugLoc dl); 168 169 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 170 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 171 172 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 173 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 174 175 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 176 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 177}; 178} 179 180/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 181/// performs the same shuffe in terms of order or result bytes, but on a type 182/// whose vector element type is narrower than the original shuffle type. 183/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 184SDValue 185SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 186 SDValue N1, SDValue N2, 187 SmallVectorImpl<int> &Mask) const { 188 unsigned NumMaskElts = VT.getVectorNumElements(); 189 unsigned NumDestElts = NVT.getVectorNumElements(); 190 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 191 192 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 193 194 if (NumEltsGrowth == 1) 195 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 196 197 SmallVector<int, 8> NewMask; 198 for (unsigned i = 0; i != NumMaskElts; ++i) { 199 int Idx = Mask[i]; 200 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 201 if (Idx < 0) 202 NewMask.push_back(-1); 203 else 204 NewMask.push_back(Idx * NumEltsGrowth + j); 205 } 206 } 207 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 208 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 209 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 210} 211 212SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 213 CodeGenOpt::Level ol) 214 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), 215 ValueTypeActions(TLI.getValueTypeActions()) { 216 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 217 "Too many value types for ValueTypeActions to hold!"); 218} 219 220void SelectionDAGLegalize::LegalizeDAG() { 221 LastCALLSEQ_END = DAG.getEntryNode(); 222 IsLegalizingCall = false; 223 224 // The legalize process is inherently a bottom-up recursive process (users 225 // legalize their uses before themselves). Given infinite stack space, we 226 // could just start legalizing on the root and traverse the whole graph. In 227 // practice however, this causes us to run out of stack space on large basic 228 // blocks. To avoid this problem, compute an ordering of the nodes where each 229 // node is only legalized after all of its operands are legalized. 230 DAG.AssignTopologicalOrder(); 231 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 232 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 233 LegalizeOp(SDValue(I, 0)); 234 235 // Finally, it's possible the root changed. Get the new root. 236 SDValue OldRoot = DAG.getRoot(); 237 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 238 DAG.setRoot(LegalizedNodes[OldRoot]); 239 240 LegalizedNodes.clear(); 241 242 // Remove dead nodes now. 243 DAG.RemoveDeadNodes(); 244} 245 246 247/// FindCallEndFromCallStart - Given a chained node that is part of a call 248/// sequence, find the CALLSEQ_END node that terminates the call sequence. 249static SDNode *FindCallEndFromCallStart(SDNode *Node) { 250 if (Node->getOpcode() == ISD::CALLSEQ_END) 251 return Node; 252 if (Node->use_empty()) 253 return 0; // No CallSeqEnd 254 255 // The chain is usually at the end. 256 SDValue TheChain(Node, Node->getNumValues()-1); 257 if (TheChain.getValueType() != MVT::Other) { 258 // Sometimes it's at the beginning. 259 TheChain = SDValue(Node, 0); 260 if (TheChain.getValueType() != MVT::Other) { 261 // Otherwise, hunt for it. 262 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 263 if (Node->getValueType(i) == MVT::Other) { 264 TheChain = SDValue(Node, i); 265 break; 266 } 267 268 // Otherwise, we walked into a node without a chain. 269 if (TheChain.getValueType() != MVT::Other) 270 return 0; 271 } 272 } 273 274 for (SDNode::use_iterator UI = Node->use_begin(), 275 E = Node->use_end(); UI != E; ++UI) { 276 277 // Make sure to only follow users of our token chain. 278 SDNode *User = *UI; 279 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 280 if (User->getOperand(i) == TheChain) 281 if (SDNode *Result = FindCallEndFromCallStart(User)) 282 return Result; 283 } 284 return 0; 285} 286 287/// FindCallStartFromCallEnd - Given a chained node that is part of a call 288/// sequence, find the CALLSEQ_START node that initiates the call sequence. 289static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 290 assert(Node && "Didn't find callseq_start for a call??"); 291 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 292 293 assert(Node->getOperand(0).getValueType() == MVT::Other && 294 "Node doesn't have a token chain argument!"); 295 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 296} 297 298/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 299/// see if any uses can reach Dest. If no dest operands can get to dest, 300/// legalize them, legalize ourself, and return false, otherwise, return true. 301/// 302/// Keep track of the nodes we fine that actually do lead to Dest in 303/// NodesLeadingTo. This avoids retraversing them exponential number of times. 304/// 305bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 306 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 307 if (N == Dest) return true; // N certainly leads to Dest :) 308 309 // If we've already processed this node and it does lead to Dest, there is no 310 // need to reprocess it. 311 if (NodesLeadingTo.count(N)) return true; 312 313 // If the first result of this node has been already legalized, then it cannot 314 // reach N. 315 if (LegalizedNodes.count(SDValue(N, 0))) return false; 316 317 // Okay, this node has not already been legalized. Check and legalize all 318 // operands. If none lead to Dest, then we can legalize this node. 319 bool OperandsLeadToDest = false; 320 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 321 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 322 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 323 324 if (OperandsLeadToDest) { 325 NodesLeadingTo.insert(N); 326 return true; 327 } 328 329 // Okay, this node looks safe, legalize it and return false. 330 LegalizeOp(SDValue(N, 0)); 331 return false; 332} 333 334/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 335/// a load from the constant pool. 336static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 337 SelectionDAG &DAG, const TargetLowering &TLI) { 338 bool Extend = false; 339 DebugLoc dl = CFP->getDebugLoc(); 340 341 // If a FP immediate is precise when represented as a float and if the 342 // target can do an extending load from float to double, we put it into 343 // the constant pool as a float, even if it's is statically typed as a 344 // double. This shrinks FP constants and canonicalizes them for targets where 345 // an FP extending load is the same cost as a normal load (such as on the x87 346 // fp stack or PPC FP unit). 347 EVT VT = CFP->getValueType(0); 348 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 349 if (!UseCP) { 350 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 351 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 352 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 353 } 354 355 EVT OrigVT = VT; 356 EVT SVT = VT; 357 while (SVT != MVT::f32) { 358 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 359 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 360 // Only do this if the target has a native EXTLOAD instruction from 361 // smaller type. 362 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 363 TLI.ShouldShrinkFPConstant(OrigVT)) { 364 const Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 365 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 366 VT = SVT; 367 Extend = true; 368 } 369 } 370 371 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 372 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 373 if (Extend) 374 return DAG.getExtLoad(ISD::EXTLOAD, dl, 375 OrigVT, DAG.getEntryNode(), 376 CPIdx, PseudoSourceValue::getConstantPool(), 377 0, VT, false, false, Alignment); 378 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 379 PseudoSourceValue::getConstantPool(), 0, false, false, 380 Alignment); 381} 382 383/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 384static 385SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 386 const TargetLowering &TLI) { 387 SDValue Chain = ST->getChain(); 388 SDValue Ptr = ST->getBasePtr(); 389 SDValue Val = ST->getValue(); 390 EVT VT = Val.getValueType(); 391 int Alignment = ST->getAlignment(); 392 int SVOffset = ST->getSrcValueOffset(); 393 DebugLoc dl = ST->getDebugLoc(); 394 if (ST->getMemoryVT().isFloatingPoint() || 395 ST->getMemoryVT().isVector()) { 396 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 397 if (TLI.isTypeLegal(intVT)) { 398 // Expand to a bitconvert of the value to the integer type of the 399 // same size, then a (misaligned) int store. 400 // FIXME: Does not handle truncating floating point stores! 401 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 402 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 403 SVOffset, ST->isVolatile(), ST->isNonTemporal(), 404 Alignment); 405 } else { 406 // Do a (aligned) store to a stack slot, then copy from the stack slot 407 // to the final destination using (unaligned) integer loads and stores. 408 EVT StoredVT = ST->getMemoryVT(); 409 EVT RegVT = 410 TLI.getRegisterType(*DAG.getContext(), EVT::getIntegerVT(*DAG.getContext(), StoredVT.getSizeInBits())); 411 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 412 unsigned RegBytes = RegVT.getSizeInBits() / 8; 413 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 414 415 // Make sure the stack slot is also aligned for the register type. 416 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 417 418 // Perform the original store, only redirected to the stack slot. 419 SDValue Store = DAG.getTruncStore(Chain, dl, 420 Val, StackPtr, NULL, 0, StoredVT, 421 false, false, 0); 422 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 423 SmallVector<SDValue, 8> Stores; 424 unsigned Offset = 0; 425 426 // Do all but one copies using the full register width. 427 for (unsigned i = 1; i < NumRegs; i++) { 428 // Load one integer register's worth from the stack slot. 429 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0, 430 false, false, 0); 431 // Store it to the final location. Remember the store. 432 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 433 ST->getSrcValue(), SVOffset + Offset, 434 ST->isVolatile(), ST->isNonTemporal(), 435 MinAlign(ST->getAlignment(), Offset))); 436 // Increment the pointers. 437 Offset += RegBytes; 438 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 439 Increment); 440 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 441 } 442 443 // The last store may be partial. Do a truncating store. On big-endian 444 // machines this requires an extending load from the stack slot to ensure 445 // that the bits are in the right place. 446 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset)); 447 448 // Load from the stack slot. 449 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 450 NULL, 0, MemVT, false, false, 0); 451 452 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 453 ST->getSrcValue(), SVOffset + Offset, 454 MemVT, ST->isVolatile(), 455 ST->isNonTemporal(), 456 MinAlign(ST->getAlignment(), Offset))); 457 // The order of the stores doesn't matter - say it with a TokenFactor. 458 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 459 Stores.size()); 460 } 461 } 462 assert(ST->getMemoryVT().isInteger() && 463 !ST->getMemoryVT().isVector() && 464 "Unaligned store of unknown type."); 465 // Get the half-size VT 466 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 467 int NumBits = NewStoredVT.getSizeInBits(); 468 int IncrementSize = NumBits / 8; 469 470 // Divide the stored value in two parts. 471 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 472 SDValue Lo = Val; 473 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 474 475 // Store the two parts 476 SDValue Store1, Store2; 477 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 478 ST->getSrcValue(), SVOffset, NewStoredVT, 479 ST->isVolatile(), ST->isNonTemporal(), Alignment); 480 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 481 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 482 Alignment = MinAlign(Alignment, IncrementSize); 483 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 484 ST->getSrcValue(), SVOffset + IncrementSize, 485 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 486 Alignment); 487 488 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 489} 490 491/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 492static 493SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 494 const TargetLowering &TLI) { 495 int SVOffset = LD->getSrcValueOffset(); 496 SDValue Chain = LD->getChain(); 497 SDValue Ptr = LD->getBasePtr(); 498 EVT VT = LD->getValueType(0); 499 EVT LoadedVT = LD->getMemoryVT(); 500 DebugLoc dl = LD->getDebugLoc(); 501 if (VT.isFloatingPoint() || VT.isVector()) { 502 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 503 if (TLI.isTypeLegal(intVT)) { 504 // Expand to a (misaligned) integer load of the same size, 505 // then bitconvert to floating point or vector. 506 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 507 SVOffset, LD->isVolatile(), 508 LD->isNonTemporal(), LD->getAlignment()); 509 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 510 if (VT.isFloatingPoint() && LoadedVT != VT) 511 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 512 513 SDValue Ops[] = { Result, Chain }; 514 return DAG.getMergeValues(Ops, 2, dl); 515 } else { 516 // Copy the value to a (aligned) stack slot using (unaligned) integer 517 // loads and stores, then do a (aligned) load from the stack slot. 518 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 519 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 520 unsigned RegBytes = RegVT.getSizeInBits() / 8; 521 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 522 523 // Make sure the stack slot is also aligned for the register type. 524 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 525 526 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 527 SmallVector<SDValue, 8> Stores; 528 SDValue StackPtr = StackBase; 529 unsigned Offset = 0; 530 531 // Do all but one copies using the full register width. 532 for (unsigned i = 1; i < NumRegs; i++) { 533 // Load one integer register's worth from the original location. 534 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 535 SVOffset + Offset, LD->isVolatile(), 536 LD->isNonTemporal(), 537 MinAlign(LD->getAlignment(), Offset)); 538 // Follow the load with a store to the stack slot. Remember the store. 539 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 540 NULL, 0, false, false, 0)); 541 // Increment the pointers. 542 Offset += RegBytes; 543 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 544 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 545 Increment); 546 } 547 548 // The last copy may be partial. Do an extending load. 549 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 8 * (LoadedBytes - Offset)); 550 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 551 LD->getSrcValue(), SVOffset + Offset, 552 MemVT, LD->isVolatile(), 553 LD->isNonTemporal(), 554 MinAlign(LD->getAlignment(), Offset)); 555 // Follow the load with a store to the stack slot. Remember the store. 556 // On big-endian machines this requires a truncating store to ensure 557 // that the bits end up in the right place. 558 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 559 NULL, 0, MemVT, false, false, 0)); 560 561 // The order of the stores doesn't matter - say it with a TokenFactor. 562 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 563 Stores.size()); 564 565 // Finally, perform the original load only redirected to the stack slot. 566 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 567 NULL, 0, LoadedVT, false, false, 0); 568 569 // Callers expect a MERGE_VALUES node. 570 SDValue Ops[] = { Load, TF }; 571 return DAG.getMergeValues(Ops, 2, dl); 572 } 573 } 574 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 575 "Unaligned load of unsupported type."); 576 577 // Compute the new VT that is half the size of the old one. This is an 578 // integer MVT. 579 unsigned NumBits = LoadedVT.getSizeInBits(); 580 EVT NewLoadedVT; 581 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 582 NumBits >>= 1; 583 584 unsigned Alignment = LD->getAlignment(); 585 unsigned IncrementSize = NumBits / 8; 586 ISD::LoadExtType HiExtType = LD->getExtensionType(); 587 588 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 589 if (HiExtType == ISD::NON_EXTLOAD) 590 HiExtType = ISD::ZEXTLOAD; 591 592 // Load the value in two parts 593 SDValue Lo, Hi; 594 if (TLI.isLittleEndian()) { 595 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 596 SVOffset, NewLoadedVT, LD->isVolatile(), 597 LD->isNonTemporal(), Alignment); 598 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 599 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 600 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 601 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 602 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize)); 603 } else { 604 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(), 605 SVOffset, NewLoadedVT, LD->isVolatile(), 606 LD->isNonTemporal(), Alignment); 607 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 608 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 609 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(), 610 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 611 LD->isNonTemporal(), MinAlign(Alignment, IncrementSize)); 612 } 613 614 // aggregate the two parts 615 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 616 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 617 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 618 619 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 620 Hi.getValue(1)); 621 622 SDValue Ops[] = { Result, TF }; 623 return DAG.getMergeValues(Ops, 2, dl); 624} 625 626/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 627/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 628/// is necessary to spill the vector being inserted into to memory, perform 629/// the insert there, and then read the result back. 630SDValue SelectionDAGLegalize:: 631PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 632 DebugLoc dl) { 633 SDValue Tmp1 = Vec; 634 SDValue Tmp2 = Val; 635 SDValue Tmp3 = Idx; 636 637 // If the target doesn't support this, we have to spill the input vector 638 // to a temporary stack slot, update the element, then reload it. This is 639 // badness. We could also load the value into a vector register (either 640 // with a "move to register" or "extload into register" instruction, then 641 // permute it into place, if the idx is a constant and if the idx is 642 // supported by the target. 643 EVT VT = Tmp1.getValueType(); 644 EVT EltVT = VT.getVectorElementType(); 645 EVT IdxVT = Tmp3.getValueType(); 646 EVT PtrVT = TLI.getPointerTy(); 647 SDValue StackPtr = DAG.CreateStackTemporary(VT); 648 649 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 650 651 // Store the vector. 652 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 653 PseudoSourceValue::getFixedStack(SPFI), 0, 654 false, false, 0); 655 656 // Truncate or zero extend offset to target pointer type. 657 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 658 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 659 // Add the offset to the index. 660 unsigned EltSize = EltVT.getSizeInBits()/8; 661 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 662 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 663 // Store the scalar value. 664 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 665 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT, 666 false, false, 0); 667 // Load the updated vector. 668 return DAG.getLoad(VT, dl, Ch, StackPtr, 669 PseudoSourceValue::getFixedStack(SPFI), 0, 670 false, false, 0); 671} 672 673 674SDValue SelectionDAGLegalize:: 675ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 676 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 677 // SCALAR_TO_VECTOR requires that the type of the value being inserted 678 // match the element type of the vector being created, except for 679 // integers in which case the inserted value can be over width. 680 EVT EltVT = Vec.getValueType().getVectorElementType(); 681 if (Val.getValueType() == EltVT || 682 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 683 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 684 Vec.getValueType(), Val); 685 686 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 687 // We generate a shuffle of InVec and ScVec, so the shuffle mask 688 // should be 0,1,2,3,4,5... with the appropriate element replaced with 689 // elt 0 of the RHS. 690 SmallVector<int, 8> ShufOps; 691 for (unsigned i = 0; i != NumElts; ++i) 692 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 693 694 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 695 &ShufOps[0]); 696 } 697 } 698 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 699} 700 701SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 702 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 703 // FIXME: We shouldn't do this for TargetConstantFP's. 704 // FIXME: move this to the DAG Combiner! Note that we can't regress due 705 // to phase ordering between legalized code and the dag combiner. This 706 // probably means that we need to integrate dag combiner and legalizer 707 // together. 708 // We generally can't do this one for long doubles. 709 SDValue Tmp1 = ST->getChain(); 710 SDValue Tmp2 = ST->getBasePtr(); 711 SDValue Tmp3; 712 int SVOffset = ST->getSrcValueOffset(); 713 unsigned Alignment = ST->getAlignment(); 714 bool isVolatile = ST->isVolatile(); 715 bool isNonTemporal = ST->isNonTemporal(); 716 DebugLoc dl = ST->getDebugLoc(); 717 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 718 if (CFP->getValueType(0) == MVT::f32 && 719 getTypeAction(MVT::i32) == Legal) { 720 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 721 bitcastToAPInt().zextOrTrunc(32), 722 MVT::i32); 723 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 724 SVOffset, isVolatile, isNonTemporal, Alignment); 725 } else if (CFP->getValueType(0) == MVT::f64) { 726 // If this target supports 64-bit registers, do a single 64-bit store. 727 if (getTypeAction(MVT::i64) == Legal) { 728 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 729 zextOrTrunc(64), MVT::i64); 730 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 731 SVOffset, isVolatile, isNonTemporal, Alignment); 732 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 733 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 734 // stores. If the target supports neither 32- nor 64-bits, this 735 // xform is certainly not worth it. 736 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 737 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 738 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 739 if (TLI.isBigEndian()) std::swap(Lo, Hi); 740 741 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 742 SVOffset, isVolatile, isNonTemporal, Alignment); 743 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 744 DAG.getIntPtrConstant(4)); 745 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 746 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 747 748 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 749 } 750 } 751 } 752 return SDValue(); 753} 754 755/// LegalizeOp - We know that the specified value has a legal type, and 756/// that its operands are legal. Now ensure that the operation itself 757/// is legal, recursively ensuring that the operands' operations remain 758/// legal. 759SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 760 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 761 return Op; 762 763 SDNode *Node = Op.getNode(); 764 DebugLoc dl = Node->getDebugLoc(); 765 766 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 767 assert(getTypeAction(Node->getValueType(i)) == Legal && 768 "Unexpected illegal type!"); 769 770 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 771 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 772 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 773 "Unexpected illegal type!"); 774 775 // Note that LegalizeOp may be reentered even from single-use nodes, which 776 // means that we always must cache transformed nodes. 777 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 778 if (I != LegalizedNodes.end()) return I->second; 779 780 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 781 SDValue Result = Op; 782 bool isCustom = false; 783 784 // Figure out the correct action; the way to query this varies by opcode 785 TargetLowering::LegalizeAction Action; 786 bool SimpleFinishLegalizing = true; 787 switch (Node->getOpcode()) { 788 case ISD::INTRINSIC_W_CHAIN: 789 case ISD::INTRINSIC_WO_CHAIN: 790 case ISD::INTRINSIC_VOID: 791 case ISD::VAARG: 792 case ISD::STACKSAVE: 793 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 794 break; 795 case ISD::SINT_TO_FP: 796 case ISD::UINT_TO_FP: 797 case ISD::EXTRACT_VECTOR_ELT: 798 Action = TLI.getOperationAction(Node->getOpcode(), 799 Node->getOperand(0).getValueType()); 800 break; 801 case ISD::FP_ROUND_INREG: 802 case ISD::SIGN_EXTEND_INREG: { 803 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 804 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 805 break; 806 } 807 case ISD::SELECT_CC: 808 case ISD::SETCC: 809 case ISD::BR_CC: { 810 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 811 Node->getOpcode() == ISD::SETCC ? 2 : 1; 812 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 813 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 814 ISD::CondCode CCCode = 815 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 816 Action = TLI.getCondCodeAction(CCCode, OpVT); 817 if (Action == TargetLowering::Legal) { 818 if (Node->getOpcode() == ISD::SELECT_CC) 819 Action = TLI.getOperationAction(Node->getOpcode(), 820 Node->getValueType(0)); 821 else 822 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 823 } 824 break; 825 } 826 case ISD::LOAD: 827 case ISD::STORE: 828 // FIXME: Model these properly. LOAD and STORE are complicated, and 829 // STORE expects the unlegalized operand in some cases. 830 SimpleFinishLegalizing = false; 831 break; 832 case ISD::CALLSEQ_START: 833 case ISD::CALLSEQ_END: 834 // FIXME: This shouldn't be necessary. These nodes have special properties 835 // dealing with the recursive nature of legalization. Removing this 836 // special case should be done as part of making LegalizeDAG non-recursive. 837 SimpleFinishLegalizing = false; 838 break; 839 case ISD::EXTRACT_ELEMENT: 840 case ISD::FLT_ROUNDS_: 841 case ISD::SADDO: 842 case ISD::SSUBO: 843 case ISD::UADDO: 844 case ISD::USUBO: 845 case ISD::SMULO: 846 case ISD::UMULO: 847 case ISD::FPOWI: 848 case ISD::MERGE_VALUES: 849 case ISD::EH_RETURN: 850 case ISD::FRAME_TO_ARGS_OFFSET: 851 // These operations lie about being legal: when they claim to be legal, 852 // they should actually be expanded. 853 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 854 if (Action == TargetLowering::Legal) 855 Action = TargetLowering::Expand; 856 break; 857 case ISD::TRAMPOLINE: 858 case ISD::FRAMEADDR: 859 case ISD::RETURNADDR: 860 // These operations lie about being legal: when they claim to be legal, 861 // they should actually be custom-lowered. 862 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 863 if (Action == TargetLowering::Legal) 864 Action = TargetLowering::Custom; 865 break; 866 case ISD::BUILD_VECTOR: 867 // A weird case: legalization for BUILD_VECTOR never legalizes the 868 // operands! 869 // FIXME: This really sucks... changing it isn't semantically incorrect, 870 // but it massively pessimizes the code for floating-point BUILD_VECTORs 871 // because ConstantFP operands get legalized into constant pool loads 872 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 873 // though, because BUILD_VECTORS usually get lowered into other nodes 874 // which get legalized properly. 875 SimpleFinishLegalizing = false; 876 break; 877 default: 878 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 879 Action = TargetLowering::Legal; 880 } else { 881 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 882 } 883 break; 884 } 885 886 if (SimpleFinishLegalizing) { 887 SmallVector<SDValue, 8> Ops, ResultVals; 888 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 889 Ops.push_back(LegalizeOp(Node->getOperand(i))); 890 switch (Node->getOpcode()) { 891 default: break; 892 case ISD::BR: 893 case ISD::BRIND: 894 case ISD::BR_JT: 895 case ISD::BR_CC: 896 case ISD::BRCOND: 897 // Branches tweak the chain to include LastCALLSEQ_END 898 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 899 LastCALLSEQ_END); 900 Ops[0] = LegalizeOp(Ops[0]); 901 LastCALLSEQ_END = DAG.getEntryNode(); 902 break; 903 case ISD::SHL: 904 case ISD::SRL: 905 case ISD::SRA: 906 case ISD::ROTL: 907 case ISD::ROTR: 908 // Legalizing shifts/rotates requires adjusting the shift amount 909 // to the appropriate width. 910 if (!Ops[1].getValueType().isVector()) 911 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 912 break; 913 case ISD::SRL_PARTS: 914 case ISD::SRA_PARTS: 915 case ISD::SHL_PARTS: 916 // Legalizing shifts/rotates requires adjusting the shift amount 917 // to the appropriate width. 918 if (!Ops[2].getValueType().isVector()) 919 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2])); 920 break; 921 } 922 923 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(), 924 Ops.size()); 925 switch (Action) { 926 case TargetLowering::Legal: 927 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 928 ResultVals.push_back(Result.getValue(i)); 929 break; 930 case TargetLowering::Custom: 931 // FIXME: The handling for custom lowering with multiple results is 932 // a complete mess. 933 Tmp1 = TLI.LowerOperation(Result, DAG); 934 if (Tmp1.getNode()) { 935 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 936 if (e == 1) 937 ResultVals.push_back(Tmp1); 938 else 939 ResultVals.push_back(Tmp1.getValue(i)); 940 } 941 break; 942 } 943 944 // FALL THROUGH 945 case TargetLowering::Expand: 946 ExpandNode(Result.getNode(), ResultVals); 947 break; 948 case TargetLowering::Promote: 949 PromoteNode(Result.getNode(), ResultVals); 950 break; 951 } 952 if (!ResultVals.empty()) { 953 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 954 if (ResultVals[i] != SDValue(Node, i)) 955 ResultVals[i] = LegalizeOp(ResultVals[i]); 956 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 957 } 958 return ResultVals[Op.getResNo()]; 959 } 960 } 961 962 switch (Node->getOpcode()) { 963 default: 964#ifndef NDEBUG 965 dbgs() << "NODE: "; 966 Node->dump( &DAG); 967 dbgs() << "\n"; 968#endif 969 assert(0 && "Do not know how to legalize this operator!"); 970 971 case ISD::BUILD_VECTOR: 972 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 973 default: assert(0 && "This action is not supported yet!"); 974 case TargetLowering::Custom: 975 Tmp3 = TLI.LowerOperation(Result, DAG); 976 if (Tmp3.getNode()) { 977 Result = Tmp3; 978 break; 979 } 980 // FALLTHROUGH 981 case TargetLowering::Expand: 982 Result = ExpandBUILD_VECTOR(Result.getNode()); 983 break; 984 } 985 break; 986 case ISD::CALLSEQ_START: { 987 SDNode *CallEnd = FindCallEndFromCallStart(Node); 988 989 // Recursively Legalize all of the inputs of the call end that do not lead 990 // to this call start. This ensures that any libcalls that need be inserted 991 // are inserted *before* the CALLSEQ_START. 992 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 993 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 994 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 995 NodesLeadingTo); 996 } 997 998 // Now that we legalized all of the inputs (which may have inserted 999 // libcalls) create the new CALLSEQ_START node. 1000 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1001 1002 // Merge in the last call, to ensure that this call start after the last 1003 // call ended. 1004 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1005 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1006 Tmp1, LastCALLSEQ_END); 1007 Tmp1 = LegalizeOp(Tmp1); 1008 } 1009 1010 // Do not try to legalize the target-specific arguments (#1+). 1011 if (Tmp1 != Node->getOperand(0)) { 1012 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1013 Ops[0] = Tmp1; 1014 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1015 } 1016 1017 // Remember that the CALLSEQ_START is legalized. 1018 AddLegalizedOperand(Op.getValue(0), Result); 1019 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1020 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1021 1022 // Now that the callseq_start and all of the non-call nodes above this call 1023 // sequence have been legalized, legalize the call itself. During this 1024 // process, no libcalls can/will be inserted, guaranteeing that no calls 1025 // can overlap. 1026 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1027 // Note that we are selecting this call! 1028 LastCALLSEQ_END = SDValue(CallEnd, 0); 1029 IsLegalizingCall = true; 1030 1031 // Legalize the call, starting from the CALLSEQ_END. 1032 LegalizeOp(LastCALLSEQ_END); 1033 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1034 return Result; 1035 } 1036 case ISD::CALLSEQ_END: 1037 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1038 // will cause this node to be legalized as well as handling libcalls right. 1039 if (LastCALLSEQ_END.getNode() != Node) { 1040 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1041 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1042 assert(I != LegalizedNodes.end() && 1043 "Legalizing the call start should have legalized this node!"); 1044 return I->second; 1045 } 1046 1047 // Otherwise, the call start has been legalized and everything is going 1048 // according to plan. Just legalize ourselves normally here. 1049 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1050 // Do not try to legalize the target-specific arguments (#1+), except for 1051 // an optional flag input. 1052 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1053 if (Tmp1 != Node->getOperand(0)) { 1054 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1055 Ops[0] = Tmp1; 1056 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1057 } 1058 } else { 1059 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1060 if (Tmp1 != Node->getOperand(0) || 1061 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1062 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1063 Ops[0] = Tmp1; 1064 Ops.back() = Tmp2; 1065 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1066 } 1067 } 1068 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1069 // This finishes up call legalization. 1070 IsLegalizingCall = false; 1071 1072 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1073 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1074 if (Node->getNumValues() == 2) 1075 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1076 return Result.getValue(Op.getResNo()); 1077 case ISD::LOAD: { 1078 LoadSDNode *LD = cast<LoadSDNode>(Node); 1079 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1080 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1081 1082 ISD::LoadExtType ExtType = LD->getExtensionType(); 1083 if (ExtType == ISD::NON_EXTLOAD) { 1084 EVT VT = Node->getValueType(0); 1085 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1086 Tmp3 = Result.getValue(0); 1087 Tmp4 = Result.getValue(1); 1088 1089 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1090 default: assert(0 && "This action is not supported yet!"); 1091 case TargetLowering::Legal: 1092 // If this is an unaligned load and the target doesn't support it, 1093 // expand it. 1094 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1095 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1096 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1097 if (LD->getAlignment() < ABIAlignment){ 1098 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1099 DAG, TLI); 1100 Tmp3 = Result.getOperand(0); 1101 Tmp4 = Result.getOperand(1); 1102 Tmp3 = LegalizeOp(Tmp3); 1103 Tmp4 = LegalizeOp(Tmp4); 1104 } 1105 } 1106 break; 1107 case TargetLowering::Custom: 1108 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1109 if (Tmp1.getNode()) { 1110 Tmp3 = LegalizeOp(Tmp1); 1111 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1112 } 1113 break; 1114 case TargetLowering::Promote: { 1115 // Only promote a load of vector type to another. 1116 assert(VT.isVector() && "Cannot promote this load!"); 1117 // Change base type to a different vector type. 1118 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1119 1120 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1121 LD->getSrcValueOffset(), 1122 LD->isVolatile(), LD->isNonTemporal(), 1123 LD->getAlignment()); 1124 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1125 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1126 break; 1127 } 1128 } 1129 // Since loads produce two values, make sure to remember that we 1130 // legalized both of them. 1131 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1132 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1133 return Op.getResNo() ? Tmp4 : Tmp3; 1134 } else { 1135 EVT SrcVT = LD->getMemoryVT(); 1136 unsigned SrcWidth = SrcVT.getSizeInBits(); 1137 int SVOffset = LD->getSrcValueOffset(); 1138 unsigned Alignment = LD->getAlignment(); 1139 bool isVolatile = LD->isVolatile(); 1140 bool isNonTemporal = LD->isNonTemporal(); 1141 1142 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1143 // Some targets pretend to have an i1 loading operation, and actually 1144 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1145 // bits are guaranteed to be zero; it helps the optimizers understand 1146 // that these bits are zero. It is also useful for EXTLOAD, since it 1147 // tells the optimizers that those bits are undefined. It would be 1148 // nice to have an effective generic way of getting these benefits... 1149 // Until such a way is found, don't insist on promoting i1 here. 1150 (SrcVT != MVT::i1 || 1151 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1152 // Promote to a byte-sized load if not loading an integral number of 1153 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1154 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1155 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 1156 SDValue Ch; 1157 1158 // The extra bits are guaranteed to be zero, since we stored them that 1159 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1160 1161 ISD::LoadExtType NewExtType = 1162 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1163 1164 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 1165 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1166 NVT, isVolatile, isNonTemporal, Alignment); 1167 1168 Ch = Result.getValue(1); // The chain. 1169 1170 if (ExtType == ISD::SEXTLOAD) 1171 // Having the top bits zero doesn't help when sign extending. 1172 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1173 Result.getValueType(), 1174 Result, DAG.getValueType(SrcVT)); 1175 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1176 // All the top bits are guaranteed to be zero - inform the optimizers. 1177 Result = DAG.getNode(ISD::AssertZext, dl, 1178 Result.getValueType(), Result, 1179 DAG.getValueType(SrcVT)); 1180 1181 Tmp1 = LegalizeOp(Result); 1182 Tmp2 = LegalizeOp(Ch); 1183 } else if (SrcWidth & (SrcWidth - 1)) { 1184 // If not loading a power-of-2 number of bits, expand as two loads. 1185 assert(!SrcVT.isVector() && "Unsupported extload!"); 1186 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1187 assert(RoundWidth < SrcWidth); 1188 unsigned ExtraWidth = SrcWidth - RoundWidth; 1189 assert(ExtraWidth < RoundWidth); 1190 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1191 "Load size not an integral number of bytes!"); 1192 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1193 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1194 SDValue Lo, Hi, Ch; 1195 unsigned IncrementSize; 1196 1197 if (TLI.isLittleEndian()) { 1198 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1199 // Load the bottom RoundWidth bits. 1200 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1201 Node->getValueType(0), Tmp1, Tmp2, 1202 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1203 isNonTemporal, Alignment); 1204 1205 // Load the remaining ExtraWidth bits. 1206 IncrementSize = RoundWidth / 8; 1207 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1208 DAG.getIntPtrConstant(IncrementSize)); 1209 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1210 LD->getSrcValue(), SVOffset + IncrementSize, 1211 ExtraVT, isVolatile, isNonTemporal, 1212 MinAlign(Alignment, IncrementSize)); 1213 1214 // Build a factor node to remember that this load is independent of the 1215 // other one. 1216 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1217 Hi.getValue(1)); 1218 1219 // Move the top bits to the right place. 1220 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1221 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1222 1223 // Join the hi and lo parts. 1224 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1225 } else { 1226 // Big endian - avoid unaligned loads. 1227 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1228 // Load the top RoundWidth bits. 1229 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, 1230 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1231 isNonTemporal, Alignment); 1232 1233 // Load the remaining ExtraWidth bits. 1234 IncrementSize = RoundWidth / 8; 1235 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1236 DAG.getIntPtrConstant(IncrementSize)); 1237 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, 1238 Node->getValueType(0), Tmp1, Tmp2, 1239 LD->getSrcValue(), SVOffset + IncrementSize, 1240 ExtraVT, isVolatile, isNonTemporal, 1241 MinAlign(Alignment, IncrementSize)); 1242 1243 // Build a factor node to remember that this load is independent of the 1244 // other one. 1245 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1246 Hi.getValue(1)); 1247 1248 // Move the top bits to the right place. 1249 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1250 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1251 1252 // Join the hi and lo parts. 1253 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1254 } 1255 1256 Tmp1 = LegalizeOp(Result); 1257 Tmp2 = LegalizeOp(Ch); 1258 } else { 1259 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1260 default: assert(0 && "This action is not supported yet!"); 1261 case TargetLowering::Custom: 1262 isCustom = true; 1263 // FALLTHROUGH 1264 case TargetLowering::Legal: 1265 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1266 Tmp1 = Result.getValue(0); 1267 Tmp2 = Result.getValue(1); 1268 1269 if (isCustom) { 1270 Tmp3 = TLI.LowerOperation(Result, DAG); 1271 if (Tmp3.getNode()) { 1272 Tmp1 = LegalizeOp(Tmp3); 1273 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1274 } 1275 } else { 1276 // If this is an unaligned load and the target doesn't support it, 1277 // expand it. 1278 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1279 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1280 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1281 if (LD->getAlignment() < ABIAlignment){ 1282 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1283 DAG, TLI); 1284 Tmp1 = Result.getOperand(0); 1285 Tmp2 = Result.getOperand(1); 1286 Tmp1 = LegalizeOp(Tmp1); 1287 Tmp2 = LegalizeOp(Tmp2); 1288 } 1289 } 1290 } 1291 break; 1292 case TargetLowering::Expand: 1293 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1294 // f128 = EXTLOAD {f32,f64} too 1295 if ((SrcVT == MVT::f32 && (Node->getValueType(0) == MVT::f64 || 1296 Node->getValueType(0) == MVT::f128)) || 1297 (SrcVT == MVT::f64 && Node->getValueType(0) == MVT::f128)) { 1298 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1299 LD->getSrcValueOffset(), 1300 LD->isVolatile(), LD->isNonTemporal(), 1301 LD->getAlignment()); 1302 Result = DAG.getNode(ISD::FP_EXTEND, dl, 1303 Node->getValueType(0), Load); 1304 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1305 Tmp2 = LegalizeOp(Load.getValue(1)); 1306 break; 1307 } 1308 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1309 // Turn the unsupported load into an EXTLOAD followed by an explicit 1310 // zero/sign extend inreg. 1311 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1312 Tmp1, Tmp2, LD->getSrcValue(), 1313 LD->getSrcValueOffset(), SrcVT, 1314 LD->isVolatile(), LD->isNonTemporal(), 1315 LD->getAlignment()); 1316 SDValue ValRes; 1317 if (ExtType == ISD::SEXTLOAD) 1318 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1319 Result.getValueType(), 1320 Result, DAG.getValueType(SrcVT)); 1321 else 1322 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1323 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1324 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1325 break; 1326 } 1327 } 1328 1329 // Since loads produce two values, make sure to remember that we legalized 1330 // both of them. 1331 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1332 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1333 return Op.getResNo() ? Tmp2 : Tmp1; 1334 } 1335 } 1336 case ISD::STORE: { 1337 StoreSDNode *ST = cast<StoreSDNode>(Node); 1338 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1339 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1340 int SVOffset = ST->getSrcValueOffset(); 1341 unsigned Alignment = ST->getAlignment(); 1342 bool isVolatile = ST->isVolatile(); 1343 bool isNonTemporal = ST->isNonTemporal(); 1344 1345 if (!ST->isTruncatingStore()) { 1346 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1347 Result = SDValue(OptStore, 0); 1348 break; 1349 } 1350 1351 { 1352 Tmp3 = LegalizeOp(ST->getValue()); 1353 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1354 ST->getOffset()); 1355 1356 EVT VT = Tmp3.getValueType(); 1357 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1358 default: assert(0 && "This action is not supported yet!"); 1359 case TargetLowering::Legal: 1360 // If this is an unaligned store and the target doesn't support it, 1361 // expand it. 1362 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1363 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1364 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1365 if (ST->getAlignment() < ABIAlignment) 1366 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1367 DAG, TLI); 1368 } 1369 break; 1370 case TargetLowering::Custom: 1371 Tmp1 = TLI.LowerOperation(Result, DAG); 1372 if (Tmp1.getNode()) Result = Tmp1; 1373 break; 1374 case TargetLowering::Promote: 1375 assert(VT.isVector() && "Unknown legal promote case!"); 1376 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1377 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1378 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1379 ST->getSrcValue(), SVOffset, isVolatile, 1380 isNonTemporal, Alignment); 1381 break; 1382 } 1383 break; 1384 } 1385 } else { 1386 Tmp3 = LegalizeOp(ST->getValue()); 1387 1388 EVT StVT = ST->getMemoryVT(); 1389 unsigned StWidth = StVT.getSizeInBits(); 1390 1391 if (StWidth != StVT.getStoreSizeInBits()) { 1392 // Promote to a byte-sized store with upper bits zero if not 1393 // storing an integral number of bytes. For example, promote 1394 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1395 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StVT.getStoreSizeInBits()); 1396 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1397 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1398 SVOffset, NVT, isVolatile, isNonTemporal, 1399 Alignment); 1400 } else if (StWidth & (StWidth - 1)) { 1401 // If not storing a power-of-2 number of bits, expand as two stores. 1402 assert(!StVT.isVector() && "Unsupported truncstore!"); 1403 unsigned RoundWidth = 1 << Log2_32(StWidth); 1404 assert(RoundWidth < StWidth); 1405 unsigned ExtraWidth = StWidth - RoundWidth; 1406 assert(ExtraWidth < RoundWidth); 1407 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1408 "Store size not an integral number of bytes!"); 1409 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1410 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1411 SDValue Lo, Hi; 1412 unsigned IncrementSize; 1413 1414 if (TLI.isLittleEndian()) { 1415 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1416 // Store the bottom RoundWidth bits. 1417 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1418 SVOffset, RoundVT, 1419 isVolatile, isNonTemporal, Alignment); 1420 1421 // Store the remaining ExtraWidth bits. 1422 IncrementSize = RoundWidth / 8; 1423 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1424 DAG.getIntPtrConstant(IncrementSize)); 1425 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1426 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1427 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1428 SVOffset + IncrementSize, ExtraVT, isVolatile, 1429 isNonTemporal, 1430 MinAlign(Alignment, IncrementSize)); 1431 } else { 1432 // Big endian - avoid unaligned stores. 1433 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1434 // Store the top RoundWidth bits. 1435 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1436 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1437 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1438 SVOffset, RoundVT, isVolatile, isNonTemporal, 1439 Alignment); 1440 1441 // Store the remaining ExtraWidth bits. 1442 IncrementSize = RoundWidth / 8; 1443 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1444 DAG.getIntPtrConstant(IncrementSize)); 1445 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1446 SVOffset + IncrementSize, ExtraVT, isVolatile, 1447 isNonTemporal, 1448 MinAlign(Alignment, IncrementSize)); 1449 } 1450 1451 // The order of the stores doesn't matter. 1452 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1453 } else { 1454 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1455 Tmp2 != ST->getBasePtr()) 1456 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 1457 ST->getOffset()); 1458 1459 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1460 default: assert(0 && "This action is not supported yet!"); 1461 case TargetLowering::Legal: 1462 // If this is an unaligned store and the target doesn't support it, 1463 // expand it. 1464 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1465 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1466 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1467 if (ST->getAlignment() < ABIAlignment) 1468 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1469 DAG, TLI); 1470 } 1471 break; 1472 case TargetLowering::Custom: 1473 Result = TLI.LowerOperation(Result, DAG); 1474 break; 1475 case Expand: 1476 // TRUNCSTORE:i16 i32 -> STORE i16 1477 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1478 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1479 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1480 SVOffset, isVolatile, isNonTemporal, 1481 Alignment); 1482 break; 1483 } 1484 } 1485 } 1486 break; 1487 } 1488 } 1489 assert(Result.getValueType() == Op.getValueType() && 1490 "Bad legalization!"); 1491 1492 // Make sure that the generated code is itself legal. 1493 if (Result != Op) 1494 Result = LegalizeOp(Result); 1495 1496 // Note that LegalizeOp may be reentered even from single-use nodes, which 1497 // means that we always must cache transformed nodes. 1498 AddLegalizedOperand(Op, Result); 1499 return Result; 1500} 1501 1502SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1503 SDValue Vec = Op.getOperand(0); 1504 SDValue Idx = Op.getOperand(1); 1505 DebugLoc dl = Op.getDebugLoc(); 1506 // Store the value to a temporary stack slot, then LOAD the returned part. 1507 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1508 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0, 1509 false, false, 0); 1510 1511 // Add the offset to the index. 1512 unsigned EltSize = 1513 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1514 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1515 DAG.getConstant(EltSize, Idx.getValueType())); 1516 1517 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1518 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1519 else 1520 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1521 1522 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1523 1524 if (Op.getValueType().isVector()) 1525 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0, 1526 false, false, 0); 1527 else 1528 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1529 NULL, 0, Vec.getValueType().getVectorElementType(), 1530 false, false, 0); 1531} 1532 1533SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1534 // We can't handle this case efficiently. Allocate a sufficiently 1535 // aligned object on the stack, store each element into it, then load 1536 // the result as a vector. 1537 // Create the stack frame object. 1538 EVT VT = Node->getValueType(0); 1539 EVT EltVT = VT.getVectorElementType(); 1540 DebugLoc dl = Node->getDebugLoc(); 1541 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1542 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1543 const Value *SV = PseudoSourceValue::getFixedStack(FI); 1544 1545 // Emit a store of each element to the stack slot. 1546 SmallVector<SDValue, 8> Stores; 1547 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1548 // Store (in the right endianness) the elements to memory. 1549 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1550 // Ignore undef elements. 1551 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1552 1553 unsigned Offset = TypeByteSize*i; 1554 1555 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1556 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1557 1558 // If the destination vector element type is narrower than the source 1559 // element type, only store the bits necessary. 1560 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1561 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1562 Node->getOperand(i), Idx, SV, Offset, 1563 EltVT, false, false, 0)); 1564 } else 1565 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1566 Node->getOperand(i), Idx, SV, Offset, 1567 false, false, 0)); 1568 } 1569 1570 SDValue StoreChain; 1571 if (!Stores.empty()) // Not all undef elements? 1572 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1573 &Stores[0], Stores.size()); 1574 else 1575 StoreChain = DAG.getEntryNode(); 1576 1577 // Result is a load from the stack slot. 1578 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0, false, false, 0); 1579} 1580 1581SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1582 DebugLoc dl = Node->getDebugLoc(); 1583 SDValue Tmp1 = Node->getOperand(0); 1584 SDValue Tmp2 = Node->getOperand(1); 1585 1586 // Get the sign bit of the RHS. First obtain a value that has the same 1587 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1588 SDValue SignBit; 1589 EVT FloatVT = Tmp2.getValueType(); 1590 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1591 if (isTypeLegal(IVT)) { 1592 // Convert to an integer with the same sign bit. 1593 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1594 } else { 1595 // Store the float to memory, then load the sign part out as an integer. 1596 MVT LoadTy = TLI.getPointerTy(); 1597 // First create a temporary that is aligned for both the load and store. 1598 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1599 // Then store the float to it. 1600 SDValue Ch = 1601 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL, 0, 1602 false, false, 0); 1603 if (TLI.isBigEndian()) { 1604 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1605 // Load out a legal integer with the same sign bit as the float. 1606 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, NULL, 0, false, false, 0); 1607 } else { // Little endian 1608 SDValue LoadPtr = StackPtr; 1609 // The float may be wider than the integer we are going to load. Advance 1610 // the pointer so that the loaded integer will contain the sign bit. 1611 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1612 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1613 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1614 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1615 // Load a legal integer containing the sign bit. 1616 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, NULL, 0, false, false, 0); 1617 // Move the sign bit to the top bit of the loaded integer. 1618 unsigned BitShift = LoadTy.getSizeInBits() - 1619 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1620 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1621 if (BitShift) 1622 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1623 DAG.getConstant(BitShift,TLI.getShiftAmountTy())); 1624 } 1625 } 1626 // Now get the sign bit proper, by seeing whether the value is negative. 1627 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1628 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1629 ISD::SETLT); 1630 // Get the absolute value of the result. 1631 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1632 // Select between the nabs and abs value based on the sign bit of 1633 // the input. 1634 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1635 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1636 AbsVal); 1637} 1638 1639void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1640 SmallVectorImpl<SDValue> &Results) { 1641 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1642 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1643 " not tell us which reg is the stack pointer!"); 1644 DebugLoc dl = Node->getDebugLoc(); 1645 EVT VT = Node->getValueType(0); 1646 SDValue Tmp1 = SDValue(Node, 0); 1647 SDValue Tmp2 = SDValue(Node, 1); 1648 SDValue Tmp3 = Node->getOperand(2); 1649 SDValue Chain = Tmp1.getOperand(0); 1650 1651 // Chain the dynamic stack allocation so that it doesn't modify the stack 1652 // pointer when other instructions are using the stack. 1653 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1654 1655 SDValue Size = Tmp2.getOperand(1); 1656 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1657 Chain = SP.getValue(1); 1658 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1659 unsigned StackAlign = 1660 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1661 if (Align > StackAlign) 1662 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1663 DAG.getConstant(-(uint64_t)Align, VT)); 1664 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1665 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1666 1667 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1668 DAG.getIntPtrConstant(0, true), SDValue()); 1669 1670 Results.push_back(Tmp1); 1671 Results.push_back(Tmp2); 1672} 1673 1674/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1675/// condition code CC on the current target. This routine expands SETCC with 1676/// illegal condition code into AND / OR of multiple SETCC values. 1677void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1678 SDValue &LHS, SDValue &RHS, 1679 SDValue &CC, 1680 DebugLoc dl) { 1681 EVT OpVT = LHS.getValueType(); 1682 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1683 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1684 default: assert(0 && "Unknown condition code action!"); 1685 case TargetLowering::Legal: 1686 // Nothing to do. 1687 break; 1688 case TargetLowering::Expand: { 1689 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1690 unsigned Opc = 0; 1691 switch (CCCode) { 1692 default: assert(0 && "Don't know how to expand this condition!"); 1693 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1694 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1695 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1696 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1697 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1698 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1699 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1700 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1701 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1702 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1703 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1704 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1705 // FIXME: Implement more expansions. 1706 } 1707 1708 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1709 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1710 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1711 RHS = SDValue(); 1712 CC = SDValue(); 1713 break; 1714 } 1715 } 1716} 1717 1718/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1719/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1720/// a load from the stack slot to DestVT, extending it if needed. 1721/// The resultant code need not be legal. 1722SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1723 EVT SlotVT, 1724 EVT DestVT, 1725 DebugLoc dl) { 1726 // Create the stack frame object. 1727 unsigned SrcAlign = 1728 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1729 getTypeForEVT(*DAG.getContext())); 1730 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1731 1732 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1733 int SPFI = StackPtrFI->getIndex(); 1734 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1735 1736 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1737 unsigned SlotSize = SlotVT.getSizeInBits(); 1738 unsigned DestSize = DestVT.getSizeInBits(); 1739 unsigned DestAlign = 1740 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT(*DAG.getContext())); 1741 1742 // Emit a store to the stack slot. Use a truncstore if the input value is 1743 // later than DestVT. 1744 SDValue Store; 1745 1746 if (SrcSize > SlotSize) 1747 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1748 SV, 0, SlotVT, false, false, SrcAlign); 1749 else { 1750 assert(SrcSize == SlotSize && "Invalid store"); 1751 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1752 SV, 0, false, false, SrcAlign); 1753 } 1754 1755 // Result is a load from the stack slot. 1756 if (SlotSize == DestSize) 1757 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, false, 1758 DestAlign); 1759 1760 assert(SlotSize < DestSize && "Unknown extension!"); 1761 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT, 1762 false, false, DestAlign); 1763} 1764 1765SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1766 DebugLoc dl = Node->getDebugLoc(); 1767 // Create a vector sized/aligned stack slot, store the value to element #0, 1768 // then load the whole vector back out. 1769 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1770 1771 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1772 int SPFI = StackPtrFI->getIndex(); 1773 1774 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1775 StackPtr, 1776 PseudoSourceValue::getFixedStack(SPFI), 0, 1777 Node->getValueType(0).getVectorElementType(), 1778 false, false, 0); 1779 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1780 PseudoSourceValue::getFixedStack(SPFI), 0, 1781 false, false, 0); 1782} 1783 1784 1785/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1786/// support the operation, but do support the resultant vector type. 1787SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1788 unsigned NumElems = Node->getNumOperands(); 1789 SDValue Value1, Value2; 1790 DebugLoc dl = Node->getDebugLoc(); 1791 EVT VT = Node->getValueType(0); 1792 EVT OpVT = Node->getOperand(0).getValueType(); 1793 EVT EltVT = VT.getVectorElementType(); 1794 1795 // If the only non-undef value is the low element, turn this into a 1796 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1797 bool isOnlyLowElement = true; 1798 bool MoreThanTwoValues = false; 1799 bool isConstant = true; 1800 for (unsigned i = 0; i < NumElems; ++i) { 1801 SDValue V = Node->getOperand(i); 1802 if (V.getOpcode() == ISD::UNDEF) 1803 continue; 1804 if (i > 0) 1805 isOnlyLowElement = false; 1806 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1807 isConstant = false; 1808 1809 if (!Value1.getNode()) { 1810 Value1 = V; 1811 } else if (!Value2.getNode()) { 1812 if (V != Value1) 1813 Value2 = V; 1814 } else if (V != Value1 && V != Value2) { 1815 MoreThanTwoValues = true; 1816 } 1817 } 1818 1819 if (!Value1.getNode()) 1820 return DAG.getUNDEF(VT); 1821 1822 if (isOnlyLowElement) 1823 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1824 1825 // If all elements are constants, create a load from the constant pool. 1826 if (isConstant) { 1827 std::vector<Constant*> CV; 1828 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1829 if (ConstantFPSDNode *V = 1830 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1831 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1832 } else if (ConstantSDNode *V = 1833 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1834 if (OpVT==EltVT) 1835 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1836 else { 1837 // If OpVT and EltVT don't match, EltVT is not legal and the 1838 // element values have been promoted/truncated earlier. Undo this; 1839 // we don't want a v16i8 to become a v16i32 for example. 1840 const ConstantInt *CI = V->getConstantIntValue(); 1841 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1842 CI->getZExtValue())); 1843 } 1844 } else { 1845 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1846 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1847 CV.push_back(UndefValue::get(OpNTy)); 1848 } 1849 } 1850 Constant *CP = ConstantVector::get(CV); 1851 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1852 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1853 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1854 PseudoSourceValue::getConstantPool(), 0, 1855 false, false, Alignment); 1856 } 1857 1858 if (!MoreThanTwoValues) { 1859 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1860 for (unsigned i = 0; i < NumElems; ++i) { 1861 SDValue V = Node->getOperand(i); 1862 if (V.getOpcode() == ISD::UNDEF) 1863 continue; 1864 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1865 } 1866 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1867 // Get the splatted value into the low element of a vector register. 1868 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1869 SDValue Vec2; 1870 if (Value2.getNode()) 1871 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1872 else 1873 Vec2 = DAG.getUNDEF(VT); 1874 1875 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1876 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1877 } 1878 } 1879 1880 // Otherwise, we can't handle this case efficiently. 1881 return ExpandVectorBuildThroughStack(Node); 1882} 1883 1884// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1885// does not fit into a register, return the lo part and set the hi part to the 1886// by-reg argument. If it does fit into a single register, return the result 1887// and leave the Hi part unset. 1888SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1889 bool isSigned) { 1890 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1891 // The input chain to this libcall is the entry node of the function. 1892 // Legalizing the call will automatically add the previous call to the 1893 // dependence. 1894 SDValue InChain = DAG.getEntryNode(); 1895 1896 TargetLowering::ArgListTy Args; 1897 TargetLowering::ArgListEntry Entry; 1898 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1899 EVT ArgVT = Node->getOperand(i).getValueType(); 1900 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1901 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1902 Entry.isSExt = isSigned; 1903 Entry.isZExt = !isSigned; 1904 Args.push_back(Entry); 1905 } 1906 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1907 TLI.getPointerTy()); 1908 1909 // Splice the libcall in wherever FindInputOutputChains tells us to. 1910 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1911 std::pair<SDValue, SDValue> CallInfo = 1912 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1913 0, TLI.getLibcallCallingConv(LC), false, 1914 /*isReturnValueUsed=*/true, 1915 Callee, Args, DAG, Node->getDebugLoc()); 1916 1917 // Legalize the call sequence, starting with the chain. This will advance 1918 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1919 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1920 LegalizeOp(CallInfo.second); 1921 return CallInfo.first; 1922} 1923 1924SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1925 RTLIB::Libcall Call_F32, 1926 RTLIB::Libcall Call_F64, 1927 RTLIB::Libcall Call_F80, 1928 RTLIB::Libcall Call_PPCF128) { 1929 RTLIB::Libcall LC; 1930 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1931 default: assert(0 && "Unexpected request for libcall!"); 1932 case MVT::f32: LC = Call_F32; break; 1933 case MVT::f64: LC = Call_F64; break; 1934 case MVT::f80: LC = Call_F80; break; 1935 case MVT::ppcf128: LC = Call_PPCF128; break; 1936 } 1937 return ExpandLibCall(LC, Node, false); 1938} 1939 1940SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 1941 RTLIB::Libcall Call_I8, 1942 RTLIB::Libcall Call_I16, 1943 RTLIB::Libcall Call_I32, 1944 RTLIB::Libcall Call_I64, 1945 RTLIB::Libcall Call_I128) { 1946 RTLIB::Libcall LC; 1947 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1948 default: assert(0 && "Unexpected request for libcall!"); 1949 case MVT::i8: LC = Call_I8; break; 1950 case MVT::i16: LC = Call_I16; break; 1951 case MVT::i32: LC = Call_I32; break; 1952 case MVT::i64: LC = Call_I64; break; 1953 case MVT::i128: LC = Call_I128; break; 1954 } 1955 return ExpandLibCall(LC, Node, isSigned); 1956} 1957 1958/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 1959/// INT_TO_FP operation of the specified operand when the target requests that 1960/// we expand it. At this point, we know that the result and operand types are 1961/// legal for the target. 1962SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 1963 SDValue Op0, 1964 EVT DestVT, 1965 DebugLoc dl) { 1966 if (Op0.getValueType() == MVT::i32) { 1967 // simple 32-bit [signed|unsigned] integer to float/double expansion 1968 1969 // Get the stack frame index of a 8 byte buffer. 1970 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 1971 1972 // word offset constant for Hi/Lo address computation 1973 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 1974 // set up Hi and Lo (into buffer) address based on endian 1975 SDValue Hi = StackSlot; 1976 SDValue Lo = DAG.getNode(ISD::ADD, dl, 1977 TLI.getPointerTy(), StackSlot, WordOff); 1978 if (TLI.isLittleEndian()) 1979 std::swap(Hi, Lo); 1980 1981 // if signed map to unsigned space 1982 SDValue Op0Mapped; 1983 if (isSigned) { 1984 // constant used to invert sign bit (signed to unsigned mapping) 1985 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 1986 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 1987 } else { 1988 Op0Mapped = Op0; 1989 } 1990 // store the lo of the constructed double - based on integer input 1991 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 1992 Op0Mapped, Lo, NULL, 0, 1993 false, false, 0); 1994 // initial hi portion of constructed double 1995 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 1996 // store the hi of the constructed double - biased exponent 1997 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0, 1998 false, false, 0); 1999 // load the constructed double 2000 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0, 2001 false, false, 0); 2002 // FP constant to bias correct the final result 2003 SDValue Bias = DAG.getConstantFP(isSigned ? 2004 BitsToDouble(0x4330000080000000ULL) : 2005 BitsToDouble(0x4330000000000000ULL), 2006 MVT::f64); 2007 // subtract the bias 2008 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2009 // final result 2010 SDValue Result; 2011 // handle final rounding 2012 if (DestVT == MVT::f64) { 2013 // do nothing 2014 Result = Sub; 2015 } else if (DestVT.bitsLT(MVT::f64)) { 2016 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2017 DAG.getIntPtrConstant(0)); 2018 } else if (DestVT.bitsGT(MVT::f64)) { 2019 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2020 } 2021 return Result; 2022 } 2023 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2024 2025 // Implementation of unsigned i64 to f64 following the algorithm in 2026 // __floatundidf in compiler_rt. This implementation has the advantage 2027 // of performing rounding correctly, both in the default rounding mode 2028 // and in all alternate rounding modes. 2029 // TODO: Generalize this for use with other types. 2030 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2031 SDValue TwoP52 = 2032 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2033 SDValue TwoP84PlusTwoP52 = 2034 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2035 SDValue TwoP84 = 2036 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2037 2038 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2039 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2040 DAG.getConstant(32, MVT::i64)); 2041 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2042 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2043 SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr); 2044 SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr); 2045 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, TwoP84PlusTwoP52); 2046 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2047 } 2048 2049 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2050 2051 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2052 Op0, DAG.getConstant(0, Op0.getValueType()), 2053 ISD::SETLT); 2054 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2055 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2056 SignSet, Four, Zero); 2057 2058 // If the sign bit of the integer is set, the large number will be treated 2059 // as a negative number. To counteract this, the dynamic code adds an 2060 // offset depending on the data type. 2061 uint64_t FF; 2062 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2063 default: assert(0 && "Unsupported integer type!"); 2064 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2065 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2066 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2067 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2068 } 2069 if (TLI.isLittleEndian()) FF <<= 32; 2070 Constant *FudgeFactor = ConstantInt::get( 2071 Type::getInt64Ty(*DAG.getContext()), FF); 2072 2073 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2074 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2075 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2076 Alignment = std::min(Alignment, 4u); 2077 SDValue FudgeInReg; 2078 if (DestVT == MVT::f32) 2079 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2080 PseudoSourceValue::getConstantPool(), 0, 2081 false, false, Alignment); 2082 else { 2083 FudgeInReg = 2084 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2085 DAG.getEntryNode(), CPIdx, 2086 PseudoSourceValue::getConstantPool(), 0, 2087 MVT::f32, false, false, Alignment)); 2088 } 2089 2090 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2091} 2092 2093/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2094/// *INT_TO_FP operation of the specified operand when the target requests that 2095/// we promote it. At this point, we know that the result and operand types are 2096/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2097/// operation that takes a larger input. 2098SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2099 EVT DestVT, 2100 bool isSigned, 2101 DebugLoc dl) { 2102 // First step, figure out the appropriate *INT_TO_FP operation to use. 2103 EVT NewInTy = LegalOp.getValueType(); 2104 2105 unsigned OpToUse = 0; 2106 2107 // Scan for the appropriate larger type to use. 2108 while (1) { 2109 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2110 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2111 2112 // If the target supports SINT_TO_FP of this type, use it. 2113 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2114 OpToUse = ISD::SINT_TO_FP; 2115 break; 2116 } 2117 if (isSigned) continue; 2118 2119 // If the target supports UINT_TO_FP of this type, use it. 2120 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2121 OpToUse = ISD::UINT_TO_FP; 2122 break; 2123 } 2124 2125 // Otherwise, try a larger type. 2126 } 2127 2128 // Okay, we found the operation and type to use. Zero extend our input to the 2129 // desired type then run the operation on it. 2130 return DAG.getNode(OpToUse, dl, DestVT, 2131 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2132 dl, NewInTy, LegalOp)); 2133} 2134 2135/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2136/// FP_TO_*INT operation of the specified operand when the target requests that 2137/// we promote it. At this point, we know that the result and operand types are 2138/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2139/// operation that returns a larger result. 2140SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2141 EVT DestVT, 2142 bool isSigned, 2143 DebugLoc dl) { 2144 // First step, figure out the appropriate FP_TO*INT operation to use. 2145 EVT NewOutTy = DestVT; 2146 2147 unsigned OpToUse = 0; 2148 2149 // Scan for the appropriate larger type to use. 2150 while (1) { 2151 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2152 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2153 2154 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2155 OpToUse = ISD::FP_TO_SINT; 2156 break; 2157 } 2158 2159 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2160 OpToUse = ISD::FP_TO_UINT; 2161 break; 2162 } 2163 2164 // Otherwise, try a larger type. 2165 } 2166 2167 2168 // Okay, we found the operation and type to use. 2169 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2170 2171 // Truncate the result of the extended FP_TO_*INT operation to the desired 2172 // size. 2173 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2174} 2175 2176/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2177/// 2178SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2179 EVT VT = Op.getValueType(); 2180 EVT SHVT = TLI.getShiftAmountTy(); 2181 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2182 switch (VT.getSimpleVT().SimpleTy) { 2183 default: assert(0 && "Unhandled Expand type in BSWAP!"); 2184 case MVT::i16: 2185 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2186 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2187 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2188 case MVT::i32: 2189 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2190 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2191 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2192 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2193 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2194 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2195 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2196 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2197 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2198 case MVT::i64: 2199 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2200 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2201 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2202 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2203 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2204 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2205 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2206 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2207 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2208 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2209 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2210 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2211 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2212 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2213 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2214 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2215 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2216 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2217 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2218 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2219 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2220 } 2221} 2222 2223/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2224/// 2225SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2226 DebugLoc dl) { 2227 switch (Opc) { 2228 default: assert(0 && "Cannot expand this yet!"); 2229 case ISD::CTPOP: { 2230 static const uint64_t mask[6] = { 2231 0x5555555555555555ULL, 0x3333333333333333ULL, 2232 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2233 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2234 }; 2235 EVT VT = Op.getValueType(); 2236 EVT ShVT = TLI.getShiftAmountTy(); 2237 unsigned len = VT.getSizeInBits(); 2238 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2239 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2240 unsigned EltSize = VT.isVector() ? 2241 VT.getVectorElementType().getSizeInBits() : len; 2242 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2243 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2244 Op = DAG.getNode(ISD::ADD, dl, VT, 2245 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2246 DAG.getNode(ISD::AND, dl, VT, 2247 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2248 Tmp2)); 2249 } 2250 return Op; 2251 } 2252 case ISD::CTLZ: { 2253 // for now, we do this: 2254 // x = x | (x >> 1); 2255 // x = x | (x >> 2); 2256 // ... 2257 // x = x | (x >>16); 2258 // x = x | (x >>32); // for 64-bit input 2259 // return popcount(~x); 2260 // 2261 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2262 EVT VT = Op.getValueType(); 2263 EVT ShVT = TLI.getShiftAmountTy(); 2264 unsigned len = VT.getSizeInBits(); 2265 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2266 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2267 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2268 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2269 } 2270 Op = DAG.getNOT(dl, Op, VT); 2271 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2272 } 2273 case ISD::CTTZ: { 2274 // for now, we use: { return popcount(~x & (x - 1)); } 2275 // unless the target has ctlz but not ctpop, in which case we use: 2276 // { return 32 - nlz(~x & (x-1)); } 2277 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2278 EVT VT = Op.getValueType(); 2279 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2280 DAG.getNOT(dl, Op, VT), 2281 DAG.getNode(ISD::SUB, dl, VT, Op, 2282 DAG.getConstant(1, VT))); 2283 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2284 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2285 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2286 return DAG.getNode(ISD::SUB, dl, VT, 2287 DAG.getConstant(VT.getSizeInBits(), VT), 2288 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2289 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2290 } 2291 } 2292} 2293 2294void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2295 SmallVectorImpl<SDValue> &Results) { 2296 DebugLoc dl = Node->getDebugLoc(); 2297 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2298 switch (Node->getOpcode()) { 2299 case ISD::CTPOP: 2300 case ISD::CTLZ: 2301 case ISD::CTTZ: 2302 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2303 Results.push_back(Tmp1); 2304 break; 2305 case ISD::BSWAP: 2306 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2307 break; 2308 case ISD::FRAMEADDR: 2309 case ISD::RETURNADDR: 2310 case ISD::FRAME_TO_ARGS_OFFSET: 2311 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2312 break; 2313 case ISD::FLT_ROUNDS_: 2314 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2315 break; 2316 case ISD::EH_RETURN: 2317 case ISD::EH_LABEL: 2318 case ISD::PREFETCH: 2319 case ISD::MEMBARRIER: 2320 case ISD::VAEND: 2321 Results.push_back(Node->getOperand(0)); 2322 break; 2323 case ISD::DYNAMIC_STACKALLOC: 2324 ExpandDYNAMIC_STACKALLOC(Node, Results); 2325 break; 2326 case ISD::MERGE_VALUES: 2327 for (unsigned i = 0; i < Node->getNumValues(); i++) 2328 Results.push_back(Node->getOperand(i)); 2329 break; 2330 case ISD::UNDEF: { 2331 EVT VT = Node->getValueType(0); 2332 if (VT.isInteger()) 2333 Results.push_back(DAG.getConstant(0, VT)); 2334 else { 2335 assert(VT.isFloatingPoint() && "Unknown value type!"); 2336 Results.push_back(DAG.getConstantFP(0, VT)); 2337 } 2338 break; 2339 } 2340 case ISD::TRAP: { 2341 // If this operation is not supported, lower it to 'abort()' call 2342 TargetLowering::ArgListTy Args; 2343 std::pair<SDValue, SDValue> CallResult = 2344 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2345 false, false, false, false, 0, CallingConv::C, false, 2346 /*isReturnValueUsed=*/true, 2347 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2348 Args, DAG, dl); 2349 Results.push_back(CallResult.second); 2350 break; 2351 } 2352 case ISD::FP_ROUND: 2353 case ISD::BIT_CONVERT: 2354 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2355 Node->getValueType(0), dl); 2356 Results.push_back(Tmp1); 2357 break; 2358 case ISD::FP_EXTEND: 2359 Tmp1 = EmitStackConvert(Node->getOperand(0), 2360 Node->getOperand(0).getValueType(), 2361 Node->getValueType(0), dl); 2362 Results.push_back(Tmp1); 2363 break; 2364 case ISD::SIGN_EXTEND_INREG: { 2365 // NOTE: we could fall back on load/store here too for targets without 2366 // SAR. However, it is doubtful that any exist. 2367 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2368 EVT VT = Node->getValueType(0); 2369 EVT ShiftAmountTy = TLI.getShiftAmountTy(); 2370 if (VT.isVector()) 2371 ShiftAmountTy = VT; 2372 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2373 ExtraVT.getScalarType().getSizeInBits(); 2374 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2375 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2376 Node->getOperand(0), ShiftCst); 2377 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2378 Results.push_back(Tmp1); 2379 break; 2380 } 2381 case ISD::FP_ROUND_INREG: { 2382 // The only way we can lower this is to turn it into a TRUNCSTORE, 2383 // EXTLOAD pair, targetting a temporary location (a stack slot). 2384 2385 // NOTE: there is a choice here between constantly creating new stack 2386 // slots and always reusing the same one. We currently always create 2387 // new ones, as reuse may inhibit scheduling. 2388 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2389 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2390 Node->getValueType(0), dl); 2391 Results.push_back(Tmp1); 2392 break; 2393 } 2394 case ISD::SINT_TO_FP: 2395 case ISD::UINT_TO_FP: 2396 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2397 Node->getOperand(0), Node->getValueType(0), dl); 2398 Results.push_back(Tmp1); 2399 break; 2400 case ISD::FP_TO_UINT: { 2401 SDValue True, False; 2402 EVT VT = Node->getOperand(0).getValueType(); 2403 EVT NVT = Node->getValueType(0); 2404 const uint64_t zero[] = {0, 0}; 2405 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2406 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2407 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2408 Tmp1 = DAG.getConstantFP(apf, VT); 2409 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2410 Node->getOperand(0), 2411 Tmp1, ISD::SETLT); 2412 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2413 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2414 DAG.getNode(ISD::FSUB, dl, VT, 2415 Node->getOperand(0), Tmp1)); 2416 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2417 DAG.getConstant(x, NVT)); 2418 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2419 Results.push_back(Tmp1); 2420 break; 2421 } 2422 case ISD::VAARG: { 2423 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2424 EVT VT = Node->getValueType(0); 2425 Tmp1 = Node->getOperand(0); 2426 Tmp2 = Node->getOperand(1); 2427 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0, 2428 false, false, 0); 2429 // Increment the pointer, VAList, to the next vaarg 2430 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2431 DAG.getConstant(TLI.getTargetData()-> 2432 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2433 TLI.getPointerTy())); 2434 // Store the incremented VAList to the legalized pointer 2435 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0, 2436 false, false, 0); 2437 // Load the actual argument out of the pointer VAList 2438 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0, 2439 false, false, 0)); 2440 Results.push_back(Results[0].getValue(1)); 2441 break; 2442 } 2443 case ISD::VACOPY: { 2444 // This defaults to loading a pointer from the input and storing it to the 2445 // output, returning the chain. 2446 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2447 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2448 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2449 Node->getOperand(2), VS, 0, false, false, 0); 2450 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0, 2451 false, false, 0); 2452 Results.push_back(Tmp1); 2453 break; 2454 } 2455 case ISD::EXTRACT_VECTOR_ELT: 2456 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2457 // This must be an access of the only element. Return it. 2458 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2459 Node->getOperand(0)); 2460 else 2461 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2462 Results.push_back(Tmp1); 2463 break; 2464 case ISD::EXTRACT_SUBVECTOR: 2465 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2466 break; 2467 case ISD::CONCAT_VECTORS: { 2468 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2469 break; 2470 } 2471 case ISD::SCALAR_TO_VECTOR: 2472 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2473 break; 2474 case ISD::INSERT_VECTOR_ELT: 2475 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2476 Node->getOperand(1), 2477 Node->getOperand(2), dl)); 2478 break; 2479 case ISD::VECTOR_SHUFFLE: { 2480 SmallVector<int, 8> Mask; 2481 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2482 2483 EVT VT = Node->getValueType(0); 2484 EVT EltVT = VT.getVectorElementType(); 2485 unsigned NumElems = VT.getVectorNumElements(); 2486 SmallVector<SDValue, 8> Ops; 2487 for (unsigned i = 0; i != NumElems; ++i) { 2488 if (Mask[i] < 0) { 2489 Ops.push_back(DAG.getUNDEF(EltVT)); 2490 continue; 2491 } 2492 unsigned Idx = Mask[i]; 2493 if (Idx < NumElems) 2494 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2495 Node->getOperand(0), 2496 DAG.getIntPtrConstant(Idx))); 2497 else 2498 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2499 Node->getOperand(1), 2500 DAG.getIntPtrConstant(Idx - NumElems))); 2501 } 2502 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2503 Results.push_back(Tmp1); 2504 break; 2505 } 2506 case ISD::EXTRACT_ELEMENT: { 2507 EVT OpTy = Node->getOperand(0).getValueType(); 2508 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2509 // 1 -> Hi 2510 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2511 DAG.getConstant(OpTy.getSizeInBits()/2, 2512 TLI.getShiftAmountTy())); 2513 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2514 } else { 2515 // 0 -> Lo 2516 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2517 Node->getOperand(0)); 2518 } 2519 Results.push_back(Tmp1); 2520 break; 2521 } 2522 case ISD::STACKSAVE: 2523 // Expand to CopyFromReg if the target set 2524 // StackPointerRegisterToSaveRestore. 2525 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2526 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2527 Node->getValueType(0))); 2528 Results.push_back(Results[0].getValue(1)); 2529 } else { 2530 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2531 Results.push_back(Node->getOperand(0)); 2532 } 2533 break; 2534 case ISD::STACKRESTORE: 2535 // Expand to CopyToReg if the target set 2536 // StackPointerRegisterToSaveRestore. 2537 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2538 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2539 Node->getOperand(1))); 2540 } else { 2541 Results.push_back(Node->getOperand(0)); 2542 } 2543 break; 2544 case ISD::FCOPYSIGN: 2545 Results.push_back(ExpandFCOPYSIGN(Node)); 2546 break; 2547 case ISD::FNEG: 2548 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2549 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2550 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2551 Node->getOperand(0)); 2552 Results.push_back(Tmp1); 2553 break; 2554 case ISD::FABS: { 2555 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2556 EVT VT = Node->getValueType(0); 2557 Tmp1 = Node->getOperand(0); 2558 Tmp2 = DAG.getConstantFP(0.0, VT); 2559 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2560 Tmp1, Tmp2, ISD::SETUGT); 2561 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2562 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2563 Results.push_back(Tmp1); 2564 break; 2565 } 2566 case ISD::FSQRT: 2567 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2568 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2569 break; 2570 case ISD::FSIN: 2571 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2572 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2573 break; 2574 case ISD::FCOS: 2575 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2576 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2577 break; 2578 case ISD::FLOG: 2579 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2580 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2581 break; 2582 case ISD::FLOG2: 2583 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2584 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2585 break; 2586 case ISD::FLOG10: 2587 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2588 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2589 break; 2590 case ISD::FEXP: 2591 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2592 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2593 break; 2594 case ISD::FEXP2: 2595 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2596 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2597 break; 2598 case ISD::FTRUNC: 2599 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2600 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2601 break; 2602 case ISD::FFLOOR: 2603 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2604 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2605 break; 2606 case ISD::FCEIL: 2607 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2608 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2609 break; 2610 case ISD::FRINT: 2611 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2612 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2613 break; 2614 case ISD::FNEARBYINT: 2615 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2616 RTLIB::NEARBYINT_F64, 2617 RTLIB::NEARBYINT_F80, 2618 RTLIB::NEARBYINT_PPCF128)); 2619 break; 2620 case ISD::FPOWI: 2621 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2622 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2623 break; 2624 case ISD::FPOW: 2625 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2626 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2627 break; 2628 case ISD::FDIV: 2629 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2630 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2631 break; 2632 case ISD::FREM: 2633 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2634 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2635 break; 2636 case ISD::FP16_TO_FP32: 2637 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 2638 break; 2639 case ISD::FP32_TO_FP16: 2640 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 2641 break; 2642 case ISD::ConstantFP: { 2643 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2644 // Check to see if this FP immediate is already legal. 2645 // If this is a legal constant, turn it into a TargetConstantFP node. 2646 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 2647 Results.push_back(SDValue(Node, 0)); 2648 else 2649 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2650 break; 2651 } 2652 case ISD::EHSELECTION: { 2653 unsigned Reg = TLI.getExceptionSelectorRegister(); 2654 assert(Reg && "Can't expand to unknown register!"); 2655 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2656 Node->getValueType(0))); 2657 Results.push_back(Results[0].getValue(1)); 2658 break; 2659 } 2660 case ISD::EXCEPTIONADDR: { 2661 unsigned Reg = TLI.getExceptionAddressRegister(); 2662 assert(Reg && "Can't expand to unknown register!"); 2663 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2664 Node->getValueType(0))); 2665 Results.push_back(Results[0].getValue(1)); 2666 break; 2667 } 2668 case ISD::SUB: { 2669 EVT VT = Node->getValueType(0); 2670 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2671 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2672 "Don't know how to expand this subtraction!"); 2673 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2674 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2675 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2676 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2677 break; 2678 } 2679 case ISD::UREM: 2680 case ISD::SREM: { 2681 EVT VT = Node->getValueType(0); 2682 SDVTList VTs = DAG.getVTList(VT, VT); 2683 bool isSigned = Node->getOpcode() == ISD::SREM; 2684 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2685 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2686 Tmp2 = Node->getOperand(0); 2687 Tmp3 = Node->getOperand(1); 2688 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2689 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2690 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2691 // X % Y -> X-X/Y*Y 2692 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2693 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2694 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2695 } else if (isSigned) { 2696 Tmp1 = ExpandIntLibCall(Node, true, 2697 RTLIB::SREM_I8, 2698 RTLIB::SREM_I16, RTLIB::SREM_I32, 2699 RTLIB::SREM_I64, RTLIB::SREM_I128); 2700 } else { 2701 Tmp1 = ExpandIntLibCall(Node, false, 2702 RTLIB::UREM_I8, 2703 RTLIB::UREM_I16, RTLIB::UREM_I32, 2704 RTLIB::UREM_I64, RTLIB::UREM_I128); 2705 } 2706 Results.push_back(Tmp1); 2707 break; 2708 } 2709 case ISD::UDIV: 2710 case ISD::SDIV: { 2711 bool isSigned = Node->getOpcode() == ISD::SDIV; 2712 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2713 EVT VT = Node->getValueType(0); 2714 SDVTList VTs = DAG.getVTList(VT, VT); 2715 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2716 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2717 Node->getOperand(1)); 2718 else if (isSigned) 2719 Tmp1 = ExpandIntLibCall(Node, true, 2720 RTLIB::SDIV_I8, 2721 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2722 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2723 else 2724 Tmp1 = ExpandIntLibCall(Node, false, 2725 RTLIB::UDIV_I8, 2726 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2727 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2728 Results.push_back(Tmp1); 2729 break; 2730 } 2731 case ISD::MULHU: 2732 case ISD::MULHS: { 2733 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2734 ISD::SMUL_LOHI; 2735 EVT VT = Node->getValueType(0); 2736 SDVTList VTs = DAG.getVTList(VT, VT); 2737 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2738 "If this wasn't legal, it shouldn't have been created!"); 2739 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 2740 Node->getOperand(1)); 2741 Results.push_back(Tmp1.getValue(1)); 2742 break; 2743 } 2744 case ISD::MUL: { 2745 EVT VT = Node->getValueType(0); 2746 SDVTList VTs = DAG.getVTList(VT, VT); 2747 // See if multiply or divide can be lowered using two-result operations. 2748 // We just need the low half of the multiply; try both the signed 2749 // and unsigned forms. If the target supports both SMUL_LOHI and 2750 // UMUL_LOHI, form a preference by checking which forms of plain 2751 // MULH it supports. 2752 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 2753 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 2754 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 2755 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 2756 unsigned OpToUse = 0; 2757 if (HasSMUL_LOHI && !HasMULHS) { 2758 OpToUse = ISD::SMUL_LOHI; 2759 } else if (HasUMUL_LOHI && !HasMULHU) { 2760 OpToUse = ISD::UMUL_LOHI; 2761 } else if (HasSMUL_LOHI) { 2762 OpToUse = ISD::SMUL_LOHI; 2763 } else if (HasUMUL_LOHI) { 2764 OpToUse = ISD::UMUL_LOHI; 2765 } 2766 if (OpToUse) { 2767 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 2768 Node->getOperand(1))); 2769 break; 2770 } 2771 Tmp1 = ExpandIntLibCall(Node, false, 2772 RTLIB::MUL_I8, 2773 RTLIB::MUL_I16, RTLIB::MUL_I32, 2774 RTLIB::MUL_I64, RTLIB::MUL_I128); 2775 Results.push_back(Tmp1); 2776 break; 2777 } 2778 case ISD::SADDO: 2779 case ISD::SSUBO: { 2780 SDValue LHS = Node->getOperand(0); 2781 SDValue RHS = Node->getOperand(1); 2782 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 2783 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2784 LHS, RHS); 2785 Results.push_back(Sum); 2786 EVT OType = Node->getValueType(1); 2787 2788 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 2789 2790 // LHSSign -> LHS >= 0 2791 // RHSSign -> RHS >= 0 2792 // SumSign -> Sum >= 0 2793 // 2794 // Add: 2795 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 2796 // Sub: 2797 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 2798 // 2799 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 2800 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 2801 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 2802 Node->getOpcode() == ISD::SADDO ? 2803 ISD::SETEQ : ISD::SETNE); 2804 2805 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 2806 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 2807 2808 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 2809 Results.push_back(Cmp); 2810 break; 2811 } 2812 case ISD::UADDO: 2813 case ISD::USUBO: { 2814 SDValue LHS = Node->getOperand(0); 2815 SDValue RHS = Node->getOperand(1); 2816 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 2817 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2818 LHS, RHS); 2819 Results.push_back(Sum); 2820 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 2821 Node->getOpcode () == ISD::UADDO ? 2822 ISD::SETULT : ISD::SETUGT)); 2823 break; 2824 } 2825 case ISD::UMULO: 2826 case ISD::SMULO: { 2827 EVT VT = Node->getValueType(0); 2828 SDValue LHS = Node->getOperand(0); 2829 SDValue RHS = Node->getOperand(1); 2830 SDValue BottomHalf; 2831 SDValue TopHalf; 2832 static const unsigned Ops[2][3] = 2833 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 2834 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 2835 bool isSigned = Node->getOpcode() == ISD::SMULO; 2836 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 2837 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 2838 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 2839 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 2840 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 2841 RHS); 2842 TopHalf = BottomHalf.getValue(1); 2843 } else { 2844 // FIXME: We should be able to fall back to a libcall with an illegal 2845 // type in some cases. 2846 // Also, we can fall back to a division in some cases, but that's a big 2847 // performance hit in the general case. 2848 assert(TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), 2849 VT.getSizeInBits() * 2)) && 2850 "Don't know how to expand this operation yet!"); 2851 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 2852 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 2853 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 2854 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 2855 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2856 DAG.getIntPtrConstant(0)); 2857 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 2858 DAG.getIntPtrConstant(1)); 2859 } 2860 if (isSigned) { 2861 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); 2862 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 2863 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 2864 ISD::SETNE); 2865 } else { 2866 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 2867 DAG.getConstant(0, VT), ISD::SETNE); 2868 } 2869 Results.push_back(BottomHalf); 2870 Results.push_back(TopHalf); 2871 break; 2872 } 2873 case ISD::BUILD_PAIR: { 2874 EVT PairTy = Node->getValueType(0); 2875 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 2876 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 2877 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 2878 DAG.getConstant(PairTy.getSizeInBits()/2, 2879 TLI.getShiftAmountTy())); 2880 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 2881 break; 2882 } 2883 case ISD::SELECT: 2884 Tmp1 = Node->getOperand(0); 2885 Tmp2 = Node->getOperand(1); 2886 Tmp3 = Node->getOperand(2); 2887 if (Tmp1.getOpcode() == ISD::SETCC) { 2888 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 2889 Tmp2, Tmp3, 2890 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2891 } else { 2892 Tmp1 = DAG.getSelectCC(dl, Tmp1, 2893 DAG.getConstant(0, Tmp1.getValueType()), 2894 Tmp2, Tmp3, ISD::SETNE); 2895 } 2896 Results.push_back(Tmp1); 2897 break; 2898 case ISD::BR_JT: { 2899 SDValue Chain = Node->getOperand(0); 2900 SDValue Table = Node->getOperand(1); 2901 SDValue Index = Node->getOperand(2); 2902 2903 EVT PTy = TLI.getPointerTy(); 2904 2905 const TargetData &TD = *TLI.getTargetData(); 2906 unsigned EntrySize = 2907 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 2908 2909 Index = DAG.getNode(ISD::MUL, dl, PTy, 2910 Index, DAG.getConstant(EntrySize, PTy)); 2911 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2912 2913 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 2914 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 2915 PseudoSourceValue::getJumpTable(), 0, MemVT, 2916 false, false, 0); 2917 Addr = LD; 2918 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2919 // For PIC, the sequence is: 2920 // BRIND(load(Jumptable + index) + RelocBase) 2921 // RelocBase can be JumpTable, GOT or some sort of global base. 2922 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 2923 TLI.getPICJumpTableRelocBase(Table, DAG)); 2924 } 2925 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 2926 Results.push_back(Tmp1); 2927 break; 2928 } 2929 case ISD::BRCOND: 2930 // Expand brcond's setcc into its constituent parts and create a BR_CC 2931 // Node. 2932 Tmp1 = Node->getOperand(0); 2933 Tmp2 = Node->getOperand(1); 2934 if (Tmp2.getOpcode() == ISD::SETCC) { 2935 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 2936 Tmp1, Tmp2.getOperand(2), 2937 Tmp2.getOperand(0), Tmp2.getOperand(1), 2938 Node->getOperand(2)); 2939 } else { 2940 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 2941 DAG.getCondCode(ISD::SETNE), Tmp2, 2942 DAG.getConstant(0, Tmp2.getValueType()), 2943 Node->getOperand(2)); 2944 } 2945 Results.push_back(Tmp1); 2946 break; 2947 case ISD::SETCC: { 2948 Tmp1 = Node->getOperand(0); 2949 Tmp2 = Node->getOperand(1); 2950 Tmp3 = Node->getOperand(2); 2951 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 2952 2953 // If we expanded the SETCC into an AND/OR, return the new node 2954 if (Tmp2.getNode() == 0) { 2955 Results.push_back(Tmp1); 2956 break; 2957 } 2958 2959 // Otherwise, SETCC for the given comparison type must be completely 2960 // illegal; expand it into a SELECT_CC. 2961 EVT VT = Node->getValueType(0); 2962 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 2963 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 2964 Results.push_back(Tmp1); 2965 break; 2966 } 2967 case ISD::SELECT_CC: { 2968 Tmp1 = Node->getOperand(0); // LHS 2969 Tmp2 = Node->getOperand(1); // RHS 2970 Tmp3 = Node->getOperand(2); // True 2971 Tmp4 = Node->getOperand(3); // False 2972 SDValue CC = Node->getOperand(4); 2973 2974 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 2975 Tmp1, Tmp2, CC, dl); 2976 2977 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 2978 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2979 CC = DAG.getCondCode(ISD::SETNE); 2980 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 2981 Tmp3, Tmp4, CC); 2982 Results.push_back(Tmp1); 2983 break; 2984 } 2985 case ISD::BR_CC: { 2986 Tmp1 = Node->getOperand(0); // Chain 2987 Tmp2 = Node->getOperand(2); // LHS 2988 Tmp3 = Node->getOperand(3); // RHS 2989 Tmp4 = Node->getOperand(1); // CC 2990 2991 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 2992 Tmp2, Tmp3, Tmp4, dl); 2993 LastCALLSEQ_END = DAG.getEntryNode(); 2994 2995 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 2996 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 2997 Tmp4 = DAG.getCondCode(ISD::SETNE); 2998 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 2999 Tmp3, Node->getOperand(4)); 3000 Results.push_back(Tmp1); 3001 break; 3002 } 3003 case ISD::GLOBAL_OFFSET_TABLE: 3004 case ISD::GlobalAddress: 3005 case ISD::GlobalTLSAddress: 3006 case ISD::ExternalSymbol: 3007 case ISD::ConstantPool: 3008 case ISD::JumpTable: 3009 case ISD::INTRINSIC_W_CHAIN: 3010 case ISD::INTRINSIC_WO_CHAIN: 3011 case ISD::INTRINSIC_VOID: 3012 // FIXME: Custom lowering for these operations shouldn't return null! 3013 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3014 Results.push_back(SDValue(Node, i)); 3015 break; 3016 } 3017} 3018void SelectionDAGLegalize::PromoteNode(SDNode *Node, 3019 SmallVectorImpl<SDValue> &Results) { 3020 EVT OVT = Node->getValueType(0); 3021 if (Node->getOpcode() == ISD::UINT_TO_FP || 3022 Node->getOpcode() == ISD::SINT_TO_FP || 3023 Node->getOpcode() == ISD::SETCC) { 3024 OVT = Node->getOperand(0).getValueType(); 3025 } 3026 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3027 DebugLoc dl = Node->getDebugLoc(); 3028 SDValue Tmp1, Tmp2, Tmp3; 3029 switch (Node->getOpcode()) { 3030 case ISD::CTTZ: 3031 case ISD::CTLZ: 3032 case ISD::CTPOP: 3033 // Zero extend the argument. 3034 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3035 // Perform the larger operation. 3036 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3037 if (Node->getOpcode() == ISD::CTTZ) { 3038 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3039 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3040 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3041 ISD::SETEQ); 3042 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3043 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3044 } else if (Node->getOpcode() == ISD::CTLZ) { 3045 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3046 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3047 DAG.getConstant(NVT.getSizeInBits() - 3048 OVT.getSizeInBits(), NVT)); 3049 } 3050 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3051 break; 3052 case ISD::BSWAP: { 3053 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3054 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3055 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3056 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3057 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3058 Results.push_back(Tmp1); 3059 break; 3060 } 3061 case ISD::FP_TO_UINT: 3062 case ISD::FP_TO_SINT: 3063 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3064 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3065 Results.push_back(Tmp1); 3066 break; 3067 case ISD::UINT_TO_FP: 3068 case ISD::SINT_TO_FP: 3069 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3070 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3071 Results.push_back(Tmp1); 3072 break; 3073 case ISD::AND: 3074 case ISD::OR: 3075 case ISD::XOR: { 3076 unsigned ExtOp, TruncOp; 3077 if (OVT.isVector()) { 3078 ExtOp = ISD::BIT_CONVERT; 3079 TruncOp = ISD::BIT_CONVERT; 3080 } else { 3081 assert(OVT.isInteger() && "Cannot promote logic operation"); 3082 ExtOp = ISD::ANY_EXTEND; 3083 TruncOp = ISD::TRUNCATE; 3084 } 3085 // Promote each of the values to the new type. 3086 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3087 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3088 // Perform the larger operation, then convert back 3089 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3090 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3091 break; 3092 } 3093 case ISD::SELECT: { 3094 unsigned ExtOp, TruncOp; 3095 if (Node->getValueType(0).isVector()) { 3096 ExtOp = ISD::BIT_CONVERT; 3097 TruncOp = ISD::BIT_CONVERT; 3098 } else if (Node->getValueType(0).isInteger()) { 3099 ExtOp = ISD::ANY_EXTEND; 3100 TruncOp = ISD::TRUNCATE; 3101 } else { 3102 ExtOp = ISD::FP_EXTEND; 3103 TruncOp = ISD::FP_ROUND; 3104 } 3105 Tmp1 = Node->getOperand(0); 3106 // Promote each of the values to the new type. 3107 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3108 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3109 // Perform the larger operation, then round down. 3110 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3111 if (TruncOp != ISD::FP_ROUND) 3112 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3113 else 3114 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3115 DAG.getIntPtrConstant(0)); 3116 Results.push_back(Tmp1); 3117 break; 3118 } 3119 case ISD::VECTOR_SHUFFLE: { 3120 SmallVector<int, 8> Mask; 3121 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3122 3123 // Cast the two input vectors. 3124 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3125 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3126 3127 // Convert the shuffle mask to the right # elements. 3128 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3129 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3130 Results.push_back(Tmp1); 3131 break; 3132 } 3133 case ISD::SETCC: { 3134 unsigned ExtOp = ISD::FP_EXTEND; 3135 if (NVT.isInteger()) { 3136 ISD::CondCode CCCode = 3137 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3138 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3139 } 3140 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3141 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3142 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3143 Tmp1, Tmp2, Node->getOperand(2))); 3144 break; 3145 } 3146 } 3147} 3148 3149// SelectionDAG::Legalize - This is the entry point for the file. 3150// 3151void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) { 3152 /// run - This is the main entry point to this class. 3153 /// 3154 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3155} 3156 3157