LegalizeDAG.cpp revision f08ed5c39b8e628e864ea8ec0923267948978a84
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/Analysis/DebugInfo.h" 20#include "llvm/CodeGen/PseudoSourceValue.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetData.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetOptions.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Function.h" 30#include "llvm/GlobalVariable.h" 31#include "llvm/LLVMContext.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/ADT/DenseMap.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/ADT/SmallPtrSet.h" 40using namespace llvm; 41 42//===----------------------------------------------------------------------===// 43/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 44/// hacks on it until the target machine can handle it. This involves 45/// eliminating value sizes the machine cannot handle (promoting small sizes to 46/// large sizes or splitting up large values into small values) as well as 47/// eliminating operations the machine cannot handle. 48/// 49/// This code also does a small amount of optimization and recognition of idioms 50/// as part of its processing. For example, if a target does not support a 51/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 52/// will attempt merge setcc and brc instructions into brcc's. 53/// 54namespace { 55class SelectionDAGLegalize { 56 const TargetMachine &TM; 57 const TargetLowering &TLI; 58 SelectionDAG &DAG; 59 CodeGenOpt::Level OptLevel; 60 61 // Libcall insertion helpers. 62 63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 64 /// legalized. We use this to ensure that calls are properly serialized 65 /// against each other, including inserted libcalls. 66 SDValue LastCALLSEQ_END; 67 68 /// IsLegalizingCall - This member is used *only* for purposes of providing 69 /// helpful assertions that a libcall isn't created while another call is 70 /// being legalized (which could lead to non-serialized call sequences). 71 bool IsLegalizingCall; 72 73 enum LegalizeAction { 74 Legal, // The target natively supports this operation. 75 Promote, // This operation should be executed in a larger type. 76 Expand // Try to expand this to other ops, otherwise use a libcall. 77 }; 78 79 /// ValueTypeActions - This is a bitvector that contains two bits for each 80 /// value type, where the two bits correspond to the LegalizeAction enum. 81 /// This can be queried with "getTypeAction(VT)". 82 TargetLowering::ValueTypeActionImpl ValueTypeActions; 83 84 /// LegalizedNodes - For nodes that are of legal width, and that have more 85 /// than one use, this map indicates what regularized operand to use. This 86 /// allows us to avoid legalizing the same thing more than once. 87 DenseMap<SDValue, SDValue> LegalizedNodes; 88 89 void AddLegalizedOperand(SDValue From, SDValue To) { 90 LegalizedNodes.insert(std::make_pair(From, To)); 91 // If someone requests legalization of the new node, return itself. 92 if (From != To) 93 LegalizedNodes.insert(std::make_pair(To, To)); 94 } 95 96public: 97 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); 98 99 /// getTypeAction - Return how we should legalize values of this type, either 100 /// it is already legal or we need to expand it into multiple registers of 101 /// smaller integer type, or we need to promote it to a larger type. 102 LegalizeAction getTypeAction(EVT VT) const { 103 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 104 } 105 106 /// isTypeLegal - Return true if this type is legal on this target. 107 /// 108 bool isTypeLegal(EVT VT) const { 109 return getTypeAction(VT) == Legal; 110 } 111 112 void LegalizeDAG(); 113 114private: 115 /// LegalizeOp - We know that the specified value has a legal type. 116 /// Recursively ensure that the operands have legal types, then return the 117 /// result. 118 SDValue LegalizeOp(SDValue O); 119 120 SDValue OptimizeFloatStore(StoreSDNode *ST); 121 122 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 123 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 124 /// is necessary to spill the vector being inserted into to memory, perform 125 /// the insert there, and then read the result back. 126 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 127 SDValue Idx, DebugLoc dl); 128 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 129 SDValue Idx, DebugLoc dl); 130 131 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 132 /// performs the same shuffe in terms of order or result bytes, but on a type 133 /// whose vector element type is narrower than the original shuffle type. 134 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 135 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 136 SDValue N1, SDValue N2, 137 SmallVectorImpl<int> &Mask) const; 138 139 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 140 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 141 142 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 143 DebugLoc dl); 144 145 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 146 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC, 147 SDNode *Node, bool isSigned); 148 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 149 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 150 RTLIB::Libcall Call_PPCF128); 151 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 152 RTLIB::Libcall Call_I8, 153 RTLIB::Libcall Call_I16, 154 RTLIB::Libcall Call_I32, 155 RTLIB::Libcall Call_I64, 156 RTLIB::Libcall Call_I128); 157 158 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 159 SDValue ExpandBUILD_VECTOR(SDNode *Node); 160 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 161 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 162 SmallVectorImpl<SDValue> &Results); 163 SDValue ExpandFCOPYSIGN(SDNode *Node); 164 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 165 DebugLoc dl); 166 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 167 DebugLoc dl); 168 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 169 DebugLoc dl); 170 171 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 172 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 173 174 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 175 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 176 177 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node); 178 179 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 180 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results); 181}; 182} 183 184/// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 185/// performs the same shuffe in terms of order or result bytes, but on a type 186/// whose vector element type is narrower than the original shuffle type. 187/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 188SDValue 189SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 190 SDValue N1, SDValue N2, 191 SmallVectorImpl<int> &Mask) const { 192 unsigned NumMaskElts = VT.getVectorNumElements(); 193 unsigned NumDestElts = NVT.getVectorNumElements(); 194 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 195 196 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 197 198 if (NumEltsGrowth == 1) 199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 200 201 SmallVector<int, 8> NewMask; 202 for (unsigned i = 0; i != NumMaskElts; ++i) { 203 int Idx = Mask[i]; 204 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 205 if (Idx < 0) 206 NewMask.push_back(-1); 207 else 208 NewMask.push_back(Idx * NumEltsGrowth + j); 209 } 210 } 211 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 212 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 213 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 214} 215 216SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, 217 CodeGenOpt::Level ol) 218 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 219 DAG(dag), OptLevel(ol), 220 ValueTypeActions(TLI.getValueTypeActions()) { 221 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 222 "Too many value types for ValueTypeActions to hold!"); 223} 224 225void SelectionDAGLegalize::LegalizeDAG() { 226 LastCALLSEQ_END = DAG.getEntryNode(); 227 IsLegalizingCall = false; 228 229 // The legalize process is inherently a bottom-up recursive process (users 230 // legalize their uses before themselves). Given infinite stack space, we 231 // could just start legalizing on the root and traverse the whole graph. In 232 // practice however, this causes us to run out of stack space on large basic 233 // blocks. To avoid this problem, compute an ordering of the nodes where each 234 // node is only legalized after all of its operands are legalized. 235 DAG.AssignTopologicalOrder(); 236 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 237 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 238 LegalizeOp(SDValue(I, 0)); 239 240 // Finally, it's possible the root changed. Get the new root. 241 SDValue OldRoot = DAG.getRoot(); 242 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 243 DAG.setRoot(LegalizedNodes[OldRoot]); 244 245 LegalizedNodes.clear(); 246 247 // Remove dead nodes now. 248 DAG.RemoveDeadNodes(); 249} 250 251 252/// FindCallEndFromCallStart - Given a chained node that is part of a call 253/// sequence, find the CALLSEQ_END node that terminates the call sequence. 254static SDNode *FindCallEndFromCallStart(SDNode *Node) { 255 if (Node->getOpcode() == ISD::CALLSEQ_END) 256 return Node; 257 if (Node->use_empty()) 258 return 0; // No CallSeqEnd 259 260 // The chain is usually at the end. 261 SDValue TheChain(Node, Node->getNumValues()-1); 262 if (TheChain.getValueType() != MVT::Other) { 263 // Sometimes it's at the beginning. 264 TheChain = SDValue(Node, 0); 265 if (TheChain.getValueType() != MVT::Other) { 266 // Otherwise, hunt for it. 267 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 268 if (Node->getValueType(i) == MVT::Other) { 269 TheChain = SDValue(Node, i); 270 break; 271 } 272 273 // Otherwise, we walked into a node without a chain. 274 if (TheChain.getValueType() != MVT::Other) 275 return 0; 276 } 277 } 278 279 for (SDNode::use_iterator UI = Node->use_begin(), 280 E = Node->use_end(); UI != E; ++UI) { 281 282 // Make sure to only follow users of our token chain. 283 SDNode *User = *UI; 284 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 285 if (User->getOperand(i) == TheChain) 286 if (SDNode *Result = FindCallEndFromCallStart(User)) 287 return Result; 288 } 289 return 0; 290} 291 292/// FindCallStartFromCallEnd - Given a chained node that is part of a call 293/// sequence, find the CALLSEQ_START node that initiates the call sequence. 294static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 295 assert(Node && "Didn't find callseq_start for a call??"); 296 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 297 298 assert(Node->getOperand(0).getValueType() == MVT::Other && 299 "Node doesn't have a token chain argument!"); 300 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 301} 302 303/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 304/// see if any uses can reach Dest. If no dest operands can get to dest, 305/// legalize them, legalize ourself, and return false, otherwise, return true. 306/// 307/// Keep track of the nodes we fine that actually do lead to Dest in 308/// NodesLeadingTo. This avoids retraversing them exponential number of times. 309/// 310bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 311 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 312 if (N == Dest) return true; // N certainly leads to Dest :) 313 314 // If we've already processed this node and it does lead to Dest, there is no 315 // need to reprocess it. 316 if (NodesLeadingTo.count(N)) return true; 317 318 // If the first result of this node has been already legalized, then it cannot 319 // reach N. 320 if (LegalizedNodes.count(SDValue(N, 0))) return false; 321 322 // Okay, this node has not already been legalized. Check and legalize all 323 // operands. If none lead to Dest, then we can legalize this node. 324 bool OperandsLeadToDest = false; 325 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 326 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 327 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, 328 NodesLeadingTo); 329 330 if (OperandsLeadToDest) { 331 NodesLeadingTo.insert(N); 332 return true; 333 } 334 335 // Okay, this node looks safe, legalize it and return false. 336 LegalizeOp(SDValue(N, 0)); 337 return false; 338} 339 340/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 341/// a load from the constant pool. 342static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 343 SelectionDAG &DAG, const TargetLowering &TLI) { 344 bool Extend = false; 345 DebugLoc dl = CFP->getDebugLoc(); 346 347 // If a FP immediate is precise when represented as a float and if the 348 // target can do an extending load from float to double, we put it into 349 // the constant pool as a float, even if it's is statically typed as a 350 // double. This shrinks FP constants and canonicalizes them for targets where 351 // an FP extending load is the same cost as a normal load (such as on the x87 352 // fp stack or PPC FP unit). 353 EVT VT = CFP->getValueType(0); 354 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 355 if (!UseCP) { 356 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 357 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 358 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 359 } 360 361 EVT OrigVT = VT; 362 EVT SVT = VT; 363 while (SVT != MVT::f32) { 364 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 365 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) && 366 // Only do this if the target has a native EXTLOAD instruction from 367 // smaller type. 368 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 369 TLI.ShouldShrinkFPConstant(OrigVT)) { 370 const Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 371 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 372 VT = SVT; 373 Extend = true; 374 } 375 } 376 377 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 378 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 379 if (Extend) 380 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, dl, 381 DAG.getEntryNode(), 382 CPIdx, PseudoSourceValue::getConstantPool(), 383 0, VT, false, false, Alignment); 384 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 385 PseudoSourceValue::getConstantPool(), 0, false, false, 386 Alignment); 387} 388 389/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 390static 391SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 392 const TargetLowering &TLI) { 393 SDValue Chain = ST->getChain(); 394 SDValue Ptr = ST->getBasePtr(); 395 SDValue Val = ST->getValue(); 396 EVT VT = Val.getValueType(); 397 int Alignment = ST->getAlignment(); 398 int SVOffset = ST->getSrcValueOffset(); 399 DebugLoc dl = ST->getDebugLoc(); 400 if (ST->getMemoryVT().isFloatingPoint() || 401 ST->getMemoryVT().isVector()) { 402 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 403 if (TLI.isTypeLegal(intVT)) { 404 // Expand to a bitconvert of the value to the integer type of the 405 // same size, then a (misaligned) int store. 406 // FIXME: Does not handle truncating floating point stores! 407 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val); 408 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(), 409 SVOffset, ST->isVolatile(), ST->isNonTemporal(), 410 Alignment); 411 } else { 412 // Do a (aligned) store to a stack slot, then copy from the stack slot 413 // to the final destination using (unaligned) integer loads and stores. 414 EVT StoredVT = ST->getMemoryVT(); 415 EVT RegVT = 416 TLI.getRegisterType(*DAG.getContext(), 417 EVT::getIntegerVT(*DAG.getContext(), 418 StoredVT.getSizeInBits())); 419 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 420 unsigned RegBytes = RegVT.getSizeInBits() / 8; 421 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 422 423 // Make sure the stack slot is also aligned for the register type. 424 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 425 426 // Perform the original store, only redirected to the stack slot. 427 SDValue Store = DAG.getTruncStore(Chain, dl, 428 Val, StackPtr, NULL, 0, StoredVT, 429 false, false, 0); 430 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 431 SmallVector<SDValue, 8> Stores; 432 unsigned Offset = 0; 433 434 // Do all but one copies using the full register width. 435 for (unsigned i = 1; i < NumRegs; i++) { 436 // Load one integer register's worth from the stack slot. 437 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0, 438 false, false, 0); 439 // Store it to the final location. Remember the store. 440 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 441 ST->getSrcValue(), SVOffset + Offset, 442 ST->isVolatile(), ST->isNonTemporal(), 443 MinAlign(ST->getAlignment(), Offset))); 444 // Increment the pointers. 445 Offset += RegBytes; 446 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 447 Increment); 448 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 449 } 450 451 // The last store may be partial. Do a truncating store. On big-endian 452 // machines this requires an extending load from the stack slot to ensure 453 // that the bits are in the right place. 454 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 455 8 * (StoredBytes - Offset)); 456 457 // Load from the stack slot. 458 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Store, StackPtr, 459 NULL, 0, MemVT, false, false, 0); 460 461 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 462 ST->getSrcValue(), SVOffset + Offset, 463 MemVT, ST->isVolatile(), 464 ST->isNonTemporal(), 465 MinAlign(ST->getAlignment(), Offset))); 466 // The order of the stores doesn't matter - say it with a TokenFactor. 467 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 468 Stores.size()); 469 } 470 } 471 assert(ST->getMemoryVT().isInteger() && 472 !ST->getMemoryVT().isVector() && 473 "Unaligned store of unknown type."); 474 // Get the half-size VT 475 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 476 int NumBits = NewStoredVT.getSizeInBits(); 477 int IncrementSize = NumBits / 8; 478 479 // Divide the stored value in two parts. 480 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 481 SDValue Lo = Val; 482 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 483 484 // Store the two parts 485 SDValue Store1, Store2; 486 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 487 ST->getSrcValue(), SVOffset, NewStoredVT, 488 ST->isVolatile(), ST->isNonTemporal(), Alignment); 489 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 490 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 491 Alignment = MinAlign(Alignment, IncrementSize); 492 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 493 ST->getSrcValue(), SVOffset + IncrementSize, 494 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 495 Alignment); 496 497 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 498} 499 500/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 501static 502SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 503 const TargetLowering &TLI) { 504 int SVOffset = LD->getSrcValueOffset(); 505 SDValue Chain = LD->getChain(); 506 SDValue Ptr = LD->getBasePtr(); 507 EVT VT = LD->getValueType(0); 508 EVT LoadedVT = LD->getMemoryVT(); 509 DebugLoc dl = LD->getDebugLoc(); 510 if (VT.isFloatingPoint() || VT.isVector()) { 511 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 512 if (TLI.isTypeLegal(intVT)) { 513 // Expand to a (misaligned) integer load of the same size, 514 // then bitconvert to floating point or vector. 515 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(), 516 SVOffset, LD->isVolatile(), 517 LD->isNonTemporal(), LD->getAlignment()); 518 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad); 519 if (VT.isFloatingPoint() && LoadedVT != VT) 520 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result); 521 522 SDValue Ops[] = { Result, Chain }; 523 return DAG.getMergeValues(Ops, 2, dl); 524 } else { 525 // Copy the value to a (aligned) stack slot using (unaligned) integer 526 // loads and stores, then do a (aligned) load from the stack slot. 527 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 528 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 529 unsigned RegBytes = RegVT.getSizeInBits() / 8; 530 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 531 532 // Make sure the stack slot is also aligned for the register type. 533 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 534 535 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 536 SmallVector<SDValue, 8> Stores; 537 SDValue StackPtr = StackBase; 538 unsigned Offset = 0; 539 540 // Do all but one copies using the full register width. 541 for (unsigned i = 1; i < NumRegs; i++) { 542 // Load one integer register's worth from the original location. 543 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(), 544 SVOffset + Offset, LD->isVolatile(), 545 LD->isNonTemporal(), 546 MinAlign(LD->getAlignment(), Offset)); 547 // Follow the load with a store to the stack slot. Remember the store. 548 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 549 NULL, 0, false, false, 0)); 550 // Increment the pointers. 551 Offset += RegBytes; 552 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 553 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 554 Increment); 555 } 556 557 // The last copy may be partial. Do an extending load. 558 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 559 8 * (LoadedBytes - Offset)); 560 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Chain, Ptr, 561 LD->getSrcValue(), SVOffset + Offset, 562 MemVT, LD->isVolatile(), 563 LD->isNonTemporal(), 564 MinAlign(LD->getAlignment(), Offset)); 565 // Follow the load with a store to the stack slot. Remember the store. 566 // On big-endian machines this requires a truncating store to ensure 567 // that the bits end up in the right place. 568 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 569 NULL, 0, MemVT, false, false, 0)); 570 571 // The order of the stores doesn't matter - say it with a TokenFactor. 572 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 573 Stores.size()); 574 575 // Finally, perform the original load only redirected to the stack slot. 576 Load = DAG.getExtLoad(LD->getExtensionType(), VT, dl, TF, StackBase, 577 NULL, 0, LoadedVT, false, false, 0); 578 579 // Callers expect a MERGE_VALUES node. 580 SDValue Ops[] = { Load, TF }; 581 return DAG.getMergeValues(Ops, 2, dl); 582 } 583 } 584 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 585 "Unaligned load of unsupported type."); 586 587 // Compute the new VT that is half the size of the old one. This is an 588 // integer MVT. 589 unsigned NumBits = LoadedVT.getSizeInBits(); 590 EVT NewLoadedVT; 591 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 592 NumBits >>= 1; 593 594 unsigned Alignment = LD->getAlignment(); 595 unsigned IncrementSize = NumBits / 8; 596 ISD::LoadExtType HiExtType = LD->getExtensionType(); 597 598 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 599 if (HiExtType == ISD::NON_EXTLOAD) 600 HiExtType = ISD::ZEXTLOAD; 601 602 // Load the value in two parts 603 SDValue Lo, Hi; 604 if (TLI.isLittleEndian()) { 605 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getSrcValue(), 606 SVOffset, NewLoadedVT, LD->isVolatile(), 607 LD->isNonTemporal(), Alignment); 608 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 609 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 610 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getSrcValue(), 611 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 612 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 613 } else { 614 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getSrcValue(), 615 SVOffset, NewLoadedVT, LD->isVolatile(), 616 LD->isNonTemporal(), Alignment); 617 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 618 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 619 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getSrcValue(), 620 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 621 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 622 } 623 624 // aggregate the two parts 625 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 626 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 627 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 628 629 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 630 Hi.getValue(1)); 631 632 SDValue Ops[] = { Result, TF }; 633 return DAG.getMergeValues(Ops, 2, dl); 634} 635 636/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 637/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 638/// is necessary to spill the vector being inserted into to memory, perform 639/// the insert there, and then read the result back. 640SDValue SelectionDAGLegalize:: 641PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 642 DebugLoc dl) { 643 SDValue Tmp1 = Vec; 644 SDValue Tmp2 = Val; 645 SDValue Tmp3 = Idx; 646 647 // If the target doesn't support this, we have to spill the input vector 648 // to a temporary stack slot, update the element, then reload it. This is 649 // badness. We could also load the value into a vector register (either 650 // with a "move to register" or "extload into register" instruction, then 651 // permute it into place, if the idx is a constant and if the idx is 652 // supported by the target. 653 EVT VT = Tmp1.getValueType(); 654 EVT EltVT = VT.getVectorElementType(); 655 EVT IdxVT = Tmp3.getValueType(); 656 EVT PtrVT = TLI.getPointerTy(); 657 SDValue StackPtr = DAG.CreateStackTemporary(VT); 658 659 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 660 661 // Store the vector. 662 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 663 PseudoSourceValue::getFixedStack(SPFI), 0, 664 false, false, 0); 665 666 // Truncate or zero extend offset to target pointer type. 667 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 668 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 669 // Add the offset to the index. 670 unsigned EltSize = EltVT.getSizeInBits()/8; 671 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 672 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 673 // Store the scalar value. 674 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, 675 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT, 676 false, false, 0); 677 // Load the updated vector. 678 return DAG.getLoad(VT, dl, Ch, StackPtr, 679 PseudoSourceValue::getFixedStack(SPFI), 0, 680 false, false, 0); 681} 682 683 684SDValue SelectionDAGLegalize:: 685ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 686 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 687 // SCALAR_TO_VECTOR requires that the type of the value being inserted 688 // match the element type of the vector being created, except for 689 // integers in which case the inserted value can be over width. 690 EVT EltVT = Vec.getValueType().getVectorElementType(); 691 if (Val.getValueType() == EltVT || 692 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 693 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 694 Vec.getValueType(), Val); 695 696 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 697 // We generate a shuffle of InVec and ScVec, so the shuffle mask 698 // should be 0,1,2,3,4,5... with the appropriate element replaced with 699 // elt 0 of the RHS. 700 SmallVector<int, 8> ShufOps; 701 for (unsigned i = 0; i != NumElts; ++i) 702 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 703 704 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 705 &ShufOps[0]); 706 } 707 } 708 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 709} 710 711SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 712 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 713 // FIXME: We shouldn't do this for TargetConstantFP's. 714 // FIXME: move this to the DAG Combiner! Note that we can't regress due 715 // to phase ordering between legalized code and the dag combiner. This 716 // probably means that we need to integrate dag combiner and legalizer 717 // together. 718 // We generally can't do this one for long doubles. 719 SDValue Tmp1 = ST->getChain(); 720 SDValue Tmp2 = ST->getBasePtr(); 721 SDValue Tmp3; 722 int SVOffset = ST->getSrcValueOffset(); 723 unsigned Alignment = ST->getAlignment(); 724 bool isVolatile = ST->isVolatile(); 725 bool isNonTemporal = ST->isNonTemporal(); 726 DebugLoc dl = ST->getDebugLoc(); 727 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 728 if (CFP->getValueType(0) == MVT::f32 && 729 getTypeAction(MVT::i32) == Legal) { 730 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 731 bitcastToAPInt().zextOrTrunc(32), 732 MVT::i32); 733 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 734 SVOffset, isVolatile, isNonTemporal, Alignment); 735 } else if (CFP->getValueType(0) == MVT::f64) { 736 // If this target supports 64-bit registers, do a single 64-bit store. 737 if (getTypeAction(MVT::i64) == Legal) { 738 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 739 zextOrTrunc(64), MVT::i64); 740 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 741 SVOffset, isVolatile, isNonTemporal, Alignment); 742 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 743 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 744 // stores. If the target supports neither 32- nor 64-bits, this 745 // xform is certainly not worth it. 746 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 747 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 748 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 749 if (TLI.isBigEndian()) std::swap(Lo, Hi); 750 751 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), 752 SVOffset, isVolatile, isNonTemporal, Alignment); 753 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 754 DAG.getIntPtrConstant(4)); 755 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 756 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 757 758 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 759 } 760 } 761 } 762 return SDValue(); 763} 764 765/// LegalizeOp - We know that the specified value has a legal type, and 766/// that its operands are legal. Now ensure that the operation itself 767/// is legal, recursively ensuring that the operands' operations remain 768/// legal. 769SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 770 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 771 return Op; 772 773 SDNode *Node = Op.getNode(); 774 DebugLoc dl = Node->getDebugLoc(); 775 776 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 777 assert(getTypeAction(Node->getValueType(i)) == Legal && 778 "Unexpected illegal type!"); 779 780 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 781 assert((isTypeLegal(Node->getOperand(i).getValueType()) || 782 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 783 "Unexpected illegal type!"); 784 785 // Note that LegalizeOp may be reentered even from single-use nodes, which 786 // means that we always must cache transformed nodes. 787 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 788 if (I != LegalizedNodes.end()) return I->second; 789 790 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 791 SDValue Result = Op; 792 bool isCustom = false; 793 794 // Figure out the correct action; the way to query this varies by opcode 795 TargetLowering::LegalizeAction Action; 796 bool SimpleFinishLegalizing = true; 797 switch (Node->getOpcode()) { 798 case ISD::INTRINSIC_W_CHAIN: 799 case ISD::INTRINSIC_WO_CHAIN: 800 case ISD::INTRINSIC_VOID: 801 case ISD::VAARG: 802 case ISD::STACKSAVE: 803 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 804 break; 805 case ISD::SINT_TO_FP: 806 case ISD::UINT_TO_FP: 807 case ISD::EXTRACT_VECTOR_ELT: 808 Action = TLI.getOperationAction(Node->getOpcode(), 809 Node->getOperand(0).getValueType()); 810 break; 811 case ISD::FP_ROUND_INREG: 812 case ISD::SIGN_EXTEND_INREG: { 813 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 814 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 815 break; 816 } 817 case ISD::SELECT_CC: 818 case ISD::SETCC: 819 case ISD::BR_CC: { 820 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 821 Node->getOpcode() == ISD::SETCC ? 2 : 1; 822 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 823 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 824 ISD::CondCode CCCode = 825 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 826 Action = TLI.getCondCodeAction(CCCode, OpVT); 827 if (Action == TargetLowering::Legal) { 828 if (Node->getOpcode() == ISD::SELECT_CC) 829 Action = TLI.getOperationAction(Node->getOpcode(), 830 Node->getValueType(0)); 831 else 832 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 833 } 834 break; 835 } 836 case ISD::LOAD: 837 case ISD::STORE: 838 // FIXME: Model these properly. LOAD and STORE are complicated, and 839 // STORE expects the unlegalized operand in some cases. 840 SimpleFinishLegalizing = false; 841 break; 842 case ISD::CALLSEQ_START: 843 case ISD::CALLSEQ_END: 844 // FIXME: This shouldn't be necessary. These nodes have special properties 845 // dealing with the recursive nature of legalization. Removing this 846 // special case should be done as part of making LegalizeDAG non-recursive. 847 SimpleFinishLegalizing = false; 848 break; 849 case ISD::EXTRACT_ELEMENT: 850 case ISD::FLT_ROUNDS_: 851 case ISD::SADDO: 852 case ISD::SSUBO: 853 case ISD::UADDO: 854 case ISD::USUBO: 855 case ISD::SMULO: 856 case ISD::UMULO: 857 case ISD::FPOWI: 858 case ISD::MERGE_VALUES: 859 case ISD::EH_RETURN: 860 case ISD::FRAME_TO_ARGS_OFFSET: 861 case ISD::EH_SJLJ_SETJMP: 862 case ISD::EH_SJLJ_LONGJMP: 863 // These operations lie about being legal: when they claim to be legal, 864 // they should actually be expanded. 865 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 866 if (Action == TargetLowering::Legal) 867 Action = TargetLowering::Expand; 868 break; 869 case ISD::TRAMPOLINE: 870 case ISD::FRAMEADDR: 871 case ISD::RETURNADDR: 872 // These operations lie about being legal: when they claim to be legal, 873 // they should actually be custom-lowered. 874 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 875 if (Action == TargetLowering::Legal) 876 Action = TargetLowering::Custom; 877 break; 878 case ISD::BUILD_VECTOR: 879 // A weird case: legalization for BUILD_VECTOR never legalizes the 880 // operands! 881 // FIXME: This really sucks... changing it isn't semantically incorrect, 882 // but it massively pessimizes the code for floating-point BUILD_VECTORs 883 // because ConstantFP operands get legalized into constant pool loads 884 // before the BUILD_VECTOR code can see them. It doesn't usually bite, 885 // though, because BUILD_VECTORS usually get lowered into other nodes 886 // which get legalized properly. 887 SimpleFinishLegalizing = false; 888 break; 889 default: 890 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 891 Action = TargetLowering::Legal; 892 } else { 893 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 894 } 895 break; 896 } 897 898 if (SimpleFinishLegalizing) { 899 SmallVector<SDValue, 8> Ops, ResultVals; 900 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 901 Ops.push_back(LegalizeOp(Node->getOperand(i))); 902 switch (Node->getOpcode()) { 903 default: break; 904 case ISD::BR: 905 case ISD::BRIND: 906 case ISD::BR_JT: 907 case ISD::BR_CC: 908 case ISD::BRCOND: 909 // Branches tweak the chain to include LastCALLSEQ_END 910 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], 911 LastCALLSEQ_END); 912 Ops[0] = LegalizeOp(Ops[0]); 913 LastCALLSEQ_END = DAG.getEntryNode(); 914 break; 915 case ISD::SHL: 916 case ISD::SRL: 917 case ISD::SRA: 918 case ISD::ROTL: 919 case ISD::ROTR: 920 // Legalizing shifts/rotates requires adjusting the shift amount 921 // to the appropriate width. 922 if (!Ops[1].getValueType().isVector()) 923 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1])); 924 break; 925 case ISD::SRL_PARTS: 926 case ISD::SRA_PARTS: 927 case ISD::SHL_PARTS: 928 // Legalizing shifts/rotates requires adjusting the shift amount 929 // to the appropriate width. 930 if (!Ops[2].getValueType().isVector()) 931 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2])); 932 break; 933 } 934 935 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(), 936 Ops.size()), 0); 937 switch (Action) { 938 case TargetLowering::Legal: 939 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 940 ResultVals.push_back(Result.getValue(i)); 941 break; 942 case TargetLowering::Custom: 943 // FIXME: The handling for custom lowering with multiple results is 944 // a complete mess. 945 Tmp1 = TLI.LowerOperation(Result, DAG); 946 if (Tmp1.getNode()) { 947 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 948 if (e == 1) 949 ResultVals.push_back(Tmp1); 950 else 951 ResultVals.push_back(Tmp1.getValue(i)); 952 } 953 break; 954 } 955 956 // FALL THROUGH 957 case TargetLowering::Expand: 958 ExpandNode(Result.getNode(), ResultVals); 959 break; 960 case TargetLowering::Promote: 961 PromoteNode(Result.getNode(), ResultVals); 962 break; 963 } 964 if (!ResultVals.empty()) { 965 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) { 966 if (ResultVals[i] != SDValue(Node, i)) 967 ResultVals[i] = LegalizeOp(ResultVals[i]); 968 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]); 969 } 970 return ResultVals[Op.getResNo()]; 971 } 972 } 973 974 switch (Node->getOpcode()) { 975 default: 976#ifndef NDEBUG 977 dbgs() << "NODE: "; 978 Node->dump( &DAG); 979 dbgs() << "\n"; 980#endif 981 assert(0 && "Do not know how to legalize this operator!"); 982 983 case ISD::BUILD_VECTOR: 984 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 985 default: assert(0 && "This action is not supported yet!"); 986 case TargetLowering::Custom: 987 Tmp3 = TLI.LowerOperation(Result, DAG); 988 if (Tmp3.getNode()) { 989 Result = Tmp3; 990 break; 991 } 992 // FALLTHROUGH 993 case TargetLowering::Expand: 994 Result = ExpandBUILD_VECTOR(Result.getNode()); 995 break; 996 } 997 break; 998 case ISD::CALLSEQ_START: { 999 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1000 1001 // Recursively Legalize all of the inputs of the call end that do not lead 1002 // to this call start. This ensures that any libcalls that need be inserted 1003 // are inserted *before* the CALLSEQ_START. 1004 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1005 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1006 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1007 NodesLeadingTo); 1008 } 1009 1010 // Now that we have legalized all of the inputs (which may have inserted 1011 // libcalls), create the new CALLSEQ_START node. 1012 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1013 1014 // Merge in the last call to ensure that this call starts after the last 1015 // call ended. 1016 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1017 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1018 Tmp1, LastCALLSEQ_END); 1019 Tmp1 = LegalizeOp(Tmp1); 1020 } 1021 1022 // Do not try to legalize the target-specific arguments (#1+). 1023 if (Tmp1 != Node->getOperand(0)) { 1024 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1025 Ops[0] = Tmp1; 1026 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0], 1027 Ops.size()), Result.getResNo()); 1028 } 1029 1030 // Remember that the CALLSEQ_START is legalized. 1031 AddLegalizedOperand(Op.getValue(0), Result); 1032 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1033 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1034 1035 // Now that the callseq_start and all of the non-call nodes above this call 1036 // sequence have been legalized, legalize the call itself. During this 1037 // process, no libcalls can/will be inserted, guaranteeing that no calls 1038 // can overlap. 1039 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1040 // Note that we are selecting this call! 1041 LastCALLSEQ_END = SDValue(CallEnd, 0); 1042 IsLegalizingCall = true; 1043 1044 // Legalize the call, starting from the CALLSEQ_END. 1045 LegalizeOp(LastCALLSEQ_END); 1046 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1047 return Result; 1048 } 1049 case ISD::CALLSEQ_END: 1050 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1051 // will cause this node to be legalized as well as handling libcalls right. 1052 if (LastCALLSEQ_END.getNode() != Node) { 1053 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1054 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1055 assert(I != LegalizedNodes.end() && 1056 "Legalizing the call start should have legalized this node!"); 1057 return I->second; 1058 } 1059 1060 // Otherwise, the call start has been legalized and everything is going 1061 // according to plan. Just legalize ourselves normally here. 1062 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1063 // Do not try to legalize the target-specific arguments (#1+), except for 1064 // an optional flag input. 1065 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1066 if (Tmp1 != Node->getOperand(0)) { 1067 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1068 Ops[0] = Tmp1; 1069 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1070 &Ops[0], Ops.size()), 1071 Result.getResNo()); 1072 } 1073 } else { 1074 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1075 if (Tmp1 != Node->getOperand(0) || 1076 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1077 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1078 Ops[0] = Tmp1; 1079 Ops.back() = Tmp2; 1080 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1081 &Ops[0], Ops.size()), 1082 Result.getResNo()); 1083 } 1084 } 1085 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1086 // This finishes up call legalization. 1087 IsLegalizingCall = false; 1088 1089 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1090 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1091 if (Node->getNumValues() == 2) 1092 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1093 return Result.getValue(Op.getResNo()); 1094 case ISD::LOAD: { 1095 LoadSDNode *LD = cast<LoadSDNode>(Node); 1096 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1097 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1098 1099 ISD::LoadExtType ExtType = LD->getExtensionType(); 1100 if (ExtType == ISD::NON_EXTLOAD) { 1101 EVT VT = Node->getValueType(0); 1102 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1103 Tmp1, Tmp2, LD->getOffset()), 1104 Result.getResNo()); 1105 Tmp3 = Result.getValue(0); 1106 Tmp4 = Result.getValue(1); 1107 1108 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1109 default: assert(0 && "This action is not supported yet!"); 1110 case TargetLowering::Legal: 1111 // If this is an unaligned load and the target doesn't support it, 1112 // expand it. 1113 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1114 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1115 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty); 1116 if (LD->getAlignment() < ABIAlignment){ 1117 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1118 DAG, TLI); 1119 Tmp3 = Result.getOperand(0); 1120 Tmp4 = Result.getOperand(1); 1121 Tmp3 = LegalizeOp(Tmp3); 1122 Tmp4 = LegalizeOp(Tmp4); 1123 } 1124 } 1125 break; 1126 case TargetLowering::Custom: 1127 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1128 if (Tmp1.getNode()) { 1129 Tmp3 = LegalizeOp(Tmp1); 1130 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1131 } 1132 break; 1133 case TargetLowering::Promote: { 1134 // Only promote a load of vector type to another. 1135 assert(VT.isVector() && "Cannot promote this load!"); 1136 // Change base type to a different vector type. 1137 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1138 1139 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1140 LD->getSrcValueOffset(), 1141 LD->isVolatile(), LD->isNonTemporal(), 1142 LD->getAlignment()); 1143 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1)); 1144 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1145 break; 1146 } 1147 } 1148 // Since loads produce two values, make sure to remember that we 1149 // legalized both of them. 1150 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1151 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1152 return Op.getResNo() ? Tmp4 : Tmp3; 1153 } else { 1154 EVT SrcVT = LD->getMemoryVT(); 1155 unsigned SrcWidth = SrcVT.getSizeInBits(); 1156 int SVOffset = LD->getSrcValueOffset(); 1157 unsigned Alignment = LD->getAlignment(); 1158 bool isVolatile = LD->isVolatile(); 1159 bool isNonTemporal = LD->isNonTemporal(); 1160 1161 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1162 // Some targets pretend to have an i1 loading operation, and actually 1163 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1164 // bits are guaranteed to be zero; it helps the optimizers understand 1165 // that these bits are zero. It is also useful for EXTLOAD, since it 1166 // tells the optimizers that those bits are undefined. It would be 1167 // nice to have an effective generic way of getting these benefits... 1168 // Until such a way is found, don't insist on promoting i1 here. 1169 (SrcVT != MVT::i1 || 1170 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1171 // Promote to a byte-sized load if not loading an integral number of 1172 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1173 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1174 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 1175 SDValue Ch; 1176 1177 // The extra bits are guaranteed to be zero, since we stored them that 1178 // way. A zext load from NVT thus automatically gives zext from SrcVT. 1179 1180 ISD::LoadExtType NewExtType = 1181 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 1182 1183 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), dl, 1184 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 1185 NVT, isVolatile, isNonTemporal, Alignment); 1186 1187 Ch = Result.getValue(1); // The chain. 1188 1189 if (ExtType == ISD::SEXTLOAD) 1190 // Having the top bits zero doesn't help when sign extending. 1191 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1192 Result.getValueType(), 1193 Result, DAG.getValueType(SrcVT)); 1194 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 1195 // All the top bits are guaranteed to be zero - inform the optimizers. 1196 Result = DAG.getNode(ISD::AssertZext, dl, 1197 Result.getValueType(), Result, 1198 DAG.getValueType(SrcVT)); 1199 1200 Tmp1 = LegalizeOp(Result); 1201 Tmp2 = LegalizeOp(Ch); 1202 } else if (SrcWidth & (SrcWidth - 1)) { 1203 // If not loading a power-of-2 number of bits, expand as two loads. 1204 assert(!SrcVT.isVector() && "Unsupported extload!"); 1205 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 1206 assert(RoundWidth < SrcWidth); 1207 unsigned ExtraWidth = SrcWidth - RoundWidth; 1208 assert(ExtraWidth < RoundWidth); 1209 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1210 "Load size not an integral number of bytes!"); 1211 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1212 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1213 SDValue Lo, Hi, Ch; 1214 unsigned IncrementSize; 1215 1216 if (TLI.isLittleEndian()) { 1217 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 1218 // Load the bottom RoundWidth bits. 1219 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), dl, 1220 Tmp1, Tmp2, 1221 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1222 isNonTemporal, Alignment); 1223 1224 // Load the remaining ExtraWidth bits. 1225 IncrementSize = RoundWidth / 8; 1226 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1227 DAG.getIntPtrConstant(IncrementSize)); 1228 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2, 1229 LD->getSrcValue(), SVOffset + IncrementSize, 1230 ExtraVT, isVolatile, isNonTemporal, 1231 MinAlign(Alignment, IncrementSize)); 1232 1233 // Build a factor node to remember that this load is independent of 1234 // the other one. 1235 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1236 Hi.getValue(1)); 1237 1238 // Move the top bits to the right place. 1239 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1240 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1241 1242 // Join the hi and lo parts. 1243 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1244 } else { 1245 // Big endian - avoid unaligned loads. 1246 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1247 // Load the top RoundWidth bits. 1248 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2, 1249 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 1250 isNonTemporal, Alignment); 1251 1252 // Load the remaining ExtraWidth bits. 1253 IncrementSize = RoundWidth / 8; 1254 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1255 DAG.getIntPtrConstant(IncrementSize)); 1256 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, 1257 Node->getValueType(0), dl, Tmp1, Tmp2, 1258 LD->getSrcValue(), SVOffset + IncrementSize, 1259 ExtraVT, isVolatile, isNonTemporal, 1260 MinAlign(Alignment, IncrementSize)); 1261 1262 // Build a factor node to remember that this load is independent of 1263 // the other one. 1264 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1265 Hi.getValue(1)); 1266 1267 // Move the top bits to the right place. 1268 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1269 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1270 1271 // Join the hi and lo parts. 1272 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1273 } 1274 1275 Tmp1 = LegalizeOp(Result); 1276 Tmp2 = LegalizeOp(Ch); 1277 } else { 1278 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1279 default: assert(0 && "This action is not supported yet!"); 1280 case TargetLowering::Custom: 1281 isCustom = true; 1282 // FALLTHROUGH 1283 case TargetLowering::Legal: 1284 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1285 Tmp1, Tmp2, LD->getOffset()), 1286 Result.getResNo()); 1287 Tmp1 = Result.getValue(0); 1288 Tmp2 = Result.getValue(1); 1289 1290 if (isCustom) { 1291 Tmp3 = TLI.LowerOperation(Result, DAG); 1292 if (Tmp3.getNode()) { 1293 Tmp1 = LegalizeOp(Tmp3); 1294 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1295 } 1296 } else { 1297 // If this is an unaligned load and the target doesn't support it, 1298 // expand it. 1299 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1300 const Type *Ty = 1301 LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1302 unsigned ABIAlignment = 1303 TLI.getTargetData()->getABITypeAlignment(Ty); 1304 if (LD->getAlignment() < ABIAlignment){ 1305 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), 1306 DAG, TLI); 1307 Tmp1 = Result.getOperand(0); 1308 Tmp2 = Result.getOperand(1); 1309 Tmp1 = LegalizeOp(Tmp1); 1310 Tmp2 = LegalizeOp(Tmp2); 1311 } 1312 } 1313 } 1314 break; 1315 case TargetLowering::Expand: 1316 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) { 1317 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), 1318 LD->getSrcValueOffset(), 1319 LD->isVolatile(), LD->isNonTemporal(), 1320 LD->getAlignment()); 1321 unsigned ExtendOp; 1322 switch (ExtType) { 1323 case ISD::EXTLOAD: 1324 ExtendOp = (SrcVT.isFloatingPoint() ? 1325 ISD::FP_EXTEND : ISD::ANY_EXTEND); 1326 break; 1327 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break; 1328 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break; 1329 default: llvm_unreachable("Unexpected extend load type!"); 1330 } 1331 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load); 1332 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1333 Tmp2 = LegalizeOp(Load.getValue(1)); 1334 break; 1335 } 1336 // FIXME: This does not work for vectors on most targets. Sign- and 1337 // zero-extend operations are currently folded into extending loads, 1338 // whether they are legal or not, and then we end up here without any 1339 // support for legalizing them. 1340 assert(ExtType != ISD::EXTLOAD && 1341 "EXTLOAD should always be supported!"); 1342 // Turn the unsupported load into an EXTLOAD followed by an explicit 1343 // zero/sign extend inreg. 1344 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), dl, 1345 Tmp1, Tmp2, LD->getSrcValue(), 1346 LD->getSrcValueOffset(), SrcVT, 1347 LD->isVolatile(), LD->isNonTemporal(), 1348 LD->getAlignment()); 1349 SDValue ValRes; 1350 if (ExtType == ISD::SEXTLOAD) 1351 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1352 Result.getValueType(), 1353 Result, DAG.getValueType(SrcVT)); 1354 else 1355 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); 1356 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1357 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1358 break; 1359 } 1360 } 1361 1362 // Since loads produce two values, make sure to remember that we legalized 1363 // both of them. 1364 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1365 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1366 return Op.getResNo() ? Tmp2 : Tmp1; 1367 } 1368 } 1369 case ISD::STORE: { 1370 StoreSDNode *ST = cast<StoreSDNode>(Node); 1371 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 1372 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 1373 int SVOffset = ST->getSrcValueOffset(); 1374 unsigned Alignment = ST->getAlignment(); 1375 bool isVolatile = ST->isVolatile(); 1376 bool isNonTemporal = ST->isNonTemporal(); 1377 1378 if (!ST->isTruncatingStore()) { 1379 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 1380 Result = SDValue(OptStore, 0); 1381 break; 1382 } 1383 1384 { 1385 Tmp3 = LegalizeOp(ST->getValue()); 1386 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1387 Tmp1, Tmp3, Tmp2, 1388 ST->getOffset()), 1389 Result.getResNo()); 1390 1391 EVT VT = Tmp3.getValueType(); 1392 switch (TLI.getOperationAction(ISD::STORE, VT)) { 1393 default: assert(0 && "This action is not supported yet!"); 1394 case TargetLowering::Legal: 1395 // If this is an unaligned store and the target doesn't support it, 1396 // expand it. 1397 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1398 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1399 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1400 if (ST->getAlignment() < ABIAlignment) 1401 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1402 DAG, TLI); 1403 } 1404 break; 1405 case TargetLowering::Custom: 1406 Tmp1 = TLI.LowerOperation(Result, DAG); 1407 if (Tmp1.getNode()) Result = Tmp1; 1408 break; 1409 case TargetLowering::Promote: 1410 assert(VT.isVector() && "Unknown legal promote case!"); 1411 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl, 1412 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 1413 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, 1414 ST->getSrcValue(), SVOffset, isVolatile, 1415 isNonTemporal, Alignment); 1416 break; 1417 } 1418 break; 1419 } 1420 } else { 1421 Tmp3 = LegalizeOp(ST->getValue()); 1422 1423 EVT StVT = ST->getMemoryVT(); 1424 unsigned StWidth = StVT.getSizeInBits(); 1425 1426 if (StWidth != StVT.getStoreSizeInBits()) { 1427 // Promote to a byte-sized store with upper bits zero if not 1428 // storing an integral number of bytes. For example, promote 1429 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 1430 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), 1431 StVT.getStoreSizeInBits()); 1432 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); 1433 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1434 SVOffset, NVT, isVolatile, isNonTemporal, 1435 Alignment); 1436 } else if (StWidth & (StWidth - 1)) { 1437 // If not storing a power-of-2 number of bits, expand as two stores. 1438 assert(!StVT.isVector() && "Unsupported truncstore!"); 1439 unsigned RoundWidth = 1 << Log2_32(StWidth); 1440 assert(RoundWidth < StWidth); 1441 unsigned ExtraWidth = StWidth - RoundWidth; 1442 assert(ExtraWidth < RoundWidth); 1443 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 1444 "Store size not an integral number of bytes!"); 1445 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 1446 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 1447 SDValue Lo, Hi; 1448 unsigned IncrementSize; 1449 1450 if (TLI.isLittleEndian()) { 1451 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 1452 // Store the bottom RoundWidth bits. 1453 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1454 SVOffset, RoundVT, 1455 isVolatile, isNonTemporal, Alignment); 1456 1457 // Store the remaining ExtraWidth bits. 1458 IncrementSize = RoundWidth / 8; 1459 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1460 DAG.getIntPtrConstant(IncrementSize)); 1461 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1462 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 1463 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1464 SVOffset + IncrementSize, ExtraVT, isVolatile, 1465 isNonTemporal, 1466 MinAlign(Alignment, IncrementSize)); 1467 } else { 1468 // Big endian - avoid unaligned stores. 1469 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 1470 // Store the top RoundWidth bits. 1471 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3, 1472 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 1473 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), 1474 SVOffset, RoundVT, isVolatile, isNonTemporal, 1475 Alignment); 1476 1477 // Store the remaining ExtraWidth bits. 1478 IncrementSize = RoundWidth / 8; 1479 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2, 1480 DAG.getIntPtrConstant(IncrementSize)); 1481 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1482 SVOffset + IncrementSize, ExtraVT, isVolatile, 1483 isNonTemporal, 1484 MinAlign(Alignment, IncrementSize)); 1485 } 1486 1487 // The order of the stores doesn't matter. 1488 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 1489 } else { 1490 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 1491 Tmp2 != ST->getBasePtr()) 1492 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), 1493 Tmp1, Tmp3, Tmp2, 1494 ST->getOffset()), 1495 Result.getResNo()); 1496 1497 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 1498 default: assert(0 && "This action is not supported yet!"); 1499 case TargetLowering::Legal: 1500 // If this is an unaligned store and the target doesn't support it, 1501 // expand it. 1502 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 1503 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1504 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 1505 if (ST->getAlignment() < ABIAlignment) 1506 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), 1507 DAG, TLI); 1508 } 1509 break; 1510 case TargetLowering::Custom: 1511 Result = TLI.LowerOperation(Result, DAG); 1512 break; 1513 case Expand: 1514 // TRUNCSTORE:i16 i32 -> STORE i16 1515 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 1516 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3); 1517 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), 1518 SVOffset, isVolatile, isNonTemporal, 1519 Alignment); 1520 break; 1521 } 1522 } 1523 } 1524 break; 1525 } 1526 } 1527 assert(Result.getValueType() == Op.getValueType() && 1528 "Bad legalization!"); 1529 1530 // Make sure that the generated code is itself legal. 1531 if (Result != Op) 1532 Result = LegalizeOp(Result); 1533 1534 // Note that LegalizeOp may be reentered even from single-use nodes, which 1535 // means that we always must cache transformed nodes. 1536 AddLegalizedOperand(Op, Result); 1537 return Result; 1538} 1539 1540SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1541 SDValue Vec = Op.getOperand(0); 1542 SDValue Idx = Op.getOperand(1); 1543 DebugLoc dl = Op.getDebugLoc(); 1544 // Store the value to a temporary stack slot, then LOAD the returned part. 1545 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1546 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0, 1547 false, false, 0); 1548 1549 // Add the offset to the index. 1550 unsigned EltSize = 1551 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1552 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1553 DAG.getConstant(EltSize, Idx.getValueType())); 1554 1555 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1556 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1557 else 1558 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1559 1560 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1561 1562 if (Op.getValueType().isVector()) 1563 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0, 1564 false, false, 0); 1565 else 1566 return DAG.getExtLoad(ISD::EXTLOAD, Op.getValueType(), dl, Ch, StackPtr, 1567 NULL, 0, Vec.getValueType().getVectorElementType(), 1568 false, false, 0); 1569} 1570 1571SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1572 // We can't handle this case efficiently. Allocate a sufficiently 1573 // aligned object on the stack, store each element into it, then load 1574 // the result as a vector. 1575 // Create the stack frame object. 1576 EVT VT = Node->getValueType(0); 1577 EVT EltVT = VT.getVectorElementType(); 1578 DebugLoc dl = Node->getDebugLoc(); 1579 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1580 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1581 const Value *SV = PseudoSourceValue::getFixedStack(FI); 1582 1583 // Emit a store of each element to the stack slot. 1584 SmallVector<SDValue, 8> Stores; 1585 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1586 // Store (in the right endianness) the elements to memory. 1587 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1588 // Ignore undef elements. 1589 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1590 1591 unsigned Offset = TypeByteSize*i; 1592 1593 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1594 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1595 1596 // If the destination vector element type is narrower than the source 1597 // element type, only store the bits necessary. 1598 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1599 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1600 Node->getOperand(i), Idx, SV, Offset, 1601 EltVT, false, false, 0)); 1602 } else 1603 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1604 Node->getOperand(i), Idx, SV, Offset, 1605 false, false, 0)); 1606 } 1607 1608 SDValue StoreChain; 1609 if (!Stores.empty()) // Not all undef elements? 1610 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1611 &Stores[0], Stores.size()); 1612 else 1613 StoreChain = DAG.getEntryNode(); 1614 1615 // Result is a load from the stack slot. 1616 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0, false, false, 0); 1617} 1618 1619SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1620 DebugLoc dl = Node->getDebugLoc(); 1621 SDValue Tmp1 = Node->getOperand(0); 1622 SDValue Tmp2 = Node->getOperand(1); 1623 1624 // Get the sign bit of the RHS. First obtain a value that has the same 1625 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1626 SDValue SignBit; 1627 EVT FloatVT = Tmp2.getValueType(); 1628 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1629 if (isTypeLegal(IVT)) { 1630 // Convert to an integer with the same sign bit. 1631 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); 1632 } else { 1633 // Store the float to memory, then load the sign part out as an integer. 1634 MVT LoadTy = TLI.getPointerTy(); 1635 // First create a temporary that is aligned for both the load and store. 1636 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1637 // Then store the float to it. 1638 SDValue Ch = 1639 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL, 0, 1640 false, false, 0); 1641 if (TLI.isBigEndian()) { 1642 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1643 // Load out a legal integer with the same sign bit as the float. 1644 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, NULL, 0, false, false, 0); 1645 } else { // Little endian 1646 SDValue LoadPtr = StackPtr; 1647 // The float may be wider than the integer we are going to load. Advance 1648 // the pointer so that the loaded integer will contain the sign bit. 1649 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1650 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1651 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1652 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1653 // Load a legal integer containing the sign bit. 1654 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, NULL, 0, false, false, 0); 1655 // Move the sign bit to the top bit of the loaded integer. 1656 unsigned BitShift = LoadTy.getSizeInBits() - 1657 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1658 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1659 if (BitShift) 1660 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1661 DAG.getConstant(BitShift,TLI.getShiftAmountTy())); 1662 } 1663 } 1664 // Now get the sign bit proper, by seeing whether the value is negative. 1665 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1666 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1667 ISD::SETLT); 1668 // Get the absolute value of the result. 1669 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1670 // Select between the nabs and abs value based on the sign bit of 1671 // the input. 1672 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1673 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1674 AbsVal); 1675} 1676 1677void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1678 SmallVectorImpl<SDValue> &Results) { 1679 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1680 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1681 " not tell us which reg is the stack pointer!"); 1682 DebugLoc dl = Node->getDebugLoc(); 1683 EVT VT = Node->getValueType(0); 1684 SDValue Tmp1 = SDValue(Node, 0); 1685 SDValue Tmp2 = SDValue(Node, 1); 1686 SDValue Tmp3 = Node->getOperand(2); 1687 SDValue Chain = Tmp1.getOperand(0); 1688 1689 // Chain the dynamic stack allocation so that it doesn't modify the stack 1690 // pointer when other instructions are using the stack. 1691 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1692 1693 SDValue Size = Tmp2.getOperand(1); 1694 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1695 Chain = SP.getValue(1); 1696 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1697 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); 1698 if (Align > StackAlign) 1699 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1700 DAG.getConstant(-(uint64_t)Align, VT)); 1701 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1702 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1703 1704 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1705 DAG.getIntPtrConstant(0, true), SDValue()); 1706 1707 Results.push_back(Tmp1); 1708 Results.push_back(Tmp2); 1709} 1710 1711/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1712/// condition code CC on the current target. This routine expands SETCC with 1713/// illegal condition code into AND / OR of multiple SETCC values. 1714void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1715 SDValue &LHS, SDValue &RHS, 1716 SDValue &CC, 1717 DebugLoc dl) { 1718 EVT OpVT = LHS.getValueType(); 1719 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1720 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1721 default: assert(0 && "Unknown condition code action!"); 1722 case TargetLowering::Legal: 1723 // Nothing to do. 1724 break; 1725 case TargetLowering::Expand: { 1726 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1727 unsigned Opc = 0; 1728 switch (CCCode) { 1729 default: assert(0 && "Don't know how to expand this condition!"); 1730 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1731 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1732 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1733 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1734 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1735 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1736 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1737 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1738 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1739 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1740 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1741 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1742 // FIXME: Implement more expansions. 1743 } 1744 1745 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1746 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1747 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1748 RHS = SDValue(); 1749 CC = SDValue(); 1750 break; 1751 } 1752 } 1753} 1754 1755/// EmitStackConvert - Emit a store/load combination to the stack. This stores 1756/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1757/// a load from the stack slot to DestVT, extending it if needed. 1758/// The resultant code need not be legal. 1759SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1760 EVT SlotVT, 1761 EVT DestVT, 1762 DebugLoc dl) { 1763 // Create the stack frame object. 1764 unsigned SrcAlign = 1765 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1766 getTypeForEVT(*DAG.getContext())); 1767 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1768 1769 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1770 int SPFI = StackPtrFI->getIndex(); 1771 const Value *SV = PseudoSourceValue::getFixedStack(SPFI); 1772 1773 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1774 unsigned SlotSize = SlotVT.getSizeInBits(); 1775 unsigned DestSize = DestVT.getSizeInBits(); 1776 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); 1777 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType); 1778 1779 // Emit a store to the stack slot. Use a truncstore if the input value is 1780 // later than DestVT. 1781 SDValue Store; 1782 1783 if (SrcSize > SlotSize) 1784 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1785 SV, 0, SlotVT, false, false, SrcAlign); 1786 else { 1787 assert(SrcSize == SlotSize && "Invalid store"); 1788 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1789 SV, 0, false, false, SrcAlign); 1790 } 1791 1792 // Result is a load from the stack slot. 1793 if (SlotSize == DestSize) 1794 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, false, 1795 DestAlign); 1796 1797 assert(SlotSize < DestSize && "Unknown extension!"); 1798 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, Store, FIPtr, SV, 0, SlotVT, 1799 false, false, DestAlign); 1800} 1801 1802SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1803 DebugLoc dl = Node->getDebugLoc(); 1804 // Create a vector sized/aligned stack slot, store the value to element #0, 1805 // then load the whole vector back out. 1806 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1807 1808 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1809 int SPFI = StackPtrFI->getIndex(); 1810 1811 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1812 StackPtr, 1813 PseudoSourceValue::getFixedStack(SPFI), 0, 1814 Node->getValueType(0).getVectorElementType(), 1815 false, false, 0); 1816 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1817 PseudoSourceValue::getFixedStack(SPFI), 0, 1818 false, false, 0); 1819} 1820 1821 1822/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1823/// support the operation, but do support the resultant vector type. 1824SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1825 unsigned NumElems = Node->getNumOperands(); 1826 SDValue Value1, Value2; 1827 DebugLoc dl = Node->getDebugLoc(); 1828 EVT VT = Node->getValueType(0); 1829 EVT OpVT = Node->getOperand(0).getValueType(); 1830 EVT EltVT = VT.getVectorElementType(); 1831 1832 // If the only non-undef value is the low element, turn this into a 1833 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1834 bool isOnlyLowElement = true; 1835 bool MoreThanTwoValues = false; 1836 bool isConstant = true; 1837 for (unsigned i = 0; i < NumElems; ++i) { 1838 SDValue V = Node->getOperand(i); 1839 if (V.getOpcode() == ISD::UNDEF) 1840 continue; 1841 if (i > 0) 1842 isOnlyLowElement = false; 1843 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1844 isConstant = false; 1845 1846 if (!Value1.getNode()) { 1847 Value1 = V; 1848 } else if (!Value2.getNode()) { 1849 if (V != Value1) 1850 Value2 = V; 1851 } else if (V != Value1 && V != Value2) { 1852 MoreThanTwoValues = true; 1853 } 1854 } 1855 1856 if (!Value1.getNode()) 1857 return DAG.getUNDEF(VT); 1858 1859 if (isOnlyLowElement) 1860 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1861 1862 // If all elements are constants, create a load from the constant pool. 1863 if (isConstant) { 1864 std::vector<Constant*> CV; 1865 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1866 if (ConstantFPSDNode *V = 1867 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1868 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1869 } else if (ConstantSDNode *V = 1870 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1871 if (OpVT==EltVT) 1872 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1873 else { 1874 // If OpVT and EltVT don't match, EltVT is not legal and the 1875 // element values have been promoted/truncated earlier. Undo this; 1876 // we don't want a v16i8 to become a v16i32 for example. 1877 const ConstantInt *CI = V->getConstantIntValue(); 1878 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1879 CI->getZExtValue())); 1880 } 1881 } else { 1882 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1883 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1884 CV.push_back(UndefValue::get(OpNTy)); 1885 } 1886 } 1887 Constant *CP = ConstantVector::get(CV); 1888 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1889 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1890 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1891 PseudoSourceValue::getConstantPool(), 0, 1892 false, false, Alignment); 1893 } 1894 1895 if (!MoreThanTwoValues) { 1896 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1897 for (unsigned i = 0; i < NumElems; ++i) { 1898 SDValue V = Node->getOperand(i); 1899 if (V.getOpcode() == ISD::UNDEF) 1900 continue; 1901 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1902 } 1903 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1904 // Get the splatted value into the low element of a vector register. 1905 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1906 SDValue Vec2; 1907 if (Value2.getNode()) 1908 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1909 else 1910 Vec2 = DAG.getUNDEF(VT); 1911 1912 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1913 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1914 } 1915 } 1916 1917 // Otherwise, we can't handle this case efficiently. 1918 return ExpandVectorBuildThroughStack(Node); 1919} 1920 1921// ExpandLibCall - Expand a node into a call to a libcall. If the result value 1922// does not fit into a register, return the lo part and set the hi part to the 1923// by-reg argument. If it does fit into a single register, return the result 1924// and leave the Hi part unset. 1925SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1926 bool isSigned) { 1927 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1928 // The input chain to this libcall is the entry node of the function. 1929 // Legalizing the call will automatically add the previous call to the 1930 // dependence. 1931 SDValue InChain = DAG.getEntryNode(); 1932 1933 TargetLowering::ArgListTy Args; 1934 TargetLowering::ArgListEntry Entry; 1935 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1936 EVT ArgVT = Node->getOperand(i).getValueType(); 1937 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1938 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1939 Entry.isSExt = isSigned; 1940 Entry.isZExt = !isSigned; 1941 Args.push_back(Entry); 1942 } 1943 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1944 TLI.getPointerTy()); 1945 1946 // Splice the libcall in wherever FindInputOutputChains tells us to. 1947 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1948 std::pair<SDValue, SDValue> CallInfo = 1949 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1950 0, TLI.getLibcallCallingConv(LC), false, 1951 /*isReturnValueUsed=*/true, 1952 Callee, Args, DAG, Node->getDebugLoc()); 1953 1954 // Legalize the call sequence, starting with the chain. This will advance 1955 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1956 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1957 LegalizeOp(CallInfo.second); 1958 return CallInfo.first; 1959} 1960 1961// ExpandChainLibCall - Expand a node into a call to a libcall. Similar to 1962// ExpandLibCall except that the first operand is the in-chain. 1963std::pair<SDValue, SDValue> 1964SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC, 1965 SDNode *Node, 1966 bool isSigned) { 1967 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 1968 SDValue InChain = Node->getOperand(0); 1969 1970 TargetLowering::ArgListTy Args; 1971 TargetLowering::ArgListEntry Entry; 1972 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) { 1973 EVT ArgVT = Node->getOperand(i).getValueType(); 1974 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1975 Entry.Node = Node->getOperand(i); 1976 Entry.Ty = ArgTy; 1977 Entry.isSExt = isSigned; 1978 Entry.isZExt = !isSigned; 1979 Args.push_back(Entry); 1980 } 1981 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1982 TLI.getPointerTy()); 1983 1984 // Splice the libcall in wherever FindInputOutputChains tells us to. 1985 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1986 std::pair<SDValue, SDValue> CallInfo = 1987 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 1988 0, TLI.getLibcallCallingConv(LC), false, 1989 /*isReturnValueUsed=*/true, 1990 Callee, Args, DAG, Node->getDebugLoc()); 1991 1992 // Legalize the call sequence, starting with the chain. This will advance 1993 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 1994 // was added by LowerCallTo (guaranteeing proper serialization of calls). 1995 LegalizeOp(CallInfo.second); 1996 return CallInfo; 1997} 1998 1999SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 2000 RTLIB::Libcall Call_F32, 2001 RTLIB::Libcall Call_F64, 2002 RTLIB::Libcall Call_F80, 2003 RTLIB::Libcall Call_PPCF128) { 2004 RTLIB::Libcall LC; 2005 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2006 default: assert(0 && "Unexpected request for libcall!"); 2007 case MVT::f32: LC = Call_F32; break; 2008 case MVT::f64: LC = Call_F64; break; 2009 case MVT::f80: LC = Call_F80; break; 2010 case MVT::ppcf128: LC = Call_PPCF128; break; 2011 } 2012 return ExpandLibCall(LC, Node, false); 2013} 2014 2015SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 2016 RTLIB::Libcall Call_I8, 2017 RTLIB::Libcall Call_I16, 2018 RTLIB::Libcall Call_I32, 2019 RTLIB::Libcall Call_I64, 2020 RTLIB::Libcall Call_I128) { 2021 RTLIB::Libcall LC; 2022 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 2023 default: assert(0 && "Unexpected request for libcall!"); 2024 case MVT::i8: LC = Call_I8; break; 2025 case MVT::i16: LC = Call_I16; break; 2026 case MVT::i32: LC = Call_I32; break; 2027 case MVT::i64: LC = Call_I64; break; 2028 case MVT::i128: LC = Call_I128; break; 2029 } 2030 return ExpandLibCall(LC, Node, isSigned); 2031} 2032 2033/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 2034/// INT_TO_FP operation of the specified operand when the target requests that 2035/// we expand it. At this point, we know that the result and operand types are 2036/// legal for the target. 2037SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 2038 SDValue Op0, 2039 EVT DestVT, 2040 DebugLoc dl) { 2041 if (Op0.getValueType() == MVT::i32) { 2042 // simple 32-bit [signed|unsigned] integer to float/double expansion 2043 2044 // Get the stack frame index of a 8 byte buffer. 2045 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 2046 2047 // word offset constant for Hi/Lo address computation 2048 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 2049 // set up Hi and Lo (into buffer) address based on endian 2050 SDValue Hi = StackSlot; 2051 SDValue Lo = DAG.getNode(ISD::ADD, dl, 2052 TLI.getPointerTy(), StackSlot, WordOff); 2053 if (TLI.isLittleEndian()) 2054 std::swap(Hi, Lo); 2055 2056 // if signed map to unsigned space 2057 SDValue Op0Mapped; 2058 if (isSigned) { 2059 // constant used to invert sign bit (signed to unsigned mapping) 2060 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 2061 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 2062 } else { 2063 Op0Mapped = Op0; 2064 } 2065 // store the lo of the constructed double - based on integer input 2066 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 2067 Op0Mapped, Lo, NULL, 0, 2068 false, false, 0); 2069 // initial hi portion of constructed double 2070 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2071 // store the hi of the constructed double - biased exponent 2072 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0, 2073 false, false, 0); 2074 // load the constructed double 2075 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0, 2076 false, false, 0); 2077 // FP constant to bias correct the final result 2078 SDValue Bias = DAG.getConstantFP(isSigned ? 2079 BitsToDouble(0x4330000080000000ULL) : 2080 BitsToDouble(0x4330000000000000ULL), 2081 MVT::f64); 2082 // subtract the bias 2083 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2084 // final result 2085 SDValue Result; 2086 // handle final rounding 2087 if (DestVT == MVT::f64) { 2088 // do nothing 2089 Result = Sub; 2090 } else if (DestVT.bitsLT(MVT::f64)) { 2091 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2092 DAG.getIntPtrConstant(0)); 2093 } else if (DestVT.bitsGT(MVT::f64)) { 2094 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2095 } 2096 return Result; 2097 } 2098 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2099 // Code below here assumes !isSigned without checking again. 2100 2101 // Implementation of unsigned i64 to f64 following the algorithm in 2102 // __floatundidf in compiler_rt. This implementation has the advantage 2103 // of performing rounding correctly, both in the default rounding mode 2104 // and in all alternate rounding modes. 2105 // TODO: Generalize this for use with other types. 2106 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2107 SDValue TwoP52 = 2108 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2109 SDValue TwoP84PlusTwoP52 = 2110 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2111 SDValue TwoP84 = 2112 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2113 2114 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2115 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2116 DAG.getConstant(32, MVT::i64)); 2117 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2118 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2119 SDValue LoFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, LoOr); 2120 SDValue HiFlt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, HiOr); 2121 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, 2122 TwoP84PlusTwoP52); 2123 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2124 } 2125 2126 // Implementation of unsigned i64 to f32. This implementation has the 2127 // advantage of performing rounding correctly. 2128 // TODO: Generalize this for use with other types. 2129 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { 2130 EVT SHVT = TLI.getShiftAmountTy(); 2131 2132 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2133 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64)); 2134 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, 2135 DAG.getConstant(UINT64_C(0x800), MVT::i64)); 2136 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2137 DAG.getConstant(UINT64_C(0x7ff), MVT::i64)); 2138 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2139 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); 2140 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0); 2141 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2142 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64), 2143 ISD::SETUGE); 2144 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0); 2145 2146 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2147 DAG.getConstant(32, SHVT)); 2148 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); 2149 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); 2150 SDValue TwoP32 = 2151 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64); 2152 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); 2153 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); 2154 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); 2155 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); 2156 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, 2157 DAG.getIntPtrConstant(0)); 2158 2159 } 2160 2161 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2162 2163 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2164 Op0, DAG.getConstant(0, Op0.getValueType()), 2165 ISD::SETLT); 2166 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2167 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2168 SignSet, Four, Zero); 2169 2170 // If the sign bit of the integer is set, the large number will be treated 2171 // as a negative number. To counteract this, the dynamic code adds an 2172 // offset depending on the data type. 2173 uint64_t FF; 2174 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2175 default: assert(0 && "Unsupported integer type!"); 2176 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2177 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2178 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2179 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2180 } 2181 if (TLI.isLittleEndian()) FF <<= 32; 2182 Constant *FudgeFactor = ConstantInt::get( 2183 Type::getInt64Ty(*DAG.getContext()), FF); 2184 2185 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2186 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2187 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2188 Alignment = std::min(Alignment, 4u); 2189 SDValue FudgeInReg; 2190 if (DestVT == MVT::f32) 2191 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2192 PseudoSourceValue::getConstantPool(), 0, 2193 false, false, Alignment); 2194 else { 2195 FudgeInReg = 2196 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, 2197 DAG.getEntryNode(), CPIdx, 2198 PseudoSourceValue::getConstantPool(), 0, 2199 MVT::f32, false, false, Alignment)); 2200 } 2201 2202 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2203} 2204 2205/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2206/// *INT_TO_FP operation of the specified operand when the target requests that 2207/// we promote it. At this point, we know that the result and operand types are 2208/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2209/// operation that takes a larger input. 2210SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2211 EVT DestVT, 2212 bool isSigned, 2213 DebugLoc dl) { 2214 // First step, figure out the appropriate *INT_TO_FP operation to use. 2215 EVT NewInTy = LegalOp.getValueType(); 2216 2217 unsigned OpToUse = 0; 2218 2219 // Scan for the appropriate larger type to use. 2220 while (1) { 2221 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2222 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2223 2224 // If the target supports SINT_TO_FP of this type, use it. 2225 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2226 OpToUse = ISD::SINT_TO_FP; 2227 break; 2228 } 2229 if (isSigned) continue; 2230 2231 // If the target supports UINT_TO_FP of this type, use it. 2232 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2233 OpToUse = ISD::UINT_TO_FP; 2234 break; 2235 } 2236 2237 // Otherwise, try a larger type. 2238 } 2239 2240 // Okay, we found the operation and type to use. Zero extend our input to the 2241 // desired type then run the operation on it. 2242 return DAG.getNode(OpToUse, dl, DestVT, 2243 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2244 dl, NewInTy, LegalOp)); 2245} 2246 2247/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2248/// FP_TO_*INT operation of the specified operand when the target requests that 2249/// we promote it. At this point, we know that the result and operand types are 2250/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2251/// operation that returns a larger result. 2252SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2253 EVT DestVT, 2254 bool isSigned, 2255 DebugLoc dl) { 2256 // First step, figure out the appropriate FP_TO*INT operation to use. 2257 EVT NewOutTy = DestVT; 2258 2259 unsigned OpToUse = 0; 2260 2261 // Scan for the appropriate larger type to use. 2262 while (1) { 2263 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2264 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2265 2266 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2267 OpToUse = ISD::FP_TO_SINT; 2268 break; 2269 } 2270 2271 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2272 OpToUse = ISD::FP_TO_UINT; 2273 break; 2274 } 2275 2276 // Otherwise, try a larger type. 2277 } 2278 2279 2280 // Okay, we found the operation and type to use. 2281 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2282 2283 // Truncate the result of the extended FP_TO_*INT operation to the desired 2284 // size. 2285 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2286} 2287 2288/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2289/// 2290SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2291 EVT VT = Op.getValueType(); 2292 EVT SHVT = TLI.getShiftAmountTy(); 2293 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2294 switch (VT.getSimpleVT().SimpleTy) { 2295 default: assert(0 && "Unhandled Expand type in BSWAP!"); 2296 case MVT::i16: 2297 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2298 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2299 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2300 case MVT::i32: 2301 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2302 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2303 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2304 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2305 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2306 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2307 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2308 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2309 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2310 case MVT::i64: 2311 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2312 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2313 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2314 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2315 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2316 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2317 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2318 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2319 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2320 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2321 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2322 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2323 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2324 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2325 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2326 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2327 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2328 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2329 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2330 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2331 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2332 } 2333} 2334 2335/// ExpandBitCount - Expand the specified bitcount instruction into operations. 2336/// 2337SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2338 DebugLoc dl) { 2339 switch (Opc) { 2340 default: assert(0 && "Cannot expand this yet!"); 2341 case ISD::CTPOP: { 2342 static const uint64_t mask[6] = { 2343 0x5555555555555555ULL, 0x3333333333333333ULL, 2344 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 2345 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 2346 }; 2347 EVT VT = Op.getValueType(); 2348 EVT ShVT = TLI.getShiftAmountTy(); 2349 unsigned len = VT.getSizeInBits(); 2350 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2351 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 2352 unsigned EltSize = VT.isVector() ? 2353 VT.getVectorElementType().getSizeInBits() : len; 2354 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT); 2355 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2356 Op = DAG.getNode(ISD::ADD, dl, VT, 2357 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2), 2358 DAG.getNode(ISD::AND, dl, VT, 2359 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3), 2360 Tmp2)); 2361 } 2362 return Op; 2363 } 2364 case ISD::CTLZ: { 2365 // for now, we do this: 2366 // x = x | (x >> 1); 2367 // x = x | (x >> 2); 2368 // ... 2369 // x = x | (x >>16); 2370 // x = x | (x >>32); // for 64-bit input 2371 // return popcount(~x); 2372 // 2373 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2374 EVT VT = Op.getValueType(); 2375 EVT ShVT = TLI.getShiftAmountTy(); 2376 unsigned len = VT.getSizeInBits(); 2377 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2378 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2379 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2380 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2381 } 2382 Op = DAG.getNOT(dl, Op, VT); 2383 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2384 } 2385 case ISD::CTTZ: { 2386 // for now, we use: { return popcount(~x & (x - 1)); } 2387 // unless the target has ctlz but not ctpop, in which case we use: 2388 // { return 32 - nlz(~x & (x-1)); } 2389 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2390 EVT VT = Op.getValueType(); 2391 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2392 DAG.getNOT(dl, Op, VT), 2393 DAG.getNode(ISD::SUB, dl, VT, Op, 2394 DAG.getConstant(1, VT))); 2395 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2396 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2397 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2398 return DAG.getNode(ISD::SUB, dl, VT, 2399 DAG.getConstant(VT.getSizeInBits(), VT), 2400 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2401 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2402 } 2403 } 2404} 2405 2406std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) { 2407 unsigned Opc = Node->getOpcode(); 2408 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 2409 RTLIB::Libcall LC; 2410 2411 switch (Opc) { 2412 default: 2413 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 2414 break; 2415 case ISD::ATOMIC_SWAP: 2416 switch (VT.SimpleTy) { 2417 default: llvm_unreachable("Unexpected value type for atomic!"); 2418 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 2419 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 2420 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 2421 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 2422 } 2423 break; 2424 case ISD::ATOMIC_CMP_SWAP: 2425 switch (VT.SimpleTy) { 2426 default: llvm_unreachable("Unexpected value type for atomic!"); 2427 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 2428 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 2429 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 2430 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 2431 } 2432 break; 2433 case ISD::ATOMIC_LOAD_ADD: 2434 switch (VT.SimpleTy) { 2435 default: llvm_unreachable("Unexpected value type for atomic!"); 2436 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 2437 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 2438 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 2439 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 2440 } 2441 break; 2442 case ISD::ATOMIC_LOAD_SUB: 2443 switch (VT.SimpleTy) { 2444 default: llvm_unreachable("Unexpected value type for atomic!"); 2445 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 2446 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 2447 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 2448 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 2449 } 2450 break; 2451 case ISD::ATOMIC_LOAD_AND: 2452 switch (VT.SimpleTy) { 2453 default: llvm_unreachable("Unexpected value type for atomic!"); 2454 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 2455 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 2456 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 2457 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 2458 } 2459 break; 2460 case ISD::ATOMIC_LOAD_OR: 2461 switch (VT.SimpleTy) { 2462 default: llvm_unreachable("Unexpected value type for atomic!"); 2463 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 2464 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 2465 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 2466 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 2467 } 2468 break; 2469 case ISD::ATOMIC_LOAD_XOR: 2470 switch (VT.SimpleTy) { 2471 default: llvm_unreachable("Unexpected value type for atomic!"); 2472 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 2473 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 2474 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 2475 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 2476 } 2477 break; 2478 case ISD::ATOMIC_LOAD_NAND: 2479 switch (VT.SimpleTy) { 2480 default: llvm_unreachable("Unexpected value type for atomic!"); 2481 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 2482 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 2483 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 2484 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 2485 } 2486 break; 2487 } 2488 2489 return ExpandChainLibCall(LC, Node, false); 2490} 2491 2492void SelectionDAGLegalize::ExpandNode(SDNode *Node, 2493 SmallVectorImpl<SDValue> &Results) { 2494 DebugLoc dl = Node->getDebugLoc(); 2495 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2496 switch (Node->getOpcode()) { 2497 case ISD::CTPOP: 2498 case ISD::CTLZ: 2499 case ISD::CTTZ: 2500 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2501 Results.push_back(Tmp1); 2502 break; 2503 case ISD::BSWAP: 2504 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2505 break; 2506 case ISD::FRAMEADDR: 2507 case ISD::RETURNADDR: 2508 case ISD::FRAME_TO_ARGS_OFFSET: 2509 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2510 break; 2511 case ISD::FLT_ROUNDS_: 2512 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2513 break; 2514 case ISD::EH_RETURN: 2515 case ISD::EH_LABEL: 2516 case ISD::PREFETCH: 2517 case ISD::VAEND: 2518 case ISD::EH_SJLJ_LONGJMP: 2519 Results.push_back(Node->getOperand(0)); 2520 break; 2521 case ISD::EH_SJLJ_SETJMP: 2522 Results.push_back(DAG.getConstant(0, MVT::i32)); 2523 Results.push_back(Node->getOperand(0)); 2524 break; 2525 case ISD::MEMBARRIER: { 2526 // If the target didn't lower this, lower it to '__sync_synchronize()' call 2527 TargetLowering::ArgListTy Args; 2528 std::pair<SDValue, SDValue> CallResult = 2529 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2530 false, false, false, false, 0, CallingConv::C, false, 2531 /*isReturnValueUsed=*/true, 2532 DAG.getExternalSymbol("__sync_synchronize", 2533 TLI.getPointerTy()), 2534 Args, DAG, dl); 2535 Results.push_back(CallResult.second); 2536 break; 2537 } 2538 // By default, atomic intrinsics are marked Legal and lowered. Targets 2539 // which don't support them directly, however, may want libcalls, in which 2540 // case they mark them Expand, and we get here. 2541 // FIXME: Unimplemented for now. Add libcalls. 2542 case ISD::ATOMIC_SWAP: 2543 case ISD::ATOMIC_LOAD_ADD: 2544 case ISD::ATOMIC_LOAD_SUB: 2545 case ISD::ATOMIC_LOAD_AND: 2546 case ISD::ATOMIC_LOAD_OR: 2547 case ISD::ATOMIC_LOAD_XOR: 2548 case ISD::ATOMIC_LOAD_NAND: 2549 case ISD::ATOMIC_LOAD_MIN: 2550 case ISD::ATOMIC_LOAD_MAX: 2551 case ISD::ATOMIC_LOAD_UMIN: 2552 case ISD::ATOMIC_LOAD_UMAX: 2553 case ISD::ATOMIC_CMP_SWAP: { 2554 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node); 2555 Results.push_back(Tmp.first); 2556 Results.push_back(Tmp.second); 2557 break; 2558 } 2559 case ISD::DYNAMIC_STACKALLOC: 2560 ExpandDYNAMIC_STACKALLOC(Node, Results); 2561 break; 2562 case ISD::MERGE_VALUES: 2563 for (unsigned i = 0; i < Node->getNumValues(); i++) 2564 Results.push_back(Node->getOperand(i)); 2565 break; 2566 case ISD::UNDEF: { 2567 EVT VT = Node->getValueType(0); 2568 if (VT.isInteger()) 2569 Results.push_back(DAG.getConstant(0, VT)); 2570 else { 2571 assert(VT.isFloatingPoint() && "Unknown value type!"); 2572 Results.push_back(DAG.getConstantFP(0, VT)); 2573 } 2574 break; 2575 } 2576 case ISD::TRAP: { 2577 // If this operation is not supported, lower it to 'abort()' call 2578 TargetLowering::ArgListTy Args; 2579 std::pair<SDValue, SDValue> CallResult = 2580 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()), 2581 false, false, false, false, 0, CallingConv::C, false, 2582 /*isReturnValueUsed=*/true, 2583 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2584 Args, DAG, dl); 2585 Results.push_back(CallResult.second); 2586 break; 2587 } 2588 case ISD::FP_ROUND: 2589 case ISD::BIT_CONVERT: 2590 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2591 Node->getValueType(0), dl); 2592 Results.push_back(Tmp1); 2593 break; 2594 case ISD::FP_EXTEND: 2595 Tmp1 = EmitStackConvert(Node->getOperand(0), 2596 Node->getOperand(0).getValueType(), 2597 Node->getValueType(0), dl); 2598 Results.push_back(Tmp1); 2599 break; 2600 case ISD::SIGN_EXTEND_INREG: { 2601 // NOTE: we could fall back on load/store here too for targets without 2602 // SAR. However, it is doubtful that any exist. 2603 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2604 EVT VT = Node->getValueType(0); 2605 EVT ShiftAmountTy = TLI.getShiftAmountTy(); 2606 if (VT.isVector()) 2607 ShiftAmountTy = VT; 2608 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2609 ExtraVT.getScalarType().getSizeInBits(); 2610 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2611 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2612 Node->getOperand(0), ShiftCst); 2613 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2614 Results.push_back(Tmp1); 2615 break; 2616 } 2617 case ISD::FP_ROUND_INREG: { 2618 // The only way we can lower this is to turn it into a TRUNCSTORE, 2619 // EXTLOAD pair, targetting a temporary location (a stack slot). 2620 2621 // NOTE: there is a choice here between constantly creating new stack 2622 // slots and always reusing the same one. We currently always create 2623 // new ones, as reuse may inhibit scheduling. 2624 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2625 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2626 Node->getValueType(0), dl); 2627 Results.push_back(Tmp1); 2628 break; 2629 } 2630 case ISD::SINT_TO_FP: 2631 case ISD::UINT_TO_FP: 2632 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2633 Node->getOperand(0), Node->getValueType(0), dl); 2634 Results.push_back(Tmp1); 2635 break; 2636 case ISD::FP_TO_UINT: { 2637 SDValue True, False; 2638 EVT VT = Node->getOperand(0).getValueType(); 2639 EVT NVT = Node->getValueType(0); 2640 const uint64_t zero[] = {0, 0}; 2641 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 2642 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2643 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2644 Tmp1 = DAG.getConstantFP(apf, VT); 2645 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2646 Node->getOperand(0), 2647 Tmp1, ISD::SETLT); 2648 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2649 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2650 DAG.getNode(ISD::FSUB, dl, VT, 2651 Node->getOperand(0), Tmp1)); 2652 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2653 DAG.getConstant(x, NVT)); 2654 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2655 Results.push_back(Tmp1); 2656 break; 2657 } 2658 case ISD::VAARG: { 2659 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2660 EVT VT = Node->getValueType(0); 2661 Tmp1 = Node->getOperand(0); 2662 Tmp2 = Node->getOperand(1); 2663 unsigned Align = Node->getConstantOperandVal(3); 2664 2665 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0, 2666 false, false, 0); 2667 SDValue VAList = VAListLoad; 2668 2669 if (Align > TLI.getMinStackArgumentAlignment()) { 2670 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2671 2672 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2673 DAG.getConstant(Align - 1, 2674 TLI.getPointerTy())); 2675 2676 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList, 2677 DAG.getConstant(-Align, 2678 TLI.getPointerTy())); 2679 } 2680 2681 // Increment the pointer, VAList, to the next vaarg 2682 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2683 DAG.getConstant(TLI.getTargetData()-> 2684 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2685 TLI.getPointerTy())); 2686 // Store the incremented VAList to the legalized pointer 2687 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, V, 0, 2688 false, false, 0); 2689 // Load the actual argument out of the pointer VAList 2690 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0, 2691 false, false, 0)); 2692 Results.push_back(Results[0].getValue(1)); 2693 break; 2694 } 2695 case ISD::VACOPY: { 2696 // This defaults to loading a pointer from the input and storing it to the 2697 // output, returning the chain. 2698 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2699 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2700 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2701 Node->getOperand(2), VS, 0, false, false, 0); 2702 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0, 2703 false, false, 0); 2704 Results.push_back(Tmp1); 2705 break; 2706 } 2707 case ISD::EXTRACT_VECTOR_ELT: 2708 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2709 // This must be an access of the only element. Return it. 2710 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), 2711 Node->getOperand(0)); 2712 else 2713 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2714 Results.push_back(Tmp1); 2715 break; 2716 case ISD::EXTRACT_SUBVECTOR: 2717 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2718 break; 2719 case ISD::CONCAT_VECTORS: { 2720 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2721 break; 2722 } 2723 case ISD::SCALAR_TO_VECTOR: 2724 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2725 break; 2726 case ISD::INSERT_VECTOR_ELT: 2727 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2728 Node->getOperand(1), 2729 Node->getOperand(2), dl)); 2730 break; 2731 case ISD::VECTOR_SHUFFLE: { 2732 SmallVector<int, 8> Mask; 2733 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 2734 2735 EVT VT = Node->getValueType(0); 2736 EVT EltVT = VT.getVectorElementType(); 2737 if (getTypeAction(EltVT) == Promote) 2738 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT); 2739 unsigned NumElems = VT.getVectorNumElements(); 2740 SmallVector<SDValue, 8> Ops; 2741 for (unsigned i = 0; i != NumElems; ++i) { 2742 if (Mask[i] < 0) { 2743 Ops.push_back(DAG.getUNDEF(EltVT)); 2744 continue; 2745 } 2746 unsigned Idx = Mask[i]; 2747 if (Idx < NumElems) 2748 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2749 Node->getOperand(0), 2750 DAG.getIntPtrConstant(Idx))); 2751 else 2752 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2753 Node->getOperand(1), 2754 DAG.getIntPtrConstant(Idx - NumElems))); 2755 } 2756 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2757 Results.push_back(Tmp1); 2758 break; 2759 } 2760 case ISD::EXTRACT_ELEMENT: { 2761 EVT OpTy = Node->getOperand(0).getValueType(); 2762 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2763 // 1 -> Hi 2764 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2765 DAG.getConstant(OpTy.getSizeInBits()/2, 2766 TLI.getShiftAmountTy())); 2767 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2768 } else { 2769 // 0 -> Lo 2770 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2771 Node->getOperand(0)); 2772 } 2773 Results.push_back(Tmp1); 2774 break; 2775 } 2776 case ISD::STACKSAVE: 2777 // Expand to CopyFromReg if the target set 2778 // StackPointerRegisterToSaveRestore. 2779 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2780 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2781 Node->getValueType(0))); 2782 Results.push_back(Results[0].getValue(1)); 2783 } else { 2784 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2785 Results.push_back(Node->getOperand(0)); 2786 } 2787 break; 2788 case ISD::STACKRESTORE: 2789 // Expand to CopyToReg if the target set 2790 // StackPointerRegisterToSaveRestore. 2791 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2792 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2793 Node->getOperand(1))); 2794 } else { 2795 Results.push_back(Node->getOperand(0)); 2796 } 2797 break; 2798 case ISD::FCOPYSIGN: 2799 Results.push_back(ExpandFCOPYSIGN(Node)); 2800 break; 2801 case ISD::FNEG: 2802 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2803 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2804 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2805 Node->getOperand(0)); 2806 Results.push_back(Tmp1); 2807 break; 2808 case ISD::FABS: { 2809 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2810 EVT VT = Node->getValueType(0); 2811 Tmp1 = Node->getOperand(0); 2812 Tmp2 = DAG.getConstantFP(0.0, VT); 2813 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2814 Tmp1, Tmp2, ISD::SETUGT); 2815 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2816 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2817 Results.push_back(Tmp1); 2818 break; 2819 } 2820 case ISD::FSQRT: 2821 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2822 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2823 break; 2824 case ISD::FSIN: 2825 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2826 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2827 break; 2828 case ISD::FCOS: 2829 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2830 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2831 break; 2832 case ISD::FLOG: 2833 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2834 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2835 break; 2836 case ISD::FLOG2: 2837 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2838 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2839 break; 2840 case ISD::FLOG10: 2841 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2842 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2843 break; 2844 case ISD::FEXP: 2845 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 2846 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 2847 break; 2848 case ISD::FEXP2: 2849 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 2850 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 2851 break; 2852 case ISD::FTRUNC: 2853 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 2854 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 2855 break; 2856 case ISD::FFLOOR: 2857 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 2858 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 2859 break; 2860 case ISD::FCEIL: 2861 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 2862 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 2863 break; 2864 case ISD::FRINT: 2865 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 2866 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 2867 break; 2868 case ISD::FNEARBYINT: 2869 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 2870 RTLIB::NEARBYINT_F64, 2871 RTLIB::NEARBYINT_F80, 2872 RTLIB::NEARBYINT_PPCF128)); 2873 break; 2874 case ISD::FPOWI: 2875 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 2876 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 2877 break; 2878 case ISD::FPOW: 2879 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 2880 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 2881 break; 2882 case ISD::FDIV: 2883 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 2884 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 2885 break; 2886 case ISD::FREM: 2887 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 2888 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 2889 break; 2890 case ISD::FP16_TO_FP32: 2891 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 2892 break; 2893 case ISD::FP32_TO_FP16: 2894 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 2895 break; 2896 case ISD::ConstantFP: { 2897 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 2898 // Check to see if this FP immediate is already legal. 2899 // If this is a legal constant, turn it into a TargetConstantFP node. 2900 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 2901 Results.push_back(SDValue(Node, 0)); 2902 else 2903 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI)); 2904 break; 2905 } 2906 case ISD::EHSELECTION: { 2907 unsigned Reg = TLI.getExceptionSelectorRegister(); 2908 assert(Reg && "Can't expand to unknown register!"); 2909 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 2910 Node->getValueType(0))); 2911 Results.push_back(Results[0].getValue(1)); 2912 break; 2913 } 2914 case ISD::EXCEPTIONADDR: { 2915 unsigned Reg = TLI.getExceptionAddressRegister(); 2916 assert(Reg && "Can't expand to unknown register!"); 2917 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 2918 Node->getValueType(0))); 2919 Results.push_back(Results[0].getValue(1)); 2920 break; 2921 } 2922 case ISD::SUB: { 2923 EVT VT = Node->getValueType(0); 2924 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 2925 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 2926 "Don't know how to expand this subtraction!"); 2927 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 2928 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 2929 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT)); 2930 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 2931 break; 2932 } 2933 case ISD::UREM: 2934 case ISD::SREM: { 2935 EVT VT = Node->getValueType(0); 2936 SDVTList VTs = DAG.getVTList(VT, VT); 2937 bool isSigned = Node->getOpcode() == ISD::SREM; 2938 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 2939 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2940 Tmp2 = Node->getOperand(0); 2941 Tmp3 = Node->getOperand(1); 2942 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { 2943 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 2944 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 2945 // X % Y -> X-X/Y*Y 2946 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 2947 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 2948 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 2949 } else if (isSigned) { 2950 Tmp1 = ExpandIntLibCall(Node, true, 2951 RTLIB::SREM_I8, 2952 RTLIB::SREM_I16, RTLIB::SREM_I32, 2953 RTLIB::SREM_I64, RTLIB::SREM_I128); 2954 } else { 2955 Tmp1 = ExpandIntLibCall(Node, false, 2956 RTLIB::UREM_I8, 2957 RTLIB::UREM_I16, RTLIB::UREM_I32, 2958 RTLIB::UREM_I64, RTLIB::UREM_I128); 2959 } 2960 Results.push_back(Tmp1); 2961 break; 2962 } 2963 case ISD::UDIV: 2964 case ISD::SDIV: { 2965 bool isSigned = Node->getOpcode() == ISD::SDIV; 2966 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 2967 EVT VT = Node->getValueType(0); 2968 SDVTList VTs = DAG.getVTList(VT, VT); 2969 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) 2970 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 2971 Node->getOperand(1)); 2972 else if (isSigned) 2973 Tmp1 = ExpandIntLibCall(Node, true, 2974 RTLIB::SDIV_I8, 2975 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 2976 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 2977 else 2978 Tmp1 = ExpandIntLibCall(Node, false, 2979 RTLIB::UDIV_I8, 2980 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 2981 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 2982 Results.push_back(Tmp1); 2983 break; 2984 } 2985 case ISD::MULHU: 2986 case ISD::MULHS: { 2987 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 2988 ISD::SMUL_LOHI; 2989 EVT VT = Node->getValueType(0); 2990 SDVTList VTs = DAG.getVTList(VT, VT); 2991 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 2992 "If this wasn't legal, it shouldn't have been created!"); 2993 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 2994 Node->getOperand(1)); 2995 Results.push_back(Tmp1.getValue(1)); 2996 break; 2997 } 2998 case ISD::MUL: { 2999 EVT VT = Node->getValueType(0); 3000 SDVTList VTs = DAG.getVTList(VT, VT); 3001 // See if multiply or divide can be lowered using two-result operations. 3002 // We just need the low half of the multiply; try both the signed 3003 // and unsigned forms. If the target supports both SMUL_LOHI and 3004 // UMUL_LOHI, form a preference by checking which forms of plain 3005 // MULH it supports. 3006 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 3007 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 3008 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 3009 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 3010 unsigned OpToUse = 0; 3011 if (HasSMUL_LOHI && !HasMULHS) { 3012 OpToUse = ISD::SMUL_LOHI; 3013 } else if (HasUMUL_LOHI && !HasMULHU) { 3014 OpToUse = ISD::UMUL_LOHI; 3015 } else if (HasSMUL_LOHI) { 3016 OpToUse = ISD::SMUL_LOHI; 3017 } else if (HasUMUL_LOHI) { 3018 OpToUse = ISD::UMUL_LOHI; 3019 } 3020 if (OpToUse) { 3021 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 3022 Node->getOperand(1))); 3023 break; 3024 } 3025 Tmp1 = ExpandIntLibCall(Node, false, 3026 RTLIB::MUL_I8, 3027 RTLIB::MUL_I16, RTLIB::MUL_I32, 3028 RTLIB::MUL_I64, RTLIB::MUL_I128); 3029 Results.push_back(Tmp1); 3030 break; 3031 } 3032 case ISD::SADDO: 3033 case ISD::SSUBO: { 3034 SDValue LHS = Node->getOperand(0); 3035 SDValue RHS = Node->getOperand(1); 3036 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 3037 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3038 LHS, RHS); 3039 Results.push_back(Sum); 3040 EVT OType = Node->getValueType(1); 3041 3042 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 3043 3044 // LHSSign -> LHS >= 0 3045 // RHSSign -> RHS >= 0 3046 // SumSign -> Sum >= 0 3047 // 3048 // Add: 3049 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 3050 // Sub: 3051 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 3052 // 3053 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 3054 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 3055 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 3056 Node->getOpcode() == ISD::SADDO ? 3057 ISD::SETEQ : ISD::SETNE); 3058 3059 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 3060 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 3061 3062 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 3063 Results.push_back(Cmp); 3064 break; 3065 } 3066 case ISD::UADDO: 3067 case ISD::USUBO: { 3068 SDValue LHS = Node->getOperand(0); 3069 SDValue RHS = Node->getOperand(1); 3070 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 3071 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3072 LHS, RHS); 3073 Results.push_back(Sum); 3074 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 3075 Node->getOpcode () == ISD::UADDO ? 3076 ISD::SETULT : ISD::SETUGT)); 3077 break; 3078 } 3079 case ISD::UMULO: 3080 case ISD::SMULO: { 3081 EVT VT = Node->getValueType(0); 3082 SDValue LHS = Node->getOperand(0); 3083 SDValue RHS = Node->getOperand(1); 3084 SDValue BottomHalf; 3085 SDValue TopHalf; 3086 static const unsigned Ops[2][3] = 3087 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 3088 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 3089 bool isSigned = Node->getOpcode() == ISD::SMULO; 3090 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 3091 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 3092 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 3093 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 3094 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 3095 RHS); 3096 TopHalf = BottomHalf.getValue(1); 3097 } else { 3098 // FIXME: We should be able to fall back to a libcall with an illegal 3099 // type in some cases. 3100 // Also, we can fall back to a division in some cases, but that's a big 3101 // performance hit in the general case. 3102 assert(TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), 3103 VT.getSizeInBits() * 2)) && 3104 "Don't know how to expand this operation yet!"); 3105 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 3106 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 3107 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 3108 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 3109 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3110 DAG.getIntPtrConstant(0)); 3111 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3112 DAG.getIntPtrConstant(1)); 3113 } 3114 if (isSigned) { 3115 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy()); 3116 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 3117 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 3118 ISD::SETNE); 3119 } else { 3120 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 3121 DAG.getConstant(0, VT), ISD::SETNE); 3122 } 3123 Results.push_back(BottomHalf); 3124 Results.push_back(TopHalf); 3125 break; 3126 } 3127 case ISD::BUILD_PAIR: { 3128 EVT PairTy = Node->getValueType(0); 3129 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 3130 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 3131 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 3132 DAG.getConstant(PairTy.getSizeInBits()/2, 3133 TLI.getShiftAmountTy())); 3134 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 3135 break; 3136 } 3137 case ISD::SELECT: 3138 Tmp1 = Node->getOperand(0); 3139 Tmp2 = Node->getOperand(1); 3140 Tmp3 = Node->getOperand(2); 3141 if (Tmp1.getOpcode() == ISD::SETCC) { 3142 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 3143 Tmp2, Tmp3, 3144 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 3145 } else { 3146 Tmp1 = DAG.getSelectCC(dl, Tmp1, 3147 DAG.getConstant(0, Tmp1.getValueType()), 3148 Tmp2, Tmp3, ISD::SETNE); 3149 } 3150 Results.push_back(Tmp1); 3151 break; 3152 case ISD::BR_JT: { 3153 SDValue Chain = Node->getOperand(0); 3154 SDValue Table = Node->getOperand(1); 3155 SDValue Index = Node->getOperand(2); 3156 3157 EVT PTy = TLI.getPointerTy(); 3158 3159 const TargetData &TD = *TLI.getTargetData(); 3160 unsigned EntrySize = 3161 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 3162 3163 Index = DAG.getNode(ISD::MUL, dl, PTy, 3164 Index, DAG.getConstant(EntrySize, PTy)); 3165 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 3166 3167 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 3168 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, dl, Chain, Addr, 3169 PseudoSourceValue::getJumpTable(), 0, MemVT, 3170 false, false, 0); 3171 Addr = LD; 3172 if (TM.getRelocationModel() == Reloc::PIC_) { 3173 // For PIC, the sequence is: 3174 // BRIND(load(Jumptable + index) + RelocBase) 3175 // RelocBase can be JumpTable, GOT or some sort of global base. 3176 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 3177 TLI.getPICJumpTableRelocBase(Table, DAG)); 3178 } 3179 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 3180 Results.push_back(Tmp1); 3181 break; 3182 } 3183 case ISD::BRCOND: 3184 // Expand brcond's setcc into its constituent parts and create a BR_CC 3185 // Node. 3186 Tmp1 = Node->getOperand(0); 3187 Tmp2 = Node->getOperand(1); 3188 if (Tmp2.getOpcode() == ISD::SETCC) { 3189 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 3190 Tmp1, Tmp2.getOperand(2), 3191 Tmp2.getOperand(0), Tmp2.getOperand(1), 3192 Node->getOperand(2)); 3193 } else { 3194 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 3195 DAG.getCondCode(ISD::SETNE), Tmp2, 3196 DAG.getConstant(0, Tmp2.getValueType()), 3197 Node->getOperand(2)); 3198 } 3199 Results.push_back(Tmp1); 3200 break; 3201 case ISD::SETCC: { 3202 Tmp1 = Node->getOperand(0); 3203 Tmp2 = Node->getOperand(1); 3204 Tmp3 = Node->getOperand(2); 3205 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 3206 3207 // If we expanded the SETCC into an AND/OR, return the new node 3208 if (Tmp2.getNode() == 0) { 3209 Results.push_back(Tmp1); 3210 break; 3211 } 3212 3213 // Otherwise, SETCC for the given comparison type must be completely 3214 // illegal; expand it into a SELECT_CC. 3215 EVT VT = Node->getValueType(0); 3216 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3217 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 3218 Results.push_back(Tmp1); 3219 break; 3220 } 3221 case ISD::SELECT_CC: { 3222 Tmp1 = Node->getOperand(0); // LHS 3223 Tmp2 = Node->getOperand(1); // RHS 3224 Tmp3 = Node->getOperand(2); // True 3225 Tmp4 = Node->getOperand(3); // False 3226 SDValue CC = Node->getOperand(4); 3227 3228 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 3229 Tmp1, Tmp2, CC, dl); 3230 3231 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 3232 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3233 CC = DAG.getCondCode(ISD::SETNE); 3234 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 3235 Tmp3, Tmp4, CC); 3236 Results.push_back(Tmp1); 3237 break; 3238 } 3239 case ISD::BR_CC: { 3240 Tmp1 = Node->getOperand(0); // Chain 3241 Tmp2 = Node->getOperand(2); // LHS 3242 Tmp3 = Node->getOperand(3); // RHS 3243 Tmp4 = Node->getOperand(1); // CC 3244 3245 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 3246 Tmp2, Tmp3, Tmp4, dl); 3247 LastCALLSEQ_END = DAG.getEntryNode(); 3248 3249 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 3250 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 3251 Tmp4 = DAG.getCondCode(ISD::SETNE); 3252 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3253 Tmp3, Node->getOperand(4)); 3254 Results.push_back(Tmp1); 3255 break; 3256 } 3257 case ISD::GLOBAL_OFFSET_TABLE: 3258 case ISD::GlobalAddress: 3259 case ISD::GlobalTLSAddress: 3260 case ISD::ExternalSymbol: 3261 case ISD::ConstantPool: 3262 case ISD::JumpTable: 3263 case ISD::INTRINSIC_W_CHAIN: 3264 case ISD::INTRINSIC_WO_CHAIN: 3265 case ISD::INTRINSIC_VOID: 3266 // FIXME: Custom lowering for these operations shouldn't return null! 3267 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3268 Results.push_back(SDValue(Node, i)); 3269 break; 3270 } 3271} 3272void SelectionDAGLegalize::PromoteNode(SDNode *Node, 3273 SmallVectorImpl<SDValue> &Results) { 3274 EVT OVT = Node->getValueType(0); 3275 if (Node->getOpcode() == ISD::UINT_TO_FP || 3276 Node->getOpcode() == ISD::SINT_TO_FP || 3277 Node->getOpcode() == ISD::SETCC) { 3278 OVT = Node->getOperand(0).getValueType(); 3279 } 3280 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3281 DebugLoc dl = Node->getDebugLoc(); 3282 SDValue Tmp1, Tmp2, Tmp3; 3283 switch (Node->getOpcode()) { 3284 case ISD::CTTZ: 3285 case ISD::CTLZ: 3286 case ISD::CTPOP: 3287 // Zero extend the argument. 3288 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3289 // Perform the larger operation. 3290 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3291 if (Node->getOpcode() == ISD::CTTZ) { 3292 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3293 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3294 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3295 ISD::SETEQ); 3296 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3297 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3298 } else if (Node->getOpcode() == ISD::CTLZ) { 3299 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3300 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3301 DAG.getConstant(NVT.getSizeInBits() - 3302 OVT.getSizeInBits(), NVT)); 3303 } 3304 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3305 break; 3306 case ISD::BSWAP: { 3307 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3308 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3309 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3310 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3311 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3312 Results.push_back(Tmp1); 3313 break; 3314 } 3315 case ISD::FP_TO_UINT: 3316 case ISD::FP_TO_SINT: 3317 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3318 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3319 Results.push_back(Tmp1); 3320 break; 3321 case ISD::UINT_TO_FP: 3322 case ISD::SINT_TO_FP: 3323 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3324 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3325 Results.push_back(Tmp1); 3326 break; 3327 case ISD::AND: 3328 case ISD::OR: 3329 case ISD::XOR: { 3330 unsigned ExtOp, TruncOp; 3331 if (OVT.isVector()) { 3332 ExtOp = ISD::BIT_CONVERT; 3333 TruncOp = ISD::BIT_CONVERT; 3334 } else { 3335 assert(OVT.isInteger() && "Cannot promote logic operation"); 3336 ExtOp = ISD::ANY_EXTEND; 3337 TruncOp = ISD::TRUNCATE; 3338 } 3339 // Promote each of the values to the new type. 3340 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3341 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3342 // Perform the larger operation, then convert back 3343 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3344 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3345 break; 3346 } 3347 case ISD::SELECT: { 3348 unsigned ExtOp, TruncOp; 3349 if (Node->getValueType(0).isVector()) { 3350 ExtOp = ISD::BIT_CONVERT; 3351 TruncOp = ISD::BIT_CONVERT; 3352 } else if (Node->getValueType(0).isInteger()) { 3353 ExtOp = ISD::ANY_EXTEND; 3354 TruncOp = ISD::TRUNCATE; 3355 } else { 3356 ExtOp = ISD::FP_EXTEND; 3357 TruncOp = ISD::FP_ROUND; 3358 } 3359 Tmp1 = Node->getOperand(0); 3360 // Promote each of the values to the new type. 3361 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3362 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3363 // Perform the larger operation, then round down. 3364 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3365 if (TruncOp != ISD::FP_ROUND) 3366 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3367 else 3368 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3369 DAG.getIntPtrConstant(0)); 3370 Results.push_back(Tmp1); 3371 break; 3372 } 3373 case ISD::VECTOR_SHUFFLE: { 3374 SmallVector<int, 8> Mask; 3375 cast<ShuffleVectorSDNode>(Node)->getMask(Mask); 3376 3377 // Cast the two input vectors. 3378 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); 3379 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); 3380 3381 // Convert the shuffle mask to the right # elements. 3382 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3383 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1); 3384 Results.push_back(Tmp1); 3385 break; 3386 } 3387 case ISD::SETCC: { 3388 unsigned ExtOp = ISD::FP_EXTEND; 3389 if (NVT.isInteger()) { 3390 ISD::CondCode CCCode = 3391 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3392 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3393 } 3394 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3395 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3396 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3397 Tmp1, Tmp2, Node->getOperand(2))); 3398 break; 3399 } 3400 } 3401} 3402 3403// SelectionDAG::Legalize - This is the entry point for the file. 3404// 3405void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) { 3406 /// run - This is the main entry point to this class. 3407 /// 3408 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); 3409} 3410 3411