LegalizeDAG.cpp revision f2670a89a7c5e29e7f71ab63e06e75dbf482c55b
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/Target/TargetFrameInfo.h" 20#include "llvm/Target/TargetLowering.h" 21#include "llvm/Target/TargetData.h" 22#include "llvm/Target/TargetMachine.h" 23#include "llvm/Target/TargetOptions.h" 24#include "llvm/CallingConv.h" 25#include "llvm/Constants.h" 26#include "llvm/DerivedTypes.h" 27#include "llvm/Support/CommandLine.h" 28#include "llvm/Support/Compiler.h" 29#include "llvm/Support/MathExtras.h" 30#include "llvm/ADT/DenseMap.h" 31#include "llvm/ADT/SmallVector.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include <map> 34using namespace llvm; 35 36#ifndef NDEBUG 37static cl::opt<bool> 38ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 39 cl::desc("Pop up a window to show dags before legalize")); 40#else 41static const bool ViewLegalizeDAGs = 0; 42#endif 43 44//===----------------------------------------------------------------------===// 45/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 46/// hacks on it until the target machine can handle it. This involves 47/// eliminating value sizes the machine cannot handle (promoting small sizes to 48/// large sizes or splitting up large values into small values) as well as 49/// eliminating operations the machine cannot handle. 50/// 51/// This code also does a small amount of optimization and recognition of idioms 52/// as part of its processing. For example, if a target does not support a 53/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 54/// will attempt merge setcc and brc instructions into brcc's. 55/// 56namespace { 57class VISIBILITY_HIDDEN SelectionDAGLegalize { 58 TargetLowering &TLI; 59 SelectionDAG &DAG; 60 61 // Libcall insertion helpers. 62 63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 64 /// legalized. We use this to ensure that calls are properly serialized 65 /// against each other, including inserted libcalls. 66 SDOperand LastCALLSEQ_END; 67 68 /// IsLegalizingCall - This member is used *only* for purposes of providing 69 /// helpful assertions that a libcall isn't created while another call is 70 /// being legalized (which could lead to non-serialized call sequences). 71 bool IsLegalizingCall; 72 73 enum LegalizeAction { 74 Legal, // The target natively supports this operation. 75 Promote, // This operation should be executed in a larger type. 76 Expand // Try to expand this to other ops, otherwise use a libcall. 77 }; 78 79 /// ValueTypeActions - This is a bitvector that contains two bits for each 80 /// value type, where the two bits correspond to the LegalizeAction enum. 81 /// This can be queried with "getTypeAction(VT)". 82 TargetLowering::ValueTypeActionImpl ValueTypeActions; 83 84 /// LegalizedNodes - For nodes that are of legal width, and that have more 85 /// than one use, this map indicates what regularized operand to use. This 86 /// allows us to avoid legalizing the same thing more than once. 87 DenseMap<SDOperand, SDOperand> LegalizedNodes; 88 89 /// PromotedNodes - For nodes that are below legal width, and that have more 90 /// than one use, this map indicates what promoted value to use. This allows 91 /// us to avoid promoting the same thing more than once. 92 DenseMap<SDOperand, SDOperand> PromotedNodes; 93 94 /// ExpandedNodes - For nodes that need to be expanded this map indicates 95 /// which which operands are the expanded version of the input. This allows 96 /// us to avoid expanding the same node more than once. 97 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 98 99 /// SplitNodes - For vector nodes that need to be split, this map indicates 100 /// which which operands are the split version of the input. This allows us 101 /// to avoid splitting the same node more than once. 102 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 103 104 /// ScalarizedNodes - For nodes that need to be converted from vector types to 105 /// scalar types, this contains the mapping of ones we have already 106 /// processed to the result. 107 std::map<SDOperand, SDOperand> ScalarizedNodes; 108 109 void AddLegalizedOperand(SDOperand From, SDOperand To) { 110 LegalizedNodes.insert(std::make_pair(From, To)); 111 // If someone requests legalization of the new node, return itself. 112 if (From != To) 113 LegalizedNodes.insert(std::make_pair(To, To)); 114 } 115 void AddPromotedOperand(SDOperand From, SDOperand To) { 116 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 117 assert(isNew && "Got into the map somehow?"); 118 // If someone requests legalization of the new node, return itself. 119 LegalizedNodes.insert(std::make_pair(To, To)); 120 } 121 122public: 123 124 SelectionDAGLegalize(SelectionDAG &DAG); 125 126 /// getTypeAction - Return how we should legalize values of this type, either 127 /// it is already legal or we need to expand it into multiple registers of 128 /// smaller integer type, or we need to promote it to a larger type. 129 LegalizeAction getTypeAction(MVT::ValueType VT) const { 130 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 131 } 132 133 /// isTypeLegal - Return true if this type is legal on this target. 134 /// 135 bool isTypeLegal(MVT::ValueType VT) const { 136 return getTypeAction(VT) == Legal; 137 } 138 139 void LegalizeDAG(); 140 141private: 142 /// HandleOp - Legalize, Promote, or Expand the specified operand as 143 /// appropriate for its type. 144 void HandleOp(SDOperand Op); 145 146 /// LegalizeOp - We know that the specified value has a legal type. 147 /// Recursively ensure that the operands have legal types, then return the 148 /// result. 149 SDOperand LegalizeOp(SDOperand O); 150 151 /// UnrollVectorOp - We know that the given vector has a legal type, however 152 /// the operation it performs is not legal and is an operation that we have 153 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 154 /// operating on each element individually. 155 SDOperand UnrollVectorOp(SDOperand O); 156 157 /// PromoteOp - Given an operation that produces a value in an invalid type, 158 /// promote it to compute the value into a larger type. The produced value 159 /// will have the correct bits for the low portion of the register, but no 160 /// guarantee is made about the top bits: it may be zero, sign-extended, or 161 /// garbage. 162 SDOperand PromoteOp(SDOperand O); 163 164 /// ExpandOp - Expand the specified SDOperand into its two component pieces 165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 166 /// the LegalizeNodes map is filled in for any results that are not expanded, 167 /// the ExpandedNodes map is filled in for any results that are expanded, and 168 /// the Lo/Hi values are returned. This applies to integer types and Vector 169 /// types. 170 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 171 172 /// SplitVectorOp - Given an operand of vector type, break it down into 173 /// two smaller values. 174 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 175 176 /// ScalarizeVectorOp - Given an operand of single-element vector type 177 /// (e.g. v1f32), convert it into the equivalent operation that returns a 178 /// scalar (e.g. f32) value. 179 SDOperand ScalarizeVectorOp(SDOperand O); 180 181 /// isShuffleLegal - Return true if a vector shuffle is legal with the 182 /// specified mask and type. Targets can specify exactly which masks they 183 /// support and the code generator is tasked with not creating illegal masks. 184 /// 185 /// Note that this will also return true for shuffles that are promoted to a 186 /// different type. 187 /// 188 /// If this is a legal shuffle, this method returns the (possibly promoted) 189 /// build_vector Mask. If it's not a legal shuffle, it returns null. 190 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const; 191 192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 194 195 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 196 197 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned, 198 SDOperand &Hi); 199 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, 200 SDOperand Source); 201 202 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp); 203 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 204 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 205 SDOperand ExpandLegalINT_TO_FP(bool isSigned, 206 SDOperand LegalOp, 207 MVT::ValueType DestVT); 208 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT, 209 bool isSigned); 210 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT, 211 bool isSigned); 212 213 SDOperand ExpandBSWAP(SDOperand Op); 214 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 215 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 216 SDOperand &Lo, SDOperand &Hi); 217 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 218 SDOperand &Lo, SDOperand &Hi); 219 220 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 221 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 222 223 SDOperand getIntPtrConstant(uint64_t Val) { 224 return DAG.getConstant(Val, TLI.getPointerTy()); 225 } 226}; 227} 228 229/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 230/// specified mask and type. Targets can specify exactly which masks they 231/// support and the code generator is tasked with not creating illegal masks. 232/// 233/// Note that this will also return true for shuffles that are promoted to a 234/// different type. 235SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT, 236 SDOperand Mask) const { 237 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 238 default: return 0; 239 case TargetLowering::Legal: 240 case TargetLowering::Custom: 241 break; 242 case TargetLowering::Promote: { 243 // If this is promoted to a different type, convert the shuffle mask and 244 // ask if it is legal in the promoted type! 245 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 246 247 // If we changed # elements, change the shuffle mask. 248 unsigned NumEltsGrowth = 249 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT); 250 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 251 if (NumEltsGrowth > 1) { 252 // Renumber the elements. 253 SmallVector<SDOperand, 8> Ops; 254 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 255 SDOperand InOp = Mask.getOperand(i); 256 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 257 if (InOp.getOpcode() == ISD::UNDEF) 258 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 259 else { 260 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 261 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 262 } 263 } 264 } 265 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 266 } 267 VT = NVT; 268 break; 269 } 270 } 271 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 272} 273 274SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 275 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 276 ValueTypeActions(TLI.getValueTypeActions()) { 277 assert(MVT::LAST_VALUETYPE <= 32 && 278 "Too many value types for ValueTypeActions to hold!"); 279} 280 281/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 282/// contains all of a nodes operands before it contains the node. 283static void ComputeTopDownOrdering(SelectionDAG &DAG, 284 SmallVector<SDNode*, 64> &Order) { 285 286 DenseMap<SDNode*, unsigned> Visited; 287 std::vector<SDNode*> Worklist; 288 Worklist.reserve(128); 289 290 // Compute ordering from all of the leaves in the graphs, those (like the 291 // entry node) that have no operands. 292 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 293 E = DAG.allnodes_end(); I != E; ++I) { 294 if (I->getNumOperands() == 0) { 295 Visited[I] = 0 - 1U; 296 Worklist.push_back(I); 297 } 298 } 299 300 while (!Worklist.empty()) { 301 SDNode *N = Worklist.back(); 302 Worklist.pop_back(); 303 304 if (++Visited[N] != N->getNumOperands()) 305 continue; // Haven't visited all operands yet 306 307 Order.push_back(N); 308 309 // Now that we have N in, add anything that uses it if all of their operands 310 // are now done. 311 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 312 UI != E; ++UI) 313 Worklist.push_back(*UI); 314 } 315 316 assert(Order.size() == Visited.size() && 317 Order.size() == 318 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) && 319 "Error: DAG is cyclic!"); 320} 321 322 323void SelectionDAGLegalize::LegalizeDAG() { 324 LastCALLSEQ_END = DAG.getEntryNode(); 325 IsLegalizingCall = false; 326 327 // The legalize process is inherently a bottom-up recursive process (users 328 // legalize their uses before themselves). Given infinite stack space, we 329 // could just start legalizing on the root and traverse the whole graph. In 330 // practice however, this causes us to run out of stack space on large basic 331 // blocks. To avoid this problem, compute an ordering of the nodes where each 332 // node is only legalized after all of its operands are legalized. 333 SmallVector<SDNode*, 64> Order; 334 ComputeTopDownOrdering(DAG, Order); 335 336 for (unsigned i = 0, e = Order.size(); i != e; ++i) 337 HandleOp(SDOperand(Order[i], 0)); 338 339 // Finally, it's possible the root changed. Get the new root. 340 SDOperand OldRoot = DAG.getRoot(); 341 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 342 DAG.setRoot(LegalizedNodes[OldRoot]); 343 344 ExpandedNodes.clear(); 345 LegalizedNodes.clear(); 346 PromotedNodes.clear(); 347 SplitNodes.clear(); 348 ScalarizedNodes.clear(); 349 350 // Remove dead nodes now. 351 DAG.RemoveDeadNodes(); 352} 353 354 355/// FindCallEndFromCallStart - Given a chained node that is part of a call 356/// sequence, find the CALLSEQ_END node that terminates the call sequence. 357static SDNode *FindCallEndFromCallStart(SDNode *Node) { 358 if (Node->getOpcode() == ISD::CALLSEQ_END) 359 return Node; 360 if (Node->use_empty()) 361 return 0; // No CallSeqEnd 362 363 // The chain is usually at the end. 364 SDOperand TheChain(Node, Node->getNumValues()-1); 365 if (TheChain.getValueType() != MVT::Other) { 366 // Sometimes it's at the beginning. 367 TheChain = SDOperand(Node, 0); 368 if (TheChain.getValueType() != MVT::Other) { 369 // Otherwise, hunt for it. 370 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 371 if (Node->getValueType(i) == MVT::Other) { 372 TheChain = SDOperand(Node, i); 373 break; 374 } 375 376 // Otherwise, we walked into a node without a chain. 377 if (TheChain.getValueType() != MVT::Other) 378 return 0; 379 } 380 } 381 382 for (SDNode::use_iterator UI = Node->use_begin(), 383 E = Node->use_end(); UI != E; ++UI) { 384 385 // Make sure to only follow users of our token chain. 386 SDNode *User = *UI; 387 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 388 if (User->getOperand(i) == TheChain) 389 if (SDNode *Result = FindCallEndFromCallStart(User)) 390 return Result; 391 } 392 return 0; 393} 394 395/// FindCallStartFromCallEnd - Given a chained node that is part of a call 396/// sequence, find the CALLSEQ_START node that initiates the call sequence. 397static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 398 assert(Node && "Didn't find callseq_start for a call??"); 399 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 400 401 assert(Node->getOperand(0).getValueType() == MVT::Other && 402 "Node doesn't have a token chain argument!"); 403 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 404} 405 406/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 407/// see if any uses can reach Dest. If no dest operands can get to dest, 408/// legalize them, legalize ourself, and return false, otherwise, return true. 409/// 410/// Keep track of the nodes we fine that actually do lead to Dest in 411/// NodesLeadingTo. This avoids retraversing them exponential number of times. 412/// 413bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 414 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 415 if (N == Dest) return true; // N certainly leads to Dest :) 416 417 // If we've already processed this node and it does lead to Dest, there is no 418 // need to reprocess it. 419 if (NodesLeadingTo.count(N)) return true; 420 421 // If the first result of this node has been already legalized, then it cannot 422 // reach N. 423 switch (getTypeAction(N->getValueType(0))) { 424 case Legal: 425 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 426 break; 427 case Promote: 428 if (PromotedNodes.count(SDOperand(N, 0))) return false; 429 break; 430 case Expand: 431 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 432 break; 433 } 434 435 // Okay, this node has not already been legalized. Check and legalize all 436 // operands. If none lead to Dest, then we can legalize this node. 437 bool OperandsLeadToDest = false; 438 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 439 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 440 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 441 442 if (OperandsLeadToDest) { 443 NodesLeadingTo.insert(N); 444 return true; 445 } 446 447 // Okay, this node looks safe, legalize it and return false. 448 HandleOp(SDOperand(N, 0)); 449 return false; 450} 451 452/// HandleOp - Legalize, Promote, or Expand the specified operand as 453/// appropriate for its type. 454void SelectionDAGLegalize::HandleOp(SDOperand Op) { 455 MVT::ValueType VT = Op.getValueType(); 456 switch (getTypeAction(VT)) { 457 default: assert(0 && "Bad type action!"); 458 case Legal: (void)LegalizeOp(Op); break; 459 case Promote: (void)PromoteOp(Op); break; 460 case Expand: 461 if (!MVT::isVector(VT)) { 462 // If this is an illegal scalar, expand it into its two component 463 // pieces. 464 SDOperand X, Y; 465 if (Op.getOpcode() == ISD::TargetConstant) 466 break; // Allow illegal target nodes. 467 ExpandOp(Op, X, Y); 468 } else if (MVT::getVectorNumElements(VT) == 1) { 469 // If this is an illegal single element vector, convert it to a 470 // scalar operation. 471 (void)ScalarizeVectorOp(Op); 472 } else { 473 // Otherwise, this is an illegal multiple element vector. 474 // Split it in half and legalize both parts. 475 SDOperand X, Y; 476 SplitVectorOp(Op, X, Y); 477 } 478 break; 479 } 480} 481 482/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 483/// a load from the constant pool. 484static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 485 SelectionDAG &DAG, TargetLowering &TLI) { 486 bool Extend = false; 487 488 // If a FP immediate is precise when represented as a float and if the 489 // target can do an extending load from float to double, we put it into 490 // the constant pool as a float, even if it's is statically typed as a 491 // double. 492 MVT::ValueType VT = CFP->getValueType(0); 493 bool isDouble = VT == MVT::f64; 494 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT), 495 CFP->getValueAPF()); 496 if (!UseCP) { 497 if (VT!=MVT::f64 && VT!=MVT::f32) 498 assert(0 && "Invalid type expansion"); 499 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(), 500 isDouble ? MVT::i64 : MVT::i32); 501 } 502 503 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) && 504 // Only do this if the target has a native EXTLOAD instruction from f32. 505 // Do not try to be clever about long doubles (so far) 506 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) { 507 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy)); 508 VT = MVT::f32; 509 Extend = true; 510 } 511 512 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 513 if (Extend) { 514 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), 515 CPIdx, NULL, 0, MVT::f32); 516 } else { 517 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 518 } 519} 520 521 522/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 523/// operations. 524static 525SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT, 526 SelectionDAG &DAG, TargetLowering &TLI) { 527 MVT::ValueType VT = Node->getValueType(0); 528 MVT::ValueType SrcVT = Node->getOperand(1).getValueType(); 529 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 530 "fcopysign expansion only supported for f32 and f64"); 531 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 532 533 // First get the sign bit of second operand. 534 SDOperand Mask1 = (SrcVT == MVT::f64) 535 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 536 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 537 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 538 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 539 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 540 // Shift right or sign-extend it if the two operands have different types. 541 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT); 542 if (SizeDiff > 0) { 543 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 544 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 545 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 546 } else if (SizeDiff < 0) 547 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 548 549 // Clear the sign bit of first operand. 550 SDOperand Mask2 = (VT == MVT::f64) 551 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 552 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 553 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 554 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 555 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 556 557 // Or the value with the sign bit. 558 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 559 return Result; 560} 561 562/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 563static 564SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 565 TargetLowering &TLI) { 566 SDOperand Chain = ST->getChain(); 567 SDOperand Ptr = ST->getBasePtr(); 568 SDOperand Val = ST->getValue(); 569 MVT::ValueType VT = Val.getValueType(); 570 int Alignment = ST->getAlignment(); 571 int SVOffset = ST->getSrcValueOffset(); 572 if (MVT::isFloatingPoint(ST->getStoredVT())) { 573 // Expand to a bitconvert of the value to the integer type of the 574 // same size, then a (misaligned) int store. 575 MVT::ValueType intVT; 576 if (VT==MVT::f64) 577 intVT = MVT::i64; 578 else if (VT==MVT::f32) 579 intVT = MVT::i32; 580 else 581 assert(0 && "Unaligned load of unsupported floating point type"); 582 583 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 584 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 585 SVOffset, ST->isVolatile(), Alignment); 586 } 587 assert(MVT::isInteger(ST->getStoredVT()) && 588 "Unaligned store of unknown type."); 589 // Get the half-size VT 590 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1; 591 int NumBits = MVT::getSizeInBits(NewStoredVT); 592 int IncrementSize = NumBits / 8; 593 594 // Divide the stored value in two parts. 595 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 596 SDOperand Lo = Val; 597 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 598 599 // Store the two parts 600 SDOperand Store1, Store2; 601 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 602 ST->getSrcValue(), SVOffset, NewStoredVT, 603 ST->isVolatile(), Alignment); 604 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 605 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 606 Alignment = MinAlign(Alignment, IncrementSize); 607 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 608 ST->getSrcValue(), SVOffset + IncrementSize, 609 NewStoredVT, ST->isVolatile(), Alignment); 610 611 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 612} 613 614/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 615static 616SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 617 TargetLowering &TLI) { 618 int SVOffset = LD->getSrcValueOffset(); 619 SDOperand Chain = LD->getChain(); 620 SDOperand Ptr = LD->getBasePtr(); 621 MVT::ValueType VT = LD->getValueType(0); 622 MVT::ValueType LoadedVT = LD->getLoadedVT(); 623 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT)) { 624 // Expand to a (misaligned) integer load of the same size, 625 // then bitconvert to floating point. 626 MVT::ValueType intVT; 627 if (LoadedVT == MVT::f64) 628 intVT = MVT::i64; 629 else if (LoadedVT == MVT::f32) 630 intVT = MVT::i32; 631 else 632 assert(0 && "Unaligned load of unsupported floating point type"); 633 634 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 635 SVOffset, LD->isVolatile(), 636 LD->getAlignment()); 637 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 638 if (LoadedVT != VT) 639 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 640 641 SDOperand Ops[] = { Result, Chain }; 642 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 643 Ops, 2); 644 } 645 assert((MVT::isInteger(LoadedVT) || MVT::isVector(LoadedVT)) && 646 "Unaligned load of unsupported type."); 647 648 // Compute the new VT that is half the size of the old one. We either have an 649 // integer MVT or we have a vector MVT. 650 unsigned NumBits = MVT::getSizeInBits(LoadedVT); 651 MVT::ValueType NewLoadedVT; 652 if (!MVT::isVector(LoadedVT)) { 653 NewLoadedVT = MVT::getIntegerType(NumBits/2); 654 } else { 655 // FIXME: This is not right for <1 x anything> it is also not right for 656 // non-power-of-two vectors. 657 NewLoadedVT = MVT::getVectorType(MVT::getVectorElementType(LoadedVT), 658 MVT::getVectorNumElements(LoadedVT)/2); 659 } 660 NumBits >>= 1; 661 662 unsigned Alignment = LD->getAlignment(); 663 unsigned IncrementSize = NumBits / 8; 664 ISD::LoadExtType HiExtType = LD->getExtensionType(); 665 666 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 667 if (HiExtType == ISD::NON_EXTLOAD) 668 HiExtType = ISD::ZEXTLOAD; 669 670 // Load the value in two parts 671 SDOperand Lo, Hi; 672 if (TLI.isLittleEndian()) { 673 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 674 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 675 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 676 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 677 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 678 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 679 MinAlign(Alignment, IncrementSize)); 680 } else { 681 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 682 NewLoadedVT,LD->isVolatile(), Alignment); 683 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 684 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 685 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 686 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 687 MinAlign(Alignment, IncrementSize)); 688 } 689 690 // aggregate the two parts 691 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 692 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 693 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 694 695 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 696 Hi.getValue(1)); 697 698 SDOperand Ops[] = { Result, TF }; 699 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2); 700} 701 702/// UnrollVectorOp - We know that the given vector has a legal type, however 703/// the operation it performs is not legal and is an operation that we have 704/// no way of lowering. "Unroll" the vector, splitting out the scalars and 705/// operating on each element individually. 706SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 707 MVT::ValueType VT = Op.getValueType(); 708 assert(isTypeLegal(VT) && 709 "Caller should expand or promote operands that are not legal!"); 710 assert(Op.Val->getNumValues() == 1 && 711 "Can't unroll a vector with multiple results!"); 712 unsigned NE = MVT::getVectorNumElements(VT); 713 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 714 715 SmallVector<SDOperand, 8> Scalars; 716 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 717 for (unsigned i = 0; i != NE; ++i) { 718 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 719 SDOperand Operand = Op.getOperand(j); 720 MVT::ValueType OperandVT = Operand.getValueType(); 721 if (MVT::isVector(OperandVT)) { 722 // A vector operand; extract a single element. 723 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT); 724 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 725 OperandEltVT, 726 Operand, 727 DAG.getConstant(i, MVT::i32)); 728 } else { 729 // A scalar operand; just use it as is. 730 Operands[j] = Operand; 731 } 732 } 733 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 734 &Operands[0], Operands.size())); 735 } 736 737 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 738} 739 740/// GetFPLibCall - Return the right libcall for the given floating point type. 741static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT, 742 RTLIB::Libcall Call_F32, 743 RTLIB::Libcall Call_F64, 744 RTLIB::Libcall Call_F80, 745 RTLIB::Libcall Call_PPCF128) { 746 return 747 VT == MVT::f32 ? Call_F32 : 748 VT == MVT::f64 ? Call_F64 : 749 VT == MVT::f80 ? Call_F80 : 750 VT == MVT::ppcf128 ? Call_PPCF128 : 751 RTLIB::UNKNOWN_LIBCALL; 752} 753 754/// LegalizeOp - We know that the specified value has a legal type, and 755/// that its operands are legal. Now ensure that the operation itself 756/// is legal, recursively ensuring that the operands' operations remain 757/// legal. 758SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 759 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 760 return Op; 761 762 assert(isTypeLegal(Op.getValueType()) && 763 "Caller should expand or promote operands that are not legal!"); 764 SDNode *Node = Op.Val; 765 766 // If this operation defines any values that cannot be represented in a 767 // register on this target, make sure to expand or promote them. 768 if (Node->getNumValues() > 1) { 769 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 770 if (getTypeAction(Node->getValueType(i)) != Legal) { 771 HandleOp(Op.getValue(i)); 772 assert(LegalizedNodes.count(Op) && 773 "Handling didn't add legal operands!"); 774 return LegalizedNodes[Op]; 775 } 776 } 777 778 // Note that LegalizeOp may be reentered even from single-use nodes, which 779 // means that we always must cache transformed nodes. 780 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 781 if (I != LegalizedNodes.end()) return I->second; 782 783 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 784 SDOperand Result = Op; 785 bool isCustom = false; 786 787 switch (Node->getOpcode()) { 788 case ISD::FrameIndex: 789 case ISD::EntryToken: 790 case ISD::Register: 791 case ISD::BasicBlock: 792 case ISD::TargetFrameIndex: 793 case ISD::TargetJumpTable: 794 case ISD::TargetConstant: 795 case ISD::TargetConstantFP: 796 case ISD::TargetConstantPool: 797 case ISD::TargetGlobalAddress: 798 case ISD::TargetGlobalTLSAddress: 799 case ISD::TargetExternalSymbol: 800 case ISD::VALUETYPE: 801 case ISD::SRCVALUE: 802 case ISD::STRING: 803 case ISD::CONDCODE: 804 // Primitives must all be legal. 805 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 806 "This must be legal!"); 807 break; 808 default: 809 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 810 // If this is a target node, legalize it by legalizing the operands then 811 // passing it through. 812 SmallVector<SDOperand, 8> Ops; 813 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 814 Ops.push_back(LegalizeOp(Node->getOperand(i))); 815 816 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 817 818 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 819 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 820 return Result.getValue(Op.ResNo); 821 } 822 // Otherwise this is an unhandled builtin node. splat. 823#ifndef NDEBUG 824 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 825#endif 826 assert(0 && "Do not know how to legalize this operator!"); 827 abort(); 828 case ISD::GLOBAL_OFFSET_TABLE: 829 case ISD::GlobalAddress: 830 case ISD::GlobalTLSAddress: 831 case ISD::ExternalSymbol: 832 case ISD::ConstantPool: 833 case ISD::JumpTable: // Nothing to do. 834 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 835 default: assert(0 && "This action is not supported yet!"); 836 case TargetLowering::Custom: 837 Tmp1 = TLI.LowerOperation(Op, DAG); 838 if (Tmp1.Val) Result = Tmp1; 839 // FALLTHROUGH if the target doesn't want to lower this op after all. 840 case TargetLowering::Legal: 841 break; 842 } 843 break; 844 case ISD::FRAMEADDR: 845 case ISD::RETURNADDR: 846 // The only option for these nodes is to custom lower them. If the target 847 // does not custom lower them, then return zero. 848 Tmp1 = TLI.LowerOperation(Op, DAG); 849 if (Tmp1.Val) 850 Result = Tmp1; 851 else 852 Result = DAG.getConstant(0, TLI.getPointerTy()); 853 break; 854 case ISD::FRAME_TO_ARGS_OFFSET: { 855 MVT::ValueType VT = Node->getValueType(0); 856 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 857 default: assert(0 && "This action is not supported yet!"); 858 case TargetLowering::Custom: 859 Result = TLI.LowerOperation(Op, DAG); 860 if (Result.Val) break; 861 // Fall Thru 862 case TargetLowering::Legal: 863 Result = DAG.getConstant(0, VT); 864 break; 865 } 866 } 867 break; 868 case ISD::EXCEPTIONADDR: { 869 Tmp1 = LegalizeOp(Node->getOperand(0)); 870 MVT::ValueType VT = Node->getValueType(0); 871 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 872 default: assert(0 && "This action is not supported yet!"); 873 case TargetLowering::Expand: { 874 unsigned Reg = TLI.getExceptionAddressRegister(); 875 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 876 } 877 break; 878 case TargetLowering::Custom: 879 Result = TLI.LowerOperation(Op, DAG); 880 if (Result.Val) break; 881 // Fall Thru 882 case TargetLowering::Legal: { 883 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 884 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 885 Ops, 2); 886 break; 887 } 888 } 889 } 890 if (Result.Val->getNumValues() == 1) break; 891 892 assert(Result.Val->getNumValues() == 2 && 893 "Cannot return more than two values!"); 894 895 // Since we produced two values, make sure to remember that we 896 // legalized both of them. 897 Tmp1 = LegalizeOp(Result); 898 Tmp2 = LegalizeOp(Result.getValue(1)); 899 AddLegalizedOperand(Op.getValue(0), Tmp1); 900 AddLegalizedOperand(Op.getValue(1), Tmp2); 901 return Op.ResNo ? Tmp2 : Tmp1; 902 case ISD::EHSELECTION: { 903 Tmp1 = LegalizeOp(Node->getOperand(0)); 904 Tmp2 = LegalizeOp(Node->getOperand(1)); 905 MVT::ValueType VT = Node->getValueType(0); 906 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 907 default: assert(0 && "This action is not supported yet!"); 908 case TargetLowering::Expand: { 909 unsigned Reg = TLI.getExceptionSelectorRegister(); 910 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 911 } 912 break; 913 case TargetLowering::Custom: 914 Result = TLI.LowerOperation(Op, DAG); 915 if (Result.Val) break; 916 // Fall Thru 917 case TargetLowering::Legal: { 918 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 919 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), 920 Ops, 2); 921 break; 922 } 923 } 924 } 925 if (Result.Val->getNumValues() == 1) break; 926 927 assert(Result.Val->getNumValues() == 2 && 928 "Cannot return more than two values!"); 929 930 // Since we produced two values, make sure to remember that we 931 // legalized both of them. 932 Tmp1 = LegalizeOp(Result); 933 Tmp2 = LegalizeOp(Result.getValue(1)); 934 AddLegalizedOperand(Op.getValue(0), Tmp1); 935 AddLegalizedOperand(Op.getValue(1), Tmp2); 936 return Op.ResNo ? Tmp2 : Tmp1; 937 case ISD::EH_RETURN: { 938 MVT::ValueType VT = Node->getValueType(0); 939 // The only "good" option for this node is to custom lower it. 940 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 941 default: assert(0 && "This action is not supported at all!"); 942 case TargetLowering::Custom: 943 Result = TLI.LowerOperation(Op, DAG); 944 if (Result.Val) break; 945 // Fall Thru 946 case TargetLowering::Legal: 947 // Target does not know, how to lower this, lower to noop 948 Result = LegalizeOp(Node->getOperand(0)); 949 break; 950 } 951 } 952 break; 953 case ISD::AssertSext: 954 case ISD::AssertZext: 955 Tmp1 = LegalizeOp(Node->getOperand(0)); 956 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 957 break; 958 case ISD::MERGE_VALUES: 959 // Legalize eliminates MERGE_VALUES nodes. 960 Result = Node->getOperand(Op.ResNo); 961 break; 962 case ISD::CopyFromReg: 963 Tmp1 = LegalizeOp(Node->getOperand(0)); 964 Result = Op.getValue(0); 965 if (Node->getNumValues() == 2) { 966 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 967 } else { 968 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 969 if (Node->getNumOperands() == 3) { 970 Tmp2 = LegalizeOp(Node->getOperand(2)); 971 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 972 } else { 973 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 974 } 975 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 976 } 977 // Since CopyFromReg produces two values, make sure to remember that we 978 // legalized both of them. 979 AddLegalizedOperand(Op.getValue(0), Result); 980 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 981 return Result.getValue(Op.ResNo); 982 case ISD::UNDEF: { 983 MVT::ValueType VT = Op.getValueType(); 984 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 985 default: assert(0 && "This action is not supported yet!"); 986 case TargetLowering::Expand: 987 if (MVT::isInteger(VT)) 988 Result = DAG.getConstant(0, VT); 989 else if (MVT::isFloatingPoint(VT)) 990 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)), 991 VT); 992 else 993 assert(0 && "Unknown value type!"); 994 break; 995 case TargetLowering::Legal: 996 break; 997 } 998 break; 999 } 1000 1001 case ISD::INTRINSIC_W_CHAIN: 1002 case ISD::INTRINSIC_WO_CHAIN: 1003 case ISD::INTRINSIC_VOID: { 1004 SmallVector<SDOperand, 8> Ops; 1005 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1006 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1007 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1008 1009 // Allow the target to custom lower its intrinsics if it wants to. 1010 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1011 TargetLowering::Custom) { 1012 Tmp3 = TLI.LowerOperation(Result, DAG); 1013 if (Tmp3.Val) Result = Tmp3; 1014 } 1015 1016 if (Result.Val->getNumValues() == 1) break; 1017 1018 // Must have return value and chain result. 1019 assert(Result.Val->getNumValues() == 2 && 1020 "Cannot return more than two values!"); 1021 1022 // Since loads produce two values, make sure to remember that we 1023 // legalized both of them. 1024 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1025 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1026 return Result.getValue(Op.ResNo); 1027 } 1028 1029 case ISD::LOCATION: 1030 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 1031 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1032 1033 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 1034 case TargetLowering::Promote: 1035 default: assert(0 && "This action is not supported yet!"); 1036 case TargetLowering::Expand: { 1037 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1038 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1039 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 1040 1041 if (MMI && (useDEBUG_LOC || useLABEL)) { 1042 const std::string &FName = 1043 cast<StringSDNode>(Node->getOperand(3))->getValue(); 1044 const std::string &DirName = 1045 cast<StringSDNode>(Node->getOperand(4))->getValue(); 1046 unsigned SrcFile = MMI->RecordSource(DirName, FName); 1047 1048 SmallVector<SDOperand, 8> Ops; 1049 Ops.push_back(Tmp1); // chain 1050 SDOperand LineOp = Node->getOperand(1); 1051 SDOperand ColOp = Node->getOperand(2); 1052 1053 if (useDEBUG_LOC) { 1054 Ops.push_back(LineOp); // line # 1055 Ops.push_back(ColOp); // col # 1056 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1057 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1058 } else { 1059 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 1060 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 1061 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile); 1062 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 1063 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size()); 1064 } 1065 } else { 1066 Result = Tmp1; // chain 1067 } 1068 break; 1069 } 1070 case TargetLowering::Legal: 1071 if (Tmp1 != Node->getOperand(0) || 1072 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1073 SmallVector<SDOperand, 8> Ops; 1074 Ops.push_back(Tmp1); 1075 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1076 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1077 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1078 } else { 1079 // Otherwise promote them. 1080 Ops.push_back(PromoteOp(Node->getOperand(1))); 1081 Ops.push_back(PromoteOp(Node->getOperand(2))); 1082 } 1083 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1084 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1085 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1086 } 1087 break; 1088 } 1089 break; 1090 1091 case ISD::DEBUG_LOC: 1092 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1093 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1094 default: assert(0 && "This action is not supported yet!"); 1095 case TargetLowering::Legal: 1096 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1097 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1098 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1099 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1100 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1101 break; 1102 } 1103 break; 1104 1105 case ISD::LABEL: 1106 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!"); 1107 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1108 default: assert(0 && "This action is not supported yet!"); 1109 case TargetLowering::Legal: 1110 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1111 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1112 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1113 break; 1114 case TargetLowering::Expand: 1115 Result = LegalizeOp(Node->getOperand(0)); 1116 break; 1117 } 1118 break; 1119 1120 case ISD::Constant: { 1121 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1122 unsigned opAction = 1123 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1124 1125 // We know we don't need to expand constants here, constants only have one 1126 // value and we check that it is fine above. 1127 1128 if (opAction == TargetLowering::Custom) { 1129 Tmp1 = TLI.LowerOperation(Result, DAG); 1130 if (Tmp1.Val) 1131 Result = Tmp1; 1132 } 1133 break; 1134 } 1135 case ISD::ConstantFP: { 1136 // Spill FP immediates to the constant pool if the target cannot directly 1137 // codegen them. Targets often have some immediate values that can be 1138 // efficiently generated into an FP register without a load. We explicitly 1139 // leave these constants as ConstantFP nodes for the target to deal with. 1140 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1141 1142 // Check to see if this FP immediate is already legal. 1143 bool isLegal = false; 1144 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1145 E = TLI.legal_fpimm_end(); I != E; ++I) 1146 if (CFP->isExactlyValue(*I)) { 1147 isLegal = true; 1148 break; 1149 } 1150 1151 // If this is a legal constant, turn it into a TargetConstantFP node. 1152 if (isLegal) { 1153 Result = DAG.getTargetConstantFP(CFP->getValueAPF(), 1154 CFP->getValueType(0)); 1155 break; 1156 } 1157 1158 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1159 default: assert(0 && "This action is not supported yet!"); 1160 case TargetLowering::Custom: 1161 Tmp3 = TLI.LowerOperation(Result, DAG); 1162 if (Tmp3.Val) { 1163 Result = Tmp3; 1164 break; 1165 } 1166 // FALLTHROUGH 1167 case TargetLowering::Expand: 1168 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1169 } 1170 break; 1171 } 1172 case ISD::TokenFactor: 1173 if (Node->getNumOperands() == 2) { 1174 Tmp1 = LegalizeOp(Node->getOperand(0)); 1175 Tmp2 = LegalizeOp(Node->getOperand(1)); 1176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1177 } else if (Node->getNumOperands() == 3) { 1178 Tmp1 = LegalizeOp(Node->getOperand(0)); 1179 Tmp2 = LegalizeOp(Node->getOperand(1)); 1180 Tmp3 = LegalizeOp(Node->getOperand(2)); 1181 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1182 } else { 1183 SmallVector<SDOperand, 8> Ops; 1184 // Legalize the operands. 1185 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1186 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1187 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1188 } 1189 break; 1190 1191 case ISD::FORMAL_ARGUMENTS: 1192 case ISD::CALL: 1193 // The only option for this is to custom lower it. 1194 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1195 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1196 1197 // The number of incoming and outgoing values should match; unless the final 1198 // outgoing value is a flag. 1199 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1200 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1201 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1202 MVT::Flag)) && 1203 "Lowering call/formal_arguments produced unexpected # results!"); 1204 1205 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1206 // remember that we legalized all of them, so it doesn't get relegalized. 1207 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1208 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1209 continue; 1210 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1211 if (Op.ResNo == i) 1212 Tmp2 = Tmp1; 1213 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1214 } 1215 return Tmp2; 1216 case ISD::EXTRACT_SUBREG: { 1217 Tmp1 = LegalizeOp(Node->getOperand(0)); 1218 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1219 assert(idx && "Operand must be a constant"); 1220 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1221 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1222 } 1223 break; 1224 case ISD::INSERT_SUBREG: { 1225 Tmp1 = LegalizeOp(Node->getOperand(0)); 1226 Tmp2 = LegalizeOp(Node->getOperand(1)); 1227 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1228 assert(idx && "Operand must be a constant"); 1229 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1230 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1231 } 1232 break; 1233 case ISD::BUILD_VECTOR: 1234 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1235 default: assert(0 && "This action is not supported yet!"); 1236 case TargetLowering::Custom: 1237 Tmp3 = TLI.LowerOperation(Result, DAG); 1238 if (Tmp3.Val) { 1239 Result = Tmp3; 1240 break; 1241 } 1242 // FALLTHROUGH 1243 case TargetLowering::Expand: 1244 Result = ExpandBUILD_VECTOR(Result.Val); 1245 break; 1246 } 1247 break; 1248 case ISD::INSERT_VECTOR_ELT: 1249 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1250 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal 1251 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1252 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1253 1254 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1255 Node->getValueType(0))) { 1256 default: assert(0 && "This action is not supported yet!"); 1257 case TargetLowering::Legal: 1258 break; 1259 case TargetLowering::Custom: 1260 Tmp4 = TLI.LowerOperation(Result, DAG); 1261 if (Tmp4.Val) { 1262 Result = Tmp4; 1263 break; 1264 } 1265 // FALLTHROUGH 1266 case TargetLowering::Expand: { 1267 // If the insert index is a constant, codegen this as a scalar_to_vector, 1268 // then a shuffle that inserts it into the right position in the vector. 1269 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1270 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1271 Tmp1.getValueType(), Tmp2); 1272 1273 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType()); 1274 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts); 1275 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT); 1276 1277 // We generate a shuffle of InVec and ScVec, so the shuffle mask should 1278 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of 1279 // the RHS. 1280 SmallVector<SDOperand, 8> ShufOps; 1281 for (unsigned i = 0; i != NumElts; ++i) { 1282 if (i != InsertPos->getValue()) 1283 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1284 else 1285 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1286 } 1287 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1288 &ShufOps[0], ShufOps.size()); 1289 1290 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1291 Tmp1, ScVec, ShufMask); 1292 Result = LegalizeOp(Result); 1293 break; 1294 } 1295 1296 // If the target doesn't support this, we have to spill the input vector 1297 // to a temporary stack slot, update the element, then reload it. This is 1298 // badness. We could also load the value into a vector register (either 1299 // with a "move to register" or "extload into register" instruction, then 1300 // permute it into place, if the idx is a constant and if the idx is 1301 // supported by the target. 1302 MVT::ValueType VT = Tmp1.getValueType(); 1303 MVT::ValueType EltVT = Tmp2.getValueType(); 1304 MVT::ValueType IdxVT = Tmp3.getValueType(); 1305 MVT::ValueType PtrVT = TLI.getPointerTy(); 1306 SDOperand StackPtr = DAG.CreateStackTemporary(VT); 1307 // Store the vector. 1308 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0); 1309 1310 // Truncate or zero extend offset to target pointer type. 1311 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 1312 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 1313 // Add the offset to the index. 1314 unsigned EltSize = MVT::getSizeInBits(EltVT)/8; 1315 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 1316 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 1317 // Store the scalar value. 1318 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0); 1319 // Load the updated vector. 1320 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0); 1321 break; 1322 } 1323 } 1324 break; 1325 case ISD::SCALAR_TO_VECTOR: 1326 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1327 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1328 break; 1329 } 1330 1331 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1332 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1333 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1334 Node->getValueType(0))) { 1335 default: assert(0 && "This action is not supported yet!"); 1336 case TargetLowering::Legal: 1337 break; 1338 case TargetLowering::Custom: 1339 Tmp3 = TLI.LowerOperation(Result, DAG); 1340 if (Tmp3.Val) { 1341 Result = Tmp3; 1342 break; 1343 } 1344 // FALLTHROUGH 1345 case TargetLowering::Expand: 1346 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1347 break; 1348 } 1349 break; 1350 case ISD::VECTOR_SHUFFLE: 1351 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1352 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1353 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1354 1355 // Allow targets to custom lower the SHUFFLEs they support. 1356 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1357 default: assert(0 && "Unknown operation action!"); 1358 case TargetLowering::Legal: 1359 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1360 "vector shuffle should not be created if not legal!"); 1361 break; 1362 case TargetLowering::Custom: 1363 Tmp3 = TLI.LowerOperation(Result, DAG); 1364 if (Tmp3.Val) { 1365 Result = Tmp3; 1366 break; 1367 } 1368 // FALLTHROUGH 1369 case TargetLowering::Expand: { 1370 MVT::ValueType VT = Node->getValueType(0); 1371 MVT::ValueType EltVT = MVT::getVectorElementType(VT); 1372 MVT::ValueType PtrVT = TLI.getPointerTy(); 1373 SDOperand Mask = Node->getOperand(2); 1374 unsigned NumElems = Mask.getNumOperands(); 1375 SmallVector<SDOperand,8> Ops; 1376 for (unsigned i = 0; i != NumElems; ++i) { 1377 SDOperand Arg = Mask.getOperand(i); 1378 if (Arg.getOpcode() == ISD::UNDEF) { 1379 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1380 } else { 1381 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1382 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1383 if (Idx < NumElems) 1384 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1385 DAG.getConstant(Idx, PtrVT))); 1386 else 1387 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1388 DAG.getConstant(Idx - NumElems, PtrVT))); 1389 } 1390 } 1391 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1392 break; 1393 } 1394 case TargetLowering::Promote: { 1395 // Change base type to a different vector type. 1396 MVT::ValueType OVT = Node->getValueType(0); 1397 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1398 1399 // Cast the two input vectors. 1400 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1401 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1402 1403 // Convert the shuffle mask to the right # elements. 1404 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1405 assert(Tmp3.Val && "Shuffle not legal?"); 1406 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1407 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1408 break; 1409 } 1410 } 1411 break; 1412 1413 case ISD::EXTRACT_VECTOR_ELT: 1414 Tmp1 = Node->getOperand(0); 1415 Tmp2 = LegalizeOp(Node->getOperand(1)); 1416 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1417 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1418 break; 1419 1420 case ISD::EXTRACT_SUBVECTOR: 1421 Tmp1 = Node->getOperand(0); 1422 Tmp2 = LegalizeOp(Node->getOperand(1)); 1423 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1424 Result = ExpandEXTRACT_SUBVECTOR(Result); 1425 break; 1426 1427 case ISD::CALLSEQ_START: { 1428 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1429 1430 // Recursively Legalize all of the inputs of the call end that do not lead 1431 // to this call start. This ensures that any libcalls that need be inserted 1432 // are inserted *before* the CALLSEQ_START. 1433 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1434 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1435 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1436 NodesLeadingTo); 1437 } 1438 1439 // Now that we legalized all of the inputs (which may have inserted 1440 // libcalls) create the new CALLSEQ_START node. 1441 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1442 1443 // Merge in the last call, to ensure that this call start after the last 1444 // call ended. 1445 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1446 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1447 Tmp1 = LegalizeOp(Tmp1); 1448 } 1449 1450 // Do not try to legalize the target-specific arguments (#1+). 1451 if (Tmp1 != Node->getOperand(0)) { 1452 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1453 Ops[0] = Tmp1; 1454 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1455 } 1456 1457 // Remember that the CALLSEQ_START is legalized. 1458 AddLegalizedOperand(Op.getValue(0), Result); 1459 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1460 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1461 1462 // Now that the callseq_start and all of the non-call nodes above this call 1463 // sequence have been legalized, legalize the call itself. During this 1464 // process, no libcalls can/will be inserted, guaranteeing that no calls 1465 // can overlap. 1466 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1467 SDOperand InCallSEQ = LastCALLSEQ_END; 1468 // Note that we are selecting this call! 1469 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1470 IsLegalizingCall = true; 1471 1472 // Legalize the call, starting from the CALLSEQ_END. 1473 LegalizeOp(LastCALLSEQ_END); 1474 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1475 return Result; 1476 } 1477 case ISD::CALLSEQ_END: 1478 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1479 // will cause this node to be legalized as well as handling libcalls right. 1480 if (LastCALLSEQ_END.Val != Node) { 1481 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1482 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1483 assert(I != LegalizedNodes.end() && 1484 "Legalizing the call start should have legalized this node!"); 1485 return I->second; 1486 } 1487 1488 // Otherwise, the call start has been legalized and everything is going 1489 // according to plan. Just legalize ourselves normally here. 1490 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1491 // Do not try to legalize the target-specific arguments (#1+), except for 1492 // an optional flag input. 1493 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1494 if (Tmp1 != Node->getOperand(0)) { 1495 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1496 Ops[0] = Tmp1; 1497 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1498 } 1499 } else { 1500 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1501 if (Tmp1 != Node->getOperand(0) || 1502 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1503 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1504 Ops[0] = Tmp1; 1505 Ops.back() = Tmp2; 1506 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1507 } 1508 } 1509 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1510 // This finishes up call legalization. 1511 IsLegalizingCall = false; 1512 1513 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1514 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1515 if (Node->getNumValues() == 2) 1516 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1517 return Result.getValue(Op.ResNo); 1518 case ISD::DYNAMIC_STACKALLOC: { 1519 MVT::ValueType VT = Node->getValueType(0); 1520 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1521 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1522 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1523 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1524 1525 Tmp1 = Result.getValue(0); 1526 Tmp2 = Result.getValue(1); 1527 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1528 default: assert(0 && "This action is not supported yet!"); 1529 case TargetLowering::Expand: { 1530 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1531 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1532 " not tell us which reg is the stack pointer!"); 1533 SDOperand Chain = Tmp1.getOperand(0); 1534 1535 // Chain the dynamic stack allocation so that it doesn't modify the stack 1536 // pointer when other instructions are using the stack. 1537 Chain = DAG.getCALLSEQ_START(Chain, 1538 DAG.getConstant(0, TLI.getPointerTy())); 1539 1540 SDOperand Size = Tmp2.getOperand(1); 1541 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1542 Chain = SP.getValue(1); 1543 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1544 unsigned StackAlign = 1545 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1546 if (Align > StackAlign) 1547 SP = DAG.getNode(ISD::AND, VT, SP, 1548 DAG.getConstant(-(uint64_t)Align, VT)); 1549 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1550 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1551 1552 Tmp2 = 1553 DAG.getCALLSEQ_END(Chain, 1554 DAG.getConstant(0, TLI.getPointerTy()), 1555 DAG.getConstant(0, TLI.getPointerTy()), 1556 SDOperand()); 1557 1558 Tmp1 = LegalizeOp(Tmp1); 1559 Tmp2 = LegalizeOp(Tmp2); 1560 break; 1561 } 1562 case TargetLowering::Custom: 1563 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1564 if (Tmp3.Val) { 1565 Tmp1 = LegalizeOp(Tmp3); 1566 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1567 } 1568 break; 1569 case TargetLowering::Legal: 1570 break; 1571 } 1572 // Since this op produce two values, make sure to remember that we 1573 // legalized both of them. 1574 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1575 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1576 return Op.ResNo ? Tmp2 : Tmp1; 1577 } 1578 case ISD::INLINEASM: { 1579 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1580 bool Changed = false; 1581 // Legalize all of the operands of the inline asm, in case they are nodes 1582 // that need to be expanded or something. Note we skip the asm string and 1583 // all of the TargetConstant flags. 1584 SDOperand Op = LegalizeOp(Ops[0]); 1585 Changed = Op != Ops[0]; 1586 Ops[0] = Op; 1587 1588 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1589 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1590 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1591 for (++i; NumVals; ++i, --NumVals) { 1592 SDOperand Op = LegalizeOp(Ops[i]); 1593 if (Op != Ops[i]) { 1594 Changed = true; 1595 Ops[i] = Op; 1596 } 1597 } 1598 } 1599 1600 if (HasInFlag) { 1601 Op = LegalizeOp(Ops.back()); 1602 Changed |= Op != Ops.back(); 1603 Ops.back() = Op; 1604 } 1605 1606 if (Changed) 1607 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1608 1609 // INLINE asm returns a chain and flag, make sure to add both to the map. 1610 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1611 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1612 return Result.getValue(Op.ResNo); 1613 } 1614 case ISD::BR: 1615 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1616 // Ensure that libcalls are emitted before a branch. 1617 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1618 Tmp1 = LegalizeOp(Tmp1); 1619 LastCALLSEQ_END = DAG.getEntryNode(); 1620 1621 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1622 break; 1623 case ISD::BRIND: 1624 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1625 // Ensure that libcalls are emitted before a branch. 1626 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1627 Tmp1 = LegalizeOp(Tmp1); 1628 LastCALLSEQ_END = DAG.getEntryNode(); 1629 1630 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1631 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1632 case Legal: 1633 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1634 break; 1635 } 1636 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1637 break; 1638 case ISD::BR_JT: 1639 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1640 // Ensure that libcalls are emitted before a branch. 1641 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1642 Tmp1 = LegalizeOp(Tmp1); 1643 LastCALLSEQ_END = DAG.getEntryNode(); 1644 1645 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1646 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1647 1648 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1649 default: assert(0 && "This action is not supported yet!"); 1650 case TargetLowering::Legal: break; 1651 case TargetLowering::Custom: 1652 Tmp1 = TLI.LowerOperation(Result, DAG); 1653 if (Tmp1.Val) Result = Tmp1; 1654 break; 1655 case TargetLowering::Expand: { 1656 SDOperand Chain = Result.getOperand(0); 1657 SDOperand Table = Result.getOperand(1); 1658 SDOperand Index = Result.getOperand(2); 1659 1660 MVT::ValueType PTy = TLI.getPointerTy(); 1661 MachineFunction &MF = DAG.getMachineFunction(); 1662 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1663 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1664 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1665 1666 SDOperand LD; 1667 switch (EntrySize) { 1668 default: assert(0 && "Size of jump table not supported yet."); break; 1669 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break; 1670 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break; 1671 } 1672 1673 Addr = LD; 1674 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1675 // For PIC, the sequence is: 1676 // BRIND(load(Jumptable + index) + RelocBase) 1677 // RelocBase can be JumpTable, GOT or some sort of global base. 1678 if (PTy != MVT::i32) 1679 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1680 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1681 TLI.getPICJumpTableRelocBase(Table, DAG)); 1682 } 1683 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1684 } 1685 } 1686 break; 1687 case ISD::BRCOND: 1688 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1689 // Ensure that libcalls are emitted before a return. 1690 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1691 Tmp1 = LegalizeOp(Tmp1); 1692 LastCALLSEQ_END = DAG.getEntryNode(); 1693 1694 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1695 case Expand: assert(0 && "It's impossible to expand bools"); 1696 case Legal: 1697 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1698 break; 1699 case Promote: 1700 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1701 1702 // The top bits of the promoted condition are not necessarily zero, ensure 1703 // that the value is properly zero extended. 1704 if (!DAG.MaskedValueIsZero(Tmp2, 1705 MVT::getIntVTBitMask(Tmp2.getValueType())^1)) 1706 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1707 break; 1708 } 1709 1710 // Basic block destination (Op#2) is always legal. 1711 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1712 1713 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1714 default: assert(0 && "This action is not supported yet!"); 1715 case TargetLowering::Legal: break; 1716 case TargetLowering::Custom: 1717 Tmp1 = TLI.LowerOperation(Result, DAG); 1718 if (Tmp1.Val) Result = Tmp1; 1719 break; 1720 case TargetLowering::Expand: 1721 // Expand brcond's setcc into its constituent parts and create a BR_CC 1722 // Node. 1723 if (Tmp2.getOpcode() == ISD::SETCC) { 1724 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1725 Tmp2.getOperand(0), Tmp2.getOperand(1), 1726 Node->getOperand(2)); 1727 } else { 1728 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1729 DAG.getCondCode(ISD::SETNE), Tmp2, 1730 DAG.getConstant(0, Tmp2.getValueType()), 1731 Node->getOperand(2)); 1732 } 1733 break; 1734 } 1735 break; 1736 case ISD::BR_CC: 1737 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1738 // Ensure that libcalls are emitted before a branch. 1739 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1740 Tmp1 = LegalizeOp(Tmp1); 1741 Tmp2 = Node->getOperand(2); // LHS 1742 Tmp3 = Node->getOperand(3); // RHS 1743 Tmp4 = Node->getOperand(1); // CC 1744 1745 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1746 LastCALLSEQ_END = DAG.getEntryNode(); 1747 1748 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1749 // the LHS is a legal SETCC itself. In this case, we need to compare 1750 // the result against zero to select between true and false values. 1751 if (Tmp3.Val == 0) { 1752 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1753 Tmp4 = DAG.getCondCode(ISD::SETNE); 1754 } 1755 1756 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1757 Node->getOperand(4)); 1758 1759 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1760 default: assert(0 && "Unexpected action for BR_CC!"); 1761 case TargetLowering::Legal: break; 1762 case TargetLowering::Custom: 1763 Tmp4 = TLI.LowerOperation(Result, DAG); 1764 if (Tmp4.Val) Result = Tmp4; 1765 break; 1766 } 1767 break; 1768 case ISD::LOAD: { 1769 LoadSDNode *LD = cast<LoadSDNode>(Node); 1770 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1771 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1772 1773 ISD::LoadExtType ExtType = LD->getExtensionType(); 1774 if (ExtType == ISD::NON_EXTLOAD) { 1775 MVT::ValueType VT = Node->getValueType(0); 1776 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1777 Tmp3 = Result.getValue(0); 1778 Tmp4 = Result.getValue(1); 1779 1780 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1781 default: assert(0 && "This action is not supported yet!"); 1782 case TargetLowering::Legal: 1783 // If this is an unaligned load and the target doesn't support it, 1784 // expand it. 1785 if (!TLI.allowsUnalignedMemoryAccesses()) { 1786 unsigned ABIAlignment = TLI.getTargetData()-> 1787 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1788 if (LD->getAlignment() < ABIAlignment){ 1789 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1790 TLI); 1791 Tmp3 = Result.getOperand(0); 1792 Tmp4 = Result.getOperand(1); 1793 Tmp3 = LegalizeOp(Tmp3); 1794 Tmp4 = LegalizeOp(Tmp4); 1795 } 1796 } 1797 break; 1798 case TargetLowering::Custom: 1799 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1800 if (Tmp1.Val) { 1801 Tmp3 = LegalizeOp(Tmp1); 1802 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1803 } 1804 break; 1805 case TargetLowering::Promote: { 1806 // Only promote a load of vector type to another. 1807 assert(MVT::isVector(VT) && "Cannot promote this load!"); 1808 // Change base type to a different vector type. 1809 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1810 1811 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1812 LD->getSrcValueOffset(), 1813 LD->isVolatile(), LD->getAlignment()); 1814 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1815 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1816 break; 1817 } 1818 } 1819 // Since loads produce two values, make sure to remember that we 1820 // legalized both of them. 1821 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1822 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1823 return Op.ResNo ? Tmp4 : Tmp3; 1824 } else { 1825 MVT::ValueType SrcVT = LD->getLoadedVT(); 1826 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 1827 default: assert(0 && "This action is not supported yet!"); 1828 case TargetLowering::Promote: 1829 assert(SrcVT == MVT::i1 && 1830 "Can only promote extending LOAD from i1 -> i8!"); 1831 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 1832 LD->getSrcValue(), LD->getSrcValueOffset(), 1833 MVT::i8, LD->isVolatile(), LD->getAlignment()); 1834 Tmp1 = Result.getValue(0); 1835 Tmp2 = Result.getValue(1); 1836 break; 1837 case TargetLowering::Custom: 1838 isCustom = true; 1839 // FALLTHROUGH 1840 case TargetLowering::Legal: 1841 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1842 Tmp1 = Result.getValue(0); 1843 Tmp2 = Result.getValue(1); 1844 1845 if (isCustom) { 1846 Tmp3 = TLI.LowerOperation(Result, DAG); 1847 if (Tmp3.Val) { 1848 Tmp1 = LegalizeOp(Tmp3); 1849 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1850 } 1851 } else { 1852 // If this is an unaligned load and the target doesn't support it, 1853 // expand it. 1854 if (!TLI.allowsUnalignedMemoryAccesses()) { 1855 unsigned ABIAlignment = TLI.getTargetData()-> 1856 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT())); 1857 if (LD->getAlignment() < ABIAlignment){ 1858 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1859 TLI); 1860 Tmp1 = Result.getOperand(0); 1861 Tmp2 = Result.getOperand(1); 1862 Tmp1 = LegalizeOp(Tmp1); 1863 Tmp2 = LegalizeOp(Tmp2); 1864 } 1865 } 1866 } 1867 break; 1868 case TargetLowering::Expand: 1869 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 1870 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 1871 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 1872 LD->getSrcValueOffset(), 1873 LD->isVolatile(), LD->getAlignment()); 1874 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 1875 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 1876 Tmp2 = LegalizeOp(Load.getValue(1)); 1877 break; 1878 } 1879 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 1880 // Turn the unsupported load into an EXTLOAD followed by an explicit 1881 // zero/sign extend inreg. 1882 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 1883 Tmp1, Tmp2, LD->getSrcValue(), 1884 LD->getSrcValueOffset(), SrcVT, 1885 LD->isVolatile(), LD->getAlignment()); 1886 SDOperand ValRes; 1887 if (ExtType == ISD::SEXTLOAD) 1888 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 1889 Result, DAG.getValueType(SrcVT)); 1890 else 1891 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 1892 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 1893 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 1894 break; 1895 } 1896 // Since loads produce two values, make sure to remember that we legalized 1897 // both of them. 1898 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1899 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1900 return Op.ResNo ? Tmp2 : Tmp1; 1901 } 1902 } 1903 case ISD::EXTRACT_ELEMENT: { 1904 MVT::ValueType OpTy = Node->getOperand(0).getValueType(); 1905 switch (getTypeAction(OpTy)) { 1906 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 1907 case Legal: 1908 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 1909 // 1 -> Hi 1910 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 1911 DAG.getConstant(MVT::getSizeInBits(OpTy)/2, 1912 TLI.getShiftAmountTy())); 1913 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 1914 } else { 1915 // 0 -> Lo 1916 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 1917 Node->getOperand(0)); 1918 } 1919 break; 1920 case Expand: 1921 // Get both the low and high parts. 1922 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 1923 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 1924 Result = Tmp2; // 1 -> Hi 1925 else 1926 Result = Tmp1; // 0 -> Lo 1927 break; 1928 } 1929 break; 1930 } 1931 1932 case ISD::CopyToReg: 1933 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1934 1935 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 1936 "Register type must be legal!"); 1937 // Legalize the incoming value (must be a legal type). 1938 Tmp2 = LegalizeOp(Node->getOperand(2)); 1939 if (Node->getNumValues() == 1) { 1940 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 1941 } else { 1942 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 1943 if (Node->getNumOperands() == 4) { 1944 Tmp3 = LegalizeOp(Node->getOperand(3)); 1945 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 1946 Tmp3); 1947 } else { 1948 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1949 } 1950 1951 // Since this produces two values, make sure to remember that we legalized 1952 // both of them. 1953 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1954 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1955 return Result; 1956 } 1957 break; 1958 1959 case ISD::RET: 1960 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1961 1962 // Ensure that libcalls are emitted before a return. 1963 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1964 Tmp1 = LegalizeOp(Tmp1); 1965 LastCALLSEQ_END = DAG.getEntryNode(); 1966 1967 switch (Node->getNumOperands()) { 1968 case 3: // ret val 1969 Tmp2 = Node->getOperand(1); 1970 Tmp3 = Node->getOperand(2); // Signness 1971 switch (getTypeAction(Tmp2.getValueType())) { 1972 case Legal: 1973 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 1974 break; 1975 case Expand: 1976 if (!MVT::isVector(Tmp2.getValueType())) { 1977 SDOperand Lo, Hi; 1978 ExpandOp(Tmp2, Lo, Hi); 1979 1980 // Big endian systems want the hi reg first. 1981 if (!TLI.isLittleEndian()) 1982 std::swap(Lo, Hi); 1983 1984 if (Hi.Val) 1985 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 1986 else 1987 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 1988 Result = LegalizeOp(Result); 1989 } else { 1990 SDNode *InVal = Tmp2.Val; 1991 int InIx = Tmp2.ResNo; 1992 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 1993 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 1994 1995 // Figure out if there is a simple type corresponding to this Vector 1996 // type. If so, convert to the vector type. 1997 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 1998 if (TLI.isTypeLegal(TVT)) { 1999 // Turn this into a return of the vector type. 2000 Tmp2 = LegalizeOp(Tmp2); 2001 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2002 } else if (NumElems == 1) { 2003 // Turn this into a return of the scalar type. 2004 Tmp2 = ScalarizeVectorOp(Tmp2); 2005 Tmp2 = LegalizeOp(Tmp2); 2006 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2007 2008 // FIXME: Returns of gcc generic vectors smaller than a legal type 2009 // should be returned in integer registers! 2010 2011 // The scalarized value type may not be legal, e.g. it might require 2012 // promotion or expansion. Relegalize the return. 2013 Result = LegalizeOp(Result); 2014 } else { 2015 // FIXME: Returns of gcc generic vectors larger than a legal vector 2016 // type should be returned by reference! 2017 SDOperand Lo, Hi; 2018 SplitVectorOp(Tmp2, Lo, Hi); 2019 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2020 Result = LegalizeOp(Result); 2021 } 2022 } 2023 break; 2024 case Promote: 2025 Tmp2 = PromoteOp(Node->getOperand(1)); 2026 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2027 Result = LegalizeOp(Result); 2028 break; 2029 } 2030 break; 2031 case 1: // ret void 2032 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2033 break; 2034 default: { // ret <values> 2035 SmallVector<SDOperand, 8> NewValues; 2036 NewValues.push_back(Tmp1); 2037 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2038 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2039 case Legal: 2040 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2041 NewValues.push_back(Node->getOperand(i+1)); 2042 break; 2043 case Expand: { 2044 SDOperand Lo, Hi; 2045 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) && 2046 "FIXME: TODO: implement returning non-legal vector types!"); 2047 ExpandOp(Node->getOperand(i), Lo, Hi); 2048 NewValues.push_back(Lo); 2049 NewValues.push_back(Node->getOperand(i+1)); 2050 if (Hi.Val) { 2051 NewValues.push_back(Hi); 2052 NewValues.push_back(Node->getOperand(i+1)); 2053 } 2054 break; 2055 } 2056 case Promote: 2057 assert(0 && "Can't promote multiple return value yet!"); 2058 } 2059 2060 if (NewValues.size() == Node->getNumOperands()) 2061 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2062 else 2063 Result = DAG.getNode(ISD::RET, MVT::Other, 2064 &NewValues[0], NewValues.size()); 2065 break; 2066 } 2067 } 2068 2069 if (Result.getOpcode() == ISD::RET) { 2070 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2071 default: assert(0 && "This action is not supported yet!"); 2072 case TargetLowering::Legal: break; 2073 case TargetLowering::Custom: 2074 Tmp1 = TLI.LowerOperation(Result, DAG); 2075 if (Tmp1.Val) Result = Tmp1; 2076 break; 2077 } 2078 } 2079 break; 2080 case ISD::STORE: { 2081 StoreSDNode *ST = cast<StoreSDNode>(Node); 2082 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2083 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2084 int SVOffset = ST->getSrcValueOffset(); 2085 unsigned Alignment = ST->getAlignment(); 2086 bool isVolatile = ST->isVolatile(); 2087 2088 if (!ST->isTruncatingStore()) { 2089 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2090 // FIXME: We shouldn't do this for TargetConstantFP's. 2091 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2092 // to phase ordering between legalized code and the dag combiner. This 2093 // probably means that we need to integrate dag combiner and legalizer 2094 // together. 2095 // We generally can't do this one for long doubles. 2096 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2097 if (CFP->getValueType(0) == MVT::f32 && 2098 getTypeAction(MVT::i32) == Legal) { 2099 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF(). 2100 convertToAPInt().getZExtValue(), 2101 MVT::i32); 2102 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2103 SVOffset, isVolatile, Alignment); 2104 break; 2105 } else if (CFP->getValueType(0) == MVT::f64) { 2106 // If this target supports 64-bit registers, do a single 64-bit store. 2107 if (getTypeAction(MVT::i64) == Legal) { 2108 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2109 getZExtValue(), MVT::i64); 2110 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2111 SVOffset, isVolatile, Alignment); 2112 break; 2113 } else if (getTypeAction(MVT::i32) == Legal) { 2114 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2115 // stores. If the target supports neither 32- nor 64-bits, this 2116 // xform is certainly not worth it. 2117 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue(); 2118 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32); 2119 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32); 2120 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 2121 2122 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2123 SVOffset, isVolatile, Alignment); 2124 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2125 getIntPtrConstant(4)); 2126 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2127 isVolatile, MinAlign(Alignment, 4U)); 2128 2129 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2130 break; 2131 } 2132 } 2133 } 2134 2135 switch (getTypeAction(ST->getStoredVT())) { 2136 case Legal: { 2137 Tmp3 = LegalizeOp(ST->getValue()); 2138 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2139 ST->getOffset()); 2140 2141 MVT::ValueType VT = Tmp3.getValueType(); 2142 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2143 default: assert(0 && "This action is not supported yet!"); 2144 case TargetLowering::Legal: 2145 // If this is an unaligned store and the target doesn't support it, 2146 // expand it. 2147 if (!TLI.allowsUnalignedMemoryAccesses()) { 2148 unsigned ABIAlignment = TLI.getTargetData()-> 2149 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2150 if (ST->getAlignment() < ABIAlignment) 2151 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2152 TLI); 2153 } 2154 break; 2155 case TargetLowering::Custom: 2156 Tmp1 = TLI.LowerOperation(Result, DAG); 2157 if (Tmp1.Val) Result = Tmp1; 2158 break; 2159 case TargetLowering::Promote: 2160 assert(MVT::isVector(VT) && "Unknown legal promote case!"); 2161 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2162 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2163 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2164 ST->getSrcValue(), SVOffset, isVolatile, 2165 Alignment); 2166 break; 2167 } 2168 break; 2169 } 2170 case Promote: 2171 // Truncate the value and store the result. 2172 Tmp3 = PromoteOp(ST->getValue()); 2173 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2174 SVOffset, ST->getStoredVT(), 2175 isVolatile, Alignment); 2176 break; 2177 2178 case Expand: 2179 unsigned IncrementSize = 0; 2180 SDOperand Lo, Hi; 2181 2182 // If this is a vector type, then we have to calculate the increment as 2183 // the product of the element size in bytes, and the number of elements 2184 // in the high half of the vector. 2185 if (MVT::isVector(ST->getValue().getValueType())) { 2186 SDNode *InVal = ST->getValue().Val; 2187 int InIx = ST->getValue().ResNo; 2188 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 2189 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 2190 2191 // Figure out if there is a simple type corresponding to this Vector 2192 // type. If so, convert to the vector type. 2193 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 2194 if (TLI.isTypeLegal(TVT)) { 2195 // Turn this into a normal store of the vector type. 2196 Tmp3 = LegalizeOp(Node->getOperand(1)); 2197 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2198 SVOffset, isVolatile, Alignment); 2199 Result = LegalizeOp(Result); 2200 break; 2201 } else if (NumElems == 1) { 2202 // Turn this into a normal store of the scalar type. 2203 Tmp3 = ScalarizeVectorOp(Node->getOperand(1)); 2204 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2205 SVOffset, isVolatile, Alignment); 2206 // The scalarized value type may not be legal, e.g. it might require 2207 // promotion or expansion. Relegalize the scalar store. 2208 Result = LegalizeOp(Result); 2209 break; 2210 } else { 2211 SplitVectorOp(Node->getOperand(1), Lo, Hi); 2212 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) * 2213 MVT::getSizeInBits(EVT)/8; 2214 } 2215 } else { 2216 ExpandOp(Node->getOperand(1), Lo, Hi); 2217 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0; 2218 2219 if (!TLI.isLittleEndian()) 2220 std::swap(Lo, Hi); 2221 } 2222 2223 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2224 SVOffset, isVolatile, Alignment); 2225 2226 if (Hi.Val == NULL) { 2227 // Must be int <-> float one-to-one expansion. 2228 Result = Lo; 2229 break; 2230 } 2231 2232 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2233 getIntPtrConstant(IncrementSize)); 2234 assert(isTypeLegal(Tmp2.getValueType()) && 2235 "Pointers must be legal!"); 2236 SVOffset += IncrementSize; 2237 Alignment = MinAlign(Alignment, IncrementSize); 2238 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2239 SVOffset, isVolatile, Alignment); 2240 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2241 break; 2242 } 2243 } else { 2244 // Truncating store 2245 assert(isTypeLegal(ST->getValue().getValueType()) && 2246 "Cannot handle illegal TRUNCSTORE yet!"); 2247 Tmp3 = LegalizeOp(ST->getValue()); 2248 2249 // The only promote case we handle is TRUNCSTORE:i1 X into 2250 // -> TRUNCSTORE:i8 (and X, 1) 2251 if (ST->getStoredVT() == MVT::i1 && 2252 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) { 2253 // Promote the bool to a mask then store. 2254 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3, 2255 DAG.getConstant(1, Tmp3.getValueType())); 2256 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2257 SVOffset, MVT::i8, 2258 isVolatile, Alignment); 2259 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2260 Tmp2 != ST->getBasePtr()) { 2261 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2262 ST->getOffset()); 2263 } 2264 2265 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT(); 2266 switch (TLI.getStoreXAction(StVT)) { 2267 default: assert(0 && "This action is not supported yet!"); 2268 case TargetLowering::Legal: 2269 // If this is an unaligned store and the target doesn't support it, 2270 // expand it. 2271 if (!TLI.allowsUnalignedMemoryAccesses()) { 2272 unsigned ABIAlignment = TLI.getTargetData()-> 2273 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT())); 2274 if (ST->getAlignment() < ABIAlignment) 2275 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2276 TLI); 2277 } 2278 break; 2279 case TargetLowering::Custom: 2280 Tmp1 = TLI.LowerOperation(Result, DAG); 2281 if (Tmp1.Val) Result = Tmp1; 2282 break; 2283 } 2284 } 2285 break; 2286 } 2287 case ISD::PCMARKER: 2288 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2289 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2290 break; 2291 case ISD::STACKSAVE: 2292 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2293 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2294 Tmp1 = Result.getValue(0); 2295 Tmp2 = Result.getValue(1); 2296 2297 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2298 default: assert(0 && "This action is not supported yet!"); 2299 case TargetLowering::Legal: break; 2300 case TargetLowering::Custom: 2301 Tmp3 = TLI.LowerOperation(Result, DAG); 2302 if (Tmp3.Val) { 2303 Tmp1 = LegalizeOp(Tmp3); 2304 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2305 } 2306 break; 2307 case TargetLowering::Expand: 2308 // Expand to CopyFromReg if the target set 2309 // StackPointerRegisterToSaveRestore. 2310 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2311 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2312 Node->getValueType(0)); 2313 Tmp2 = Tmp1.getValue(1); 2314 } else { 2315 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2316 Tmp2 = Node->getOperand(0); 2317 } 2318 break; 2319 } 2320 2321 // Since stacksave produce two values, make sure to remember that we 2322 // legalized both of them. 2323 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2324 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2325 return Op.ResNo ? Tmp2 : Tmp1; 2326 2327 case ISD::STACKRESTORE: 2328 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2329 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2330 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2331 2332 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2333 default: assert(0 && "This action is not supported yet!"); 2334 case TargetLowering::Legal: break; 2335 case TargetLowering::Custom: 2336 Tmp1 = TLI.LowerOperation(Result, DAG); 2337 if (Tmp1.Val) Result = Tmp1; 2338 break; 2339 case TargetLowering::Expand: 2340 // Expand to CopyToReg if the target set 2341 // StackPointerRegisterToSaveRestore. 2342 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2343 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2344 } else { 2345 Result = Tmp1; 2346 } 2347 break; 2348 } 2349 break; 2350 2351 case ISD::READCYCLECOUNTER: 2352 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2353 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2354 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2355 Node->getValueType(0))) { 2356 default: assert(0 && "This action is not supported yet!"); 2357 case TargetLowering::Legal: 2358 Tmp1 = Result.getValue(0); 2359 Tmp2 = Result.getValue(1); 2360 break; 2361 case TargetLowering::Custom: 2362 Result = TLI.LowerOperation(Result, DAG); 2363 Tmp1 = LegalizeOp(Result.getValue(0)); 2364 Tmp2 = LegalizeOp(Result.getValue(1)); 2365 break; 2366 } 2367 2368 // Since rdcc produce two values, make sure to remember that we legalized 2369 // both of them. 2370 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2371 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2372 return Result; 2373 2374 case ISD::SELECT: 2375 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2376 case Expand: assert(0 && "It's impossible to expand bools"); 2377 case Legal: 2378 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2379 break; 2380 case Promote: 2381 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2382 // Make sure the condition is either zero or one. 2383 if (!DAG.MaskedValueIsZero(Tmp1, 2384 MVT::getIntVTBitMask(Tmp1.getValueType())^1)) 2385 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2386 break; 2387 } 2388 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2389 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2390 2391 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2392 2393 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2394 default: assert(0 && "This action is not supported yet!"); 2395 case TargetLowering::Legal: break; 2396 case TargetLowering::Custom: { 2397 Tmp1 = TLI.LowerOperation(Result, DAG); 2398 if (Tmp1.Val) Result = Tmp1; 2399 break; 2400 } 2401 case TargetLowering::Expand: 2402 if (Tmp1.getOpcode() == ISD::SETCC) { 2403 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2404 Tmp2, Tmp3, 2405 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2406 } else { 2407 Result = DAG.getSelectCC(Tmp1, 2408 DAG.getConstant(0, Tmp1.getValueType()), 2409 Tmp2, Tmp3, ISD::SETNE); 2410 } 2411 break; 2412 case TargetLowering::Promote: { 2413 MVT::ValueType NVT = 2414 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2415 unsigned ExtOp, TruncOp; 2416 if (MVT::isVector(Tmp2.getValueType())) { 2417 ExtOp = ISD::BIT_CONVERT; 2418 TruncOp = ISD::BIT_CONVERT; 2419 } else if (MVT::isInteger(Tmp2.getValueType())) { 2420 ExtOp = ISD::ANY_EXTEND; 2421 TruncOp = ISD::TRUNCATE; 2422 } else { 2423 ExtOp = ISD::FP_EXTEND; 2424 TruncOp = ISD::FP_ROUND; 2425 } 2426 // Promote each of the values to the new type. 2427 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2428 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2429 // Perform the larger operation, then round down. 2430 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2431 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2432 break; 2433 } 2434 } 2435 break; 2436 case ISD::SELECT_CC: { 2437 Tmp1 = Node->getOperand(0); // LHS 2438 Tmp2 = Node->getOperand(1); // RHS 2439 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2440 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2441 SDOperand CC = Node->getOperand(4); 2442 2443 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2444 2445 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2446 // the LHS is a legal SETCC itself. In this case, we need to compare 2447 // the result against zero to select between true and false values. 2448 if (Tmp2.Val == 0) { 2449 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2450 CC = DAG.getCondCode(ISD::SETNE); 2451 } 2452 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2453 2454 // Everything is legal, see if we should expand this op or something. 2455 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2456 default: assert(0 && "This action is not supported yet!"); 2457 case TargetLowering::Legal: break; 2458 case TargetLowering::Custom: 2459 Tmp1 = TLI.LowerOperation(Result, DAG); 2460 if (Tmp1.Val) Result = Tmp1; 2461 break; 2462 } 2463 break; 2464 } 2465 case ISD::SETCC: 2466 Tmp1 = Node->getOperand(0); 2467 Tmp2 = Node->getOperand(1); 2468 Tmp3 = Node->getOperand(2); 2469 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2470 2471 // If we had to Expand the SetCC operands into a SELECT node, then it may 2472 // not always be possible to return a true LHS & RHS. In this case, just 2473 // return the value we legalized, returned in the LHS 2474 if (Tmp2.Val == 0) { 2475 Result = Tmp1; 2476 break; 2477 } 2478 2479 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2480 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2481 case TargetLowering::Custom: 2482 isCustom = true; 2483 // FALLTHROUGH. 2484 case TargetLowering::Legal: 2485 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2486 if (isCustom) { 2487 Tmp4 = TLI.LowerOperation(Result, DAG); 2488 if (Tmp4.Val) Result = Tmp4; 2489 } 2490 break; 2491 case TargetLowering::Promote: { 2492 // First step, figure out the appropriate operation to use. 2493 // Allow SETCC to not be supported for all legal data types 2494 // Mostly this targets FP 2495 MVT::ValueType NewInTy = Node->getOperand(0).getValueType(); 2496 MVT::ValueType OldVT = NewInTy; OldVT = OldVT; 2497 2498 // Scan for the appropriate larger type to use. 2499 while (1) { 2500 NewInTy = (MVT::ValueType)(NewInTy+1); 2501 2502 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) && 2503 "Fell off of the edge of the integer world"); 2504 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) && 2505 "Fell off of the edge of the floating point world"); 2506 2507 // If the target supports SETCC of this type, use it. 2508 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2509 break; 2510 } 2511 if (MVT::isInteger(NewInTy)) 2512 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2513 else { 2514 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2515 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2516 } 2517 Tmp1 = LegalizeOp(Tmp1); 2518 Tmp2 = LegalizeOp(Tmp2); 2519 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2520 Result = LegalizeOp(Result); 2521 break; 2522 } 2523 case TargetLowering::Expand: 2524 // Expand a setcc node into a select_cc of the same condition, lhs, and 2525 // rhs that selects between const 1 (true) and const 0 (false). 2526 MVT::ValueType VT = Node->getValueType(0); 2527 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2528 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2529 Tmp3); 2530 break; 2531 } 2532 break; 2533 case ISD::MEMSET: 2534 case ISD::MEMCPY: 2535 case ISD::MEMMOVE: { 2536 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain 2537 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer 2538 2539 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte 2540 switch (getTypeAction(Node->getOperand(2).getValueType())) { 2541 case Expand: assert(0 && "Cannot expand a byte!"); 2542 case Legal: 2543 Tmp3 = LegalizeOp(Node->getOperand(2)); 2544 break; 2545 case Promote: 2546 Tmp3 = PromoteOp(Node->getOperand(2)); 2547 break; 2548 } 2549 } else { 2550 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer, 2551 } 2552 2553 SDOperand Tmp4; 2554 switch (getTypeAction(Node->getOperand(3).getValueType())) { 2555 case Expand: { 2556 // Length is too big, just take the lo-part of the length. 2557 SDOperand HiPart; 2558 ExpandOp(Node->getOperand(3), Tmp4, HiPart); 2559 break; 2560 } 2561 case Legal: 2562 Tmp4 = LegalizeOp(Node->getOperand(3)); 2563 break; 2564 case Promote: 2565 Tmp4 = PromoteOp(Node->getOperand(3)); 2566 break; 2567 } 2568 2569 SDOperand Tmp5; 2570 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint 2571 case Expand: assert(0 && "Cannot expand this yet!"); 2572 case Legal: 2573 Tmp5 = LegalizeOp(Node->getOperand(4)); 2574 break; 2575 case Promote: 2576 Tmp5 = PromoteOp(Node->getOperand(4)); 2577 break; 2578 } 2579 2580 SDOperand Tmp6; 2581 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool 2582 case Expand: assert(0 && "Cannot expand this yet!"); 2583 case Legal: 2584 Tmp6 = LegalizeOp(Node->getOperand(5)); 2585 break; 2586 case Promote: 2587 Tmp6 = PromoteOp(Node->getOperand(5)); 2588 break; 2589 } 2590 2591 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 2592 default: assert(0 && "This action not implemented for this operation!"); 2593 case TargetLowering::Custom: 2594 isCustom = true; 2595 // FALLTHROUGH 2596 case TargetLowering::Legal: { 2597 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 }; 2598 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 2599 if (isCustom) { 2600 Tmp1 = TLI.LowerOperation(Result, DAG); 2601 if (Tmp1.Val) Result = Tmp1; 2602 } 2603 break; 2604 } 2605 case TargetLowering::Expand: { 2606 // Otherwise, the target does not support this operation. Lower the 2607 // operation to an explicit libcall as appropriate. 2608 MVT::ValueType IntPtr = TLI.getPointerTy(); 2609 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType(); 2610 TargetLowering::ArgListTy Args; 2611 TargetLowering::ArgListEntry Entry; 2612 2613 const char *FnName = 0; 2614 if (Node->getOpcode() == ISD::MEMSET) { 2615 Entry.Node = Tmp2; Entry.Ty = IntPtrTy; 2616 Args.push_back(Entry); 2617 // Extend the (previously legalized) ubyte argument to be an int value 2618 // for the call. 2619 if (Tmp3.getValueType() > MVT::i32) 2620 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3); 2621 else 2622 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3); 2623 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; 2624 Args.push_back(Entry); 2625 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false; 2626 Args.push_back(Entry); 2627 2628 FnName = "memset"; 2629 } else if (Node->getOpcode() == ISD::MEMCPY || 2630 Node->getOpcode() == ISD::MEMMOVE) { 2631 Entry.Ty = IntPtrTy; 2632 Entry.Node = Tmp2; Args.push_back(Entry); 2633 Entry.Node = Tmp3; Args.push_back(Entry); 2634 Entry.Node = Tmp4; Args.push_back(Entry); 2635 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy"; 2636 } else { 2637 assert(0 && "Unknown op!"); 2638 } 2639 2640 std::pair<SDOperand,SDOperand> CallResult = 2641 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 2642 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG); 2643 Result = CallResult.second; 2644 break; 2645 } 2646 } 2647 break; 2648 } 2649 2650 case ISD::SHL_PARTS: 2651 case ISD::SRA_PARTS: 2652 case ISD::SRL_PARTS: { 2653 SmallVector<SDOperand, 8> Ops; 2654 bool Changed = false; 2655 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2656 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2657 Changed |= Ops.back() != Node->getOperand(i); 2658 } 2659 if (Changed) 2660 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2661 2662 switch (TLI.getOperationAction(Node->getOpcode(), 2663 Node->getValueType(0))) { 2664 default: assert(0 && "This action is not supported yet!"); 2665 case TargetLowering::Legal: break; 2666 case TargetLowering::Custom: 2667 Tmp1 = TLI.LowerOperation(Result, DAG); 2668 if (Tmp1.Val) { 2669 SDOperand Tmp2, RetVal(0, 0); 2670 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2671 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2672 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2673 if (i == Op.ResNo) 2674 RetVal = Tmp2; 2675 } 2676 assert(RetVal.Val && "Illegal result number"); 2677 return RetVal; 2678 } 2679 break; 2680 } 2681 2682 // Since these produce multiple values, make sure to remember that we 2683 // legalized all of them. 2684 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2685 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2686 return Result.getValue(Op.ResNo); 2687 } 2688 2689 // Binary operators 2690 case ISD::ADD: 2691 case ISD::SUB: 2692 case ISD::MUL: 2693 case ISD::MULHS: 2694 case ISD::MULHU: 2695 case ISD::UDIV: 2696 case ISD::SDIV: 2697 case ISD::AND: 2698 case ISD::OR: 2699 case ISD::XOR: 2700 case ISD::SHL: 2701 case ISD::SRL: 2702 case ISD::SRA: 2703 case ISD::FADD: 2704 case ISD::FSUB: 2705 case ISD::FMUL: 2706 case ISD::FDIV: 2707 case ISD::FPOW: 2708 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2709 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2710 case Expand: assert(0 && "Not possible"); 2711 case Legal: 2712 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2713 break; 2714 case Promote: 2715 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2716 break; 2717 } 2718 2719 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2720 2721 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2722 default: assert(0 && "BinOp legalize operation not supported"); 2723 case TargetLowering::Legal: break; 2724 case TargetLowering::Custom: 2725 Tmp1 = TLI.LowerOperation(Result, DAG); 2726 if (Tmp1.Val) Result = Tmp1; 2727 break; 2728 case TargetLowering::Expand: { 2729 MVT::ValueType VT = Op.getValueType(); 2730 2731 // See if multiply or divide can be lowered using two-result operations. 2732 SDVTList VTs = DAG.getVTList(VT, VT); 2733 if (Node->getOpcode() == ISD::MUL) { 2734 // We just need the low half of the multiply; try both the signed 2735 // and unsigned forms. If the target supports both SMUL_LOHI and 2736 // UMUL_LOHI, form a preference by checking which forms of plain 2737 // MULH it supports. 2738 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2739 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2740 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2741 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2742 unsigned OpToUse = 0; 2743 if (HasSMUL_LOHI && !HasMULHS) { 2744 OpToUse = ISD::SMUL_LOHI; 2745 } else if (HasUMUL_LOHI && !HasMULHU) { 2746 OpToUse = ISD::UMUL_LOHI; 2747 } else if (HasSMUL_LOHI) { 2748 OpToUse = ISD::SMUL_LOHI; 2749 } else if (HasUMUL_LOHI) { 2750 OpToUse = ISD::UMUL_LOHI; 2751 } 2752 if (OpToUse) { 2753 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 2754 break; 2755 } 2756 } 2757 if (Node->getOpcode() == ISD::MULHS && 2758 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 2759 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2760 break; 2761 } 2762 if (Node->getOpcode() == ISD::MULHU && 2763 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 2764 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 2765 break; 2766 } 2767 if (Node->getOpcode() == ISD::SDIV && 2768 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 2769 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 2770 break; 2771 } 2772 if (Node->getOpcode() == ISD::UDIV && 2773 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 2774 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 2775 break; 2776 } 2777 2778 // Check to see if we have a libcall for this operator. 2779 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2780 bool isSigned = false; 2781 switch (Node->getOpcode()) { 2782 case ISD::UDIV: 2783 case ISD::SDIV: 2784 if (VT == MVT::i32) { 2785 LC = Node->getOpcode() == ISD::UDIV 2786 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 2787 isSigned = Node->getOpcode() == ISD::SDIV; 2788 } 2789 break; 2790 case ISD::FPOW: 2791 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 2792 RTLIB::POW_PPCF128); 2793 break; 2794 default: break; 2795 } 2796 if (LC != RTLIB::UNKNOWN_LIBCALL) { 2797 SDOperand Dummy; 2798 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 2799 break; 2800 } 2801 2802 assert(MVT::isVector(Node->getValueType(0)) && 2803 "Cannot expand this binary operator!"); 2804 // Expand the operation into a bunch of nasty scalar code. 2805 Result = LegalizeOp(UnrollVectorOp(Op)); 2806 break; 2807 } 2808 case TargetLowering::Promote: { 2809 switch (Node->getOpcode()) { 2810 default: assert(0 && "Do not know how to promote this BinOp!"); 2811 case ISD::AND: 2812 case ISD::OR: 2813 case ISD::XOR: { 2814 MVT::ValueType OVT = Node->getValueType(0); 2815 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 2816 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!"); 2817 // Bit convert each of the values to the new type. 2818 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 2819 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 2820 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 2821 // Bit convert the result back the original type. 2822 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 2823 break; 2824 } 2825 } 2826 } 2827 } 2828 break; 2829 2830 case ISD::SMUL_LOHI: 2831 case ISD::UMUL_LOHI: 2832 case ISD::SDIVREM: 2833 case ISD::UDIVREM: 2834 // These nodes will only be produced by target-specific lowering, so 2835 // they shouldn't be here if they aren't legal. 2836 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 2837 "This must be legal!"); 2838 2839 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2840 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2841 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2842 break; 2843 2844 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 2845 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2846 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2847 case Expand: assert(0 && "Not possible"); 2848 case Legal: 2849 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2850 break; 2851 case Promote: 2852 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2853 break; 2854 } 2855 2856 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2857 2858 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2859 default: assert(0 && "Operation not supported"); 2860 case TargetLowering::Custom: 2861 Tmp1 = TLI.LowerOperation(Result, DAG); 2862 if (Tmp1.Val) Result = Tmp1; 2863 break; 2864 case TargetLowering::Legal: break; 2865 case TargetLowering::Expand: { 2866 // If this target supports fabs/fneg natively and select is cheap, 2867 // do this efficiently. 2868 if (!TLI.isSelectExpensive() && 2869 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 2870 TargetLowering::Legal && 2871 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 2872 TargetLowering::Legal) { 2873 // Get the sign bit of the RHS. 2874 MVT::ValueType IVT = 2875 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 2876 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 2877 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(), 2878 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 2879 // Get the absolute value of the result. 2880 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 2881 // Select between the nabs and abs value based on the sign bit of 2882 // the input. 2883 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 2884 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 2885 AbsVal), 2886 AbsVal); 2887 Result = LegalizeOp(Result); 2888 break; 2889 } 2890 2891 // Otherwise, do bitwise ops! 2892 MVT::ValueType NVT = 2893 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 2894 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 2895 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 2896 Result = LegalizeOp(Result); 2897 break; 2898 } 2899 } 2900 break; 2901 2902 case ISD::ADDC: 2903 case ISD::SUBC: 2904 Tmp1 = LegalizeOp(Node->getOperand(0)); 2905 Tmp2 = LegalizeOp(Node->getOperand(1)); 2906 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2907 // Since this produces two values, make sure to remember that we legalized 2908 // both of them. 2909 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2910 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2911 return Result; 2912 2913 case ISD::ADDE: 2914 case ISD::SUBE: 2915 Tmp1 = LegalizeOp(Node->getOperand(0)); 2916 Tmp2 = LegalizeOp(Node->getOperand(1)); 2917 Tmp3 = LegalizeOp(Node->getOperand(2)); 2918 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2919 // Since this produces two values, make sure to remember that we legalized 2920 // both of them. 2921 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2922 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2923 return Result; 2924 2925 case ISD::BUILD_PAIR: { 2926 MVT::ValueType PairTy = Node->getValueType(0); 2927 // TODO: handle the case where the Lo and Hi operands are not of legal type 2928 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 2929 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 2930 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 2931 case TargetLowering::Promote: 2932 case TargetLowering::Custom: 2933 assert(0 && "Cannot promote/custom this yet!"); 2934 case TargetLowering::Legal: 2935 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 2936 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 2937 break; 2938 case TargetLowering::Expand: 2939 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 2940 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 2941 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 2942 DAG.getConstant(MVT::getSizeInBits(PairTy)/2, 2943 TLI.getShiftAmountTy())); 2944 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 2945 break; 2946 } 2947 break; 2948 } 2949 2950 case ISD::UREM: 2951 case ISD::SREM: 2952 case ISD::FREM: 2953 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2954 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2955 2956 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2957 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 2958 case TargetLowering::Custom: 2959 isCustom = true; 2960 // FALLTHROUGH 2961 case TargetLowering::Legal: 2962 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2963 if (isCustom) { 2964 Tmp1 = TLI.LowerOperation(Result, DAG); 2965 if (Tmp1.Val) Result = Tmp1; 2966 } 2967 break; 2968 case TargetLowering::Expand: { 2969 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 2970 bool isSigned = DivOpc == ISD::SDIV; 2971 MVT::ValueType VT = Node->getValueType(0); 2972 2973 // See if remainder can be lowered using two-result operations. 2974 SDVTList VTs = DAG.getVTList(VT, VT); 2975 if (Node->getOpcode() == ISD::SREM && 2976 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 2977 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 2978 break; 2979 } 2980 if (Node->getOpcode() == ISD::UREM && 2981 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 2982 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 2983 break; 2984 } 2985 2986 if (MVT::isInteger(VT)) { 2987 if (TLI.getOperationAction(DivOpc, VT) == 2988 TargetLowering::Legal) { 2989 // X % Y -> X-X/Y*Y 2990 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 2991 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 2992 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 2993 } else if (MVT::isVector(VT)) { 2994 Result = LegalizeOp(UnrollVectorOp(Op)); 2995 } else { 2996 assert(VT == MVT::i32 && 2997 "Cannot expand this binary operator!"); 2998 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 2999 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3000 SDOperand Dummy; 3001 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy); 3002 } 3003 } else { 3004 assert(MVT::isFloatingPoint(VT) && 3005 "remainder op must have integer or floating-point type"); 3006 if (MVT::isVector(VT)) { 3007 Result = LegalizeOp(UnrollVectorOp(Op)); 3008 } else { 3009 // Floating point mod -> fmod libcall. 3010 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3011 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3012 SDOperand Dummy; 3013 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3014 false/*sign irrelevant*/, Dummy); 3015 } 3016 } 3017 break; 3018 } 3019 } 3020 break; 3021 case ISD::VAARG: { 3022 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3023 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3024 3025 MVT::ValueType VT = Node->getValueType(0); 3026 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3027 default: assert(0 && "This action is not supported yet!"); 3028 case TargetLowering::Custom: 3029 isCustom = true; 3030 // FALLTHROUGH 3031 case TargetLowering::Legal: 3032 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3033 Result = Result.getValue(0); 3034 Tmp1 = Result.getValue(1); 3035 3036 if (isCustom) { 3037 Tmp2 = TLI.LowerOperation(Result, DAG); 3038 if (Tmp2.Val) { 3039 Result = LegalizeOp(Tmp2); 3040 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3041 } 3042 } 3043 break; 3044 case TargetLowering::Expand: { 3045 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 3046 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 3047 SV->getValue(), SV->getOffset()); 3048 // Increment the pointer, VAList, to the next vaarg 3049 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3050 DAG.getConstant(MVT::getSizeInBits(VT)/8, 3051 TLI.getPointerTy())); 3052 // Store the incremented VAList to the legalized pointer 3053 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 3054 SV->getOffset()); 3055 // Load the actual argument out of the pointer VAList 3056 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3057 Tmp1 = LegalizeOp(Result.getValue(1)); 3058 Result = LegalizeOp(Result); 3059 break; 3060 } 3061 } 3062 // Since VAARG produces two values, make sure to remember that we 3063 // legalized both of them. 3064 AddLegalizedOperand(SDOperand(Node, 0), Result); 3065 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3066 return Op.ResNo ? Tmp1 : Result; 3067 } 3068 3069 case ISD::VACOPY: 3070 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3071 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3072 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3073 3074 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3075 default: assert(0 && "This action is not supported yet!"); 3076 case TargetLowering::Custom: 3077 isCustom = true; 3078 // FALLTHROUGH 3079 case TargetLowering::Legal: 3080 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3081 Node->getOperand(3), Node->getOperand(4)); 3082 if (isCustom) { 3083 Tmp1 = TLI.LowerOperation(Result, DAG); 3084 if (Tmp1.Val) Result = Tmp1; 3085 } 3086 break; 3087 case TargetLowering::Expand: 3088 // This defaults to loading a pointer from the input and storing it to the 3089 // output, returning the chain. 3090 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3)); 3091 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4)); 3092 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(), 3093 SVD->getOffset()); 3094 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(), 3095 SVS->getOffset()); 3096 break; 3097 } 3098 break; 3099 3100 case ISD::VAEND: 3101 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3102 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3103 3104 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3105 default: assert(0 && "This action is not supported yet!"); 3106 case TargetLowering::Custom: 3107 isCustom = true; 3108 // FALLTHROUGH 3109 case TargetLowering::Legal: 3110 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3111 if (isCustom) { 3112 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3113 if (Tmp1.Val) Result = Tmp1; 3114 } 3115 break; 3116 case TargetLowering::Expand: 3117 Result = Tmp1; // Default to a no-op, return the chain 3118 break; 3119 } 3120 break; 3121 3122 case ISD::VASTART: 3123 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3124 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3125 3126 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3127 3128 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3129 default: assert(0 && "This action is not supported yet!"); 3130 case TargetLowering::Legal: break; 3131 case TargetLowering::Custom: 3132 Tmp1 = TLI.LowerOperation(Result, DAG); 3133 if (Tmp1.Val) Result = Tmp1; 3134 break; 3135 } 3136 break; 3137 3138 case ISD::ROTL: 3139 case ISD::ROTR: 3140 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3141 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3142 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3143 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3144 default: 3145 assert(0 && "ROTL/ROTR legalize operation not supported"); 3146 break; 3147 case TargetLowering::Legal: 3148 break; 3149 case TargetLowering::Custom: 3150 Tmp1 = TLI.LowerOperation(Result, DAG); 3151 if (Tmp1.Val) Result = Tmp1; 3152 break; 3153 case TargetLowering::Promote: 3154 assert(0 && "Do not know how to promote ROTL/ROTR"); 3155 break; 3156 case TargetLowering::Expand: 3157 assert(0 && "Do not know how to expand ROTL/ROTR"); 3158 break; 3159 } 3160 break; 3161 3162 case ISD::BSWAP: 3163 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3164 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3165 case TargetLowering::Custom: 3166 assert(0 && "Cannot custom legalize this yet!"); 3167 case TargetLowering::Legal: 3168 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3169 break; 3170 case TargetLowering::Promote: { 3171 MVT::ValueType OVT = Tmp1.getValueType(); 3172 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3173 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT); 3174 3175 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3176 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3177 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3178 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3179 break; 3180 } 3181 case TargetLowering::Expand: 3182 Result = ExpandBSWAP(Tmp1); 3183 break; 3184 } 3185 break; 3186 3187 case ISD::CTPOP: 3188 case ISD::CTTZ: 3189 case ISD::CTLZ: 3190 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3191 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3192 case TargetLowering::Custom: 3193 case TargetLowering::Legal: 3194 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3195 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3196 TargetLowering::Custom) { 3197 Tmp1 = TLI.LowerOperation(Result, DAG); 3198 if (Tmp1.Val) { 3199 Result = Tmp1; 3200 } 3201 } 3202 break; 3203 case TargetLowering::Promote: { 3204 MVT::ValueType OVT = Tmp1.getValueType(); 3205 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3206 3207 // Zero extend the argument. 3208 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3209 // Perform the larger operation, then subtract if needed. 3210 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3211 switch (Node->getOpcode()) { 3212 case ISD::CTPOP: 3213 Result = Tmp1; 3214 break; 3215 case ISD::CTTZ: 3216 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3217 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 3218 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 3219 ISD::SETEQ); 3220 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3221 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1); 3222 break; 3223 case ISD::CTLZ: 3224 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3225 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3226 DAG.getConstant(MVT::getSizeInBits(NVT) - 3227 MVT::getSizeInBits(OVT), NVT)); 3228 break; 3229 } 3230 break; 3231 } 3232 case TargetLowering::Expand: 3233 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3234 break; 3235 } 3236 break; 3237 3238 // Unary operators 3239 case ISD::FABS: 3240 case ISD::FNEG: 3241 case ISD::FSQRT: 3242 case ISD::FSIN: 3243 case ISD::FCOS: 3244 Tmp1 = LegalizeOp(Node->getOperand(0)); 3245 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3246 case TargetLowering::Promote: 3247 case TargetLowering::Custom: 3248 isCustom = true; 3249 // FALLTHROUGH 3250 case TargetLowering::Legal: 3251 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3252 if (isCustom) { 3253 Tmp1 = TLI.LowerOperation(Result, DAG); 3254 if (Tmp1.Val) Result = Tmp1; 3255 } 3256 break; 3257 case TargetLowering::Expand: 3258 switch (Node->getOpcode()) { 3259 default: assert(0 && "Unreachable!"); 3260 case ISD::FNEG: 3261 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3262 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3263 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3264 break; 3265 case ISD::FABS: { 3266 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3267 MVT::ValueType VT = Node->getValueType(0); 3268 Tmp2 = DAG.getConstantFP(0.0, VT); 3269 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT); 3270 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3271 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3272 break; 3273 } 3274 case ISD::FSQRT: 3275 case ISD::FSIN: 3276 case ISD::FCOS: { 3277 MVT::ValueType VT = Node->getValueType(0); 3278 3279 // Expand unsupported unary vector operators by unrolling them. 3280 if (MVT::isVector(VT)) { 3281 Result = LegalizeOp(UnrollVectorOp(Op)); 3282 break; 3283 } 3284 3285 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3286 switch(Node->getOpcode()) { 3287 case ISD::FSQRT: 3288 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3289 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3290 break; 3291 case ISD::FSIN: 3292 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3293 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3294 break; 3295 case ISD::FCOS: 3296 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3297 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3298 break; 3299 default: assert(0 && "Unreachable!"); 3300 } 3301 SDOperand Dummy; 3302 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3303 false/*sign irrelevant*/, Dummy); 3304 break; 3305 } 3306 } 3307 break; 3308 } 3309 break; 3310 case ISD::FPOWI: { 3311 MVT::ValueType VT = Node->getValueType(0); 3312 3313 // Expand unsupported unary vector operators by unrolling them. 3314 if (MVT::isVector(VT)) { 3315 Result = LegalizeOp(UnrollVectorOp(Op)); 3316 break; 3317 } 3318 3319 // We always lower FPOWI into a libcall. No target support for it yet. 3320 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3321 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3322 SDOperand Dummy; 3323 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3324 false/*sign irrelevant*/, Dummy); 3325 break; 3326 } 3327 case ISD::BIT_CONVERT: 3328 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3329 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3330 } else if (MVT::isVector(Op.getOperand(0).getValueType())) { 3331 // The input has to be a vector type, we have to either scalarize it, pack 3332 // it, or convert it based on whether the input vector type is legal. 3333 SDNode *InVal = Node->getOperand(0).Val; 3334 int InIx = Node->getOperand(0).ResNo; 3335 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx)); 3336 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx)); 3337 3338 // Figure out if there is a simple type corresponding to this Vector 3339 // type. If so, convert to the vector type. 3340 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems); 3341 if (TLI.isTypeLegal(TVT)) { 3342 // Turn this into a bit convert of the vector input. 3343 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3344 LegalizeOp(Node->getOperand(0))); 3345 break; 3346 } else if (NumElems == 1) { 3347 // Turn this into a bit convert of the scalar input. 3348 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3349 ScalarizeVectorOp(Node->getOperand(0))); 3350 break; 3351 } else { 3352 // FIXME: UNIMP! Store then reload 3353 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3354 } 3355 } else { 3356 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3357 Node->getOperand(0).getValueType())) { 3358 default: assert(0 && "Unknown operation action!"); 3359 case TargetLowering::Expand: 3360 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3361 break; 3362 case TargetLowering::Legal: 3363 Tmp1 = LegalizeOp(Node->getOperand(0)); 3364 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3365 break; 3366 } 3367 } 3368 break; 3369 3370 // Conversion operators. The source and destination have different types. 3371 case ISD::SINT_TO_FP: 3372 case ISD::UINT_TO_FP: { 3373 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3374 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3375 case Legal: 3376 switch (TLI.getOperationAction(Node->getOpcode(), 3377 Node->getOperand(0).getValueType())) { 3378 default: assert(0 && "Unknown operation action!"); 3379 case TargetLowering::Custom: 3380 isCustom = true; 3381 // FALLTHROUGH 3382 case TargetLowering::Legal: 3383 Tmp1 = LegalizeOp(Node->getOperand(0)); 3384 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3385 if (isCustom) { 3386 Tmp1 = TLI.LowerOperation(Result, DAG); 3387 if (Tmp1.Val) Result = Tmp1; 3388 } 3389 break; 3390 case TargetLowering::Expand: 3391 Result = ExpandLegalINT_TO_FP(isSigned, 3392 LegalizeOp(Node->getOperand(0)), 3393 Node->getValueType(0)); 3394 break; 3395 case TargetLowering::Promote: 3396 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3397 Node->getValueType(0), 3398 isSigned); 3399 break; 3400 } 3401 break; 3402 case Expand: 3403 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3404 Node->getValueType(0), Node->getOperand(0)); 3405 break; 3406 case Promote: 3407 Tmp1 = PromoteOp(Node->getOperand(0)); 3408 if (isSigned) { 3409 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3410 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3411 } else { 3412 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3413 Node->getOperand(0).getValueType()); 3414 } 3415 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3416 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3417 break; 3418 } 3419 break; 3420 } 3421 case ISD::TRUNCATE: 3422 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3423 case Legal: 3424 Tmp1 = LegalizeOp(Node->getOperand(0)); 3425 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3426 break; 3427 case Expand: 3428 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3429 3430 // Since the result is legal, we should just be able to truncate the low 3431 // part of the source. 3432 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3433 break; 3434 case Promote: 3435 Result = PromoteOp(Node->getOperand(0)); 3436 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3437 break; 3438 } 3439 break; 3440 3441 case ISD::FP_TO_SINT: 3442 case ISD::FP_TO_UINT: 3443 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3444 case Legal: 3445 Tmp1 = LegalizeOp(Node->getOperand(0)); 3446 3447 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3448 default: assert(0 && "Unknown operation action!"); 3449 case TargetLowering::Custom: 3450 isCustom = true; 3451 // FALLTHROUGH 3452 case TargetLowering::Legal: 3453 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3454 if (isCustom) { 3455 Tmp1 = TLI.LowerOperation(Result, DAG); 3456 if (Tmp1.Val) Result = Tmp1; 3457 } 3458 break; 3459 case TargetLowering::Promote: 3460 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3461 Node->getOpcode() == ISD::FP_TO_SINT); 3462 break; 3463 case TargetLowering::Expand: 3464 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3465 SDOperand True, False; 3466 MVT::ValueType VT = Node->getOperand(0).getValueType(); 3467 MVT::ValueType NVT = Node->getValueType(0); 3468 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1; 3469 const uint64_t zero[] = {0, 0}; 3470 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero)); 3471 uint64_t x = 1ULL << ShiftAmt; 3472 (void)apf.convertFromZeroExtendedInteger 3473 (&x, MVT::getSizeInBits(NVT), false, APFloat::rmNearestTiesToEven); 3474 Tmp2 = DAG.getConstantFP(apf, VT); 3475 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(), 3476 Node->getOperand(0), Tmp2, ISD::SETLT); 3477 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3478 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3479 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3480 Tmp2)); 3481 False = DAG.getNode(ISD::XOR, NVT, False, 3482 DAG.getConstant(1ULL << ShiftAmt, NVT)); 3483 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3484 break; 3485 } else { 3486 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3487 } 3488 break; 3489 } 3490 break; 3491 case Expand: { 3492 MVT::ValueType VT = Op.getValueType(); 3493 MVT::ValueType OVT = Node->getOperand(0).getValueType(); 3494 // Convert ppcf128 to i32 3495 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3496 if (Node->getOpcode()==ISD::FP_TO_SINT) 3497 Result = DAG.getNode(ISD::FP_TO_SINT, VT, 3498 DAG.getNode(ISD::FP_ROUND, MVT::f64, 3499 (DAG.getNode(ISD::FP_ROUND_INREG, 3500 MVT::ppcf128, Node->getOperand(0), 3501 DAG.getValueType(MVT::f64))))); 3502 else { 3503 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3504 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3505 Tmp2 = DAG.getConstantFP(apf, OVT); 3506 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3507 // FIXME: generated code sucks. 3508 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3509 DAG.getNode(ISD::ADD, MVT::i32, 3510 DAG.getNode(ISD::FP_TO_SINT, VT, 3511 DAG.getNode(ISD::FSUB, OVT, 3512 Node->getOperand(0), Tmp2)), 3513 DAG.getConstant(0x80000000, MVT::i32)), 3514 DAG.getNode(ISD::FP_TO_SINT, VT, 3515 Node->getOperand(0)), 3516 DAG.getCondCode(ISD::SETGE)); 3517 } 3518 break; 3519 } 3520 // Convert f32 / f64 to i32 / i64. 3521 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3522 switch (Node->getOpcode()) { 3523 case ISD::FP_TO_SINT: { 3524 if (OVT == MVT::f32) 3525 LC = (VT == MVT::i32) 3526 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3527 else if (OVT == MVT::f64) 3528 LC = (VT == MVT::i32) 3529 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3530 else if (OVT == MVT::f80) { 3531 assert(VT == MVT::i64); 3532 LC = RTLIB::FPTOSINT_F80_I64; 3533 } 3534 else if (OVT == MVT::ppcf128) { 3535 assert(VT == MVT::i64); 3536 LC = RTLIB::FPTOSINT_PPCF128_I64; 3537 } 3538 break; 3539 } 3540 case ISD::FP_TO_UINT: { 3541 if (OVT == MVT::f32) 3542 LC = (VT == MVT::i32) 3543 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64; 3544 else if (OVT == MVT::f64) 3545 LC = (VT == MVT::i32) 3546 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64; 3547 else if (OVT == MVT::f80) { 3548 LC = (VT == MVT::i32) 3549 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64; 3550 } 3551 else if (OVT == MVT::ppcf128) { 3552 assert(VT == MVT::i64); 3553 LC = RTLIB::FPTOUINT_PPCF128_I64; 3554 } 3555 break; 3556 } 3557 default: assert(0 && "Unreachable!"); 3558 } 3559 SDOperand Dummy; 3560 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, 3561 false/*sign irrelevant*/, Dummy); 3562 break; 3563 } 3564 case Promote: 3565 Tmp1 = PromoteOp(Node->getOperand(0)); 3566 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3567 Result = LegalizeOp(Result); 3568 break; 3569 } 3570 break; 3571 3572 case ISD::FP_EXTEND: { 3573 MVT::ValueType newVT = Op.getValueType(); 3574 MVT::ValueType oldVT = Op.getOperand(0).getValueType(); 3575 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) { 3576 // The only other way we can lower this is to turn it into a STORE, 3577 // LOAD pair, targetting a temporary location (a stack slot). 3578 3579 // NOTE: there is a choice here between constantly creating new stack 3580 // slots and always reusing the same one. We currently always create 3581 // new ones, as reuse may inhibit scheduling. 3582 const Type *Ty = MVT::getTypeForValueType(oldVT); 3583 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 3584 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3585 MachineFunction &MF = DAG.getMachineFunction(); 3586 int SSFI = 3587 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3588 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3589 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), 3590 StackSlot, NULL, 0); 3591 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT, 3592 Result, StackSlot, NULL, 0, oldVT); 3593 break; 3594 } 3595 } 3596 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3597 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3598 case Legal: 3599 Tmp1 = LegalizeOp(Node->getOperand(0)); 3600 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3601 break; 3602 case Promote: 3603 Tmp1 = PromoteOp(Node->getOperand(0)); 3604 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3605 break; 3606 } 3607 break; 3608 case ISD::FP_ROUND: { 3609 MVT::ValueType newVT = Op.getValueType(); 3610 MVT::ValueType oldVT = Op.getOperand(0).getValueType(); 3611 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) { 3612 if (oldVT == MVT::ppcf128) { 3613 SDOperand Lo, Hi; 3614 ExpandOp(Node->getOperand(0), Lo, Hi); 3615 Result = DAG.getNode(ISD::FP_ROUND, newVT, Hi); 3616 break; 3617 } else { 3618 // The only other way we can lower this is to turn it into a STORE, 3619 // LOAD pair, targetting a temporary location (a stack slot). 3620 3621 // NOTE: there is a choice here between constantly creating new stack 3622 // slots and always reusing the same one. We currently always create 3623 // new ones, as reuse may inhibit scheduling. 3624 const Type *Ty = MVT::getTypeForValueType(newVT); 3625 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 3626 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3627 MachineFunction &MF = DAG.getMachineFunction(); 3628 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align); 3629 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3630 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3631 StackSlot, NULL, 0, newVT); 3632 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0); 3633 break; 3634 } 3635 } 3636 } 3637 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3638 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3639 case Legal: 3640 Tmp1 = LegalizeOp(Node->getOperand(0)); 3641 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3642 break; 3643 case Promote: 3644 Tmp1 = PromoteOp(Node->getOperand(0)); 3645 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1); 3646 break; 3647 } 3648 break; 3649 case ISD::ANY_EXTEND: 3650 case ISD::ZERO_EXTEND: 3651 case ISD::SIGN_EXTEND: 3652 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3653 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3654 case Legal: 3655 Tmp1 = LegalizeOp(Node->getOperand(0)); 3656 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3657 break; 3658 case Promote: 3659 switch (Node->getOpcode()) { 3660 case ISD::ANY_EXTEND: 3661 Tmp1 = PromoteOp(Node->getOperand(0)); 3662 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3663 break; 3664 case ISD::ZERO_EXTEND: 3665 Result = PromoteOp(Node->getOperand(0)); 3666 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3667 Result = DAG.getZeroExtendInReg(Result, 3668 Node->getOperand(0).getValueType()); 3669 break; 3670 case ISD::SIGN_EXTEND: 3671 Result = PromoteOp(Node->getOperand(0)); 3672 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3673 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3674 Result, 3675 DAG.getValueType(Node->getOperand(0).getValueType())); 3676 break; 3677 } 3678 } 3679 break; 3680 case ISD::FP_ROUND_INREG: 3681 case ISD::SIGN_EXTEND_INREG: { 3682 Tmp1 = LegalizeOp(Node->getOperand(0)); 3683 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3684 3685 // If this operation is not supported, convert it to a shl/shr or load/store 3686 // pair. 3687 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3688 default: assert(0 && "This action not supported for this op yet!"); 3689 case TargetLowering::Legal: 3690 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3691 break; 3692 case TargetLowering::Expand: 3693 // If this is an integer extend and shifts are supported, do that. 3694 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3695 // NOTE: we could fall back on load/store here too for targets without 3696 // SAR. However, it is doubtful that any exist. 3697 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) - 3698 MVT::getSizeInBits(ExtraVT); 3699 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3700 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3701 Node->getOperand(0), ShiftCst); 3702 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3703 Result, ShiftCst); 3704 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3705 // The only way we can lower this is to turn it into a TRUNCSTORE, 3706 // EXTLOAD pair, targetting a temporary location (a stack slot). 3707 3708 // NOTE: there is a choice here between constantly creating new stack 3709 // slots and always reusing the same one. We currently always create 3710 // new ones, as reuse may inhibit scheduling. 3711 const Type *Ty = MVT::getTypeForValueType(ExtraVT); 3712 uint64_t TySize = TLI.getTargetData()->getABITypeSize(Ty); 3713 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 3714 MachineFunction &MF = DAG.getMachineFunction(); 3715 int SSFI = 3716 MF.getFrameInfo()->CreateStackObject(TySize, Align); 3717 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 3718 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0), 3719 StackSlot, NULL, 0, ExtraVT); 3720 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 3721 Result, StackSlot, NULL, 0, ExtraVT); 3722 } else { 3723 assert(0 && "Unknown op"); 3724 } 3725 break; 3726 } 3727 break; 3728 } 3729 case ISD::TRAMPOLINE: { 3730 SDOperand Ops[6]; 3731 for (unsigned i = 0; i != 6; ++i) 3732 Ops[i] = LegalizeOp(Node->getOperand(i)); 3733 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3734 // The only option for this node is to custom lower it. 3735 Result = TLI.LowerOperation(Result, DAG); 3736 assert(Result.Val && "Should always custom lower!"); 3737 3738 // Since trampoline produces two values, make sure to remember that we 3739 // legalized both of them. 3740 Tmp1 = LegalizeOp(Result.getValue(1)); 3741 Result = LegalizeOp(Result); 3742 AddLegalizedOperand(SDOperand(Node, 0), Result); 3743 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3744 return Op.ResNo ? Tmp1 : Result; 3745 } 3746 case ISD::FLT_ROUNDS: { 3747 MVT::ValueType VT = Node->getValueType(0); 3748 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3749 default: assert(0 && "This action not supported for this op yet!"); 3750 case TargetLowering::Custom: 3751 Result = TLI.LowerOperation(Op, DAG); 3752 if (Result.Val) break; 3753 // Fall Thru 3754 case TargetLowering::Legal: 3755 // If this operation is not supported, lower it to constant 1 3756 Result = DAG.getConstant(1, VT); 3757 break; 3758 } 3759 } 3760 case ISD::TRAP: { 3761 MVT::ValueType VT = Node->getValueType(0); 3762 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3763 default: assert(0 && "This action not supported for this op yet!"); 3764 case TargetLowering::Legal: 3765 Tmp1 = LegalizeOp(Node->getOperand(0)); 3766 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3767 break; 3768 case TargetLowering::Custom: 3769 Result = TLI.LowerOperation(Op, DAG); 3770 if (Result.Val) break; 3771 // Fall Thru 3772 case TargetLowering::Expand: 3773 // If this operation is not supported, lower it to 'abort()' call 3774 Tmp1 = LegalizeOp(Node->getOperand(0)); 3775 TargetLowering::ArgListTy Args; 3776 std::pair<SDOperand,SDOperand> CallResult = 3777 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false, 3778 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 3779 Args, DAG); 3780 Result = CallResult.second; 3781 break; 3782 } 3783 break; 3784 } 3785 } 3786 3787 assert(Result.getValueType() == Op.getValueType() && 3788 "Bad legalization!"); 3789 3790 // Make sure that the generated code is itself legal. 3791 if (Result != Op) 3792 Result = LegalizeOp(Result); 3793 3794 // Note that LegalizeOp may be reentered even from single-use nodes, which 3795 // means that we always must cache transformed nodes. 3796 AddLegalizedOperand(Op, Result); 3797 return Result; 3798} 3799 3800/// PromoteOp - Given an operation that produces a value in an invalid type, 3801/// promote it to compute the value into a larger type. The produced value will 3802/// have the correct bits for the low portion of the register, but no guarantee 3803/// is made about the top bits: it may be zero, sign-extended, or garbage. 3804SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 3805 MVT::ValueType VT = Op.getValueType(); 3806 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 3807 assert(getTypeAction(VT) == Promote && 3808 "Caller should expand or legalize operands that are not promotable!"); 3809 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) && 3810 "Cannot promote to smaller type!"); 3811 3812 SDOperand Tmp1, Tmp2, Tmp3; 3813 SDOperand Result; 3814 SDNode *Node = Op.Val; 3815 3816 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 3817 if (I != PromotedNodes.end()) return I->second; 3818 3819 switch (Node->getOpcode()) { 3820 case ISD::CopyFromReg: 3821 assert(0 && "CopyFromReg must be legal!"); 3822 default: 3823#ifndef NDEBUG 3824 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 3825#endif 3826 assert(0 && "Do not know how to promote this operator!"); 3827 abort(); 3828 case ISD::UNDEF: 3829 Result = DAG.getNode(ISD::UNDEF, NVT); 3830 break; 3831 case ISD::Constant: 3832 if (VT != MVT::i1) 3833 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 3834 else 3835 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 3836 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 3837 break; 3838 case ISD::ConstantFP: 3839 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 3840 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 3841 break; 3842 3843 case ISD::SETCC: 3844 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??"); 3845 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0), 3846 Node->getOperand(1), Node->getOperand(2)); 3847 break; 3848 3849 case ISD::TRUNCATE: 3850 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3851 case Legal: 3852 Result = LegalizeOp(Node->getOperand(0)); 3853 assert(Result.getValueType() >= NVT && 3854 "This truncation doesn't make sense!"); 3855 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT 3856 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 3857 break; 3858 case Promote: 3859 // The truncation is not required, because we don't guarantee anything 3860 // about high bits anyway. 3861 Result = PromoteOp(Node->getOperand(0)); 3862 break; 3863 case Expand: 3864 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3865 // Truncate the low part of the expanded value to the result type 3866 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 3867 } 3868 break; 3869 case ISD::SIGN_EXTEND: 3870 case ISD::ZERO_EXTEND: 3871 case ISD::ANY_EXTEND: 3872 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3873 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 3874 case Legal: 3875 // Input is legal? Just do extend all the way to the larger type. 3876 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3877 break; 3878 case Promote: 3879 // Promote the reg if it's smaller. 3880 Result = PromoteOp(Node->getOperand(0)); 3881 // The high bits are not guaranteed to be anything. Insert an extend. 3882 if (Node->getOpcode() == ISD::SIGN_EXTEND) 3883 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3884 DAG.getValueType(Node->getOperand(0).getValueType())); 3885 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 3886 Result = DAG.getZeroExtendInReg(Result, 3887 Node->getOperand(0).getValueType()); 3888 break; 3889 } 3890 break; 3891 case ISD::BIT_CONVERT: 3892 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0)); 3893 Result = PromoteOp(Result); 3894 break; 3895 3896 case ISD::FP_EXTEND: 3897 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 3898 case ISD::FP_ROUND: 3899 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3900 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 3901 case Promote: assert(0 && "Unreachable with 2 FP types!"); 3902 case Legal: 3903 // Input is legal? Do an FP_ROUND_INREG. 3904 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 3905 DAG.getValueType(VT)); 3906 break; 3907 } 3908 break; 3909 3910 case ISD::SINT_TO_FP: 3911 case ISD::UINT_TO_FP: 3912 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3913 case Legal: 3914 // No extra round required here. 3915 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 3916 break; 3917 3918 case Promote: 3919 Result = PromoteOp(Node->getOperand(0)); 3920 if (Node->getOpcode() == ISD::SINT_TO_FP) 3921 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3922 Result, 3923 DAG.getValueType(Node->getOperand(0).getValueType())); 3924 else 3925 Result = DAG.getZeroExtendInReg(Result, 3926 Node->getOperand(0).getValueType()); 3927 // No extra round required here. 3928 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 3929 break; 3930 case Expand: 3931 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 3932 Node->getOperand(0)); 3933 // Round if we cannot tolerate excess precision. 3934 if (NoExcessFPPrecision) 3935 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3936 DAG.getValueType(VT)); 3937 break; 3938 } 3939 break; 3940 3941 case ISD::SIGN_EXTEND_INREG: 3942 Result = PromoteOp(Node->getOperand(0)); 3943 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 3944 Node->getOperand(1)); 3945 break; 3946 case ISD::FP_TO_SINT: 3947 case ISD::FP_TO_UINT: 3948 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3949 case Legal: 3950 case Expand: 3951 Tmp1 = Node->getOperand(0); 3952 break; 3953 case Promote: 3954 // The input result is prerounded, so we don't have to do anything 3955 // special. 3956 Tmp1 = PromoteOp(Node->getOperand(0)); 3957 break; 3958 } 3959 // If we're promoting a UINT to a larger size, check to see if the new node 3960 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 3961 // we can use that instead. This allows us to generate better code for 3962 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 3963 // legal, such as PowerPC. 3964 if (Node->getOpcode() == ISD::FP_TO_UINT && 3965 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 3966 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 3967 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 3968 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 3969 } else { 3970 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3971 } 3972 break; 3973 3974 case ISD::FABS: 3975 case ISD::FNEG: 3976 Tmp1 = PromoteOp(Node->getOperand(0)); 3977 assert(Tmp1.getValueType() == NVT); 3978 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3979 // NOTE: we do not have to do any extra rounding here for 3980 // NoExcessFPPrecision, because we know the input will have the appropriate 3981 // precision, and these operations don't modify precision at all. 3982 break; 3983 3984 case ISD::FSQRT: 3985 case ISD::FSIN: 3986 case ISD::FCOS: 3987 Tmp1 = PromoteOp(Node->getOperand(0)); 3988 assert(Tmp1.getValueType() == NVT); 3989 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 3990 if (NoExcessFPPrecision) 3991 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 3992 DAG.getValueType(VT)); 3993 break; 3994 3995 case ISD::FPOWI: { 3996 // Promote f32 powi to f64 powi. Note that this could insert a libcall 3997 // directly as well, which may be better. 3998 Tmp1 = PromoteOp(Node->getOperand(0)); 3999 assert(Tmp1.getValueType() == NVT); 4000 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 4001 if (NoExcessFPPrecision) 4002 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4003 DAG.getValueType(VT)); 4004 break; 4005 } 4006 4007 case ISD::AND: 4008 case ISD::OR: 4009 case ISD::XOR: 4010 case ISD::ADD: 4011 case ISD::SUB: 4012 case ISD::MUL: 4013 // The input may have strange things in the top bits of the registers, but 4014 // these operations don't care. They may have weird bits going out, but 4015 // that too is okay if they are integer operations. 4016 Tmp1 = PromoteOp(Node->getOperand(0)); 4017 Tmp2 = PromoteOp(Node->getOperand(1)); 4018 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4019 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4020 break; 4021 case ISD::FADD: 4022 case ISD::FSUB: 4023 case ISD::FMUL: 4024 Tmp1 = PromoteOp(Node->getOperand(0)); 4025 Tmp2 = PromoteOp(Node->getOperand(1)); 4026 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4027 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4028 4029 // Floating point operations will give excess precision that we may not be 4030 // able to tolerate. If we DO allow excess precision, just leave it, 4031 // otherwise excise it. 4032 // FIXME: Why would we need to round FP ops more than integer ones? 4033 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4034 if (NoExcessFPPrecision) 4035 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4036 DAG.getValueType(VT)); 4037 break; 4038 4039 case ISD::SDIV: 4040 case ISD::SREM: 4041 // These operators require that their input be sign extended. 4042 Tmp1 = PromoteOp(Node->getOperand(0)); 4043 Tmp2 = PromoteOp(Node->getOperand(1)); 4044 if (MVT::isInteger(NVT)) { 4045 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4046 DAG.getValueType(VT)); 4047 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4048 DAG.getValueType(VT)); 4049 } 4050 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4051 4052 // Perform FP_ROUND: this is probably overly pessimistic. 4053 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision) 4054 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4055 DAG.getValueType(VT)); 4056 break; 4057 case ISD::FDIV: 4058 case ISD::FREM: 4059 case ISD::FCOPYSIGN: 4060 // These operators require that their input be fp extended. 4061 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4062 case Legal: 4063 Tmp1 = LegalizeOp(Node->getOperand(0)); 4064 break; 4065 case Promote: 4066 Tmp1 = PromoteOp(Node->getOperand(0)); 4067 break; 4068 case Expand: 4069 assert(0 && "not implemented"); 4070 } 4071 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4072 case Legal: 4073 Tmp2 = LegalizeOp(Node->getOperand(1)); 4074 break; 4075 case Promote: 4076 Tmp2 = PromoteOp(Node->getOperand(1)); 4077 break; 4078 case Expand: 4079 assert(0 && "not implemented"); 4080 } 4081 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4082 4083 // Perform FP_ROUND: this is probably overly pessimistic. 4084 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4085 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4086 DAG.getValueType(VT)); 4087 break; 4088 4089 case ISD::UDIV: 4090 case ISD::UREM: 4091 // These operators require that their input be zero extended. 4092 Tmp1 = PromoteOp(Node->getOperand(0)); 4093 Tmp2 = PromoteOp(Node->getOperand(1)); 4094 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!"); 4095 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4096 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4097 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4098 break; 4099 4100 case ISD::SHL: 4101 Tmp1 = PromoteOp(Node->getOperand(0)); 4102 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4103 break; 4104 case ISD::SRA: 4105 // The input value must be properly sign extended. 4106 Tmp1 = PromoteOp(Node->getOperand(0)); 4107 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4108 DAG.getValueType(VT)); 4109 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4110 break; 4111 case ISD::SRL: 4112 // The input value must be properly zero extended. 4113 Tmp1 = PromoteOp(Node->getOperand(0)); 4114 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4115 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4116 break; 4117 4118 case ISD::VAARG: 4119 Tmp1 = Node->getOperand(0); // Get the chain. 4120 Tmp2 = Node->getOperand(1); // Get the pointer. 4121 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4122 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4123 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 4124 } else { 4125 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 4126 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, 4127 SV->getValue(), SV->getOffset()); 4128 // Increment the pointer, VAList, to the next vaarg 4129 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4130 DAG.getConstant(MVT::getSizeInBits(VT)/8, 4131 TLI.getPointerTy())); 4132 // Store the incremented VAList to the legalized pointer 4133 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(), 4134 SV->getOffset()); 4135 // Load the actual argument out of the pointer VAList 4136 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4137 } 4138 // Remember that we legalized the chain. 4139 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4140 break; 4141 4142 case ISD::LOAD: { 4143 LoadSDNode *LD = cast<LoadSDNode>(Node); 4144 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4145 ? ISD::EXTLOAD : LD->getExtensionType(); 4146 Result = DAG.getExtLoad(ExtType, NVT, 4147 LD->getChain(), LD->getBasePtr(), 4148 LD->getSrcValue(), LD->getSrcValueOffset(), 4149 LD->getLoadedVT(), 4150 LD->isVolatile(), 4151 LD->getAlignment()); 4152 // Remember that we legalized the chain. 4153 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4154 break; 4155 } 4156 case ISD::SELECT: 4157 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4158 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4159 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3); 4160 break; 4161 case ISD::SELECT_CC: 4162 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4163 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4164 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4165 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4166 break; 4167 case ISD::BSWAP: 4168 Tmp1 = Node->getOperand(0); 4169 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4170 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4171 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4172 DAG.getConstant(MVT::getSizeInBits(NVT) - 4173 MVT::getSizeInBits(VT), 4174 TLI.getShiftAmountTy())); 4175 break; 4176 case ISD::CTPOP: 4177 case ISD::CTTZ: 4178 case ISD::CTLZ: 4179 // Zero extend the argument 4180 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4181 // Perform the larger operation, then subtract if needed. 4182 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4183 switch(Node->getOpcode()) { 4184 case ISD::CTPOP: 4185 Result = Tmp1; 4186 break; 4187 case ISD::CTTZ: 4188 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4189 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, 4190 DAG.getConstant(MVT::getSizeInBits(NVT), NVT), 4191 ISD::SETEQ); 4192 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4193 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1); 4194 break; 4195 case ISD::CTLZ: 4196 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4197 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4198 DAG.getConstant(MVT::getSizeInBits(NVT) - 4199 MVT::getSizeInBits(VT), NVT)); 4200 break; 4201 } 4202 break; 4203 case ISD::EXTRACT_SUBVECTOR: 4204 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4205 break; 4206 case ISD::EXTRACT_VECTOR_ELT: 4207 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4208 break; 4209 } 4210 4211 assert(Result.Val && "Didn't set a result!"); 4212 4213 // Make sure the result is itself legal. 4214 Result = LegalizeOp(Result); 4215 4216 // Remember that we promoted this! 4217 AddPromotedOperand(Op, Result); 4218 return Result; 4219} 4220 4221/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4222/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4223/// based on the vector type. The return type of this matches the element type 4224/// of the vector, which may not be legal for the target. 4225SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4226 // We know that operand #0 is the Vec vector. If the index is a constant 4227 // or if the invec is a supported hardware type, we can use it. Otherwise, 4228 // lower to a store then an indexed load. 4229 SDOperand Vec = Op.getOperand(0); 4230 SDOperand Idx = Op.getOperand(1); 4231 4232 MVT::ValueType TVT = Vec.getValueType(); 4233 unsigned NumElems = MVT::getVectorNumElements(TVT); 4234 4235 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4236 default: assert(0 && "This action is not supported yet!"); 4237 case TargetLowering::Custom: { 4238 Vec = LegalizeOp(Vec); 4239 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4240 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4241 if (Tmp3.Val) 4242 return Tmp3; 4243 break; 4244 } 4245 case TargetLowering::Legal: 4246 if (isTypeLegal(TVT)) { 4247 Vec = LegalizeOp(Vec); 4248 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4249 return Op; 4250 } 4251 break; 4252 case TargetLowering::Expand: 4253 break; 4254 } 4255 4256 if (NumElems == 1) { 4257 // This must be an access of the only element. Return it. 4258 Op = ScalarizeVectorOp(Vec); 4259 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4260 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4261 SDOperand Lo, Hi; 4262 SplitVectorOp(Vec, Lo, Hi); 4263 if (CIdx->getValue() < NumElems/2) { 4264 Vec = Lo; 4265 } else { 4266 Vec = Hi; 4267 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, 4268 Idx.getValueType()); 4269 } 4270 4271 // It's now an extract from the appropriate high or low part. Recurse. 4272 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4273 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4274 } else { 4275 // Store the value to a temporary stack slot, then LOAD the scalar 4276 // element back out. 4277 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4278 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4279 4280 // Add the offset to the index. 4281 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8; 4282 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4283 DAG.getConstant(EltSize, Idx.getValueType())); 4284 4285 if (MVT::getSizeInBits(Idx.getValueType()) > 4286 MVT::getSizeInBits(TLI.getPointerTy())) 4287 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4288 else 4289 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4290 4291 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4292 4293 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4294 } 4295 return Op; 4296} 4297 4298/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4299/// we assume the operation can be split if it is not already legal. 4300SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4301 // We know that operand #0 is the Vec vector. For now we assume the index 4302 // is a constant and that the extracted result is a supported hardware type. 4303 SDOperand Vec = Op.getOperand(0); 4304 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4305 4306 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType()); 4307 4308 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) { 4309 // This must be an access of the desired vector length. Return it. 4310 return Vec; 4311 } 4312 4313 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4314 SDOperand Lo, Hi; 4315 SplitVectorOp(Vec, Lo, Hi); 4316 if (CIdx->getValue() < NumElems/2) { 4317 Vec = Lo; 4318 } else { 4319 Vec = Hi; 4320 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4321 } 4322 4323 // It's now an extract from the appropriate high or low part. Recurse. 4324 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4325 return ExpandEXTRACT_SUBVECTOR(Op); 4326} 4327 4328/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4329/// with condition CC on the current target. This usually involves legalizing 4330/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4331/// there may be no choice but to create a new SetCC node to represent the 4332/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4333/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4334void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4335 SDOperand &RHS, 4336 SDOperand &CC) { 4337 SDOperand Tmp1, Tmp2, Tmp3, Result; 4338 4339 switch (getTypeAction(LHS.getValueType())) { 4340 case Legal: 4341 Tmp1 = LegalizeOp(LHS); // LHS 4342 Tmp2 = LegalizeOp(RHS); // RHS 4343 break; 4344 case Promote: 4345 Tmp1 = PromoteOp(LHS); // LHS 4346 Tmp2 = PromoteOp(RHS); // RHS 4347 4348 // If this is an FP compare, the operands have already been extended. 4349 if (MVT::isInteger(LHS.getValueType())) { 4350 MVT::ValueType VT = LHS.getValueType(); 4351 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 4352 4353 // Otherwise, we have to insert explicit sign or zero extends. Note 4354 // that we could insert sign extends for ALL conditions, but zero extend 4355 // is cheaper on many machines (an AND instead of two shifts), so prefer 4356 // it. 4357 switch (cast<CondCodeSDNode>(CC)->get()) { 4358 default: assert(0 && "Unknown integer comparison!"); 4359 case ISD::SETEQ: 4360 case ISD::SETNE: 4361 case ISD::SETUGE: 4362 case ISD::SETUGT: 4363 case ISD::SETULE: 4364 case ISD::SETULT: 4365 // ALL of these operations will work if we either sign or zero extend 4366 // the operands (including the unsigned comparisons!). Zero extend is 4367 // usually a simpler/cheaper operation, so prefer it. 4368 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4369 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4370 break; 4371 case ISD::SETGE: 4372 case ISD::SETGT: 4373 case ISD::SETLT: 4374 case ISD::SETLE: 4375 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4376 DAG.getValueType(VT)); 4377 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4378 DAG.getValueType(VT)); 4379 break; 4380 } 4381 } 4382 break; 4383 case Expand: { 4384 MVT::ValueType VT = LHS.getValueType(); 4385 if (VT == MVT::f32 || VT == MVT::f64) { 4386 // Expand into one or more soft-fp libcall(s). 4387 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4388 switch (cast<CondCodeSDNode>(CC)->get()) { 4389 case ISD::SETEQ: 4390 case ISD::SETOEQ: 4391 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4392 break; 4393 case ISD::SETNE: 4394 case ISD::SETUNE: 4395 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4396 break; 4397 case ISD::SETGE: 4398 case ISD::SETOGE: 4399 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4400 break; 4401 case ISD::SETLT: 4402 case ISD::SETOLT: 4403 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4404 break; 4405 case ISD::SETLE: 4406 case ISD::SETOLE: 4407 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4408 break; 4409 case ISD::SETGT: 4410 case ISD::SETOGT: 4411 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4412 break; 4413 case ISD::SETUO: 4414 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4415 break; 4416 case ISD::SETO: 4417 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4418 break; 4419 default: 4420 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4421 switch (cast<CondCodeSDNode>(CC)->get()) { 4422 case ISD::SETONE: 4423 // SETONE = SETOLT | SETOGT 4424 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4425 // Fallthrough 4426 case ISD::SETUGT: 4427 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4428 break; 4429 case ISD::SETUGE: 4430 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4431 break; 4432 case ISD::SETULT: 4433 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4434 break; 4435 case ISD::SETULE: 4436 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4437 break; 4438 case ISD::SETUEQ: 4439 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4440 break; 4441 default: assert(0 && "Unsupported FP setcc!"); 4442 } 4443 } 4444 4445 SDOperand Dummy; 4446 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1), 4447 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4448 false /*sign irrelevant*/, Dummy); 4449 Tmp2 = DAG.getConstant(0, MVT::i32); 4450 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4451 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4452 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC); 4453 LHS = ExpandLibCall(TLI.getLibcallName(LC2), 4454 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4455 false /*sign irrelevant*/, Dummy); 4456 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2, 4457 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4458 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4459 Tmp2 = SDOperand(); 4460 } 4461 LHS = Tmp1; 4462 RHS = Tmp2; 4463 return; 4464 } 4465 4466 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4467 ExpandOp(LHS, LHSLo, LHSHi); 4468 ExpandOp(RHS, RHSLo, RHSHi); 4469 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4470 4471 if (VT==MVT::ppcf128) { 4472 // FIXME: This generated code sucks. We want to generate 4473 // FCMP crN, hi1, hi2 4474 // BNE crN, L: 4475 // FCMP crN, lo1, lo2 4476 // The following can be improved, but not that much. 4477 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4478 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode); 4479 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4480 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE); 4481 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode); 4482 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4483 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4484 Tmp2 = SDOperand(); 4485 break; 4486 } 4487 4488 switch (CCCode) { 4489 case ISD::SETEQ: 4490 case ISD::SETNE: 4491 if (RHSLo == RHSHi) 4492 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4493 if (RHSCST->isAllOnesValue()) { 4494 // Comparison to -1. 4495 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4496 Tmp2 = RHSLo; 4497 break; 4498 } 4499 4500 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4501 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4502 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4503 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4504 break; 4505 default: 4506 // If this is a comparison of the sign bit, just look at the top part. 4507 // X > -1, x < 0 4508 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4509 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4510 CST->getValue() == 0) || // X < 0 4511 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4512 CST->isAllOnesValue())) { // X > -1 4513 Tmp1 = LHSHi; 4514 Tmp2 = RHSHi; 4515 break; 4516 } 4517 4518 // FIXME: This generated code sucks. 4519 ISD::CondCode LowCC; 4520 switch (CCCode) { 4521 default: assert(0 && "Unknown integer setcc!"); 4522 case ISD::SETLT: 4523 case ISD::SETULT: LowCC = ISD::SETULT; break; 4524 case ISD::SETGT: 4525 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4526 case ISD::SETLE: 4527 case ISD::SETULE: LowCC = ISD::SETULE; break; 4528 case ISD::SETGE: 4529 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4530 } 4531 4532 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4533 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4534 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4535 4536 // NOTE: on targets without efficient SELECT of bools, we can always use 4537 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4538 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4539 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC, 4540 false, DagCombineInfo); 4541 if (!Tmp1.Val) 4542 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC); 4543 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4544 CCCode, false, DagCombineInfo); 4545 if (!Tmp2.Val) 4546 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC); 4547 4548 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4549 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4550 if ((Tmp1C && Tmp1C->getValue() == 0) || 4551 (Tmp2C && Tmp2C->getValue() == 0 && 4552 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4553 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4554 (Tmp2C && Tmp2C->getValue() == 1 && 4555 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4556 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4557 // low part is known false, returns high part. 4558 // For LE / GE, if high part is known false, ignore the low part. 4559 // For LT / GT, if high part is known true, ignore the low part. 4560 Tmp1 = Tmp2; 4561 Tmp2 = SDOperand(); 4562 } else { 4563 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, 4564 ISD::SETEQ, false, DagCombineInfo); 4565 if (!Result.Val) 4566 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ); 4567 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4568 Result, Tmp1, Tmp2)); 4569 Tmp1 = Result; 4570 Tmp2 = SDOperand(); 4571 } 4572 } 4573 } 4574 } 4575 LHS = Tmp1; 4576 RHS = Tmp2; 4577} 4578 4579/// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination. 4580/// The resultant code need not be legal. Note that SrcOp is the input operand 4581/// to the BIT_CONVERT, not the BIT_CONVERT node itself. 4582SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT, 4583 SDOperand SrcOp) { 4584 // Create the stack frame object. 4585 SDOperand FIPtr = DAG.CreateStackTemporary(DestVT); 4586 4587 // Emit a store to the stack slot. 4588 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0); 4589 // Result is a load from the stack slot. 4590 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4591} 4592 4593SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4594 // Create a vector sized/aligned stack slot, store the value to element #0, 4595 // then load the whole vector back out. 4596 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4597 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4598 NULL, 0); 4599 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0); 4600} 4601 4602 4603/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4604/// support the operation, but do support the resultant vector type. 4605SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4606 4607 // If the only non-undef value is the low element, turn this into a 4608 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4609 unsigned NumElems = Node->getNumOperands(); 4610 bool isOnlyLowElement = true; 4611 SDOperand SplatValue = Node->getOperand(0); 4612 std::map<SDOperand, std::vector<unsigned> > Values; 4613 Values[SplatValue].push_back(0); 4614 bool isConstant = true; 4615 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4616 SplatValue.getOpcode() != ISD::UNDEF) 4617 isConstant = false; 4618 4619 for (unsigned i = 1; i < NumElems; ++i) { 4620 SDOperand V = Node->getOperand(i); 4621 Values[V].push_back(i); 4622 if (V.getOpcode() != ISD::UNDEF) 4623 isOnlyLowElement = false; 4624 if (SplatValue != V) 4625 SplatValue = SDOperand(0,0); 4626 4627 // If this isn't a constant element or an undef, we can't use a constant 4628 // pool load. 4629 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4630 V.getOpcode() != ISD::UNDEF) 4631 isConstant = false; 4632 } 4633 4634 if (isOnlyLowElement) { 4635 // If the low element is an undef too, then this whole things is an undef. 4636 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4637 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4638 // Otherwise, turn this into a scalar_to_vector node. 4639 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4640 Node->getOperand(0)); 4641 } 4642 4643 // If all elements are constants, create a load from the constant pool. 4644 if (isConstant) { 4645 MVT::ValueType VT = Node->getValueType(0); 4646 const Type *OpNTy = 4647 MVT::getTypeForValueType(Node->getOperand(0).getValueType()); 4648 std::vector<Constant*> CV; 4649 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4650 if (ConstantFPSDNode *V = 4651 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4652 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF())); 4653 } else if (ConstantSDNode *V = 4654 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4655 CV.push_back(ConstantInt::get(OpNTy, V->getValue())); 4656 } else { 4657 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4658 CV.push_back(UndefValue::get(OpNTy)); 4659 } 4660 } 4661 Constant *CP = ConstantVector::get(CV); 4662 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4663 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0); 4664 } 4665 4666 if (SplatValue.Val) { // Splat of one value? 4667 // Build the shuffle constant vector: <0, 0, 0, 0> 4668 MVT::ValueType MaskVT = 4669 MVT::getIntVectorWithNumElements(NumElems); 4670 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT)); 4671 std::vector<SDOperand> ZeroVec(NumElems, Zero); 4672 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4673 &ZeroVec[0], ZeroVec.size()); 4674 4675 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4676 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 4677 // Get the splatted value into the low element of a vector register. 4678 SDOperand LowValVec = 4679 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 4680 4681 // Return shuffle(LowValVec, undef, <0,0,0,0>) 4682 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 4683 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 4684 SplatMask); 4685 } 4686 } 4687 4688 // If there are only two unique elements, we may be able to turn this into a 4689 // vector shuffle. 4690 if (Values.size() == 2) { 4691 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 4692 MVT::ValueType MaskVT = 4693 MVT::getIntVectorWithNumElements(NumElems); 4694 std::vector<SDOperand> MaskVec(NumElems); 4695 unsigned i = 0; 4696 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4697 E = Values.end(); I != E; ++I) { 4698 for (std::vector<unsigned>::iterator II = I->second.begin(), 4699 EE = I->second.end(); II != EE; ++II) 4700 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT)); 4701 i += NumElems; 4702 } 4703 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 4704 &MaskVec[0], MaskVec.size()); 4705 4706 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 4707 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 4708 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 4709 SmallVector<SDOperand, 8> Ops; 4710 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(), 4711 E = Values.end(); I != E; ++I) { 4712 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4713 I->first); 4714 Ops.push_back(Op); 4715 } 4716 Ops.push_back(ShuffleMask); 4717 4718 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 4719 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), 4720 &Ops[0], Ops.size()); 4721 } 4722 } 4723 4724 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 4725 // aligned object on the stack, store each element into it, then load 4726 // the result as a vector. 4727 MVT::ValueType VT = Node->getValueType(0); 4728 // Create the stack frame object. 4729 SDOperand FIPtr = DAG.CreateStackTemporary(VT); 4730 4731 // Emit a store of each element to the stack slot. 4732 SmallVector<SDOperand, 8> Stores; 4733 unsigned TypeByteSize = 4734 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8; 4735 // Store (in the right endianness) the elements to memory. 4736 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4737 // Ignore undef elements. 4738 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4739 4740 unsigned Offset = TypeByteSize*i; 4741 4742 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 4743 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 4744 4745 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 4746 NULL, 0)); 4747 } 4748 4749 SDOperand StoreChain; 4750 if (!Stores.empty()) // Not all undef elements? 4751 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4752 &Stores[0], Stores.size()); 4753 else 4754 StoreChain = DAG.getEntryNode(); 4755 4756 // Result is a load from the stack slot. 4757 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 4758} 4759 4760void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 4761 SDOperand Op, SDOperand Amt, 4762 SDOperand &Lo, SDOperand &Hi) { 4763 // Expand the subcomponents. 4764 SDOperand LHSL, LHSH; 4765 ExpandOp(Op, LHSL, LHSH); 4766 4767 SDOperand Ops[] = { LHSL, LHSH, Amt }; 4768 MVT::ValueType VT = LHSL.getValueType(); 4769 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 4770 Hi = Lo.getValue(1); 4771} 4772 4773 4774/// ExpandShift - Try to find a clever way to expand this shift operation out to 4775/// smaller elements. If we can't find a way that is more efficient than a 4776/// libcall on this target, return false. Otherwise, return true with the 4777/// low-parts expanded into Lo and Hi. 4778bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 4779 SDOperand &Lo, SDOperand &Hi) { 4780 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 4781 "This is not a shift!"); 4782 4783 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType()); 4784 SDOperand ShAmt = LegalizeOp(Amt); 4785 MVT::ValueType ShTy = ShAmt.getValueType(); 4786 unsigned VTBits = MVT::getSizeInBits(Op.getValueType()); 4787 unsigned NVTBits = MVT::getSizeInBits(NVT); 4788 4789 // Handle the case when Amt is an immediate. 4790 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 4791 unsigned Cst = CN->getValue(); 4792 // Expand the incoming operand to be shifted, so that we have its parts 4793 SDOperand InL, InH; 4794 ExpandOp(Op, InL, InH); 4795 switch(Opc) { 4796 case ISD::SHL: 4797 if (Cst > VTBits) { 4798 Lo = DAG.getConstant(0, NVT); 4799 Hi = DAG.getConstant(0, NVT); 4800 } else if (Cst > NVTBits) { 4801 Lo = DAG.getConstant(0, NVT); 4802 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 4803 } else if (Cst == NVTBits) { 4804 Lo = DAG.getConstant(0, NVT); 4805 Hi = InL; 4806 } else { 4807 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 4808 Hi = DAG.getNode(ISD::OR, NVT, 4809 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 4810 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 4811 } 4812 return true; 4813 case ISD::SRL: 4814 if (Cst > VTBits) { 4815 Lo = DAG.getConstant(0, NVT); 4816 Hi = DAG.getConstant(0, NVT); 4817 } else if (Cst > NVTBits) { 4818 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 4819 Hi = DAG.getConstant(0, NVT); 4820 } else if (Cst == NVTBits) { 4821 Lo = InH; 4822 Hi = DAG.getConstant(0, NVT); 4823 } else { 4824 Lo = DAG.getNode(ISD::OR, NVT, 4825 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4826 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4827 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 4828 } 4829 return true; 4830 case ISD::SRA: 4831 if (Cst > VTBits) { 4832 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 4833 DAG.getConstant(NVTBits-1, ShTy)); 4834 } else if (Cst > NVTBits) { 4835 Lo = DAG.getNode(ISD::SRA, NVT, InH, 4836 DAG.getConstant(Cst-NVTBits, ShTy)); 4837 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4838 DAG.getConstant(NVTBits-1, ShTy)); 4839 } else if (Cst == NVTBits) { 4840 Lo = InH; 4841 Hi = DAG.getNode(ISD::SRA, NVT, InH, 4842 DAG.getConstant(NVTBits-1, ShTy)); 4843 } else { 4844 Lo = DAG.getNode(ISD::OR, NVT, 4845 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 4846 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 4847 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 4848 } 4849 return true; 4850 } 4851 } 4852 4853 // Okay, the shift amount isn't constant. However, if we can tell that it is 4854 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 4855 uint64_t Mask = NVTBits, KnownZero, KnownOne; 4856 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 4857 4858 // If we know that the high bit of the shift amount is one, then we can do 4859 // this as a couple of simple shifts. 4860 if (KnownOne & Mask) { 4861 // Mask out the high bit, which we know is set. 4862 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 4863 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4864 4865 // Expand the incoming operand to be shifted, so that we have its parts 4866 SDOperand InL, InH; 4867 ExpandOp(Op, InL, InH); 4868 switch(Opc) { 4869 case ISD::SHL: 4870 Lo = DAG.getConstant(0, NVT); // Low part is zero. 4871 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 4872 return true; 4873 case ISD::SRL: 4874 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 4875 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 4876 return true; 4877 case ISD::SRA: 4878 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 4879 DAG.getConstant(NVTBits-1, Amt.getValueType())); 4880 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 4881 return true; 4882 } 4883 } 4884 4885 // If we know that the high bit of the shift amount is zero, then we can do 4886 // this as a couple of simple shifts. 4887 if (KnownZero & Mask) { 4888 // Compute 32-amt. 4889 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 4890 DAG.getConstant(NVTBits, Amt.getValueType()), 4891 Amt); 4892 4893 // Expand the incoming operand to be shifted, so that we have its parts 4894 SDOperand InL, InH; 4895 ExpandOp(Op, InL, InH); 4896 switch(Opc) { 4897 case ISD::SHL: 4898 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 4899 Hi = DAG.getNode(ISD::OR, NVT, 4900 DAG.getNode(ISD::SHL, NVT, InH, Amt), 4901 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 4902 return true; 4903 case ISD::SRL: 4904 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 4905 Lo = DAG.getNode(ISD::OR, NVT, 4906 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4907 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4908 return true; 4909 case ISD::SRA: 4910 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 4911 Lo = DAG.getNode(ISD::OR, NVT, 4912 DAG.getNode(ISD::SRL, NVT, InL, Amt), 4913 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 4914 return true; 4915 } 4916 } 4917 4918 return false; 4919} 4920 4921 4922// ExpandLibCall - Expand a node into a call to a libcall. If the result value 4923// does not fit into a register, return the lo part and set the hi part to the 4924// by-reg argument. If it does fit into a single register, return the result 4925// and leave the Hi part unset. 4926SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node, 4927 bool isSigned, SDOperand &Hi) { 4928 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 4929 // The input chain to this libcall is the entry node of the function. 4930 // Legalizing the call will automatically add the previous call to the 4931 // dependence. 4932 SDOperand InChain = DAG.getEntryNode(); 4933 4934 TargetLowering::ArgListTy Args; 4935 TargetLowering::ArgListEntry Entry; 4936 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 4937 MVT::ValueType ArgVT = Node->getOperand(i).getValueType(); 4938 const Type *ArgTy = MVT::getTypeForValueType(ArgVT); 4939 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 4940 Entry.isSExt = isSigned; 4941 Args.push_back(Entry); 4942 } 4943 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy()); 4944 4945 // Splice the libcall in wherever FindInputOutputChains tells us to. 4946 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0)); 4947 std::pair<SDOperand,SDOperand> CallInfo = 4948 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false, 4949 Callee, Args, DAG); 4950 4951 // Legalize the call sequence, starting with the chain. This will advance 4952 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 4953 // was added by LowerCallTo (guaranteeing proper serialization of calls). 4954 LegalizeOp(CallInfo.second); 4955 SDOperand Result; 4956 switch (getTypeAction(CallInfo.first.getValueType())) { 4957 default: assert(0 && "Unknown thing"); 4958 case Legal: 4959 Result = CallInfo.first; 4960 break; 4961 case Expand: 4962 ExpandOp(CallInfo.first, Result, Hi); 4963 break; 4964 } 4965 return Result; 4966} 4967 4968 4969/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 4970/// 4971SDOperand SelectionDAGLegalize:: 4972ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) { 4973 assert(getTypeAction(Source.getValueType()) == Expand && 4974 "This is not an expansion!"); 4975 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!"); 4976 4977 if (!isSigned) { 4978 assert(Source.getValueType() == MVT::i64 && 4979 "This only works for 64-bit -> FP"); 4980 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 4981 // incoming integer is set. To handle this, we dynamically test to see if 4982 // it is set, and, if so, add a fudge factor. 4983 SDOperand Lo, Hi; 4984 ExpandOp(Source, Lo, Hi); 4985 4986 // If this is unsigned, and not supported, first perform the conversion to 4987 // signed, then adjust the result if the sign bit is set. 4988 SDOperand SignedConv = ExpandIntToFP(true, DestTy, 4989 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi)); 4990 4991 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi, 4992 DAG.getConstant(0, Hi.getValueType()), 4993 ISD::SETLT); 4994 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 4995 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 4996 SignSet, Four, Zero); 4997 uint64_t FF = 0x5f800000ULL; 4998 if (TLI.isLittleEndian()) FF <<= 32; 4999 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5000 5001 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5002 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5003 SDOperand FudgeInReg; 5004 if (DestTy == MVT::f32) 5005 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 5006 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32)) 5007 // FIXME: Avoid the extend by construction the right constantpool? 5008 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5009 CPIdx, NULL, 0, MVT::f32); 5010 else 5011 assert(0 && "Unexpected conversion"); 5012 5013 MVT::ValueType SCVT = SignedConv.getValueType(); 5014 if (SCVT != DestTy) { 5015 // Destination type needs to be expanded as well. The FADD now we are 5016 // constructing will be expanded into a libcall. 5017 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) { 5018 assert(SCVT == MVT::i32 && DestTy == MVT::f64); 5019 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, 5020 SignedConv, SignedConv.getValue(1)); 5021 } 5022 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5023 } 5024 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5025 } 5026 5027 // Check to see if the target has a custom way to lower this. If so, use it. 5028 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) { 5029 default: assert(0 && "This action not implemented for this operation!"); 5030 case TargetLowering::Legal: 5031 case TargetLowering::Expand: 5032 break; // This case is handled below. 5033 case TargetLowering::Custom: { 5034 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5035 Source), DAG); 5036 if (NV.Val) 5037 return LegalizeOp(NV); 5038 break; // The target decided this was legal after all 5039 } 5040 } 5041 5042 // Expand the source, then glue it back together for the call. We must expand 5043 // the source in case it is shared (this pass of legalize must traverse it). 5044 SDOperand SrcLo, SrcHi; 5045 ExpandOp(Source, SrcLo, SrcHi); 5046 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi); 5047 5048 RTLIB::Libcall LC; 5049 if (DestTy == MVT::f32) 5050 LC = RTLIB::SINTTOFP_I64_F32; 5051 else { 5052 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 5053 LC = RTLIB::SINTTOFP_I64_F64; 5054 } 5055 5056 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 5057 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5058 SDOperand UnusedHiPart; 5059 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned, 5060 UnusedHiPart); 5061} 5062 5063/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5064/// INT_TO_FP operation of the specified operand when the target requests that 5065/// we expand it. At this point, we know that the result and operand types are 5066/// legal for the target. 5067SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5068 SDOperand Op0, 5069 MVT::ValueType DestVT) { 5070 if (Op0.getValueType() == MVT::i32) { 5071 // simple 32-bit [signed|unsigned] integer to float/double expansion 5072 5073 // get the stack frame index of a 8 byte buffer, pessimistically aligned 5074 MachineFunction &MF = DAG.getMachineFunction(); 5075 const Type *F64Type = MVT::getTypeForValueType(MVT::f64); 5076 unsigned StackAlign = 5077 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type); 5078 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign); 5079 // get address of 8 byte buffer 5080 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5081 // word offset constant for Hi/Lo address computation 5082 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5083 // set up Hi and Lo (into buffer) address based on endian 5084 SDOperand Hi = StackSlot; 5085 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5086 if (TLI.isLittleEndian()) 5087 std::swap(Hi, Lo); 5088 5089 // if signed map to unsigned space 5090 SDOperand Op0Mapped; 5091 if (isSigned) { 5092 // constant used to invert sign bit (signed to unsigned mapping) 5093 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5094 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5095 } else { 5096 Op0Mapped = Op0; 5097 } 5098 // store the lo of the constructed double - based on integer input 5099 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 5100 Op0Mapped, Lo, NULL, 0); 5101 // initial hi portion of constructed double 5102 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5103 // store the hi of the constructed double - biased exponent 5104 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5105 // load the constructed double 5106 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5107 // FP constant to bias correct the final result 5108 SDOperand Bias = DAG.getConstantFP(isSigned ? 5109 BitsToDouble(0x4330000080000000ULL) 5110 : BitsToDouble(0x4330000000000000ULL), 5111 MVT::f64); 5112 // subtract the bias 5113 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5114 // final result 5115 SDOperand Result; 5116 // handle final rounding 5117 if (DestVT == MVT::f64) { 5118 // do nothing 5119 Result = Sub; 5120 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) { 5121 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub); 5122 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) { 5123 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5124 } 5125 return Result; 5126 } 5127 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5128 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5129 5130 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0, 5131 DAG.getConstant(0, Op0.getValueType()), 5132 ISD::SETLT); 5133 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4); 5134 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5135 SignSet, Four, Zero); 5136 5137 // If the sign bit of the integer is set, the large number will be treated 5138 // as a negative number. To counteract this, the dynamic code adds an 5139 // offset depending on the data type. 5140 uint64_t FF; 5141 switch (Op0.getValueType()) { 5142 default: assert(0 && "Unsupported integer type!"); 5143 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5144 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5145 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5146 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5147 } 5148 if (TLI.isLittleEndian()) FF <<= 32; 5149 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5150 5151 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5152 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5153 SDOperand FudgeInReg; 5154 if (DestVT == MVT::f32) 5155 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 5156 else { 5157 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5158 DAG.getEntryNode(), CPIdx, 5159 NULL, 0, MVT::f32)); 5160 } 5161 5162 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5163} 5164 5165/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5166/// *INT_TO_FP operation of the specified operand when the target requests that 5167/// we promote it. At this point, we know that the result and operand types are 5168/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5169/// operation that takes a larger input. 5170SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5171 MVT::ValueType DestVT, 5172 bool isSigned) { 5173 // First step, figure out the appropriate *INT_TO_FP operation to use. 5174 MVT::ValueType NewInTy = LegalOp.getValueType(); 5175 5176 unsigned OpToUse = 0; 5177 5178 // Scan for the appropriate larger type to use. 5179 while (1) { 5180 NewInTy = (MVT::ValueType)(NewInTy+1); 5181 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!"); 5182 5183 // If the target supports SINT_TO_FP of this type, use it. 5184 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5185 default: break; 5186 case TargetLowering::Legal: 5187 if (!TLI.isTypeLegal(NewInTy)) 5188 break; // Can't use this datatype. 5189 // FALL THROUGH. 5190 case TargetLowering::Custom: 5191 OpToUse = ISD::SINT_TO_FP; 5192 break; 5193 } 5194 if (OpToUse) break; 5195 if (isSigned) continue; 5196 5197 // If the target supports UINT_TO_FP of this type, use it. 5198 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5199 default: break; 5200 case TargetLowering::Legal: 5201 if (!TLI.isTypeLegal(NewInTy)) 5202 break; // Can't use this datatype. 5203 // FALL THROUGH. 5204 case TargetLowering::Custom: 5205 OpToUse = ISD::UINT_TO_FP; 5206 break; 5207 } 5208 if (OpToUse) break; 5209 5210 // Otherwise, try a larger type. 5211 } 5212 5213 // Okay, we found the operation and type to use. Zero extend our input to the 5214 // desired type then run the operation on it. 5215 return DAG.getNode(OpToUse, DestVT, 5216 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5217 NewInTy, LegalOp)); 5218} 5219 5220/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5221/// FP_TO_*INT operation of the specified operand when the target requests that 5222/// we promote it. At this point, we know that the result and operand types are 5223/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5224/// operation that returns a larger result. 5225SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5226 MVT::ValueType DestVT, 5227 bool isSigned) { 5228 // First step, figure out the appropriate FP_TO*INT operation to use. 5229 MVT::ValueType NewOutTy = DestVT; 5230 5231 unsigned OpToUse = 0; 5232 5233 // Scan for the appropriate larger type to use. 5234 while (1) { 5235 NewOutTy = (MVT::ValueType)(NewOutTy+1); 5236 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!"); 5237 5238 // If the target supports FP_TO_SINT returning this type, use it. 5239 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5240 default: break; 5241 case TargetLowering::Legal: 5242 if (!TLI.isTypeLegal(NewOutTy)) 5243 break; // Can't use this datatype. 5244 // FALL THROUGH. 5245 case TargetLowering::Custom: 5246 OpToUse = ISD::FP_TO_SINT; 5247 break; 5248 } 5249 if (OpToUse) break; 5250 5251 // If the target supports FP_TO_UINT of this type, use it. 5252 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5253 default: break; 5254 case TargetLowering::Legal: 5255 if (!TLI.isTypeLegal(NewOutTy)) 5256 break; // Can't use this datatype. 5257 // FALL THROUGH. 5258 case TargetLowering::Custom: 5259 OpToUse = ISD::FP_TO_UINT; 5260 break; 5261 } 5262 if (OpToUse) break; 5263 5264 // Otherwise, try a larger type. 5265 } 5266 5267 5268 // Okay, we found the operation and type to use. 5269 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5270 5271 // If the operation produces an invalid type, it must be custom lowered. Use 5272 // the target lowering hooks to expand it. Just keep the low part of the 5273 // expanded operation, we know that we're truncating anyway. 5274 if (getTypeAction(NewOutTy) == Expand) { 5275 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0); 5276 assert(Operation.Val && "Didn't return anything"); 5277 } 5278 5279 // Truncate the result of the extended FP_TO_*INT operation to the desired 5280 // size. 5281 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5282} 5283 5284/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5285/// 5286SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5287 MVT::ValueType VT = Op.getValueType(); 5288 MVT::ValueType SHVT = TLI.getShiftAmountTy(); 5289 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5290 switch (VT) { 5291 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5292 case MVT::i16: 5293 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5294 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5295 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5296 case MVT::i32: 5297 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5298 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5299 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5300 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5301 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5302 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5303 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5304 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5305 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5306 case MVT::i64: 5307 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5308 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5309 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5310 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5311 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5312 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5313 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5314 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5315 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5316 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5317 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5318 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5319 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5320 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5321 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5322 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5323 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5324 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5325 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5326 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5327 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5328 } 5329} 5330 5331/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5332/// 5333SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5334 switch (Opc) { 5335 default: assert(0 && "Cannot expand this yet!"); 5336 case ISD::CTPOP: { 5337 static const uint64_t mask[6] = { 5338 0x5555555555555555ULL, 0x3333333333333333ULL, 5339 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5340 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5341 }; 5342 MVT::ValueType VT = Op.getValueType(); 5343 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5344 unsigned len = MVT::getSizeInBits(VT); 5345 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5346 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5347 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5348 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5349 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5350 DAG.getNode(ISD::AND, VT, 5351 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5352 } 5353 return Op; 5354 } 5355 case ISD::CTLZ: { 5356 // for now, we do this: 5357 // x = x | (x >> 1); 5358 // x = x | (x >> 2); 5359 // ... 5360 // x = x | (x >>16); 5361 // x = x | (x >>32); // for 64-bit input 5362 // return popcount(~x); 5363 // 5364 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5365 MVT::ValueType VT = Op.getValueType(); 5366 MVT::ValueType ShVT = TLI.getShiftAmountTy(); 5367 unsigned len = MVT::getSizeInBits(VT); 5368 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5369 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5370 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5371 } 5372 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5373 return DAG.getNode(ISD::CTPOP, VT, Op); 5374 } 5375 case ISD::CTTZ: { 5376 // for now, we use: { return popcount(~x & (x - 1)); } 5377 // unless the target has ctlz but not ctpop, in which case we use: 5378 // { return 32 - nlz(~x & (x-1)); } 5379 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5380 MVT::ValueType VT = Op.getValueType(); 5381 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5382 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5383 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5384 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5385 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5386 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5387 TLI.isOperationLegal(ISD::CTLZ, VT)) 5388 return DAG.getNode(ISD::SUB, VT, 5389 DAG.getConstant(MVT::getSizeInBits(VT), VT), 5390 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5391 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5392 } 5393 } 5394} 5395 5396/// ExpandOp - Expand the specified SDOperand into its two component pieces 5397/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5398/// LegalizeNodes map is filled in for any results that are not expanded, the 5399/// ExpandedNodes map is filled in for any results that are expanded, and the 5400/// Lo/Hi values are returned. 5401void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5402 MVT::ValueType VT = Op.getValueType(); 5403 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT); 5404 SDNode *Node = Op.Val; 5405 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5406 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) || 5407 MVT::isVector(VT)) && 5408 "Cannot expand to FP value or to larger int value!"); 5409 5410 // See if we already expanded it. 5411 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5412 = ExpandedNodes.find(Op); 5413 if (I != ExpandedNodes.end()) { 5414 Lo = I->second.first; 5415 Hi = I->second.second; 5416 return; 5417 } 5418 5419 switch (Node->getOpcode()) { 5420 case ISD::CopyFromReg: 5421 assert(0 && "CopyFromReg must be legal!"); 5422 case ISD::FP_ROUND_INREG: 5423 if (VT == MVT::ppcf128 && 5424 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5425 TargetLowering::Custom) { 5426 SDOperand SrcLo, SrcHi, Src; 5427 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5428 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5429 SDOperand Result = TLI.LowerOperation( 5430 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5431 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5432 Lo = Result.Val->getOperand(0); 5433 Hi = Result.Val->getOperand(1); 5434 break; 5435 } 5436 // fall through 5437 default: 5438#ifndef NDEBUG 5439 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5440#endif 5441 assert(0 && "Do not know how to expand this operator!"); 5442 abort(); 5443 case ISD::EXTRACT_VECTOR_ELT: 5444 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5445 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5446 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5447 return ExpandOp(Lo, Lo, Hi); 5448 case ISD::UNDEF: 5449 NVT = TLI.getTypeToExpandTo(VT); 5450 Lo = DAG.getNode(ISD::UNDEF, NVT); 5451 Hi = DAG.getNode(ISD::UNDEF, NVT); 5452 break; 5453 case ISD::Constant: { 5454 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue(); 5455 Lo = DAG.getConstant(Cst, NVT); 5456 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT); 5457 break; 5458 } 5459 case ISD::ConstantFP: { 5460 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5461 if (CFP->getValueType(0) == MVT::ppcf128) { 5462 APInt api = CFP->getValueAPF().convertToAPInt(); 5463 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5464 MVT::f64); 5465 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5466 MVT::f64); 5467 break; 5468 } 5469 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5470 if (getTypeAction(Lo.getValueType()) == Expand) 5471 ExpandOp(Lo, Lo, Hi); 5472 break; 5473 } 5474 case ISD::BUILD_PAIR: 5475 // Return the operands. 5476 Lo = Node->getOperand(0); 5477 Hi = Node->getOperand(1); 5478 break; 5479 5480 case ISD::MERGE_VALUES: 5481 if (Node->getNumValues() == 1) { 5482 ExpandOp(Op.getOperand(0), Lo, Hi); 5483 break; 5484 } 5485 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5486 assert(Op.ResNo == 0 && Node->getNumValues() == 2 && 5487 Op.getValue(1).getValueType() == MVT::Other && 5488 "unhandled MERGE_VALUES"); 5489 ExpandOp(Op.getOperand(0), Lo, Hi); 5490 // Remember that we legalized the chain. 5491 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5492 break; 5493 5494 case ISD::SIGN_EXTEND_INREG: 5495 ExpandOp(Node->getOperand(0), Lo, Hi); 5496 // sext_inreg the low part if needed. 5497 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5498 5499 // The high part gets the sign extension from the lo-part. This handles 5500 // things like sextinreg V:i64 from i8. 5501 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5502 DAG.getConstant(MVT::getSizeInBits(NVT)-1, 5503 TLI.getShiftAmountTy())); 5504 break; 5505 5506 case ISD::BSWAP: { 5507 ExpandOp(Node->getOperand(0), Lo, Hi); 5508 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5509 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5510 Lo = TempLo; 5511 break; 5512 } 5513 5514 case ISD::CTPOP: 5515 ExpandOp(Node->getOperand(0), Lo, Hi); 5516 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5517 DAG.getNode(ISD::CTPOP, NVT, Lo), 5518 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5519 Hi = DAG.getConstant(0, NVT); 5520 break; 5521 5522 case ISD::CTLZ: { 5523 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5524 ExpandOp(Node->getOperand(0), Lo, Hi); 5525 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5526 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5527 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC, 5528 ISD::SETNE); 5529 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5530 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5531 5532 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5533 Hi = DAG.getConstant(0, NVT); 5534 break; 5535 } 5536 5537 case ISD::CTTZ: { 5538 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5539 ExpandOp(Node->getOperand(0), Lo, Hi); 5540 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT); 5541 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5542 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC, 5543 ISD::SETNE); 5544 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5545 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5546 5547 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5548 Hi = DAG.getConstant(0, NVT); 5549 break; 5550 } 5551 5552 case ISD::VAARG: { 5553 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5554 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5555 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5556 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5557 5558 // Remember that we legalized the chain. 5559 Hi = LegalizeOp(Hi); 5560 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5561 if (!TLI.isLittleEndian()) 5562 std::swap(Lo, Hi); 5563 break; 5564 } 5565 5566 case ISD::LOAD: { 5567 LoadSDNode *LD = cast<LoadSDNode>(Node); 5568 SDOperand Ch = LD->getChain(); // Legalize the chain. 5569 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5570 ISD::LoadExtType ExtType = LD->getExtensionType(); 5571 int SVOffset = LD->getSrcValueOffset(); 5572 unsigned Alignment = LD->getAlignment(); 5573 bool isVolatile = LD->isVolatile(); 5574 5575 if (ExtType == ISD::NON_EXTLOAD) { 5576 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5577 isVolatile, Alignment); 5578 if (VT == MVT::f32 || VT == MVT::f64) { 5579 // f32->i32 or f64->i64 one to one expansion. 5580 // Remember that we legalized the chain. 5581 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5582 // Recursively expand the new load. 5583 if (getTypeAction(NVT) == Expand) 5584 ExpandOp(Lo, Lo, Hi); 5585 break; 5586 } 5587 5588 // Increment the pointer to the other half. 5589 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8; 5590 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5591 getIntPtrConstant(IncrementSize)); 5592 SVOffset += IncrementSize; 5593 Alignment = MinAlign(Alignment, IncrementSize); 5594 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5595 isVolatile, Alignment); 5596 5597 // Build a factor node to remember that this load is independent of the 5598 // other one. 5599 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5600 Hi.getValue(1)); 5601 5602 // Remember that we legalized the chain. 5603 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5604 if (!TLI.isLittleEndian()) 5605 std::swap(Lo, Hi); 5606 } else { 5607 MVT::ValueType EVT = LD->getLoadedVT(); 5608 5609 if ((VT == MVT::f64 && EVT == MVT::f32) || 5610 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 5611 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5612 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5613 SVOffset, isVolatile, Alignment); 5614 // Remember that we legalized the chain. 5615 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 5616 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 5617 break; 5618 } 5619 5620 if (EVT == NVT) 5621 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 5622 SVOffset, isVolatile, Alignment); 5623 else 5624 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 5625 SVOffset, EVT, isVolatile, 5626 Alignment); 5627 5628 // Remember that we legalized the chain. 5629 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5630 5631 if (ExtType == ISD::SEXTLOAD) { 5632 // The high part is obtained by SRA'ing all but one of the bits of the 5633 // lo part. 5634 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5635 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5636 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5637 } else if (ExtType == ISD::ZEXTLOAD) { 5638 // The high part is just a zero. 5639 Hi = DAG.getConstant(0, NVT); 5640 } else /* if (ExtType == ISD::EXTLOAD) */ { 5641 // The high part is undefined. 5642 Hi = DAG.getNode(ISD::UNDEF, NVT); 5643 } 5644 } 5645 break; 5646 } 5647 case ISD::AND: 5648 case ISD::OR: 5649 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 5650 SDOperand LL, LH, RL, RH; 5651 ExpandOp(Node->getOperand(0), LL, LH); 5652 ExpandOp(Node->getOperand(1), RL, RH); 5653 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 5654 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 5655 break; 5656 } 5657 case ISD::SELECT: { 5658 SDOperand LL, LH, RL, RH; 5659 ExpandOp(Node->getOperand(1), LL, LH); 5660 ExpandOp(Node->getOperand(2), RL, RH); 5661 if (getTypeAction(NVT) == Expand) 5662 NVT = TLI.getTypeToExpandTo(NVT); 5663 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 5664 if (VT != MVT::f32) 5665 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 5666 break; 5667 } 5668 case ISD::SELECT_CC: { 5669 SDOperand TL, TH, FL, FH; 5670 ExpandOp(Node->getOperand(2), TL, TH); 5671 ExpandOp(Node->getOperand(3), FL, FH); 5672 if (getTypeAction(NVT) == Expand) 5673 NVT = TLI.getTypeToExpandTo(NVT); 5674 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5675 Node->getOperand(1), TL, FL, Node->getOperand(4)); 5676 if (VT != MVT::f32) 5677 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 5678 Node->getOperand(1), TH, FH, Node->getOperand(4)); 5679 break; 5680 } 5681 case ISD::ANY_EXTEND: 5682 // The low part is any extension of the input (which degenerates to a copy). 5683 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 5684 // The high part is undefined. 5685 Hi = DAG.getNode(ISD::UNDEF, NVT); 5686 break; 5687 case ISD::SIGN_EXTEND: { 5688 // The low part is just a sign extension of the input (which degenerates to 5689 // a copy). 5690 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 5691 5692 // The high part is obtained by SRA'ing all but one of the bits of the lo 5693 // part. 5694 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); 5695 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5696 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 5697 break; 5698 } 5699 case ISD::ZERO_EXTEND: 5700 // The low part is just a zero extension of the input (which degenerates to 5701 // a copy). 5702 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 5703 5704 // The high part is just a zero. 5705 Hi = DAG.getConstant(0, NVT); 5706 break; 5707 5708 case ISD::TRUNCATE: { 5709 // The input value must be larger than this value. Expand *it*. 5710 SDOperand NewLo; 5711 ExpandOp(Node->getOperand(0), NewLo, Hi); 5712 5713 // The low part is now either the right size, or it is closer. If not the 5714 // right size, make an illegal truncate so we recursively expand it. 5715 if (NewLo.getValueType() != Node->getValueType(0)) 5716 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 5717 ExpandOp(NewLo, Lo, Hi); 5718 break; 5719 } 5720 5721 case ISD::BIT_CONVERT: { 5722 SDOperand Tmp; 5723 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 5724 // If the target wants to, allow it to lower this itself. 5725 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5726 case Expand: assert(0 && "cannot expand FP!"); 5727 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 5728 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 5729 } 5730 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 5731 } 5732 5733 // f32 / f64 must be expanded to i32 / i64. 5734 if (VT == MVT::f32 || VT == MVT::f64) { 5735 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 5736 if (getTypeAction(NVT) == Expand) 5737 ExpandOp(Lo, Lo, Hi); 5738 break; 5739 } 5740 5741 // If source operand will be expanded to the same type as VT, i.e. 5742 // i64 <- f64, i32 <- f32, expand the source operand instead. 5743 MVT::ValueType VT0 = Node->getOperand(0).getValueType(); 5744 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 5745 ExpandOp(Node->getOperand(0), Lo, Hi); 5746 break; 5747 } 5748 5749 // Turn this into a load/store pair by default. 5750 if (Tmp.Val == 0) 5751 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0)); 5752 5753 ExpandOp(Tmp, Lo, Hi); 5754 break; 5755 } 5756 5757 case ISD::READCYCLECOUNTER: { 5758 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 5759 TargetLowering::Custom && 5760 "Must custom expand ReadCycleCounter"); 5761 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 5762 assert(Tmp.Val && "Node must be custom expanded!"); 5763 ExpandOp(Tmp.getValue(0), Lo, Hi); 5764 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 5765 LegalizeOp(Tmp.getValue(1))); 5766 break; 5767 } 5768 5769 // These operators cannot be expanded directly, emit them as calls to 5770 // library functions. 5771 case ISD::FP_TO_SINT: { 5772 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 5773 SDOperand Op; 5774 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5775 case Expand: assert(0 && "cannot expand FP!"); 5776 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5777 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5778 } 5779 5780 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 5781 5782 // Now that the custom expander is done, expand the result, which is still 5783 // VT. 5784 if (Op.Val) { 5785 ExpandOp(Op, Lo, Hi); 5786 break; 5787 } 5788 } 5789 5790 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5791 if (Node->getOperand(0).getValueType() == MVT::f32) 5792 LC = RTLIB::FPTOSINT_F32_I64; 5793 else if (Node->getOperand(0).getValueType() == MVT::f64) 5794 LC = RTLIB::FPTOSINT_F64_I64; 5795 else if (Node->getOperand(0).getValueType() == MVT::f80) 5796 LC = RTLIB::FPTOSINT_F80_I64; 5797 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 5798 LC = RTLIB::FPTOSINT_PPCF128_I64; 5799 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5800 false/*sign irrelevant*/, Hi); 5801 break; 5802 } 5803 5804 case ISD::FP_TO_UINT: { 5805 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 5806 SDOperand Op; 5807 switch (getTypeAction(Node->getOperand(0).getValueType())) { 5808 case Expand: assert(0 && "cannot expand FP!"); 5809 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 5810 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 5811 } 5812 5813 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 5814 5815 // Now that the custom expander is done, expand the result. 5816 if (Op.Val) { 5817 ExpandOp(Op, Lo, Hi); 5818 break; 5819 } 5820 } 5821 5822 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 5823 if (Node->getOperand(0).getValueType() == MVT::f32) 5824 LC = RTLIB::FPTOUINT_F32_I64; 5825 else if (Node->getOperand(0).getValueType() == MVT::f64) 5826 LC = RTLIB::FPTOUINT_F64_I64; 5827 else if (Node->getOperand(0).getValueType() == MVT::f80) 5828 LC = RTLIB::FPTOUINT_F80_I64; 5829 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 5830 LC = RTLIB::FPTOUINT_PPCF128_I64; 5831 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, 5832 false/*sign irrelevant*/, Hi); 5833 break; 5834 } 5835 5836 case ISD::SHL: { 5837 // If the target wants custom lowering, do so. 5838 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5839 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 5840 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 5841 Op = TLI.LowerOperation(Op, DAG); 5842 if (Op.Val) { 5843 // Now that the custom expander is done, expand the result, which is 5844 // still VT. 5845 ExpandOp(Op, Lo, Hi); 5846 break; 5847 } 5848 } 5849 5850 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 5851 // this X << 1 as X+X. 5852 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 5853 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 5854 TLI.isOperationLegal(ISD::ADDE, NVT)) { 5855 SDOperand LoOps[2], HiOps[3]; 5856 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 5857 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 5858 LoOps[1] = LoOps[0]; 5859 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5860 5861 HiOps[1] = HiOps[0]; 5862 HiOps[2] = Lo.getValue(1); 5863 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5864 break; 5865 } 5866 } 5867 5868 // If we can emit an efficient shift operation, do so now. 5869 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5870 break; 5871 5872 // If this target supports SHL_PARTS, use it. 5873 TargetLowering::LegalizeAction Action = 5874 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 5875 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5876 Action == TargetLowering::Custom) { 5877 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5878 break; 5879 } 5880 5881 // Otherwise, emit a libcall. 5882 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node, 5883 false/*left shift=unsigned*/, Hi); 5884 break; 5885 } 5886 5887 case ISD::SRA: { 5888 // If the target wants custom lowering, do so. 5889 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5890 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 5891 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 5892 Op = TLI.LowerOperation(Op, DAG); 5893 if (Op.Val) { 5894 // Now that the custom expander is done, expand the result, which is 5895 // still VT. 5896 ExpandOp(Op, Lo, Hi); 5897 break; 5898 } 5899 } 5900 5901 // If we can emit an efficient shift operation, do so now. 5902 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5903 break; 5904 5905 // If this target supports SRA_PARTS, use it. 5906 TargetLowering::LegalizeAction Action = 5907 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 5908 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5909 Action == TargetLowering::Custom) { 5910 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5911 break; 5912 } 5913 5914 // Otherwise, emit a libcall. 5915 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node, 5916 true/*ashr is signed*/, Hi); 5917 break; 5918 } 5919 5920 case ISD::SRL: { 5921 // If the target wants custom lowering, do so. 5922 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 5923 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 5924 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 5925 Op = TLI.LowerOperation(Op, DAG); 5926 if (Op.Val) { 5927 // Now that the custom expander is done, expand the result, which is 5928 // still VT. 5929 ExpandOp(Op, Lo, Hi); 5930 break; 5931 } 5932 } 5933 5934 // If we can emit an efficient shift operation, do so now. 5935 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 5936 break; 5937 5938 // If this target supports SRL_PARTS, use it. 5939 TargetLowering::LegalizeAction Action = 5940 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 5941 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 5942 Action == TargetLowering::Custom) { 5943 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 5944 break; 5945 } 5946 5947 // Otherwise, emit a libcall. 5948 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node, 5949 false/*lshr is unsigned*/, Hi); 5950 break; 5951 } 5952 5953 case ISD::ADD: 5954 case ISD::SUB: { 5955 // If the target wants to custom expand this, let them. 5956 if (TLI.getOperationAction(Node->getOpcode(), VT) == 5957 TargetLowering::Custom) { 5958 Op = TLI.LowerOperation(Op, DAG); 5959 if (Op.Val) { 5960 ExpandOp(Op, Lo, Hi); 5961 break; 5962 } 5963 } 5964 5965 // Expand the subcomponents. 5966 SDOperand LHSL, LHSH, RHSL, RHSH; 5967 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5968 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5969 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5970 SDOperand LoOps[2], HiOps[3]; 5971 LoOps[0] = LHSL; 5972 LoOps[1] = RHSL; 5973 HiOps[0] = LHSH; 5974 HiOps[1] = RHSH; 5975 if (Node->getOpcode() == ISD::ADD) { 5976 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5977 HiOps[2] = Lo.getValue(1); 5978 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 5979 } else { 5980 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 5981 HiOps[2] = Lo.getValue(1); 5982 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 5983 } 5984 break; 5985 } 5986 5987 case ISD::ADDC: 5988 case ISD::SUBC: { 5989 // Expand the subcomponents. 5990 SDOperand LHSL, LHSH, RHSL, RHSH; 5991 ExpandOp(Node->getOperand(0), LHSL, LHSH); 5992 ExpandOp(Node->getOperand(1), RHSL, RHSH); 5993 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 5994 SDOperand LoOps[2] = { LHSL, RHSL }; 5995 SDOperand HiOps[3] = { LHSH, RHSH }; 5996 5997 if (Node->getOpcode() == ISD::ADDC) { 5998 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 5999 HiOps[2] = Lo.getValue(1); 6000 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6001 } else { 6002 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6003 HiOps[2] = Lo.getValue(1); 6004 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6005 } 6006 // Remember that we legalized the flag. 6007 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6008 break; 6009 } 6010 case ISD::ADDE: 6011 case ISD::SUBE: { 6012 // Expand the subcomponents. 6013 SDOperand LHSL, LHSH, RHSL, RHSH; 6014 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6015 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6016 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6017 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 6018 SDOperand HiOps[3] = { LHSH, RHSH }; 6019 6020 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6021 HiOps[2] = Lo.getValue(1); 6022 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6023 6024 // Remember that we legalized the flag. 6025 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6026 break; 6027 } 6028 case ISD::MUL: { 6029 // If the target wants to custom expand this, let them. 6030 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6031 SDOperand New = TLI.LowerOperation(Op, DAG); 6032 if (New.Val) { 6033 ExpandOp(New, Lo, Hi); 6034 break; 6035 } 6036 } 6037 6038 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6039 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6040 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6041 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6042 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6043 SDOperand LL, LH, RL, RH; 6044 ExpandOp(Node->getOperand(0), LL, LH); 6045 ExpandOp(Node->getOperand(1), RL, RH); 6046 unsigned BitSize = MVT::getSizeInBits(RH.getValueType()); 6047 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6048 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6049 // FIXME: generalize this to handle other bit sizes 6050 if (LHSSB == 32 && RHSSB == 32 && 6051 DAG.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) && 6052 DAG.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) { 6053 // The inputs are both zero-extended. 6054 if (HasUMUL_LOHI) { 6055 // We can emit a umul_lohi. 6056 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6057 Hi = SDOperand(Lo.Val, 1); 6058 break; 6059 } 6060 if (HasMULHU) { 6061 // We can emit a mulhu+mul. 6062 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6063 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6064 break; 6065 } 6066 } 6067 if (LHSSB > BitSize && RHSSB > BitSize) { 6068 // The input values are both sign-extended. 6069 if (HasSMUL_LOHI) { 6070 // We can emit a smul_lohi. 6071 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6072 Hi = SDOperand(Lo.Val, 1); 6073 break; 6074 } 6075 if (HasMULHS) { 6076 // We can emit a mulhs+mul. 6077 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6078 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6079 break; 6080 } 6081 } 6082 if (HasUMUL_LOHI) { 6083 // Lo,Hi = umul LHS, RHS. 6084 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6085 DAG.getVTList(NVT, NVT), LL, RL); 6086 Lo = UMulLOHI; 6087 Hi = UMulLOHI.getValue(1); 6088 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6089 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6090 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6091 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6092 break; 6093 } 6094 if (HasMULHU) { 6095 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6096 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6097 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6098 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6099 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6100 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6101 break; 6102 } 6103 } 6104 6105 // If nothing else, we can make a libcall. 6106 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node, 6107 false/*sign irrelevant*/, Hi); 6108 break; 6109 } 6110 case ISD::SDIV: 6111 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi); 6112 break; 6113 case ISD::UDIV: 6114 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi); 6115 break; 6116 case ISD::SREM: 6117 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi); 6118 break; 6119 case ISD::UREM: 6120 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi); 6121 break; 6122 6123 case ISD::FADD: 6124 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32, 6125 RTLIB::ADD_F64, 6126 RTLIB::ADD_F80, 6127 RTLIB::ADD_PPCF128)), 6128 Node, false, Hi); 6129 break; 6130 case ISD::FSUB: 6131 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32, 6132 RTLIB::SUB_F64, 6133 RTLIB::SUB_F80, 6134 RTLIB::SUB_PPCF128)), 6135 Node, false, Hi); 6136 break; 6137 case ISD::FMUL: 6138 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32, 6139 RTLIB::MUL_F64, 6140 RTLIB::MUL_F80, 6141 RTLIB::MUL_PPCF128)), 6142 Node, false, Hi); 6143 break; 6144 case ISD::FDIV: 6145 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32, 6146 RTLIB::DIV_F64, 6147 RTLIB::DIV_F80, 6148 RTLIB::DIV_PPCF128)), 6149 Node, false, Hi); 6150 break; 6151 case ISD::FP_EXTEND: 6152 if (VT == MVT::ppcf128) { 6153 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6154 Node->getOperand(0).getValueType()==MVT::f64); 6155 const uint64_t zero = 0; 6156 if (Node->getOperand(0).getValueType()==MVT::f32) 6157 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6158 else 6159 Hi = Node->getOperand(0); 6160 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6161 break; 6162 } 6163 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi); 6164 break; 6165 case ISD::FP_ROUND: 6166 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi); 6167 break; 6168 case ISD::FPOWI: 6169 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32, 6170 RTLIB::POWI_F64, 6171 RTLIB::POWI_F80, 6172 RTLIB::POWI_PPCF128)), 6173 Node, false, Hi); 6174 break; 6175 case ISD::FSQRT: 6176 case ISD::FSIN: 6177 case ISD::FCOS: { 6178 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6179 switch(Node->getOpcode()) { 6180 case ISD::FSQRT: 6181 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6182 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6183 break; 6184 case ISD::FSIN: 6185 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6186 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6187 break; 6188 case ISD::FCOS: 6189 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6190 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6191 break; 6192 default: assert(0 && "Unreachable!"); 6193 } 6194 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi); 6195 break; 6196 } 6197 case ISD::FABS: { 6198 if (VT == MVT::ppcf128) { 6199 SDOperand Tmp; 6200 ExpandOp(Node->getOperand(0), Lo, Tmp); 6201 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6202 // lo = hi==fabs(hi) ? lo : -lo; 6203 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6204 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6205 DAG.getCondCode(ISD::SETEQ)); 6206 break; 6207 } 6208 SDOperand Mask = (VT == MVT::f64) 6209 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6210 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6211 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6212 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6213 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6214 if (getTypeAction(NVT) == Expand) 6215 ExpandOp(Lo, Lo, Hi); 6216 break; 6217 } 6218 case ISD::FNEG: { 6219 if (VT == MVT::ppcf128) { 6220 ExpandOp(Node->getOperand(0), Lo, Hi); 6221 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6222 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6223 break; 6224 } 6225 SDOperand Mask = (VT == MVT::f64) 6226 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6227 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6228 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6229 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6230 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6231 if (getTypeAction(NVT) == Expand) 6232 ExpandOp(Lo, Lo, Hi); 6233 break; 6234 } 6235 case ISD::FCOPYSIGN: { 6236 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6237 if (getTypeAction(NVT) == Expand) 6238 ExpandOp(Lo, Lo, Hi); 6239 break; 6240 } 6241 case ISD::SINT_TO_FP: 6242 case ISD::UINT_TO_FP: { 6243 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6244 MVT::ValueType SrcVT = Node->getOperand(0).getValueType(); 6245 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) { 6246 static uint64_t zero = 0; 6247 if (isSigned) { 6248 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6249 Node->getOperand(0))); 6250 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6251 } else { 6252 static uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6253 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6254 Node->getOperand(0))); 6255 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6256 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6257 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6258 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6259 DAG.getConstant(0, MVT::i32), 6260 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6261 DAG.getConstantFP( 6262 APFloat(APInt(128, 2, TwoE32)), 6263 MVT::ppcf128)), 6264 Hi, 6265 DAG.getCondCode(ISD::SETLT)), 6266 Lo, Hi); 6267 } 6268 break; 6269 } 6270 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6271 // si64->ppcf128 done by libcall, below 6272 static uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6273 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6274 Lo, Hi); 6275 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6276 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6277 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6278 DAG.getConstant(0, MVT::i64), 6279 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6280 DAG.getConstantFP( 6281 APFloat(APInt(128, 2, TwoE64)), 6282 MVT::ppcf128)), 6283 Hi, 6284 DAG.getCondCode(ISD::SETLT)), 6285 Lo, Hi); 6286 break; 6287 } 6288 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6289 if (Node->getOperand(0).getValueType() == MVT::i64) { 6290 if (VT == MVT::f32) 6291 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32; 6292 else if (VT == MVT::f64) 6293 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64; 6294 else if (VT == MVT::f80) { 6295 assert(isSigned); 6296 LC = RTLIB::SINTTOFP_I64_F80; 6297 } 6298 else if (VT == MVT::ppcf128) { 6299 assert(isSigned); 6300 LC = RTLIB::SINTTOFP_I64_PPCF128; 6301 } 6302 } else { 6303 if (VT == MVT::f32) 6304 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 6305 else 6306 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 6307 } 6308 6309 // Promote the operand if needed. 6310 if (getTypeAction(SrcVT) == Promote) { 6311 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6312 Tmp = isSigned 6313 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6314 DAG.getValueType(SrcVT)) 6315 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6316 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6317 } 6318 6319 const char *LibCall = TLI.getLibcallName(LC); 6320 if (LibCall) 6321 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi); 6322 else { 6323 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6324 Node->getOperand(0)); 6325 if (getTypeAction(Lo.getValueType()) == Expand) 6326 ExpandOp(Lo, Lo, Hi); 6327 } 6328 break; 6329 } 6330 } 6331 6332 // Make sure the resultant values have been legalized themselves, unless this 6333 // is a type that requires multi-step expansion. 6334 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6335 Lo = LegalizeOp(Lo); 6336 if (Hi.Val) 6337 // Don't legalize the high part if it is expanded to a single node. 6338 Hi = LegalizeOp(Hi); 6339 } 6340 6341 // Remember in a map if the values will be reused later. 6342 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6343 assert(isNew && "Value already expanded?!?"); 6344} 6345 6346/// SplitVectorOp - Given an operand of vector type, break it down into 6347/// two smaller values, still of vector type. 6348void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6349 SDOperand &Hi) { 6350 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!"); 6351 SDNode *Node = Op.Val; 6352 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType()); 6353 assert(NumElements > 1 && "Cannot split a single element vector!"); 6354 6355 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType()); 6356 6357 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6358 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6359 6360 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo); 6361 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi); 6362 6363 // See if we already split it. 6364 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6365 = SplitNodes.find(Op); 6366 if (I != SplitNodes.end()) { 6367 Lo = I->second.first; 6368 Hi = I->second.second; 6369 return; 6370 } 6371 6372 switch (Node->getOpcode()) { 6373 default: 6374#ifndef NDEBUG 6375 Node->dump(&DAG); 6376#endif 6377 assert(0 && "Unhandled operation in SplitVectorOp!"); 6378 case ISD::UNDEF: 6379 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6380 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6381 break; 6382 case ISD::BUILD_PAIR: 6383 Lo = Node->getOperand(0); 6384 Hi = Node->getOperand(1); 6385 break; 6386 case ISD::INSERT_VECTOR_ELT: { 6387 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6388 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue(); 6389 SDOperand ScalarOp = Node->getOperand(1); 6390 if (Index < NewNumElts_Lo) 6391 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6392 DAG.getConstant(Index, TLI.getPointerTy())); 6393 else 6394 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6395 DAG.getConstant(Index - NewNumElts_Lo, 6396 TLI.getPointerTy())); 6397 break; 6398 } 6399 case ISD::VECTOR_SHUFFLE: { 6400 // Build the low part. 6401 SDOperand Mask = Node->getOperand(2); 6402 SmallVector<SDOperand, 8> Ops; 6403 MVT::ValueType PtrVT = TLI.getPointerTy(); 6404 6405 // Insert all of the elements from the input that are needed. We use 6406 // buildvector of extractelement here because the input vectors will have 6407 // to be legalized, so this makes the code simpler. 6408 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6409 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 6410 SDOperand InVec = Node->getOperand(0); 6411 if (Idx >= NumElements) { 6412 InVec = Node->getOperand(1); 6413 Idx -= NumElements; 6414 } 6415 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6416 DAG.getConstant(Idx, PtrVT))); 6417 } 6418 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6419 Ops.clear(); 6420 6421 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6422 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue(); 6423 SDOperand InVec = Node->getOperand(0); 6424 if (Idx >= NumElements) { 6425 InVec = Node->getOperand(1); 6426 Idx -= NumElements; 6427 } 6428 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6429 DAG.getConstant(Idx, PtrVT))); 6430 } 6431 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6432 break; 6433 } 6434 case ISD::BUILD_VECTOR: { 6435 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6436 Node->op_begin()+NewNumElts_Lo); 6437 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6438 6439 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6440 Node->op_end()); 6441 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6442 break; 6443 } 6444 case ISD::CONCAT_VECTORS: { 6445 // FIXME: Handle non-power-of-two vectors? 6446 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6447 if (NewNumSubvectors == 1) { 6448 Lo = Node->getOperand(0); 6449 Hi = Node->getOperand(1); 6450 } else { 6451 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6452 Node->op_begin()+NewNumSubvectors); 6453 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6454 6455 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6456 Node->op_end()); 6457 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6458 } 6459 break; 6460 } 6461 case ISD::SELECT: { 6462 SDOperand Cond = Node->getOperand(0); 6463 6464 SDOperand LL, LH, RL, RH; 6465 SplitVectorOp(Node->getOperand(1), LL, LH); 6466 SplitVectorOp(Node->getOperand(2), RL, RH); 6467 6468 if (MVT::isVector(Cond.getValueType())) { 6469 // Handle a vector merge. 6470 SDOperand CL, CH; 6471 SplitVectorOp(Cond, CL, CH); 6472 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6473 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6474 } else { 6475 // Handle a simple select with vector operands. 6476 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6477 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6478 } 6479 break; 6480 } 6481 case ISD::ADD: 6482 case ISD::SUB: 6483 case ISD::MUL: 6484 case ISD::FADD: 6485 case ISD::FSUB: 6486 case ISD::FMUL: 6487 case ISD::SDIV: 6488 case ISD::UDIV: 6489 case ISD::FDIV: 6490 case ISD::FPOW: 6491 case ISD::AND: 6492 case ISD::OR: 6493 case ISD::XOR: 6494 case ISD::UREM: 6495 case ISD::SREM: 6496 case ISD::FREM: { 6497 SDOperand LL, LH, RL, RH; 6498 SplitVectorOp(Node->getOperand(0), LL, LH); 6499 SplitVectorOp(Node->getOperand(1), RL, RH); 6500 6501 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 6502 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 6503 break; 6504 } 6505 case ISD::FPOWI: { 6506 SDOperand L, H; 6507 SplitVectorOp(Node->getOperand(0), L, H); 6508 6509 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 6510 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 6511 break; 6512 } 6513 case ISD::CTTZ: 6514 case ISD::CTLZ: 6515 case ISD::CTPOP: 6516 case ISD::FNEG: 6517 case ISD::FABS: 6518 case ISD::FSQRT: 6519 case ISD::FSIN: 6520 case ISD::FCOS: 6521 case ISD::FP_TO_SINT: 6522 case ISD::FP_TO_UINT: 6523 case ISD::SINT_TO_FP: 6524 case ISD::UINT_TO_FP: { 6525 SDOperand L, H; 6526 SplitVectorOp(Node->getOperand(0), L, H); 6527 6528 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 6529 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 6530 break; 6531 } 6532 case ISD::LOAD: { 6533 LoadSDNode *LD = cast<LoadSDNode>(Node); 6534 SDOperand Ch = LD->getChain(); 6535 SDOperand Ptr = LD->getBasePtr(); 6536 const Value *SV = LD->getSrcValue(); 6537 int SVOffset = LD->getSrcValueOffset(); 6538 unsigned Alignment = LD->getAlignment(); 6539 bool isVolatile = LD->isVolatile(); 6540 6541 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6542 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8; 6543 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6544 getIntPtrConstant(IncrementSize)); 6545 SVOffset += IncrementSize; 6546 Alignment = MinAlign(Alignment, IncrementSize); 6547 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6548 6549 // Build a factor node to remember that this load is independent of the 6550 // other one. 6551 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6552 Hi.getValue(1)); 6553 6554 // Remember that we legalized the chain. 6555 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6556 break; 6557 } 6558 case ISD::BIT_CONVERT: { 6559 // We know the result is a vector. The input may be either a vector or a 6560 // scalar value. 6561 SDOperand InOp = Node->getOperand(0); 6562 if (!MVT::isVector(InOp.getValueType()) || 6563 MVT::getVectorNumElements(InOp.getValueType()) == 1) { 6564 // The input is a scalar or single-element vector. 6565 // Lower to a store/load so that it can be split. 6566 // FIXME: this could be improved probably. 6567 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); 6568 6569 SDOperand St = DAG.getStore(DAG.getEntryNode(), 6570 InOp, Ptr, NULL, 0); 6571 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0); 6572 } 6573 // Split the vector and convert each of the pieces now. 6574 SplitVectorOp(InOp, Lo, Hi); 6575 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 6576 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 6577 break; 6578 } 6579 } 6580 6581 // Remember in a map if the values will be reused later. 6582 bool isNew = 6583 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 6584 assert(isNew && "Value already split?!?"); 6585} 6586 6587 6588/// ScalarizeVectorOp - Given an operand of single-element vector type 6589/// (e.g. v1f32), convert it into the equivalent operation that returns a 6590/// scalar (e.g. f32) value. 6591SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 6592 assert(MVT::isVector(Op.getValueType()) && 6593 "Bad ScalarizeVectorOp invocation!"); 6594 SDNode *Node = Op.Val; 6595 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType()); 6596 assert(MVT::getVectorNumElements(Op.getValueType()) == 1); 6597 6598 // See if we already scalarized it. 6599 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 6600 if (I != ScalarizedNodes.end()) return I->second; 6601 6602 SDOperand Result; 6603 switch (Node->getOpcode()) { 6604 default: 6605#ifndef NDEBUG 6606 Node->dump(&DAG); cerr << "\n"; 6607#endif 6608 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 6609 case ISD::ADD: 6610 case ISD::FADD: 6611 case ISD::SUB: 6612 case ISD::FSUB: 6613 case ISD::MUL: 6614 case ISD::FMUL: 6615 case ISD::SDIV: 6616 case ISD::UDIV: 6617 case ISD::FDIV: 6618 case ISD::SREM: 6619 case ISD::UREM: 6620 case ISD::FREM: 6621 case ISD::FPOW: 6622 case ISD::AND: 6623 case ISD::OR: 6624 case ISD::XOR: 6625 Result = DAG.getNode(Node->getOpcode(), 6626 NewVT, 6627 ScalarizeVectorOp(Node->getOperand(0)), 6628 ScalarizeVectorOp(Node->getOperand(1))); 6629 break; 6630 case ISD::FNEG: 6631 case ISD::FABS: 6632 case ISD::FSQRT: 6633 case ISD::FSIN: 6634 case ISD::FCOS: 6635 Result = DAG.getNode(Node->getOpcode(), 6636 NewVT, 6637 ScalarizeVectorOp(Node->getOperand(0))); 6638 break; 6639 case ISD::FPOWI: 6640 Result = DAG.getNode(Node->getOpcode(), 6641 NewVT, 6642 ScalarizeVectorOp(Node->getOperand(0)), 6643 Node->getOperand(1)); 6644 break; 6645 case ISD::LOAD: { 6646 LoadSDNode *LD = cast<LoadSDNode>(Node); 6647 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 6648 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 6649 6650 const Value *SV = LD->getSrcValue(); 6651 int SVOffset = LD->getSrcValueOffset(); 6652 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 6653 LD->isVolatile(), LD->getAlignment()); 6654 6655 // Remember that we legalized the chain. 6656 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 6657 break; 6658 } 6659 case ISD::BUILD_VECTOR: 6660 Result = Node->getOperand(0); 6661 break; 6662 case ISD::INSERT_VECTOR_ELT: 6663 // Returning the inserted scalar element. 6664 Result = Node->getOperand(1); 6665 break; 6666 case ISD::CONCAT_VECTORS: 6667 assert(Node->getOperand(0).getValueType() == NewVT && 6668 "Concat of non-legal vectors not yet supported!"); 6669 Result = Node->getOperand(0); 6670 break; 6671 case ISD::VECTOR_SHUFFLE: { 6672 // Figure out if the scalar is the LHS or RHS and return it. 6673 SDOperand EltNum = Node->getOperand(2).getOperand(0); 6674 if (cast<ConstantSDNode>(EltNum)->getValue()) 6675 Result = ScalarizeVectorOp(Node->getOperand(1)); 6676 else 6677 Result = ScalarizeVectorOp(Node->getOperand(0)); 6678 break; 6679 } 6680 case ISD::EXTRACT_SUBVECTOR: 6681 Result = Node->getOperand(0); 6682 assert(Result.getValueType() == NewVT); 6683 break; 6684 case ISD::BIT_CONVERT: 6685 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0)); 6686 break; 6687 case ISD::SELECT: 6688 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 6689 ScalarizeVectorOp(Op.getOperand(1)), 6690 ScalarizeVectorOp(Op.getOperand(2))); 6691 break; 6692 } 6693 6694 if (TLI.isTypeLegal(NewVT)) 6695 Result = LegalizeOp(Result); 6696 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 6697 assert(isNew && "Value already scalarized?"); 6698 return Result; 6699} 6700 6701 6702// SelectionDAG::Legalize - This is the entry point for the file. 6703// 6704void SelectionDAG::Legalize() { 6705 if (ViewLegalizeDAGs) viewGraph(); 6706 6707 /// run - This is the main entry point to this class. 6708 /// 6709 SelectionDAGLegalize(*this).LegalizeDAG(); 6710} 6711 6712