LegalizeDAG.cpp revision f9516208e57364ab1e7d8748af1f59a2ea5fb572
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetFrameInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/Target/TargetSubtarget.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/SmallPtrSet.h" 35#include <map> 36using namespace llvm; 37 38#ifndef NDEBUG 39static cl::opt<bool> 40ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 41 cl::desc("Pop up a window to show dags before legalize")); 42#else 43static const bool ViewLegalizeDAGs = 0; 44#endif 45 46//===----------------------------------------------------------------------===// 47/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 48/// hacks on it until the target machine can handle it. This involves 49/// eliminating value sizes the machine cannot handle (promoting small sizes to 50/// large sizes or splitting up large values into small values) as well as 51/// eliminating operations the machine cannot handle. 52/// 53/// This code also does a small amount of optimization and recognition of idioms 54/// as part of its processing. For example, if a target does not support a 55/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 56/// will attempt merge setcc and brc instructions into brcc's. 57/// 58namespace { 59class VISIBILITY_HIDDEN SelectionDAGLegalize { 60 TargetLowering &TLI; 61 SelectionDAG &DAG; 62 63 // Libcall insertion helpers. 64 65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 66 /// legalized. We use this to ensure that calls are properly serialized 67 /// against each other, including inserted libcalls. 68 SDOperand LastCALLSEQ_END; 69 70 /// IsLegalizingCall - This member is used *only* for purposes of providing 71 /// helpful assertions that a libcall isn't created while another call is 72 /// being legalized (which could lead to non-serialized call sequences). 73 bool IsLegalizingCall; 74 75 enum LegalizeAction { 76 Legal, // The target natively supports this operation. 77 Promote, // This operation should be executed in a larger type. 78 Expand // Try to expand this to other ops, otherwise use a libcall. 79 }; 80 81 /// ValueTypeActions - This is a bitvector that contains two bits for each 82 /// value type, where the two bits correspond to the LegalizeAction enum. 83 /// This can be queried with "getTypeAction(VT)". 84 TargetLowering::ValueTypeActionImpl ValueTypeActions; 85 86 /// LegalizedNodes - For nodes that are of legal width, and that have more 87 /// than one use, this map indicates what regularized operand to use. This 88 /// allows us to avoid legalizing the same thing more than once. 89 DenseMap<SDOperand, SDOperand> LegalizedNodes; 90 91 /// PromotedNodes - For nodes that are below legal width, and that have more 92 /// than one use, this map indicates what promoted value to use. This allows 93 /// us to avoid promoting the same thing more than once. 94 DenseMap<SDOperand, SDOperand> PromotedNodes; 95 96 /// ExpandedNodes - For nodes that need to be expanded this map indicates 97 /// which which operands are the expanded version of the input. This allows 98 /// us to avoid expanding the same node more than once. 99 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes; 100 101 /// SplitNodes - For vector nodes that need to be split, this map indicates 102 /// which which operands are the split version of the input. This allows us 103 /// to avoid splitting the same node more than once. 104 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes; 105 106 /// ScalarizedNodes - For nodes that need to be converted from vector types to 107 /// scalar types, this contains the mapping of ones we have already 108 /// processed to the result. 109 std::map<SDOperand, SDOperand> ScalarizedNodes; 110 111 void AddLegalizedOperand(SDOperand From, SDOperand To) { 112 LegalizedNodes.insert(std::make_pair(From, To)); 113 // If someone requests legalization of the new node, return itself. 114 if (From != To) 115 LegalizedNodes.insert(std::make_pair(To, To)); 116 } 117 void AddPromotedOperand(SDOperand From, SDOperand To) { 118 bool isNew = PromotedNodes.insert(std::make_pair(From, To)); 119 assert(isNew && "Got into the map somehow?"); 120 // If someone requests legalization of the new node, return itself. 121 LegalizedNodes.insert(std::make_pair(To, To)); 122 } 123 124public: 125 126 SelectionDAGLegalize(SelectionDAG &DAG); 127 128 /// getTypeAction - Return how we should legalize values of this type, either 129 /// it is already legal or we need to expand it into multiple registers of 130 /// smaller integer type, or we need to promote it to a larger type. 131 LegalizeAction getTypeAction(MVT VT) const { 132 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 133 } 134 135 /// isTypeLegal - Return true if this type is legal on this target. 136 /// 137 bool isTypeLegal(MVT VT) const { 138 return getTypeAction(VT) == Legal; 139 } 140 141 void LegalizeDAG(); 142 143private: 144 /// HandleOp - Legalize, Promote, or Expand the specified operand as 145 /// appropriate for its type. 146 void HandleOp(SDOperand Op); 147 148 /// LegalizeOp - We know that the specified value has a legal type. 149 /// Recursively ensure that the operands have legal types, then return the 150 /// result. 151 SDOperand LegalizeOp(SDOperand O); 152 153 /// UnrollVectorOp - We know that the given vector has a legal type, however 154 /// the operation it performs is not legal and is an operation that we have 155 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 156 /// operating on each element individually. 157 SDOperand UnrollVectorOp(SDOperand O); 158 159 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 160 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 161 /// is necessary to spill the vector being inserted into to memory, perform 162 /// the insert there, and then read the result back. 163 SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, 164 SDOperand Idx); 165 166 /// PromoteOp - Given an operation that produces a value in an invalid type, 167 /// promote it to compute the value into a larger type. The produced value 168 /// will have the correct bits for the low portion of the register, but no 169 /// guarantee is made about the top bits: it may be zero, sign-extended, or 170 /// garbage. 171 SDOperand PromoteOp(SDOperand O); 172 173 /// ExpandOp - Expand the specified SDOperand into its two component pieces 174 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 175 /// the LegalizeNodes map is filled in for any results that are not expanded, 176 /// the ExpandedNodes map is filled in for any results that are expanded, and 177 /// the Lo/Hi values are returned. This applies to integer types and Vector 178 /// types. 179 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 180 181 /// SplitVectorOp - Given an operand of vector type, break it down into 182 /// two smaller values. 183 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi); 184 185 /// ScalarizeVectorOp - Given an operand of single-element vector type 186 /// (e.g. v1f32), convert it into the equivalent operation that returns a 187 /// scalar (e.g. f32) value. 188 SDOperand ScalarizeVectorOp(SDOperand O); 189 190 /// isShuffleLegal - Return true if a vector shuffle is legal with the 191 /// specified mask and type. Targets can specify exactly which masks they 192 /// support and the code generator is tasked with not creating illegal masks. 193 /// 194 /// Note that this will also return true for shuffles that are promoted to a 195 /// different type. 196 /// 197 /// If this is a legal shuffle, this method returns the (possibly promoted) 198 /// build_vector Mask. If it's not a legal shuffle, it returns null. 199 SDNode *isShuffleLegal(MVT VT, SDOperand Mask) const; 200 201 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 202 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 203 204 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC); 205 206 SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 207 SDOperand &Hi); 208 SDOperand ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source); 209 210 SDOperand EmitStackConvert(SDOperand SrcOp, MVT SlotVT, MVT DestVT); 211 SDOperand ExpandBUILD_VECTOR(SDNode *Node); 212 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node); 213 SDOperand ExpandLegalINT_TO_FP(bool isSigned, SDOperand LegalOp, MVT DestVT); 214 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT DestVT, bool isSigned); 215 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT DestVT, bool isSigned); 216 217 SDOperand ExpandBSWAP(SDOperand Op); 218 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op); 219 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt, 220 SDOperand &Lo, SDOperand &Hi); 221 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt, 222 SDOperand &Lo, SDOperand &Hi); 223 224 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op); 225 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op); 226}; 227} 228 229/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 230/// specified mask and type. Targets can specify exactly which masks they 231/// support and the code generator is tasked with not creating illegal masks. 232/// 233/// Note that this will also return true for shuffles that are promoted to a 234/// different type. 235SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const { 236 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 237 default: return 0; 238 case TargetLowering::Legal: 239 case TargetLowering::Custom: 240 break; 241 case TargetLowering::Promote: { 242 // If this is promoted to a different type, convert the shuffle mask and 243 // ask if it is legal in the promoted type! 244 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 245 246 // If we changed # elements, change the shuffle mask. 247 unsigned NumEltsGrowth = 248 NVT.getVectorNumElements() / VT.getVectorNumElements(); 249 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 250 if (NumEltsGrowth > 1) { 251 // Renumber the elements. 252 SmallVector<SDOperand, 8> Ops; 253 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 254 SDOperand InOp = Mask.getOperand(i); 255 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 256 if (InOp.getOpcode() == ISD::UNDEF) 257 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 258 else { 259 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue(); 260 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32)); 261 } 262 } 263 } 264 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 265 } 266 VT = NVT; 267 break; 268 } 269 } 270 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0; 271} 272 273SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 274 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 275 ValueTypeActions(TLI.getValueTypeActions()) { 276 assert(MVT::LAST_VALUETYPE <= 32 && 277 "Too many value types for ValueTypeActions to hold!"); 278} 279 280/// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order 281/// contains all of a nodes operands before it contains the node. 282static void ComputeTopDownOrdering(SelectionDAG &DAG, 283 SmallVector<SDNode*, 64> &Order) { 284 285 DenseMap<SDNode*, unsigned> Visited; 286 std::vector<SDNode*> Worklist; 287 Worklist.reserve(128); 288 289 // Compute ordering from all of the leaves in the graphs, those (like the 290 // entry node) that have no operands. 291 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 292 E = DAG.allnodes_end(); I != E; ++I) { 293 if (I->getNumOperands() == 0) { 294 Visited[I] = 0 - 1U; 295 Worklist.push_back(I); 296 } 297 } 298 299 while (!Worklist.empty()) { 300 SDNode *N = Worklist.back(); 301 Worklist.pop_back(); 302 303 if (++Visited[N] != N->getNumOperands()) 304 continue; // Haven't visited all operands yet 305 306 Order.push_back(N); 307 308 // Now that we have N in, add anything that uses it if all of their operands 309 // are now done. 310 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); 311 UI != E; ++UI) 312 Worklist.push_back(UI->getUser()); 313 } 314 315 assert(Order.size() == Visited.size() && 316 Order.size() == DAG.allnodes_size() && 317 "Error: DAG is cyclic!"); 318} 319 320 321void SelectionDAGLegalize::LegalizeDAG() { 322 LastCALLSEQ_END = DAG.getEntryNode(); 323 IsLegalizingCall = false; 324 325 // The legalize process is inherently a bottom-up recursive process (users 326 // legalize their uses before themselves). Given infinite stack space, we 327 // could just start legalizing on the root and traverse the whole graph. In 328 // practice however, this causes us to run out of stack space on large basic 329 // blocks. To avoid this problem, compute an ordering of the nodes where each 330 // node is only legalized after all of its operands are legalized. 331 SmallVector<SDNode*, 64> Order; 332 ComputeTopDownOrdering(DAG, Order); 333 334 for (unsigned i = 0, e = Order.size(); i != e; ++i) 335 HandleOp(SDOperand(Order[i], 0)); 336 337 // Finally, it's possible the root changed. Get the new root. 338 SDOperand OldRoot = DAG.getRoot(); 339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 340 DAG.setRoot(LegalizedNodes[OldRoot]); 341 342 ExpandedNodes.clear(); 343 LegalizedNodes.clear(); 344 PromotedNodes.clear(); 345 SplitNodes.clear(); 346 ScalarizedNodes.clear(); 347 348 // Remove dead nodes now. 349 DAG.RemoveDeadNodes(); 350} 351 352 353/// FindCallEndFromCallStart - Given a chained node that is part of a call 354/// sequence, find the CALLSEQ_END node that terminates the call sequence. 355static SDNode *FindCallEndFromCallStart(SDNode *Node) { 356 if (Node->getOpcode() == ISD::CALLSEQ_END) 357 return Node; 358 if (Node->use_empty()) 359 return 0; // No CallSeqEnd 360 361 // The chain is usually at the end. 362 SDOperand TheChain(Node, Node->getNumValues()-1); 363 if (TheChain.getValueType() != MVT::Other) { 364 // Sometimes it's at the beginning. 365 TheChain = SDOperand(Node, 0); 366 if (TheChain.getValueType() != MVT::Other) { 367 // Otherwise, hunt for it. 368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 369 if (Node->getValueType(i) == MVT::Other) { 370 TheChain = SDOperand(Node, i); 371 break; 372 } 373 374 // Otherwise, we walked into a node without a chain. 375 if (TheChain.getValueType() != MVT::Other) 376 return 0; 377 } 378 } 379 380 for (SDNode::use_iterator UI = Node->use_begin(), 381 E = Node->use_end(); UI != E; ++UI) { 382 383 // Make sure to only follow users of our token chain. 384 SDNode *User = UI->getUser(); 385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 386 if (User->getOperand(i) == TheChain) 387 if (SDNode *Result = FindCallEndFromCallStart(User)) 388 return Result; 389 } 390 return 0; 391} 392 393/// FindCallStartFromCallEnd - Given a chained node that is part of a call 394/// sequence, find the CALLSEQ_START node that initiates the call sequence. 395static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 396 assert(Node && "Didn't find callseq_start for a call??"); 397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 398 399 assert(Node->getOperand(0).getValueType() == MVT::Other && 400 "Node doesn't have a token chain argument!"); 401 return FindCallStartFromCallEnd(Node->getOperand(0).Val); 402} 403 404/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 405/// see if any uses can reach Dest. If no dest operands can get to dest, 406/// legalize them, legalize ourself, and return false, otherwise, return true. 407/// 408/// Keep track of the nodes we fine that actually do lead to Dest in 409/// NodesLeadingTo. This avoids retraversing them exponential number of times. 410/// 411bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 413 if (N == Dest) return true; // N certainly leads to Dest :) 414 415 // If we've already processed this node and it does lead to Dest, there is no 416 // need to reprocess it. 417 if (NodesLeadingTo.count(N)) return true; 418 419 // If the first result of this node has been already legalized, then it cannot 420 // reach N. 421 switch (getTypeAction(N->getValueType(0))) { 422 case Legal: 423 if (LegalizedNodes.count(SDOperand(N, 0))) return false; 424 break; 425 case Promote: 426 if (PromotedNodes.count(SDOperand(N, 0))) return false; 427 break; 428 case Expand: 429 if (ExpandedNodes.count(SDOperand(N, 0))) return false; 430 break; 431 } 432 433 // Okay, this node has not already been legalized. Check and legalize all 434 // operands. If none lead to Dest, then we can legalize this node. 435 bool OperandsLeadToDest = false; 436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 437 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo); 439 440 if (OperandsLeadToDest) { 441 NodesLeadingTo.insert(N); 442 return true; 443 } 444 445 // Okay, this node looks safe, legalize it and return false. 446 HandleOp(SDOperand(N, 0)); 447 return false; 448} 449 450/// HandleOp - Legalize, Promote, or Expand the specified operand as 451/// appropriate for its type. 452void SelectionDAGLegalize::HandleOp(SDOperand Op) { 453 MVT VT = Op.getValueType(); 454 switch (getTypeAction(VT)) { 455 default: assert(0 && "Bad type action!"); 456 case Legal: (void)LegalizeOp(Op); break; 457 case Promote: (void)PromoteOp(Op); break; 458 case Expand: 459 if (!VT.isVector()) { 460 // If this is an illegal scalar, expand it into its two component 461 // pieces. 462 SDOperand X, Y; 463 if (Op.getOpcode() == ISD::TargetConstant) 464 break; // Allow illegal target nodes. 465 ExpandOp(Op, X, Y); 466 } else if (VT.getVectorNumElements() == 1) { 467 // If this is an illegal single element vector, convert it to a 468 // scalar operation. 469 (void)ScalarizeVectorOp(Op); 470 } else { 471 // Otherwise, this is an illegal multiple element vector. 472 // Split it in half and legalize both parts. 473 SDOperand X, Y; 474 SplitVectorOp(Op, X, Y); 475 } 476 break; 477 } 478} 479 480/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 481/// a load from the constant pool. 482static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 483 SelectionDAG &DAG, TargetLowering &TLI) { 484 bool Extend = false; 485 486 // If a FP immediate is precise when represented as a float and if the 487 // target can do an extending load from float to double, we put it into 488 // the constant pool as a float, even if it's is statically typed as a 489 // double. This shrinks FP constants and canonicalizes them for targets where 490 // an FP extending load is the same cost as a normal load (such as on the x87 491 // fp stack or PPC FP unit). 492 MVT VT = CFP->getValueType(0); 493 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF()); 494 if (!UseCP) { 495 if (VT!=MVT::f64 && VT!=MVT::f32) 496 assert(0 && "Invalid type expansion"); 497 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(), 498 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 499 } 500 501 MVT OrigVT = VT; 502 MVT SVT = VT; 503 while (SVT != MVT::f32) { 504 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 505 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 506 // Only do this if the target has a native EXTLOAD instruction from 507 // smaller type. 508 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && 509 TLI.ShouldShrinkFPConstant(OrigVT)) { 510 const Type *SType = SVT.getTypeForMVT(); 511 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 512 VT = SVT; 513 Extend = true; 514 } 515 } 516 517 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 518 if (Extend) 519 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), 520 CPIdx, PseudoSourceValue::getConstantPool(), 521 0, VT); 522 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 523 PseudoSourceValue::getConstantPool(), 0); 524} 525 526 527/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 528/// operations. 529static 530SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, 531 SelectionDAG &DAG, TargetLowering &TLI) { 532 MVT VT = Node->getValueType(0); 533 MVT SrcVT = Node->getOperand(1).getValueType(); 534 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 535 "fcopysign expansion only supported for f32 and f64"); 536 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 537 538 // First get the sign bit of second operand. 539 SDOperand Mask1 = (SrcVT == MVT::f64) 540 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 541 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 542 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 543 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 544 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 545 // Shift right or sign-extend it if the two operands have different types. 546 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); 547 if (SizeDiff > 0) { 548 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 549 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 550 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 551 } else if (SizeDiff < 0) 552 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit); 553 554 // Clear the sign bit of first operand. 555 SDOperand Mask2 = (VT == MVT::f64) 556 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 557 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 558 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 559 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 560 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 561 562 // Or the value with the sign bit. 563 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 564 return Result; 565} 566 567/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 568static 569SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 570 TargetLowering &TLI) { 571 SDOperand Chain = ST->getChain(); 572 SDOperand Ptr = ST->getBasePtr(); 573 SDOperand Val = ST->getValue(); 574 MVT VT = Val.getValueType(); 575 int Alignment = ST->getAlignment(); 576 int SVOffset = ST->getSrcValueOffset(); 577 if (ST->getMemoryVT().isFloatingPoint() || 578 ST->getMemoryVT().isVector()) { 579 // Expand to a bitconvert of the value to the integer type of the 580 // same size, then a (misaligned) int store. 581 MVT intVT; 582 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128) 583 intVT = MVT::i128; 584 else if (VT.is64BitVector() || VT==MVT::f64) 585 intVT = MVT::i64; 586 else if (VT==MVT::f32) 587 intVT = MVT::i32; 588 else 589 assert(0 && "Unaligned store of unsupported type"); 590 591 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 592 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 593 SVOffset, ST->isVolatile(), Alignment); 594 } 595 assert(ST->getMemoryVT().isInteger() && 596 !ST->getMemoryVT().isVector() && 597 "Unaligned store of unknown type."); 598 // Get the half-size VT 599 MVT NewStoredVT = 600 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 601 int NumBits = NewStoredVT.getSizeInBits(); 602 int IncrementSize = NumBits / 8; 603 604 // Divide the stored value in two parts. 605 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 606 SDOperand Lo = Val; 607 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 608 609 // Store the two parts 610 SDOperand Store1, Store2; 611 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 612 ST->getSrcValue(), SVOffset, NewStoredVT, 613 ST->isVolatile(), Alignment); 614 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 615 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 616 Alignment = MinAlign(Alignment, IncrementSize); 617 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 618 ST->getSrcValue(), SVOffset + IncrementSize, 619 NewStoredVT, ST->isVolatile(), Alignment); 620 621 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 622} 623 624/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 625static 626SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 627 TargetLowering &TLI) { 628 int SVOffset = LD->getSrcValueOffset(); 629 SDOperand Chain = LD->getChain(); 630 SDOperand Ptr = LD->getBasePtr(); 631 MVT VT = LD->getValueType(0); 632 MVT LoadedVT = LD->getMemoryVT(); 633 if (VT.isFloatingPoint() || VT.isVector()) { 634 // Expand to a (misaligned) integer load of the same size, 635 // then bitconvert to floating point or vector. 636 MVT intVT; 637 if (LoadedVT.is128BitVector() || 638 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128) 639 intVT = MVT::i128; 640 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64) 641 intVT = MVT::i64; 642 else if (LoadedVT == MVT::f32) 643 intVT = MVT::i32; 644 else 645 assert(0 && "Unaligned load of unsupported type"); 646 647 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 648 SVOffset, LD->isVolatile(), 649 LD->getAlignment()); 650 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 651 if (VT.isFloatingPoint() && LoadedVT != VT) 652 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 653 654 SDOperand Ops[] = { Result, Chain }; 655 return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); 656 } 657 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 658 "Unaligned load of unsupported type."); 659 660 // Compute the new VT that is half the size of the old one. This is an 661 // integer MVT. 662 unsigned NumBits = LoadedVT.getSizeInBits(); 663 MVT NewLoadedVT; 664 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 665 NumBits >>= 1; 666 667 unsigned Alignment = LD->getAlignment(); 668 unsigned IncrementSize = NumBits / 8; 669 ISD::LoadExtType HiExtType = LD->getExtensionType(); 670 671 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 672 if (HiExtType == ISD::NON_EXTLOAD) 673 HiExtType = ISD::ZEXTLOAD; 674 675 // Load the value in two parts 676 SDOperand Lo, Hi; 677 if (TLI.isLittleEndian()) { 678 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 679 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 680 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 681 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 682 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 683 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 684 MinAlign(Alignment, IncrementSize)); 685 } else { 686 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 687 NewLoadedVT,LD->isVolatile(), Alignment); 688 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 689 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 690 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 691 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 692 MinAlign(Alignment, IncrementSize)); 693 } 694 695 // aggregate the two parts 696 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 697 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 698 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 699 700 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 701 Hi.getValue(1)); 702 703 SDOperand Ops[] = { Result, TF }; 704 return DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); 705} 706 707/// UnrollVectorOp - We know that the given vector has a legal type, however 708/// the operation it performs is not legal and is an operation that we have 709/// no way of lowering. "Unroll" the vector, splitting out the scalars and 710/// operating on each element individually. 711SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) { 712 MVT VT = Op.getValueType(); 713 assert(isTypeLegal(VT) && 714 "Caller should expand or promote operands that are not legal!"); 715 assert(Op.Val->getNumValues() == 1 && 716 "Can't unroll a vector with multiple results!"); 717 unsigned NE = VT.getVectorNumElements(); 718 MVT EltVT = VT.getVectorElementType(); 719 720 SmallVector<SDOperand, 8> Scalars; 721 SmallVector<SDOperand, 4> Operands(Op.getNumOperands()); 722 for (unsigned i = 0; i != NE; ++i) { 723 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 724 SDOperand Operand = Op.getOperand(j); 725 MVT OperandVT = Operand.getValueType(); 726 if (OperandVT.isVector()) { 727 // A vector operand; extract a single element. 728 MVT OperandEltVT = OperandVT.getVectorElementType(); 729 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 730 OperandEltVT, 731 Operand, 732 DAG.getConstant(i, MVT::i32)); 733 } else { 734 // A scalar operand; just use it as is. 735 Operands[j] = Operand; 736 } 737 } 738 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 739 &Operands[0], Operands.size())); 740 } 741 742 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 743} 744 745/// GetFPLibCall - Return the right libcall for the given floating point type. 746static RTLIB::Libcall GetFPLibCall(MVT VT, 747 RTLIB::Libcall Call_F32, 748 RTLIB::Libcall Call_F64, 749 RTLIB::Libcall Call_F80, 750 RTLIB::Libcall Call_PPCF128) { 751 return 752 VT == MVT::f32 ? Call_F32 : 753 VT == MVT::f64 ? Call_F64 : 754 VT == MVT::f80 ? Call_F80 : 755 VT == MVT::ppcf128 ? Call_PPCF128 : 756 RTLIB::UNKNOWN_LIBCALL; 757} 758 759/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 760/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 761/// is necessary to spill the vector being inserted into to memory, perform 762/// the insert there, and then read the result back. 763SDOperand SelectionDAGLegalize:: 764PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) { 765 SDOperand Tmp1 = Vec; 766 SDOperand Tmp2 = Val; 767 SDOperand Tmp3 = Idx; 768 769 // If the target doesn't support this, we have to spill the input vector 770 // to a temporary stack slot, update the element, then reload it. This is 771 // badness. We could also load the value into a vector register (either 772 // with a "move to register" or "extload into register" instruction, then 773 // permute it into place, if the idx is a constant and if the idx is 774 // supported by the target. 775 MVT VT = Tmp1.getValueType(); 776 MVT EltVT = VT.getVectorElementType(); 777 MVT IdxVT = Tmp3.getValueType(); 778 MVT PtrVT = TLI.getPointerTy(); 779 SDOperand StackPtr = DAG.CreateStackTemporary(VT); 780 781 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val); 782 int SPFI = StackPtrFI->getIndex(); 783 784 // Store the vector. 785 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, 786 PseudoSourceValue::getFixedStack(), 787 SPFI); 788 789 // Truncate or zero extend offset to target pointer type. 790 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 791 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 792 // Add the offset to the index. 793 unsigned EltSize = EltVT.getSizeInBits()/8; 794 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 795 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 796 // Store the scalar value. 797 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, 798 PseudoSourceValue::getFixedStack(), SPFI, EltVT); 799 // Load the updated vector. 800 return DAG.getLoad(VT, Ch, StackPtr, PseudoSourceValue::getFixedStack(),SPFI); 801} 802 803/// LegalizeOp - We know that the specified value has a legal type, and 804/// that its operands are legal. Now ensure that the operation itself 805/// is legal, recursively ensuring that the operands' operations remain 806/// legal. 807SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { 808 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 809 return Op; 810 811 assert(isTypeLegal(Op.getValueType()) && 812 "Caller should expand or promote operands that are not legal!"); 813 SDNode *Node = Op.Val; 814 815 // If this operation defines any values that cannot be represented in a 816 // register on this target, make sure to expand or promote them. 817 if (Node->getNumValues() > 1) { 818 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 819 if (getTypeAction(Node->getValueType(i)) != Legal) { 820 HandleOp(Op.getValue(i)); 821 assert(LegalizedNodes.count(Op) && 822 "Handling didn't add legal operands!"); 823 return LegalizedNodes[Op]; 824 } 825 } 826 827 // Note that LegalizeOp may be reentered even from single-use nodes, which 828 // means that we always must cache transformed nodes. 829 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 830 if (I != LegalizedNodes.end()) return I->second; 831 832 SDOperand Tmp1, Tmp2, Tmp3, Tmp4; 833 SDOperand Result = Op; 834 bool isCustom = false; 835 836 switch (Node->getOpcode()) { 837 case ISD::FrameIndex: 838 case ISD::EntryToken: 839 case ISD::Register: 840 case ISD::BasicBlock: 841 case ISD::TargetFrameIndex: 842 case ISD::TargetJumpTable: 843 case ISD::TargetConstant: 844 case ISD::TargetConstantFP: 845 case ISD::TargetConstantPool: 846 case ISD::TargetGlobalAddress: 847 case ISD::TargetGlobalTLSAddress: 848 case ISD::TargetExternalSymbol: 849 case ISD::VALUETYPE: 850 case ISD::SRCVALUE: 851 case ISD::MEMOPERAND: 852 case ISD::STRING: 853 case ISD::CONDCODE: 854 case ISD::ARG_FLAGS: 855 // Primitives must all be legal. 856 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 857 "This must be legal!"); 858 break; 859 default: 860 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 861 // If this is a target node, legalize it by legalizing the operands then 862 // passing it through. 863 SmallVector<SDOperand, 8> Ops; 864 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 865 Ops.push_back(LegalizeOp(Node->getOperand(i))); 866 867 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 868 869 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 870 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 871 return Result.getValue(Op.ResNo); 872 } 873 // Otherwise this is an unhandled builtin node. splat. 874#ifndef NDEBUG 875 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 876#endif 877 assert(0 && "Do not know how to legalize this operator!"); 878 abort(); 879 case ISD::GLOBAL_OFFSET_TABLE: 880 case ISD::GlobalAddress: 881 case ISD::GlobalTLSAddress: 882 case ISD::ExternalSymbol: 883 case ISD::ConstantPool: 884 case ISD::JumpTable: // Nothing to do. 885 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 886 default: assert(0 && "This action is not supported yet!"); 887 case TargetLowering::Custom: 888 Tmp1 = TLI.LowerOperation(Op, DAG); 889 if (Tmp1.Val) Result = Tmp1; 890 // FALLTHROUGH if the target doesn't want to lower this op after all. 891 case TargetLowering::Legal: 892 break; 893 } 894 break; 895 case ISD::FRAMEADDR: 896 case ISD::RETURNADDR: 897 // The only option for these nodes is to custom lower them. If the target 898 // does not custom lower them, then return zero. 899 Tmp1 = TLI.LowerOperation(Op, DAG); 900 if (Tmp1.Val) 901 Result = Tmp1; 902 else 903 Result = DAG.getConstant(0, TLI.getPointerTy()); 904 break; 905 case ISD::FRAME_TO_ARGS_OFFSET: { 906 MVT VT = Node->getValueType(0); 907 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 908 default: assert(0 && "This action is not supported yet!"); 909 case TargetLowering::Custom: 910 Result = TLI.LowerOperation(Op, DAG); 911 if (Result.Val) break; 912 // Fall Thru 913 case TargetLowering::Legal: 914 Result = DAG.getConstant(0, VT); 915 break; 916 } 917 } 918 break; 919 case ISD::EXCEPTIONADDR: { 920 Tmp1 = LegalizeOp(Node->getOperand(0)); 921 MVT VT = Node->getValueType(0); 922 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 923 default: assert(0 && "This action is not supported yet!"); 924 case TargetLowering::Expand: { 925 unsigned Reg = TLI.getExceptionAddressRegister(); 926 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 927 } 928 break; 929 case TargetLowering::Custom: 930 Result = TLI.LowerOperation(Op, DAG); 931 if (Result.Val) break; 932 // Fall Thru 933 case TargetLowering::Legal: { 934 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 935 Result = DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); 936 break; 937 } 938 } 939 } 940 if (Result.Val->getNumValues() == 1) break; 941 942 assert(Result.Val->getNumValues() == 2 && 943 "Cannot return more than two values!"); 944 945 // Since we produced two values, make sure to remember that we 946 // legalized both of them. 947 Tmp1 = LegalizeOp(Result); 948 Tmp2 = LegalizeOp(Result.getValue(1)); 949 AddLegalizedOperand(Op.getValue(0), Tmp1); 950 AddLegalizedOperand(Op.getValue(1), Tmp2); 951 return Op.ResNo ? Tmp2 : Tmp1; 952 case ISD::EHSELECTION: { 953 Tmp1 = LegalizeOp(Node->getOperand(0)); 954 Tmp2 = LegalizeOp(Node->getOperand(1)); 955 MVT VT = Node->getValueType(0); 956 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 957 default: assert(0 && "This action is not supported yet!"); 958 case TargetLowering::Expand: { 959 unsigned Reg = TLI.getExceptionSelectorRegister(); 960 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 961 } 962 break; 963 case TargetLowering::Custom: 964 Result = TLI.LowerOperation(Op, DAG); 965 if (Result.Val) break; 966 // Fall Thru 967 case TargetLowering::Legal: { 968 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 969 Result = DAG.getMergeValues(DAG.getVTList(VT, MVT::Other), Ops, 2); 970 break; 971 } 972 } 973 } 974 if (Result.Val->getNumValues() == 1) break; 975 976 assert(Result.Val->getNumValues() == 2 && 977 "Cannot return more than two values!"); 978 979 // Since we produced two values, make sure to remember that we 980 // legalized both of them. 981 Tmp1 = LegalizeOp(Result); 982 Tmp2 = LegalizeOp(Result.getValue(1)); 983 AddLegalizedOperand(Op.getValue(0), Tmp1); 984 AddLegalizedOperand(Op.getValue(1), Tmp2); 985 return Op.ResNo ? Tmp2 : Tmp1; 986 case ISD::EH_RETURN: { 987 MVT VT = Node->getValueType(0); 988 // The only "good" option for this node is to custom lower it. 989 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 990 default: assert(0 && "This action is not supported at all!"); 991 case TargetLowering::Custom: 992 Result = TLI.LowerOperation(Op, DAG); 993 if (Result.Val) break; 994 // Fall Thru 995 case TargetLowering::Legal: 996 // Target does not know, how to lower this, lower to noop 997 Result = LegalizeOp(Node->getOperand(0)); 998 break; 999 } 1000 } 1001 break; 1002 case ISD::AssertSext: 1003 case ISD::AssertZext: 1004 Tmp1 = LegalizeOp(Node->getOperand(0)); 1005 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1006 break; 1007 case ISD::MERGE_VALUES: 1008 // Legalize eliminates MERGE_VALUES nodes. 1009 Result = Node->getOperand(Op.ResNo); 1010 break; 1011 case ISD::CopyFromReg: 1012 Tmp1 = LegalizeOp(Node->getOperand(0)); 1013 Result = Op.getValue(0); 1014 if (Node->getNumValues() == 2) { 1015 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1016 } else { 1017 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 1018 if (Node->getNumOperands() == 3) { 1019 Tmp2 = LegalizeOp(Node->getOperand(2)); 1020 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1021 } else { 1022 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1023 } 1024 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 1025 } 1026 // Since CopyFromReg produces two values, make sure to remember that we 1027 // legalized both of them. 1028 AddLegalizedOperand(Op.getValue(0), Result); 1029 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1030 return Result.getValue(Op.ResNo); 1031 case ISD::UNDEF: { 1032 MVT VT = Op.getValueType(); 1033 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 1034 default: assert(0 && "This action is not supported yet!"); 1035 case TargetLowering::Expand: 1036 if (VT.isInteger()) 1037 Result = DAG.getConstant(0, VT); 1038 else if (VT.isFloatingPoint()) 1039 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), 1040 VT); 1041 else 1042 assert(0 && "Unknown value type!"); 1043 break; 1044 case TargetLowering::Legal: 1045 break; 1046 } 1047 break; 1048 } 1049 1050 case ISD::INTRINSIC_W_CHAIN: 1051 case ISD::INTRINSIC_WO_CHAIN: 1052 case ISD::INTRINSIC_VOID: { 1053 SmallVector<SDOperand, 8> Ops; 1054 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1055 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1056 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1057 1058 // Allow the target to custom lower its intrinsics if it wants to. 1059 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1060 TargetLowering::Custom) { 1061 Tmp3 = TLI.LowerOperation(Result, DAG); 1062 if (Tmp3.Val) Result = Tmp3; 1063 } 1064 1065 if (Result.Val->getNumValues() == 1) break; 1066 1067 // Must have return value and chain result. 1068 assert(Result.Val->getNumValues() == 2 && 1069 "Cannot return more than two values!"); 1070 1071 // Since loads produce two values, make sure to remember that we 1072 // legalized both of them. 1073 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1074 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1075 return Result.getValue(Op.ResNo); 1076 } 1077 1078 case ISD::LOCATION: 1079 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!"); 1080 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1081 1082 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) { 1083 case TargetLowering::Promote: 1084 default: assert(0 && "This action is not supported yet!"); 1085 case TargetLowering::Expand: { 1086 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1087 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1088 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other); 1089 1090 if (MMI && (useDEBUG_LOC || useLABEL)) { 1091 const std::string &FName = 1092 cast<StringSDNode>(Node->getOperand(3))->getValue(); 1093 const std::string &DirName = 1094 cast<StringSDNode>(Node->getOperand(4))->getValue(); 1095 unsigned SrcFile = MMI->RecordSource(DirName, FName); 1096 1097 SmallVector<SDOperand, 8> Ops; 1098 Ops.push_back(Tmp1); // chain 1099 SDOperand LineOp = Node->getOperand(1); 1100 SDOperand ColOp = Node->getOperand(2); 1101 1102 if (useDEBUG_LOC) { 1103 Ops.push_back(LineOp); // line # 1104 Ops.push_back(ColOp); // col # 1105 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id 1106 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size()); 1107 } else { 1108 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue(); 1109 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue(); 1110 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 1111 Ops.push_back(DAG.getConstant(ID, MVT::i32)); 1112 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label 1113 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size()); 1114 } 1115 } else { 1116 Result = Tmp1; // chain 1117 } 1118 break; 1119 } 1120 case TargetLowering::Legal: 1121 if (Tmp1 != Node->getOperand(0) || 1122 getTypeAction(Node->getOperand(1).getValueType()) == Promote) { 1123 SmallVector<SDOperand, 8> Ops; 1124 Ops.push_back(Tmp1); 1125 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) { 1126 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1127 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1128 } else { 1129 // Otherwise promote them. 1130 Ops.push_back(PromoteOp(Node->getOperand(1))); 1131 Ops.push_back(PromoteOp(Node->getOperand(2))); 1132 } 1133 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1134 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1135 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1136 } 1137 break; 1138 } 1139 break; 1140 1141 case ISD::DECLARE: 1142 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1143 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1144 default: assert(0 && "This action is not supported yet!"); 1145 case TargetLowering::Legal: 1146 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1147 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1148 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1149 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1150 break; 1151 case TargetLowering::Expand: 1152 Result = LegalizeOp(Node->getOperand(0)); 1153 break; 1154 } 1155 break; 1156 1157 case ISD::DEBUG_LOC: 1158 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1159 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1160 default: assert(0 && "This action is not supported yet!"); 1161 case TargetLowering::Legal: 1162 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1163 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1164 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1165 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1166 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1167 break; 1168 } 1169 break; 1170 1171 case ISD::LABEL: 1172 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!"); 1173 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) { 1174 default: assert(0 && "This action is not supported yet!"); 1175 case TargetLowering::Legal: 1176 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1177 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id. 1178 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand. 1179 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1180 break; 1181 case TargetLowering::Expand: 1182 Result = LegalizeOp(Node->getOperand(0)); 1183 break; 1184 } 1185 break; 1186 1187 case ISD::PREFETCH: 1188 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1189 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1190 default: assert(0 && "This action is not supported yet!"); 1191 case TargetLowering::Legal: 1192 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1193 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1194 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1195 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1196 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1197 break; 1198 case TargetLowering::Expand: 1199 // It's a noop. 1200 Result = LegalizeOp(Node->getOperand(0)); 1201 break; 1202 } 1203 break; 1204 1205 case ISD::MEMBARRIER: { 1206 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1207 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1208 default: assert(0 && "This action is not supported yet!"); 1209 case TargetLowering::Legal: { 1210 SDOperand Ops[6]; 1211 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1212 for (int x = 1; x < 6; ++x) { 1213 Ops[x] = Node->getOperand(x); 1214 if (!isTypeLegal(Ops[x].getValueType())) 1215 Ops[x] = PromoteOp(Ops[x]); 1216 } 1217 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1218 break; 1219 } 1220 case TargetLowering::Expand: 1221 //There is no libgcc call for this op 1222 Result = Node->getOperand(0); // Noop 1223 break; 1224 } 1225 break; 1226 } 1227 1228 case ISD::ATOMIC_CMP_SWAP: { 1229 unsigned int num_operands = 4; 1230 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1231 SDOperand Ops[4]; 1232 for (unsigned int x = 0; x < num_operands; ++x) 1233 Ops[x] = LegalizeOp(Node->getOperand(x)); 1234 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1235 1236 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1237 default: assert(0 && "This action is not supported yet!"); 1238 case TargetLowering::Custom: 1239 Result = TLI.LowerOperation(Result, DAG); 1240 break; 1241 case TargetLowering::Legal: 1242 break; 1243 } 1244 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1245 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1246 return Result.getValue(Op.ResNo); 1247 } 1248 case ISD::ATOMIC_LOAD_ADD: 1249 case ISD::ATOMIC_LOAD_SUB: 1250 case ISD::ATOMIC_LOAD_AND: 1251 case ISD::ATOMIC_LOAD_OR: 1252 case ISD::ATOMIC_LOAD_XOR: 1253 case ISD::ATOMIC_LOAD_NAND: 1254 case ISD::ATOMIC_LOAD_MIN: 1255 case ISD::ATOMIC_LOAD_MAX: 1256 case ISD::ATOMIC_LOAD_UMIN: 1257 case ISD::ATOMIC_LOAD_UMAX: 1258 case ISD::ATOMIC_SWAP: { 1259 unsigned int num_operands = 3; 1260 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1261 SDOperand Ops[3]; 1262 for (unsigned int x = 0; x < num_operands; ++x) 1263 Ops[x] = LegalizeOp(Node->getOperand(x)); 1264 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1265 1266 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1267 default: assert(0 && "This action is not supported yet!"); 1268 case TargetLowering::Custom: 1269 Result = TLI.LowerOperation(Result, DAG); 1270 break; 1271 case TargetLowering::Expand: 1272 Result = SDOperand(TLI.ExpandOperationResult(Op.Val, DAG),0); 1273 break; 1274 case TargetLowering::Legal: 1275 break; 1276 } 1277 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1278 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1279 return Result.getValue(Op.ResNo); 1280 } 1281 case ISD::Constant: { 1282 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1283 unsigned opAction = 1284 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1285 1286 // We know we don't need to expand constants here, constants only have one 1287 // value and we check that it is fine above. 1288 1289 if (opAction == TargetLowering::Custom) { 1290 Tmp1 = TLI.LowerOperation(Result, DAG); 1291 if (Tmp1.Val) 1292 Result = Tmp1; 1293 } 1294 break; 1295 } 1296 case ISD::ConstantFP: { 1297 // Spill FP immediates to the constant pool if the target cannot directly 1298 // codegen them. Targets often have some immediate values that can be 1299 // efficiently generated into an FP register without a load. We explicitly 1300 // leave these constants as ConstantFP nodes for the target to deal with. 1301 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1302 1303 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1304 default: assert(0 && "This action is not supported yet!"); 1305 case TargetLowering::Legal: 1306 break; 1307 case TargetLowering::Custom: 1308 Tmp3 = TLI.LowerOperation(Result, DAG); 1309 if (Tmp3.Val) { 1310 Result = Tmp3; 1311 break; 1312 } 1313 // FALLTHROUGH 1314 case TargetLowering::Expand: { 1315 // Check to see if this FP immediate is already legal. 1316 bool isLegal = false; 1317 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1318 E = TLI.legal_fpimm_end(); I != E; ++I) { 1319 if (CFP->isExactlyValue(*I)) { 1320 isLegal = true; 1321 break; 1322 } 1323 } 1324 // If this is a legal constant, turn it into a TargetConstantFP node. 1325 if (isLegal) 1326 break; 1327 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1328 } 1329 } 1330 break; 1331 } 1332 case ISD::TokenFactor: 1333 if (Node->getNumOperands() == 2) { 1334 Tmp1 = LegalizeOp(Node->getOperand(0)); 1335 Tmp2 = LegalizeOp(Node->getOperand(1)); 1336 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1337 } else if (Node->getNumOperands() == 3) { 1338 Tmp1 = LegalizeOp(Node->getOperand(0)); 1339 Tmp2 = LegalizeOp(Node->getOperand(1)); 1340 Tmp3 = LegalizeOp(Node->getOperand(2)); 1341 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1342 } else { 1343 SmallVector<SDOperand, 8> Ops; 1344 // Legalize the operands. 1345 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1346 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1347 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1348 } 1349 break; 1350 1351 case ISD::FORMAL_ARGUMENTS: 1352 case ISD::CALL: 1353 // The only option for this is to custom lower it. 1354 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1355 assert(Tmp3.Val && "Target didn't custom lower this node!"); 1356 // A call within a calling sequence must be legalized to something 1357 // other than the normal CALLSEQ_END. Violating this gets Legalize 1358 // into an infinite loop. 1359 assert ((!IsLegalizingCall || 1360 Node->getOpcode() != ISD::CALL || 1361 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) && 1362 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1363 1364 // The number of incoming and outgoing values should match; unless the final 1365 // outgoing value is a flag. 1366 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() || 1367 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 && 1368 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) == 1369 MVT::Flag)) && 1370 "Lowering call/formal_arguments produced unexpected # results!"); 1371 1372 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1373 // remember that we legalized all of them, so it doesn't get relegalized. 1374 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) { 1375 if (Tmp3.Val->getValueType(i) == MVT::Flag) 1376 continue; 1377 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1378 if (Op.ResNo == i) 1379 Tmp2 = Tmp1; 1380 AddLegalizedOperand(SDOperand(Node, i), Tmp1); 1381 } 1382 return Tmp2; 1383 case ISD::EXTRACT_SUBREG: { 1384 Tmp1 = LegalizeOp(Node->getOperand(0)); 1385 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1386 assert(idx && "Operand must be a constant"); 1387 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1388 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1389 } 1390 break; 1391 case ISD::INSERT_SUBREG: { 1392 Tmp1 = LegalizeOp(Node->getOperand(0)); 1393 Tmp2 = LegalizeOp(Node->getOperand(1)); 1394 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1395 assert(idx && "Operand must be a constant"); 1396 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0)); 1397 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1398 } 1399 break; 1400 case ISD::BUILD_VECTOR: 1401 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1402 default: assert(0 && "This action is not supported yet!"); 1403 case TargetLowering::Custom: 1404 Tmp3 = TLI.LowerOperation(Result, DAG); 1405 if (Tmp3.Val) { 1406 Result = Tmp3; 1407 break; 1408 } 1409 // FALLTHROUGH 1410 case TargetLowering::Expand: 1411 Result = ExpandBUILD_VECTOR(Result.Val); 1412 break; 1413 } 1414 break; 1415 case ISD::INSERT_VECTOR_ELT: 1416 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1417 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1418 1419 // The type of the value to insert may not be legal, even though the vector 1420 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1421 // here. 1422 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1423 default: assert(0 && "Cannot expand insert element operand"); 1424 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1425 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1426 } 1427 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1428 1429 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1430 Node->getValueType(0))) { 1431 default: assert(0 && "This action is not supported yet!"); 1432 case TargetLowering::Legal: 1433 break; 1434 case TargetLowering::Custom: 1435 Tmp4 = TLI.LowerOperation(Result, DAG); 1436 if (Tmp4.Val) { 1437 Result = Tmp4; 1438 break; 1439 } 1440 // FALLTHROUGH 1441 case TargetLowering::Expand: { 1442 // If the insert index is a constant, codegen this as a scalar_to_vector, 1443 // then a shuffle that inserts it into the right position in the vector. 1444 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1445 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1446 // match the element type of the vector being created. 1447 if (Tmp2.getValueType() == 1448 Op.getValueType().getVectorElementType()) { 1449 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1450 Tmp1.getValueType(), Tmp2); 1451 1452 unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); 1453 MVT ShufMaskVT = 1454 MVT::getIntVectorWithNumElements(NumElts); 1455 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); 1456 1457 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1458 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1459 // elt 0 of the RHS. 1460 SmallVector<SDOperand, 8> ShufOps; 1461 for (unsigned i = 0; i != NumElts; ++i) { 1462 if (i != InsertPos->getValue()) 1463 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1464 else 1465 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1466 } 1467 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1468 &ShufOps[0], ShufOps.size()); 1469 1470 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1471 Tmp1, ScVec, ShufMask); 1472 Result = LegalizeOp(Result); 1473 break; 1474 } 1475 } 1476 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3); 1477 break; 1478 } 1479 } 1480 break; 1481 case ISD::SCALAR_TO_VECTOR: 1482 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1483 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1484 break; 1485 } 1486 1487 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1488 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1489 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1490 Node->getValueType(0))) { 1491 default: assert(0 && "This action is not supported yet!"); 1492 case TargetLowering::Legal: 1493 break; 1494 case TargetLowering::Custom: 1495 Tmp3 = TLI.LowerOperation(Result, DAG); 1496 if (Tmp3.Val) { 1497 Result = Tmp3; 1498 break; 1499 } 1500 // FALLTHROUGH 1501 case TargetLowering::Expand: 1502 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1503 break; 1504 } 1505 break; 1506 case ISD::VECTOR_SHUFFLE: 1507 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1508 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1509 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1510 1511 // Allow targets to custom lower the SHUFFLEs they support. 1512 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1513 default: assert(0 && "Unknown operation action!"); 1514 case TargetLowering::Legal: 1515 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1516 "vector shuffle should not be created if not legal!"); 1517 break; 1518 case TargetLowering::Custom: 1519 Tmp3 = TLI.LowerOperation(Result, DAG); 1520 if (Tmp3.Val) { 1521 Result = Tmp3; 1522 break; 1523 } 1524 // FALLTHROUGH 1525 case TargetLowering::Expand: { 1526 MVT VT = Node->getValueType(0); 1527 MVT EltVT = VT.getVectorElementType(); 1528 MVT PtrVT = TLI.getPointerTy(); 1529 SDOperand Mask = Node->getOperand(2); 1530 unsigned NumElems = Mask.getNumOperands(); 1531 SmallVector<SDOperand,8> Ops; 1532 for (unsigned i = 0; i != NumElems; ++i) { 1533 SDOperand Arg = Mask.getOperand(i); 1534 if (Arg.getOpcode() == ISD::UNDEF) { 1535 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1536 } else { 1537 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1538 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue(); 1539 if (Idx < NumElems) 1540 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1541 DAG.getConstant(Idx, PtrVT))); 1542 else 1543 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1544 DAG.getConstant(Idx - NumElems, PtrVT))); 1545 } 1546 } 1547 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1548 break; 1549 } 1550 case TargetLowering::Promote: { 1551 // Change base type to a different vector type. 1552 MVT OVT = Node->getValueType(0); 1553 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1554 1555 // Cast the two input vectors. 1556 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1557 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1558 1559 // Convert the shuffle mask to the right # elements. 1560 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1561 assert(Tmp3.Val && "Shuffle not legal?"); 1562 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1563 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1564 break; 1565 } 1566 } 1567 break; 1568 1569 case ISD::EXTRACT_VECTOR_ELT: 1570 Tmp1 = Node->getOperand(0); 1571 Tmp2 = LegalizeOp(Node->getOperand(1)); 1572 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1573 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1574 break; 1575 1576 case ISD::EXTRACT_SUBVECTOR: 1577 Tmp1 = Node->getOperand(0); 1578 Tmp2 = LegalizeOp(Node->getOperand(1)); 1579 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1580 Result = ExpandEXTRACT_SUBVECTOR(Result); 1581 break; 1582 1583 case ISD::CALLSEQ_START: { 1584 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1585 1586 // Recursively Legalize all of the inputs of the call end that do not lead 1587 // to this call start. This ensures that any libcalls that need be inserted 1588 // are inserted *before* the CALLSEQ_START. 1589 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1590 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1591 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node, 1592 NodesLeadingTo); 1593 } 1594 1595 // Now that we legalized all of the inputs (which may have inserted 1596 // libcalls) create the new CALLSEQ_START node. 1597 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1598 1599 // Merge in the last call, to ensure that this call start after the last 1600 // call ended. 1601 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1602 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1603 Tmp1 = LegalizeOp(Tmp1); 1604 } 1605 1606 // Do not try to legalize the target-specific arguments (#1+). 1607 if (Tmp1 != Node->getOperand(0)) { 1608 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1609 Ops[0] = Tmp1; 1610 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1611 } 1612 1613 // Remember that the CALLSEQ_START is legalized. 1614 AddLegalizedOperand(Op.getValue(0), Result); 1615 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1616 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1617 1618 // Now that the callseq_start and all of the non-call nodes above this call 1619 // sequence have been legalized, legalize the call itself. During this 1620 // process, no libcalls can/will be inserted, guaranteeing that no calls 1621 // can overlap. 1622 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1623 // Note that we are selecting this call! 1624 LastCALLSEQ_END = SDOperand(CallEnd, 0); 1625 IsLegalizingCall = true; 1626 1627 // Legalize the call, starting from the CALLSEQ_END. 1628 LegalizeOp(LastCALLSEQ_END); 1629 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1630 return Result; 1631 } 1632 case ISD::CALLSEQ_END: 1633 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1634 // will cause this node to be legalized as well as handling libcalls right. 1635 if (LastCALLSEQ_END.Val != Node) { 1636 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0)); 1637 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op); 1638 assert(I != LegalizedNodes.end() && 1639 "Legalizing the call start should have legalized this node!"); 1640 return I->second; 1641 } 1642 1643 // Otherwise, the call start has been legalized and everything is going 1644 // according to plan. Just legalize ourselves normally here. 1645 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1646 // Do not try to legalize the target-specific arguments (#1+), except for 1647 // an optional flag input. 1648 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1649 if (Tmp1 != Node->getOperand(0)) { 1650 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1651 Ops[0] = Tmp1; 1652 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1653 } 1654 } else { 1655 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1656 if (Tmp1 != Node->getOperand(0) || 1657 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1658 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1659 Ops[0] = Tmp1; 1660 Ops.back() = Tmp2; 1661 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1662 } 1663 } 1664 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1665 // This finishes up call legalization. 1666 IsLegalizingCall = false; 1667 1668 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1669 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1670 if (Node->getNumValues() == 2) 1671 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1672 return Result.getValue(Op.ResNo); 1673 case ISD::DYNAMIC_STACKALLOC: { 1674 MVT VT = Node->getValueType(0); 1675 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1676 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1677 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1678 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1679 1680 Tmp1 = Result.getValue(0); 1681 Tmp2 = Result.getValue(1); 1682 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1683 default: assert(0 && "This action is not supported yet!"); 1684 case TargetLowering::Expand: { 1685 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1686 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1687 " not tell us which reg is the stack pointer!"); 1688 SDOperand Chain = Tmp1.getOperand(0); 1689 1690 // Chain the dynamic stack allocation so that it doesn't modify the stack 1691 // pointer when other instructions are using the stack. 1692 Chain = DAG.getCALLSEQ_START(Chain, 1693 DAG.getConstant(0, TLI.getPointerTy())); 1694 1695 SDOperand Size = Tmp2.getOperand(1); 1696 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1697 Chain = SP.getValue(1); 1698 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue(); 1699 unsigned StackAlign = 1700 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1701 if (Align > StackAlign) 1702 SP = DAG.getNode(ISD::AND, VT, SP, 1703 DAG.getConstant(-(uint64_t)Align, VT)); 1704 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1705 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1706 1707 Tmp2 = 1708 DAG.getCALLSEQ_END(Chain, 1709 DAG.getConstant(0, TLI.getPointerTy()), 1710 DAG.getConstant(0, TLI.getPointerTy()), 1711 SDOperand()); 1712 1713 Tmp1 = LegalizeOp(Tmp1); 1714 Tmp2 = LegalizeOp(Tmp2); 1715 break; 1716 } 1717 case TargetLowering::Custom: 1718 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1719 if (Tmp3.Val) { 1720 Tmp1 = LegalizeOp(Tmp3); 1721 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1722 } 1723 break; 1724 case TargetLowering::Legal: 1725 break; 1726 } 1727 // Since this op produce two values, make sure to remember that we 1728 // legalized both of them. 1729 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 1730 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 1731 return Op.ResNo ? Tmp2 : Tmp1; 1732 } 1733 case ISD::INLINEASM: { 1734 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end()); 1735 bool Changed = false; 1736 // Legalize all of the operands of the inline asm, in case they are nodes 1737 // that need to be expanded or something. Note we skip the asm string and 1738 // all of the TargetConstant flags. 1739 SDOperand Op = LegalizeOp(Ops[0]); 1740 Changed = Op != Ops[0]; 1741 Ops[0] = Op; 1742 1743 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1744 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1745 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3; 1746 for (++i; NumVals; ++i, --NumVals) { 1747 SDOperand Op = LegalizeOp(Ops[i]); 1748 if (Op != Ops[i]) { 1749 Changed = true; 1750 Ops[i] = Op; 1751 } 1752 } 1753 } 1754 1755 if (HasInFlag) { 1756 Op = LegalizeOp(Ops.back()); 1757 Changed |= Op != Ops.back(); 1758 Ops.back() = Op; 1759 } 1760 1761 if (Changed) 1762 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1763 1764 // INLINE asm returns a chain and flag, make sure to add both to the map. 1765 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 1766 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 1767 return Result.getValue(Op.ResNo); 1768 } 1769 case ISD::BR: 1770 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1771 // Ensure that libcalls are emitted before a branch. 1772 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1773 Tmp1 = LegalizeOp(Tmp1); 1774 LastCALLSEQ_END = DAG.getEntryNode(); 1775 1776 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1777 break; 1778 case ISD::BRIND: 1779 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1780 // Ensure that libcalls are emitted before a branch. 1781 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1782 Tmp1 = LegalizeOp(Tmp1); 1783 LastCALLSEQ_END = DAG.getEntryNode(); 1784 1785 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1786 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1787 case Legal: 1788 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1789 break; 1790 } 1791 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1792 break; 1793 case ISD::BR_JT: 1794 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1795 // Ensure that libcalls are emitted before a branch. 1796 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1797 Tmp1 = LegalizeOp(Tmp1); 1798 LastCALLSEQ_END = DAG.getEntryNode(); 1799 1800 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1801 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1802 1803 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1804 default: assert(0 && "This action is not supported yet!"); 1805 case TargetLowering::Legal: break; 1806 case TargetLowering::Custom: 1807 Tmp1 = TLI.LowerOperation(Result, DAG); 1808 if (Tmp1.Val) Result = Tmp1; 1809 break; 1810 case TargetLowering::Expand: { 1811 SDOperand Chain = Result.getOperand(0); 1812 SDOperand Table = Result.getOperand(1); 1813 SDOperand Index = Result.getOperand(2); 1814 1815 MVT PTy = TLI.getPointerTy(); 1816 MachineFunction &MF = DAG.getMachineFunction(); 1817 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1818 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1819 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1820 1821 SDOperand LD; 1822 switch (EntrySize) { 1823 default: assert(0 && "Size of jump table not supported yet."); break; 1824 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, 1825 PseudoSourceValue::getJumpTable(), 0); break; 1826 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, 1827 PseudoSourceValue::getJumpTable(), 0); break; 1828 } 1829 1830 Addr = LD; 1831 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1832 // For PIC, the sequence is: 1833 // BRIND(load(Jumptable + index) + RelocBase) 1834 // RelocBase can be JumpTable, GOT or some sort of global base. 1835 if (PTy != MVT::i32) 1836 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1837 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1838 TLI.getPICJumpTableRelocBase(Table, DAG)); 1839 } 1840 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1841 } 1842 } 1843 break; 1844 case ISD::BRCOND: 1845 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1846 // Ensure that libcalls are emitted before a return. 1847 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1848 Tmp1 = LegalizeOp(Tmp1); 1849 LastCALLSEQ_END = DAG.getEntryNode(); 1850 1851 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1852 case Expand: assert(0 && "It's impossible to expand bools"); 1853 case Legal: 1854 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1855 break; 1856 case Promote: { 1857 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1858 1859 // The top bits of the promoted condition are not necessarily zero, ensure 1860 // that the value is properly zero extended. 1861 unsigned BitWidth = Tmp2.getValueSizeInBits(); 1862 if (!DAG.MaskedValueIsZero(Tmp2, 1863 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 1864 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1865 break; 1866 } 1867 } 1868 1869 // Basic block destination (Op#2) is always legal. 1870 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1871 1872 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1873 default: assert(0 && "This action is not supported yet!"); 1874 case TargetLowering::Legal: break; 1875 case TargetLowering::Custom: 1876 Tmp1 = TLI.LowerOperation(Result, DAG); 1877 if (Tmp1.Val) Result = Tmp1; 1878 break; 1879 case TargetLowering::Expand: 1880 // Expand brcond's setcc into its constituent parts and create a BR_CC 1881 // Node. 1882 if (Tmp2.getOpcode() == ISD::SETCC) { 1883 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1884 Tmp2.getOperand(0), Tmp2.getOperand(1), 1885 Node->getOperand(2)); 1886 } else { 1887 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1888 DAG.getCondCode(ISD::SETNE), Tmp2, 1889 DAG.getConstant(0, Tmp2.getValueType()), 1890 Node->getOperand(2)); 1891 } 1892 break; 1893 } 1894 break; 1895 case ISD::BR_CC: 1896 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1897 // Ensure that libcalls are emitted before a branch. 1898 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1899 Tmp1 = LegalizeOp(Tmp1); 1900 Tmp2 = Node->getOperand(2); // LHS 1901 Tmp3 = Node->getOperand(3); // RHS 1902 Tmp4 = Node->getOperand(1); // CC 1903 1904 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1905 LastCALLSEQ_END = DAG.getEntryNode(); 1906 1907 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1908 // the LHS is a legal SETCC itself. In this case, we need to compare 1909 // the result against zero to select between true and false values. 1910 if (Tmp3.Val == 0) { 1911 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1912 Tmp4 = DAG.getCondCode(ISD::SETNE); 1913 } 1914 1915 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1916 Node->getOperand(4)); 1917 1918 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1919 default: assert(0 && "Unexpected action for BR_CC!"); 1920 case TargetLowering::Legal: break; 1921 case TargetLowering::Custom: 1922 Tmp4 = TLI.LowerOperation(Result, DAG); 1923 if (Tmp4.Val) Result = Tmp4; 1924 break; 1925 } 1926 break; 1927 case ISD::LOAD: { 1928 LoadSDNode *LD = cast<LoadSDNode>(Node); 1929 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1930 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1931 1932 ISD::LoadExtType ExtType = LD->getExtensionType(); 1933 if (ExtType == ISD::NON_EXTLOAD) { 1934 MVT VT = Node->getValueType(0); 1935 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1936 Tmp3 = Result.getValue(0); 1937 Tmp4 = Result.getValue(1); 1938 1939 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1940 default: assert(0 && "This action is not supported yet!"); 1941 case TargetLowering::Legal: 1942 // If this is an unaligned load and the target doesn't support it, 1943 // expand it. 1944 if (!TLI.allowsUnalignedMemoryAccesses()) { 1945 unsigned ABIAlignment = TLI.getTargetData()-> 1946 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 1947 if (LD->getAlignment() < ABIAlignment){ 1948 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 1949 TLI); 1950 Tmp3 = Result.getOperand(0); 1951 Tmp4 = Result.getOperand(1); 1952 Tmp3 = LegalizeOp(Tmp3); 1953 Tmp4 = LegalizeOp(Tmp4); 1954 } 1955 } 1956 break; 1957 case TargetLowering::Custom: 1958 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1959 if (Tmp1.Val) { 1960 Tmp3 = LegalizeOp(Tmp1); 1961 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1962 } 1963 break; 1964 case TargetLowering::Promote: { 1965 // Only promote a load of vector type to another. 1966 assert(VT.isVector() && "Cannot promote this load!"); 1967 // Change base type to a different vector type. 1968 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1969 1970 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1971 LD->getSrcValueOffset(), 1972 LD->isVolatile(), LD->getAlignment()); 1973 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1974 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1975 break; 1976 } 1977 } 1978 // Since loads produce two values, make sure to remember that we 1979 // legalized both of them. 1980 AddLegalizedOperand(SDOperand(Node, 0), Tmp3); 1981 AddLegalizedOperand(SDOperand(Node, 1), Tmp4); 1982 return Op.ResNo ? Tmp4 : Tmp3; 1983 } else { 1984 MVT SrcVT = LD->getMemoryVT(); 1985 unsigned SrcWidth = SrcVT.getSizeInBits(); 1986 int SVOffset = LD->getSrcValueOffset(); 1987 unsigned Alignment = LD->getAlignment(); 1988 bool isVolatile = LD->isVolatile(); 1989 1990 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1991 // Some targets pretend to have an i1 loading operation, and actually 1992 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1993 // bits are guaranteed to be zero; it helps the optimizers understand 1994 // that these bits are zero. It is also useful for EXTLOAD, since it 1995 // tells the optimizers that those bits are undefined. It would be 1996 // nice to have an effective generic way of getting these benefits... 1997 // Until such a way is found, don't insist on promoting i1 here. 1998 (SrcVT != MVT::i1 || 1999 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 2000 // Promote to a byte-sized load if not loading an integral number of 2001 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 2002 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 2003 MVT NVT = MVT::getIntegerVT(NewWidth); 2004 SDOperand Ch; 2005 2006 // The extra bits are guaranteed to be zero, since we stored them that 2007 // way. A zext load from NVT thus automatically gives zext from SrcVT. 2008 2009 ISD::LoadExtType NewExtType = 2010 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2011 2012 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 2013 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2014 NVT, isVolatile, Alignment); 2015 2016 Ch = Result.getValue(1); // The chain. 2017 2018 if (ExtType == ISD::SEXTLOAD) 2019 // Having the top bits zero doesn't help when sign extending. 2020 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2021 Result, DAG.getValueType(SrcVT)); 2022 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2023 // All the top bits are guaranteed to be zero - inform the optimizers. 2024 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 2025 DAG.getValueType(SrcVT)); 2026 2027 Tmp1 = LegalizeOp(Result); 2028 Tmp2 = LegalizeOp(Ch); 2029 } else if (SrcWidth & (SrcWidth - 1)) { 2030 // If not loading a power-of-2 number of bits, expand as two loads. 2031 assert(SrcVT.isExtended() && !SrcVT.isVector() && 2032 "Unsupported extload!"); 2033 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2034 assert(RoundWidth < SrcWidth); 2035 unsigned ExtraWidth = SrcWidth - RoundWidth; 2036 assert(ExtraWidth < RoundWidth); 2037 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2038 "Load size not an integral number of bytes!"); 2039 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2040 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2041 SDOperand Lo, Hi, Ch; 2042 unsigned IncrementSize; 2043 2044 if (TLI.isLittleEndian()) { 2045 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2046 // Load the bottom RoundWidth bits. 2047 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2048 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2049 Alignment); 2050 2051 // Load the remaining ExtraWidth bits. 2052 IncrementSize = RoundWidth / 8; 2053 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2054 DAG.getIntPtrConstant(IncrementSize)); 2055 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2056 LD->getSrcValue(), SVOffset + IncrementSize, 2057 ExtraVT, isVolatile, 2058 MinAlign(Alignment, IncrementSize)); 2059 2060 // Build a factor node to remember that this load is independent of the 2061 // other one. 2062 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2063 Hi.getValue(1)); 2064 2065 // Move the top bits to the right place. 2066 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2067 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2068 2069 // Join the hi and lo parts. 2070 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2071 } else { 2072 // Big endian - avoid unaligned loads. 2073 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2074 // Load the top RoundWidth bits. 2075 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2076 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2077 Alignment); 2078 2079 // Load the remaining ExtraWidth bits. 2080 IncrementSize = RoundWidth / 8; 2081 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2082 DAG.getIntPtrConstant(IncrementSize)); 2083 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2084 LD->getSrcValue(), SVOffset + IncrementSize, 2085 ExtraVT, isVolatile, 2086 MinAlign(Alignment, IncrementSize)); 2087 2088 // Build a factor node to remember that this load is independent of the 2089 // other one. 2090 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2091 Hi.getValue(1)); 2092 2093 // Move the top bits to the right place. 2094 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2095 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2096 2097 // Join the hi and lo parts. 2098 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2099 } 2100 2101 Tmp1 = LegalizeOp(Result); 2102 Tmp2 = LegalizeOp(Ch); 2103 } else { 2104 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 2105 default: assert(0 && "This action is not supported yet!"); 2106 case TargetLowering::Custom: 2107 isCustom = true; 2108 // FALLTHROUGH 2109 case TargetLowering::Legal: 2110 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2111 Tmp1 = Result.getValue(0); 2112 Tmp2 = Result.getValue(1); 2113 2114 if (isCustom) { 2115 Tmp3 = TLI.LowerOperation(Result, DAG); 2116 if (Tmp3.Val) { 2117 Tmp1 = LegalizeOp(Tmp3); 2118 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2119 } 2120 } else { 2121 // If this is an unaligned load and the target doesn't support it, 2122 // expand it. 2123 if (!TLI.allowsUnalignedMemoryAccesses()) { 2124 unsigned ABIAlignment = TLI.getTargetData()-> 2125 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2126 if (LD->getAlignment() < ABIAlignment){ 2127 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG, 2128 TLI); 2129 Tmp1 = Result.getOperand(0); 2130 Tmp2 = Result.getOperand(1); 2131 Tmp1 = LegalizeOp(Tmp1); 2132 Tmp2 = LegalizeOp(Tmp2); 2133 } 2134 } 2135 } 2136 break; 2137 case TargetLowering::Expand: 2138 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2139 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2140 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2141 LD->getSrcValueOffset(), 2142 LD->isVolatile(), LD->getAlignment()); 2143 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2144 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2145 Tmp2 = LegalizeOp(Load.getValue(1)); 2146 break; 2147 } 2148 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2149 // Turn the unsupported load into an EXTLOAD followed by an explicit 2150 // zero/sign extend inreg. 2151 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2152 Tmp1, Tmp2, LD->getSrcValue(), 2153 LD->getSrcValueOffset(), SrcVT, 2154 LD->isVolatile(), LD->getAlignment()); 2155 SDOperand ValRes; 2156 if (ExtType == ISD::SEXTLOAD) 2157 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2158 Result, DAG.getValueType(SrcVT)); 2159 else 2160 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2161 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2162 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2163 break; 2164 } 2165 } 2166 2167 // Since loads produce two values, make sure to remember that we legalized 2168 // both of them. 2169 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2170 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2171 return Op.ResNo ? Tmp2 : Tmp1; 2172 } 2173 } 2174 case ISD::EXTRACT_ELEMENT: { 2175 MVT OpTy = Node->getOperand(0).getValueType(); 2176 switch (getTypeAction(OpTy)) { 2177 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2178 case Legal: 2179 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) { 2180 // 1 -> Hi 2181 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2182 DAG.getConstant(OpTy.getSizeInBits()/2, 2183 TLI.getShiftAmountTy())); 2184 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2185 } else { 2186 // 0 -> Lo 2187 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2188 Node->getOperand(0)); 2189 } 2190 break; 2191 case Expand: 2192 // Get both the low and high parts. 2193 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2194 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 2195 Result = Tmp2; // 1 -> Hi 2196 else 2197 Result = Tmp1; // 0 -> Lo 2198 break; 2199 } 2200 break; 2201 } 2202 2203 case ISD::CopyToReg: 2204 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2205 2206 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2207 "Register type must be legal!"); 2208 // Legalize the incoming value (must be a legal type). 2209 Tmp2 = LegalizeOp(Node->getOperand(2)); 2210 if (Node->getNumValues() == 1) { 2211 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2212 } else { 2213 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2214 if (Node->getNumOperands() == 4) { 2215 Tmp3 = LegalizeOp(Node->getOperand(3)); 2216 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2217 Tmp3); 2218 } else { 2219 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2220 } 2221 2222 // Since this produces two values, make sure to remember that we legalized 2223 // both of them. 2224 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 2225 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 2226 return Result; 2227 } 2228 break; 2229 2230 case ISD::RET: 2231 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2232 2233 // Ensure that libcalls are emitted before a return. 2234 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2235 Tmp1 = LegalizeOp(Tmp1); 2236 LastCALLSEQ_END = DAG.getEntryNode(); 2237 2238 switch (Node->getNumOperands()) { 2239 case 3: // ret val 2240 Tmp2 = Node->getOperand(1); 2241 Tmp3 = Node->getOperand(2); // Signness 2242 switch (getTypeAction(Tmp2.getValueType())) { 2243 case Legal: 2244 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2245 break; 2246 case Expand: 2247 if (!Tmp2.getValueType().isVector()) { 2248 SDOperand Lo, Hi; 2249 ExpandOp(Tmp2, Lo, Hi); 2250 2251 // Big endian systems want the hi reg first. 2252 if (TLI.isBigEndian()) 2253 std::swap(Lo, Hi); 2254 2255 if (Hi.Val) 2256 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2257 else 2258 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2259 Result = LegalizeOp(Result); 2260 } else { 2261 SDNode *InVal = Tmp2.Val; 2262 int InIx = Tmp2.ResNo; 2263 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 2264 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 2265 2266 // Figure out if there is a simple type corresponding to this Vector 2267 // type. If so, convert to the vector type. 2268 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2269 if (TLI.isTypeLegal(TVT)) { 2270 // Turn this into a return of the vector type. 2271 Tmp2 = LegalizeOp(Tmp2); 2272 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2273 } else if (NumElems == 1) { 2274 // Turn this into a return of the scalar type. 2275 Tmp2 = ScalarizeVectorOp(Tmp2); 2276 Tmp2 = LegalizeOp(Tmp2); 2277 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2278 2279 // FIXME: Returns of gcc generic vectors smaller than a legal type 2280 // should be returned in integer registers! 2281 2282 // The scalarized value type may not be legal, e.g. it might require 2283 // promotion or expansion. Relegalize the return. 2284 Result = LegalizeOp(Result); 2285 } else { 2286 // FIXME: Returns of gcc generic vectors larger than a legal vector 2287 // type should be returned by reference! 2288 SDOperand Lo, Hi; 2289 SplitVectorOp(Tmp2, Lo, Hi); 2290 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2291 Result = LegalizeOp(Result); 2292 } 2293 } 2294 break; 2295 case Promote: 2296 Tmp2 = PromoteOp(Node->getOperand(1)); 2297 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2298 Result = LegalizeOp(Result); 2299 break; 2300 } 2301 break; 2302 case 1: // ret void 2303 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2304 break; 2305 default: { // ret <values> 2306 SmallVector<SDOperand, 8> NewValues; 2307 NewValues.push_back(Tmp1); 2308 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2309 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2310 case Legal: 2311 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2312 NewValues.push_back(Node->getOperand(i+1)); 2313 break; 2314 case Expand: { 2315 SDOperand Lo, Hi; 2316 assert(!Node->getOperand(i).getValueType().isExtended() && 2317 "FIXME: TODO: implement returning non-legal vector types!"); 2318 ExpandOp(Node->getOperand(i), Lo, Hi); 2319 NewValues.push_back(Lo); 2320 NewValues.push_back(Node->getOperand(i+1)); 2321 if (Hi.Val) { 2322 NewValues.push_back(Hi); 2323 NewValues.push_back(Node->getOperand(i+1)); 2324 } 2325 break; 2326 } 2327 case Promote: 2328 assert(0 && "Can't promote multiple return value yet!"); 2329 } 2330 2331 if (NewValues.size() == Node->getNumOperands()) 2332 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2333 else 2334 Result = DAG.getNode(ISD::RET, MVT::Other, 2335 &NewValues[0], NewValues.size()); 2336 break; 2337 } 2338 } 2339 2340 if (Result.getOpcode() == ISD::RET) { 2341 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2342 default: assert(0 && "This action is not supported yet!"); 2343 case TargetLowering::Legal: break; 2344 case TargetLowering::Custom: 2345 Tmp1 = TLI.LowerOperation(Result, DAG); 2346 if (Tmp1.Val) Result = Tmp1; 2347 break; 2348 } 2349 } 2350 break; 2351 case ISD::STORE: { 2352 StoreSDNode *ST = cast<StoreSDNode>(Node); 2353 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2354 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2355 int SVOffset = ST->getSrcValueOffset(); 2356 unsigned Alignment = ST->getAlignment(); 2357 bool isVolatile = ST->isVolatile(); 2358 2359 if (!ST->isTruncatingStore()) { 2360 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2361 // FIXME: We shouldn't do this for TargetConstantFP's. 2362 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2363 // to phase ordering between legalized code and the dag combiner. This 2364 // probably means that we need to integrate dag combiner and legalizer 2365 // together. 2366 // We generally can't do this one for long doubles. 2367 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2368 if (CFP->getValueType(0) == MVT::f32 && 2369 getTypeAction(MVT::i32) == Legal) { 2370 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2371 convertToAPInt().zextOrTrunc(32), 2372 MVT::i32); 2373 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2374 SVOffset, isVolatile, Alignment); 2375 break; 2376 } else if (CFP->getValueType(0) == MVT::f64) { 2377 // If this target supports 64-bit registers, do a single 64-bit store. 2378 if (getTypeAction(MVT::i64) == Legal) { 2379 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2380 zextOrTrunc(64), MVT::i64); 2381 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2382 SVOffset, isVolatile, Alignment); 2383 break; 2384 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 2385 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2386 // stores. If the target supports neither 32- nor 64-bits, this 2387 // xform is certainly not worth it. 2388 const APInt &IntVal =CFP->getValueAPF().convertToAPInt(); 2389 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2390 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2391 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2392 2393 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2394 SVOffset, isVolatile, Alignment); 2395 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2396 DAG.getIntPtrConstant(4)); 2397 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2398 isVolatile, MinAlign(Alignment, 4U)); 2399 2400 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2401 break; 2402 } 2403 } 2404 } 2405 2406 switch (getTypeAction(ST->getMemoryVT())) { 2407 case Legal: { 2408 Tmp3 = LegalizeOp(ST->getValue()); 2409 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2410 ST->getOffset()); 2411 2412 MVT VT = Tmp3.getValueType(); 2413 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2414 default: assert(0 && "This action is not supported yet!"); 2415 case TargetLowering::Legal: 2416 // If this is an unaligned store and the target doesn't support it, 2417 // expand it. 2418 if (!TLI.allowsUnalignedMemoryAccesses()) { 2419 unsigned ABIAlignment = TLI.getTargetData()-> 2420 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2421 if (ST->getAlignment() < ABIAlignment) 2422 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2423 TLI); 2424 } 2425 break; 2426 case TargetLowering::Custom: 2427 Tmp1 = TLI.LowerOperation(Result, DAG); 2428 if (Tmp1.Val) Result = Tmp1; 2429 break; 2430 case TargetLowering::Promote: 2431 assert(VT.isVector() && "Unknown legal promote case!"); 2432 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2433 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2434 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2435 ST->getSrcValue(), SVOffset, isVolatile, 2436 Alignment); 2437 break; 2438 } 2439 break; 2440 } 2441 case Promote: 2442 // Truncate the value and store the result. 2443 Tmp3 = PromoteOp(ST->getValue()); 2444 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2445 SVOffset, ST->getMemoryVT(), 2446 isVolatile, Alignment); 2447 break; 2448 2449 case Expand: 2450 unsigned IncrementSize = 0; 2451 SDOperand Lo, Hi; 2452 2453 // If this is a vector type, then we have to calculate the increment as 2454 // the product of the element size in bytes, and the number of elements 2455 // in the high half of the vector. 2456 if (ST->getValue().getValueType().isVector()) { 2457 SDNode *InVal = ST->getValue().Val; 2458 int InIx = ST->getValue().ResNo; 2459 MVT InVT = InVal->getValueType(InIx); 2460 unsigned NumElems = InVT.getVectorNumElements(); 2461 MVT EVT = InVT.getVectorElementType(); 2462 2463 // Figure out if there is a simple type corresponding to this Vector 2464 // type. If so, convert to the vector type. 2465 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2466 if (TLI.isTypeLegal(TVT)) { 2467 // Turn this into a normal store of the vector type. 2468 Tmp3 = LegalizeOp(ST->getValue()); 2469 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2470 SVOffset, isVolatile, Alignment); 2471 Result = LegalizeOp(Result); 2472 break; 2473 } else if (NumElems == 1) { 2474 // Turn this into a normal store of the scalar type. 2475 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2476 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2477 SVOffset, isVolatile, Alignment); 2478 // The scalarized value type may not be legal, e.g. it might require 2479 // promotion or expansion. Relegalize the scalar store. 2480 Result = LegalizeOp(Result); 2481 break; 2482 } else { 2483 SplitVectorOp(ST->getValue(), Lo, Hi); 2484 IncrementSize = Lo.Val->getValueType(0).getVectorNumElements() * 2485 EVT.getSizeInBits()/8; 2486 } 2487 } else { 2488 ExpandOp(ST->getValue(), Lo, Hi); 2489 IncrementSize = Hi.Val ? Hi.getValueType().getSizeInBits()/8 : 0; 2490 2491 if (TLI.isBigEndian()) 2492 std::swap(Lo, Hi); 2493 } 2494 2495 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2496 SVOffset, isVolatile, Alignment); 2497 2498 if (Hi.Val == NULL) { 2499 // Must be int <-> float one-to-one expansion. 2500 Result = Lo; 2501 break; 2502 } 2503 2504 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2505 DAG.getIntPtrConstant(IncrementSize)); 2506 assert(isTypeLegal(Tmp2.getValueType()) && 2507 "Pointers must be legal!"); 2508 SVOffset += IncrementSize; 2509 Alignment = MinAlign(Alignment, IncrementSize); 2510 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2511 SVOffset, isVolatile, Alignment); 2512 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2513 break; 2514 } 2515 } else { 2516 switch (getTypeAction(ST->getValue().getValueType())) { 2517 case Legal: 2518 Tmp3 = LegalizeOp(ST->getValue()); 2519 break; 2520 case Promote: 2521 // We can promote the value, the truncstore will still take care of it. 2522 Tmp3 = PromoteOp(ST->getValue()); 2523 break; 2524 case Expand: 2525 // Just store the low part. This may become a non-trunc store, so make 2526 // sure to use getTruncStore, not UpdateNodeOperands below. 2527 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2528 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2529 SVOffset, MVT::i8, isVolatile, Alignment); 2530 } 2531 2532 MVT StVT = ST->getMemoryVT(); 2533 unsigned StWidth = StVT.getSizeInBits(); 2534 2535 if (StWidth != StVT.getStoreSizeInBits()) { 2536 // Promote to a byte-sized store with upper bits zero if not 2537 // storing an integral number of bytes. For example, promote 2538 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2539 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 2540 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2541 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2542 SVOffset, NVT, isVolatile, Alignment); 2543 } else if (StWidth & (StWidth - 1)) { 2544 // If not storing a power-of-2 number of bits, expand as two stores. 2545 assert(StVT.isExtended() && !StVT.isVector() && 2546 "Unsupported truncstore!"); 2547 unsigned RoundWidth = 1 << Log2_32(StWidth); 2548 assert(RoundWidth < StWidth); 2549 unsigned ExtraWidth = StWidth - RoundWidth; 2550 assert(ExtraWidth < RoundWidth); 2551 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2552 "Store size not an integral number of bytes!"); 2553 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2554 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2555 SDOperand Lo, Hi; 2556 unsigned IncrementSize; 2557 2558 if (TLI.isLittleEndian()) { 2559 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2560 // Store the bottom RoundWidth bits. 2561 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2562 SVOffset, RoundVT, 2563 isVolatile, Alignment); 2564 2565 // Store the remaining ExtraWidth bits. 2566 IncrementSize = RoundWidth / 8; 2567 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2568 DAG.getIntPtrConstant(IncrementSize)); 2569 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2570 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2571 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2572 SVOffset + IncrementSize, ExtraVT, isVolatile, 2573 MinAlign(Alignment, IncrementSize)); 2574 } else { 2575 // Big endian - avoid unaligned stores. 2576 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2577 // Store the top RoundWidth bits. 2578 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2579 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2580 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2581 RoundVT, isVolatile, Alignment); 2582 2583 // Store the remaining ExtraWidth bits. 2584 IncrementSize = RoundWidth / 8; 2585 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2586 DAG.getIntPtrConstant(IncrementSize)); 2587 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2588 SVOffset + IncrementSize, ExtraVT, isVolatile, 2589 MinAlign(Alignment, IncrementSize)); 2590 } 2591 2592 // The order of the stores doesn't matter. 2593 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2594 } else { 2595 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2596 Tmp2 != ST->getBasePtr()) 2597 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2598 ST->getOffset()); 2599 2600 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2601 default: assert(0 && "This action is not supported yet!"); 2602 case TargetLowering::Legal: 2603 // If this is an unaligned store and the target doesn't support it, 2604 // expand it. 2605 if (!TLI.allowsUnalignedMemoryAccesses()) { 2606 unsigned ABIAlignment = TLI.getTargetData()-> 2607 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2608 if (ST->getAlignment() < ABIAlignment) 2609 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG, 2610 TLI); 2611 } 2612 break; 2613 case TargetLowering::Custom: 2614 Result = TLI.LowerOperation(Result, DAG); 2615 break; 2616 case Expand: 2617 // TRUNCSTORE:i16 i32 -> STORE i16 2618 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2619 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2620 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2621 isVolatile, Alignment); 2622 break; 2623 } 2624 } 2625 } 2626 break; 2627 } 2628 case ISD::PCMARKER: 2629 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2630 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2631 break; 2632 case ISD::STACKSAVE: 2633 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2634 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2635 Tmp1 = Result.getValue(0); 2636 Tmp2 = Result.getValue(1); 2637 2638 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2639 default: assert(0 && "This action is not supported yet!"); 2640 case TargetLowering::Legal: break; 2641 case TargetLowering::Custom: 2642 Tmp3 = TLI.LowerOperation(Result, DAG); 2643 if (Tmp3.Val) { 2644 Tmp1 = LegalizeOp(Tmp3); 2645 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2646 } 2647 break; 2648 case TargetLowering::Expand: 2649 // Expand to CopyFromReg if the target set 2650 // StackPointerRegisterToSaveRestore. 2651 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2652 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2653 Node->getValueType(0)); 2654 Tmp2 = Tmp1.getValue(1); 2655 } else { 2656 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2657 Tmp2 = Node->getOperand(0); 2658 } 2659 break; 2660 } 2661 2662 // Since stacksave produce two values, make sure to remember that we 2663 // legalized both of them. 2664 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2665 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2666 return Op.ResNo ? Tmp2 : Tmp1; 2667 2668 case ISD::STACKRESTORE: 2669 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2670 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2671 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2672 2673 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2674 default: assert(0 && "This action is not supported yet!"); 2675 case TargetLowering::Legal: break; 2676 case TargetLowering::Custom: 2677 Tmp1 = TLI.LowerOperation(Result, DAG); 2678 if (Tmp1.Val) Result = Tmp1; 2679 break; 2680 case TargetLowering::Expand: 2681 // Expand to CopyToReg if the target set 2682 // StackPointerRegisterToSaveRestore. 2683 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2684 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2685 } else { 2686 Result = Tmp1; 2687 } 2688 break; 2689 } 2690 break; 2691 2692 case ISD::READCYCLECOUNTER: 2693 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2694 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2695 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2696 Node->getValueType(0))) { 2697 default: assert(0 && "This action is not supported yet!"); 2698 case TargetLowering::Legal: 2699 Tmp1 = Result.getValue(0); 2700 Tmp2 = Result.getValue(1); 2701 break; 2702 case TargetLowering::Custom: 2703 Result = TLI.LowerOperation(Result, DAG); 2704 Tmp1 = LegalizeOp(Result.getValue(0)); 2705 Tmp2 = LegalizeOp(Result.getValue(1)); 2706 break; 2707 } 2708 2709 // Since rdcc produce two values, make sure to remember that we legalized 2710 // both of them. 2711 AddLegalizedOperand(SDOperand(Node, 0), Tmp1); 2712 AddLegalizedOperand(SDOperand(Node, 1), Tmp2); 2713 return Result; 2714 2715 case ISD::SELECT: 2716 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2717 case Expand: assert(0 && "It's impossible to expand bools"); 2718 case Legal: 2719 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2720 break; 2721 case Promote: { 2722 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2723 // Make sure the condition is either zero or one. 2724 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2725 if (!DAG.MaskedValueIsZero(Tmp1, 2726 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2727 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2728 break; 2729 } 2730 } 2731 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2732 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2733 2734 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2735 2736 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2737 default: assert(0 && "This action is not supported yet!"); 2738 case TargetLowering::Legal: break; 2739 case TargetLowering::Custom: { 2740 Tmp1 = TLI.LowerOperation(Result, DAG); 2741 if (Tmp1.Val) Result = Tmp1; 2742 break; 2743 } 2744 case TargetLowering::Expand: 2745 if (Tmp1.getOpcode() == ISD::SETCC) { 2746 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2747 Tmp2, Tmp3, 2748 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2749 } else { 2750 Result = DAG.getSelectCC(Tmp1, 2751 DAG.getConstant(0, Tmp1.getValueType()), 2752 Tmp2, Tmp3, ISD::SETNE); 2753 } 2754 break; 2755 case TargetLowering::Promote: { 2756 MVT NVT = 2757 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2758 unsigned ExtOp, TruncOp; 2759 if (Tmp2.getValueType().isVector()) { 2760 ExtOp = ISD::BIT_CONVERT; 2761 TruncOp = ISD::BIT_CONVERT; 2762 } else if (Tmp2.getValueType().isInteger()) { 2763 ExtOp = ISD::ANY_EXTEND; 2764 TruncOp = ISD::TRUNCATE; 2765 } else { 2766 ExtOp = ISD::FP_EXTEND; 2767 TruncOp = ISD::FP_ROUND; 2768 } 2769 // Promote each of the values to the new type. 2770 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2771 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2772 // Perform the larger operation, then round down. 2773 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2774 if (TruncOp != ISD::FP_ROUND) 2775 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2776 else 2777 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2778 DAG.getIntPtrConstant(0)); 2779 break; 2780 } 2781 } 2782 break; 2783 case ISD::SELECT_CC: { 2784 Tmp1 = Node->getOperand(0); // LHS 2785 Tmp2 = Node->getOperand(1); // RHS 2786 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2787 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2788 SDOperand CC = Node->getOperand(4); 2789 2790 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2791 2792 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2793 // the LHS is a legal SETCC itself. In this case, we need to compare 2794 // the result against zero to select between true and false values. 2795 if (Tmp2.Val == 0) { 2796 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2797 CC = DAG.getCondCode(ISD::SETNE); 2798 } 2799 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2800 2801 // Everything is legal, see if we should expand this op or something. 2802 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2803 default: assert(0 && "This action is not supported yet!"); 2804 case TargetLowering::Legal: break; 2805 case TargetLowering::Custom: 2806 Tmp1 = TLI.LowerOperation(Result, DAG); 2807 if (Tmp1.Val) Result = Tmp1; 2808 break; 2809 } 2810 break; 2811 } 2812 case ISD::SETCC: 2813 Tmp1 = Node->getOperand(0); 2814 Tmp2 = Node->getOperand(1); 2815 Tmp3 = Node->getOperand(2); 2816 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2817 2818 // If we had to Expand the SetCC operands into a SELECT node, then it may 2819 // not always be possible to return a true LHS & RHS. In this case, just 2820 // return the value we legalized, returned in the LHS 2821 if (Tmp2.Val == 0) { 2822 Result = Tmp1; 2823 break; 2824 } 2825 2826 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2827 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2828 case TargetLowering::Custom: 2829 isCustom = true; 2830 // FALLTHROUGH. 2831 case TargetLowering::Legal: 2832 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2833 if (isCustom) { 2834 Tmp4 = TLI.LowerOperation(Result, DAG); 2835 if (Tmp4.Val) Result = Tmp4; 2836 } 2837 break; 2838 case TargetLowering::Promote: { 2839 // First step, figure out the appropriate operation to use. 2840 // Allow SETCC to not be supported for all legal data types 2841 // Mostly this targets FP 2842 MVT NewInTy = Node->getOperand(0).getValueType(); 2843 MVT OldVT = NewInTy; OldVT = OldVT; 2844 2845 // Scan for the appropriate larger type to use. 2846 while (1) { 2847 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 2848 2849 assert(NewInTy.isInteger() == OldVT.isInteger() && 2850 "Fell off of the edge of the integer world"); 2851 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 2852 "Fell off of the edge of the floating point world"); 2853 2854 // If the target supports SETCC of this type, use it. 2855 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2856 break; 2857 } 2858 if (NewInTy.isInteger()) 2859 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2860 else { 2861 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2862 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2863 } 2864 Tmp1 = LegalizeOp(Tmp1); 2865 Tmp2 = LegalizeOp(Tmp2); 2866 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2867 Result = LegalizeOp(Result); 2868 break; 2869 } 2870 case TargetLowering::Expand: 2871 // Expand a setcc node into a select_cc of the same condition, lhs, and 2872 // rhs that selects between const 1 (true) and const 0 (false). 2873 MVT VT = Node->getValueType(0); 2874 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2875 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2876 Tmp3); 2877 break; 2878 } 2879 break; 2880 case ISD::VSETCC: { 2881 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2882 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2883 SDOperand CC = Node->getOperand(2); 2884 2885 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC); 2886 2887 // Everything is legal, see if we should expand this op or something. 2888 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) { 2889 default: assert(0 && "This action is not supported yet!"); 2890 case TargetLowering::Legal: break; 2891 case TargetLowering::Custom: 2892 Tmp1 = TLI.LowerOperation(Result, DAG); 2893 if (Tmp1.Val) Result = Tmp1; 2894 break; 2895 } 2896 break; 2897 } 2898 2899 case ISD::SHL_PARTS: 2900 case ISD::SRA_PARTS: 2901 case ISD::SRL_PARTS: { 2902 SmallVector<SDOperand, 8> Ops; 2903 bool Changed = false; 2904 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2905 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2906 Changed |= Ops.back() != Node->getOperand(i); 2907 } 2908 if (Changed) 2909 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2910 2911 switch (TLI.getOperationAction(Node->getOpcode(), 2912 Node->getValueType(0))) { 2913 default: assert(0 && "This action is not supported yet!"); 2914 case TargetLowering::Legal: break; 2915 case TargetLowering::Custom: 2916 Tmp1 = TLI.LowerOperation(Result, DAG); 2917 if (Tmp1.Val) { 2918 SDOperand Tmp2, RetVal(0, 0); 2919 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2920 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2921 AddLegalizedOperand(SDOperand(Node, i), Tmp2); 2922 if (i == Op.ResNo) 2923 RetVal = Tmp2; 2924 } 2925 assert(RetVal.Val && "Illegal result number"); 2926 return RetVal; 2927 } 2928 break; 2929 } 2930 2931 // Since these produce multiple values, make sure to remember that we 2932 // legalized all of them. 2933 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2934 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i)); 2935 return Result.getValue(Op.ResNo); 2936 } 2937 2938 // Binary operators 2939 case ISD::ADD: 2940 case ISD::SUB: 2941 case ISD::MUL: 2942 case ISD::MULHS: 2943 case ISD::MULHU: 2944 case ISD::UDIV: 2945 case ISD::SDIV: 2946 case ISD::AND: 2947 case ISD::OR: 2948 case ISD::XOR: 2949 case ISD::SHL: 2950 case ISD::SRL: 2951 case ISD::SRA: 2952 case ISD::FADD: 2953 case ISD::FSUB: 2954 case ISD::FMUL: 2955 case ISD::FDIV: 2956 case ISD::FPOW: 2957 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2958 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2959 case Expand: assert(0 && "Not possible"); 2960 case Legal: 2961 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2962 break; 2963 case Promote: 2964 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2965 break; 2966 } 2967 2968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2969 2970 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2971 default: assert(0 && "BinOp legalize operation not supported"); 2972 case TargetLowering::Legal: break; 2973 case TargetLowering::Custom: 2974 Tmp1 = TLI.LowerOperation(Result, DAG); 2975 if (Tmp1.Val) Result = Tmp1; 2976 break; 2977 case TargetLowering::Expand: { 2978 MVT VT = Op.getValueType(); 2979 2980 // See if multiply or divide can be lowered using two-result operations. 2981 SDVTList VTs = DAG.getVTList(VT, VT); 2982 if (Node->getOpcode() == ISD::MUL) { 2983 // We just need the low half of the multiply; try both the signed 2984 // and unsigned forms. If the target supports both SMUL_LOHI and 2985 // UMUL_LOHI, form a preference by checking which forms of plain 2986 // MULH it supports. 2987 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2988 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2989 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2990 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2991 unsigned OpToUse = 0; 2992 if (HasSMUL_LOHI && !HasMULHS) { 2993 OpToUse = ISD::SMUL_LOHI; 2994 } else if (HasUMUL_LOHI && !HasMULHU) { 2995 OpToUse = ISD::UMUL_LOHI; 2996 } else if (HasSMUL_LOHI) { 2997 OpToUse = ISD::SMUL_LOHI; 2998 } else if (HasUMUL_LOHI) { 2999 OpToUse = ISD::UMUL_LOHI; 3000 } 3001 if (OpToUse) { 3002 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0); 3003 break; 3004 } 3005 } 3006 if (Node->getOpcode() == ISD::MULHS && 3007 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 3008 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3009 break; 3010 } 3011 if (Node->getOpcode() == ISD::MULHU && 3012 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 3013 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1); 3014 break; 3015 } 3016 if (Node->getOpcode() == ISD::SDIV && 3017 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3018 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3019 break; 3020 } 3021 if (Node->getOpcode() == ISD::UDIV && 3022 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3023 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0); 3024 break; 3025 } 3026 3027 // Check to see if we have a libcall for this operator. 3028 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3029 bool isSigned = false; 3030 switch (Node->getOpcode()) { 3031 case ISD::UDIV: 3032 case ISD::SDIV: 3033 if (VT == MVT::i32) { 3034 LC = Node->getOpcode() == ISD::UDIV 3035 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3036 isSigned = Node->getOpcode() == ISD::SDIV; 3037 } 3038 break; 3039 case ISD::FPOW: 3040 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3041 RTLIB::POW_PPCF128); 3042 break; 3043 default: break; 3044 } 3045 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3046 SDOperand Dummy; 3047 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3048 break; 3049 } 3050 3051 assert(Node->getValueType(0).isVector() && 3052 "Cannot expand this binary operator!"); 3053 // Expand the operation into a bunch of nasty scalar code. 3054 Result = LegalizeOp(UnrollVectorOp(Op)); 3055 break; 3056 } 3057 case TargetLowering::Promote: { 3058 switch (Node->getOpcode()) { 3059 default: assert(0 && "Do not know how to promote this BinOp!"); 3060 case ISD::AND: 3061 case ISD::OR: 3062 case ISD::XOR: { 3063 MVT OVT = Node->getValueType(0); 3064 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3065 assert(OVT.isVector() && "Cannot promote this BinOp!"); 3066 // Bit convert each of the values to the new type. 3067 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3068 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3069 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3070 // Bit convert the result back the original type. 3071 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3072 break; 3073 } 3074 } 3075 } 3076 } 3077 break; 3078 3079 case ISD::SMUL_LOHI: 3080 case ISD::UMUL_LOHI: 3081 case ISD::SDIVREM: 3082 case ISD::UDIVREM: 3083 // These nodes will only be produced by target-specific lowering, so 3084 // they shouldn't be here if they aren't legal. 3085 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3086 "This must be legal!"); 3087 3088 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3089 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3090 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3091 break; 3092 3093 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3094 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3095 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3096 case Expand: assert(0 && "Not possible"); 3097 case Legal: 3098 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3099 break; 3100 case Promote: 3101 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3102 break; 3103 } 3104 3105 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3106 3107 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3108 default: assert(0 && "Operation not supported"); 3109 case TargetLowering::Custom: 3110 Tmp1 = TLI.LowerOperation(Result, DAG); 3111 if (Tmp1.Val) Result = Tmp1; 3112 break; 3113 case TargetLowering::Legal: break; 3114 case TargetLowering::Expand: { 3115 // If this target supports fabs/fneg natively and select is cheap, 3116 // do this efficiently. 3117 if (!TLI.isSelectExpensive() && 3118 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3119 TargetLowering::Legal && 3120 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3121 TargetLowering::Legal) { 3122 // Get the sign bit of the RHS. 3123 MVT IVT = 3124 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3125 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3126 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), 3127 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3128 // Get the absolute value of the result. 3129 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3130 // Select between the nabs and abs value based on the sign bit of 3131 // the input. 3132 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3133 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3134 AbsVal), 3135 AbsVal); 3136 Result = LegalizeOp(Result); 3137 break; 3138 } 3139 3140 // Otherwise, do bitwise ops! 3141 MVT NVT = 3142 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3143 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3144 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3145 Result = LegalizeOp(Result); 3146 break; 3147 } 3148 } 3149 break; 3150 3151 case ISD::ADDC: 3152 case ISD::SUBC: 3153 Tmp1 = LegalizeOp(Node->getOperand(0)); 3154 Tmp2 = LegalizeOp(Node->getOperand(1)); 3155 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3156 // Since this produces two values, make sure to remember that we legalized 3157 // both of them. 3158 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3159 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3160 return Result; 3161 3162 case ISD::ADDE: 3163 case ISD::SUBE: 3164 Tmp1 = LegalizeOp(Node->getOperand(0)); 3165 Tmp2 = LegalizeOp(Node->getOperand(1)); 3166 Tmp3 = LegalizeOp(Node->getOperand(2)); 3167 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3168 // Since this produces two values, make sure to remember that we legalized 3169 // both of them. 3170 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0)); 3171 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1)); 3172 return Result; 3173 3174 case ISD::BUILD_PAIR: { 3175 MVT PairTy = Node->getValueType(0); 3176 // TODO: handle the case where the Lo and Hi operands are not of legal type 3177 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3178 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3179 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3180 case TargetLowering::Promote: 3181 case TargetLowering::Custom: 3182 assert(0 && "Cannot promote/custom this yet!"); 3183 case TargetLowering::Legal: 3184 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3185 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3186 break; 3187 case TargetLowering::Expand: 3188 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3189 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3190 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3191 DAG.getConstant(PairTy.getSizeInBits()/2, 3192 TLI.getShiftAmountTy())); 3193 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3194 break; 3195 } 3196 break; 3197 } 3198 3199 case ISD::UREM: 3200 case ISD::SREM: 3201 case ISD::FREM: 3202 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3203 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3204 3205 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3206 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3207 case TargetLowering::Custom: 3208 isCustom = true; 3209 // FALLTHROUGH 3210 case TargetLowering::Legal: 3211 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3212 if (isCustom) { 3213 Tmp1 = TLI.LowerOperation(Result, DAG); 3214 if (Tmp1.Val) Result = Tmp1; 3215 } 3216 break; 3217 case TargetLowering::Expand: { 3218 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3219 bool isSigned = DivOpc == ISD::SDIV; 3220 MVT VT = Node->getValueType(0); 3221 3222 // See if remainder can be lowered using two-result operations. 3223 SDVTList VTs = DAG.getVTList(VT, VT); 3224 if (Node->getOpcode() == ISD::SREM && 3225 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3226 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3227 break; 3228 } 3229 if (Node->getOpcode() == ISD::UREM && 3230 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3231 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1); 3232 break; 3233 } 3234 3235 if (VT.isInteger()) { 3236 if (TLI.getOperationAction(DivOpc, VT) == 3237 TargetLowering::Legal) { 3238 // X % Y -> X-X/Y*Y 3239 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3240 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3241 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3242 } else if (VT.isVector()) { 3243 Result = LegalizeOp(UnrollVectorOp(Op)); 3244 } else { 3245 assert(VT == MVT::i32 && 3246 "Cannot expand this binary operator!"); 3247 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3248 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3249 SDOperand Dummy; 3250 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3251 } 3252 } else { 3253 assert(VT.isFloatingPoint() && 3254 "remainder op must have integer or floating-point type"); 3255 if (VT.isVector()) { 3256 Result = LegalizeOp(UnrollVectorOp(Op)); 3257 } else { 3258 // Floating point mod -> fmod libcall. 3259 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3260 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3261 SDOperand Dummy; 3262 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3263 } 3264 } 3265 break; 3266 } 3267 } 3268 break; 3269 case ISD::VAARG: { 3270 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3271 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3272 3273 MVT VT = Node->getValueType(0); 3274 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3275 default: assert(0 && "This action is not supported yet!"); 3276 case TargetLowering::Custom: 3277 isCustom = true; 3278 // FALLTHROUGH 3279 case TargetLowering::Legal: 3280 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3281 Result = Result.getValue(0); 3282 Tmp1 = Result.getValue(1); 3283 3284 if (isCustom) { 3285 Tmp2 = TLI.LowerOperation(Result, DAG); 3286 if (Tmp2.Val) { 3287 Result = LegalizeOp(Tmp2); 3288 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3289 } 3290 } 3291 break; 3292 case TargetLowering::Expand: { 3293 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3294 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3295 // Increment the pointer, VAList, to the next vaarg 3296 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3297 DAG.getConstant(VT.getSizeInBits()/8, 3298 TLI.getPointerTy())); 3299 // Store the incremented VAList to the legalized pointer 3300 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3301 // Load the actual argument out of the pointer VAList 3302 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3303 Tmp1 = LegalizeOp(Result.getValue(1)); 3304 Result = LegalizeOp(Result); 3305 break; 3306 } 3307 } 3308 // Since VAARG produces two values, make sure to remember that we 3309 // legalized both of them. 3310 AddLegalizedOperand(SDOperand(Node, 0), Result); 3311 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3312 return Op.ResNo ? Tmp1 : Result; 3313 } 3314 3315 case ISD::VACOPY: 3316 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3317 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3318 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3319 3320 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3321 default: assert(0 && "This action is not supported yet!"); 3322 case TargetLowering::Custom: 3323 isCustom = true; 3324 // FALLTHROUGH 3325 case TargetLowering::Legal: 3326 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3327 Node->getOperand(3), Node->getOperand(4)); 3328 if (isCustom) { 3329 Tmp1 = TLI.LowerOperation(Result, DAG); 3330 if (Tmp1.Val) Result = Tmp1; 3331 } 3332 break; 3333 case TargetLowering::Expand: 3334 // This defaults to loading a pointer from the input and storing it to the 3335 // output, returning the chain. 3336 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3337 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3338 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0); 3339 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0); 3340 break; 3341 } 3342 break; 3343 3344 case ISD::VAEND: 3345 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3346 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3347 3348 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3349 default: assert(0 && "This action is not supported yet!"); 3350 case TargetLowering::Custom: 3351 isCustom = true; 3352 // FALLTHROUGH 3353 case TargetLowering::Legal: 3354 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3355 if (isCustom) { 3356 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3357 if (Tmp1.Val) Result = Tmp1; 3358 } 3359 break; 3360 case TargetLowering::Expand: 3361 Result = Tmp1; // Default to a no-op, return the chain 3362 break; 3363 } 3364 break; 3365 3366 case ISD::VASTART: 3367 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3368 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3369 3370 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3371 3372 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3373 default: assert(0 && "This action is not supported yet!"); 3374 case TargetLowering::Legal: break; 3375 case TargetLowering::Custom: 3376 Tmp1 = TLI.LowerOperation(Result, DAG); 3377 if (Tmp1.Val) Result = Tmp1; 3378 break; 3379 } 3380 break; 3381 3382 case ISD::ROTL: 3383 case ISD::ROTR: 3384 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3385 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3386 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3387 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3388 default: 3389 assert(0 && "ROTL/ROTR legalize operation not supported"); 3390 break; 3391 case TargetLowering::Legal: 3392 break; 3393 case TargetLowering::Custom: 3394 Tmp1 = TLI.LowerOperation(Result, DAG); 3395 if (Tmp1.Val) Result = Tmp1; 3396 break; 3397 case TargetLowering::Promote: 3398 assert(0 && "Do not know how to promote ROTL/ROTR"); 3399 break; 3400 case TargetLowering::Expand: 3401 assert(0 && "Do not know how to expand ROTL/ROTR"); 3402 break; 3403 } 3404 break; 3405 3406 case ISD::BSWAP: 3407 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3408 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3409 case TargetLowering::Custom: 3410 assert(0 && "Cannot custom legalize this yet!"); 3411 case TargetLowering::Legal: 3412 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3413 break; 3414 case TargetLowering::Promote: { 3415 MVT OVT = Tmp1.getValueType(); 3416 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3417 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3418 3419 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3420 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3421 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3422 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3423 break; 3424 } 3425 case TargetLowering::Expand: 3426 Result = ExpandBSWAP(Tmp1); 3427 break; 3428 } 3429 break; 3430 3431 case ISD::CTPOP: 3432 case ISD::CTTZ: 3433 case ISD::CTLZ: 3434 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3435 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3436 case TargetLowering::Custom: 3437 case TargetLowering::Legal: 3438 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3439 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3440 TargetLowering::Custom) { 3441 Tmp1 = TLI.LowerOperation(Result, DAG); 3442 if (Tmp1.Val) { 3443 Result = Tmp1; 3444 } 3445 } 3446 break; 3447 case TargetLowering::Promote: { 3448 MVT OVT = Tmp1.getValueType(); 3449 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3450 3451 // Zero extend the argument. 3452 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3453 // Perform the larger operation, then subtract if needed. 3454 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3455 switch (Node->getOpcode()) { 3456 case ISD::CTPOP: 3457 Result = Tmp1; 3458 break; 3459 case ISD::CTTZ: 3460 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3461 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 3462 DAG.getConstant(NVT.getSizeInBits(), NVT), 3463 ISD::SETEQ); 3464 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3465 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3466 break; 3467 case ISD::CTLZ: 3468 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3469 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3470 DAG.getConstant(NVT.getSizeInBits() - 3471 OVT.getSizeInBits(), NVT)); 3472 break; 3473 } 3474 break; 3475 } 3476 case TargetLowering::Expand: 3477 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3478 break; 3479 } 3480 break; 3481 3482 // Unary operators 3483 case ISD::FABS: 3484 case ISD::FNEG: 3485 case ISD::FSQRT: 3486 case ISD::FSIN: 3487 case ISD::FCOS: 3488 Tmp1 = LegalizeOp(Node->getOperand(0)); 3489 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3490 case TargetLowering::Promote: 3491 case TargetLowering::Custom: 3492 isCustom = true; 3493 // FALLTHROUGH 3494 case TargetLowering::Legal: 3495 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3496 if (isCustom) { 3497 Tmp1 = TLI.LowerOperation(Result, DAG); 3498 if (Tmp1.Val) Result = Tmp1; 3499 } 3500 break; 3501 case TargetLowering::Expand: 3502 switch (Node->getOpcode()) { 3503 default: assert(0 && "Unreachable!"); 3504 case ISD::FNEG: 3505 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3506 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3507 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3508 break; 3509 case ISD::FABS: { 3510 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3511 MVT VT = Node->getValueType(0); 3512 Tmp2 = DAG.getConstantFP(0.0, VT); 3513 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 3514 ISD::SETUGT); 3515 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3516 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3517 break; 3518 } 3519 case ISD::FSQRT: 3520 case ISD::FSIN: 3521 case ISD::FCOS: { 3522 MVT VT = Node->getValueType(0); 3523 3524 // Expand unsupported unary vector operators by unrolling them. 3525 if (VT.isVector()) { 3526 Result = LegalizeOp(UnrollVectorOp(Op)); 3527 break; 3528 } 3529 3530 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3531 switch(Node->getOpcode()) { 3532 case ISD::FSQRT: 3533 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3534 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3535 break; 3536 case ISD::FSIN: 3537 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3538 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3539 break; 3540 case ISD::FCOS: 3541 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3542 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3543 break; 3544 default: assert(0 && "Unreachable!"); 3545 } 3546 SDOperand Dummy; 3547 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3548 break; 3549 } 3550 } 3551 break; 3552 } 3553 break; 3554 case ISD::FPOWI: { 3555 MVT VT = Node->getValueType(0); 3556 3557 // Expand unsupported unary vector operators by unrolling them. 3558 if (VT.isVector()) { 3559 Result = LegalizeOp(UnrollVectorOp(Op)); 3560 break; 3561 } 3562 3563 // We always lower FPOWI into a libcall. No target support for it yet. 3564 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3565 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3566 SDOperand Dummy; 3567 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3568 break; 3569 } 3570 case ISD::BIT_CONVERT: 3571 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3572 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3573 Node->getValueType(0)); 3574 } else if (Op.getOperand(0).getValueType().isVector()) { 3575 // The input has to be a vector type, we have to either scalarize it, pack 3576 // it, or convert it based on whether the input vector type is legal. 3577 SDNode *InVal = Node->getOperand(0).Val; 3578 int InIx = Node->getOperand(0).ResNo; 3579 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 3580 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 3581 3582 // Figure out if there is a simple type corresponding to this Vector 3583 // type. If so, convert to the vector type. 3584 MVT TVT = MVT::getVectorVT(EVT, NumElems); 3585 if (TLI.isTypeLegal(TVT)) { 3586 // Turn this into a bit convert of the vector input. 3587 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3588 LegalizeOp(Node->getOperand(0))); 3589 break; 3590 } else if (NumElems == 1) { 3591 // Turn this into a bit convert of the scalar input. 3592 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3593 ScalarizeVectorOp(Node->getOperand(0))); 3594 break; 3595 } else { 3596 // FIXME: UNIMP! Store then reload 3597 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3598 } 3599 } else { 3600 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3601 Node->getOperand(0).getValueType())) { 3602 default: assert(0 && "Unknown operation action!"); 3603 case TargetLowering::Expand: 3604 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3605 Node->getValueType(0)); 3606 break; 3607 case TargetLowering::Legal: 3608 Tmp1 = LegalizeOp(Node->getOperand(0)); 3609 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3610 break; 3611 } 3612 } 3613 break; 3614 3615 // Conversion operators. The source and destination have different types. 3616 case ISD::SINT_TO_FP: 3617 case ISD::UINT_TO_FP: { 3618 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3619 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3620 case Legal: 3621 switch (TLI.getOperationAction(Node->getOpcode(), 3622 Node->getOperand(0).getValueType())) { 3623 default: assert(0 && "Unknown operation action!"); 3624 case TargetLowering::Custom: 3625 isCustom = true; 3626 // FALLTHROUGH 3627 case TargetLowering::Legal: 3628 Tmp1 = LegalizeOp(Node->getOperand(0)); 3629 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3630 if (isCustom) { 3631 Tmp1 = TLI.LowerOperation(Result, DAG); 3632 if (Tmp1.Val) Result = Tmp1; 3633 } 3634 break; 3635 case TargetLowering::Expand: 3636 Result = ExpandLegalINT_TO_FP(isSigned, 3637 LegalizeOp(Node->getOperand(0)), 3638 Node->getValueType(0)); 3639 break; 3640 case TargetLowering::Promote: 3641 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)), 3642 Node->getValueType(0), 3643 isSigned); 3644 break; 3645 } 3646 break; 3647 case Expand: 3648 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, 3649 Node->getValueType(0), Node->getOperand(0)); 3650 break; 3651 case Promote: 3652 Tmp1 = PromoteOp(Node->getOperand(0)); 3653 if (isSigned) { 3654 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 3655 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType())); 3656 } else { 3657 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 3658 Node->getOperand(0).getValueType()); 3659 } 3660 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3661 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 3662 break; 3663 } 3664 break; 3665 } 3666 case ISD::TRUNCATE: 3667 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3668 case Legal: 3669 Tmp1 = LegalizeOp(Node->getOperand(0)); 3670 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3671 break; 3672 case Expand: 3673 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3674 3675 // Since the result is legal, we should just be able to truncate the low 3676 // part of the source. 3677 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3678 break; 3679 case Promote: 3680 Result = PromoteOp(Node->getOperand(0)); 3681 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3682 break; 3683 } 3684 break; 3685 3686 case ISD::FP_TO_SINT: 3687 case ISD::FP_TO_UINT: 3688 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3689 case Legal: 3690 Tmp1 = LegalizeOp(Node->getOperand(0)); 3691 3692 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3693 default: assert(0 && "Unknown operation action!"); 3694 case TargetLowering::Custom: 3695 isCustom = true; 3696 // FALLTHROUGH 3697 case TargetLowering::Legal: 3698 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3699 if (isCustom) { 3700 Tmp1 = TLI.LowerOperation(Result, DAG); 3701 if (Tmp1.Val) Result = Tmp1; 3702 } 3703 break; 3704 case TargetLowering::Promote: 3705 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3706 Node->getOpcode() == ISD::FP_TO_SINT); 3707 break; 3708 case TargetLowering::Expand: 3709 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3710 SDOperand True, False; 3711 MVT VT = Node->getOperand(0).getValueType(); 3712 MVT NVT = Node->getValueType(0); 3713 const uint64_t zero[] = {0, 0}; 3714 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 3715 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 3716 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 3717 Tmp2 = DAG.getConstantFP(apf, VT); 3718 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), 3719 Node->getOperand(0), Tmp2, ISD::SETLT); 3720 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3721 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3722 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3723 Tmp2)); 3724 False = DAG.getNode(ISD::XOR, NVT, False, 3725 DAG.getConstant(x, NVT)); 3726 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3727 break; 3728 } else { 3729 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3730 } 3731 break; 3732 } 3733 break; 3734 case Expand: { 3735 MVT VT = Op.getValueType(); 3736 MVT OVT = Node->getOperand(0).getValueType(); 3737 // Convert ppcf128 to i32 3738 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3739 if (Node->getOpcode() == ISD::FP_TO_SINT) { 3740 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 3741 Node->getOperand(0), DAG.getValueType(MVT::f64)); 3742 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 3743 DAG.getIntPtrConstant(1)); 3744 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 3745 } else { 3746 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3747 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3748 Tmp2 = DAG.getConstantFP(apf, OVT); 3749 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3750 // FIXME: generated code sucks. 3751 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3752 DAG.getNode(ISD::ADD, MVT::i32, 3753 DAG.getNode(ISD::FP_TO_SINT, VT, 3754 DAG.getNode(ISD::FSUB, OVT, 3755 Node->getOperand(0), Tmp2)), 3756 DAG.getConstant(0x80000000, MVT::i32)), 3757 DAG.getNode(ISD::FP_TO_SINT, VT, 3758 Node->getOperand(0)), 3759 DAG.getCondCode(ISD::SETGE)); 3760 } 3761 break; 3762 } 3763 // Convert f32 / f64 to i32 / i64 / i128. 3764 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3765 switch (Node->getOpcode()) { 3766 case ISD::FP_TO_SINT: { 3767 if (VT == MVT::i32) { 3768 if (OVT == MVT::f32) 3769 LC = RTLIB::FPTOSINT_F32_I32; 3770 else if (OVT == MVT::f64) 3771 LC = RTLIB::FPTOSINT_F64_I32; 3772 else 3773 assert(0 && "Unexpected i32-to-fp conversion!"); 3774 } else if (VT == MVT::i64) { 3775 if (OVT == MVT::f32) 3776 LC = RTLIB::FPTOSINT_F32_I64; 3777 else if (OVT == MVT::f64) 3778 LC = RTLIB::FPTOSINT_F64_I64; 3779 else if (OVT == MVT::f80) 3780 LC = RTLIB::FPTOSINT_F80_I64; 3781 else if (OVT == MVT::ppcf128) 3782 LC = RTLIB::FPTOSINT_PPCF128_I64; 3783 else 3784 assert(0 && "Unexpected i64-to-fp conversion!"); 3785 } else if (VT == MVT::i128) { 3786 if (OVT == MVT::f32) 3787 LC = RTLIB::FPTOSINT_F32_I128; 3788 else if (OVT == MVT::f64) 3789 LC = RTLIB::FPTOSINT_F64_I128; 3790 else if (OVT == MVT::f80) 3791 LC = RTLIB::FPTOSINT_F80_I128; 3792 else if (OVT == MVT::ppcf128) 3793 LC = RTLIB::FPTOSINT_PPCF128_I128; 3794 else 3795 assert(0 && "Unexpected i128-to-fp conversion!"); 3796 } else { 3797 assert(0 && "Unexpectd int-to-fp conversion!"); 3798 } 3799 break; 3800 } 3801 case ISD::FP_TO_UINT: { 3802 if (VT == MVT::i32) { 3803 if (OVT == MVT::f32) 3804 LC = RTLIB::FPTOUINT_F32_I32; 3805 else if (OVT == MVT::f64) 3806 LC = RTLIB::FPTOUINT_F64_I32; 3807 else if (OVT == MVT::f80) 3808 LC = RTLIB::FPTOUINT_F80_I32; 3809 else 3810 assert(0 && "Unexpected i32-to-fp conversion!"); 3811 } else if (VT == MVT::i64) { 3812 if (OVT == MVT::f32) 3813 LC = RTLIB::FPTOUINT_F32_I64; 3814 else if (OVT == MVT::f64) 3815 LC = RTLIB::FPTOUINT_F64_I64; 3816 else if (OVT == MVT::f80) 3817 LC = RTLIB::FPTOUINT_F80_I64; 3818 else if (OVT == MVT::ppcf128) 3819 LC = RTLIB::FPTOUINT_PPCF128_I64; 3820 else 3821 assert(0 && "Unexpected i64-to-fp conversion!"); 3822 } else if (VT == MVT::i128) { 3823 if (OVT == MVT::f32) 3824 LC = RTLIB::FPTOUINT_F32_I128; 3825 else if (OVT == MVT::f64) 3826 LC = RTLIB::FPTOUINT_F64_I128; 3827 else if (OVT == MVT::f80) 3828 LC = RTLIB::FPTOUINT_F80_I128; 3829 else if (OVT == MVT::ppcf128) 3830 LC = RTLIB::FPTOUINT_PPCF128_I128; 3831 else 3832 assert(0 && "Unexpected i128-to-fp conversion!"); 3833 } else { 3834 assert(0 && "Unexpectd int-to-fp conversion!"); 3835 } 3836 break; 3837 } 3838 default: assert(0 && "Unreachable!"); 3839 } 3840 SDOperand Dummy; 3841 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3842 break; 3843 } 3844 case Promote: 3845 Tmp1 = PromoteOp(Node->getOperand(0)); 3846 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3847 Result = LegalizeOp(Result); 3848 break; 3849 } 3850 break; 3851 3852 case ISD::FP_EXTEND: { 3853 MVT DstVT = Op.getValueType(); 3854 MVT SrcVT = Op.getOperand(0).getValueType(); 3855 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3856 // The only other way we can lower this is to turn it into a STORE, 3857 // LOAD pair, targetting a temporary location (a stack slot). 3858 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 3859 break; 3860 } 3861 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3862 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3863 case Legal: 3864 Tmp1 = LegalizeOp(Node->getOperand(0)); 3865 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3866 break; 3867 case Promote: 3868 Tmp1 = PromoteOp(Node->getOperand(0)); 3869 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3870 break; 3871 } 3872 break; 3873 } 3874 case ISD::FP_ROUND: { 3875 MVT DstVT = Op.getValueType(); 3876 MVT SrcVT = Op.getOperand(0).getValueType(); 3877 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3878 if (SrcVT == MVT::ppcf128) { 3879 SDOperand Lo; 3880 ExpandOp(Node->getOperand(0), Lo, Result); 3881 // Round it the rest of the way (e.g. to f32) if needed. 3882 if (DstVT!=MVT::f64) 3883 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 3884 break; 3885 } 3886 // The only other way we can lower this is to turn it into a STORE, 3887 // LOAD pair, targetting a temporary location (a stack slot). 3888 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 3889 break; 3890 } 3891 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3892 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3893 case Legal: 3894 Tmp1 = LegalizeOp(Node->getOperand(0)); 3895 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3896 break; 3897 case Promote: 3898 Tmp1 = PromoteOp(Node->getOperand(0)); 3899 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 3900 Node->getOperand(1)); 3901 break; 3902 } 3903 break; 3904 } 3905 case ISD::ANY_EXTEND: 3906 case ISD::ZERO_EXTEND: 3907 case ISD::SIGN_EXTEND: 3908 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3909 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3910 case Legal: 3911 Tmp1 = LegalizeOp(Node->getOperand(0)); 3912 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3913 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3914 TargetLowering::Custom) { 3915 Tmp1 = TLI.LowerOperation(Result, DAG); 3916 if (Tmp1.Val) Result = Tmp1; 3917 } 3918 break; 3919 case Promote: 3920 switch (Node->getOpcode()) { 3921 case ISD::ANY_EXTEND: 3922 Tmp1 = PromoteOp(Node->getOperand(0)); 3923 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3924 break; 3925 case ISD::ZERO_EXTEND: 3926 Result = PromoteOp(Node->getOperand(0)); 3927 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3928 Result = DAG.getZeroExtendInReg(Result, 3929 Node->getOperand(0).getValueType()); 3930 break; 3931 case ISD::SIGN_EXTEND: 3932 Result = PromoteOp(Node->getOperand(0)); 3933 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3934 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3935 Result, 3936 DAG.getValueType(Node->getOperand(0).getValueType())); 3937 break; 3938 } 3939 } 3940 break; 3941 case ISD::FP_ROUND_INREG: 3942 case ISD::SIGN_EXTEND_INREG: { 3943 Tmp1 = LegalizeOp(Node->getOperand(0)); 3944 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3945 3946 // If this operation is not supported, convert it to a shl/shr or load/store 3947 // pair. 3948 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3949 default: assert(0 && "This action not supported for this op yet!"); 3950 case TargetLowering::Legal: 3951 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3952 break; 3953 case TargetLowering::Expand: 3954 // If this is an integer extend and shifts are supported, do that. 3955 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3956 // NOTE: we could fall back on load/store here too for targets without 3957 // SAR. However, it is doubtful that any exist. 3958 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 3959 ExtraVT.getSizeInBits(); 3960 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3961 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3962 Node->getOperand(0), ShiftCst); 3963 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3964 Result, ShiftCst); 3965 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3966 // The only way we can lower this is to turn it into a TRUNCSTORE, 3967 // EXTLOAD pair, targetting a temporary location (a stack slot). 3968 3969 // NOTE: there is a choice here between constantly creating new stack 3970 // slots and always reusing the same one. We currently always create 3971 // new ones, as reuse may inhibit scheduling. 3972 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 3973 Node->getValueType(0)); 3974 } else { 3975 assert(0 && "Unknown op"); 3976 } 3977 break; 3978 } 3979 break; 3980 } 3981 case ISD::TRAMPOLINE: { 3982 SDOperand Ops[6]; 3983 for (unsigned i = 0; i != 6; ++i) 3984 Ops[i] = LegalizeOp(Node->getOperand(i)); 3985 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3986 // The only option for this node is to custom lower it. 3987 Result = TLI.LowerOperation(Result, DAG); 3988 assert(Result.Val && "Should always custom lower!"); 3989 3990 // Since trampoline produces two values, make sure to remember that we 3991 // legalized both of them. 3992 Tmp1 = LegalizeOp(Result.getValue(1)); 3993 Result = LegalizeOp(Result); 3994 AddLegalizedOperand(SDOperand(Node, 0), Result); 3995 AddLegalizedOperand(SDOperand(Node, 1), Tmp1); 3996 return Op.ResNo ? Tmp1 : Result; 3997 } 3998 case ISD::FLT_ROUNDS_: { 3999 MVT VT = Node->getValueType(0); 4000 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4001 default: assert(0 && "This action not supported for this op yet!"); 4002 case TargetLowering::Custom: 4003 Result = TLI.LowerOperation(Op, DAG); 4004 if (Result.Val) break; 4005 // Fall Thru 4006 case TargetLowering::Legal: 4007 // If this operation is not supported, lower it to constant 1 4008 Result = DAG.getConstant(1, VT); 4009 break; 4010 } 4011 break; 4012 } 4013 case ISD::TRAP: { 4014 MVT VT = Node->getValueType(0); 4015 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4016 default: assert(0 && "This action not supported for this op yet!"); 4017 case TargetLowering::Legal: 4018 Tmp1 = LegalizeOp(Node->getOperand(0)); 4019 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4020 break; 4021 case TargetLowering::Custom: 4022 Result = TLI.LowerOperation(Op, DAG); 4023 if (Result.Val) break; 4024 // Fall Thru 4025 case TargetLowering::Expand: 4026 // If this operation is not supported, lower it to 'abort()' call 4027 Tmp1 = LegalizeOp(Node->getOperand(0)); 4028 TargetLowering::ArgListTy Args; 4029 std::pair<SDOperand,SDOperand> CallResult = 4030 TLI.LowerCallTo(Tmp1, Type::VoidTy, 4031 false, false, false, CallingConv::C, false, 4032 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 4033 Args, DAG); 4034 Result = CallResult.second; 4035 break; 4036 } 4037 break; 4038 } 4039 } 4040 4041 assert(Result.getValueType() == Op.getValueType() && 4042 "Bad legalization!"); 4043 4044 // Make sure that the generated code is itself legal. 4045 if (Result != Op) 4046 Result = LegalizeOp(Result); 4047 4048 // Note that LegalizeOp may be reentered even from single-use nodes, which 4049 // means that we always must cache transformed nodes. 4050 AddLegalizedOperand(Op, Result); 4051 return Result; 4052} 4053 4054/// PromoteOp - Given an operation that produces a value in an invalid type, 4055/// promote it to compute the value into a larger type. The produced value will 4056/// have the correct bits for the low portion of the register, but no guarantee 4057/// is made about the top bits: it may be zero, sign-extended, or garbage. 4058SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { 4059 MVT VT = Op.getValueType(); 4060 MVT NVT = TLI.getTypeToTransformTo(VT); 4061 assert(getTypeAction(VT) == Promote && 4062 "Caller should expand or legalize operands that are not promotable!"); 4063 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() && 4064 "Cannot promote to smaller type!"); 4065 4066 SDOperand Tmp1, Tmp2, Tmp3; 4067 SDOperand Result; 4068 SDNode *Node = Op.Val; 4069 4070 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op); 4071 if (I != PromotedNodes.end()) return I->second; 4072 4073 switch (Node->getOpcode()) { 4074 case ISD::CopyFromReg: 4075 assert(0 && "CopyFromReg must be legal!"); 4076 default: 4077#ifndef NDEBUG 4078 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4079#endif 4080 assert(0 && "Do not know how to promote this operator!"); 4081 abort(); 4082 case ISD::UNDEF: 4083 Result = DAG.getNode(ISD::UNDEF, NVT); 4084 break; 4085 case ISD::Constant: 4086 if (VT != MVT::i1) 4087 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4088 else 4089 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4090 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4091 break; 4092 case ISD::ConstantFP: 4093 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4094 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4095 break; 4096 4097 case ISD::SETCC: 4098 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0))) 4099 && "SetCC type is not legal??"); 4100 Result = DAG.getNode(ISD::SETCC, 4101 TLI.getSetCCResultType(Node->getOperand(0)), 4102 Node->getOperand(0), Node->getOperand(1), 4103 Node->getOperand(2)); 4104 break; 4105 4106 case ISD::TRUNCATE: 4107 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4108 case Legal: 4109 Result = LegalizeOp(Node->getOperand(0)); 4110 assert(Result.getValueType().bitsGE(NVT) && 4111 "This truncation doesn't make sense!"); 4112 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT 4113 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4114 break; 4115 case Promote: 4116 // The truncation is not required, because we don't guarantee anything 4117 // about high bits anyway. 4118 Result = PromoteOp(Node->getOperand(0)); 4119 break; 4120 case Expand: 4121 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4122 // Truncate the low part of the expanded value to the result type 4123 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4124 } 4125 break; 4126 case ISD::SIGN_EXTEND: 4127 case ISD::ZERO_EXTEND: 4128 case ISD::ANY_EXTEND: 4129 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4130 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4131 case Legal: 4132 // Input is legal? Just do extend all the way to the larger type. 4133 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4134 break; 4135 case Promote: 4136 // Promote the reg if it's smaller. 4137 Result = PromoteOp(Node->getOperand(0)); 4138 // The high bits are not guaranteed to be anything. Insert an extend. 4139 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4140 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4141 DAG.getValueType(Node->getOperand(0).getValueType())); 4142 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4143 Result = DAG.getZeroExtendInReg(Result, 4144 Node->getOperand(0).getValueType()); 4145 break; 4146 } 4147 break; 4148 case ISD::BIT_CONVERT: 4149 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4150 Node->getValueType(0)); 4151 Result = PromoteOp(Result); 4152 break; 4153 4154 case ISD::FP_EXTEND: 4155 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4156 case ISD::FP_ROUND: 4157 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4158 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4159 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4160 case Legal: 4161 if (Node->getConstantOperandVal(1) == 0) { 4162 // Input is legal? Do an FP_ROUND_INREG. 4163 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4164 DAG.getValueType(VT)); 4165 } else { 4166 // Just remove the truncate, it isn't affecting the value. 4167 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4168 Node->getOperand(1)); 4169 } 4170 break; 4171 } 4172 break; 4173 case ISD::SINT_TO_FP: 4174 case ISD::UINT_TO_FP: 4175 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4176 case Legal: 4177 // No extra round required here. 4178 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4179 break; 4180 4181 case Promote: 4182 Result = PromoteOp(Node->getOperand(0)); 4183 if (Node->getOpcode() == ISD::SINT_TO_FP) 4184 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4185 Result, 4186 DAG.getValueType(Node->getOperand(0).getValueType())); 4187 else 4188 Result = DAG.getZeroExtendInReg(Result, 4189 Node->getOperand(0).getValueType()); 4190 // No extra round required here. 4191 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4192 break; 4193 case Expand: 4194 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4195 Node->getOperand(0)); 4196 // Round if we cannot tolerate excess precision. 4197 if (NoExcessFPPrecision) 4198 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4199 DAG.getValueType(VT)); 4200 break; 4201 } 4202 break; 4203 4204 case ISD::SIGN_EXTEND_INREG: 4205 Result = PromoteOp(Node->getOperand(0)); 4206 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4207 Node->getOperand(1)); 4208 break; 4209 case ISD::FP_TO_SINT: 4210 case ISD::FP_TO_UINT: 4211 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4212 case Legal: 4213 case Expand: 4214 Tmp1 = Node->getOperand(0); 4215 break; 4216 case Promote: 4217 // The input result is prerounded, so we don't have to do anything 4218 // special. 4219 Tmp1 = PromoteOp(Node->getOperand(0)); 4220 break; 4221 } 4222 // If we're promoting a UINT to a larger size, check to see if the new node 4223 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4224 // we can use that instead. This allows us to generate better code for 4225 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4226 // legal, such as PowerPC. 4227 if (Node->getOpcode() == ISD::FP_TO_UINT && 4228 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 4229 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 4230 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4231 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4232 } else { 4233 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4234 } 4235 break; 4236 4237 case ISD::FABS: 4238 case ISD::FNEG: 4239 Tmp1 = PromoteOp(Node->getOperand(0)); 4240 assert(Tmp1.getValueType() == NVT); 4241 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4242 // NOTE: we do not have to do any extra rounding here for 4243 // NoExcessFPPrecision, because we know the input will have the appropriate 4244 // precision, and these operations don't modify precision at all. 4245 break; 4246 4247 case ISD::FSQRT: 4248 case ISD::FSIN: 4249 case ISD::FCOS: 4250 Tmp1 = PromoteOp(Node->getOperand(0)); 4251 assert(Tmp1.getValueType() == NVT); 4252 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4253 if (NoExcessFPPrecision) 4254 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4255 DAG.getValueType(VT)); 4256 break; 4257 4258 case ISD::FPOWI: { 4259 // Promote f32 powi to f64 powi. Note that this could insert a libcall 4260 // directly as well, which may be better. 4261 Tmp1 = PromoteOp(Node->getOperand(0)); 4262 assert(Tmp1.getValueType() == NVT); 4263 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1)); 4264 if (NoExcessFPPrecision) 4265 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4266 DAG.getValueType(VT)); 4267 break; 4268 } 4269 4270 case ISD::ATOMIC_CMP_SWAP: { 4271 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4272 Tmp2 = PromoteOp(Node->getOperand(2)); 4273 Tmp3 = PromoteOp(Node->getOperand(3)); 4274 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 4275 AtomNode->getBasePtr(), Tmp2, Tmp3, 4276 AtomNode->getSrcValue(), 4277 AtomNode->getAlignment()); 4278 // Remember that we legalized the chain. 4279 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4280 break; 4281 } 4282 case ISD::ATOMIC_LOAD_ADD: 4283 case ISD::ATOMIC_LOAD_SUB: 4284 case ISD::ATOMIC_LOAD_AND: 4285 case ISD::ATOMIC_LOAD_OR: 4286 case ISD::ATOMIC_LOAD_XOR: 4287 case ISD::ATOMIC_LOAD_NAND: 4288 case ISD::ATOMIC_LOAD_MIN: 4289 case ISD::ATOMIC_LOAD_MAX: 4290 case ISD::ATOMIC_LOAD_UMIN: 4291 case ISD::ATOMIC_LOAD_UMAX: 4292 case ISD::ATOMIC_SWAP: { 4293 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4294 Tmp2 = PromoteOp(Node->getOperand(2)); 4295 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 4296 AtomNode->getBasePtr(), Tmp2, 4297 AtomNode->getSrcValue(), 4298 AtomNode->getAlignment()); 4299 // Remember that we legalized the chain. 4300 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4301 break; 4302 } 4303 4304 case ISD::AND: 4305 case ISD::OR: 4306 case ISD::XOR: 4307 case ISD::ADD: 4308 case ISD::SUB: 4309 case ISD::MUL: 4310 // The input may have strange things in the top bits of the registers, but 4311 // these operations don't care. They may have weird bits going out, but 4312 // that too is okay if they are integer operations. 4313 Tmp1 = PromoteOp(Node->getOperand(0)); 4314 Tmp2 = PromoteOp(Node->getOperand(1)); 4315 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4316 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4317 break; 4318 case ISD::FADD: 4319 case ISD::FSUB: 4320 case ISD::FMUL: 4321 Tmp1 = PromoteOp(Node->getOperand(0)); 4322 Tmp2 = PromoteOp(Node->getOperand(1)); 4323 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4324 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4325 4326 // Floating point operations will give excess precision that we may not be 4327 // able to tolerate. If we DO allow excess precision, just leave it, 4328 // otherwise excise it. 4329 // FIXME: Why would we need to round FP ops more than integer ones? 4330 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4331 if (NoExcessFPPrecision) 4332 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4333 DAG.getValueType(VT)); 4334 break; 4335 4336 case ISD::SDIV: 4337 case ISD::SREM: 4338 // These operators require that their input be sign extended. 4339 Tmp1 = PromoteOp(Node->getOperand(0)); 4340 Tmp2 = PromoteOp(Node->getOperand(1)); 4341 if (NVT.isInteger()) { 4342 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4343 DAG.getValueType(VT)); 4344 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4345 DAG.getValueType(VT)); 4346 } 4347 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4348 4349 // Perform FP_ROUND: this is probably overly pessimistic. 4350 if (NVT.isFloatingPoint() && NoExcessFPPrecision) 4351 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4352 DAG.getValueType(VT)); 4353 break; 4354 case ISD::FDIV: 4355 case ISD::FREM: 4356 case ISD::FCOPYSIGN: 4357 // These operators require that their input be fp extended. 4358 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4359 case Expand: assert(0 && "not implemented"); 4360 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4361 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4362 } 4363 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4364 case Expand: assert(0 && "not implemented"); 4365 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4366 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4367 } 4368 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4369 4370 // Perform FP_ROUND: this is probably overly pessimistic. 4371 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4372 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4373 DAG.getValueType(VT)); 4374 break; 4375 4376 case ISD::UDIV: 4377 case ISD::UREM: 4378 // These operators require that their input be zero extended. 4379 Tmp1 = PromoteOp(Node->getOperand(0)); 4380 Tmp2 = PromoteOp(Node->getOperand(1)); 4381 assert(NVT.isInteger() && "Operators don't apply to FP!"); 4382 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4383 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4384 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4385 break; 4386 4387 case ISD::SHL: 4388 Tmp1 = PromoteOp(Node->getOperand(0)); 4389 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4390 break; 4391 case ISD::SRA: 4392 // The input value must be properly sign extended. 4393 Tmp1 = PromoteOp(Node->getOperand(0)); 4394 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4395 DAG.getValueType(VT)); 4396 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4397 break; 4398 case ISD::SRL: 4399 // The input value must be properly zero extended. 4400 Tmp1 = PromoteOp(Node->getOperand(0)); 4401 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4402 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4403 break; 4404 4405 case ISD::VAARG: 4406 Tmp1 = Node->getOperand(0); // Get the chain. 4407 Tmp2 = Node->getOperand(1); // Get the pointer. 4408 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4409 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4410 Result = TLI.CustomPromoteOperation(Tmp3, DAG); 4411 } else { 4412 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4413 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4414 // Increment the pointer, VAList, to the next vaarg 4415 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4416 DAG.getConstant(VT.getSizeInBits()/8, 4417 TLI.getPointerTy())); 4418 // Store the incremented VAList to the legalized pointer 4419 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4420 // Load the actual argument out of the pointer VAList 4421 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4422 } 4423 // Remember that we legalized the chain. 4424 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4425 break; 4426 4427 case ISD::LOAD: { 4428 LoadSDNode *LD = cast<LoadSDNode>(Node); 4429 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4430 ? ISD::EXTLOAD : LD->getExtensionType(); 4431 Result = DAG.getExtLoad(ExtType, NVT, 4432 LD->getChain(), LD->getBasePtr(), 4433 LD->getSrcValue(), LD->getSrcValueOffset(), 4434 LD->getMemoryVT(), 4435 LD->isVolatile(), 4436 LD->getAlignment()); 4437 // Remember that we legalized the chain. 4438 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4439 break; 4440 } 4441 case ISD::SELECT: { 4442 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4443 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4444 4445 MVT VT2 = Tmp2.getValueType(); 4446 assert(VT2 == Tmp3.getValueType() 4447 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); 4448 // Ensure that the resulting node is at least the same size as the operands' 4449 // value types, because we cannot assume that TLI.getSetCCValueType() is 4450 // constant. 4451 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3); 4452 break; 4453 } 4454 case ISD::SELECT_CC: 4455 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4456 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4457 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4458 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4459 break; 4460 case ISD::BSWAP: 4461 Tmp1 = Node->getOperand(0); 4462 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4463 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4464 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4465 DAG.getConstant(NVT.getSizeInBits() - 4466 VT.getSizeInBits(), 4467 TLI.getShiftAmountTy())); 4468 break; 4469 case ISD::CTPOP: 4470 case ISD::CTTZ: 4471 case ISD::CTLZ: 4472 // Zero extend the argument 4473 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4474 // Perform the larger operation, then subtract if needed. 4475 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4476 switch(Node->getOpcode()) { 4477 case ISD::CTPOP: 4478 Result = Tmp1; 4479 break; 4480 case ISD::CTTZ: 4481 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4482 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 4483 DAG.getConstant(NVT.getSizeInBits(), NVT), 4484 ISD::SETEQ); 4485 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4486 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); 4487 break; 4488 case ISD::CTLZ: 4489 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4490 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4491 DAG.getConstant(NVT.getSizeInBits() - 4492 VT.getSizeInBits(), NVT)); 4493 break; 4494 } 4495 break; 4496 case ISD::EXTRACT_SUBVECTOR: 4497 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4498 break; 4499 case ISD::EXTRACT_VECTOR_ELT: 4500 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4501 break; 4502 } 4503 4504 assert(Result.Val && "Didn't set a result!"); 4505 4506 // Make sure the result is itself legal. 4507 Result = LegalizeOp(Result); 4508 4509 // Remember that we promoted this! 4510 AddPromotedOperand(Op, Result); 4511 return Result; 4512} 4513 4514/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4515/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4516/// based on the vector type. The return type of this matches the element type 4517/// of the vector, which may not be legal for the target. 4518SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) { 4519 // We know that operand #0 is the Vec vector. If the index is a constant 4520 // or if the invec is a supported hardware type, we can use it. Otherwise, 4521 // lower to a store then an indexed load. 4522 SDOperand Vec = Op.getOperand(0); 4523 SDOperand Idx = Op.getOperand(1); 4524 4525 MVT TVT = Vec.getValueType(); 4526 unsigned NumElems = TVT.getVectorNumElements(); 4527 4528 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4529 default: assert(0 && "This action is not supported yet!"); 4530 case TargetLowering::Custom: { 4531 Vec = LegalizeOp(Vec); 4532 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4533 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG); 4534 if (Tmp3.Val) 4535 return Tmp3; 4536 break; 4537 } 4538 case TargetLowering::Legal: 4539 if (isTypeLegal(TVT)) { 4540 Vec = LegalizeOp(Vec); 4541 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4542 return Op; 4543 } 4544 break; 4545 case TargetLowering::Expand: 4546 break; 4547 } 4548 4549 if (NumElems == 1) { 4550 // This must be an access of the only element. Return it. 4551 Op = ScalarizeVectorOp(Vec); 4552 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4553 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 4554 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4555 SDOperand Lo, Hi; 4556 SplitVectorOp(Vec, Lo, Hi); 4557 if (CIdx->getValue() < NumLoElts) { 4558 Vec = Lo; 4559 } else { 4560 Vec = Hi; 4561 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts, 4562 Idx.getValueType()); 4563 } 4564 4565 // It's now an extract from the appropriate high or low part. Recurse. 4566 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4567 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4568 } else { 4569 // Store the value to a temporary stack slot, then LOAD the scalar 4570 // element back out. 4571 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4572 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4573 4574 // Add the offset to the index. 4575 unsigned EltSize = Op.getValueType().getSizeInBits()/8; 4576 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4577 DAG.getConstant(EltSize, Idx.getValueType())); 4578 4579 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 4580 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4581 else 4582 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4583 4584 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4585 4586 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4587 } 4588 return Op; 4589} 4590 4591/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4592/// we assume the operation can be split if it is not already legal. 4593SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) { 4594 // We know that operand #0 is the Vec vector. For now we assume the index 4595 // is a constant and that the extracted result is a supported hardware type. 4596 SDOperand Vec = Op.getOperand(0); 4597 SDOperand Idx = LegalizeOp(Op.getOperand(1)); 4598 4599 unsigned NumElems = Vec.getValueType().getVectorNumElements(); 4600 4601 if (NumElems == Op.getValueType().getVectorNumElements()) { 4602 // This must be an access of the desired vector length. Return it. 4603 return Vec; 4604 } 4605 4606 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4607 SDOperand Lo, Hi; 4608 SplitVectorOp(Vec, Lo, Hi); 4609 if (CIdx->getValue() < NumElems/2) { 4610 Vec = Lo; 4611 } else { 4612 Vec = Hi; 4613 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType()); 4614 } 4615 4616 // It's now an extract from the appropriate high or low part. Recurse. 4617 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4618 return ExpandEXTRACT_SUBVECTOR(Op); 4619} 4620 4621/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4622/// with condition CC on the current target. This usually involves legalizing 4623/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4624/// there may be no choice but to create a new SetCC node to represent the 4625/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4626/// LHS, and the SDOperand returned in RHS has a nil SDNode value. 4627void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS, 4628 SDOperand &RHS, 4629 SDOperand &CC) { 4630 SDOperand Tmp1, Tmp2, Tmp3, Result; 4631 4632 switch (getTypeAction(LHS.getValueType())) { 4633 case Legal: 4634 Tmp1 = LegalizeOp(LHS); // LHS 4635 Tmp2 = LegalizeOp(RHS); // RHS 4636 break; 4637 case Promote: 4638 Tmp1 = PromoteOp(LHS); // LHS 4639 Tmp2 = PromoteOp(RHS); // RHS 4640 4641 // If this is an FP compare, the operands have already been extended. 4642 if (LHS.getValueType().isInteger()) { 4643 MVT VT = LHS.getValueType(); 4644 MVT NVT = TLI.getTypeToTransformTo(VT); 4645 4646 // Otherwise, we have to insert explicit sign or zero extends. Note 4647 // that we could insert sign extends for ALL conditions, but zero extend 4648 // is cheaper on many machines (an AND instead of two shifts), so prefer 4649 // it. 4650 switch (cast<CondCodeSDNode>(CC)->get()) { 4651 default: assert(0 && "Unknown integer comparison!"); 4652 case ISD::SETEQ: 4653 case ISD::SETNE: 4654 case ISD::SETUGE: 4655 case ISD::SETUGT: 4656 case ISD::SETULE: 4657 case ISD::SETULT: 4658 // ALL of these operations will work if we either sign or zero extend 4659 // the operands (including the unsigned comparisons!). Zero extend is 4660 // usually a simpler/cheaper operation, so prefer it. 4661 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4662 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4663 break; 4664 case ISD::SETGE: 4665 case ISD::SETGT: 4666 case ISD::SETLT: 4667 case ISD::SETLE: 4668 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4669 DAG.getValueType(VT)); 4670 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4671 DAG.getValueType(VT)); 4672 break; 4673 } 4674 } 4675 break; 4676 case Expand: { 4677 MVT VT = LHS.getValueType(); 4678 if (VT == MVT::f32 || VT == MVT::f64) { 4679 // Expand into one or more soft-fp libcall(s). 4680 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL; 4681 switch (cast<CondCodeSDNode>(CC)->get()) { 4682 case ISD::SETEQ: 4683 case ISD::SETOEQ: 4684 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4685 break; 4686 case ISD::SETNE: 4687 case ISD::SETUNE: 4688 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4689 break; 4690 case ISD::SETGE: 4691 case ISD::SETOGE: 4692 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4693 break; 4694 case ISD::SETLT: 4695 case ISD::SETOLT: 4696 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4697 break; 4698 case ISD::SETLE: 4699 case ISD::SETOLE: 4700 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4701 break; 4702 case ISD::SETGT: 4703 case ISD::SETOGT: 4704 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4705 break; 4706 case ISD::SETUO: 4707 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4708 break; 4709 case ISD::SETO: 4710 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4711 break; 4712 default: 4713 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4714 switch (cast<CondCodeSDNode>(CC)->get()) { 4715 case ISD::SETONE: 4716 // SETONE = SETOLT | SETOGT 4717 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4718 // Fallthrough 4719 case ISD::SETUGT: 4720 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4721 break; 4722 case ISD::SETUGE: 4723 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4724 break; 4725 case ISD::SETULT: 4726 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4727 break; 4728 case ISD::SETULE: 4729 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4730 break; 4731 case ISD::SETUEQ: 4732 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4733 break; 4734 default: assert(0 && "Unsupported FP setcc!"); 4735 } 4736 } 4737 4738 SDOperand Dummy; 4739 Tmp1 = ExpandLibCall(LC1, 4740 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4741 false /*sign irrelevant*/, Dummy); 4742 Tmp2 = DAG.getConstant(0, MVT::i32); 4743 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4744 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4745 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 4746 CC); 4747 LHS = ExpandLibCall(LC2, 4748 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val, 4749 false /*sign irrelevant*/, Dummy); 4750 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, 4751 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4752 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4753 Tmp2 = SDOperand(); 4754 } 4755 LHS = Tmp1; 4756 RHS = Tmp2; 4757 return; 4758 } 4759 4760 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 4761 ExpandOp(LHS, LHSLo, LHSHi); 4762 ExpandOp(RHS, RHSLo, RHSHi); 4763 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4764 4765 if (VT==MVT::ppcf128) { 4766 // FIXME: This generated code sucks. We want to generate 4767 // FCMP crN, hi1, hi2 4768 // BNE crN, L: 4769 // FCMP crN, lo1, lo2 4770 // The following can be improved, but not that much. 4771 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ); 4772 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode); 4773 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4774 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE); 4775 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode); 4776 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4777 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4778 Tmp2 = SDOperand(); 4779 break; 4780 } 4781 4782 switch (CCCode) { 4783 case ISD::SETEQ: 4784 case ISD::SETNE: 4785 if (RHSLo == RHSHi) 4786 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4787 if (RHSCST->isAllOnesValue()) { 4788 // Comparison to -1. 4789 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4790 Tmp2 = RHSLo; 4791 break; 4792 } 4793 4794 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4795 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4796 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4797 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4798 break; 4799 default: 4800 // If this is a comparison of the sign bit, just look at the top part. 4801 // X > -1, x < 0 4802 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4803 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4804 CST->isNullValue()) || // X < 0 4805 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4806 CST->isAllOnesValue())) { // X > -1 4807 Tmp1 = LHSHi; 4808 Tmp2 = RHSHi; 4809 break; 4810 } 4811 4812 // FIXME: This generated code sucks. 4813 ISD::CondCode LowCC; 4814 switch (CCCode) { 4815 default: assert(0 && "Unknown integer setcc!"); 4816 case ISD::SETLT: 4817 case ISD::SETULT: LowCC = ISD::SETULT; break; 4818 case ISD::SETGT: 4819 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4820 case ISD::SETLE: 4821 case ISD::SETULE: LowCC = ISD::SETULE; break; 4822 case ISD::SETGE: 4823 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4824 } 4825 4826 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4827 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4828 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4829 4830 // NOTE: on targets without efficient SELECT of bools, we can always use 4831 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4832 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4833 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, 4834 LowCC, false, DagCombineInfo); 4835 if (!Tmp1.Val) 4836 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 4837 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4838 CCCode, false, DagCombineInfo); 4839 if (!Tmp2.Val) 4840 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, 4841 RHSHi,CC); 4842 4843 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 4844 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 4845 if ((Tmp1C && Tmp1C->isNullValue()) || 4846 (Tmp2C && Tmp2C->isNullValue() && 4847 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4848 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4849 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 4850 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4851 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4852 // low part is known false, returns high part. 4853 // For LE / GE, if high part is known false, ignore the low part. 4854 // For LT / GT, if high part is known true, ignore the low part. 4855 Tmp1 = Tmp2; 4856 Tmp2 = SDOperand(); 4857 } else { 4858 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4859 ISD::SETEQ, false, DagCombineInfo); 4860 if (!Result.Val) 4861 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4862 ISD::SETEQ); 4863 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4864 Result, Tmp1, Tmp2)); 4865 Tmp1 = Result; 4866 Tmp2 = SDOperand(); 4867 } 4868 } 4869 } 4870 } 4871 LHS = Tmp1; 4872 RHS = Tmp2; 4873} 4874 4875/// EmitStackConvert - Emit a store/load combination to the stack. This stores 4876/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 4877/// a load from the stack slot to DestVT, extending it if needed. 4878/// The resultant code need not be legal. 4879SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp, 4880 MVT SlotVT, 4881 MVT DestVT) { 4882 // Create the stack frame object. 4883 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT); 4884 4885 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 4886 int SPFI = StackPtrFI->getIndex(); 4887 4888 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 4889 unsigned SlotSize = SlotVT.getSizeInBits(); 4890 unsigned DestSize = DestVT.getSizeInBits(); 4891 4892 // Emit a store to the stack slot. Use a truncstore if the input value is 4893 // later than DestVT. 4894 SDOperand Store; 4895 if (SrcSize > SlotSize) 4896 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 4897 PseudoSourceValue::getFixedStack(), 4898 SPFI, SlotVT); 4899 else { 4900 assert(SrcSize == SlotSize && "Invalid store"); 4901 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 4902 PseudoSourceValue::getFixedStack(), 4903 SPFI); 4904 } 4905 4906 // Result is a load from the stack slot. 4907 if (SlotSize == DestSize) 4908 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0); 4909 4910 assert(SlotSize < DestSize && "Unknown extension!"); 4911 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT); 4912} 4913 4914SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4915 // Create a vector sized/aligned stack slot, store the value to element #0, 4916 // then load the whole vector back out. 4917 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4918 4919 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 4920 int SPFI = StackPtrFI->getIndex(); 4921 4922 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4923 PseudoSourceValue::getFixedStack(), SPFI); 4924 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 4925 PseudoSourceValue::getFixedStack(), SPFI); 4926} 4927 4928 4929/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4930/// support the operation, but do support the resultant vector type. 4931SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4932 4933 // If the only non-undef value is the low element, turn this into a 4934 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4935 unsigned NumElems = Node->getNumOperands(); 4936 bool isOnlyLowElement = true; 4937 SDOperand SplatValue = Node->getOperand(0); 4938 4939 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t> 4940 // and use a bitmask instead of a list of elements. 4941 std::map<SDOperand, std::vector<unsigned> > Values; 4942 Values[SplatValue].push_back(0); 4943 bool isConstant = true; 4944 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4945 SplatValue.getOpcode() != ISD::UNDEF) 4946 isConstant = false; 4947 4948 for (unsigned i = 1; i < NumElems; ++i) { 4949 SDOperand V = Node->getOperand(i); 4950 Values[V].push_back(i); 4951 if (V.getOpcode() != ISD::UNDEF) 4952 isOnlyLowElement = false; 4953 if (SplatValue != V) 4954 SplatValue = SDOperand(0,0); 4955 4956 // If this isn't a constant element or an undef, we can't use a constant 4957 // pool load. 4958 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4959 V.getOpcode() != ISD::UNDEF) 4960 isConstant = false; 4961 } 4962 4963 if (isOnlyLowElement) { 4964 // If the low element is an undef too, then this whole things is an undef. 4965 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4966 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4967 // Otherwise, turn this into a scalar_to_vector node. 4968 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4969 Node->getOperand(0)); 4970 } 4971 4972 // If all elements are constants, create a load from the constant pool. 4973 if (isConstant) { 4974 MVT VT = Node->getValueType(0); 4975 std::vector<Constant*> CV; 4976 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4977 if (ConstantFPSDNode *V = 4978 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4979 CV.push_back(ConstantFP::get(V->getValueAPF())); 4980 } else if (ConstantSDNode *V = 4981 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4982 CV.push_back(ConstantInt::get(V->getAPIntValue())); 4983 } else { 4984 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4985 const Type *OpNTy = 4986 Node->getOperand(0).getValueType().getTypeForMVT(); 4987 CV.push_back(UndefValue::get(OpNTy)); 4988 } 4989 } 4990 Constant *CP = ConstantVector::get(CV); 4991 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 4992 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 4993 PseudoSourceValue::getConstantPool(), 0); 4994 } 4995 4996 if (SplatValue.Val) { // Splat of one value? 4997 // Build the shuffle constant vector: <0, 0, 0, 0> 4998 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 4999 SDOperand Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); 5000 std::vector<SDOperand> ZeroVec(NumElems, Zero); 5001 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5002 &ZeroVec[0], ZeroVec.size()); 5003 5004 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 5005 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 5006 // Get the splatted value into the low element of a vector register. 5007 SDOperand LowValVec = 5008 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 5009 5010 // Return shuffle(LowValVec, undef, <0,0,0,0>) 5011 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 5012 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 5013 SplatMask); 5014 } 5015 } 5016 5017 // If there are only two unique elements, we may be able to turn this into a 5018 // vector shuffle. 5019 if (Values.size() == 2) { 5020 // Get the two values in deterministic order. 5021 SDOperand Val1 = Node->getOperand(1); 5022 SDOperand Val2; 5023 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin(); 5024 if (MI->first != Val1) 5025 Val2 = MI->first; 5026 else 5027 Val2 = (++MI)->first; 5028 5029 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 5030 // vector shuffle has the undef vector on the RHS. 5031 if (Val1.getOpcode() == ISD::UNDEF) 5032 std::swap(Val1, Val2); 5033 5034 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 5035 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5036 MVT MaskEltVT = MaskVT.getVectorElementType(); 5037 std::vector<SDOperand> MaskVec(NumElems); 5038 5039 // Set elements of the shuffle mask for Val1. 5040 std::vector<unsigned> &Val1Elts = Values[Val1]; 5041 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 5042 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 5043 5044 // Set elements of the shuffle mask for Val2. 5045 std::vector<unsigned> &Val2Elts = Values[Val2]; 5046 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 5047 if (Val2.getOpcode() != ISD::UNDEF) 5048 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 5049 else 5050 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); 5051 5052 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5053 &MaskVec[0], MaskVec.size()); 5054 5055 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 5056 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 5057 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 5058 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); 5059 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); 5060 SDOperand Ops[] = { Val1, Val2, ShuffleMask }; 5061 5062 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 5063 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); 5064 } 5065 } 5066 5067 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5068 // aligned object on the stack, store each element into it, then load 5069 // the result as a vector. 5070 MVT VT = Node->getValueType(0); 5071 // Create the stack frame object. 5072 SDOperand FIPtr = DAG.CreateStackTemporary(VT); 5073 5074 // Emit a store of each element to the stack slot. 5075 SmallVector<SDOperand, 8> Stores; 5076 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8; 5077 // Store (in the right endianness) the elements to memory. 5078 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5079 // Ignore undef elements. 5080 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5081 5082 unsigned Offset = TypeByteSize*i; 5083 5084 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5085 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 5086 5087 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 5088 NULL, 0)); 5089 } 5090 5091 SDOperand StoreChain; 5092 if (!Stores.empty()) // Not all undef elements? 5093 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5094 &Stores[0], Stores.size()); 5095 else 5096 StoreChain = DAG.getEntryNode(); 5097 5098 // Result is a load from the stack slot. 5099 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 5100} 5101 5102void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5103 SDOperand Op, SDOperand Amt, 5104 SDOperand &Lo, SDOperand &Hi) { 5105 // Expand the subcomponents. 5106 SDOperand LHSL, LHSH; 5107 ExpandOp(Op, LHSL, LHSH); 5108 5109 SDOperand Ops[] = { LHSL, LHSH, Amt }; 5110 MVT VT = LHSL.getValueType(); 5111 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5112 Hi = Lo.getValue(1); 5113} 5114 5115 5116/// ExpandShift - Try to find a clever way to expand this shift operation out to 5117/// smaller elements. If we can't find a way that is more efficient than a 5118/// libcall on this target, return false. Otherwise, return true with the 5119/// low-parts expanded into Lo and Hi. 5120bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt, 5121 SDOperand &Lo, SDOperand &Hi) { 5122 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5123 "This is not a shift!"); 5124 5125 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5126 SDOperand ShAmt = LegalizeOp(Amt); 5127 MVT ShTy = ShAmt.getValueType(); 5128 unsigned ShBits = ShTy.getSizeInBits(); 5129 unsigned VTBits = Op.getValueType().getSizeInBits(); 5130 unsigned NVTBits = NVT.getSizeInBits(); 5131 5132 // Handle the case when Amt is an immediate. 5133 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) { 5134 unsigned Cst = CN->getValue(); 5135 // Expand the incoming operand to be shifted, so that we have its parts 5136 SDOperand InL, InH; 5137 ExpandOp(Op, InL, InH); 5138 switch(Opc) { 5139 case ISD::SHL: 5140 if (Cst > VTBits) { 5141 Lo = DAG.getConstant(0, NVT); 5142 Hi = DAG.getConstant(0, NVT); 5143 } else if (Cst > NVTBits) { 5144 Lo = DAG.getConstant(0, NVT); 5145 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5146 } else if (Cst == NVTBits) { 5147 Lo = DAG.getConstant(0, NVT); 5148 Hi = InL; 5149 } else { 5150 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5151 Hi = DAG.getNode(ISD::OR, NVT, 5152 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5153 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5154 } 5155 return true; 5156 case ISD::SRL: 5157 if (Cst > VTBits) { 5158 Lo = DAG.getConstant(0, NVT); 5159 Hi = DAG.getConstant(0, NVT); 5160 } else if (Cst > NVTBits) { 5161 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5162 Hi = DAG.getConstant(0, NVT); 5163 } else if (Cst == NVTBits) { 5164 Lo = InH; 5165 Hi = DAG.getConstant(0, NVT); 5166 } else { 5167 Lo = DAG.getNode(ISD::OR, NVT, 5168 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5169 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5170 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5171 } 5172 return true; 5173 case ISD::SRA: 5174 if (Cst > VTBits) { 5175 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5176 DAG.getConstant(NVTBits-1, ShTy)); 5177 } else if (Cst > NVTBits) { 5178 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5179 DAG.getConstant(Cst-NVTBits, ShTy)); 5180 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5181 DAG.getConstant(NVTBits-1, ShTy)); 5182 } else if (Cst == NVTBits) { 5183 Lo = InH; 5184 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5185 DAG.getConstant(NVTBits-1, ShTy)); 5186 } else { 5187 Lo = DAG.getNode(ISD::OR, NVT, 5188 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5189 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5190 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5191 } 5192 return true; 5193 } 5194 } 5195 5196 // Okay, the shift amount isn't constant. However, if we can tell that it is 5197 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5198 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5199 APInt KnownZero, KnownOne; 5200 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5201 5202 // If we know that if any of the high bits of the shift amount are one, then 5203 // we can do this as a couple of simple shifts. 5204 if (KnownOne.intersects(Mask)) { 5205 // Mask out the high bit, which we know is set. 5206 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5207 DAG.getConstant(~Mask, Amt.getValueType())); 5208 5209 // Expand the incoming operand to be shifted, so that we have its parts 5210 SDOperand InL, InH; 5211 ExpandOp(Op, InL, InH); 5212 switch(Opc) { 5213 case ISD::SHL: 5214 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5215 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5216 return true; 5217 case ISD::SRL: 5218 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5219 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5220 return true; 5221 case ISD::SRA: 5222 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5223 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5224 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5225 return true; 5226 } 5227 } 5228 5229 // If we know that the high bits of the shift amount are all zero, then we can 5230 // do this as a couple of simple shifts. 5231 if ((KnownZero & Mask) == Mask) { 5232 // Compute 32-amt. 5233 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5234 DAG.getConstant(NVTBits, Amt.getValueType()), 5235 Amt); 5236 5237 // Expand the incoming operand to be shifted, so that we have its parts 5238 SDOperand InL, InH; 5239 ExpandOp(Op, InL, InH); 5240 switch(Opc) { 5241 case ISD::SHL: 5242 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5243 Hi = DAG.getNode(ISD::OR, NVT, 5244 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5245 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5246 return true; 5247 case ISD::SRL: 5248 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5249 Lo = DAG.getNode(ISD::OR, NVT, 5250 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5251 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5252 return true; 5253 case ISD::SRA: 5254 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5255 Lo = DAG.getNode(ISD::OR, NVT, 5256 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5257 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5258 return true; 5259 } 5260 } 5261 5262 return false; 5263} 5264 5265 5266// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5267// does not fit into a register, return the lo part and set the hi part to the 5268// by-reg argument. If it does fit into a single register, return the result 5269// and leave the Hi part unset. 5270SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5271 bool isSigned, SDOperand &Hi) { 5272 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5273 // The input chain to this libcall is the entry node of the function. 5274 // Legalizing the call will automatically add the previous call to the 5275 // dependence. 5276 SDOperand InChain = DAG.getEntryNode(); 5277 5278 TargetLowering::ArgListTy Args; 5279 TargetLowering::ArgListEntry Entry; 5280 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5281 MVT ArgVT = Node->getOperand(i).getValueType(); 5282 const Type *ArgTy = ArgVT.getTypeForMVT(); 5283 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5284 Entry.isSExt = isSigned; 5285 Entry.isZExt = !isSigned; 5286 Args.push_back(Entry); 5287 } 5288 SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5289 TLI.getPointerTy()); 5290 5291 // Splice the libcall in wherever FindInputOutputChains tells us to. 5292 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 5293 std::pair<SDOperand,SDOperand> CallInfo = 5294 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C, 5295 false, Callee, Args, DAG); 5296 5297 // Legalize the call sequence, starting with the chain. This will advance 5298 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5299 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5300 LegalizeOp(CallInfo.second); 5301 SDOperand Result; 5302 switch (getTypeAction(CallInfo.first.getValueType())) { 5303 default: assert(0 && "Unknown thing"); 5304 case Legal: 5305 Result = CallInfo.first; 5306 break; 5307 case Expand: 5308 ExpandOp(CallInfo.first, Result, Hi); 5309 break; 5310 } 5311 return Result; 5312} 5313 5314 5315/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5316/// 5317SDOperand SelectionDAGLegalize:: 5318ExpandIntToFP(bool isSigned, MVT DestTy, SDOperand Source) { 5319 MVT SourceVT = Source.getValueType(); 5320 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5321 5322 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5323 if (!isSigned && SourceVT != MVT::i32) { 5324 // The integer value loaded will be incorrectly if the 'sign bit' of the 5325 // incoming integer is set. To handle this, we dynamically test to see if 5326 // it is set, and, if so, add a fudge factor. 5327 SDOperand Hi; 5328 if (ExpandSource) { 5329 SDOperand Lo; 5330 ExpandOp(Source, Lo, Hi); 5331 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); 5332 } else { 5333 // The comparison for the sign bit will use the entire operand. 5334 Hi = Source; 5335 } 5336 5337 // If this is unsigned, and not supported, first perform the conversion to 5338 // signed, then adjust the result if the sign bit is set. 5339 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source); 5340 5341 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 5342 DAG.getConstant(0, Hi.getValueType()), 5343 ISD::SETLT); 5344 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5345 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5346 SignSet, Four, Zero); 5347 uint64_t FF = 0x5f800000ULL; 5348 if (TLI.isLittleEndian()) FF <<= 32; 5349 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5350 5351 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5352 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5353 SDOperand FudgeInReg; 5354 if (DestTy == MVT::f32) 5355 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5356 PseudoSourceValue::getConstantPool(), 0); 5357 else if (DestTy.bitsGT(MVT::f32)) 5358 // FIXME: Avoid the extend by construction the right constantpool? 5359 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5360 CPIdx, 5361 PseudoSourceValue::getConstantPool(), 0, 5362 MVT::f32); 5363 else 5364 assert(0 && "Unexpected conversion"); 5365 5366 MVT SCVT = SignedConv.getValueType(); 5367 if (SCVT != DestTy) { 5368 // Destination type needs to be expanded as well. The FADD now we are 5369 // constructing will be expanded into a libcall. 5370 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { 5371 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); 5372 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, 5373 SignedConv, SignedConv.getValue(1)); 5374 } 5375 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5376 } 5377 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5378 } 5379 5380 // Check to see if the target has a custom way to lower this. If so, use it. 5381 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 5382 default: assert(0 && "This action not implemented for this operation!"); 5383 case TargetLowering::Legal: 5384 case TargetLowering::Expand: 5385 break; // This case is handled below. 5386 case TargetLowering::Custom: { 5387 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5388 Source), DAG); 5389 if (NV.Val) 5390 return LegalizeOp(NV); 5391 break; // The target decided this was legal after all 5392 } 5393 } 5394 5395 // Expand the source, then glue it back together for the call. We must expand 5396 // the source in case it is shared (this pass of legalize must traverse it). 5397 if (ExpandSource) { 5398 SDOperand SrcLo, SrcHi; 5399 ExpandOp(Source, SrcLo, SrcHi); 5400 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); 5401 } 5402 5403 RTLIB::Libcall LC; 5404 if (SourceVT == MVT::i32) { 5405 if (DestTy == MVT::f32) 5406 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32; 5407 else { 5408 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 5409 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64; 5410 } 5411 } else if (SourceVT == MVT::i64) { 5412 if (DestTy == MVT::f32) 5413 LC = RTLIB::SINTTOFP_I64_F32; 5414 else if (DestTy == MVT::f64) 5415 LC = RTLIB::SINTTOFP_I64_F64; 5416 else if (DestTy == MVT::f80) 5417 LC = RTLIB::SINTTOFP_I64_F80; 5418 else { 5419 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 5420 LC = RTLIB::SINTTOFP_I64_PPCF128; 5421 } 5422 } else if (SourceVT == MVT::i128) { 5423 if (DestTy == MVT::f32) 5424 LC = RTLIB::SINTTOFP_I128_F32; 5425 else if (DestTy == MVT::f64) 5426 LC = RTLIB::SINTTOFP_I128_F64; 5427 else if (DestTy == MVT::f80) 5428 LC = RTLIB::SINTTOFP_I128_F80; 5429 else { 5430 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 5431 LC = RTLIB::SINTTOFP_I128_PPCF128; 5432 } 5433 } else { 5434 assert(0 && "Unknown int value type"); 5435 } 5436 5437 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!"); 5438 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5439 SDOperand HiPart; 5440 SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart); 5441 if (Result.getValueType() != DestTy && HiPart.Val) 5442 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); 5443 return Result; 5444} 5445 5446/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5447/// INT_TO_FP operation of the specified operand when the target requests that 5448/// we expand it. At this point, we know that the result and operand types are 5449/// legal for the target. 5450SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5451 SDOperand Op0, 5452 MVT DestVT) { 5453 if (Op0.getValueType() == MVT::i32) { 5454 // simple 32-bit [signed|unsigned] integer to float/double expansion 5455 5456 // Get the stack frame index of a 8 byte buffer. 5457 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64); 5458 5459 // word offset constant for Hi/Lo address computation 5460 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5461 // set up Hi and Lo (into buffer) address based on endian 5462 SDOperand Hi = StackSlot; 5463 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5464 if (TLI.isLittleEndian()) 5465 std::swap(Hi, Lo); 5466 5467 // if signed map to unsigned space 5468 SDOperand Op0Mapped; 5469 if (isSigned) { 5470 // constant used to invert sign bit (signed to unsigned mapping) 5471 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5472 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5473 } else { 5474 Op0Mapped = Op0; 5475 } 5476 // store the lo of the constructed double - based on integer input 5477 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(), 5478 Op0Mapped, Lo, NULL, 0); 5479 // initial hi portion of constructed double 5480 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5481 // store the hi of the constructed double - biased exponent 5482 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5483 // load the constructed double 5484 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5485 // FP constant to bias correct the final result 5486 SDOperand Bias = DAG.getConstantFP(isSigned ? 5487 BitsToDouble(0x4330000080000000ULL) 5488 : BitsToDouble(0x4330000000000000ULL), 5489 MVT::f64); 5490 // subtract the bias 5491 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5492 // final result 5493 SDOperand Result; 5494 // handle final rounding 5495 if (DestVT == MVT::f64) { 5496 // do nothing 5497 Result = Sub; 5498 } else if (DestVT.bitsLT(MVT::f64)) { 5499 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 5500 DAG.getIntPtrConstant(0)); 5501 } else if (DestVT.bitsGT(MVT::f64)) { 5502 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5503 } 5504 return Result; 5505 } 5506 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5507 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5508 5509 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0, 5510 DAG.getConstant(0, Op0.getValueType()), 5511 ISD::SETLT); 5512 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5513 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5514 SignSet, Four, Zero); 5515 5516 // If the sign bit of the integer is set, the large number will be treated 5517 // as a negative number. To counteract this, the dynamic code adds an 5518 // offset depending on the data type. 5519 uint64_t FF; 5520 switch (Op0.getValueType().getSimpleVT()) { 5521 default: assert(0 && "Unsupported integer type!"); 5522 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5523 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5524 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5525 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5526 } 5527 if (TLI.isLittleEndian()) FF <<= 32; 5528 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5529 5530 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5531 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5532 SDOperand FudgeInReg; 5533 if (DestVT == MVT::f32) 5534 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5535 PseudoSourceValue::getConstantPool(), 0); 5536 else { 5537 FudgeInReg = 5538 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5539 DAG.getEntryNode(), CPIdx, 5540 PseudoSourceValue::getConstantPool(), 0, 5541 MVT::f32)); 5542 } 5543 5544 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5545} 5546 5547/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5548/// *INT_TO_FP operation of the specified operand when the target requests that 5549/// we promote it. At this point, we know that the result and operand types are 5550/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5551/// operation that takes a larger input. 5552SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp, 5553 MVT DestVT, 5554 bool isSigned) { 5555 // First step, figure out the appropriate *INT_TO_FP operation to use. 5556 MVT NewInTy = LegalOp.getValueType(); 5557 5558 unsigned OpToUse = 0; 5559 5560 // Scan for the appropriate larger type to use. 5561 while (1) { 5562 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 5563 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 5564 5565 // If the target supports SINT_TO_FP of this type, use it. 5566 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5567 default: break; 5568 case TargetLowering::Legal: 5569 if (!TLI.isTypeLegal(NewInTy)) 5570 break; // Can't use this datatype. 5571 // FALL THROUGH. 5572 case TargetLowering::Custom: 5573 OpToUse = ISD::SINT_TO_FP; 5574 break; 5575 } 5576 if (OpToUse) break; 5577 if (isSigned) continue; 5578 5579 // If the target supports UINT_TO_FP of this type, use it. 5580 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5581 default: break; 5582 case TargetLowering::Legal: 5583 if (!TLI.isTypeLegal(NewInTy)) 5584 break; // Can't use this datatype. 5585 // FALL THROUGH. 5586 case TargetLowering::Custom: 5587 OpToUse = ISD::UINT_TO_FP; 5588 break; 5589 } 5590 if (OpToUse) break; 5591 5592 // Otherwise, try a larger type. 5593 } 5594 5595 // Okay, we found the operation and type to use. Zero extend our input to the 5596 // desired type then run the operation on it. 5597 return DAG.getNode(OpToUse, DestVT, 5598 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5599 NewInTy, LegalOp)); 5600} 5601 5602/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5603/// FP_TO_*INT operation of the specified operand when the target requests that 5604/// we promote it. At this point, we know that the result and operand types are 5605/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5606/// operation that returns a larger result. 5607SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp, 5608 MVT DestVT, 5609 bool isSigned) { 5610 // First step, figure out the appropriate FP_TO*INT operation to use. 5611 MVT NewOutTy = DestVT; 5612 5613 unsigned OpToUse = 0; 5614 5615 // Scan for the appropriate larger type to use. 5616 while (1) { 5617 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 5618 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 5619 5620 // If the target supports FP_TO_SINT returning this type, use it. 5621 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5622 default: break; 5623 case TargetLowering::Legal: 5624 if (!TLI.isTypeLegal(NewOutTy)) 5625 break; // Can't use this datatype. 5626 // FALL THROUGH. 5627 case TargetLowering::Custom: 5628 OpToUse = ISD::FP_TO_SINT; 5629 break; 5630 } 5631 if (OpToUse) break; 5632 5633 // If the target supports FP_TO_UINT of this type, use it. 5634 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5635 default: break; 5636 case TargetLowering::Legal: 5637 if (!TLI.isTypeLegal(NewOutTy)) 5638 break; // Can't use this datatype. 5639 // FALL THROUGH. 5640 case TargetLowering::Custom: 5641 OpToUse = ISD::FP_TO_UINT; 5642 break; 5643 } 5644 if (OpToUse) break; 5645 5646 // Otherwise, try a larger type. 5647 } 5648 5649 5650 // Okay, we found the operation and type to use. 5651 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5652 5653 // If the operation produces an invalid type, it must be custom lowered. Use 5654 // the target lowering hooks to expand it. Just keep the low part of the 5655 // expanded operation, we know that we're truncating anyway. 5656 if (getTypeAction(NewOutTy) == Expand) { 5657 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0); 5658 assert(Operation.Val && "Didn't return anything"); 5659 } 5660 5661 // Truncate the result of the extended FP_TO_*INT operation to the desired 5662 // size. 5663 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5664} 5665 5666/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5667/// 5668SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) { 5669 MVT VT = Op.getValueType(); 5670 MVT SHVT = TLI.getShiftAmountTy(); 5671 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5672 switch (VT.getSimpleVT()) { 5673 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5674 case MVT::i16: 5675 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5676 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5677 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5678 case MVT::i32: 5679 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5680 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5681 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5682 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5683 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5684 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5685 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5686 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5687 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5688 case MVT::i64: 5689 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5690 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5691 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5692 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5693 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5694 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5695 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5696 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5697 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5698 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5699 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5700 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5701 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5702 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5703 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5704 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5705 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5706 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5707 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5708 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5709 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5710 } 5711} 5712 5713/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5714/// 5715SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) { 5716 switch (Opc) { 5717 default: assert(0 && "Cannot expand this yet!"); 5718 case ISD::CTPOP: { 5719 static const uint64_t mask[6] = { 5720 0x5555555555555555ULL, 0x3333333333333333ULL, 5721 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5722 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5723 }; 5724 MVT VT = Op.getValueType(); 5725 MVT ShVT = TLI.getShiftAmountTy(); 5726 unsigned len = VT.getSizeInBits(); 5727 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5728 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5729 SDOperand Tmp2 = DAG.getConstant(mask[i], VT); 5730 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5731 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5732 DAG.getNode(ISD::AND, VT, 5733 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5734 } 5735 return Op; 5736 } 5737 case ISD::CTLZ: { 5738 // for now, we do this: 5739 // x = x | (x >> 1); 5740 // x = x | (x >> 2); 5741 // ... 5742 // x = x | (x >>16); 5743 // x = x | (x >>32); // for 64-bit input 5744 // return popcount(~x); 5745 // 5746 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5747 MVT VT = Op.getValueType(); 5748 MVT ShVT = TLI.getShiftAmountTy(); 5749 unsigned len = VT.getSizeInBits(); 5750 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5751 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5752 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5753 } 5754 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5755 return DAG.getNode(ISD::CTPOP, VT, Op); 5756 } 5757 case ISD::CTTZ: { 5758 // for now, we use: { return popcount(~x & (x - 1)); } 5759 // unless the target has ctlz but not ctpop, in which case we use: 5760 // { return 32 - nlz(~x & (x-1)); } 5761 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5762 MVT VT = Op.getValueType(); 5763 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT); 5764 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT, 5765 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5766 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5767 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5768 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5769 TLI.isOperationLegal(ISD::CTLZ, VT)) 5770 return DAG.getNode(ISD::SUB, VT, 5771 DAG.getConstant(VT.getSizeInBits(), VT), 5772 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5773 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5774 } 5775 } 5776} 5777 5778/// ExpandOp - Expand the specified SDOperand into its two component pieces 5779/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5780/// LegalizeNodes map is filled in for any results that are not expanded, the 5781/// ExpandedNodes map is filled in for any results that are expanded, and the 5782/// Lo/Hi values are returned. 5783void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ 5784 MVT VT = Op.getValueType(); 5785 MVT NVT = TLI.getTypeToTransformTo(VT); 5786 SDNode *Node = Op.Val; 5787 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5788 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || 5789 VT.isVector()) && "Cannot expand to FP value or to larger int value!"); 5790 5791 // See if we already expanded it. 5792 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 5793 = ExpandedNodes.find(Op); 5794 if (I != ExpandedNodes.end()) { 5795 Lo = I->second.first; 5796 Hi = I->second.second; 5797 return; 5798 } 5799 5800 switch (Node->getOpcode()) { 5801 case ISD::CopyFromReg: 5802 assert(0 && "CopyFromReg must be legal!"); 5803 case ISD::FP_ROUND_INREG: 5804 if (VT == MVT::ppcf128 && 5805 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5806 TargetLowering::Custom) { 5807 SDOperand SrcLo, SrcHi, Src; 5808 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5809 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5810 SDOperand Result = TLI.LowerOperation( 5811 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5812 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR); 5813 Lo = Result.Val->getOperand(0); 5814 Hi = Result.Val->getOperand(1); 5815 break; 5816 } 5817 // fall through 5818 default: 5819#ifndef NDEBUG 5820 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5821#endif 5822 assert(0 && "Do not know how to expand this operator!"); 5823 abort(); 5824 case ISD::EXTRACT_ELEMENT: 5825 ExpandOp(Node->getOperand(0), Lo, Hi); 5826 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) 5827 return ExpandOp(Hi, Lo, Hi); 5828 return ExpandOp(Lo, Lo, Hi); 5829 case ISD::EXTRACT_VECTOR_ELT: 5830 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5831 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5832 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5833 return ExpandOp(Lo, Lo, Hi); 5834 case ISD::UNDEF: 5835 Lo = DAG.getNode(ISD::UNDEF, NVT); 5836 Hi = DAG.getNode(ISD::UNDEF, NVT); 5837 break; 5838 case ISD::Constant: { 5839 unsigned NVTBits = NVT.getSizeInBits(); 5840 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 5841 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 5842 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 5843 break; 5844 } 5845 case ISD::ConstantFP: { 5846 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5847 if (CFP->getValueType(0) == MVT::ppcf128) { 5848 APInt api = CFP->getValueAPF().convertToAPInt(); 5849 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5850 MVT::f64); 5851 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5852 MVT::f64); 5853 break; 5854 } 5855 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5856 if (getTypeAction(Lo.getValueType()) == Expand) 5857 ExpandOp(Lo, Lo, Hi); 5858 break; 5859 } 5860 case ISD::BUILD_PAIR: 5861 // Return the operands. 5862 Lo = Node->getOperand(0); 5863 Hi = Node->getOperand(1); 5864 break; 5865 5866 case ISD::MERGE_VALUES: 5867 if (Node->getNumValues() == 1) { 5868 ExpandOp(Op.getOperand(0), Lo, Hi); 5869 break; 5870 } 5871 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5872 assert(Op.ResNo == 0 && Node->getNumValues() == 2 && 5873 Op.getValue(1).getValueType() == MVT::Other && 5874 "unhandled MERGE_VALUES"); 5875 ExpandOp(Op.getOperand(0), Lo, Hi); 5876 // Remember that we legalized the chain. 5877 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5878 break; 5879 5880 case ISD::SIGN_EXTEND_INREG: 5881 ExpandOp(Node->getOperand(0), Lo, Hi); 5882 // sext_inreg the low part if needed. 5883 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5884 5885 // The high part gets the sign extension from the lo-part. This handles 5886 // things like sextinreg V:i64 from i8. 5887 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5888 DAG.getConstant(NVT.getSizeInBits()-1, 5889 TLI.getShiftAmountTy())); 5890 break; 5891 5892 case ISD::BSWAP: { 5893 ExpandOp(Node->getOperand(0), Lo, Hi); 5894 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5895 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5896 Lo = TempLo; 5897 break; 5898 } 5899 5900 case ISD::CTPOP: 5901 ExpandOp(Node->getOperand(0), Lo, Hi); 5902 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5903 DAG.getNode(ISD::CTPOP, NVT, Lo), 5904 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5905 Hi = DAG.getConstant(0, NVT); 5906 break; 5907 5908 case ISD::CTLZ: { 5909 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5910 ExpandOp(Node->getOperand(0), Lo, Hi); 5911 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 5912 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5913 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, 5914 ISD::SETNE); 5915 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5916 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5917 5918 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5919 Hi = DAG.getConstant(0, NVT); 5920 break; 5921 } 5922 5923 case ISD::CTTZ: { 5924 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5925 ExpandOp(Node->getOperand(0), Lo, Hi); 5926 SDOperand BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 5927 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5928 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, 5929 ISD::SETNE); 5930 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5931 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5932 5933 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5934 Hi = DAG.getConstant(0, NVT); 5935 break; 5936 } 5937 5938 case ISD::VAARG: { 5939 SDOperand Ch = Node->getOperand(0); // Legalize the chain. 5940 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer. 5941 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5942 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5943 5944 // Remember that we legalized the chain. 5945 Hi = LegalizeOp(Hi); 5946 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 5947 if (TLI.isBigEndian()) 5948 std::swap(Lo, Hi); 5949 break; 5950 } 5951 5952 case ISD::LOAD: { 5953 LoadSDNode *LD = cast<LoadSDNode>(Node); 5954 SDOperand Ch = LD->getChain(); // Legalize the chain. 5955 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer. 5956 ISD::LoadExtType ExtType = LD->getExtensionType(); 5957 int SVOffset = LD->getSrcValueOffset(); 5958 unsigned Alignment = LD->getAlignment(); 5959 bool isVolatile = LD->isVolatile(); 5960 5961 if (ExtType == ISD::NON_EXTLOAD) { 5962 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5963 isVolatile, Alignment); 5964 if (VT == MVT::f32 || VT == MVT::f64) { 5965 // f32->i32 or f64->i64 one to one expansion. 5966 // Remember that we legalized the chain. 5967 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 5968 // Recursively expand the new load. 5969 if (getTypeAction(NVT) == Expand) 5970 ExpandOp(Lo, Lo, Hi); 5971 break; 5972 } 5973 5974 // Increment the pointer to the other half. 5975 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 5976 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 5977 DAG.getIntPtrConstant(IncrementSize)); 5978 SVOffset += IncrementSize; 5979 Alignment = MinAlign(Alignment, IncrementSize); 5980 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset, 5981 isVolatile, Alignment); 5982 5983 // Build a factor node to remember that this load is independent of the 5984 // other one. 5985 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 5986 Hi.getValue(1)); 5987 5988 // Remember that we legalized the chain. 5989 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 5990 if (TLI.isBigEndian()) 5991 std::swap(Lo, Hi); 5992 } else { 5993 MVT EVT = LD->getMemoryVT(); 5994 5995 if ((VT == MVT::f64 && EVT == MVT::f32) || 5996 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 5997 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 5998 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(), 5999 SVOffset, isVolatile, Alignment); 6000 // Remember that we legalized the chain. 6001 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1))); 6002 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 6003 break; 6004 } 6005 6006 if (EVT == NVT) 6007 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), 6008 SVOffset, isVolatile, Alignment); 6009 else 6010 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(), 6011 SVOffset, EVT, isVolatile, 6012 Alignment); 6013 6014 // Remember that we legalized the chain. 6015 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1))); 6016 6017 if (ExtType == ISD::SEXTLOAD) { 6018 // The high part is obtained by SRA'ing all but one of the bits of the 6019 // lo part. 6020 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6021 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6022 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6023 } else if (ExtType == ISD::ZEXTLOAD) { 6024 // The high part is just a zero. 6025 Hi = DAG.getConstant(0, NVT); 6026 } else /* if (ExtType == ISD::EXTLOAD) */ { 6027 // The high part is undefined. 6028 Hi = DAG.getNode(ISD::UNDEF, NVT); 6029 } 6030 } 6031 break; 6032 } 6033 case ISD::AND: 6034 case ISD::OR: 6035 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6036 SDOperand LL, LH, RL, RH; 6037 ExpandOp(Node->getOperand(0), LL, LH); 6038 ExpandOp(Node->getOperand(1), RL, RH); 6039 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 6040 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 6041 break; 6042 } 6043 case ISD::SELECT: { 6044 SDOperand LL, LH, RL, RH; 6045 ExpandOp(Node->getOperand(1), LL, LH); 6046 ExpandOp(Node->getOperand(2), RL, RH); 6047 if (getTypeAction(NVT) == Expand) 6048 NVT = TLI.getTypeToExpandTo(NVT); 6049 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 6050 if (VT != MVT::f32) 6051 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 6052 break; 6053 } 6054 case ISD::SELECT_CC: { 6055 SDOperand TL, TH, FL, FH; 6056 ExpandOp(Node->getOperand(2), TL, TH); 6057 ExpandOp(Node->getOperand(3), FL, FH); 6058 if (getTypeAction(NVT) == Expand) 6059 NVT = TLI.getTypeToExpandTo(NVT); 6060 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6061 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6062 if (VT != MVT::f32) 6063 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6064 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6065 break; 6066 } 6067 case ISD::ANY_EXTEND: 6068 // The low part is any extension of the input (which degenerates to a copy). 6069 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 6070 // The high part is undefined. 6071 Hi = DAG.getNode(ISD::UNDEF, NVT); 6072 break; 6073 case ISD::SIGN_EXTEND: { 6074 // The low part is just a sign extension of the input (which degenerates to 6075 // a copy). 6076 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 6077 6078 // The high part is obtained by SRA'ing all but one of the bits of the lo 6079 // part. 6080 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6081 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6082 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6083 break; 6084 } 6085 case ISD::ZERO_EXTEND: 6086 // The low part is just a zero extension of the input (which degenerates to 6087 // a copy). 6088 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 6089 6090 // The high part is just a zero. 6091 Hi = DAG.getConstant(0, NVT); 6092 break; 6093 6094 case ISD::TRUNCATE: { 6095 // The input value must be larger than this value. Expand *it*. 6096 SDOperand NewLo; 6097 ExpandOp(Node->getOperand(0), NewLo, Hi); 6098 6099 // The low part is now either the right size, or it is closer. If not the 6100 // right size, make an illegal truncate so we recursively expand it. 6101 if (NewLo.getValueType() != Node->getValueType(0)) 6102 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 6103 ExpandOp(NewLo, Lo, Hi); 6104 break; 6105 } 6106 6107 case ISD::BIT_CONVERT: { 6108 SDOperand Tmp; 6109 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6110 // If the target wants to, allow it to lower this itself. 6111 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6112 case Expand: assert(0 && "cannot expand FP!"); 6113 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6114 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6115 } 6116 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 6117 } 6118 6119 // f32 / f64 must be expanded to i32 / i64. 6120 if (VT == MVT::f32 || VT == MVT::f64) { 6121 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6122 if (getTypeAction(NVT) == Expand) 6123 ExpandOp(Lo, Lo, Hi); 6124 break; 6125 } 6126 6127 // If source operand will be expanded to the same type as VT, i.e. 6128 // i64 <- f64, i32 <- f32, expand the source operand instead. 6129 MVT VT0 = Node->getOperand(0).getValueType(); 6130 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6131 ExpandOp(Node->getOperand(0), Lo, Hi); 6132 break; 6133 } 6134 6135 // Turn this into a load/store pair by default. 6136 if (Tmp.Val == 0) 6137 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 6138 6139 ExpandOp(Tmp, Lo, Hi); 6140 break; 6141 } 6142 6143 case ISD::READCYCLECOUNTER: { 6144 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6145 TargetLowering::Custom && 6146 "Must custom expand ReadCycleCounter"); 6147 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 6148 assert(Tmp.Val && "Node must be custom expanded!"); 6149 ExpandOp(Tmp.getValue(0), Lo, Hi); 6150 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6151 LegalizeOp(Tmp.getValue(1))); 6152 break; 6153 } 6154 6155 case ISD::ATOMIC_CMP_SWAP: { 6156 SDOperand Tmp = TLI.LowerOperation(Op, DAG); 6157 assert(Tmp.Val && "Node must be custom expanded!"); 6158 ExpandOp(Tmp.getValue(0), Lo, Hi); 6159 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain. 6160 LegalizeOp(Tmp.getValue(1))); 6161 break; 6162 } 6163 6164 6165 6166 // These operators cannot be expanded directly, emit them as calls to 6167 // library functions. 6168 case ISD::FP_TO_SINT: { 6169 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6170 SDOperand Op; 6171 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6172 case Expand: assert(0 && "cannot expand FP!"); 6173 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6174 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6175 } 6176 6177 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6178 6179 // Now that the custom expander is done, expand the result, which is still 6180 // VT. 6181 if (Op.Val) { 6182 ExpandOp(Op, Lo, Hi); 6183 break; 6184 } 6185 } 6186 6187 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6188 if (VT == MVT::i64) { 6189 if (Node->getOperand(0).getValueType() == MVT::f32) 6190 LC = RTLIB::FPTOSINT_F32_I64; 6191 else if (Node->getOperand(0).getValueType() == MVT::f64) 6192 LC = RTLIB::FPTOSINT_F64_I64; 6193 else if (Node->getOperand(0).getValueType() == MVT::f80) 6194 LC = RTLIB::FPTOSINT_F80_I64; 6195 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6196 LC = RTLIB::FPTOSINT_PPCF128_I64; 6197 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6198 } else if (VT == MVT::i128) { 6199 if (Node->getOperand(0).getValueType() == MVT::f32) 6200 LC = RTLIB::FPTOSINT_F32_I128; 6201 else if (Node->getOperand(0).getValueType() == MVT::f64) 6202 LC = RTLIB::FPTOSINT_F64_I128; 6203 else if (Node->getOperand(0).getValueType() == MVT::f80) 6204 LC = RTLIB::FPTOSINT_F80_I128; 6205 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6206 LC = RTLIB::FPTOSINT_PPCF128_I128; 6207 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6208 } else { 6209 assert(0 && "Unexpected uint-to-fp conversion!"); 6210 } 6211 break; 6212 } 6213 6214 case ISD::FP_TO_UINT: { 6215 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6216 SDOperand Op; 6217 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6218 case Expand: assert(0 && "cannot expand FP!"); 6219 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6220 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6221 } 6222 6223 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6224 6225 // Now that the custom expander is done, expand the result. 6226 if (Op.Val) { 6227 ExpandOp(Op, Lo, Hi); 6228 break; 6229 } 6230 } 6231 6232 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6233 if (VT == MVT::i64) { 6234 if (Node->getOperand(0).getValueType() == MVT::f32) 6235 LC = RTLIB::FPTOUINT_F32_I64; 6236 else if (Node->getOperand(0).getValueType() == MVT::f64) 6237 LC = RTLIB::FPTOUINT_F64_I64; 6238 else if (Node->getOperand(0).getValueType() == MVT::f80) 6239 LC = RTLIB::FPTOUINT_F80_I64; 6240 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6241 LC = RTLIB::FPTOUINT_PPCF128_I64; 6242 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6243 } else if (VT == MVT::i128) { 6244 if (Node->getOperand(0).getValueType() == MVT::f32) 6245 LC = RTLIB::FPTOUINT_F32_I128; 6246 else if (Node->getOperand(0).getValueType() == MVT::f64) 6247 LC = RTLIB::FPTOUINT_F64_I128; 6248 else if (Node->getOperand(0).getValueType() == MVT::f80) 6249 LC = RTLIB::FPTOUINT_F80_I128; 6250 else if (Node->getOperand(0).getValueType() == MVT::ppcf128) 6251 LC = RTLIB::FPTOUINT_PPCF128_I128; 6252 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6253 } else { 6254 assert(0 && "Unexpected uint-to-fp conversion!"); 6255 } 6256 break; 6257 } 6258 6259 case ISD::SHL: { 6260 // If the target wants custom lowering, do so. 6261 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6262 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6263 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6264 Op = TLI.LowerOperation(Op, DAG); 6265 if (Op.Val) { 6266 // Now that the custom expander is done, expand the result, which is 6267 // still VT. 6268 ExpandOp(Op, Lo, Hi); 6269 break; 6270 } 6271 } 6272 6273 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6274 // this X << 1 as X+X. 6275 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6276 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 6277 TLI.isOperationLegal(ISD::ADDE, NVT)) { 6278 SDOperand LoOps[2], HiOps[3]; 6279 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6280 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6281 LoOps[1] = LoOps[0]; 6282 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6283 6284 HiOps[1] = HiOps[0]; 6285 HiOps[2] = Lo.getValue(1); 6286 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6287 break; 6288 } 6289 } 6290 6291 // If we can emit an efficient shift operation, do so now. 6292 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6293 break; 6294 6295 // If this target supports SHL_PARTS, use it. 6296 TargetLowering::LegalizeAction Action = 6297 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6298 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6299 Action == TargetLowering::Custom) { 6300 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6301 break; 6302 } 6303 6304 // Otherwise, emit a libcall. 6305 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6306 break; 6307 } 6308 6309 case ISD::SRA: { 6310 // If the target wants custom lowering, do so. 6311 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6312 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6313 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6314 Op = TLI.LowerOperation(Op, DAG); 6315 if (Op.Val) { 6316 // Now that the custom expander is done, expand the result, which is 6317 // still VT. 6318 ExpandOp(Op, Lo, Hi); 6319 break; 6320 } 6321 } 6322 6323 // If we can emit an efficient shift operation, do so now. 6324 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6325 break; 6326 6327 // If this target supports SRA_PARTS, use it. 6328 TargetLowering::LegalizeAction Action = 6329 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6330 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6331 Action == TargetLowering::Custom) { 6332 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6333 break; 6334 } 6335 6336 // Otherwise, emit a libcall. 6337 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6338 break; 6339 } 6340 6341 case ISD::SRL: { 6342 // If the target wants custom lowering, do so. 6343 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1)); 6344 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6345 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6346 Op = TLI.LowerOperation(Op, DAG); 6347 if (Op.Val) { 6348 // Now that the custom expander is done, expand the result, which is 6349 // still VT. 6350 ExpandOp(Op, Lo, Hi); 6351 break; 6352 } 6353 } 6354 6355 // If we can emit an efficient shift operation, do so now. 6356 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6357 break; 6358 6359 // If this target supports SRL_PARTS, use it. 6360 TargetLowering::LegalizeAction Action = 6361 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6362 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6363 Action == TargetLowering::Custom) { 6364 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6365 break; 6366 } 6367 6368 // Otherwise, emit a libcall. 6369 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6370 break; 6371 } 6372 6373 case ISD::ADD: 6374 case ISD::SUB: { 6375 // If the target wants to custom expand this, let them. 6376 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6377 TargetLowering::Custom) { 6378 SDOperand Result = TLI.LowerOperation(Op, DAG); 6379 if (Result.Val) { 6380 ExpandOp(Result, Lo, Hi); 6381 break; 6382 } 6383 } 6384 6385 // Expand the subcomponents. 6386 SDOperand LHSL, LHSH, RHSL, RHSH; 6387 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6388 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6389 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6390 SDOperand LoOps[2], HiOps[3]; 6391 LoOps[0] = LHSL; 6392 LoOps[1] = RHSL; 6393 HiOps[0] = LHSH; 6394 HiOps[1] = RHSH; 6395 if (Node->getOpcode() == ISD::ADD) { 6396 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6397 HiOps[2] = Lo.getValue(1); 6398 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6399 } else { 6400 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6401 HiOps[2] = Lo.getValue(1); 6402 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6403 } 6404 break; 6405 } 6406 6407 case ISD::ADDC: 6408 case ISD::SUBC: { 6409 // Expand the subcomponents. 6410 SDOperand LHSL, LHSH, RHSL, RHSH; 6411 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6412 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6413 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6414 SDOperand LoOps[2] = { LHSL, RHSL }; 6415 SDOperand HiOps[3] = { LHSH, RHSH }; 6416 6417 if (Node->getOpcode() == ISD::ADDC) { 6418 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6419 HiOps[2] = Lo.getValue(1); 6420 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6421 } else { 6422 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6423 HiOps[2] = Lo.getValue(1); 6424 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6425 } 6426 // Remember that we legalized the flag. 6427 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6428 break; 6429 } 6430 case ISD::ADDE: 6431 case ISD::SUBE: { 6432 // Expand the subcomponents. 6433 SDOperand LHSL, LHSH, RHSL, RHSH; 6434 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6435 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6436 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6437 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 6438 SDOperand HiOps[3] = { LHSH, RHSH }; 6439 6440 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6441 HiOps[2] = Lo.getValue(1); 6442 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6443 6444 // Remember that we legalized the flag. 6445 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6446 break; 6447 } 6448 case ISD::MUL: { 6449 // If the target wants to custom expand this, let them. 6450 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6451 SDOperand New = TLI.LowerOperation(Op, DAG); 6452 if (New.Val) { 6453 ExpandOp(New, Lo, Hi); 6454 break; 6455 } 6456 } 6457 6458 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6459 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6460 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6461 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6462 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6463 SDOperand LL, LH, RL, RH; 6464 ExpandOp(Node->getOperand(0), LL, LH); 6465 ExpandOp(Node->getOperand(1), RL, RH); 6466 unsigned OuterBitSize = Op.getValueSizeInBits(); 6467 unsigned InnerBitSize = RH.getValueSizeInBits(); 6468 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6469 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6470 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 6471 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 6472 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 6473 // The inputs are both zero-extended. 6474 if (HasUMUL_LOHI) { 6475 // We can emit a umul_lohi. 6476 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6477 Hi = SDOperand(Lo.Val, 1); 6478 break; 6479 } 6480 if (HasMULHU) { 6481 // We can emit a mulhu+mul. 6482 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6483 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6484 break; 6485 } 6486 } 6487 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 6488 // The input values are both sign-extended. 6489 if (HasSMUL_LOHI) { 6490 // We can emit a smul_lohi. 6491 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6492 Hi = SDOperand(Lo.Val, 1); 6493 break; 6494 } 6495 if (HasMULHS) { 6496 // We can emit a mulhs+mul. 6497 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6498 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6499 break; 6500 } 6501 } 6502 if (HasUMUL_LOHI) { 6503 // Lo,Hi = umul LHS, RHS. 6504 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6505 DAG.getVTList(NVT, NVT), LL, RL); 6506 Lo = UMulLOHI; 6507 Hi = UMulLOHI.getValue(1); 6508 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6509 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6510 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6511 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6512 break; 6513 } 6514 if (HasMULHU) { 6515 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6516 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6517 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6518 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6519 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6520 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6521 break; 6522 } 6523 } 6524 6525 // If nothing else, we can make a libcall. 6526 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 6527 break; 6528 } 6529 case ISD::SDIV: 6530 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 6531 break; 6532 case ISD::UDIV: 6533 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 6534 break; 6535 case ISD::SREM: 6536 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 6537 break; 6538 case ISD::UREM: 6539 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 6540 break; 6541 6542 case ISD::FADD: 6543 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 6544 RTLIB::ADD_F64, 6545 RTLIB::ADD_F80, 6546 RTLIB::ADD_PPCF128), 6547 Node, false, Hi); 6548 break; 6549 case ISD::FSUB: 6550 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 6551 RTLIB::SUB_F64, 6552 RTLIB::SUB_F80, 6553 RTLIB::SUB_PPCF128), 6554 Node, false, Hi); 6555 break; 6556 case ISD::FMUL: 6557 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 6558 RTLIB::MUL_F64, 6559 RTLIB::MUL_F80, 6560 RTLIB::MUL_PPCF128), 6561 Node, false, Hi); 6562 break; 6563 case ISD::FDIV: 6564 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 6565 RTLIB::DIV_F64, 6566 RTLIB::DIV_F80, 6567 RTLIB::DIV_PPCF128), 6568 Node, false, Hi); 6569 break; 6570 case ISD::FP_EXTEND: 6571 if (VT == MVT::ppcf128) { 6572 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6573 Node->getOperand(0).getValueType()==MVT::f64); 6574 const uint64_t zero = 0; 6575 if (Node->getOperand(0).getValueType()==MVT::f32) 6576 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6577 else 6578 Hi = Node->getOperand(0); 6579 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6580 break; 6581 } 6582 Lo = ExpandLibCall(RTLIB::FPEXT_F32_F64, Node, true, Hi); 6583 break; 6584 case ISD::FP_ROUND: 6585 Lo = ExpandLibCall(RTLIB::FPROUND_F64_F32, Node, true, Hi); 6586 break; 6587 case ISD::FPOWI: 6588 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32, 6589 RTLIB::POWI_F64, 6590 RTLIB::POWI_F80, 6591 RTLIB::POWI_PPCF128), 6592 Node, false, Hi); 6593 break; 6594 case ISD::FSQRT: 6595 case ISD::FSIN: 6596 case ISD::FCOS: { 6597 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6598 switch(Node->getOpcode()) { 6599 case ISD::FSQRT: 6600 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6601 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6602 break; 6603 case ISD::FSIN: 6604 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6605 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6606 break; 6607 case ISD::FCOS: 6608 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6609 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6610 break; 6611 default: assert(0 && "Unreachable!"); 6612 } 6613 Lo = ExpandLibCall(LC, Node, false, Hi); 6614 break; 6615 } 6616 case ISD::FABS: { 6617 if (VT == MVT::ppcf128) { 6618 SDOperand Tmp; 6619 ExpandOp(Node->getOperand(0), Lo, Tmp); 6620 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6621 // lo = hi==fabs(hi) ? lo : -lo; 6622 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6623 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6624 DAG.getCondCode(ISD::SETEQ)); 6625 break; 6626 } 6627 SDOperand Mask = (VT == MVT::f64) 6628 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6629 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6630 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6631 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6632 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6633 if (getTypeAction(NVT) == Expand) 6634 ExpandOp(Lo, Lo, Hi); 6635 break; 6636 } 6637 case ISD::FNEG: { 6638 if (VT == MVT::ppcf128) { 6639 ExpandOp(Node->getOperand(0), Lo, Hi); 6640 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6641 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6642 break; 6643 } 6644 SDOperand Mask = (VT == MVT::f64) 6645 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6646 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6647 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6648 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6649 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6650 if (getTypeAction(NVT) == Expand) 6651 ExpandOp(Lo, Lo, Hi); 6652 break; 6653 } 6654 case ISD::FCOPYSIGN: { 6655 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6656 if (getTypeAction(NVT) == Expand) 6657 ExpandOp(Lo, Lo, Hi); 6658 break; 6659 } 6660 case ISD::SINT_TO_FP: 6661 case ISD::UINT_TO_FP: { 6662 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6663 MVT SrcVT = Node->getOperand(0).getValueType(); 6664 6665 // Promote the operand if needed. Do this before checking for 6666 // ppcf128 so conversions of i16 and i8 work. 6667 if (getTypeAction(SrcVT) == Promote) { 6668 SDOperand Tmp = PromoteOp(Node->getOperand(0)); 6669 Tmp = isSigned 6670 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6671 DAG.getValueType(SrcVT)) 6672 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6673 Node = DAG.UpdateNodeOperands(Op, Tmp).Val; 6674 SrcVT = Node->getOperand(0).getValueType(); 6675 } 6676 6677 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 6678 static const uint64_t zero = 0; 6679 if (isSigned) { 6680 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6681 Node->getOperand(0))); 6682 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6683 } else { 6684 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6685 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6686 Node->getOperand(0))); 6687 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6688 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6689 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6690 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6691 DAG.getConstant(0, MVT::i32), 6692 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6693 DAG.getConstantFP( 6694 APFloat(APInt(128, 2, TwoE32)), 6695 MVT::ppcf128)), 6696 Hi, 6697 DAG.getCondCode(ISD::SETLT)), 6698 Lo, Hi); 6699 } 6700 break; 6701 } 6702 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6703 // si64->ppcf128 done by libcall, below 6704 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6705 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6706 Lo, Hi); 6707 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6708 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6709 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6710 DAG.getConstant(0, MVT::i64), 6711 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6712 DAG.getConstantFP( 6713 APFloat(APInt(128, 2, TwoE64)), 6714 MVT::ppcf128)), 6715 Hi, 6716 DAG.getCondCode(ISD::SETLT)), 6717 Lo, Hi); 6718 break; 6719 } 6720 6721 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6722 Node->getOperand(0)); 6723 if (getTypeAction(Lo.getValueType()) == Expand) 6724 // float to i32 etc. can be 'expanded' to a single node. 6725 ExpandOp(Lo, Lo, Hi); 6726 break; 6727 } 6728 } 6729 6730 // Make sure the resultant values have been legalized themselves, unless this 6731 // is a type that requires multi-step expansion. 6732 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6733 Lo = LegalizeOp(Lo); 6734 if (Hi.Val) 6735 // Don't legalize the high part if it is expanded to a single node. 6736 Hi = LegalizeOp(Hi); 6737 } 6738 6739 // Remember in a map if the values will be reused later. 6740 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))); 6741 assert(isNew && "Value already expanded?!?"); 6742} 6743 6744/// SplitVectorOp - Given an operand of vector type, break it down into 6745/// two smaller values, still of vector type. 6746void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo, 6747 SDOperand &Hi) { 6748 assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); 6749 SDNode *Node = Op.Val; 6750 unsigned NumElements = Op.getValueType().getVectorNumElements(); 6751 assert(NumElements > 1 && "Cannot split a single element vector!"); 6752 6753 MVT NewEltVT = Op.getValueType().getVectorElementType(); 6754 6755 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6756 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6757 6758 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); 6759 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); 6760 6761 // See if we already split it. 6762 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I 6763 = SplitNodes.find(Op); 6764 if (I != SplitNodes.end()) { 6765 Lo = I->second.first; 6766 Hi = I->second.second; 6767 return; 6768 } 6769 6770 switch (Node->getOpcode()) { 6771 default: 6772#ifndef NDEBUG 6773 Node->dump(&DAG); 6774#endif 6775 assert(0 && "Unhandled operation in SplitVectorOp!"); 6776 case ISD::UNDEF: 6777 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6778 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6779 break; 6780 case ISD::BUILD_PAIR: 6781 Lo = Node->getOperand(0); 6782 Hi = Node->getOperand(1); 6783 break; 6784 case ISD::INSERT_VECTOR_ELT: { 6785 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 6786 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6787 unsigned Index = Idx->getValue(); 6788 SDOperand ScalarOp = Node->getOperand(1); 6789 if (Index < NewNumElts_Lo) 6790 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6791 DAG.getIntPtrConstant(Index)); 6792 else 6793 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6794 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 6795 break; 6796 } 6797 SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 6798 Node->getOperand(1), 6799 Node->getOperand(2)); 6800 SplitVectorOp(Tmp, Lo, Hi); 6801 break; 6802 } 6803 case ISD::VECTOR_SHUFFLE: { 6804 // Build the low part. 6805 SDOperand Mask = Node->getOperand(2); 6806 SmallVector<SDOperand, 8> Ops; 6807 MVT PtrVT = TLI.getPointerTy(); 6808 6809 // Insert all of the elements from the input that are needed. We use 6810 // buildvector of extractelement here because the input vectors will have 6811 // to be legalized, so this makes the code simpler. 6812 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6813 SDOperand IdxNode = Mask.getOperand(i); 6814 if (IdxNode.getOpcode() == ISD::UNDEF) { 6815 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6816 continue; 6817 } 6818 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6819 SDOperand InVec = Node->getOperand(0); 6820 if (Idx >= NumElements) { 6821 InVec = Node->getOperand(1); 6822 Idx -= NumElements; 6823 } 6824 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6825 DAG.getConstant(Idx, PtrVT))); 6826 } 6827 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6828 Ops.clear(); 6829 6830 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6831 SDOperand IdxNode = Mask.getOperand(i); 6832 if (IdxNode.getOpcode() == ISD::UNDEF) { 6833 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6834 continue; 6835 } 6836 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue(); 6837 SDOperand InVec = Node->getOperand(0); 6838 if (Idx >= NumElements) { 6839 InVec = Node->getOperand(1); 6840 Idx -= NumElements; 6841 } 6842 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6843 DAG.getConstant(Idx, PtrVT))); 6844 } 6845 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6846 break; 6847 } 6848 case ISD::BUILD_VECTOR: { 6849 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6850 Node->op_begin()+NewNumElts_Lo); 6851 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6852 6853 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6854 Node->op_end()); 6855 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6856 break; 6857 } 6858 case ISD::CONCAT_VECTORS: { 6859 // FIXME: Handle non-power-of-two vectors? 6860 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6861 if (NewNumSubvectors == 1) { 6862 Lo = Node->getOperand(0); 6863 Hi = Node->getOperand(1); 6864 } else { 6865 SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 6866 Node->op_begin()+NewNumSubvectors); 6867 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6868 6869 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6870 Node->op_end()); 6871 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6872 } 6873 break; 6874 } 6875 case ISD::SELECT: { 6876 SDOperand Cond = Node->getOperand(0); 6877 6878 SDOperand LL, LH, RL, RH; 6879 SplitVectorOp(Node->getOperand(1), LL, LH); 6880 SplitVectorOp(Node->getOperand(2), RL, RH); 6881 6882 if (Cond.getValueType().isVector()) { 6883 // Handle a vector merge. 6884 SDOperand CL, CH; 6885 SplitVectorOp(Cond, CL, CH); 6886 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6887 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6888 } else { 6889 // Handle a simple select with vector operands. 6890 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6891 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6892 } 6893 break; 6894 } 6895 case ISD::SELECT_CC: { 6896 SDOperand CondLHS = Node->getOperand(0); 6897 SDOperand CondRHS = Node->getOperand(1); 6898 SDOperand CondCode = Node->getOperand(4); 6899 6900 SDOperand LL, LH, RL, RH; 6901 SplitVectorOp(Node->getOperand(2), LL, LH); 6902 SplitVectorOp(Node->getOperand(3), RL, RH); 6903 6904 // Handle a simple select with vector operands. 6905 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS, 6906 LL, RL, CondCode); 6907 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS, 6908 LH, RH, CondCode); 6909 break; 6910 } 6911 case ISD::VSETCC: { 6912 SDOperand LL, LH, RL, RH; 6913 SplitVectorOp(Node->getOperand(0), LL, LH); 6914 SplitVectorOp(Node->getOperand(1), RL, RH); 6915 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2)); 6916 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2)); 6917 break; 6918 } 6919 case ISD::ADD: 6920 case ISD::SUB: 6921 case ISD::MUL: 6922 case ISD::FADD: 6923 case ISD::FSUB: 6924 case ISD::FMUL: 6925 case ISD::SDIV: 6926 case ISD::UDIV: 6927 case ISD::FDIV: 6928 case ISD::FPOW: 6929 case ISD::AND: 6930 case ISD::OR: 6931 case ISD::XOR: 6932 case ISD::UREM: 6933 case ISD::SREM: 6934 case ISD::FREM: { 6935 SDOperand LL, LH, RL, RH; 6936 SplitVectorOp(Node->getOperand(0), LL, LH); 6937 SplitVectorOp(Node->getOperand(1), RL, RH); 6938 6939 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 6940 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 6941 break; 6942 } 6943 case ISD::FPOWI: { 6944 SDOperand L, H; 6945 SplitVectorOp(Node->getOperand(0), L, H); 6946 6947 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 6948 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 6949 break; 6950 } 6951 case ISD::CTTZ: 6952 case ISD::CTLZ: 6953 case ISD::CTPOP: 6954 case ISD::FNEG: 6955 case ISD::FABS: 6956 case ISD::FSQRT: 6957 case ISD::FSIN: 6958 case ISD::FCOS: 6959 case ISD::FP_TO_SINT: 6960 case ISD::FP_TO_UINT: 6961 case ISD::SINT_TO_FP: 6962 case ISD::UINT_TO_FP: { 6963 SDOperand L, H; 6964 SplitVectorOp(Node->getOperand(0), L, H); 6965 6966 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 6967 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 6968 break; 6969 } 6970 case ISD::LOAD: { 6971 LoadSDNode *LD = cast<LoadSDNode>(Node); 6972 SDOperand Ch = LD->getChain(); 6973 SDOperand Ptr = LD->getBasePtr(); 6974 const Value *SV = LD->getSrcValue(); 6975 int SVOffset = LD->getSrcValueOffset(); 6976 unsigned Alignment = LD->getAlignment(); 6977 bool isVolatile = LD->isVolatile(); 6978 6979 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6980 unsigned IncrementSize = NewNumElts_Lo * NewEltVT.getSizeInBits()/8; 6981 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6982 DAG.getIntPtrConstant(IncrementSize)); 6983 SVOffset += IncrementSize; 6984 Alignment = MinAlign(Alignment, IncrementSize); 6985 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment); 6986 6987 // Build a factor node to remember that this load is independent of the 6988 // other one. 6989 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6990 Hi.getValue(1)); 6991 6992 // Remember that we legalized the chain. 6993 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6994 break; 6995 } 6996 case ISD::BIT_CONVERT: { 6997 // We know the result is a vector. The input may be either a vector or a 6998 // scalar value. 6999 SDOperand InOp = Node->getOperand(0); 7000 if (!InOp.getValueType().isVector() || 7001 InOp.getValueType().getVectorNumElements() == 1) { 7002 // The input is a scalar or single-element vector. 7003 // Lower to a store/load so that it can be split. 7004 // FIXME: this could be improved probably. 7005 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType()); 7006 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val); 7007 7008 SDOperand St = DAG.getStore(DAG.getEntryNode(), 7009 InOp, Ptr, 7010 PseudoSourceValue::getFixedStack(), 7011 FI->getIndex()); 7012 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 7013 PseudoSourceValue::getFixedStack(), 7014 FI->getIndex()); 7015 } 7016 // Split the vector and convert each of the pieces now. 7017 SplitVectorOp(InOp, Lo, Hi); 7018 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 7019 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 7020 break; 7021 } 7022 } 7023 7024 // Remember in a map if the values will be reused later. 7025 bool isNew = 7026 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7027 assert(isNew && "Value already split?!?"); 7028} 7029 7030 7031/// ScalarizeVectorOp - Given an operand of single-element vector type 7032/// (e.g. v1f32), convert it into the equivalent operation that returns a 7033/// scalar (e.g. f32) value. 7034SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) { 7035 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); 7036 SDNode *Node = Op.Val; 7037 MVT NewVT = Op.getValueType().getVectorElementType(); 7038 assert(Op.getValueType().getVectorNumElements() == 1); 7039 7040 // See if we already scalarized it. 7041 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op); 7042 if (I != ScalarizedNodes.end()) return I->second; 7043 7044 SDOperand Result; 7045 switch (Node->getOpcode()) { 7046 default: 7047#ifndef NDEBUG 7048 Node->dump(&DAG); cerr << "\n"; 7049#endif 7050 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7051 case ISD::ADD: 7052 case ISD::FADD: 7053 case ISD::SUB: 7054 case ISD::FSUB: 7055 case ISD::MUL: 7056 case ISD::FMUL: 7057 case ISD::SDIV: 7058 case ISD::UDIV: 7059 case ISD::FDIV: 7060 case ISD::SREM: 7061 case ISD::UREM: 7062 case ISD::FREM: 7063 case ISD::FPOW: 7064 case ISD::AND: 7065 case ISD::OR: 7066 case ISD::XOR: 7067 Result = DAG.getNode(Node->getOpcode(), 7068 NewVT, 7069 ScalarizeVectorOp(Node->getOperand(0)), 7070 ScalarizeVectorOp(Node->getOperand(1))); 7071 break; 7072 case ISD::FNEG: 7073 case ISD::FABS: 7074 case ISD::FSQRT: 7075 case ISD::FSIN: 7076 case ISD::FCOS: 7077 Result = DAG.getNode(Node->getOpcode(), 7078 NewVT, 7079 ScalarizeVectorOp(Node->getOperand(0))); 7080 break; 7081 case ISD::FPOWI: 7082 Result = DAG.getNode(Node->getOpcode(), 7083 NewVT, 7084 ScalarizeVectorOp(Node->getOperand(0)), 7085 Node->getOperand(1)); 7086 break; 7087 case ISD::LOAD: { 7088 LoadSDNode *LD = cast<LoadSDNode>(Node); 7089 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7090 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7091 7092 const Value *SV = LD->getSrcValue(); 7093 int SVOffset = LD->getSrcValueOffset(); 7094 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, 7095 LD->isVolatile(), LD->getAlignment()); 7096 7097 // Remember that we legalized the chain. 7098 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7099 break; 7100 } 7101 case ISD::BUILD_VECTOR: 7102 Result = Node->getOperand(0); 7103 break; 7104 case ISD::INSERT_VECTOR_ELT: 7105 // Returning the inserted scalar element. 7106 Result = Node->getOperand(1); 7107 break; 7108 case ISD::CONCAT_VECTORS: 7109 assert(Node->getOperand(0).getValueType() == NewVT && 7110 "Concat of non-legal vectors not yet supported!"); 7111 Result = Node->getOperand(0); 7112 break; 7113 case ISD::VECTOR_SHUFFLE: { 7114 // Figure out if the scalar is the LHS or RHS and return it. 7115 SDOperand EltNum = Node->getOperand(2).getOperand(0); 7116 if (cast<ConstantSDNode>(EltNum)->getValue()) 7117 Result = ScalarizeVectorOp(Node->getOperand(1)); 7118 else 7119 Result = ScalarizeVectorOp(Node->getOperand(0)); 7120 break; 7121 } 7122 case ISD::EXTRACT_SUBVECTOR: 7123 Result = Node->getOperand(0); 7124 assert(Result.getValueType() == NewVT); 7125 break; 7126 case ISD::BIT_CONVERT: { 7127 SDOperand Op0 = Op.getOperand(0); 7128 if (Op0.getValueType().getVectorNumElements() == 1) 7129 Op0 = ScalarizeVectorOp(Op0); 7130 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); 7131 break; 7132 } 7133 case ISD::SELECT: 7134 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 7135 ScalarizeVectorOp(Op.getOperand(1)), 7136 ScalarizeVectorOp(Op.getOperand(2))); 7137 break; 7138 case ISD::SELECT_CC: 7139 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0), 7140 Node->getOperand(1), 7141 ScalarizeVectorOp(Op.getOperand(2)), 7142 ScalarizeVectorOp(Op.getOperand(3)), 7143 Node->getOperand(4)); 7144 break; 7145 case ISD::VSETCC: { 7146 SDOperand Op0 = ScalarizeVectorOp(Op.getOperand(0)); 7147 SDOperand Op1 = ScalarizeVectorOp(Op.getOperand(1)); 7148 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1, 7149 Op.getOperand(2)); 7150 Result = DAG.getNode(ISD::SELECT, NewVT, Result, 7151 DAG.getConstant(-1ULL, NewVT), 7152 DAG.getConstant(0ULL, NewVT)); 7153 break; 7154 } 7155 } 7156 7157 if (TLI.isTypeLegal(NewVT)) 7158 Result = LegalizeOp(Result); 7159 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7160 assert(isNew && "Value already scalarized?"); 7161 return Result; 7162} 7163 7164 7165// SelectionDAG::Legalize - This is the entry point for the file. 7166// 7167void SelectionDAG::Legalize() { 7168 if (ViewLegalizeDAGs) viewGraph(); 7169 7170 /// run - This is the main entry point to this class. 7171 /// 7172 SelectionDAGLegalize(*this).LegalizeDAG(); 7173} 7174 7175