LegalizeDAG.cpp revision faeb4a35197737b3674fcfc34fd6e84220aa437b
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetFrameInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/Target/TargetSubtarget.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/SmallPtrSet.h" 35#include <map> 36using namespace llvm; 37 38//===----------------------------------------------------------------------===// 39/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 40/// hacks on it until the target machine can handle it. This involves 41/// eliminating value sizes the machine cannot handle (promoting small sizes to 42/// large sizes or splitting up large values into small values) as well as 43/// eliminating operations the machine cannot handle. 44/// 45/// This code also does a small amount of optimization and recognition of idioms 46/// as part of its processing. For example, if a target does not support a 47/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 48/// will attempt merge setcc and brc instructions into brcc's. 49/// 50namespace { 51class VISIBILITY_HIDDEN SelectionDAGLegalize { 52 TargetLowering &TLI; 53 SelectionDAG &DAG; 54 55 // Libcall insertion helpers. 56 57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 58 /// legalized. We use this to ensure that calls are properly serialized 59 /// against each other, including inserted libcalls. 60 SDValue LastCALLSEQ_END; 61 62 /// IsLegalizingCall - This member is used *only* for purposes of providing 63 /// helpful assertions that a libcall isn't created while another call is 64 /// being legalized (which could lead to non-serialized call sequences). 65 bool IsLegalizingCall; 66 67 enum LegalizeAction { 68 Legal, // The target natively supports this operation. 69 Promote, // This operation should be executed in a larger type. 70 Expand // Try to expand this to other ops, otherwise use a libcall. 71 }; 72 73 /// ValueTypeActions - This is a bitvector that contains two bits for each 74 /// value type, where the two bits correspond to the LegalizeAction enum. 75 /// This can be queried with "getTypeAction(VT)". 76 TargetLowering::ValueTypeActionImpl ValueTypeActions; 77 78 /// LegalizedNodes - For nodes that are of legal width, and that have more 79 /// than one use, this map indicates what regularized operand to use. This 80 /// allows us to avoid legalizing the same thing more than once. 81 DenseMap<SDValue, SDValue> LegalizedNodes; 82 83 /// PromotedNodes - For nodes that are below legal width, and that have more 84 /// than one use, this map indicates what promoted value to use. This allows 85 /// us to avoid promoting the same thing more than once. 86 DenseMap<SDValue, SDValue> PromotedNodes; 87 88 /// ExpandedNodes - For nodes that need to be expanded this map indicates 89 /// which which operands are the expanded version of the input. This allows 90 /// us to avoid expanding the same node more than once. 91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes; 92 93 /// SplitNodes - For vector nodes that need to be split, this map indicates 94 /// which which operands are the split version of the input. This allows us 95 /// to avoid splitting the same node more than once. 96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes; 97 98 /// ScalarizedNodes - For nodes that need to be converted from vector types to 99 /// scalar types, this contains the mapping of ones we have already 100 /// processed to the result. 101 std::map<SDValue, SDValue> ScalarizedNodes; 102 103 void AddLegalizedOperand(SDValue From, SDValue To) { 104 LegalizedNodes.insert(std::make_pair(From, To)); 105 // If someone requests legalization of the new node, return itself. 106 if (From != To) 107 LegalizedNodes.insert(std::make_pair(To, To)); 108 } 109 void AddPromotedOperand(SDValue From, SDValue To) { 110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 111 assert(isNew && "Got into the map somehow?"); 112 // If someone requests legalization of the new node, return itself. 113 LegalizedNodes.insert(std::make_pair(To, To)); 114 } 115 116public: 117 explicit SelectionDAGLegalize(SelectionDAG &DAG); 118 119 /// getTypeAction - Return how we should legalize values of this type, either 120 /// it is already legal or we need to expand it into multiple registers of 121 /// smaller integer type, or we need to promote it to a larger type. 122 LegalizeAction getTypeAction(MVT VT) const { 123 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 124 } 125 126 /// isTypeLegal - Return true if this type is legal on this target. 127 /// 128 bool isTypeLegal(MVT VT) const { 129 return getTypeAction(VT) == Legal; 130 } 131 132 void LegalizeDAG(); 133 134private: 135 /// HandleOp - Legalize, Promote, or Expand the specified operand as 136 /// appropriate for its type. 137 void HandleOp(SDValue Op); 138 139 /// LegalizeOp - We know that the specified value has a legal type. 140 /// Recursively ensure that the operands have legal types, then return the 141 /// result. 142 SDValue LegalizeOp(SDValue O); 143 144 /// UnrollVectorOp - We know that the given vector has a legal type, however 145 /// the operation it performs is not legal and is an operation that we have 146 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 147 /// operating on each element individually. 148 SDValue UnrollVectorOp(SDValue O); 149 150 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 151 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 152 /// is necessary to spill the vector being inserted into to memory, perform 153 /// the insert there, and then read the result back. 154 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 155 SDValue Idx); 156 157 /// PromoteOp - Given an operation that produces a value in an invalid type, 158 /// promote it to compute the value into a larger type. The produced value 159 /// will have the correct bits for the low portion of the register, but no 160 /// guarantee is made about the top bits: it may be zero, sign-extended, or 161 /// garbage. 162 SDValue PromoteOp(SDValue O); 163 164 /// ExpandOp - Expand the specified SDValue into its two component pieces 165 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 166 /// the LegalizeNodes map is filled in for any results that are not expanded, 167 /// the ExpandedNodes map is filled in for any results that are expanded, and 168 /// the Lo/Hi values are returned. This applies to integer types and Vector 169 /// types. 170 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi); 171 172 /// SplitVectorOp - Given an operand of vector type, break it down into 173 /// two smaller values. 174 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi); 175 176 /// ScalarizeVectorOp - Given an operand of single-element vector type 177 /// (e.g. v1f32), convert it into the equivalent operation that returns a 178 /// scalar (e.g. f32) value. 179 SDValue ScalarizeVectorOp(SDValue O); 180 181 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the 182 /// specified mask and type. Targets can specify exactly which masks they 183 /// support and the code generator is tasked with not creating illegal masks. 184 /// 185 /// Note that this will also return true for shuffles that are promoted to a 186 /// different type. 187 /// 188 /// If this is a legal shuffle, this method returns the (possibly promoted) 189 /// build_vector Mask. If it's not a legal shuffle, it returns null. 190 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const; 191 192 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 193 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 194 195 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC); 196 197 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 198 SDValue &Hi); 199 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source); 200 201 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT); 202 SDValue ExpandBUILD_VECTOR(SDNode *Node); 203 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 204 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op); 205 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT); 206 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned); 207 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned); 208 209 SDValue ExpandBSWAP(SDValue Op); 210 SDValue ExpandBitCount(unsigned Opc, SDValue Op); 211 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt, 212 SDValue &Lo, SDValue &Hi); 213 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt, 214 SDValue &Lo, SDValue &Hi); 215 216 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op); 217 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op); 218}; 219} 220 221/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 222/// specified mask and type. Targets can specify exactly which masks they 223/// support and the code generator is tasked with not creating illegal masks. 224/// 225/// Note that this will also return true for shuffles that are promoted to a 226/// different type. 227SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const { 228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 229 default: return 0; 230 case TargetLowering::Legal: 231 case TargetLowering::Custom: 232 break; 233 case TargetLowering::Promote: { 234 // If this is promoted to a different type, convert the shuffle mask and 235 // ask if it is legal in the promoted type! 236 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 237 MVT EltVT = NVT.getVectorElementType(); 238 239 // If we changed # elements, change the shuffle mask. 240 unsigned NumEltsGrowth = 241 NVT.getVectorNumElements() / VT.getVectorNumElements(); 242 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 243 if (NumEltsGrowth > 1) { 244 // Renumber the elements. 245 SmallVector<SDValue, 8> Ops; 246 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 247 SDValue InOp = Mask.getOperand(i); 248 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 249 if (InOp.getOpcode() == ISD::UNDEF) 250 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 251 else { 252 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue(); 253 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT)); 254 } 255 } 256 } 257 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 258 } 259 VT = NVT; 260 break; 261 } 262 } 263 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0; 264} 265 266SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 267 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 268 ValueTypeActions(TLI.getValueTypeActions()) { 269 assert(MVT::LAST_VALUETYPE <= 32 && 270 "Too many value types for ValueTypeActions to hold!"); 271} 272 273void SelectionDAGLegalize::LegalizeDAG() { 274 LastCALLSEQ_END = DAG.getEntryNode(); 275 IsLegalizingCall = false; 276 277 // The legalize process is inherently a bottom-up recursive process (users 278 // legalize their uses before themselves). Given infinite stack space, we 279 // could just start legalizing on the root and traverse the whole graph. In 280 // practice however, this causes us to run out of stack space on large basic 281 // blocks. To avoid this problem, compute an ordering of the nodes where each 282 // node is only legalized after all of its operands are legalized. 283 std::vector<SDNode *> TopOrder; 284 unsigned N = DAG.AssignTopologicalOrder(TopOrder); 285 for (unsigned i = N; i != 0; --i) 286 HandleOp(SDValue(TopOrder[i-1], 0)); 287 TopOrder.clear(); 288 289 // Finally, it's possible the root changed. Get the new root. 290 SDValue OldRoot = DAG.getRoot(); 291 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 292 DAG.setRoot(LegalizedNodes[OldRoot]); 293 294 ExpandedNodes.clear(); 295 LegalizedNodes.clear(); 296 PromotedNodes.clear(); 297 SplitNodes.clear(); 298 ScalarizedNodes.clear(); 299 300 // Remove dead nodes now. 301 DAG.RemoveDeadNodes(); 302} 303 304 305/// FindCallEndFromCallStart - Given a chained node that is part of a call 306/// sequence, find the CALLSEQ_END node that terminates the call sequence. 307static SDNode *FindCallEndFromCallStart(SDNode *Node) { 308 if (Node->getOpcode() == ISD::CALLSEQ_END) 309 return Node; 310 if (Node->use_empty()) 311 return 0; // No CallSeqEnd 312 313 // The chain is usually at the end. 314 SDValue TheChain(Node, Node->getNumValues()-1); 315 if (TheChain.getValueType() != MVT::Other) { 316 // Sometimes it's at the beginning. 317 TheChain = SDValue(Node, 0); 318 if (TheChain.getValueType() != MVT::Other) { 319 // Otherwise, hunt for it. 320 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 321 if (Node->getValueType(i) == MVT::Other) { 322 TheChain = SDValue(Node, i); 323 break; 324 } 325 326 // Otherwise, we walked into a node without a chain. 327 if (TheChain.getValueType() != MVT::Other) 328 return 0; 329 } 330 } 331 332 for (SDNode::use_iterator UI = Node->use_begin(), 333 E = Node->use_end(); UI != E; ++UI) { 334 335 // Make sure to only follow users of our token chain. 336 SDNode *User = *UI; 337 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 338 if (User->getOperand(i) == TheChain) 339 if (SDNode *Result = FindCallEndFromCallStart(User)) 340 return Result; 341 } 342 return 0; 343} 344 345/// FindCallStartFromCallEnd - Given a chained node that is part of a call 346/// sequence, find the CALLSEQ_START node that initiates the call sequence. 347static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 348 assert(Node && "Didn't find callseq_start for a call??"); 349 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 350 351 assert(Node->getOperand(0).getValueType() == MVT::Other && 352 "Node doesn't have a token chain argument!"); 353 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 354} 355 356/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 357/// see if any uses can reach Dest. If no dest operands can get to dest, 358/// legalize them, legalize ourself, and return false, otherwise, return true. 359/// 360/// Keep track of the nodes we fine that actually do lead to Dest in 361/// NodesLeadingTo. This avoids retraversing them exponential number of times. 362/// 363bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 364 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 365 if (N == Dest) return true; // N certainly leads to Dest :) 366 367 // If we've already processed this node and it does lead to Dest, there is no 368 // need to reprocess it. 369 if (NodesLeadingTo.count(N)) return true; 370 371 // If the first result of this node has been already legalized, then it cannot 372 // reach N. 373 switch (getTypeAction(N->getValueType(0))) { 374 case Legal: 375 if (LegalizedNodes.count(SDValue(N, 0))) return false; 376 break; 377 case Promote: 378 if (PromotedNodes.count(SDValue(N, 0))) return false; 379 break; 380 case Expand: 381 if (ExpandedNodes.count(SDValue(N, 0))) return false; 382 break; 383 } 384 385 // Okay, this node has not already been legalized. Check and legalize all 386 // operands. If none lead to Dest, then we can legalize this node. 387 bool OperandsLeadToDest = false; 388 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 389 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 390 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 391 392 if (OperandsLeadToDest) { 393 NodesLeadingTo.insert(N); 394 return true; 395 } 396 397 // Okay, this node looks safe, legalize it and return false. 398 HandleOp(SDValue(N, 0)); 399 return false; 400} 401 402/// HandleOp - Legalize, Promote, or Expand the specified operand as 403/// appropriate for its type. 404void SelectionDAGLegalize::HandleOp(SDValue Op) { 405 MVT VT = Op.getValueType(); 406 switch (getTypeAction(VT)) { 407 default: assert(0 && "Bad type action!"); 408 case Legal: (void)LegalizeOp(Op); break; 409 case Promote: (void)PromoteOp(Op); break; 410 case Expand: 411 if (!VT.isVector()) { 412 // If this is an illegal scalar, expand it into its two component 413 // pieces. 414 SDValue X, Y; 415 if (Op.getOpcode() == ISD::TargetConstant) 416 break; // Allow illegal target nodes. 417 ExpandOp(Op, X, Y); 418 } else if (VT.getVectorNumElements() == 1) { 419 // If this is an illegal single element vector, convert it to a 420 // scalar operation. 421 (void)ScalarizeVectorOp(Op); 422 } else { 423 // Otherwise, this is an illegal multiple element vector. 424 // Split it in half and legalize both parts. 425 SDValue X, Y; 426 SplitVectorOp(Op, X, Y); 427 } 428 break; 429 } 430} 431 432/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 433/// a load from the constant pool. 434static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 435 SelectionDAG &DAG, TargetLowering &TLI) { 436 bool Extend = false; 437 438 // If a FP immediate is precise when represented as a float and if the 439 // target can do an extending load from float to double, we put it into 440 // the constant pool as a float, even if it's is statically typed as a 441 // double. This shrinks FP constants and canonicalizes them for targets where 442 // an FP extending load is the same cost as a normal load (such as on the x87 443 // fp stack or PPC FP unit). 444 MVT VT = CFP->getValueType(0); 445 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF()); 446 if (!UseCP) { 447 if (VT!=MVT::f64 && VT!=MVT::f32) 448 assert(0 && "Invalid type expansion"); 449 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(), 450 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 451 } 452 453 MVT OrigVT = VT; 454 MVT SVT = VT; 455 while (SVT != MVT::f32) { 456 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 457 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 458 // Only do this if the target has a native EXTLOAD instruction from 459 // smaller type. 460 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) && 461 TLI.ShouldShrinkFPConstant(OrigVT)) { 462 const Type *SType = SVT.getTypeForMVT(); 463 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 464 VT = SVT; 465 Extend = true; 466 } 467 } 468 469 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 470 if (Extend) 471 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), 472 CPIdx, PseudoSourceValue::getConstantPool(), 473 0, VT); 474 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 475 PseudoSourceValue::getConstantPool(), 0); 476} 477 478 479/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 480/// operations. 481static 482SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, 483 SelectionDAG &DAG, TargetLowering &TLI) { 484 MVT VT = Node->getValueType(0); 485 MVT SrcVT = Node->getOperand(1).getValueType(); 486 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 487 "fcopysign expansion only supported for f32 and f64"); 488 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 489 490 // First get the sign bit of second operand. 491 SDValue Mask1 = (SrcVT == MVT::f64) 492 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 493 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 494 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 495 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 496 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 497 // Shift right or sign-extend it if the two operands have different types. 498 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); 499 if (SizeDiff > 0) { 500 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 501 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 502 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 503 } else if (SizeDiff < 0) { 504 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit); 505 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit, 506 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy())); 507 } 508 509 // Clear the sign bit of first operand. 510 SDValue Mask2 = (VT == MVT::f64) 511 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 512 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 513 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 514 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 515 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 516 517 // Or the value with the sign bit. 518 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 519 return Result; 520} 521 522/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 523static 524SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 525 TargetLowering &TLI) { 526 SDValue Chain = ST->getChain(); 527 SDValue Ptr = ST->getBasePtr(); 528 SDValue Val = ST->getValue(); 529 MVT VT = Val.getValueType(); 530 int Alignment = ST->getAlignment(); 531 int SVOffset = ST->getSrcValueOffset(); 532 if (ST->getMemoryVT().isFloatingPoint() || 533 ST->getMemoryVT().isVector()) { 534 // Expand to a bitconvert of the value to the integer type of the 535 // same size, then a (misaligned) int store. 536 MVT intVT; 537 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128) 538 intVT = MVT::i128; 539 else if (VT.is64BitVector() || VT==MVT::f64) 540 intVT = MVT::i64; 541 else if (VT==MVT::f32) 542 intVT = MVT::i32; 543 else 544 assert(0 && "Unaligned store of unsupported type"); 545 546 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 547 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 548 SVOffset, ST->isVolatile(), Alignment); 549 } 550 assert(ST->getMemoryVT().isInteger() && 551 !ST->getMemoryVT().isVector() && 552 "Unaligned store of unknown type."); 553 // Get the half-size VT 554 MVT NewStoredVT = 555 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 556 int NumBits = NewStoredVT.getSizeInBits(); 557 int IncrementSize = NumBits / 8; 558 559 // Divide the stored value in two parts. 560 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 561 SDValue Lo = Val; 562 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 563 564 // Store the two parts 565 SDValue Store1, Store2; 566 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 567 ST->getSrcValue(), SVOffset, NewStoredVT, 568 ST->isVolatile(), Alignment); 569 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 570 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 571 Alignment = MinAlign(Alignment, IncrementSize); 572 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 573 ST->getSrcValue(), SVOffset + IncrementSize, 574 NewStoredVT, ST->isVolatile(), Alignment); 575 576 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 577} 578 579/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 580static 581SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 582 TargetLowering &TLI) { 583 int SVOffset = LD->getSrcValueOffset(); 584 SDValue Chain = LD->getChain(); 585 SDValue Ptr = LD->getBasePtr(); 586 MVT VT = LD->getValueType(0); 587 MVT LoadedVT = LD->getMemoryVT(); 588 if (VT.isFloatingPoint() || VT.isVector()) { 589 // Expand to a (misaligned) integer load of the same size, 590 // then bitconvert to floating point or vector. 591 MVT intVT; 592 if (LoadedVT.is128BitVector() || 593 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128) 594 intVT = MVT::i128; 595 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64) 596 intVT = MVT::i64; 597 else if (LoadedVT == MVT::f32) 598 intVT = MVT::i32; 599 else 600 assert(0 && "Unaligned load of unsupported type"); 601 602 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 603 SVOffset, LD->isVolatile(), 604 LD->getAlignment()); 605 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 606 if (VT.isFloatingPoint() && LoadedVT != VT) 607 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 608 609 SDValue Ops[] = { Result, Chain }; 610 return DAG.getMergeValues(Ops, 2); 611 } 612 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 613 "Unaligned load of unsupported type."); 614 615 // Compute the new VT that is half the size of the old one. This is an 616 // integer MVT. 617 unsigned NumBits = LoadedVT.getSizeInBits(); 618 MVT NewLoadedVT; 619 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 620 NumBits >>= 1; 621 622 unsigned Alignment = LD->getAlignment(); 623 unsigned IncrementSize = NumBits / 8; 624 ISD::LoadExtType HiExtType = LD->getExtensionType(); 625 626 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 627 if (HiExtType == ISD::NON_EXTLOAD) 628 HiExtType = ISD::ZEXTLOAD; 629 630 // Load the value in two parts 631 SDValue Lo, Hi; 632 if (TLI.isLittleEndian()) { 633 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 634 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 635 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 636 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 637 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 638 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 639 MinAlign(Alignment, IncrementSize)); 640 } else { 641 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 642 NewLoadedVT,LD->isVolatile(), Alignment); 643 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 644 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 645 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 646 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 647 MinAlign(Alignment, IncrementSize)); 648 } 649 650 // aggregate the two parts 651 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 652 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 653 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 654 655 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 656 Hi.getValue(1)); 657 658 SDValue Ops[] = { Result, TF }; 659 return DAG.getMergeValues(Ops, 2); 660} 661 662/// UnrollVectorOp - We know that the given vector has a legal type, however 663/// the operation it performs is not legal and is an operation that we have 664/// no way of lowering. "Unroll" the vector, splitting out the scalars and 665/// operating on each element individually. 666SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) { 667 MVT VT = Op.getValueType(); 668 assert(isTypeLegal(VT) && 669 "Caller should expand or promote operands that are not legal!"); 670 assert(Op.getNode()->getNumValues() == 1 && 671 "Can't unroll a vector with multiple results!"); 672 unsigned NE = VT.getVectorNumElements(); 673 MVT EltVT = VT.getVectorElementType(); 674 675 SmallVector<SDValue, 8> Scalars; 676 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 677 for (unsigned i = 0; i != NE; ++i) { 678 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 679 SDValue Operand = Op.getOperand(j); 680 MVT OperandVT = Operand.getValueType(); 681 if (OperandVT.isVector()) { 682 // A vector operand; extract a single element. 683 MVT OperandEltVT = OperandVT.getVectorElementType(); 684 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 685 OperandEltVT, 686 Operand, 687 DAG.getConstant(i, MVT::i32)); 688 } else { 689 // A scalar operand; just use it as is. 690 Operands[j] = Operand; 691 } 692 } 693 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 694 &Operands[0], Operands.size())); 695 } 696 697 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 698} 699 700/// GetFPLibCall - Return the right libcall for the given floating point type. 701static RTLIB::Libcall GetFPLibCall(MVT VT, 702 RTLIB::Libcall Call_F32, 703 RTLIB::Libcall Call_F64, 704 RTLIB::Libcall Call_F80, 705 RTLIB::Libcall Call_PPCF128) { 706 return 707 VT == MVT::f32 ? Call_F32 : 708 VT == MVT::f64 ? Call_F64 : 709 VT == MVT::f80 ? Call_F80 : 710 VT == MVT::ppcf128 ? Call_PPCF128 : 711 RTLIB::UNKNOWN_LIBCALL; 712} 713 714/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 715/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 716/// is necessary to spill the vector being inserted into to memory, perform 717/// the insert there, and then read the result back. 718SDValue SelectionDAGLegalize:: 719PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) { 720 SDValue Tmp1 = Vec; 721 SDValue Tmp2 = Val; 722 SDValue Tmp3 = Idx; 723 724 // If the target doesn't support this, we have to spill the input vector 725 // to a temporary stack slot, update the element, then reload it. This is 726 // badness. We could also load the value into a vector register (either 727 // with a "move to register" or "extload into register" instruction, then 728 // permute it into place, if the idx is a constant and if the idx is 729 // supported by the target. 730 MVT VT = Tmp1.getValueType(); 731 MVT EltVT = VT.getVectorElementType(); 732 MVT IdxVT = Tmp3.getValueType(); 733 MVT PtrVT = TLI.getPointerTy(); 734 SDValue StackPtr = DAG.CreateStackTemporary(VT); 735 736 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 737 738 // Store the vector. 739 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, 740 PseudoSourceValue::getFixedStack(SPFI), 0); 741 742 // Truncate or zero extend offset to target pointer type. 743 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 744 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 745 // Add the offset to the index. 746 unsigned EltSize = EltVT.getSizeInBits()/8; 747 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 748 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 749 // Store the scalar value. 750 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, 751 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 752 // Load the updated vector. 753 return DAG.getLoad(VT, Ch, StackPtr, 754 PseudoSourceValue::getFixedStack(SPFI), 0); 755} 756 757/// LegalizeOp - We know that the specified value has a legal type, and 758/// that its operands are legal. Now ensure that the operation itself 759/// is legal, recursively ensuring that the operands' operations remain 760/// legal. 761SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 762 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 763 return Op; 764 765 assert(isTypeLegal(Op.getValueType()) && 766 "Caller should expand or promote operands that are not legal!"); 767 SDNode *Node = Op.getNode(); 768 769 // If this operation defines any values that cannot be represented in a 770 // register on this target, make sure to expand or promote them. 771 if (Node->getNumValues() > 1) { 772 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 773 if (getTypeAction(Node->getValueType(i)) != Legal) { 774 HandleOp(Op.getValue(i)); 775 assert(LegalizedNodes.count(Op) && 776 "Handling didn't add legal operands!"); 777 return LegalizedNodes[Op]; 778 } 779 } 780 781 // Note that LegalizeOp may be reentered even from single-use nodes, which 782 // means that we always must cache transformed nodes. 783 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 784 if (I != LegalizedNodes.end()) return I->second; 785 786 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 787 SDValue Result = Op; 788 bool isCustom = false; 789 790 switch (Node->getOpcode()) { 791 case ISD::FrameIndex: 792 case ISD::EntryToken: 793 case ISD::Register: 794 case ISD::BasicBlock: 795 case ISD::TargetFrameIndex: 796 case ISD::TargetJumpTable: 797 case ISD::TargetConstant: 798 case ISD::TargetConstantFP: 799 case ISD::TargetConstantPool: 800 case ISD::TargetGlobalAddress: 801 case ISD::TargetGlobalTLSAddress: 802 case ISD::TargetExternalSymbol: 803 case ISD::VALUETYPE: 804 case ISD::SRCVALUE: 805 case ISD::MEMOPERAND: 806 case ISD::CONDCODE: 807 case ISD::ARG_FLAGS: 808 // Primitives must all be legal. 809 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 810 "This must be legal!"); 811 break; 812 default: 813 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 814 // If this is a target node, legalize it by legalizing the operands then 815 // passing it through. 816 SmallVector<SDValue, 8> Ops; 817 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 818 Ops.push_back(LegalizeOp(Node->getOperand(i))); 819 820 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 821 822 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 823 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 824 return Result.getValue(Op.getResNo()); 825 } 826 // Otherwise this is an unhandled builtin node. splat. 827#ifndef NDEBUG 828 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 829#endif 830 assert(0 && "Do not know how to legalize this operator!"); 831 abort(); 832 case ISD::GLOBAL_OFFSET_TABLE: 833 case ISD::GlobalAddress: 834 case ISD::GlobalTLSAddress: 835 case ISD::ExternalSymbol: 836 case ISD::ConstantPool: 837 case ISD::JumpTable: // Nothing to do. 838 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 839 default: assert(0 && "This action is not supported yet!"); 840 case TargetLowering::Custom: 841 Tmp1 = TLI.LowerOperation(Op, DAG); 842 if (Tmp1.getNode()) Result = Tmp1; 843 // FALLTHROUGH if the target doesn't want to lower this op after all. 844 case TargetLowering::Legal: 845 break; 846 } 847 break; 848 case ISD::FRAMEADDR: 849 case ISD::RETURNADDR: 850 // The only option for these nodes is to custom lower them. If the target 851 // does not custom lower them, then return zero. 852 Tmp1 = TLI.LowerOperation(Op, DAG); 853 if (Tmp1.getNode()) 854 Result = Tmp1; 855 else 856 Result = DAG.getConstant(0, TLI.getPointerTy()); 857 break; 858 case ISD::FRAME_TO_ARGS_OFFSET: { 859 MVT VT = Node->getValueType(0); 860 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 861 default: assert(0 && "This action is not supported yet!"); 862 case TargetLowering::Custom: 863 Result = TLI.LowerOperation(Op, DAG); 864 if (Result.getNode()) break; 865 // Fall Thru 866 case TargetLowering::Legal: 867 Result = DAG.getConstant(0, VT); 868 break; 869 } 870 } 871 break; 872 case ISD::EXCEPTIONADDR: { 873 Tmp1 = LegalizeOp(Node->getOperand(0)); 874 MVT VT = Node->getValueType(0); 875 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 876 default: assert(0 && "This action is not supported yet!"); 877 case TargetLowering::Expand: { 878 unsigned Reg = TLI.getExceptionAddressRegister(); 879 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 880 } 881 break; 882 case TargetLowering::Custom: 883 Result = TLI.LowerOperation(Op, DAG); 884 if (Result.getNode()) break; 885 // Fall Thru 886 case TargetLowering::Legal: { 887 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 888 Result = DAG.getMergeValues(Ops, 2); 889 break; 890 } 891 } 892 } 893 if (Result.getNode()->getNumValues() == 1) break; 894 895 assert(Result.getNode()->getNumValues() == 2 && 896 "Cannot return more than two values!"); 897 898 // Since we produced two values, make sure to remember that we 899 // legalized both of them. 900 Tmp1 = LegalizeOp(Result); 901 Tmp2 = LegalizeOp(Result.getValue(1)); 902 AddLegalizedOperand(Op.getValue(0), Tmp1); 903 AddLegalizedOperand(Op.getValue(1), Tmp2); 904 return Op.getResNo() ? Tmp2 : Tmp1; 905 case ISD::EHSELECTION: { 906 Tmp1 = LegalizeOp(Node->getOperand(0)); 907 Tmp2 = LegalizeOp(Node->getOperand(1)); 908 MVT VT = Node->getValueType(0); 909 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 910 default: assert(0 && "This action is not supported yet!"); 911 case TargetLowering::Expand: { 912 unsigned Reg = TLI.getExceptionSelectorRegister(); 913 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 914 } 915 break; 916 case TargetLowering::Custom: 917 Result = TLI.LowerOperation(Op, DAG); 918 if (Result.getNode()) break; 919 // Fall Thru 920 case TargetLowering::Legal: { 921 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 922 Result = DAG.getMergeValues(Ops, 2); 923 break; 924 } 925 } 926 } 927 if (Result.getNode()->getNumValues() == 1) break; 928 929 assert(Result.getNode()->getNumValues() == 2 && 930 "Cannot return more than two values!"); 931 932 // Since we produced two values, make sure to remember that we 933 // legalized both of them. 934 Tmp1 = LegalizeOp(Result); 935 Tmp2 = LegalizeOp(Result.getValue(1)); 936 AddLegalizedOperand(Op.getValue(0), Tmp1); 937 AddLegalizedOperand(Op.getValue(1), Tmp2); 938 return Op.getResNo() ? Tmp2 : Tmp1; 939 case ISD::EH_RETURN: { 940 MVT VT = Node->getValueType(0); 941 // The only "good" option for this node is to custom lower it. 942 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 943 default: assert(0 && "This action is not supported at all!"); 944 case TargetLowering::Custom: 945 Result = TLI.LowerOperation(Op, DAG); 946 if (Result.getNode()) break; 947 // Fall Thru 948 case TargetLowering::Legal: 949 // Target does not know, how to lower this, lower to noop 950 Result = LegalizeOp(Node->getOperand(0)); 951 break; 952 } 953 } 954 break; 955 case ISD::AssertSext: 956 case ISD::AssertZext: 957 Tmp1 = LegalizeOp(Node->getOperand(0)); 958 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 959 break; 960 case ISD::MERGE_VALUES: 961 // Legalize eliminates MERGE_VALUES nodes. 962 Result = Node->getOperand(Op.getResNo()); 963 break; 964 case ISD::CopyFromReg: 965 Tmp1 = LegalizeOp(Node->getOperand(0)); 966 Result = Op.getValue(0); 967 if (Node->getNumValues() == 2) { 968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 969 } else { 970 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 971 if (Node->getNumOperands() == 3) { 972 Tmp2 = LegalizeOp(Node->getOperand(2)); 973 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 974 } else { 975 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 976 } 977 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 978 } 979 // Since CopyFromReg produces two values, make sure to remember that we 980 // legalized both of them. 981 AddLegalizedOperand(Op.getValue(0), Result); 982 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 983 return Result.getValue(Op.getResNo()); 984 case ISD::UNDEF: { 985 MVT VT = Op.getValueType(); 986 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 987 default: assert(0 && "This action is not supported yet!"); 988 case TargetLowering::Expand: 989 if (VT.isInteger()) 990 Result = DAG.getConstant(0, VT); 991 else if (VT.isFloatingPoint()) 992 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), 993 VT); 994 else 995 assert(0 && "Unknown value type!"); 996 break; 997 case TargetLowering::Legal: 998 break; 999 } 1000 break; 1001 } 1002 1003 case ISD::INTRINSIC_W_CHAIN: 1004 case ISD::INTRINSIC_WO_CHAIN: 1005 case ISD::INTRINSIC_VOID: { 1006 SmallVector<SDValue, 8> Ops; 1007 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1008 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1009 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1010 1011 // Allow the target to custom lower its intrinsics if it wants to. 1012 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1013 TargetLowering::Custom) { 1014 Tmp3 = TLI.LowerOperation(Result, DAG); 1015 if (Tmp3.getNode()) Result = Tmp3; 1016 } 1017 1018 if (Result.getNode()->getNumValues() == 1) break; 1019 1020 // Must have return value and chain result. 1021 assert(Result.getNode()->getNumValues() == 2 && 1022 "Cannot return more than two values!"); 1023 1024 // Since loads produce two values, make sure to remember that we 1025 // legalized both of them. 1026 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1027 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1028 return Result.getValue(Op.getResNo()); 1029 } 1030 1031 case ISD::DBG_STOPPOINT: 1032 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!"); 1033 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1034 1035 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) { 1036 case TargetLowering::Promote: 1037 default: assert(0 && "This action is not supported yet!"); 1038 case TargetLowering::Expand: { 1039 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1040 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1041 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other); 1042 1043 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1044 if (MMI && (useDEBUG_LOC || useLABEL)) { 1045 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit(); 1046 unsigned SrcFile = MMI->RecordSource(CompileUnit); 1047 1048 unsigned Line = DSP->getLine(); 1049 unsigned Col = DSP->getColumn(); 1050 1051 if (useDEBUG_LOC) { 1052 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), 1053 DAG.getConstant(Col, MVT::i32), 1054 DAG.getConstant(SrcFile, MVT::i32) }; 1055 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4); 1056 } else { 1057 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 1058 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID); 1059 } 1060 } else { 1061 Result = Tmp1; // chain 1062 } 1063 break; 1064 } 1065 case TargetLowering::Legal: { 1066 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1067 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1068 break; 1069 1070 SmallVector<SDValue, 8> Ops; 1071 Ops.push_back(Tmp1); 1072 if (Action == Legal) { 1073 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1074 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1075 } else { 1076 // Otherwise promote them. 1077 Ops.push_back(PromoteOp(Node->getOperand(1))); 1078 Ops.push_back(PromoteOp(Node->getOperand(2))); 1079 } 1080 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1081 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1082 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1083 break; 1084 } 1085 } 1086 break; 1087 1088 case ISD::DECLARE: 1089 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1090 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1091 default: assert(0 && "This action is not supported yet!"); 1092 case TargetLowering::Legal: 1093 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1094 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1095 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1096 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1097 break; 1098 case TargetLowering::Expand: 1099 Result = LegalizeOp(Node->getOperand(0)); 1100 break; 1101 } 1102 break; 1103 1104 case ISD::DEBUG_LOC: 1105 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1106 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1107 default: assert(0 && "This action is not supported yet!"); 1108 case TargetLowering::Legal: { 1109 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1110 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1111 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1112 break; 1113 if (Action == Legal) { 1114 Tmp2 = Node->getOperand(1); 1115 Tmp3 = Node->getOperand(2); 1116 Tmp4 = Node->getOperand(3); 1117 } else { 1118 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1119 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1120 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1121 } 1122 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1123 break; 1124 } 1125 } 1126 break; 1127 1128 case ISD::DBG_LABEL: 1129 case ISD::EH_LABEL: 1130 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!"); 1131 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1132 default: assert(0 && "This action is not supported yet!"); 1133 case TargetLowering::Legal: 1134 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1135 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1136 break; 1137 case TargetLowering::Expand: 1138 Result = LegalizeOp(Node->getOperand(0)); 1139 break; 1140 } 1141 break; 1142 1143 case ISD::PREFETCH: 1144 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1145 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1146 default: assert(0 && "This action is not supported yet!"); 1147 case TargetLowering::Legal: 1148 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1149 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1150 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1151 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1152 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1153 break; 1154 case TargetLowering::Expand: 1155 // It's a noop. 1156 Result = LegalizeOp(Node->getOperand(0)); 1157 break; 1158 } 1159 break; 1160 1161 case ISD::MEMBARRIER: { 1162 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1163 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1164 default: assert(0 && "This action is not supported yet!"); 1165 case TargetLowering::Legal: { 1166 SDValue Ops[6]; 1167 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1168 for (int x = 1; x < 6; ++x) { 1169 Ops[x] = Node->getOperand(x); 1170 if (!isTypeLegal(Ops[x].getValueType())) 1171 Ops[x] = PromoteOp(Ops[x]); 1172 } 1173 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1174 break; 1175 } 1176 case TargetLowering::Expand: 1177 //There is no libgcc call for this op 1178 Result = Node->getOperand(0); // Noop 1179 break; 1180 } 1181 break; 1182 } 1183 1184 case ISD::ATOMIC_CMP_SWAP_8: 1185 case ISD::ATOMIC_CMP_SWAP_16: 1186 case ISD::ATOMIC_CMP_SWAP_32: 1187 case ISD::ATOMIC_CMP_SWAP_64: { 1188 unsigned int num_operands = 4; 1189 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1190 SDValue Ops[4]; 1191 for (unsigned int x = 0; x < num_operands; ++x) 1192 Ops[x] = LegalizeOp(Node->getOperand(x)); 1193 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1194 1195 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1196 default: assert(0 && "This action is not supported yet!"); 1197 case TargetLowering::Custom: 1198 Result = TLI.LowerOperation(Result, DAG); 1199 break; 1200 case TargetLowering::Legal: 1201 break; 1202 } 1203 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1204 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1205 return Result.getValue(Op.getResNo()); 1206 } 1207 case ISD::ATOMIC_LOAD_ADD_8: 1208 case ISD::ATOMIC_LOAD_SUB_8: 1209 case ISD::ATOMIC_LOAD_AND_8: 1210 case ISD::ATOMIC_LOAD_OR_8: 1211 case ISD::ATOMIC_LOAD_XOR_8: 1212 case ISD::ATOMIC_LOAD_NAND_8: 1213 case ISD::ATOMIC_LOAD_MIN_8: 1214 case ISD::ATOMIC_LOAD_MAX_8: 1215 case ISD::ATOMIC_LOAD_UMIN_8: 1216 case ISD::ATOMIC_LOAD_UMAX_8: 1217 case ISD::ATOMIC_SWAP_8: 1218 case ISD::ATOMIC_LOAD_ADD_16: 1219 case ISD::ATOMIC_LOAD_SUB_16: 1220 case ISD::ATOMIC_LOAD_AND_16: 1221 case ISD::ATOMIC_LOAD_OR_16: 1222 case ISD::ATOMIC_LOAD_XOR_16: 1223 case ISD::ATOMIC_LOAD_NAND_16: 1224 case ISD::ATOMIC_LOAD_MIN_16: 1225 case ISD::ATOMIC_LOAD_MAX_16: 1226 case ISD::ATOMIC_LOAD_UMIN_16: 1227 case ISD::ATOMIC_LOAD_UMAX_16: 1228 case ISD::ATOMIC_SWAP_16: 1229 case ISD::ATOMIC_LOAD_ADD_32: 1230 case ISD::ATOMIC_LOAD_SUB_32: 1231 case ISD::ATOMIC_LOAD_AND_32: 1232 case ISD::ATOMIC_LOAD_OR_32: 1233 case ISD::ATOMIC_LOAD_XOR_32: 1234 case ISD::ATOMIC_LOAD_NAND_32: 1235 case ISD::ATOMIC_LOAD_MIN_32: 1236 case ISD::ATOMIC_LOAD_MAX_32: 1237 case ISD::ATOMIC_LOAD_UMIN_32: 1238 case ISD::ATOMIC_LOAD_UMAX_32: 1239 case ISD::ATOMIC_SWAP_32: 1240 case ISD::ATOMIC_LOAD_ADD_64: 1241 case ISD::ATOMIC_LOAD_SUB_64: 1242 case ISD::ATOMIC_LOAD_AND_64: 1243 case ISD::ATOMIC_LOAD_OR_64: 1244 case ISD::ATOMIC_LOAD_XOR_64: 1245 case ISD::ATOMIC_LOAD_NAND_64: 1246 case ISD::ATOMIC_LOAD_MIN_64: 1247 case ISD::ATOMIC_LOAD_MAX_64: 1248 case ISD::ATOMIC_LOAD_UMIN_64: 1249 case ISD::ATOMIC_LOAD_UMAX_64: 1250 case ISD::ATOMIC_SWAP_64: { 1251 unsigned int num_operands = 3; 1252 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1253 SDValue Ops[3]; 1254 for (unsigned int x = 0; x < num_operands; ++x) 1255 Ops[x] = LegalizeOp(Node->getOperand(x)); 1256 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1257 1258 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1259 default: assert(0 && "This action is not supported yet!"); 1260 case TargetLowering::Custom: 1261 Result = TLI.LowerOperation(Result, DAG); 1262 break; 1263 case TargetLowering::Expand: 1264 Result = SDValue(TLI.ReplaceNodeResults(Op.getNode(), DAG),0); 1265 break; 1266 case TargetLowering::Legal: 1267 break; 1268 } 1269 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1270 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1271 return Result.getValue(Op.getResNo()); 1272 } 1273 case ISD::Constant: { 1274 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1275 unsigned opAction = 1276 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1277 1278 // We know we don't need to expand constants here, constants only have one 1279 // value and we check that it is fine above. 1280 1281 if (opAction == TargetLowering::Custom) { 1282 Tmp1 = TLI.LowerOperation(Result, DAG); 1283 if (Tmp1.getNode()) 1284 Result = Tmp1; 1285 } 1286 break; 1287 } 1288 case ISD::ConstantFP: { 1289 // Spill FP immediates to the constant pool if the target cannot directly 1290 // codegen them. Targets often have some immediate values that can be 1291 // efficiently generated into an FP register without a load. We explicitly 1292 // leave these constants as ConstantFP nodes for the target to deal with. 1293 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1294 1295 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1296 default: assert(0 && "This action is not supported yet!"); 1297 case TargetLowering::Legal: 1298 break; 1299 case TargetLowering::Custom: 1300 Tmp3 = TLI.LowerOperation(Result, DAG); 1301 if (Tmp3.getNode()) { 1302 Result = Tmp3; 1303 break; 1304 } 1305 // FALLTHROUGH 1306 case TargetLowering::Expand: { 1307 // Check to see if this FP immediate is already legal. 1308 bool isLegal = false; 1309 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1310 E = TLI.legal_fpimm_end(); I != E; ++I) { 1311 if (CFP->isExactlyValue(*I)) { 1312 isLegal = true; 1313 break; 1314 } 1315 } 1316 // If this is a legal constant, turn it into a TargetConstantFP node. 1317 if (isLegal) 1318 break; 1319 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1320 } 1321 } 1322 break; 1323 } 1324 case ISD::TokenFactor: 1325 if (Node->getNumOperands() == 2) { 1326 Tmp1 = LegalizeOp(Node->getOperand(0)); 1327 Tmp2 = LegalizeOp(Node->getOperand(1)); 1328 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1329 } else if (Node->getNumOperands() == 3) { 1330 Tmp1 = LegalizeOp(Node->getOperand(0)); 1331 Tmp2 = LegalizeOp(Node->getOperand(1)); 1332 Tmp3 = LegalizeOp(Node->getOperand(2)); 1333 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1334 } else { 1335 SmallVector<SDValue, 8> Ops; 1336 // Legalize the operands. 1337 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1338 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1339 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1340 } 1341 break; 1342 1343 case ISD::FORMAL_ARGUMENTS: 1344 case ISD::CALL: 1345 // The only option for this is to custom lower it. 1346 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1347 assert(Tmp3.getNode() && "Target didn't custom lower this node!"); 1348 // A call within a calling sequence must be legalized to something 1349 // other than the normal CALLSEQ_END. Violating this gets Legalize 1350 // into an infinite loop. 1351 assert ((!IsLegalizingCall || 1352 Node->getOpcode() != ISD::CALL || 1353 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) && 1354 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1355 1356 // The number of incoming and outgoing values should match; unless the final 1357 // outgoing value is a flag. 1358 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || 1359 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 && 1360 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == 1361 MVT::Flag)) && 1362 "Lowering call/formal_arguments produced unexpected # results!"); 1363 1364 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1365 // remember that we legalized all of them, so it doesn't get relegalized. 1366 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) { 1367 if (Tmp3.getNode()->getValueType(i) == MVT::Flag) 1368 continue; 1369 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1370 if (Op.getResNo() == i) 1371 Tmp2 = Tmp1; 1372 AddLegalizedOperand(SDValue(Node, i), Tmp1); 1373 } 1374 return Tmp2; 1375 case ISD::EXTRACT_SUBREG: { 1376 Tmp1 = LegalizeOp(Node->getOperand(0)); 1377 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1378 assert(idx && "Operand must be a constant"); 1379 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); 1380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1381 } 1382 break; 1383 case ISD::INSERT_SUBREG: { 1384 Tmp1 = LegalizeOp(Node->getOperand(0)); 1385 Tmp2 = LegalizeOp(Node->getOperand(1)); 1386 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1387 assert(idx && "Operand must be a constant"); 1388 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); 1389 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1390 } 1391 break; 1392 case ISD::BUILD_VECTOR: 1393 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1394 default: assert(0 && "This action is not supported yet!"); 1395 case TargetLowering::Custom: 1396 Tmp3 = TLI.LowerOperation(Result, DAG); 1397 if (Tmp3.getNode()) { 1398 Result = Tmp3; 1399 break; 1400 } 1401 // FALLTHROUGH 1402 case TargetLowering::Expand: 1403 Result = ExpandBUILD_VECTOR(Result.getNode()); 1404 break; 1405 } 1406 break; 1407 case ISD::INSERT_VECTOR_ELT: 1408 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1409 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1410 1411 // The type of the value to insert may not be legal, even though the vector 1412 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1413 // here. 1414 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1415 default: assert(0 && "Cannot expand insert element operand"); 1416 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1417 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1418 } 1419 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1420 1421 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1422 Node->getValueType(0))) { 1423 default: assert(0 && "This action is not supported yet!"); 1424 case TargetLowering::Legal: 1425 break; 1426 case TargetLowering::Custom: 1427 Tmp4 = TLI.LowerOperation(Result, DAG); 1428 if (Tmp4.getNode()) { 1429 Result = Tmp4; 1430 break; 1431 } 1432 // FALLTHROUGH 1433 case TargetLowering::Expand: { 1434 // If the insert index is a constant, codegen this as a scalar_to_vector, 1435 // then a shuffle that inserts it into the right position in the vector. 1436 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1437 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1438 // match the element type of the vector being created. 1439 if (Tmp2.getValueType() == 1440 Op.getValueType().getVectorElementType()) { 1441 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1442 Tmp1.getValueType(), Tmp2); 1443 1444 unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); 1445 MVT ShufMaskVT = 1446 MVT::getIntVectorWithNumElements(NumElts); 1447 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); 1448 1449 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1450 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1451 // elt 0 of the RHS. 1452 SmallVector<SDValue, 8> ShufOps; 1453 for (unsigned i = 0; i != NumElts; ++i) { 1454 if (i != InsertPos->getZExtValue()) 1455 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1456 else 1457 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1458 } 1459 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1460 &ShufOps[0], ShufOps.size()); 1461 1462 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1463 Tmp1, ScVec, ShufMask); 1464 Result = LegalizeOp(Result); 1465 break; 1466 } 1467 } 1468 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3); 1469 break; 1470 } 1471 } 1472 break; 1473 case ISD::SCALAR_TO_VECTOR: 1474 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1475 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1476 break; 1477 } 1478 1479 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1480 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1481 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1482 Node->getValueType(0))) { 1483 default: assert(0 && "This action is not supported yet!"); 1484 case TargetLowering::Legal: 1485 break; 1486 case TargetLowering::Custom: 1487 Tmp3 = TLI.LowerOperation(Result, DAG); 1488 if (Tmp3.getNode()) { 1489 Result = Tmp3; 1490 break; 1491 } 1492 // FALLTHROUGH 1493 case TargetLowering::Expand: 1494 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1495 break; 1496 } 1497 break; 1498 case ISD::VECTOR_SHUFFLE: 1499 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1500 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1501 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1502 1503 // Allow targets to custom lower the SHUFFLEs they support. 1504 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1505 default: assert(0 && "Unknown operation action!"); 1506 case TargetLowering::Legal: 1507 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1508 "vector shuffle should not be created if not legal!"); 1509 break; 1510 case TargetLowering::Custom: 1511 Tmp3 = TLI.LowerOperation(Result, DAG); 1512 if (Tmp3.getNode()) { 1513 Result = Tmp3; 1514 break; 1515 } 1516 // FALLTHROUGH 1517 case TargetLowering::Expand: { 1518 MVT VT = Node->getValueType(0); 1519 MVT EltVT = VT.getVectorElementType(); 1520 MVT PtrVT = TLI.getPointerTy(); 1521 SDValue Mask = Node->getOperand(2); 1522 unsigned NumElems = Mask.getNumOperands(); 1523 SmallVector<SDValue,8> Ops; 1524 for (unsigned i = 0; i != NumElems; ++i) { 1525 SDValue Arg = Mask.getOperand(i); 1526 if (Arg.getOpcode() == ISD::UNDEF) { 1527 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1528 } else { 1529 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1530 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue(); 1531 if (Idx < NumElems) 1532 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1533 DAG.getConstant(Idx, PtrVT))); 1534 else 1535 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1536 DAG.getConstant(Idx - NumElems, PtrVT))); 1537 } 1538 } 1539 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1540 break; 1541 } 1542 case TargetLowering::Promote: { 1543 // Change base type to a different vector type. 1544 MVT OVT = Node->getValueType(0); 1545 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1546 1547 // Cast the two input vectors. 1548 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1549 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1550 1551 // Convert the shuffle mask to the right # elements. 1552 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1553 assert(Tmp3.getNode() && "Shuffle not legal?"); 1554 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1555 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1556 break; 1557 } 1558 } 1559 break; 1560 1561 case ISD::EXTRACT_VECTOR_ELT: 1562 Tmp1 = Node->getOperand(0); 1563 Tmp2 = LegalizeOp(Node->getOperand(1)); 1564 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1565 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1566 break; 1567 1568 case ISD::EXTRACT_SUBVECTOR: 1569 Tmp1 = Node->getOperand(0); 1570 Tmp2 = LegalizeOp(Node->getOperand(1)); 1571 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1572 Result = ExpandEXTRACT_SUBVECTOR(Result); 1573 break; 1574 1575 case ISD::CALLSEQ_START: { 1576 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1577 1578 // Recursively Legalize all of the inputs of the call end that do not lead 1579 // to this call start. This ensures that any libcalls that need be inserted 1580 // are inserted *before* the CALLSEQ_START. 1581 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1582 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1583 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1584 NodesLeadingTo); 1585 } 1586 1587 // Now that we legalized all of the inputs (which may have inserted 1588 // libcalls) create the new CALLSEQ_START node. 1589 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1590 1591 // Merge in the last call, to ensure that this call start after the last 1592 // call ended. 1593 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1594 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1595 Tmp1 = LegalizeOp(Tmp1); 1596 } 1597 1598 // Do not try to legalize the target-specific arguments (#1+). 1599 if (Tmp1 != Node->getOperand(0)) { 1600 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1601 Ops[0] = Tmp1; 1602 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1603 } 1604 1605 // Remember that the CALLSEQ_START is legalized. 1606 AddLegalizedOperand(Op.getValue(0), Result); 1607 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1608 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1609 1610 // Now that the callseq_start and all of the non-call nodes above this call 1611 // sequence have been legalized, legalize the call itself. During this 1612 // process, no libcalls can/will be inserted, guaranteeing that no calls 1613 // can overlap. 1614 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1615 // Note that we are selecting this call! 1616 LastCALLSEQ_END = SDValue(CallEnd, 0); 1617 IsLegalizingCall = true; 1618 1619 // Legalize the call, starting from the CALLSEQ_END. 1620 LegalizeOp(LastCALLSEQ_END); 1621 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1622 return Result; 1623 } 1624 case ISD::CALLSEQ_END: 1625 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1626 // will cause this node to be legalized as well as handling libcalls right. 1627 if (LastCALLSEQ_END.getNode() != Node) { 1628 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1629 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1630 assert(I != LegalizedNodes.end() && 1631 "Legalizing the call start should have legalized this node!"); 1632 return I->second; 1633 } 1634 1635 // Otherwise, the call start has been legalized and everything is going 1636 // according to plan. Just legalize ourselves normally here. 1637 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1638 // Do not try to legalize the target-specific arguments (#1+), except for 1639 // an optional flag input. 1640 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1641 if (Tmp1 != Node->getOperand(0)) { 1642 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1643 Ops[0] = Tmp1; 1644 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1645 } 1646 } else { 1647 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1648 if (Tmp1 != Node->getOperand(0) || 1649 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1650 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1651 Ops[0] = Tmp1; 1652 Ops.back() = Tmp2; 1653 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1654 } 1655 } 1656 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1657 // This finishes up call legalization. 1658 IsLegalizingCall = false; 1659 1660 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1661 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1662 if (Node->getNumValues() == 2) 1663 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1664 return Result.getValue(Op.getResNo()); 1665 case ISD::DYNAMIC_STACKALLOC: { 1666 MVT VT = Node->getValueType(0); 1667 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1668 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1669 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1670 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1671 1672 Tmp1 = Result.getValue(0); 1673 Tmp2 = Result.getValue(1); 1674 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1675 default: assert(0 && "This action is not supported yet!"); 1676 case TargetLowering::Expand: { 1677 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1678 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1679 " not tell us which reg is the stack pointer!"); 1680 SDValue Chain = Tmp1.getOperand(0); 1681 1682 // Chain the dynamic stack allocation so that it doesn't modify the stack 1683 // pointer when other instructions are using the stack. 1684 Chain = DAG.getCALLSEQ_START(Chain, 1685 DAG.getConstant(0, TLI.getPointerTy())); 1686 1687 SDValue Size = Tmp2.getOperand(1); 1688 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1689 Chain = SP.getValue(1); 1690 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1691 unsigned StackAlign = 1692 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1693 if (Align > StackAlign) 1694 SP = DAG.getNode(ISD::AND, VT, SP, 1695 DAG.getConstant(-(uint64_t)Align, VT)); 1696 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1697 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1698 1699 Tmp2 = 1700 DAG.getCALLSEQ_END(Chain, 1701 DAG.getConstant(0, TLI.getPointerTy()), 1702 DAG.getConstant(0, TLI.getPointerTy()), 1703 SDValue()); 1704 1705 Tmp1 = LegalizeOp(Tmp1); 1706 Tmp2 = LegalizeOp(Tmp2); 1707 break; 1708 } 1709 case TargetLowering::Custom: 1710 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1711 if (Tmp3.getNode()) { 1712 Tmp1 = LegalizeOp(Tmp3); 1713 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1714 } 1715 break; 1716 case TargetLowering::Legal: 1717 break; 1718 } 1719 // Since this op produce two values, make sure to remember that we 1720 // legalized both of them. 1721 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1722 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1723 return Op.getResNo() ? Tmp2 : Tmp1; 1724 } 1725 case ISD::INLINEASM: { 1726 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1727 bool Changed = false; 1728 // Legalize all of the operands of the inline asm, in case they are nodes 1729 // that need to be expanded or something. Note we skip the asm string and 1730 // all of the TargetConstant flags. 1731 SDValue Op = LegalizeOp(Ops[0]); 1732 Changed = Op != Ops[0]; 1733 Ops[0] = Op; 1734 1735 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1736 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1737 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3; 1738 for (++i; NumVals; ++i, --NumVals) { 1739 SDValue Op = LegalizeOp(Ops[i]); 1740 if (Op != Ops[i]) { 1741 Changed = true; 1742 Ops[i] = Op; 1743 } 1744 } 1745 } 1746 1747 if (HasInFlag) { 1748 Op = LegalizeOp(Ops.back()); 1749 Changed |= Op != Ops.back(); 1750 Ops.back() = Op; 1751 } 1752 1753 if (Changed) 1754 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1755 1756 // INLINE asm returns a chain and flag, make sure to add both to the map. 1757 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1758 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1759 return Result.getValue(Op.getResNo()); 1760 } 1761 case ISD::BR: 1762 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1763 // Ensure that libcalls are emitted before a branch. 1764 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1765 Tmp1 = LegalizeOp(Tmp1); 1766 LastCALLSEQ_END = DAG.getEntryNode(); 1767 1768 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1769 break; 1770 case ISD::BRIND: 1771 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1772 // Ensure that libcalls are emitted before a branch. 1773 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1774 Tmp1 = LegalizeOp(Tmp1); 1775 LastCALLSEQ_END = DAG.getEntryNode(); 1776 1777 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1778 default: assert(0 && "Indirect target must be legal type (pointer)!"); 1779 case Legal: 1780 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1781 break; 1782 } 1783 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1784 break; 1785 case ISD::BR_JT: 1786 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1787 // Ensure that libcalls are emitted before a branch. 1788 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1789 Tmp1 = LegalizeOp(Tmp1); 1790 LastCALLSEQ_END = DAG.getEntryNode(); 1791 1792 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 1793 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1794 1795 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 1796 default: assert(0 && "This action is not supported yet!"); 1797 case TargetLowering::Legal: break; 1798 case TargetLowering::Custom: 1799 Tmp1 = TLI.LowerOperation(Result, DAG); 1800 if (Tmp1.getNode()) Result = Tmp1; 1801 break; 1802 case TargetLowering::Expand: { 1803 SDValue Chain = Result.getOperand(0); 1804 SDValue Table = Result.getOperand(1); 1805 SDValue Index = Result.getOperand(2); 1806 1807 MVT PTy = TLI.getPointerTy(); 1808 MachineFunction &MF = DAG.getMachineFunction(); 1809 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 1810 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 1811 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1812 1813 SDValue LD; 1814 switch (EntrySize) { 1815 default: assert(0 && "Size of jump table not supported yet."); break; 1816 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, 1817 PseudoSourceValue::getJumpTable(), 0); break; 1818 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, 1819 PseudoSourceValue::getJumpTable(), 0); break; 1820 } 1821 1822 Addr = LD; 1823 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1824 // For PIC, the sequence is: 1825 // BRIND(load(Jumptable + index) + RelocBase) 1826 // RelocBase can be JumpTable, GOT or some sort of global base. 1827 if (PTy != MVT::i32) 1828 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr); 1829 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 1830 TLI.getPICJumpTableRelocBase(Table, DAG)); 1831 } 1832 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 1833 } 1834 } 1835 break; 1836 case ISD::BRCOND: 1837 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1838 // Ensure that libcalls are emitted before a return. 1839 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1840 Tmp1 = LegalizeOp(Tmp1); 1841 LastCALLSEQ_END = DAG.getEntryNode(); 1842 1843 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1844 case Expand: assert(0 && "It's impossible to expand bools"); 1845 case Legal: 1846 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 1847 break; 1848 case Promote: { 1849 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 1850 1851 // The top bits of the promoted condition are not necessarily zero, ensure 1852 // that the value is properly zero extended. 1853 unsigned BitWidth = Tmp2.getValueSizeInBits(); 1854 if (!DAG.MaskedValueIsZero(Tmp2, 1855 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 1856 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 1857 break; 1858 } 1859 } 1860 1861 // Basic block destination (Op#2) is always legal. 1862 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1863 1864 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 1865 default: assert(0 && "This action is not supported yet!"); 1866 case TargetLowering::Legal: break; 1867 case TargetLowering::Custom: 1868 Tmp1 = TLI.LowerOperation(Result, DAG); 1869 if (Tmp1.getNode()) Result = Tmp1; 1870 break; 1871 case TargetLowering::Expand: 1872 // Expand brcond's setcc into its constituent parts and create a BR_CC 1873 // Node. 1874 if (Tmp2.getOpcode() == ISD::SETCC) { 1875 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 1876 Tmp2.getOperand(0), Tmp2.getOperand(1), 1877 Node->getOperand(2)); 1878 } else { 1879 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 1880 DAG.getCondCode(ISD::SETNE), Tmp2, 1881 DAG.getConstant(0, Tmp2.getValueType()), 1882 Node->getOperand(2)); 1883 } 1884 break; 1885 } 1886 break; 1887 case ISD::BR_CC: 1888 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1889 // Ensure that libcalls are emitted before a branch. 1890 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1891 Tmp1 = LegalizeOp(Tmp1); 1892 Tmp2 = Node->getOperand(2); // LHS 1893 Tmp3 = Node->getOperand(3); // RHS 1894 Tmp4 = Node->getOperand(1); // CC 1895 1896 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4); 1897 LastCALLSEQ_END = DAG.getEntryNode(); 1898 1899 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 1900 // the LHS is a legal SETCC itself. In this case, we need to compare 1901 // the result against zero to select between true and false values. 1902 if (Tmp3.getNode() == 0) { 1903 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 1904 Tmp4 = DAG.getCondCode(ISD::SETNE); 1905 } 1906 1907 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 1908 Node->getOperand(4)); 1909 1910 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 1911 default: assert(0 && "Unexpected action for BR_CC!"); 1912 case TargetLowering::Legal: break; 1913 case TargetLowering::Custom: 1914 Tmp4 = TLI.LowerOperation(Result, DAG); 1915 if (Tmp4.getNode()) Result = Tmp4; 1916 break; 1917 } 1918 break; 1919 case ISD::LOAD: { 1920 LoadSDNode *LD = cast<LoadSDNode>(Node); 1921 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 1922 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 1923 1924 ISD::LoadExtType ExtType = LD->getExtensionType(); 1925 if (ExtType == ISD::NON_EXTLOAD) { 1926 MVT VT = Node->getValueType(0); 1927 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 1928 Tmp3 = Result.getValue(0); 1929 Tmp4 = Result.getValue(1); 1930 1931 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1932 default: assert(0 && "This action is not supported yet!"); 1933 case TargetLowering::Legal: 1934 // If this is an unaligned load and the target doesn't support it, 1935 // expand it. 1936 if (!TLI.allowsUnalignedMemoryAccesses()) { 1937 unsigned ABIAlignment = TLI.getTargetData()-> 1938 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 1939 if (LD->getAlignment() < ABIAlignment){ 1940 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 1941 TLI); 1942 Tmp3 = Result.getOperand(0); 1943 Tmp4 = Result.getOperand(1); 1944 Tmp3 = LegalizeOp(Tmp3); 1945 Tmp4 = LegalizeOp(Tmp4); 1946 } 1947 } 1948 break; 1949 case TargetLowering::Custom: 1950 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 1951 if (Tmp1.getNode()) { 1952 Tmp3 = LegalizeOp(Tmp1); 1953 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1954 } 1955 break; 1956 case TargetLowering::Promote: { 1957 // Only promote a load of vector type to another. 1958 assert(VT.isVector() && "Cannot promote this load!"); 1959 // Change base type to a different vector type. 1960 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 1961 1962 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 1963 LD->getSrcValueOffset(), 1964 LD->isVolatile(), LD->getAlignment()); 1965 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 1966 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 1967 break; 1968 } 1969 } 1970 // Since loads produce two values, make sure to remember that we 1971 // legalized both of them. 1972 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 1973 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 1974 return Op.getResNo() ? Tmp4 : Tmp3; 1975 } else { 1976 MVT SrcVT = LD->getMemoryVT(); 1977 unsigned SrcWidth = SrcVT.getSizeInBits(); 1978 int SVOffset = LD->getSrcValueOffset(); 1979 unsigned Alignment = LD->getAlignment(); 1980 bool isVolatile = LD->isVolatile(); 1981 1982 if (SrcWidth != SrcVT.getStoreSizeInBits() && 1983 // Some targets pretend to have an i1 loading operation, and actually 1984 // load an i8. This trick is correct for ZEXTLOAD because the top 7 1985 // bits are guaranteed to be zero; it helps the optimizers understand 1986 // that these bits are zero. It is also useful for EXTLOAD, since it 1987 // tells the optimizers that those bits are undefined. It would be 1988 // nice to have an effective generic way of getting these benefits... 1989 // Until such a way is found, don't insist on promoting i1 here. 1990 (SrcVT != MVT::i1 || 1991 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 1992 // Promote to a byte-sized load if not loading an integral number of 1993 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 1994 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 1995 MVT NVT = MVT::getIntegerVT(NewWidth); 1996 SDValue Ch; 1997 1998 // The extra bits are guaranteed to be zero, since we stored them that 1999 // way. A zext load from NVT thus automatically gives zext from SrcVT. 2000 2001 ISD::LoadExtType NewExtType = 2002 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2003 2004 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 2005 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2006 NVT, isVolatile, Alignment); 2007 2008 Ch = Result.getValue(1); // The chain. 2009 2010 if (ExtType == ISD::SEXTLOAD) 2011 // Having the top bits zero doesn't help when sign extending. 2012 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2013 Result, DAG.getValueType(SrcVT)); 2014 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2015 // All the top bits are guaranteed to be zero - inform the optimizers. 2016 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 2017 DAG.getValueType(SrcVT)); 2018 2019 Tmp1 = LegalizeOp(Result); 2020 Tmp2 = LegalizeOp(Ch); 2021 } else if (SrcWidth & (SrcWidth - 1)) { 2022 // If not loading a power-of-2 number of bits, expand as two loads. 2023 assert(SrcVT.isExtended() && !SrcVT.isVector() && 2024 "Unsupported extload!"); 2025 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2026 assert(RoundWidth < SrcWidth); 2027 unsigned ExtraWidth = SrcWidth - RoundWidth; 2028 assert(ExtraWidth < RoundWidth); 2029 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2030 "Load size not an integral number of bytes!"); 2031 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2032 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2033 SDValue Lo, Hi, Ch; 2034 unsigned IncrementSize; 2035 2036 if (TLI.isLittleEndian()) { 2037 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2038 // Load the bottom RoundWidth bits. 2039 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2040 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2041 Alignment); 2042 2043 // Load the remaining ExtraWidth bits. 2044 IncrementSize = RoundWidth / 8; 2045 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2046 DAG.getIntPtrConstant(IncrementSize)); 2047 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2048 LD->getSrcValue(), SVOffset + IncrementSize, 2049 ExtraVT, isVolatile, 2050 MinAlign(Alignment, IncrementSize)); 2051 2052 // Build a factor node to remember that this load is independent of the 2053 // other one. 2054 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2055 Hi.getValue(1)); 2056 2057 // Move the top bits to the right place. 2058 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2059 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2060 2061 // Join the hi and lo parts. 2062 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2063 } else { 2064 // Big endian - avoid unaligned loads. 2065 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2066 // Load the top RoundWidth bits. 2067 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2068 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2069 Alignment); 2070 2071 // Load the remaining ExtraWidth bits. 2072 IncrementSize = RoundWidth / 8; 2073 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2074 DAG.getIntPtrConstant(IncrementSize)); 2075 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2076 LD->getSrcValue(), SVOffset + IncrementSize, 2077 ExtraVT, isVolatile, 2078 MinAlign(Alignment, IncrementSize)); 2079 2080 // Build a factor node to remember that this load is independent of the 2081 // other one. 2082 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2083 Hi.getValue(1)); 2084 2085 // Move the top bits to the right place. 2086 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2087 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2088 2089 // Join the hi and lo parts. 2090 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2091 } 2092 2093 Tmp1 = LegalizeOp(Result); 2094 Tmp2 = LegalizeOp(Ch); 2095 } else { 2096 switch (TLI.getLoadXAction(ExtType, SrcVT)) { 2097 default: assert(0 && "This action is not supported yet!"); 2098 case TargetLowering::Custom: 2099 isCustom = true; 2100 // FALLTHROUGH 2101 case TargetLowering::Legal: 2102 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2103 Tmp1 = Result.getValue(0); 2104 Tmp2 = Result.getValue(1); 2105 2106 if (isCustom) { 2107 Tmp3 = TLI.LowerOperation(Result, DAG); 2108 if (Tmp3.getNode()) { 2109 Tmp1 = LegalizeOp(Tmp3); 2110 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2111 } 2112 } else { 2113 // If this is an unaligned load and the target doesn't support it, 2114 // expand it. 2115 if (!TLI.allowsUnalignedMemoryAccesses()) { 2116 unsigned ABIAlignment = TLI.getTargetData()-> 2117 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2118 if (LD->getAlignment() < ABIAlignment){ 2119 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 2120 TLI); 2121 Tmp1 = Result.getOperand(0); 2122 Tmp2 = Result.getOperand(1); 2123 Tmp1 = LegalizeOp(Tmp1); 2124 Tmp2 = LegalizeOp(Tmp2); 2125 } 2126 } 2127 } 2128 break; 2129 case TargetLowering::Expand: 2130 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2131 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2132 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2133 LD->getSrcValueOffset(), 2134 LD->isVolatile(), LD->getAlignment()); 2135 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2136 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2137 Tmp2 = LegalizeOp(Load.getValue(1)); 2138 break; 2139 } 2140 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2141 // Turn the unsupported load into an EXTLOAD followed by an explicit 2142 // zero/sign extend inreg. 2143 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2144 Tmp1, Tmp2, LD->getSrcValue(), 2145 LD->getSrcValueOffset(), SrcVT, 2146 LD->isVolatile(), LD->getAlignment()); 2147 SDValue ValRes; 2148 if (ExtType == ISD::SEXTLOAD) 2149 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2150 Result, DAG.getValueType(SrcVT)); 2151 else 2152 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2153 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2154 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2155 break; 2156 } 2157 } 2158 2159 // Since loads produce two values, make sure to remember that we legalized 2160 // both of them. 2161 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2162 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2163 return Op.getResNo() ? Tmp2 : Tmp1; 2164 } 2165 } 2166 case ISD::EXTRACT_ELEMENT: { 2167 MVT OpTy = Node->getOperand(0).getValueType(); 2168 switch (getTypeAction(OpTy)) { 2169 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2170 case Legal: 2171 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2172 // 1 -> Hi 2173 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2174 DAG.getConstant(OpTy.getSizeInBits()/2, 2175 TLI.getShiftAmountTy())); 2176 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2177 } else { 2178 // 0 -> Lo 2179 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2180 Node->getOperand(0)); 2181 } 2182 break; 2183 case Expand: 2184 // Get both the low and high parts. 2185 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2186 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) 2187 Result = Tmp2; // 1 -> Hi 2188 else 2189 Result = Tmp1; // 0 -> Lo 2190 break; 2191 } 2192 break; 2193 } 2194 2195 case ISD::CopyToReg: 2196 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2197 2198 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2199 "Register type must be legal!"); 2200 // Legalize the incoming value (must be a legal type). 2201 Tmp2 = LegalizeOp(Node->getOperand(2)); 2202 if (Node->getNumValues() == 1) { 2203 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2204 } else { 2205 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2206 if (Node->getNumOperands() == 4) { 2207 Tmp3 = LegalizeOp(Node->getOperand(3)); 2208 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2209 Tmp3); 2210 } else { 2211 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2212 } 2213 2214 // Since this produces two values, make sure to remember that we legalized 2215 // both of them. 2216 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 2217 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 2218 return Result; 2219 } 2220 break; 2221 2222 case ISD::RET: 2223 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2224 2225 // Ensure that libcalls are emitted before a return. 2226 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2227 Tmp1 = LegalizeOp(Tmp1); 2228 LastCALLSEQ_END = DAG.getEntryNode(); 2229 2230 switch (Node->getNumOperands()) { 2231 case 3: // ret val 2232 Tmp2 = Node->getOperand(1); 2233 Tmp3 = Node->getOperand(2); // Signness 2234 switch (getTypeAction(Tmp2.getValueType())) { 2235 case Legal: 2236 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2237 break; 2238 case Expand: 2239 if (!Tmp2.getValueType().isVector()) { 2240 SDValue Lo, Hi; 2241 ExpandOp(Tmp2, Lo, Hi); 2242 2243 // Big endian systems want the hi reg first. 2244 if (TLI.isBigEndian()) 2245 std::swap(Lo, Hi); 2246 2247 if (Hi.getNode()) 2248 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2249 else 2250 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2251 Result = LegalizeOp(Result); 2252 } else { 2253 SDNode *InVal = Tmp2.getNode(); 2254 int InIx = Tmp2.getResNo(); 2255 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 2256 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 2257 2258 // Figure out if there is a simple type corresponding to this Vector 2259 // type. If so, convert to the vector type. 2260 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2261 if (TLI.isTypeLegal(TVT)) { 2262 // Turn this into a return of the vector type. 2263 Tmp2 = LegalizeOp(Tmp2); 2264 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2265 } else if (NumElems == 1) { 2266 // Turn this into a return of the scalar type. 2267 Tmp2 = ScalarizeVectorOp(Tmp2); 2268 Tmp2 = LegalizeOp(Tmp2); 2269 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2270 2271 // FIXME: Returns of gcc generic vectors smaller than a legal type 2272 // should be returned in integer registers! 2273 2274 // The scalarized value type may not be legal, e.g. it might require 2275 // promotion or expansion. Relegalize the return. 2276 Result = LegalizeOp(Result); 2277 } else { 2278 // FIXME: Returns of gcc generic vectors larger than a legal vector 2279 // type should be returned by reference! 2280 SDValue Lo, Hi; 2281 SplitVectorOp(Tmp2, Lo, Hi); 2282 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2283 Result = LegalizeOp(Result); 2284 } 2285 } 2286 break; 2287 case Promote: 2288 Tmp2 = PromoteOp(Node->getOperand(1)); 2289 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2290 Result = LegalizeOp(Result); 2291 break; 2292 } 2293 break; 2294 case 1: // ret void 2295 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2296 break; 2297 default: { // ret <values> 2298 SmallVector<SDValue, 8> NewValues; 2299 NewValues.push_back(Tmp1); 2300 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2301 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2302 case Legal: 2303 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2304 NewValues.push_back(Node->getOperand(i+1)); 2305 break; 2306 case Expand: { 2307 SDValue Lo, Hi; 2308 assert(!Node->getOperand(i).getValueType().isExtended() && 2309 "FIXME: TODO: implement returning non-legal vector types!"); 2310 ExpandOp(Node->getOperand(i), Lo, Hi); 2311 NewValues.push_back(Lo); 2312 NewValues.push_back(Node->getOperand(i+1)); 2313 if (Hi.getNode()) { 2314 NewValues.push_back(Hi); 2315 NewValues.push_back(Node->getOperand(i+1)); 2316 } 2317 break; 2318 } 2319 case Promote: 2320 assert(0 && "Can't promote multiple return value yet!"); 2321 } 2322 2323 if (NewValues.size() == Node->getNumOperands()) 2324 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2325 else 2326 Result = DAG.getNode(ISD::RET, MVT::Other, 2327 &NewValues[0], NewValues.size()); 2328 break; 2329 } 2330 } 2331 2332 if (Result.getOpcode() == ISD::RET) { 2333 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2334 default: assert(0 && "This action is not supported yet!"); 2335 case TargetLowering::Legal: break; 2336 case TargetLowering::Custom: 2337 Tmp1 = TLI.LowerOperation(Result, DAG); 2338 if (Tmp1.getNode()) Result = Tmp1; 2339 break; 2340 } 2341 } 2342 break; 2343 case ISD::STORE: { 2344 StoreSDNode *ST = cast<StoreSDNode>(Node); 2345 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2346 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2347 int SVOffset = ST->getSrcValueOffset(); 2348 unsigned Alignment = ST->getAlignment(); 2349 bool isVolatile = ST->isVolatile(); 2350 2351 if (!ST->isTruncatingStore()) { 2352 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2353 // FIXME: We shouldn't do this for TargetConstantFP's. 2354 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2355 // to phase ordering between legalized code and the dag combiner. This 2356 // probably means that we need to integrate dag combiner and legalizer 2357 // together. 2358 // We generally can't do this one for long doubles. 2359 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2360 if (CFP->getValueType(0) == MVT::f32 && 2361 getTypeAction(MVT::i32) == Legal) { 2362 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2363 convertToAPInt().zextOrTrunc(32), 2364 MVT::i32); 2365 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2366 SVOffset, isVolatile, Alignment); 2367 break; 2368 } else if (CFP->getValueType(0) == MVT::f64) { 2369 // If this target supports 64-bit registers, do a single 64-bit store. 2370 if (getTypeAction(MVT::i64) == Legal) { 2371 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 2372 zextOrTrunc(64), MVT::i64); 2373 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2374 SVOffset, isVolatile, Alignment); 2375 break; 2376 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 2377 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2378 // stores. If the target supports neither 32- nor 64-bits, this 2379 // xform is certainly not worth it. 2380 const APInt &IntVal =CFP->getValueAPF().convertToAPInt(); 2381 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2382 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2383 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2384 2385 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2386 SVOffset, isVolatile, Alignment); 2387 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2388 DAG.getIntPtrConstant(4)); 2389 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2390 isVolatile, MinAlign(Alignment, 4U)); 2391 2392 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2393 break; 2394 } 2395 } 2396 } 2397 2398 switch (getTypeAction(ST->getMemoryVT())) { 2399 case Legal: { 2400 Tmp3 = LegalizeOp(ST->getValue()); 2401 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2402 ST->getOffset()); 2403 2404 MVT VT = Tmp3.getValueType(); 2405 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2406 default: assert(0 && "This action is not supported yet!"); 2407 case TargetLowering::Legal: 2408 // If this is an unaligned store and the target doesn't support it, 2409 // expand it. 2410 if (!TLI.allowsUnalignedMemoryAccesses()) { 2411 unsigned ABIAlignment = TLI.getTargetData()-> 2412 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2413 if (ST->getAlignment() < ABIAlignment) 2414 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 2415 TLI); 2416 } 2417 break; 2418 case TargetLowering::Custom: 2419 Tmp1 = TLI.LowerOperation(Result, DAG); 2420 if (Tmp1.getNode()) Result = Tmp1; 2421 break; 2422 case TargetLowering::Promote: 2423 assert(VT.isVector() && "Unknown legal promote case!"); 2424 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2425 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2426 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2427 ST->getSrcValue(), SVOffset, isVolatile, 2428 Alignment); 2429 break; 2430 } 2431 break; 2432 } 2433 case Promote: 2434 // Truncate the value and store the result. 2435 Tmp3 = PromoteOp(ST->getValue()); 2436 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2437 SVOffset, ST->getMemoryVT(), 2438 isVolatile, Alignment); 2439 break; 2440 2441 case Expand: 2442 unsigned IncrementSize = 0; 2443 SDValue Lo, Hi; 2444 2445 // If this is a vector type, then we have to calculate the increment as 2446 // the product of the element size in bytes, and the number of elements 2447 // in the high half of the vector. 2448 if (ST->getValue().getValueType().isVector()) { 2449 SDNode *InVal = ST->getValue().getNode(); 2450 int InIx = ST->getValue().getResNo(); 2451 MVT InVT = InVal->getValueType(InIx); 2452 unsigned NumElems = InVT.getVectorNumElements(); 2453 MVT EVT = InVT.getVectorElementType(); 2454 2455 // Figure out if there is a simple type corresponding to this Vector 2456 // type. If so, convert to the vector type. 2457 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2458 if (TLI.isTypeLegal(TVT)) { 2459 // Turn this into a normal store of the vector type. 2460 Tmp3 = LegalizeOp(ST->getValue()); 2461 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2462 SVOffset, isVolatile, Alignment); 2463 Result = LegalizeOp(Result); 2464 break; 2465 } else if (NumElems == 1) { 2466 // Turn this into a normal store of the scalar type. 2467 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2468 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2469 SVOffset, isVolatile, Alignment); 2470 // The scalarized value type may not be legal, e.g. it might require 2471 // promotion or expansion. Relegalize the scalar store. 2472 Result = LegalizeOp(Result); 2473 break; 2474 } else { 2475 SplitVectorOp(ST->getValue(), Lo, Hi); 2476 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() * 2477 EVT.getSizeInBits()/8; 2478 } 2479 } else { 2480 ExpandOp(ST->getValue(), Lo, Hi); 2481 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0; 2482 2483 if (TLI.isBigEndian()) 2484 std::swap(Lo, Hi); 2485 } 2486 2487 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2488 SVOffset, isVolatile, Alignment); 2489 2490 if (Hi.getNode() == NULL) { 2491 // Must be int <-> float one-to-one expansion. 2492 Result = Lo; 2493 break; 2494 } 2495 2496 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2497 DAG.getIntPtrConstant(IncrementSize)); 2498 assert(isTypeLegal(Tmp2.getValueType()) && 2499 "Pointers must be legal!"); 2500 SVOffset += IncrementSize; 2501 Alignment = MinAlign(Alignment, IncrementSize); 2502 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2503 SVOffset, isVolatile, Alignment); 2504 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2505 break; 2506 } 2507 } else { 2508 switch (getTypeAction(ST->getValue().getValueType())) { 2509 case Legal: 2510 Tmp3 = LegalizeOp(ST->getValue()); 2511 break; 2512 case Promote: 2513 // We can promote the value, the truncstore will still take care of it. 2514 Tmp3 = PromoteOp(ST->getValue()); 2515 break; 2516 case Expand: 2517 // Just store the low part. This may become a non-trunc store, so make 2518 // sure to use getTruncStore, not UpdateNodeOperands below. 2519 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2520 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2521 SVOffset, MVT::i8, isVolatile, Alignment); 2522 } 2523 2524 MVT StVT = ST->getMemoryVT(); 2525 unsigned StWidth = StVT.getSizeInBits(); 2526 2527 if (StWidth != StVT.getStoreSizeInBits()) { 2528 // Promote to a byte-sized store with upper bits zero if not 2529 // storing an integral number of bytes. For example, promote 2530 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2531 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 2532 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2533 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2534 SVOffset, NVT, isVolatile, Alignment); 2535 } else if (StWidth & (StWidth - 1)) { 2536 // If not storing a power-of-2 number of bits, expand as two stores. 2537 assert(StVT.isExtended() && !StVT.isVector() && 2538 "Unsupported truncstore!"); 2539 unsigned RoundWidth = 1 << Log2_32(StWidth); 2540 assert(RoundWidth < StWidth); 2541 unsigned ExtraWidth = StWidth - RoundWidth; 2542 assert(ExtraWidth < RoundWidth); 2543 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2544 "Store size not an integral number of bytes!"); 2545 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2546 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2547 SDValue Lo, Hi; 2548 unsigned IncrementSize; 2549 2550 if (TLI.isLittleEndian()) { 2551 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2552 // Store the bottom RoundWidth bits. 2553 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2554 SVOffset, RoundVT, 2555 isVolatile, Alignment); 2556 2557 // Store the remaining ExtraWidth bits. 2558 IncrementSize = RoundWidth / 8; 2559 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2560 DAG.getIntPtrConstant(IncrementSize)); 2561 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2562 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2563 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2564 SVOffset + IncrementSize, ExtraVT, isVolatile, 2565 MinAlign(Alignment, IncrementSize)); 2566 } else { 2567 // Big endian - avoid unaligned stores. 2568 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2569 // Store the top RoundWidth bits. 2570 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2571 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2572 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2573 RoundVT, isVolatile, Alignment); 2574 2575 // Store the remaining ExtraWidth bits. 2576 IncrementSize = RoundWidth / 8; 2577 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2578 DAG.getIntPtrConstant(IncrementSize)); 2579 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2580 SVOffset + IncrementSize, ExtraVT, isVolatile, 2581 MinAlign(Alignment, IncrementSize)); 2582 } 2583 2584 // The order of the stores doesn't matter. 2585 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2586 } else { 2587 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2588 Tmp2 != ST->getBasePtr()) 2589 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2590 ST->getOffset()); 2591 2592 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2593 default: assert(0 && "This action is not supported yet!"); 2594 case TargetLowering::Legal: 2595 // If this is an unaligned store and the target doesn't support it, 2596 // expand it. 2597 if (!TLI.allowsUnalignedMemoryAccesses()) { 2598 unsigned ABIAlignment = TLI.getTargetData()-> 2599 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2600 if (ST->getAlignment() < ABIAlignment) 2601 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 2602 TLI); 2603 } 2604 break; 2605 case TargetLowering::Custom: 2606 Result = TLI.LowerOperation(Result, DAG); 2607 break; 2608 case Expand: 2609 // TRUNCSTORE:i16 i32 -> STORE i16 2610 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2611 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2612 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2613 isVolatile, Alignment); 2614 break; 2615 } 2616 } 2617 } 2618 break; 2619 } 2620 case ISD::PCMARKER: 2621 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2622 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2623 break; 2624 case ISD::STACKSAVE: 2625 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2626 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2627 Tmp1 = Result.getValue(0); 2628 Tmp2 = Result.getValue(1); 2629 2630 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2631 default: assert(0 && "This action is not supported yet!"); 2632 case TargetLowering::Legal: break; 2633 case TargetLowering::Custom: 2634 Tmp3 = TLI.LowerOperation(Result, DAG); 2635 if (Tmp3.getNode()) { 2636 Tmp1 = LegalizeOp(Tmp3); 2637 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2638 } 2639 break; 2640 case TargetLowering::Expand: 2641 // Expand to CopyFromReg if the target set 2642 // StackPointerRegisterToSaveRestore. 2643 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2644 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2645 Node->getValueType(0)); 2646 Tmp2 = Tmp1.getValue(1); 2647 } else { 2648 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2649 Tmp2 = Node->getOperand(0); 2650 } 2651 break; 2652 } 2653 2654 // Since stacksave produce two values, make sure to remember that we 2655 // legalized both of them. 2656 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2657 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2658 return Op.getResNo() ? Tmp2 : Tmp1; 2659 2660 case ISD::STACKRESTORE: 2661 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2662 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2663 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2664 2665 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2666 default: assert(0 && "This action is not supported yet!"); 2667 case TargetLowering::Legal: break; 2668 case TargetLowering::Custom: 2669 Tmp1 = TLI.LowerOperation(Result, DAG); 2670 if (Tmp1.getNode()) Result = Tmp1; 2671 break; 2672 case TargetLowering::Expand: 2673 // Expand to CopyToReg if the target set 2674 // StackPointerRegisterToSaveRestore. 2675 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2676 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2677 } else { 2678 Result = Tmp1; 2679 } 2680 break; 2681 } 2682 break; 2683 2684 case ISD::READCYCLECOUNTER: 2685 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2686 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2687 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2688 Node->getValueType(0))) { 2689 default: assert(0 && "This action is not supported yet!"); 2690 case TargetLowering::Legal: 2691 Tmp1 = Result.getValue(0); 2692 Tmp2 = Result.getValue(1); 2693 break; 2694 case TargetLowering::Custom: 2695 Result = TLI.LowerOperation(Result, DAG); 2696 Tmp1 = LegalizeOp(Result.getValue(0)); 2697 Tmp2 = LegalizeOp(Result.getValue(1)); 2698 break; 2699 } 2700 2701 // Since rdcc produce two values, make sure to remember that we legalized 2702 // both of them. 2703 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2704 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2705 return Result; 2706 2707 case ISD::SELECT: 2708 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2709 case Expand: assert(0 && "It's impossible to expand bools"); 2710 case Legal: 2711 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2712 break; 2713 case Promote: { 2714 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2715 // Make sure the condition is either zero or one. 2716 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2717 if (!DAG.MaskedValueIsZero(Tmp1, 2718 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2719 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2720 break; 2721 } 2722 } 2723 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2724 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2725 2726 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2727 2728 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2729 default: assert(0 && "This action is not supported yet!"); 2730 case TargetLowering::Legal: break; 2731 case TargetLowering::Custom: { 2732 Tmp1 = TLI.LowerOperation(Result, DAG); 2733 if (Tmp1.getNode()) Result = Tmp1; 2734 break; 2735 } 2736 case TargetLowering::Expand: 2737 if (Tmp1.getOpcode() == ISD::SETCC) { 2738 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2739 Tmp2, Tmp3, 2740 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2741 } else { 2742 Result = DAG.getSelectCC(Tmp1, 2743 DAG.getConstant(0, Tmp1.getValueType()), 2744 Tmp2, Tmp3, ISD::SETNE); 2745 } 2746 break; 2747 case TargetLowering::Promote: { 2748 MVT NVT = 2749 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2750 unsigned ExtOp, TruncOp; 2751 if (Tmp2.getValueType().isVector()) { 2752 ExtOp = ISD::BIT_CONVERT; 2753 TruncOp = ISD::BIT_CONVERT; 2754 } else if (Tmp2.getValueType().isInteger()) { 2755 ExtOp = ISD::ANY_EXTEND; 2756 TruncOp = ISD::TRUNCATE; 2757 } else { 2758 ExtOp = ISD::FP_EXTEND; 2759 TruncOp = ISD::FP_ROUND; 2760 } 2761 // Promote each of the values to the new type. 2762 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 2763 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 2764 // Perform the larger operation, then round down. 2765 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 2766 if (TruncOp != ISD::FP_ROUND) 2767 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 2768 else 2769 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 2770 DAG.getIntPtrConstant(0)); 2771 break; 2772 } 2773 } 2774 break; 2775 case ISD::SELECT_CC: { 2776 Tmp1 = Node->getOperand(0); // LHS 2777 Tmp2 = Node->getOperand(1); // RHS 2778 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 2779 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 2780 SDValue CC = Node->getOperand(4); 2781 2782 LegalizeSetCCOperands(Tmp1, Tmp2, CC); 2783 2784 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands, 2785 // the LHS is a legal SETCC itself. In this case, we need to compare 2786 // the result against zero to select between true and false values. 2787 if (Tmp2.getNode() == 0) { 2788 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 2789 CC = DAG.getCondCode(ISD::SETNE); 2790 } 2791 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 2792 2793 // Everything is legal, see if we should expand this op or something. 2794 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 2795 default: assert(0 && "This action is not supported yet!"); 2796 case TargetLowering::Legal: break; 2797 case TargetLowering::Custom: 2798 Tmp1 = TLI.LowerOperation(Result, DAG); 2799 if (Tmp1.getNode()) Result = Tmp1; 2800 break; 2801 } 2802 break; 2803 } 2804 case ISD::SETCC: 2805 Tmp1 = Node->getOperand(0); 2806 Tmp2 = Node->getOperand(1); 2807 Tmp3 = Node->getOperand(2); 2808 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3); 2809 2810 // If we had to Expand the SetCC operands into a SELECT node, then it may 2811 // not always be possible to return a true LHS & RHS. In this case, just 2812 // return the value we legalized, returned in the LHS 2813 if (Tmp2.getNode() == 0) { 2814 Result = Tmp1; 2815 break; 2816 } 2817 2818 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 2819 default: assert(0 && "Cannot handle this action for SETCC yet!"); 2820 case TargetLowering::Custom: 2821 isCustom = true; 2822 // FALLTHROUGH. 2823 case TargetLowering::Legal: 2824 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2825 if (isCustom) { 2826 Tmp4 = TLI.LowerOperation(Result, DAG); 2827 if (Tmp4.getNode()) Result = Tmp4; 2828 } 2829 break; 2830 case TargetLowering::Promote: { 2831 // First step, figure out the appropriate operation to use. 2832 // Allow SETCC to not be supported for all legal data types 2833 // Mostly this targets FP 2834 MVT NewInTy = Node->getOperand(0).getValueType(); 2835 MVT OldVT = NewInTy; OldVT = OldVT; 2836 2837 // Scan for the appropriate larger type to use. 2838 while (1) { 2839 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 2840 2841 assert(NewInTy.isInteger() == OldVT.isInteger() && 2842 "Fell off of the edge of the integer world"); 2843 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 2844 "Fell off of the edge of the floating point world"); 2845 2846 // If the target supports SETCC of this type, use it. 2847 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 2848 break; 2849 } 2850 if (NewInTy.isInteger()) 2851 assert(0 && "Cannot promote Legal Integer SETCC yet"); 2852 else { 2853 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 2854 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 2855 } 2856 Tmp1 = LegalizeOp(Tmp1); 2857 Tmp2 = LegalizeOp(Tmp2); 2858 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2859 Result = LegalizeOp(Result); 2860 break; 2861 } 2862 case TargetLowering::Expand: 2863 // Expand a setcc node into a select_cc of the same condition, lhs, and 2864 // rhs that selects between const 1 (true) and const 0 (false). 2865 MVT VT = Node->getValueType(0); 2866 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 2867 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2868 Tmp3); 2869 break; 2870 } 2871 break; 2872 case ISD::VSETCC: { 2873 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2874 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 2875 SDValue CC = Node->getOperand(2); 2876 2877 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC); 2878 2879 // Everything is legal, see if we should expand this op or something. 2880 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) { 2881 default: assert(0 && "This action is not supported yet!"); 2882 case TargetLowering::Legal: break; 2883 case TargetLowering::Custom: 2884 Tmp1 = TLI.LowerOperation(Result, DAG); 2885 if (Tmp1.getNode()) Result = Tmp1; 2886 break; 2887 } 2888 break; 2889 } 2890 2891 case ISD::SHL_PARTS: 2892 case ISD::SRA_PARTS: 2893 case ISD::SRL_PARTS: { 2894 SmallVector<SDValue, 8> Ops; 2895 bool Changed = false; 2896 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2897 Ops.push_back(LegalizeOp(Node->getOperand(i))); 2898 Changed |= Ops.back() != Node->getOperand(i); 2899 } 2900 if (Changed) 2901 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 2902 2903 switch (TLI.getOperationAction(Node->getOpcode(), 2904 Node->getValueType(0))) { 2905 default: assert(0 && "This action is not supported yet!"); 2906 case TargetLowering::Legal: break; 2907 case TargetLowering::Custom: 2908 Tmp1 = TLI.LowerOperation(Result, DAG); 2909 if (Tmp1.getNode()) { 2910 SDValue Tmp2, RetVal(0, 0); 2911 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 2912 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 2913 AddLegalizedOperand(SDValue(Node, i), Tmp2); 2914 if (i == Op.getResNo()) 2915 RetVal = Tmp2; 2916 } 2917 assert(RetVal.getNode() && "Illegal result number"); 2918 return RetVal; 2919 } 2920 break; 2921 } 2922 2923 // Since these produce multiple values, make sure to remember that we 2924 // legalized all of them. 2925 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 2926 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i)); 2927 return Result.getValue(Op.getResNo()); 2928 } 2929 2930 // Binary operators 2931 case ISD::ADD: 2932 case ISD::SUB: 2933 case ISD::MUL: 2934 case ISD::MULHS: 2935 case ISD::MULHU: 2936 case ISD::UDIV: 2937 case ISD::SDIV: 2938 case ISD::AND: 2939 case ISD::OR: 2940 case ISD::XOR: 2941 case ISD::SHL: 2942 case ISD::SRL: 2943 case ISD::SRA: 2944 case ISD::FADD: 2945 case ISD::FSUB: 2946 case ISD::FMUL: 2947 case ISD::FDIV: 2948 case ISD::FPOW: 2949 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 2950 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2951 case Expand: assert(0 && "Not possible"); 2952 case Legal: 2953 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 2954 break; 2955 case Promote: 2956 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 2957 break; 2958 } 2959 2960 if ((Node->getOpcode() == ISD::SHL || 2961 Node->getOpcode() == ISD::SRL || 2962 Node->getOpcode() == ISD::SRA) && 2963 !Node->getValueType(0).isVector()) { 2964 if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType())) 2965 Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2); 2966 else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType())) 2967 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2); 2968 } 2969 2970 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2971 2972 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 2973 default: assert(0 && "BinOp legalize operation not supported"); 2974 case TargetLowering::Legal: break; 2975 case TargetLowering::Custom: 2976 Tmp1 = TLI.LowerOperation(Result, DAG); 2977 if (Tmp1.getNode()) { 2978 Result = Tmp1; 2979 break; 2980 } 2981 // Fall through if the custom lower can't deal with the operation 2982 case TargetLowering::Expand: { 2983 MVT VT = Op.getValueType(); 2984 2985 // See if multiply or divide can be lowered using two-result operations. 2986 SDVTList VTs = DAG.getVTList(VT, VT); 2987 if (Node->getOpcode() == ISD::MUL) { 2988 // We just need the low half of the multiply; try both the signed 2989 // and unsigned forms. If the target supports both SMUL_LOHI and 2990 // UMUL_LOHI, form a preference by checking which forms of plain 2991 // MULH it supports. 2992 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 2993 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 2994 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 2995 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 2996 unsigned OpToUse = 0; 2997 if (HasSMUL_LOHI && !HasMULHS) { 2998 OpToUse = ISD::SMUL_LOHI; 2999 } else if (HasUMUL_LOHI && !HasMULHU) { 3000 OpToUse = ISD::UMUL_LOHI; 3001 } else if (HasSMUL_LOHI) { 3002 OpToUse = ISD::SMUL_LOHI; 3003 } else if (HasUMUL_LOHI) { 3004 OpToUse = ISD::UMUL_LOHI; 3005 } 3006 if (OpToUse) { 3007 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0); 3008 break; 3009 } 3010 } 3011 if (Node->getOpcode() == ISD::MULHS && 3012 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 3013 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 1); 3014 break; 3015 } 3016 if (Node->getOpcode() == ISD::MULHU && 3017 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 3018 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 1); 3019 break; 3020 } 3021 if (Node->getOpcode() == ISD::SDIV && 3022 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3023 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 0); 3024 break; 3025 } 3026 if (Node->getOpcode() == ISD::UDIV && 3027 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3028 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 0); 3029 break; 3030 } 3031 3032 // Check to see if we have a libcall for this operator. 3033 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3034 bool isSigned = false; 3035 switch (Node->getOpcode()) { 3036 case ISD::UDIV: 3037 case ISD::SDIV: 3038 if (VT == MVT::i32) { 3039 LC = Node->getOpcode() == ISD::UDIV 3040 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3041 isSigned = Node->getOpcode() == ISD::SDIV; 3042 } 3043 break; 3044 case ISD::FPOW: 3045 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3046 RTLIB::POW_PPCF128); 3047 break; 3048 default: break; 3049 } 3050 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3051 SDValue Dummy; 3052 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3053 break; 3054 } 3055 3056 assert(Node->getValueType(0).isVector() && 3057 "Cannot expand this binary operator!"); 3058 // Expand the operation into a bunch of nasty scalar code. 3059 Result = LegalizeOp(UnrollVectorOp(Op)); 3060 break; 3061 } 3062 case TargetLowering::Promote: { 3063 switch (Node->getOpcode()) { 3064 default: assert(0 && "Do not know how to promote this BinOp!"); 3065 case ISD::AND: 3066 case ISD::OR: 3067 case ISD::XOR: { 3068 MVT OVT = Node->getValueType(0); 3069 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3070 assert(OVT.isVector() && "Cannot promote this BinOp!"); 3071 // Bit convert each of the values to the new type. 3072 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3073 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3074 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3075 // Bit convert the result back the original type. 3076 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3077 break; 3078 } 3079 } 3080 } 3081 } 3082 break; 3083 3084 case ISD::SMUL_LOHI: 3085 case ISD::UMUL_LOHI: 3086 case ISD::SDIVREM: 3087 case ISD::UDIVREM: 3088 // These nodes will only be produced by target-specific lowering, so 3089 // they shouldn't be here if they aren't legal. 3090 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3091 "This must be legal!"); 3092 3093 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3094 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3095 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3096 break; 3097 3098 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3099 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3100 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3101 case Expand: assert(0 && "Not possible"); 3102 case Legal: 3103 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3104 break; 3105 case Promote: 3106 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3107 break; 3108 } 3109 3110 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3111 3112 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3113 default: assert(0 && "Operation not supported"); 3114 case TargetLowering::Custom: 3115 Tmp1 = TLI.LowerOperation(Result, DAG); 3116 if (Tmp1.getNode()) Result = Tmp1; 3117 break; 3118 case TargetLowering::Legal: break; 3119 case TargetLowering::Expand: { 3120 // If this target supports fabs/fneg natively and select is cheap, 3121 // do this efficiently. 3122 if (!TLI.isSelectExpensive() && 3123 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3124 TargetLowering::Legal && 3125 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3126 TargetLowering::Legal) { 3127 // Get the sign bit of the RHS. 3128 MVT IVT = 3129 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3130 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3131 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), 3132 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3133 // Get the absolute value of the result. 3134 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3135 // Select between the nabs and abs value based on the sign bit of 3136 // the input. 3137 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3138 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3139 AbsVal), 3140 AbsVal); 3141 Result = LegalizeOp(Result); 3142 break; 3143 } 3144 3145 // Otherwise, do bitwise ops! 3146 MVT NVT = 3147 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3148 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3149 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3150 Result = LegalizeOp(Result); 3151 break; 3152 } 3153 } 3154 break; 3155 3156 case ISD::ADDC: 3157 case ISD::SUBC: 3158 Tmp1 = LegalizeOp(Node->getOperand(0)); 3159 Tmp2 = LegalizeOp(Node->getOperand(1)); 3160 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3161 // Since this produces two values, make sure to remember that we legalized 3162 // both of them. 3163 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 3164 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 3165 return Result; 3166 3167 case ISD::ADDE: 3168 case ISD::SUBE: 3169 Tmp1 = LegalizeOp(Node->getOperand(0)); 3170 Tmp2 = LegalizeOp(Node->getOperand(1)); 3171 Tmp3 = LegalizeOp(Node->getOperand(2)); 3172 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3173 // Since this produces two values, make sure to remember that we legalized 3174 // both of them. 3175 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 3176 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 3177 return Result; 3178 3179 case ISD::BUILD_PAIR: { 3180 MVT PairTy = Node->getValueType(0); 3181 // TODO: handle the case where the Lo and Hi operands are not of legal type 3182 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3183 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3184 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3185 case TargetLowering::Promote: 3186 case TargetLowering::Custom: 3187 assert(0 && "Cannot promote/custom this yet!"); 3188 case TargetLowering::Legal: 3189 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3190 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3191 break; 3192 case TargetLowering::Expand: 3193 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3194 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3195 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3196 DAG.getConstant(PairTy.getSizeInBits()/2, 3197 TLI.getShiftAmountTy())); 3198 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3199 break; 3200 } 3201 break; 3202 } 3203 3204 case ISD::UREM: 3205 case ISD::SREM: 3206 case ISD::FREM: 3207 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3208 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3209 3210 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3211 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3212 case TargetLowering::Custom: 3213 isCustom = true; 3214 // FALLTHROUGH 3215 case TargetLowering::Legal: 3216 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3217 if (isCustom) { 3218 Tmp1 = TLI.LowerOperation(Result, DAG); 3219 if (Tmp1.getNode()) Result = Tmp1; 3220 } 3221 break; 3222 case TargetLowering::Expand: { 3223 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3224 bool isSigned = DivOpc == ISD::SDIV; 3225 MVT VT = Node->getValueType(0); 3226 3227 // See if remainder can be lowered using two-result operations. 3228 SDVTList VTs = DAG.getVTList(VT, VT); 3229 if (Node->getOpcode() == ISD::SREM && 3230 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3231 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1); 3232 break; 3233 } 3234 if (Node->getOpcode() == ISD::UREM && 3235 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3236 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1); 3237 break; 3238 } 3239 3240 if (VT.isInteger()) { 3241 if (TLI.getOperationAction(DivOpc, VT) == 3242 TargetLowering::Legal) { 3243 // X % Y -> X-X/Y*Y 3244 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3245 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3246 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3247 } else if (VT.isVector()) { 3248 Result = LegalizeOp(UnrollVectorOp(Op)); 3249 } else { 3250 assert(VT == MVT::i32 && 3251 "Cannot expand this binary operator!"); 3252 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3253 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3254 SDValue Dummy; 3255 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3256 } 3257 } else { 3258 assert(VT.isFloatingPoint() && 3259 "remainder op must have integer or floating-point type"); 3260 if (VT.isVector()) { 3261 Result = LegalizeOp(UnrollVectorOp(Op)); 3262 } else { 3263 // Floating point mod -> fmod libcall. 3264 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3265 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3266 SDValue Dummy; 3267 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3268 } 3269 } 3270 break; 3271 } 3272 } 3273 break; 3274 case ISD::VAARG: { 3275 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3276 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3277 3278 MVT VT = Node->getValueType(0); 3279 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3280 default: assert(0 && "This action is not supported yet!"); 3281 case TargetLowering::Custom: 3282 isCustom = true; 3283 // FALLTHROUGH 3284 case TargetLowering::Legal: 3285 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3286 Result = Result.getValue(0); 3287 Tmp1 = Result.getValue(1); 3288 3289 if (isCustom) { 3290 Tmp2 = TLI.LowerOperation(Result, DAG); 3291 if (Tmp2.getNode()) { 3292 Result = LegalizeOp(Tmp2); 3293 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3294 } 3295 } 3296 break; 3297 case TargetLowering::Expand: { 3298 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3299 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3300 // Increment the pointer, VAList, to the next vaarg 3301 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3302 DAG.getConstant(VT.getSizeInBits()/8, 3303 TLI.getPointerTy())); 3304 // Store the incremented VAList to the legalized pointer 3305 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3306 // Load the actual argument out of the pointer VAList 3307 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3308 Tmp1 = LegalizeOp(Result.getValue(1)); 3309 Result = LegalizeOp(Result); 3310 break; 3311 } 3312 } 3313 // Since VAARG produces two values, make sure to remember that we 3314 // legalized both of them. 3315 AddLegalizedOperand(SDValue(Node, 0), Result); 3316 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 3317 return Op.getResNo() ? Tmp1 : Result; 3318 } 3319 3320 case ISD::VACOPY: 3321 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3322 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3323 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3324 3325 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3326 default: assert(0 && "This action is not supported yet!"); 3327 case TargetLowering::Custom: 3328 isCustom = true; 3329 // FALLTHROUGH 3330 case TargetLowering::Legal: 3331 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3332 Node->getOperand(3), Node->getOperand(4)); 3333 if (isCustom) { 3334 Tmp1 = TLI.LowerOperation(Result, DAG); 3335 if (Tmp1.getNode()) Result = Tmp1; 3336 } 3337 break; 3338 case TargetLowering::Expand: 3339 // This defaults to loading a pointer from the input and storing it to the 3340 // output, returning the chain. 3341 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3342 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3343 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0); 3344 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0); 3345 break; 3346 } 3347 break; 3348 3349 case ISD::VAEND: 3350 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3351 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3352 3353 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3354 default: assert(0 && "This action is not supported yet!"); 3355 case TargetLowering::Custom: 3356 isCustom = true; 3357 // FALLTHROUGH 3358 case TargetLowering::Legal: 3359 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3360 if (isCustom) { 3361 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3362 if (Tmp1.getNode()) Result = Tmp1; 3363 } 3364 break; 3365 case TargetLowering::Expand: 3366 Result = Tmp1; // Default to a no-op, return the chain 3367 break; 3368 } 3369 break; 3370 3371 case ISD::VASTART: 3372 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3373 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3374 3375 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3376 3377 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3378 default: assert(0 && "This action is not supported yet!"); 3379 case TargetLowering::Legal: break; 3380 case TargetLowering::Custom: 3381 Tmp1 = TLI.LowerOperation(Result, DAG); 3382 if (Tmp1.getNode()) Result = Tmp1; 3383 break; 3384 } 3385 break; 3386 3387 case ISD::ROTL: 3388 case ISD::ROTR: 3389 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3390 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3391 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3392 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3393 default: 3394 assert(0 && "ROTL/ROTR legalize operation not supported"); 3395 break; 3396 case TargetLowering::Legal: 3397 break; 3398 case TargetLowering::Custom: 3399 Tmp1 = TLI.LowerOperation(Result, DAG); 3400 if (Tmp1.getNode()) Result = Tmp1; 3401 break; 3402 case TargetLowering::Promote: 3403 assert(0 && "Do not know how to promote ROTL/ROTR"); 3404 break; 3405 case TargetLowering::Expand: 3406 assert(0 && "Do not know how to expand ROTL/ROTR"); 3407 break; 3408 } 3409 break; 3410 3411 case ISD::BSWAP: 3412 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3413 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3414 case TargetLowering::Custom: 3415 assert(0 && "Cannot custom legalize this yet!"); 3416 case TargetLowering::Legal: 3417 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3418 break; 3419 case TargetLowering::Promote: { 3420 MVT OVT = Tmp1.getValueType(); 3421 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3422 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3423 3424 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3425 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3426 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3427 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3428 break; 3429 } 3430 case TargetLowering::Expand: 3431 Result = ExpandBSWAP(Tmp1); 3432 break; 3433 } 3434 break; 3435 3436 case ISD::CTPOP: 3437 case ISD::CTTZ: 3438 case ISD::CTLZ: 3439 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3440 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3441 case TargetLowering::Custom: 3442 case TargetLowering::Legal: 3443 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3444 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3445 TargetLowering::Custom) { 3446 Tmp1 = TLI.LowerOperation(Result, DAG); 3447 if (Tmp1.getNode()) { 3448 Result = Tmp1; 3449 } 3450 } 3451 break; 3452 case TargetLowering::Promote: { 3453 MVT OVT = Tmp1.getValueType(); 3454 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3455 3456 // Zero extend the argument. 3457 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3458 // Perform the larger operation, then subtract if needed. 3459 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3460 switch (Node->getOpcode()) { 3461 case ISD::CTPOP: 3462 Result = Tmp1; 3463 break; 3464 case ISD::CTTZ: 3465 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3466 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 3467 DAG.getConstant(NVT.getSizeInBits(), NVT), 3468 ISD::SETEQ); 3469 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3470 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3471 break; 3472 case ISD::CTLZ: 3473 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3474 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3475 DAG.getConstant(NVT.getSizeInBits() - 3476 OVT.getSizeInBits(), NVT)); 3477 break; 3478 } 3479 break; 3480 } 3481 case TargetLowering::Expand: 3482 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3483 break; 3484 } 3485 break; 3486 3487 // Unary operators 3488 case ISD::FABS: 3489 case ISD::FNEG: 3490 case ISD::FSQRT: 3491 case ISD::FSIN: 3492 case ISD::FCOS: 3493 case ISD::FLOG: 3494 case ISD::FLOG2: 3495 case ISD::FLOG10: 3496 case ISD::FEXP: 3497 case ISD::FEXP2: 3498 case ISD::FTRUNC: 3499 case ISD::FFLOOR: 3500 case ISD::FCEIL: 3501 case ISD::FRINT: 3502 case ISD::FNEARBYINT: 3503 Tmp1 = LegalizeOp(Node->getOperand(0)); 3504 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3505 case TargetLowering::Promote: 3506 case TargetLowering::Custom: 3507 isCustom = true; 3508 // FALLTHROUGH 3509 case TargetLowering::Legal: 3510 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3511 if (isCustom) { 3512 Tmp1 = TLI.LowerOperation(Result, DAG); 3513 if (Tmp1.getNode()) Result = Tmp1; 3514 } 3515 break; 3516 case TargetLowering::Expand: 3517 switch (Node->getOpcode()) { 3518 default: assert(0 && "Unreachable!"); 3519 case ISD::FNEG: 3520 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3521 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3522 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3523 break; 3524 case ISD::FABS: { 3525 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3526 MVT VT = Node->getValueType(0); 3527 Tmp2 = DAG.getConstantFP(0.0, VT); 3528 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 3529 ISD::SETUGT); 3530 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3531 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3532 break; 3533 } 3534 case ISD::FSQRT: 3535 case ISD::FSIN: 3536 case ISD::FCOS: 3537 case ISD::FLOG: 3538 case ISD::FLOG2: 3539 case ISD::FLOG10: 3540 case ISD::FEXP: 3541 case ISD::FEXP2: 3542 case ISD::FTRUNC: 3543 case ISD::FFLOOR: 3544 case ISD::FCEIL: 3545 case ISD::FRINT: 3546 case ISD::FNEARBYINT: { 3547 MVT VT = Node->getValueType(0); 3548 3549 // Expand unsupported unary vector operators by unrolling them. 3550 if (VT.isVector()) { 3551 Result = LegalizeOp(UnrollVectorOp(Op)); 3552 break; 3553 } 3554 3555 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3556 switch(Node->getOpcode()) { 3557 case ISD::FSQRT: 3558 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3559 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3560 break; 3561 case ISD::FSIN: 3562 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3563 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3564 break; 3565 case ISD::FCOS: 3566 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3567 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3568 break; 3569 case ISD::FLOG: 3570 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64, 3571 RTLIB::LOG_F80, RTLIB::LOG_PPCF128); 3572 break; 3573 case ISD::FLOG2: 3574 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 3575 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128); 3576 break; 3577 case ISD::FLOG10: 3578 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 3579 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128); 3580 break; 3581 case ISD::FEXP: 3582 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64, 3583 RTLIB::EXP_F80, RTLIB::EXP_PPCF128); 3584 break; 3585 case ISD::FEXP2: 3586 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 3587 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128); 3588 break; 3589 case ISD::FTRUNC: 3590 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 3591 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 3592 break; 3593 case ISD::FFLOOR: 3594 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 3595 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 3596 break; 3597 case ISD::FCEIL: 3598 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 3599 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 3600 break; 3601 case ISD::FRINT: 3602 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 3603 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 3604 break; 3605 case ISD::FNEARBYINT: 3606 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 3607 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 3608 break; 3609 break; 3610 default: assert(0 && "Unreachable!"); 3611 } 3612 SDValue Dummy; 3613 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3614 break; 3615 } 3616 } 3617 break; 3618 } 3619 break; 3620 case ISD::FPOWI: { 3621 MVT VT = Node->getValueType(0); 3622 3623 // Expand unsupported unary vector operators by unrolling them. 3624 if (VT.isVector()) { 3625 Result = LegalizeOp(UnrollVectorOp(Op)); 3626 break; 3627 } 3628 3629 // We always lower FPOWI into a libcall. No target support for it yet. 3630 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3631 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3632 SDValue Dummy; 3633 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3634 break; 3635 } 3636 case ISD::BIT_CONVERT: 3637 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3638 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3639 Node->getValueType(0)); 3640 } else if (Op.getOperand(0).getValueType().isVector()) { 3641 // The input has to be a vector type, we have to either scalarize it, pack 3642 // it, or convert it based on whether the input vector type is legal. 3643 SDNode *InVal = Node->getOperand(0).getNode(); 3644 int InIx = Node->getOperand(0).getResNo(); 3645 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 3646 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 3647 3648 // Figure out if there is a simple type corresponding to this Vector 3649 // type. If so, convert to the vector type. 3650 MVT TVT = MVT::getVectorVT(EVT, NumElems); 3651 if (TLI.isTypeLegal(TVT)) { 3652 // Turn this into a bit convert of the vector input. 3653 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3654 LegalizeOp(Node->getOperand(0))); 3655 break; 3656 } else if (NumElems == 1) { 3657 // Turn this into a bit convert of the scalar input. 3658 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3659 ScalarizeVectorOp(Node->getOperand(0))); 3660 break; 3661 } else { 3662 // FIXME: UNIMP! Store then reload 3663 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3664 } 3665 } else { 3666 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3667 Node->getOperand(0).getValueType())) { 3668 default: assert(0 && "Unknown operation action!"); 3669 case TargetLowering::Expand: 3670 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3671 Node->getValueType(0)); 3672 break; 3673 case TargetLowering::Legal: 3674 Tmp1 = LegalizeOp(Node->getOperand(0)); 3675 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3676 break; 3677 } 3678 } 3679 break; 3680 3681 // Conversion operators. The source and destination have different types. 3682 case ISD::SINT_TO_FP: 3683 case ISD::UINT_TO_FP: { 3684 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 3685 Result = LegalizeINT_TO_FP(Result, isSigned, 3686 Node->getValueType(0), Node->getOperand(0)); 3687 break; 3688 } 3689 case ISD::TRUNCATE: 3690 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3691 case Legal: 3692 Tmp1 = LegalizeOp(Node->getOperand(0)); 3693 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3694 break; 3695 case Expand: 3696 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 3697 3698 // Since the result is legal, we should just be able to truncate the low 3699 // part of the source. 3700 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 3701 break; 3702 case Promote: 3703 Result = PromoteOp(Node->getOperand(0)); 3704 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 3705 break; 3706 } 3707 break; 3708 3709 case ISD::FP_TO_SINT: 3710 case ISD::FP_TO_UINT: 3711 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3712 case Legal: 3713 Tmp1 = LegalizeOp(Node->getOperand(0)); 3714 3715 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 3716 default: assert(0 && "Unknown operation action!"); 3717 case TargetLowering::Custom: 3718 isCustom = true; 3719 // FALLTHROUGH 3720 case TargetLowering::Legal: 3721 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3722 if (isCustom) { 3723 Tmp1 = TLI.LowerOperation(Result, DAG); 3724 if (Tmp1.getNode()) Result = Tmp1; 3725 } 3726 break; 3727 case TargetLowering::Promote: 3728 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 3729 Node->getOpcode() == ISD::FP_TO_SINT); 3730 break; 3731 case TargetLowering::Expand: 3732 if (Node->getOpcode() == ISD::FP_TO_UINT) { 3733 SDValue True, False; 3734 MVT VT = Node->getOperand(0).getValueType(); 3735 MVT NVT = Node->getValueType(0); 3736 const uint64_t zero[] = {0, 0}; 3737 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 3738 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 3739 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 3740 Tmp2 = DAG.getConstantFP(apf, VT); 3741 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), 3742 Node->getOperand(0), Tmp2, ISD::SETLT); 3743 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 3744 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 3745 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 3746 Tmp2)); 3747 False = DAG.getNode(ISD::XOR, NVT, False, 3748 DAG.getConstant(x, NVT)); 3749 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 3750 break; 3751 } else { 3752 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 3753 } 3754 break; 3755 } 3756 break; 3757 case Expand: { 3758 MVT VT = Op.getValueType(); 3759 MVT OVT = Node->getOperand(0).getValueType(); 3760 // Convert ppcf128 to i32 3761 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 3762 if (Node->getOpcode() == ISD::FP_TO_SINT) { 3763 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 3764 Node->getOperand(0), DAG.getValueType(MVT::f64)); 3765 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 3766 DAG.getIntPtrConstant(1)); 3767 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 3768 } else { 3769 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 3770 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 3771 Tmp2 = DAG.getConstantFP(apf, OVT); 3772 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 3773 // FIXME: generated code sucks. 3774 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 3775 DAG.getNode(ISD::ADD, MVT::i32, 3776 DAG.getNode(ISD::FP_TO_SINT, VT, 3777 DAG.getNode(ISD::FSUB, OVT, 3778 Node->getOperand(0), Tmp2)), 3779 DAG.getConstant(0x80000000, MVT::i32)), 3780 DAG.getNode(ISD::FP_TO_SINT, VT, 3781 Node->getOperand(0)), 3782 DAG.getCondCode(ISD::SETGE)); 3783 } 3784 break; 3785 } 3786 // Convert f32 / f64 to i32 / i64 / i128. 3787 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ? 3788 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT); 3789 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!"); 3790 SDValue Dummy; 3791 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3792 break; 3793 } 3794 case Promote: 3795 Tmp1 = PromoteOp(Node->getOperand(0)); 3796 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 3797 Result = LegalizeOp(Result); 3798 break; 3799 } 3800 break; 3801 3802 case ISD::FP_EXTEND: { 3803 MVT DstVT = Op.getValueType(); 3804 MVT SrcVT = Op.getOperand(0).getValueType(); 3805 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3806 // The only other way we can lower this is to turn it into a STORE, 3807 // LOAD pair, targetting a temporary location (a stack slot). 3808 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 3809 break; 3810 } 3811 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3812 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3813 case Legal: 3814 Tmp1 = LegalizeOp(Node->getOperand(0)); 3815 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3816 break; 3817 case Promote: 3818 Tmp1 = PromoteOp(Node->getOperand(0)); 3819 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 3820 break; 3821 } 3822 break; 3823 } 3824 case ISD::FP_ROUND: { 3825 MVT DstVT = Op.getValueType(); 3826 MVT SrcVT = Op.getOperand(0).getValueType(); 3827 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 3828 if (SrcVT == MVT::ppcf128) { 3829 SDValue Lo; 3830 ExpandOp(Node->getOperand(0), Lo, Result); 3831 // Round it the rest of the way (e.g. to f32) if needed. 3832 if (DstVT!=MVT::f64) 3833 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 3834 break; 3835 } 3836 // The only other way we can lower this is to turn it into a STORE, 3837 // LOAD pair, targetting a temporary location (a stack slot). 3838 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 3839 break; 3840 } 3841 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3842 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3843 case Legal: 3844 Tmp1 = LegalizeOp(Node->getOperand(0)); 3845 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3846 break; 3847 case Promote: 3848 Tmp1 = PromoteOp(Node->getOperand(0)); 3849 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 3850 Node->getOperand(1)); 3851 break; 3852 } 3853 break; 3854 } 3855 case ISD::ANY_EXTEND: 3856 case ISD::ZERO_EXTEND: 3857 case ISD::SIGN_EXTEND: 3858 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3859 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3860 case Legal: 3861 Tmp1 = LegalizeOp(Node->getOperand(0)); 3862 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3863 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3864 TargetLowering::Custom) { 3865 Tmp1 = TLI.LowerOperation(Result, DAG); 3866 if (Tmp1.getNode()) Result = Tmp1; 3867 } 3868 break; 3869 case Promote: 3870 switch (Node->getOpcode()) { 3871 case ISD::ANY_EXTEND: 3872 Tmp1 = PromoteOp(Node->getOperand(0)); 3873 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 3874 break; 3875 case ISD::ZERO_EXTEND: 3876 Result = PromoteOp(Node->getOperand(0)); 3877 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3878 Result = DAG.getZeroExtendInReg(Result, 3879 Node->getOperand(0).getValueType()); 3880 break; 3881 case ISD::SIGN_EXTEND: 3882 Result = PromoteOp(Node->getOperand(0)); 3883 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 3884 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 3885 Result, 3886 DAG.getValueType(Node->getOperand(0).getValueType())); 3887 break; 3888 } 3889 } 3890 break; 3891 case ISD::FP_ROUND_INREG: 3892 case ISD::SIGN_EXTEND_INREG: { 3893 Tmp1 = LegalizeOp(Node->getOperand(0)); 3894 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 3895 3896 // If this operation is not supported, convert it to a shl/shr or load/store 3897 // pair. 3898 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 3899 default: assert(0 && "This action not supported for this op yet!"); 3900 case TargetLowering::Legal: 3901 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 3902 break; 3903 case TargetLowering::Expand: 3904 // If this is an integer extend and shifts are supported, do that. 3905 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 3906 // NOTE: we could fall back on load/store here too for targets without 3907 // SAR. However, it is doubtful that any exist. 3908 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 3909 ExtraVT.getSizeInBits(); 3910 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 3911 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 3912 Node->getOperand(0), ShiftCst); 3913 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 3914 Result, ShiftCst); 3915 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 3916 // The only way we can lower this is to turn it into a TRUNCSTORE, 3917 // EXTLOAD pair, targetting a temporary location (a stack slot). 3918 3919 // NOTE: there is a choice here between constantly creating new stack 3920 // slots and always reusing the same one. We currently always create 3921 // new ones, as reuse may inhibit scheduling. 3922 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 3923 Node->getValueType(0)); 3924 } else { 3925 assert(0 && "Unknown op"); 3926 } 3927 break; 3928 } 3929 break; 3930 } 3931 case ISD::TRAMPOLINE: { 3932 SDValue Ops[6]; 3933 for (unsigned i = 0; i != 6; ++i) 3934 Ops[i] = LegalizeOp(Node->getOperand(i)); 3935 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 3936 // The only option for this node is to custom lower it. 3937 Result = TLI.LowerOperation(Result, DAG); 3938 assert(Result.getNode() && "Should always custom lower!"); 3939 3940 // Since trampoline produces two values, make sure to remember that we 3941 // legalized both of them. 3942 Tmp1 = LegalizeOp(Result.getValue(1)); 3943 Result = LegalizeOp(Result); 3944 AddLegalizedOperand(SDValue(Node, 0), Result); 3945 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 3946 return Op.getResNo() ? Tmp1 : Result; 3947 } 3948 case ISD::FLT_ROUNDS_: { 3949 MVT VT = Node->getValueType(0); 3950 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3951 default: assert(0 && "This action not supported for this op yet!"); 3952 case TargetLowering::Custom: 3953 Result = TLI.LowerOperation(Op, DAG); 3954 if (Result.getNode()) break; 3955 // Fall Thru 3956 case TargetLowering::Legal: 3957 // If this operation is not supported, lower it to constant 1 3958 Result = DAG.getConstant(1, VT); 3959 break; 3960 } 3961 break; 3962 } 3963 case ISD::TRAP: { 3964 MVT VT = Node->getValueType(0); 3965 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 3966 default: assert(0 && "This action not supported for this op yet!"); 3967 case TargetLowering::Legal: 3968 Tmp1 = LegalizeOp(Node->getOperand(0)); 3969 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3970 break; 3971 case TargetLowering::Custom: 3972 Result = TLI.LowerOperation(Op, DAG); 3973 if (Result.getNode()) break; 3974 // Fall Thru 3975 case TargetLowering::Expand: 3976 // If this operation is not supported, lower it to 'abort()' call 3977 Tmp1 = LegalizeOp(Node->getOperand(0)); 3978 TargetLowering::ArgListTy Args; 3979 std::pair<SDValue,SDValue> CallResult = 3980 TLI.LowerCallTo(Tmp1, Type::VoidTy, 3981 false, false, false, CallingConv::C, false, 3982 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 3983 Args, DAG); 3984 Result = CallResult.second; 3985 break; 3986 } 3987 break; 3988 } 3989 } 3990 3991 assert(Result.getValueType() == Op.getValueType() && 3992 "Bad legalization!"); 3993 3994 // Make sure that the generated code is itself legal. 3995 if (Result != Op) 3996 Result = LegalizeOp(Result); 3997 3998 // Note that LegalizeOp may be reentered even from single-use nodes, which 3999 // means that we always must cache transformed nodes. 4000 AddLegalizedOperand(Op, Result); 4001 return Result; 4002} 4003 4004/// PromoteOp - Given an operation that produces a value in an invalid type, 4005/// promote it to compute the value into a larger type. The produced value will 4006/// have the correct bits for the low portion of the register, but no guarantee 4007/// is made about the top bits: it may be zero, sign-extended, or garbage. 4008SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { 4009 MVT VT = Op.getValueType(); 4010 MVT NVT = TLI.getTypeToTransformTo(VT); 4011 assert(getTypeAction(VT) == Promote && 4012 "Caller should expand or legalize operands that are not promotable!"); 4013 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() && 4014 "Cannot promote to smaller type!"); 4015 4016 SDValue Tmp1, Tmp2, Tmp3; 4017 SDValue Result; 4018 SDNode *Node = Op.getNode(); 4019 4020 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op); 4021 if (I != PromotedNodes.end()) return I->second; 4022 4023 switch (Node->getOpcode()) { 4024 case ISD::CopyFromReg: 4025 assert(0 && "CopyFromReg must be legal!"); 4026 default: 4027#ifndef NDEBUG 4028 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4029#endif 4030 assert(0 && "Do not know how to promote this operator!"); 4031 abort(); 4032 case ISD::UNDEF: 4033 Result = DAG.getNode(ISD::UNDEF, NVT); 4034 break; 4035 case ISD::Constant: 4036 if (VT != MVT::i1) 4037 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4038 else 4039 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4040 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4041 break; 4042 case ISD::ConstantFP: 4043 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4044 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4045 break; 4046 4047 case ISD::SETCC: 4048 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0))) 4049 && "SetCC type is not legal??"); 4050 Result = DAG.getNode(ISD::SETCC, 4051 TLI.getSetCCResultType(Node->getOperand(0)), 4052 Node->getOperand(0), Node->getOperand(1), 4053 Node->getOperand(2)); 4054 break; 4055 4056 case ISD::TRUNCATE: 4057 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4058 case Legal: 4059 Result = LegalizeOp(Node->getOperand(0)); 4060 assert(Result.getValueType().bitsGE(NVT) && 4061 "This truncation doesn't make sense!"); 4062 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT 4063 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4064 break; 4065 case Promote: 4066 // The truncation is not required, because we don't guarantee anything 4067 // about high bits anyway. 4068 Result = PromoteOp(Node->getOperand(0)); 4069 break; 4070 case Expand: 4071 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4072 // Truncate the low part of the expanded value to the result type 4073 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4074 } 4075 break; 4076 case ISD::SIGN_EXTEND: 4077 case ISD::ZERO_EXTEND: 4078 case ISD::ANY_EXTEND: 4079 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4080 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4081 case Legal: 4082 // Input is legal? Just do extend all the way to the larger type. 4083 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4084 break; 4085 case Promote: 4086 // Promote the reg if it's smaller. 4087 Result = PromoteOp(Node->getOperand(0)); 4088 // The high bits are not guaranteed to be anything. Insert an extend. 4089 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4090 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4091 DAG.getValueType(Node->getOperand(0).getValueType())); 4092 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4093 Result = DAG.getZeroExtendInReg(Result, 4094 Node->getOperand(0).getValueType()); 4095 break; 4096 } 4097 break; 4098 case ISD::BIT_CONVERT: 4099 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4100 Node->getValueType(0)); 4101 Result = PromoteOp(Result); 4102 break; 4103 4104 case ISD::FP_EXTEND: 4105 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4106 case ISD::FP_ROUND: 4107 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4108 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4109 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4110 case Legal: 4111 if (Node->getConstantOperandVal(1) == 0) { 4112 // Input is legal? Do an FP_ROUND_INREG. 4113 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4114 DAG.getValueType(VT)); 4115 } else { 4116 // Just remove the truncate, it isn't affecting the value. 4117 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4118 Node->getOperand(1)); 4119 } 4120 break; 4121 } 4122 break; 4123 case ISD::SINT_TO_FP: 4124 case ISD::UINT_TO_FP: 4125 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4126 case Legal: 4127 // No extra round required here. 4128 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4129 break; 4130 4131 case Promote: 4132 Result = PromoteOp(Node->getOperand(0)); 4133 if (Node->getOpcode() == ISD::SINT_TO_FP) 4134 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4135 Result, 4136 DAG.getValueType(Node->getOperand(0).getValueType())); 4137 else 4138 Result = DAG.getZeroExtendInReg(Result, 4139 Node->getOperand(0).getValueType()); 4140 // No extra round required here. 4141 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4142 break; 4143 case Expand: 4144 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4145 Node->getOperand(0)); 4146 // Round if we cannot tolerate excess precision. 4147 if (NoExcessFPPrecision) 4148 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4149 DAG.getValueType(VT)); 4150 break; 4151 } 4152 break; 4153 4154 case ISD::SIGN_EXTEND_INREG: 4155 Result = PromoteOp(Node->getOperand(0)); 4156 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4157 Node->getOperand(1)); 4158 break; 4159 case ISD::FP_TO_SINT: 4160 case ISD::FP_TO_UINT: 4161 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4162 case Legal: 4163 case Expand: 4164 Tmp1 = Node->getOperand(0); 4165 break; 4166 case Promote: 4167 // The input result is prerounded, so we don't have to do anything 4168 // special. 4169 Tmp1 = PromoteOp(Node->getOperand(0)); 4170 break; 4171 } 4172 // If we're promoting a UINT to a larger size, check to see if the new node 4173 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4174 // we can use that instead. This allows us to generate better code for 4175 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4176 // legal, such as PowerPC. 4177 if (Node->getOpcode() == ISD::FP_TO_UINT && 4178 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 4179 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 4180 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4181 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4182 } else { 4183 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4184 } 4185 break; 4186 4187 case ISD::FABS: 4188 case ISD::FNEG: 4189 Tmp1 = PromoteOp(Node->getOperand(0)); 4190 assert(Tmp1.getValueType() == NVT); 4191 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4192 // NOTE: we do not have to do any extra rounding here for 4193 // NoExcessFPPrecision, because we know the input will have the appropriate 4194 // precision, and these operations don't modify precision at all. 4195 break; 4196 4197 case ISD::FLOG: 4198 case ISD::FLOG2: 4199 case ISD::FLOG10: 4200 case ISD::FEXP: 4201 case ISD::FEXP2: 4202 case ISD::FSQRT: 4203 case ISD::FSIN: 4204 case ISD::FCOS: 4205 case ISD::FTRUNC: 4206 case ISD::FFLOOR: 4207 case ISD::FCEIL: 4208 case ISD::FRINT: 4209 case ISD::FNEARBYINT: 4210 Tmp1 = PromoteOp(Node->getOperand(0)); 4211 assert(Tmp1.getValueType() == NVT); 4212 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4213 if (NoExcessFPPrecision) 4214 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4215 DAG.getValueType(VT)); 4216 break; 4217 4218 case ISD::FPOW: 4219 case ISD::FPOWI: { 4220 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall 4221 // directly as well, which may be better. 4222 Tmp1 = PromoteOp(Node->getOperand(0)); 4223 Tmp2 = Node->getOperand(1); 4224 if (Node->getOpcode() == ISD::FPOW) 4225 Tmp2 = PromoteOp(Tmp2); 4226 assert(Tmp1.getValueType() == NVT); 4227 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4228 if (NoExcessFPPrecision) 4229 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4230 DAG.getValueType(VT)); 4231 break; 4232 } 4233 4234 case ISD::ATOMIC_CMP_SWAP_8: 4235 case ISD::ATOMIC_CMP_SWAP_16: 4236 case ISD::ATOMIC_CMP_SWAP_32: 4237 case ISD::ATOMIC_CMP_SWAP_64: { 4238 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4239 Tmp2 = PromoteOp(Node->getOperand(2)); 4240 Tmp3 = PromoteOp(Node->getOperand(3)); 4241 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 4242 AtomNode->getBasePtr(), Tmp2, Tmp3, 4243 AtomNode->getSrcValue(), 4244 AtomNode->getAlignment()); 4245 // Remember that we legalized the chain. 4246 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4247 break; 4248 } 4249 case ISD::ATOMIC_LOAD_ADD_8: 4250 case ISD::ATOMIC_LOAD_SUB_8: 4251 case ISD::ATOMIC_LOAD_AND_8: 4252 case ISD::ATOMIC_LOAD_OR_8: 4253 case ISD::ATOMIC_LOAD_XOR_8: 4254 case ISD::ATOMIC_LOAD_NAND_8: 4255 case ISD::ATOMIC_LOAD_MIN_8: 4256 case ISD::ATOMIC_LOAD_MAX_8: 4257 case ISD::ATOMIC_LOAD_UMIN_8: 4258 case ISD::ATOMIC_LOAD_UMAX_8: 4259 case ISD::ATOMIC_SWAP_8: 4260 case ISD::ATOMIC_LOAD_ADD_16: 4261 case ISD::ATOMIC_LOAD_SUB_16: 4262 case ISD::ATOMIC_LOAD_AND_16: 4263 case ISD::ATOMIC_LOAD_OR_16: 4264 case ISD::ATOMIC_LOAD_XOR_16: 4265 case ISD::ATOMIC_LOAD_NAND_16: 4266 case ISD::ATOMIC_LOAD_MIN_16: 4267 case ISD::ATOMIC_LOAD_MAX_16: 4268 case ISD::ATOMIC_LOAD_UMIN_16: 4269 case ISD::ATOMIC_LOAD_UMAX_16: 4270 case ISD::ATOMIC_SWAP_16: 4271 case ISD::ATOMIC_LOAD_ADD_32: 4272 case ISD::ATOMIC_LOAD_SUB_32: 4273 case ISD::ATOMIC_LOAD_AND_32: 4274 case ISD::ATOMIC_LOAD_OR_32: 4275 case ISD::ATOMIC_LOAD_XOR_32: 4276 case ISD::ATOMIC_LOAD_NAND_32: 4277 case ISD::ATOMIC_LOAD_MIN_32: 4278 case ISD::ATOMIC_LOAD_MAX_32: 4279 case ISD::ATOMIC_LOAD_UMIN_32: 4280 case ISD::ATOMIC_LOAD_UMAX_32: 4281 case ISD::ATOMIC_SWAP_32: 4282 case ISD::ATOMIC_LOAD_ADD_64: 4283 case ISD::ATOMIC_LOAD_SUB_64: 4284 case ISD::ATOMIC_LOAD_AND_64: 4285 case ISD::ATOMIC_LOAD_OR_64: 4286 case ISD::ATOMIC_LOAD_XOR_64: 4287 case ISD::ATOMIC_LOAD_NAND_64: 4288 case ISD::ATOMIC_LOAD_MIN_64: 4289 case ISD::ATOMIC_LOAD_MAX_64: 4290 case ISD::ATOMIC_LOAD_UMIN_64: 4291 case ISD::ATOMIC_LOAD_UMAX_64: 4292 case ISD::ATOMIC_SWAP_64: { 4293 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4294 Tmp2 = PromoteOp(Node->getOperand(2)); 4295 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 4296 AtomNode->getBasePtr(), Tmp2, 4297 AtomNode->getSrcValue(), 4298 AtomNode->getAlignment()); 4299 // Remember that we legalized the chain. 4300 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4301 break; 4302 } 4303 4304 case ISD::AND: 4305 case ISD::OR: 4306 case ISD::XOR: 4307 case ISD::ADD: 4308 case ISD::SUB: 4309 case ISD::MUL: 4310 // The input may have strange things in the top bits of the registers, but 4311 // these operations don't care. They may have weird bits going out, but 4312 // that too is okay if they are integer operations. 4313 Tmp1 = PromoteOp(Node->getOperand(0)); 4314 Tmp2 = PromoteOp(Node->getOperand(1)); 4315 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4316 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4317 break; 4318 case ISD::FADD: 4319 case ISD::FSUB: 4320 case ISD::FMUL: 4321 Tmp1 = PromoteOp(Node->getOperand(0)); 4322 Tmp2 = PromoteOp(Node->getOperand(1)); 4323 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4324 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4325 4326 // Floating point operations will give excess precision that we may not be 4327 // able to tolerate. If we DO allow excess precision, just leave it, 4328 // otherwise excise it. 4329 // FIXME: Why would we need to round FP ops more than integer ones? 4330 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4331 if (NoExcessFPPrecision) 4332 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4333 DAG.getValueType(VT)); 4334 break; 4335 4336 case ISD::SDIV: 4337 case ISD::SREM: 4338 // These operators require that their input be sign extended. 4339 Tmp1 = PromoteOp(Node->getOperand(0)); 4340 Tmp2 = PromoteOp(Node->getOperand(1)); 4341 if (NVT.isInteger()) { 4342 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4343 DAG.getValueType(VT)); 4344 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4345 DAG.getValueType(VT)); 4346 } 4347 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4348 4349 // Perform FP_ROUND: this is probably overly pessimistic. 4350 if (NVT.isFloatingPoint() && NoExcessFPPrecision) 4351 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4352 DAG.getValueType(VT)); 4353 break; 4354 case ISD::FDIV: 4355 case ISD::FREM: 4356 case ISD::FCOPYSIGN: 4357 // These operators require that their input be fp extended. 4358 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4359 case Expand: assert(0 && "not implemented"); 4360 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4361 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4362 } 4363 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4364 case Expand: assert(0 && "not implemented"); 4365 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4366 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4367 } 4368 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4369 4370 // Perform FP_ROUND: this is probably overly pessimistic. 4371 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4372 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4373 DAG.getValueType(VT)); 4374 break; 4375 4376 case ISD::UDIV: 4377 case ISD::UREM: 4378 // These operators require that their input be zero extended. 4379 Tmp1 = PromoteOp(Node->getOperand(0)); 4380 Tmp2 = PromoteOp(Node->getOperand(1)); 4381 assert(NVT.isInteger() && "Operators don't apply to FP!"); 4382 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4383 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4384 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4385 break; 4386 4387 case ISD::SHL: 4388 Tmp1 = PromoteOp(Node->getOperand(0)); 4389 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4390 break; 4391 case ISD::SRA: 4392 // The input value must be properly sign extended. 4393 Tmp1 = PromoteOp(Node->getOperand(0)); 4394 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4395 DAG.getValueType(VT)); 4396 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4397 break; 4398 case ISD::SRL: 4399 // The input value must be properly zero extended. 4400 Tmp1 = PromoteOp(Node->getOperand(0)); 4401 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4402 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4403 break; 4404 4405 case ISD::VAARG: 4406 Tmp1 = Node->getOperand(0); // Get the chain. 4407 Tmp2 = Node->getOperand(1); // Get the pointer. 4408 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4409 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4410 Result = TLI.LowerOperation(Tmp3, DAG); 4411 } else { 4412 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4413 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4414 // Increment the pointer, VAList, to the next vaarg 4415 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4416 DAG.getConstant(VT.getSizeInBits()/8, 4417 TLI.getPointerTy())); 4418 // Store the incremented VAList to the legalized pointer 4419 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4420 // Load the actual argument out of the pointer VAList 4421 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4422 } 4423 // Remember that we legalized the chain. 4424 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4425 break; 4426 4427 case ISD::LOAD: { 4428 LoadSDNode *LD = cast<LoadSDNode>(Node); 4429 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4430 ? ISD::EXTLOAD : LD->getExtensionType(); 4431 Result = DAG.getExtLoad(ExtType, NVT, 4432 LD->getChain(), LD->getBasePtr(), 4433 LD->getSrcValue(), LD->getSrcValueOffset(), 4434 LD->getMemoryVT(), 4435 LD->isVolatile(), 4436 LD->getAlignment()); 4437 // Remember that we legalized the chain. 4438 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4439 break; 4440 } 4441 case ISD::SELECT: { 4442 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4443 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4444 4445 MVT VT2 = Tmp2.getValueType(); 4446 assert(VT2 == Tmp3.getValueType() 4447 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); 4448 // Ensure that the resulting node is at least the same size as the operands' 4449 // value types, because we cannot assume that TLI.getSetCCValueType() is 4450 // constant. 4451 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3); 4452 break; 4453 } 4454 case ISD::SELECT_CC: 4455 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4456 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4457 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4458 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4459 break; 4460 case ISD::BSWAP: 4461 Tmp1 = Node->getOperand(0); 4462 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4463 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4464 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4465 DAG.getConstant(NVT.getSizeInBits() - 4466 VT.getSizeInBits(), 4467 TLI.getShiftAmountTy())); 4468 break; 4469 case ISD::CTPOP: 4470 case ISD::CTTZ: 4471 case ISD::CTLZ: 4472 // Zero extend the argument 4473 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4474 // Perform the larger operation, then subtract if needed. 4475 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4476 switch(Node->getOpcode()) { 4477 case ISD::CTPOP: 4478 Result = Tmp1; 4479 break; 4480 case ISD::CTTZ: 4481 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4482 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 4483 DAG.getConstant(NVT.getSizeInBits(), NVT), 4484 ISD::SETEQ); 4485 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4486 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); 4487 break; 4488 case ISD::CTLZ: 4489 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4490 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4491 DAG.getConstant(NVT.getSizeInBits() - 4492 VT.getSizeInBits(), NVT)); 4493 break; 4494 } 4495 break; 4496 case ISD::EXTRACT_SUBVECTOR: 4497 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4498 break; 4499 case ISD::EXTRACT_VECTOR_ELT: 4500 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4501 break; 4502 } 4503 4504 assert(Result.getNode() && "Didn't set a result!"); 4505 4506 // Make sure the result is itself legal. 4507 Result = LegalizeOp(Result); 4508 4509 // Remember that we promoted this! 4510 AddPromotedOperand(Op, Result); 4511 return Result; 4512} 4513 4514/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4515/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4516/// based on the vector type. The return type of this matches the element type 4517/// of the vector, which may not be legal for the target. 4518SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) { 4519 // We know that operand #0 is the Vec vector. If the index is a constant 4520 // or if the invec is a supported hardware type, we can use it. Otherwise, 4521 // lower to a store then an indexed load. 4522 SDValue Vec = Op.getOperand(0); 4523 SDValue Idx = Op.getOperand(1); 4524 4525 MVT TVT = Vec.getValueType(); 4526 unsigned NumElems = TVT.getVectorNumElements(); 4527 4528 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4529 default: assert(0 && "This action is not supported yet!"); 4530 case TargetLowering::Custom: { 4531 Vec = LegalizeOp(Vec); 4532 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4533 SDValue Tmp3 = TLI.LowerOperation(Op, DAG); 4534 if (Tmp3.getNode()) 4535 return Tmp3; 4536 break; 4537 } 4538 case TargetLowering::Legal: 4539 if (isTypeLegal(TVT)) { 4540 Vec = LegalizeOp(Vec); 4541 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4542 return Op; 4543 } 4544 break; 4545 case TargetLowering::Expand: 4546 break; 4547 } 4548 4549 if (NumElems == 1) { 4550 // This must be an access of the only element. Return it. 4551 Op = ScalarizeVectorOp(Vec); 4552 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 4553 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 4554 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4555 SDValue Lo, Hi; 4556 SplitVectorOp(Vec, Lo, Hi); 4557 if (CIdx->getZExtValue() < NumLoElts) { 4558 Vec = Lo; 4559 } else { 4560 Vec = Hi; 4561 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts, 4562 Idx.getValueType()); 4563 } 4564 4565 // It's now an extract from the appropriate high or low part. Recurse. 4566 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4567 Op = ExpandEXTRACT_VECTOR_ELT(Op); 4568 } else { 4569 // Store the value to a temporary stack slot, then LOAD the scalar 4570 // element back out. 4571 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 4572 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 4573 4574 // Add the offset to the index. 4575 unsigned EltSize = Op.getValueType().getSizeInBits()/8; 4576 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 4577 DAG.getConstant(EltSize, Idx.getValueType())); 4578 4579 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 4580 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 4581 else 4582 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 4583 4584 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 4585 4586 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 4587 } 4588 return Op; 4589} 4590 4591/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 4592/// we assume the operation can be split if it is not already legal. 4593SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) { 4594 // We know that operand #0 is the Vec vector. For now we assume the index 4595 // is a constant and that the extracted result is a supported hardware type. 4596 SDValue Vec = Op.getOperand(0); 4597 SDValue Idx = LegalizeOp(Op.getOperand(1)); 4598 4599 unsigned NumElems = Vec.getValueType().getVectorNumElements(); 4600 4601 if (NumElems == Op.getValueType().getVectorNumElements()) { 4602 // This must be an access of the desired vector length. Return it. 4603 return Vec; 4604 } 4605 4606 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 4607 SDValue Lo, Hi; 4608 SplitVectorOp(Vec, Lo, Hi); 4609 if (CIdx->getZExtValue() < NumElems/2) { 4610 Vec = Lo; 4611 } else { 4612 Vec = Hi; 4613 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2, 4614 Idx.getValueType()); 4615 } 4616 4617 // It's now an extract from the appropriate high or low part. Recurse. 4618 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4619 return ExpandEXTRACT_SUBVECTOR(Op); 4620} 4621 4622/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 4623/// with condition CC on the current target. This usually involves legalizing 4624/// or promoting the arguments. In the case where LHS and RHS must be expanded, 4625/// there may be no choice but to create a new SetCC node to represent the 4626/// legalized value of setcc lhs, rhs. In this case, the value is returned in 4627/// LHS, and the SDValue returned in RHS has a nil SDNode value. 4628void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS, 4629 SDValue &RHS, 4630 SDValue &CC) { 4631 SDValue Tmp1, Tmp2, Tmp3, Result; 4632 4633 switch (getTypeAction(LHS.getValueType())) { 4634 case Legal: 4635 Tmp1 = LegalizeOp(LHS); // LHS 4636 Tmp2 = LegalizeOp(RHS); // RHS 4637 break; 4638 case Promote: 4639 Tmp1 = PromoteOp(LHS); // LHS 4640 Tmp2 = PromoteOp(RHS); // RHS 4641 4642 // If this is an FP compare, the operands have already been extended. 4643 if (LHS.getValueType().isInteger()) { 4644 MVT VT = LHS.getValueType(); 4645 MVT NVT = TLI.getTypeToTransformTo(VT); 4646 4647 // Otherwise, we have to insert explicit sign or zero extends. Note 4648 // that we could insert sign extends for ALL conditions, but zero extend 4649 // is cheaper on many machines (an AND instead of two shifts), so prefer 4650 // it. 4651 switch (cast<CondCodeSDNode>(CC)->get()) { 4652 default: assert(0 && "Unknown integer comparison!"); 4653 case ISD::SETEQ: 4654 case ISD::SETNE: 4655 case ISD::SETUGE: 4656 case ISD::SETUGT: 4657 case ISD::SETULE: 4658 case ISD::SETULT: 4659 // ALL of these operations will work if we either sign or zero extend 4660 // the operands (including the unsigned comparisons!). Zero extend is 4661 // usually a simpler/cheaper operation, so prefer it. 4662 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4663 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4664 break; 4665 case ISD::SETGE: 4666 case ISD::SETGT: 4667 case ISD::SETLT: 4668 case ISD::SETLE: 4669 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4670 DAG.getValueType(VT)); 4671 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4672 DAG.getValueType(VT)); 4673 break; 4674 } 4675 } 4676 break; 4677 case Expand: { 4678 MVT VT = LHS.getValueType(); 4679 if (VT == MVT::f32 || VT == MVT::f64) { 4680 // Expand into one or more soft-fp libcall(s). 4681 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; 4682 switch (cast<CondCodeSDNode>(CC)->get()) { 4683 case ISD::SETEQ: 4684 case ISD::SETOEQ: 4685 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4686 break; 4687 case ISD::SETNE: 4688 case ISD::SETUNE: 4689 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 4690 break; 4691 case ISD::SETGE: 4692 case ISD::SETOGE: 4693 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4694 break; 4695 case ISD::SETLT: 4696 case ISD::SETOLT: 4697 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4698 break; 4699 case ISD::SETLE: 4700 case ISD::SETOLE: 4701 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4702 break; 4703 case ISD::SETGT: 4704 case ISD::SETOGT: 4705 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4706 break; 4707 case ISD::SETUO: 4708 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4709 break; 4710 case ISD::SETO: 4711 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 4712 break; 4713 default: 4714 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 4715 switch (cast<CondCodeSDNode>(CC)->get()) { 4716 case ISD::SETONE: 4717 // SETONE = SETOLT | SETOGT 4718 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4719 // Fallthrough 4720 case ISD::SETUGT: 4721 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 4722 break; 4723 case ISD::SETUGE: 4724 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 4725 break; 4726 case ISD::SETULT: 4727 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 4728 break; 4729 case ISD::SETULE: 4730 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 4731 break; 4732 case ISD::SETUEQ: 4733 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 4734 break; 4735 default: assert(0 && "Unsupported FP setcc!"); 4736 } 4737 } 4738 4739 SDValue Dummy; 4740 SDValue Ops[2] = { LHS, RHS }; 4741 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(), 4742 false /*sign irrelevant*/, Dummy); 4743 Tmp2 = DAG.getConstant(0, MVT::i32); 4744 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 4745 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 4746 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 4747 CC); 4748 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(), 4749 false /*sign irrelevant*/, Dummy); 4750 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, 4751 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 4752 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4753 Tmp2 = SDValue(); 4754 } 4755 LHS = LegalizeOp(Tmp1); 4756 RHS = Tmp2; 4757 return; 4758 } 4759 4760 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 4761 ExpandOp(LHS, LHSLo, LHSHi); 4762 ExpandOp(RHS, RHSLo, RHSHi); 4763 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 4764 4765 if (VT==MVT::ppcf128) { 4766 // FIXME: This generated code sucks. We want to generate 4767 // FCMPU crN, hi1, hi2 4768 // BNE crN, L: 4769 // FCMPU crN, lo1, lo2 4770 // The following can be improved, but not that much. 4771 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4772 ISD::SETOEQ); 4773 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode); 4774 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4775 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4776 ISD::SETUNE); 4777 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode); 4778 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 4779 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 4780 Tmp2 = SDValue(); 4781 break; 4782 } 4783 4784 switch (CCCode) { 4785 case ISD::SETEQ: 4786 case ISD::SETNE: 4787 if (RHSLo == RHSHi) 4788 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 4789 if (RHSCST->isAllOnesValue()) { 4790 // Comparison to -1. 4791 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 4792 Tmp2 = RHSLo; 4793 break; 4794 } 4795 4796 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 4797 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 4798 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 4799 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 4800 break; 4801 default: 4802 // If this is a comparison of the sign bit, just look at the top part. 4803 // X > -1, x < 0 4804 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 4805 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 4806 CST->isNullValue()) || // X < 0 4807 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 4808 CST->isAllOnesValue())) { // X > -1 4809 Tmp1 = LHSHi; 4810 Tmp2 = RHSHi; 4811 break; 4812 } 4813 4814 // FIXME: This generated code sucks. 4815 ISD::CondCode LowCC; 4816 switch (CCCode) { 4817 default: assert(0 && "Unknown integer setcc!"); 4818 case ISD::SETLT: 4819 case ISD::SETULT: LowCC = ISD::SETULT; break; 4820 case ISD::SETGT: 4821 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 4822 case ISD::SETLE: 4823 case ISD::SETULE: LowCC = ISD::SETULE; break; 4824 case ISD::SETGE: 4825 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 4826 } 4827 4828 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 4829 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 4830 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 4831 4832 // NOTE: on targets without efficient SELECT of bools, we can always use 4833 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 4834 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 4835 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, 4836 LowCC, false, DagCombineInfo); 4837 if (!Tmp1.getNode()) 4838 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 4839 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4840 CCCode, false, DagCombineInfo); 4841 if (!Tmp2.getNode()) 4842 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, 4843 RHSHi,CC); 4844 4845 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 4846 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 4847 if ((Tmp1C && Tmp1C->isNullValue()) || 4848 (Tmp2C && Tmp2C->isNullValue() && 4849 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 4850 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 4851 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 4852 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 4853 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 4854 // low part is known false, returns high part. 4855 // For LE / GE, if high part is known false, ignore the low part. 4856 // For LT / GT, if high part is known true, ignore the low part. 4857 Tmp1 = Tmp2; 4858 Tmp2 = SDValue(); 4859 } else { 4860 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4861 ISD::SETEQ, false, DagCombineInfo); 4862 if (!Result.getNode()) 4863 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 4864 ISD::SETEQ); 4865 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 4866 Result, Tmp1, Tmp2)); 4867 Tmp1 = Result; 4868 Tmp2 = SDValue(); 4869 } 4870 } 4871 } 4872 } 4873 LHS = Tmp1; 4874 RHS = Tmp2; 4875} 4876 4877/// EmitStackConvert - Emit a store/load combination to the stack. This stores 4878/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 4879/// a load from the stack slot to DestVT, extending it if needed. 4880/// The resultant code need not be legal. 4881SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 4882 MVT SlotVT, 4883 MVT DestVT) { 4884 // Create the stack frame object. 4885 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment( 4886 SrcOp.getValueType().getTypeForMVT()); 4887 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 4888 4889 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 4890 int SPFI = StackPtrFI->getIndex(); 4891 4892 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 4893 unsigned SlotSize = SlotVT.getSizeInBits(); 4894 unsigned DestSize = DestVT.getSizeInBits(); 4895 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment( 4896 DestVT.getTypeForMVT()); 4897 4898 // Emit a store to the stack slot. Use a truncstore if the input value is 4899 // later than DestVT. 4900 SDValue Store; 4901 4902 if (SrcSize > SlotSize) 4903 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 4904 PseudoSourceValue::getFixedStack(SPFI), 0, 4905 SlotVT, false, SrcAlign); 4906 else { 4907 assert(SrcSize == SlotSize && "Invalid store"); 4908 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 4909 PseudoSourceValue::getFixedStack(SPFI), 0, 4910 false, SrcAlign); 4911 } 4912 4913 // Result is a load from the stack slot. 4914 if (SlotSize == DestSize) 4915 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign); 4916 4917 assert(SlotSize < DestSize && "Unknown extension!"); 4918 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT, 4919 false, DestAlign); 4920} 4921 4922SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 4923 // Create a vector sized/aligned stack slot, store the value to element #0, 4924 // then load the whole vector back out. 4925 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 4926 4927 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 4928 int SPFI = StackPtrFI->getIndex(); 4929 4930 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 4931 PseudoSourceValue::getFixedStack(SPFI), 0); 4932 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 4933 PseudoSourceValue::getFixedStack(SPFI), 0); 4934} 4935 4936 4937/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 4938/// support the operation, but do support the resultant vector type. 4939SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 4940 4941 // If the only non-undef value is the low element, turn this into a 4942 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 4943 unsigned NumElems = Node->getNumOperands(); 4944 bool isOnlyLowElement = true; 4945 SDValue SplatValue = Node->getOperand(0); 4946 4947 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t> 4948 // and use a bitmask instead of a list of elements. 4949 std::map<SDValue, std::vector<unsigned> > Values; 4950 Values[SplatValue].push_back(0); 4951 bool isConstant = true; 4952 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 4953 SplatValue.getOpcode() != ISD::UNDEF) 4954 isConstant = false; 4955 4956 for (unsigned i = 1; i < NumElems; ++i) { 4957 SDValue V = Node->getOperand(i); 4958 Values[V].push_back(i); 4959 if (V.getOpcode() != ISD::UNDEF) 4960 isOnlyLowElement = false; 4961 if (SplatValue != V) 4962 SplatValue = SDValue(0,0); 4963 4964 // If this isn't a constant element or an undef, we can't use a constant 4965 // pool load. 4966 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 4967 V.getOpcode() != ISD::UNDEF) 4968 isConstant = false; 4969 } 4970 4971 if (isOnlyLowElement) { 4972 // If the low element is an undef too, then this whole things is an undef. 4973 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 4974 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 4975 // Otherwise, turn this into a scalar_to_vector node. 4976 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 4977 Node->getOperand(0)); 4978 } 4979 4980 // If all elements are constants, create a load from the constant pool. 4981 if (isConstant) { 4982 MVT VT = Node->getValueType(0); 4983 std::vector<Constant*> CV; 4984 for (unsigned i = 0, e = NumElems; i != e; ++i) { 4985 if (ConstantFPSDNode *V = 4986 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 4987 CV.push_back(ConstantFP::get(V->getValueAPF())); 4988 } else if (ConstantSDNode *V = 4989 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 4990 CV.push_back(ConstantInt::get(V->getAPIntValue())); 4991 } else { 4992 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 4993 const Type *OpNTy = 4994 Node->getOperand(0).getValueType().getTypeForMVT(); 4995 CV.push_back(UndefValue::get(OpNTy)); 4996 } 4997 } 4998 Constant *CP = ConstantVector::get(CV); 4999 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 5000 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 5001 PseudoSourceValue::getConstantPool(), 0); 5002 } 5003 5004 if (SplatValue.getNode()) { // Splat of one value? 5005 // Build the shuffle constant vector: <0, 0, 0, 0> 5006 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5007 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); 5008 std::vector<SDValue> ZeroVec(NumElems, Zero); 5009 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5010 &ZeroVec[0], ZeroVec.size()); 5011 5012 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 5013 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 5014 // Get the splatted value into the low element of a vector register. 5015 SDValue LowValVec = 5016 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 5017 5018 // Return shuffle(LowValVec, undef, <0,0,0,0>) 5019 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 5020 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 5021 SplatMask); 5022 } 5023 } 5024 5025 // If there are only two unique elements, we may be able to turn this into a 5026 // vector shuffle. 5027 if (Values.size() == 2) { 5028 // Get the two values in deterministic order. 5029 SDValue Val1 = Node->getOperand(1); 5030 SDValue Val2; 5031 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin(); 5032 if (MI->first != Val1) 5033 Val2 = MI->first; 5034 else 5035 Val2 = (++MI)->first; 5036 5037 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 5038 // vector shuffle has the undef vector on the RHS. 5039 if (Val1.getOpcode() == ISD::UNDEF) 5040 std::swap(Val1, Val2); 5041 5042 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 5043 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5044 MVT MaskEltVT = MaskVT.getVectorElementType(); 5045 std::vector<SDValue> MaskVec(NumElems); 5046 5047 // Set elements of the shuffle mask for Val1. 5048 std::vector<unsigned> &Val1Elts = Values[Val1]; 5049 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 5050 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 5051 5052 // Set elements of the shuffle mask for Val2. 5053 std::vector<unsigned> &Val2Elts = Values[Val2]; 5054 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 5055 if (Val2.getOpcode() != ISD::UNDEF) 5056 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 5057 else 5058 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); 5059 5060 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5061 &MaskVec[0], MaskVec.size()); 5062 5063 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 5064 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 5065 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 5066 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); 5067 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); 5068 SDValue Ops[] = { Val1, Val2, ShuffleMask }; 5069 5070 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 5071 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); 5072 } 5073 } 5074 5075 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5076 // aligned object on the stack, store each element into it, then load 5077 // the result as a vector. 5078 MVT VT = Node->getValueType(0); 5079 // Create the stack frame object. 5080 SDValue FIPtr = DAG.CreateStackTemporary(VT); 5081 5082 // Emit a store of each element to the stack slot. 5083 SmallVector<SDValue, 8> Stores; 5084 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8; 5085 // Store (in the right endianness) the elements to memory. 5086 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5087 // Ignore undef elements. 5088 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5089 5090 unsigned Offset = TypeByteSize*i; 5091 5092 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5093 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 5094 5095 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 5096 NULL, 0)); 5097 } 5098 5099 SDValue StoreChain; 5100 if (!Stores.empty()) // Not all undef elements? 5101 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5102 &Stores[0], Stores.size()); 5103 else 5104 StoreChain = DAG.getEntryNode(); 5105 5106 // Result is a load from the stack slot. 5107 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 5108} 5109 5110void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5111 SDValue Op, SDValue Amt, 5112 SDValue &Lo, SDValue &Hi) { 5113 // Expand the subcomponents. 5114 SDValue LHSL, LHSH; 5115 ExpandOp(Op, LHSL, LHSH); 5116 5117 SDValue Ops[] = { LHSL, LHSH, Amt }; 5118 MVT VT = LHSL.getValueType(); 5119 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5120 Hi = Lo.getValue(1); 5121} 5122 5123 5124/// ExpandShift - Try to find a clever way to expand this shift operation out to 5125/// smaller elements. If we can't find a way that is more efficient than a 5126/// libcall on this target, return false. Otherwise, return true with the 5127/// low-parts expanded into Lo and Hi. 5128bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, 5129 SDValue &Lo, SDValue &Hi) { 5130 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5131 "This is not a shift!"); 5132 5133 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5134 SDValue ShAmt = LegalizeOp(Amt); 5135 MVT ShTy = ShAmt.getValueType(); 5136 unsigned ShBits = ShTy.getSizeInBits(); 5137 unsigned VTBits = Op.getValueType().getSizeInBits(); 5138 unsigned NVTBits = NVT.getSizeInBits(); 5139 5140 // Handle the case when Amt is an immediate. 5141 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) { 5142 unsigned Cst = CN->getZExtValue(); 5143 // Expand the incoming operand to be shifted, so that we have its parts 5144 SDValue InL, InH; 5145 ExpandOp(Op, InL, InH); 5146 switch(Opc) { 5147 case ISD::SHL: 5148 if (Cst > VTBits) { 5149 Lo = DAG.getConstant(0, NVT); 5150 Hi = DAG.getConstant(0, NVT); 5151 } else if (Cst > NVTBits) { 5152 Lo = DAG.getConstant(0, NVT); 5153 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5154 } else if (Cst == NVTBits) { 5155 Lo = DAG.getConstant(0, NVT); 5156 Hi = InL; 5157 } else { 5158 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5159 Hi = DAG.getNode(ISD::OR, NVT, 5160 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5161 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5162 } 5163 return true; 5164 case ISD::SRL: 5165 if (Cst > VTBits) { 5166 Lo = DAG.getConstant(0, NVT); 5167 Hi = DAG.getConstant(0, NVT); 5168 } else if (Cst > NVTBits) { 5169 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5170 Hi = DAG.getConstant(0, NVT); 5171 } else if (Cst == NVTBits) { 5172 Lo = InH; 5173 Hi = DAG.getConstant(0, NVT); 5174 } else { 5175 Lo = DAG.getNode(ISD::OR, NVT, 5176 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5177 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5178 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5179 } 5180 return true; 5181 case ISD::SRA: 5182 if (Cst > VTBits) { 5183 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5184 DAG.getConstant(NVTBits-1, ShTy)); 5185 } else if (Cst > NVTBits) { 5186 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5187 DAG.getConstant(Cst-NVTBits, ShTy)); 5188 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5189 DAG.getConstant(NVTBits-1, ShTy)); 5190 } else if (Cst == NVTBits) { 5191 Lo = InH; 5192 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5193 DAG.getConstant(NVTBits-1, ShTy)); 5194 } else { 5195 Lo = DAG.getNode(ISD::OR, NVT, 5196 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5197 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5198 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5199 } 5200 return true; 5201 } 5202 } 5203 5204 // Okay, the shift amount isn't constant. However, if we can tell that it is 5205 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5206 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5207 APInt KnownZero, KnownOne; 5208 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5209 5210 // If we know that if any of the high bits of the shift amount are one, then 5211 // we can do this as a couple of simple shifts. 5212 if (KnownOne.intersects(Mask)) { 5213 // Mask out the high bit, which we know is set. 5214 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5215 DAG.getConstant(~Mask, Amt.getValueType())); 5216 5217 // Expand the incoming operand to be shifted, so that we have its parts 5218 SDValue InL, InH; 5219 ExpandOp(Op, InL, InH); 5220 switch(Opc) { 5221 case ISD::SHL: 5222 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5223 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5224 return true; 5225 case ISD::SRL: 5226 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5227 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5228 return true; 5229 case ISD::SRA: 5230 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5231 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5232 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5233 return true; 5234 } 5235 } 5236 5237 // If we know that the high bits of the shift amount are all zero, then we can 5238 // do this as a couple of simple shifts. 5239 if ((KnownZero & Mask) == Mask) { 5240 // Compute 32-amt. 5241 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5242 DAG.getConstant(NVTBits, Amt.getValueType()), 5243 Amt); 5244 5245 // Expand the incoming operand to be shifted, so that we have its parts 5246 SDValue InL, InH; 5247 ExpandOp(Op, InL, InH); 5248 switch(Opc) { 5249 case ISD::SHL: 5250 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5251 Hi = DAG.getNode(ISD::OR, NVT, 5252 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5253 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5254 return true; 5255 case ISD::SRL: 5256 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5257 Lo = DAG.getNode(ISD::OR, NVT, 5258 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5259 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5260 return true; 5261 case ISD::SRA: 5262 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5263 Lo = DAG.getNode(ISD::OR, NVT, 5264 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5265 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5266 return true; 5267 } 5268 } 5269 5270 return false; 5271} 5272 5273 5274// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5275// does not fit into a register, return the lo part and set the hi part to the 5276// by-reg argument. If it does fit into a single register, return the result 5277// and leave the Hi part unset. 5278SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5279 bool isSigned, SDValue &Hi) { 5280 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5281 // The input chain to this libcall is the entry node of the function. 5282 // Legalizing the call will automatically add the previous call to the 5283 // dependence. 5284 SDValue InChain = DAG.getEntryNode(); 5285 5286 TargetLowering::ArgListTy Args; 5287 TargetLowering::ArgListEntry Entry; 5288 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5289 MVT ArgVT = Node->getOperand(i).getValueType(); 5290 const Type *ArgTy = ArgVT.getTypeForMVT(); 5291 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5292 Entry.isSExt = isSigned; 5293 Entry.isZExt = !isSigned; 5294 Args.push_back(Entry); 5295 } 5296 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5297 TLI.getPointerTy()); 5298 5299 // Splice the libcall in wherever FindInputOutputChains tells us to. 5300 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 5301 std::pair<SDValue,SDValue> CallInfo = 5302 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C, 5303 false, Callee, Args, DAG); 5304 5305 // Legalize the call sequence, starting with the chain. This will advance 5306 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5307 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5308 LegalizeOp(CallInfo.second); 5309 SDValue Result; 5310 switch (getTypeAction(CallInfo.first.getValueType())) { 5311 default: assert(0 && "Unknown thing"); 5312 case Legal: 5313 Result = CallInfo.first; 5314 break; 5315 case Expand: 5316 ExpandOp(CallInfo.first, Result, Hi); 5317 break; 5318 } 5319 return Result; 5320} 5321 5322/// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation. 5323/// 5324SDValue SelectionDAGLegalize:: 5325LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) { 5326 bool isCustom = false; 5327 SDValue Tmp1; 5328 switch (getTypeAction(Op.getValueType())) { 5329 case Legal: 5330 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5331 Op.getValueType())) { 5332 default: assert(0 && "Unknown operation action!"); 5333 case TargetLowering::Custom: 5334 isCustom = true; 5335 // FALLTHROUGH 5336 case TargetLowering::Legal: 5337 Tmp1 = LegalizeOp(Op); 5338 if (Result.getNode()) 5339 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5340 else 5341 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5342 DestTy, Tmp1); 5343 if (isCustom) { 5344 Tmp1 = TLI.LowerOperation(Result, DAG); 5345 if (Tmp1.getNode()) Result = Tmp1; 5346 } 5347 break; 5348 case TargetLowering::Expand: 5349 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy); 5350 break; 5351 case TargetLowering::Promote: 5352 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned); 5353 break; 5354 } 5355 break; 5356 case Expand: 5357 Result = ExpandIntToFP(isSigned, DestTy, Op); 5358 break; 5359 case Promote: 5360 Tmp1 = PromoteOp(Op); 5361 if (isSigned) { 5362 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 5363 Tmp1, DAG.getValueType(Op.getValueType())); 5364 } else { 5365 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 5366 Op.getValueType()); 5367 } 5368 if (Result.getNode()) 5369 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5370 else 5371 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5372 DestTy, Tmp1); 5373 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 5374 break; 5375 } 5376 return Result; 5377} 5378 5379/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5380/// 5381SDValue SelectionDAGLegalize:: 5382ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) { 5383 MVT SourceVT = Source.getValueType(); 5384 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5385 5386 // Expand unsupported int-to-fp vector casts by unrolling them. 5387 if (DestTy.isVector()) { 5388 if (!ExpandSource) 5389 return LegalizeOp(UnrollVectorOp(Source)); 5390 MVT DestEltTy = DestTy.getVectorElementType(); 5391 if (DestTy.getVectorNumElements() == 1) { 5392 SDValue Scalar = ScalarizeVectorOp(Source); 5393 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned, 5394 DestEltTy, Scalar); 5395 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result); 5396 } 5397 SDValue Lo, Hi; 5398 SplitVectorOp(Source, Lo, Hi); 5399 MVT SplitDestTy = MVT::getVectorVT(DestEltTy, 5400 DestTy.getVectorNumElements() / 2); 5401 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo); 5402 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi); 5403 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult, HiResult)); 5404 } 5405 5406 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5407 if (!isSigned && SourceVT != MVT::i32) { 5408 // The integer value loaded will be incorrectly if the 'sign bit' of the 5409 // incoming integer is set. To handle this, we dynamically test to see if 5410 // it is set, and, if so, add a fudge factor. 5411 SDValue Hi; 5412 if (ExpandSource) { 5413 SDValue Lo; 5414 ExpandOp(Source, Lo, Hi); 5415 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); 5416 } else { 5417 // The comparison for the sign bit will use the entire operand. 5418 Hi = Source; 5419 } 5420 5421 // If this is unsigned, and not supported, first perform the conversion to 5422 // signed, then adjust the result if the sign bit is set. 5423 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source); 5424 5425 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 5426 DAG.getConstant(0, Hi.getValueType()), 5427 ISD::SETLT); 5428 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5429 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5430 SignSet, Four, Zero); 5431 uint64_t FF = 0x5f800000ULL; 5432 if (TLI.isLittleEndian()) FF <<= 32; 5433 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5434 5435 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5436 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5437 SDValue FudgeInReg; 5438 if (DestTy == MVT::f32) 5439 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5440 PseudoSourceValue::getConstantPool(), 0); 5441 else if (DestTy.bitsGT(MVT::f32)) 5442 // FIXME: Avoid the extend by construction the right constantpool? 5443 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5444 CPIdx, 5445 PseudoSourceValue::getConstantPool(), 0, 5446 MVT::f32); 5447 else 5448 assert(0 && "Unexpected conversion"); 5449 5450 MVT SCVT = SignedConv.getValueType(); 5451 if (SCVT != DestTy) { 5452 // Destination type needs to be expanded as well. The FADD now we are 5453 // constructing will be expanded into a libcall. 5454 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { 5455 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); 5456 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, 5457 SignedConv, SignedConv.getValue(1)); 5458 } 5459 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5460 } 5461 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5462 } 5463 5464 // Check to see if the target has a custom way to lower this. If so, use it. 5465 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 5466 default: assert(0 && "This action not implemented for this operation!"); 5467 case TargetLowering::Legal: 5468 case TargetLowering::Expand: 5469 break; // This case is handled below. 5470 case TargetLowering::Custom: { 5471 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 5472 Source), DAG); 5473 if (NV.getNode()) 5474 return LegalizeOp(NV); 5475 break; // The target decided this was legal after all 5476 } 5477 } 5478 5479 // Expand the source, then glue it back together for the call. We must expand 5480 // the source in case it is shared (this pass of legalize must traverse it). 5481 if (ExpandSource) { 5482 SDValue SrcLo, SrcHi; 5483 ExpandOp(Source, SrcLo, SrcHi); 5484 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); 5485 } 5486 5487 RTLIB::Libcall LC = isSigned ? 5488 RTLIB::getSINTTOFP(SourceVT, DestTy) : 5489 RTLIB::getUINTTOFP(SourceVT, DestTy); 5490 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type"); 5491 5492 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 5493 SDValue HiPart; 5494 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart); 5495 if (Result.getValueType() != DestTy && HiPart.getNode()) 5496 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); 5497 return Result; 5498} 5499 5500/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 5501/// INT_TO_FP operation of the specified operand when the target requests that 5502/// we expand it. At this point, we know that the result and operand types are 5503/// legal for the target. 5504SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 5505 SDValue Op0, 5506 MVT DestVT) { 5507 if (Op0.getValueType() == MVT::i32) { 5508 // simple 32-bit [signed|unsigned] integer to float/double expansion 5509 5510 // Get the stack frame index of a 8 byte buffer. 5511 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 5512 5513 // word offset constant for Hi/Lo address computation 5514 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 5515 // set up Hi and Lo (into buffer) address based on endian 5516 SDValue Hi = StackSlot; 5517 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 5518 if (TLI.isLittleEndian()) 5519 std::swap(Hi, Lo); 5520 5521 // if signed map to unsigned space 5522 SDValue Op0Mapped; 5523 if (isSigned) { 5524 // constant used to invert sign bit (signed to unsigned mapping) 5525 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 5526 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 5527 } else { 5528 Op0Mapped = Op0; 5529 } 5530 // store the lo of the constructed double - based on integer input 5531 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), 5532 Op0Mapped, Lo, NULL, 0); 5533 // initial hi portion of constructed double 5534 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 5535 // store the hi of the constructed double - biased exponent 5536 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 5537 // load the constructed double 5538 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 5539 // FP constant to bias correct the final result 5540 SDValue Bias = DAG.getConstantFP(isSigned ? 5541 BitsToDouble(0x4330000080000000ULL) 5542 : BitsToDouble(0x4330000000000000ULL), 5543 MVT::f64); 5544 // subtract the bias 5545 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 5546 // final result 5547 SDValue Result; 5548 // handle final rounding 5549 if (DestVT == MVT::f64) { 5550 // do nothing 5551 Result = Sub; 5552 } else if (DestVT.bitsLT(MVT::f64)) { 5553 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 5554 DAG.getIntPtrConstant(0)); 5555 } else if (DestVT.bitsGT(MVT::f64)) { 5556 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 5557 } 5558 return Result; 5559 } 5560 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 5561 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 5562 5563 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0, 5564 DAG.getConstant(0, Op0.getValueType()), 5565 ISD::SETLT); 5566 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5567 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5568 SignSet, Four, Zero); 5569 5570 // If the sign bit of the integer is set, the large number will be treated 5571 // as a negative number. To counteract this, the dynamic code adds an 5572 // offset depending on the data type. 5573 uint64_t FF; 5574 switch (Op0.getValueType().getSimpleVT()) { 5575 default: assert(0 && "Unsupported integer type!"); 5576 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 5577 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 5578 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 5579 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 5580 } 5581 if (TLI.isLittleEndian()) FF <<= 32; 5582 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5583 5584 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5585 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5586 SDValue FudgeInReg; 5587 if (DestVT == MVT::f32) 5588 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5589 PseudoSourceValue::getConstantPool(), 0); 5590 else { 5591 FudgeInReg = 5592 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 5593 DAG.getEntryNode(), CPIdx, 5594 PseudoSourceValue::getConstantPool(), 0, 5595 MVT::f32)); 5596 } 5597 5598 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 5599} 5600 5601/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 5602/// *INT_TO_FP operation of the specified operand when the target requests that 5603/// we promote it. At this point, we know that the result and operand types are 5604/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 5605/// operation that takes a larger input. 5606SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 5607 MVT DestVT, 5608 bool isSigned) { 5609 // First step, figure out the appropriate *INT_TO_FP operation to use. 5610 MVT NewInTy = LegalOp.getValueType(); 5611 5612 unsigned OpToUse = 0; 5613 5614 // Scan for the appropriate larger type to use. 5615 while (1) { 5616 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 5617 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 5618 5619 // If the target supports SINT_TO_FP of this type, use it. 5620 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 5621 default: break; 5622 case TargetLowering::Legal: 5623 if (!TLI.isTypeLegal(NewInTy)) 5624 break; // Can't use this datatype. 5625 // FALL THROUGH. 5626 case TargetLowering::Custom: 5627 OpToUse = ISD::SINT_TO_FP; 5628 break; 5629 } 5630 if (OpToUse) break; 5631 if (isSigned) continue; 5632 5633 // If the target supports UINT_TO_FP of this type, use it. 5634 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 5635 default: break; 5636 case TargetLowering::Legal: 5637 if (!TLI.isTypeLegal(NewInTy)) 5638 break; // Can't use this datatype. 5639 // FALL THROUGH. 5640 case TargetLowering::Custom: 5641 OpToUse = ISD::UINT_TO_FP; 5642 break; 5643 } 5644 if (OpToUse) break; 5645 5646 // Otherwise, try a larger type. 5647 } 5648 5649 // Okay, we found the operation and type to use. Zero extend our input to the 5650 // desired type then run the operation on it. 5651 return DAG.getNode(OpToUse, DestVT, 5652 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 5653 NewInTy, LegalOp)); 5654} 5655 5656/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 5657/// FP_TO_*INT operation of the specified operand when the target requests that 5658/// we promote it. At this point, we know that the result and operand types are 5659/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 5660/// operation that returns a larger result. 5661SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 5662 MVT DestVT, 5663 bool isSigned) { 5664 // First step, figure out the appropriate FP_TO*INT operation to use. 5665 MVT NewOutTy = DestVT; 5666 5667 unsigned OpToUse = 0; 5668 5669 // Scan for the appropriate larger type to use. 5670 while (1) { 5671 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 5672 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 5673 5674 // If the target supports FP_TO_SINT returning this type, use it. 5675 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 5676 default: break; 5677 case TargetLowering::Legal: 5678 if (!TLI.isTypeLegal(NewOutTy)) 5679 break; // Can't use this datatype. 5680 // FALL THROUGH. 5681 case TargetLowering::Custom: 5682 OpToUse = ISD::FP_TO_SINT; 5683 break; 5684 } 5685 if (OpToUse) break; 5686 5687 // If the target supports FP_TO_UINT of this type, use it. 5688 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 5689 default: break; 5690 case TargetLowering::Legal: 5691 if (!TLI.isTypeLegal(NewOutTy)) 5692 break; // Can't use this datatype. 5693 // FALL THROUGH. 5694 case TargetLowering::Custom: 5695 OpToUse = ISD::FP_TO_UINT; 5696 break; 5697 } 5698 if (OpToUse) break; 5699 5700 // Otherwise, try a larger type. 5701 } 5702 5703 5704 // Okay, we found the operation and type to use. 5705 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 5706 5707 // If the operation produces an invalid type, it must be custom lowered. Use 5708 // the target lowering hooks to expand it. Just keep the low part of the 5709 // expanded operation, we know that we're truncating anyway. 5710 if (getTypeAction(NewOutTy) == Expand) { 5711 Operation = SDValue(TLI.ReplaceNodeResults(Operation.getNode(), DAG), 0); 5712 assert(Operation.getNode() && "Didn't return anything"); 5713 } 5714 5715 // Truncate the result of the extended FP_TO_*INT operation to the desired 5716 // size. 5717 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 5718} 5719 5720/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 5721/// 5722SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) { 5723 MVT VT = Op.getValueType(); 5724 MVT SHVT = TLI.getShiftAmountTy(); 5725 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 5726 switch (VT.getSimpleVT()) { 5727 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 5728 case MVT::i16: 5729 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5730 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5731 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 5732 case MVT::i32: 5733 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5734 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5735 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5736 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5737 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 5738 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 5739 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5740 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5741 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5742 case MVT::i64: 5743 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 5744 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 5745 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 5746 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 5747 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 5748 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 5749 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 5750 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 5751 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 5752 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 5753 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 5754 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 5755 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 5756 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 5757 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 5758 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 5759 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 5760 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 5761 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 5762 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 5763 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 5764 } 5765} 5766 5767/// ExpandBitCount - Expand the specified bitcount instruction into operations. 5768/// 5769SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) { 5770 switch (Opc) { 5771 default: assert(0 && "Cannot expand this yet!"); 5772 case ISD::CTPOP: { 5773 static const uint64_t mask[6] = { 5774 0x5555555555555555ULL, 0x3333333333333333ULL, 5775 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 5776 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 5777 }; 5778 MVT VT = Op.getValueType(); 5779 MVT ShVT = TLI.getShiftAmountTy(); 5780 unsigned len = VT.getSizeInBits(); 5781 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5782 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 5783 SDValue Tmp2 = DAG.getConstant(mask[i], VT); 5784 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5785 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 5786 DAG.getNode(ISD::AND, VT, 5787 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 5788 } 5789 return Op; 5790 } 5791 case ISD::CTLZ: { 5792 // for now, we do this: 5793 // x = x | (x >> 1); 5794 // x = x | (x >> 2); 5795 // ... 5796 // x = x | (x >>16); 5797 // x = x | (x >>32); // for 64-bit input 5798 // return popcount(~x); 5799 // 5800 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 5801 MVT VT = Op.getValueType(); 5802 MVT ShVT = TLI.getShiftAmountTy(); 5803 unsigned len = VT.getSizeInBits(); 5804 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 5805 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 5806 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 5807 } 5808 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 5809 return DAG.getNode(ISD::CTPOP, VT, Op); 5810 } 5811 case ISD::CTTZ: { 5812 // for now, we use: { return popcount(~x & (x - 1)); } 5813 // unless the target has ctlz but not ctpop, in which case we use: 5814 // { return 32 - nlz(~x & (x-1)); } 5815 // see also http://www.hackersdelight.org/HDcode/ntz.cc 5816 MVT VT = Op.getValueType(); 5817 SDValue Tmp2 = DAG.getConstant(~0ULL, VT); 5818 SDValue Tmp3 = DAG.getNode(ISD::AND, VT, 5819 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 5820 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 5821 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 5822 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 5823 TLI.isOperationLegal(ISD::CTLZ, VT)) 5824 return DAG.getNode(ISD::SUB, VT, 5825 DAG.getConstant(VT.getSizeInBits(), VT), 5826 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 5827 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 5828 } 5829 } 5830} 5831 5832/// ExpandOp - Expand the specified SDValue into its two component pieces 5833/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 5834/// LegalizeNodes map is filled in for any results that are not expanded, the 5835/// ExpandedNodes map is filled in for any results that are expanded, and the 5836/// Lo/Hi values are returned. 5837void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ 5838 MVT VT = Op.getValueType(); 5839 MVT NVT = TLI.getTypeToTransformTo(VT); 5840 SDNode *Node = Op.getNode(); 5841 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 5842 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || 5843 VT.isVector()) && "Cannot expand to FP value or to larger int value!"); 5844 5845 // See if we already expanded it. 5846 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I 5847 = ExpandedNodes.find(Op); 5848 if (I != ExpandedNodes.end()) { 5849 Lo = I->second.first; 5850 Hi = I->second.second; 5851 return; 5852 } 5853 5854 switch (Node->getOpcode()) { 5855 case ISD::CopyFromReg: 5856 assert(0 && "CopyFromReg must be legal!"); 5857 case ISD::FP_ROUND_INREG: 5858 if (VT == MVT::ppcf128 && 5859 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 5860 TargetLowering::Custom) { 5861 SDValue SrcLo, SrcHi, Src; 5862 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 5863 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 5864 SDValue Result = TLI.LowerOperation( 5865 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 5866 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR); 5867 Lo = Result.getNode()->getOperand(0); 5868 Hi = Result.getNode()->getOperand(1); 5869 break; 5870 } 5871 // fall through 5872 default: 5873#ifndef NDEBUG 5874 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 5875#endif 5876 assert(0 && "Do not know how to expand this operator!"); 5877 abort(); 5878 case ISD::EXTRACT_ELEMENT: 5879 ExpandOp(Node->getOperand(0), Lo, Hi); 5880 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) 5881 return ExpandOp(Hi, Lo, Hi); 5882 return ExpandOp(Lo, Lo, Hi); 5883 case ISD::EXTRACT_VECTOR_ELT: 5884 assert(VT==MVT::i64 && "Do not know how to expand this operator!"); 5885 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 5886 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 5887 return ExpandOp(Lo, Lo, Hi); 5888 case ISD::UNDEF: 5889 Lo = DAG.getNode(ISD::UNDEF, NVT); 5890 Hi = DAG.getNode(ISD::UNDEF, NVT); 5891 break; 5892 case ISD::Constant: { 5893 unsigned NVTBits = NVT.getSizeInBits(); 5894 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 5895 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 5896 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 5897 break; 5898 } 5899 case ISD::ConstantFP: { 5900 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 5901 if (CFP->getValueType(0) == MVT::ppcf128) { 5902 APInt api = CFP->getValueAPF().convertToAPInt(); 5903 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 5904 MVT::f64); 5905 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 5906 MVT::f64); 5907 break; 5908 } 5909 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 5910 if (getTypeAction(Lo.getValueType()) == Expand) 5911 ExpandOp(Lo, Lo, Hi); 5912 break; 5913 } 5914 case ISD::BUILD_PAIR: 5915 // Return the operands. 5916 Lo = Node->getOperand(0); 5917 Hi = Node->getOperand(1); 5918 break; 5919 5920 case ISD::MERGE_VALUES: 5921 if (Node->getNumValues() == 1) { 5922 ExpandOp(Op.getOperand(0), Lo, Hi); 5923 break; 5924 } 5925 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 5926 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 && 5927 Op.getValue(1).getValueType() == MVT::Other && 5928 "unhandled MERGE_VALUES"); 5929 ExpandOp(Op.getOperand(0), Lo, Hi); 5930 // Remember that we legalized the chain. 5931 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 5932 break; 5933 5934 case ISD::SIGN_EXTEND_INREG: 5935 ExpandOp(Node->getOperand(0), Lo, Hi); 5936 // sext_inreg the low part if needed. 5937 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 5938 5939 // The high part gets the sign extension from the lo-part. This handles 5940 // things like sextinreg V:i64 from i8. 5941 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 5942 DAG.getConstant(NVT.getSizeInBits()-1, 5943 TLI.getShiftAmountTy())); 5944 break; 5945 5946 case ISD::BSWAP: { 5947 ExpandOp(Node->getOperand(0), Lo, Hi); 5948 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 5949 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 5950 Lo = TempLo; 5951 break; 5952 } 5953 5954 case ISD::CTPOP: 5955 ExpandOp(Node->getOperand(0), Lo, Hi); 5956 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 5957 DAG.getNode(ISD::CTPOP, NVT, Lo), 5958 DAG.getNode(ISD::CTPOP, NVT, Hi)); 5959 Hi = DAG.getConstant(0, NVT); 5960 break; 5961 5962 case ISD::CTLZ: { 5963 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 5964 ExpandOp(Node->getOperand(0), Lo, Hi); 5965 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 5966 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 5967 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, 5968 ISD::SETNE); 5969 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 5970 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 5971 5972 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 5973 Hi = DAG.getConstant(0, NVT); 5974 break; 5975 } 5976 5977 case ISD::CTTZ: { 5978 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 5979 ExpandOp(Node->getOperand(0), Lo, Hi); 5980 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 5981 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 5982 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, 5983 ISD::SETNE); 5984 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 5985 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 5986 5987 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 5988 Hi = DAG.getConstant(0, NVT); 5989 break; 5990 } 5991 5992 case ISD::VAARG: { 5993 SDValue Ch = Node->getOperand(0); // Legalize the chain. 5994 SDValue Ptr = Node->getOperand(1); // Legalize the pointer. 5995 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 5996 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 5997 5998 // Remember that we legalized the chain. 5999 Hi = LegalizeOp(Hi); 6000 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 6001 if (TLI.isBigEndian()) 6002 std::swap(Lo, Hi); 6003 break; 6004 } 6005 6006 case ISD::LOAD: { 6007 LoadSDNode *LD = cast<LoadSDNode>(Node); 6008 SDValue Ch = LD->getChain(); // Legalize the chain. 6009 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer. 6010 ISD::LoadExtType ExtType = LD->getExtensionType(); 6011 const Value *SV = LD->getSrcValue(); 6012 int SVOffset = LD->getSrcValueOffset(); 6013 unsigned Alignment = LD->getAlignment(); 6014 bool isVolatile = LD->isVolatile(); 6015 6016 if (ExtType == ISD::NON_EXTLOAD) { 6017 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset, 6018 isVolatile, Alignment); 6019 if (VT == MVT::f32 || VT == MVT::f64) { 6020 // f32->i32 or f64->i64 one to one expansion. 6021 // Remember that we legalized the chain. 6022 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 6023 // Recursively expand the new load. 6024 if (getTypeAction(NVT) == Expand) 6025 ExpandOp(Lo, Lo, Hi); 6026 break; 6027 } 6028 6029 // Increment the pointer to the other half. 6030 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 6031 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6032 DAG.getIntPtrConstant(IncrementSize)); 6033 SVOffset += IncrementSize; 6034 Alignment = MinAlign(Alignment, IncrementSize); 6035 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset, 6036 isVolatile, Alignment); 6037 6038 // Build a factor node to remember that this load is independent of the 6039 // other one. 6040 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6041 Hi.getValue(1)); 6042 6043 // Remember that we legalized the chain. 6044 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6045 if (TLI.isBigEndian()) 6046 std::swap(Lo, Hi); 6047 } else { 6048 MVT EVT = LD->getMemoryVT(); 6049 6050 if ((VT == MVT::f64 && EVT == MVT::f32) || 6051 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 6052 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 6053 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV, 6054 SVOffset, isVolatile, Alignment); 6055 // Remember that we legalized the chain. 6056 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1))); 6057 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 6058 break; 6059 } 6060 6061 if (EVT == NVT) 6062 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, 6063 SVOffset, isVolatile, Alignment); 6064 else 6065 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV, 6066 SVOffset, EVT, isVolatile, 6067 Alignment); 6068 6069 // Remember that we legalized the chain. 6070 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 6071 6072 if (ExtType == ISD::SEXTLOAD) { 6073 // The high part is obtained by SRA'ing all but one of the bits of the 6074 // lo part. 6075 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6076 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6077 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6078 } else if (ExtType == ISD::ZEXTLOAD) { 6079 // The high part is just a zero. 6080 Hi = DAG.getConstant(0, NVT); 6081 } else /* if (ExtType == ISD::EXTLOAD) */ { 6082 // The high part is undefined. 6083 Hi = DAG.getNode(ISD::UNDEF, NVT); 6084 } 6085 } 6086 break; 6087 } 6088 case ISD::AND: 6089 case ISD::OR: 6090 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6091 SDValue LL, LH, RL, RH; 6092 ExpandOp(Node->getOperand(0), LL, LH); 6093 ExpandOp(Node->getOperand(1), RL, RH); 6094 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 6095 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 6096 break; 6097 } 6098 case ISD::SELECT: { 6099 SDValue LL, LH, RL, RH; 6100 ExpandOp(Node->getOperand(1), LL, LH); 6101 ExpandOp(Node->getOperand(2), RL, RH); 6102 if (getTypeAction(NVT) == Expand) 6103 NVT = TLI.getTypeToExpandTo(NVT); 6104 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 6105 if (VT != MVT::f32) 6106 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 6107 break; 6108 } 6109 case ISD::SELECT_CC: { 6110 SDValue TL, TH, FL, FH; 6111 ExpandOp(Node->getOperand(2), TL, TH); 6112 ExpandOp(Node->getOperand(3), FL, FH); 6113 if (getTypeAction(NVT) == Expand) 6114 NVT = TLI.getTypeToExpandTo(NVT); 6115 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6116 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6117 if (VT != MVT::f32) 6118 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6119 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6120 break; 6121 } 6122 case ISD::ANY_EXTEND: 6123 // The low part is any extension of the input (which degenerates to a copy). 6124 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 6125 // The high part is undefined. 6126 Hi = DAG.getNode(ISD::UNDEF, NVT); 6127 break; 6128 case ISD::SIGN_EXTEND: { 6129 // The low part is just a sign extension of the input (which degenerates to 6130 // a copy). 6131 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 6132 6133 // The high part is obtained by SRA'ing all but one of the bits of the lo 6134 // part. 6135 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6136 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6137 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6138 break; 6139 } 6140 case ISD::ZERO_EXTEND: 6141 // The low part is just a zero extension of the input (which degenerates to 6142 // a copy). 6143 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 6144 6145 // The high part is just a zero. 6146 Hi = DAG.getConstant(0, NVT); 6147 break; 6148 6149 case ISD::TRUNCATE: { 6150 // The input value must be larger than this value. Expand *it*. 6151 SDValue NewLo; 6152 ExpandOp(Node->getOperand(0), NewLo, Hi); 6153 6154 // The low part is now either the right size, or it is closer. If not the 6155 // right size, make an illegal truncate so we recursively expand it. 6156 if (NewLo.getValueType() != Node->getValueType(0)) 6157 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 6158 ExpandOp(NewLo, Lo, Hi); 6159 break; 6160 } 6161 6162 case ISD::BIT_CONVERT: { 6163 SDValue Tmp; 6164 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6165 // If the target wants to, allow it to lower this itself. 6166 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6167 case Expand: assert(0 && "cannot expand FP!"); 6168 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6169 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6170 } 6171 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 6172 } 6173 6174 // f32 / f64 must be expanded to i32 / i64. 6175 if (VT == MVT::f32 || VT == MVT::f64) { 6176 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6177 if (getTypeAction(NVT) == Expand) 6178 ExpandOp(Lo, Lo, Hi); 6179 break; 6180 } 6181 6182 // If source operand will be expanded to the same type as VT, i.e. 6183 // i64 <- f64, i32 <- f32, expand the source operand instead. 6184 MVT VT0 = Node->getOperand(0).getValueType(); 6185 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6186 ExpandOp(Node->getOperand(0), Lo, Hi); 6187 break; 6188 } 6189 6190 // Turn this into a load/store pair by default. 6191 if (Tmp.getNode() == 0) 6192 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 6193 6194 ExpandOp(Tmp, Lo, Hi); 6195 break; 6196 } 6197 6198 case ISD::READCYCLECOUNTER: { 6199 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6200 TargetLowering::Custom && 6201 "Must custom expand ReadCycleCounter"); 6202 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6203 assert(Tmp.getNode() && "Node must be custom expanded!"); 6204 ExpandOp(Tmp.getValue(0), Lo, Hi); 6205 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6206 LegalizeOp(Tmp.getValue(1))); 6207 break; 6208 } 6209 6210 // FIXME: should the LOAD_BIN and SWAP atomics get here too? Probably. 6211 case ISD::ATOMIC_CMP_SWAP_8: 6212 case ISD::ATOMIC_CMP_SWAP_16: 6213 case ISD::ATOMIC_CMP_SWAP_32: 6214 case ISD::ATOMIC_CMP_SWAP_64: { 6215 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6216 assert(Tmp.getNode() && "Node must be custom expanded!"); 6217 ExpandOp(Tmp.getValue(0), Lo, Hi); 6218 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6219 LegalizeOp(Tmp.getValue(1))); 6220 break; 6221 } 6222 6223 6224 6225 // These operators cannot be expanded directly, emit them as calls to 6226 // library functions. 6227 case ISD::FP_TO_SINT: { 6228 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6229 SDValue Op; 6230 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6231 case Expand: assert(0 && "cannot expand FP!"); 6232 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6233 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6234 } 6235 6236 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6237 6238 // Now that the custom expander is done, expand the result, which is still 6239 // VT. 6240 if (Op.getNode()) { 6241 ExpandOp(Op, Lo, Hi); 6242 break; 6243 } 6244 } 6245 6246 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(), 6247 VT); 6248 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!"); 6249 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6250 break; 6251 } 6252 6253 case ISD::FP_TO_UINT: { 6254 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6255 SDValue Op; 6256 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6257 case Expand: assert(0 && "cannot expand FP!"); 6258 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6259 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6260 } 6261 6262 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6263 6264 // Now that the custom expander is done, expand the result. 6265 if (Op.getNode()) { 6266 ExpandOp(Op, Lo, Hi); 6267 break; 6268 } 6269 } 6270 6271 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(), 6272 VT); 6273 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 6274 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6275 break; 6276 } 6277 6278 case ISD::SHL: { 6279 // If the target wants custom lowering, do so. 6280 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6281 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6282 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6283 Op = TLI.LowerOperation(Op, DAG); 6284 if (Op.getNode()) { 6285 // Now that the custom expander is done, expand the result, which is 6286 // still VT. 6287 ExpandOp(Op, Lo, Hi); 6288 break; 6289 } 6290 } 6291 6292 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6293 // this X << 1 as X+X. 6294 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6295 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 6296 TLI.isOperationLegal(ISD::ADDE, NVT)) { 6297 SDValue LoOps[2], HiOps[3]; 6298 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6299 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6300 LoOps[1] = LoOps[0]; 6301 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6302 6303 HiOps[1] = HiOps[0]; 6304 HiOps[2] = Lo.getValue(1); 6305 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6306 break; 6307 } 6308 } 6309 6310 // If we can emit an efficient shift operation, do so now. 6311 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6312 break; 6313 6314 // If this target supports SHL_PARTS, use it. 6315 TargetLowering::LegalizeAction Action = 6316 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6317 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6318 Action == TargetLowering::Custom) { 6319 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6320 break; 6321 } 6322 6323 // Otherwise, emit a libcall. 6324 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6325 break; 6326 } 6327 6328 case ISD::SRA: { 6329 // If the target wants custom lowering, do so. 6330 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6331 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6332 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6333 Op = TLI.LowerOperation(Op, DAG); 6334 if (Op.getNode()) { 6335 // Now that the custom expander is done, expand the result, which is 6336 // still VT. 6337 ExpandOp(Op, Lo, Hi); 6338 break; 6339 } 6340 } 6341 6342 // If we can emit an efficient shift operation, do so now. 6343 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6344 break; 6345 6346 // If this target supports SRA_PARTS, use it. 6347 TargetLowering::LegalizeAction Action = 6348 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6349 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6350 Action == TargetLowering::Custom) { 6351 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6352 break; 6353 } 6354 6355 // Otherwise, emit a libcall. 6356 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6357 break; 6358 } 6359 6360 case ISD::SRL: { 6361 // If the target wants custom lowering, do so. 6362 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6363 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6364 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6365 Op = TLI.LowerOperation(Op, DAG); 6366 if (Op.getNode()) { 6367 // Now that the custom expander is done, expand the result, which is 6368 // still VT. 6369 ExpandOp(Op, Lo, Hi); 6370 break; 6371 } 6372 } 6373 6374 // If we can emit an efficient shift operation, do so now. 6375 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6376 break; 6377 6378 // If this target supports SRL_PARTS, use it. 6379 TargetLowering::LegalizeAction Action = 6380 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6381 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6382 Action == TargetLowering::Custom) { 6383 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6384 break; 6385 } 6386 6387 // Otherwise, emit a libcall. 6388 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6389 break; 6390 } 6391 6392 case ISD::ADD: 6393 case ISD::SUB: { 6394 // If the target wants to custom expand this, let them. 6395 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6396 TargetLowering::Custom) { 6397 SDValue Result = TLI.LowerOperation(Op, DAG); 6398 if (Result.getNode()) { 6399 ExpandOp(Result, Lo, Hi); 6400 break; 6401 } 6402 } 6403 6404 // Expand the subcomponents. 6405 SDValue LHSL, LHSH, RHSL, RHSH; 6406 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6407 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6408 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6409 SDValue LoOps[2], HiOps[3]; 6410 LoOps[0] = LHSL; 6411 LoOps[1] = RHSL; 6412 HiOps[0] = LHSH; 6413 HiOps[1] = RHSH; 6414 if (Node->getOpcode() == ISD::ADD) { 6415 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6416 HiOps[2] = Lo.getValue(1); 6417 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6418 } else { 6419 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6420 HiOps[2] = Lo.getValue(1); 6421 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6422 } 6423 break; 6424 } 6425 6426 case ISD::ADDC: 6427 case ISD::SUBC: { 6428 // Expand the subcomponents. 6429 SDValue LHSL, LHSH, RHSL, RHSH; 6430 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6431 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6432 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6433 SDValue LoOps[2] = { LHSL, RHSL }; 6434 SDValue HiOps[3] = { LHSH, RHSH }; 6435 6436 if (Node->getOpcode() == ISD::ADDC) { 6437 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6438 HiOps[2] = Lo.getValue(1); 6439 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6440 } else { 6441 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6442 HiOps[2] = Lo.getValue(1); 6443 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6444 } 6445 // Remember that we legalized the flag. 6446 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6447 break; 6448 } 6449 case ISD::ADDE: 6450 case ISD::SUBE: { 6451 // Expand the subcomponents. 6452 SDValue LHSL, LHSH, RHSL, RHSH; 6453 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6454 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6455 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6456 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 6457 SDValue HiOps[3] = { LHSH, RHSH }; 6458 6459 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 6460 HiOps[2] = Lo.getValue(1); 6461 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 6462 6463 // Remember that we legalized the flag. 6464 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 6465 break; 6466 } 6467 case ISD::MUL: { 6468 // If the target wants to custom expand this, let them. 6469 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 6470 SDValue New = TLI.LowerOperation(Op, DAG); 6471 if (New.getNode()) { 6472 ExpandOp(New, Lo, Hi); 6473 break; 6474 } 6475 } 6476 6477 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 6478 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 6479 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 6480 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 6481 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 6482 SDValue LL, LH, RL, RH; 6483 ExpandOp(Node->getOperand(0), LL, LH); 6484 ExpandOp(Node->getOperand(1), RL, RH); 6485 unsigned OuterBitSize = Op.getValueSizeInBits(); 6486 unsigned InnerBitSize = RH.getValueSizeInBits(); 6487 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 6488 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 6489 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 6490 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 6491 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 6492 // The inputs are both zero-extended. 6493 if (HasUMUL_LOHI) { 6494 // We can emit a umul_lohi. 6495 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6496 Hi = SDValue(Lo.getNode(), 1); 6497 break; 6498 } 6499 if (HasMULHU) { 6500 // We can emit a mulhu+mul. 6501 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6502 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6503 break; 6504 } 6505 } 6506 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 6507 // The input values are both sign-extended. 6508 if (HasSMUL_LOHI) { 6509 // We can emit a smul_lohi. 6510 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 6511 Hi = SDValue(Lo.getNode(), 1); 6512 break; 6513 } 6514 if (HasMULHS) { 6515 // We can emit a mulhs+mul. 6516 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6517 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 6518 break; 6519 } 6520 } 6521 if (HasUMUL_LOHI) { 6522 // Lo,Hi = umul LHS, RHS. 6523 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 6524 DAG.getVTList(NVT, NVT), LL, RL); 6525 Lo = UMulLOHI; 6526 Hi = UMulLOHI.getValue(1); 6527 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6528 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6529 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6530 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6531 break; 6532 } 6533 if (HasMULHU) { 6534 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 6535 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 6536 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 6537 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 6538 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 6539 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 6540 break; 6541 } 6542 } 6543 6544 // If nothing else, we can make a libcall. 6545 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 6546 break; 6547 } 6548 case ISD::SDIV: 6549 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 6550 break; 6551 case ISD::UDIV: 6552 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 6553 break; 6554 case ISD::SREM: 6555 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 6556 break; 6557 case ISD::UREM: 6558 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 6559 break; 6560 6561 case ISD::FADD: 6562 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 6563 RTLIB::ADD_F64, 6564 RTLIB::ADD_F80, 6565 RTLIB::ADD_PPCF128), 6566 Node, false, Hi); 6567 break; 6568 case ISD::FSUB: 6569 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 6570 RTLIB::SUB_F64, 6571 RTLIB::SUB_F80, 6572 RTLIB::SUB_PPCF128), 6573 Node, false, Hi); 6574 break; 6575 case ISD::FMUL: 6576 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 6577 RTLIB::MUL_F64, 6578 RTLIB::MUL_F80, 6579 RTLIB::MUL_PPCF128), 6580 Node, false, Hi); 6581 break; 6582 case ISD::FDIV: 6583 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 6584 RTLIB::DIV_F64, 6585 RTLIB::DIV_F80, 6586 RTLIB::DIV_PPCF128), 6587 Node, false, Hi); 6588 break; 6589 case ISD::FP_EXTEND: { 6590 if (VT == MVT::ppcf128) { 6591 assert(Node->getOperand(0).getValueType()==MVT::f32 || 6592 Node->getOperand(0).getValueType()==MVT::f64); 6593 const uint64_t zero = 0; 6594 if (Node->getOperand(0).getValueType()==MVT::f32) 6595 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 6596 else 6597 Hi = Node->getOperand(0); 6598 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6599 break; 6600 } 6601 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT); 6602 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!"); 6603 Lo = ExpandLibCall(LC, Node, true, Hi); 6604 break; 6605 } 6606 case ISD::FP_ROUND: { 6607 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(), 6608 VT); 6609 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!"); 6610 Lo = ExpandLibCall(LC, Node, true, Hi); 6611 break; 6612 } 6613 case ISD::FSQRT: 6614 case ISD::FSIN: 6615 case ISD::FCOS: 6616 case ISD::FLOG: 6617 case ISD::FLOG2: 6618 case ISD::FLOG10: 6619 case ISD::FEXP: 6620 case ISD::FEXP2: 6621 case ISD::FTRUNC: 6622 case ISD::FFLOOR: 6623 case ISD::FCEIL: 6624 case ISD::FRINT: 6625 case ISD::FNEARBYINT: 6626 case ISD::FPOW: 6627 case ISD::FPOWI: { 6628 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 6629 switch(Node->getOpcode()) { 6630 case ISD::FSQRT: 6631 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 6632 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 6633 break; 6634 case ISD::FSIN: 6635 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 6636 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 6637 break; 6638 case ISD::FCOS: 6639 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 6640 RTLIB::COS_F80, RTLIB::COS_PPCF128); 6641 break; 6642 case ISD::FLOG: 6643 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64, 6644 RTLIB::LOG_F80, RTLIB::LOG_PPCF128); 6645 break; 6646 case ISD::FLOG2: 6647 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 6648 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128); 6649 break; 6650 case ISD::FLOG10: 6651 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 6652 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128); 6653 break; 6654 case ISD::FEXP: 6655 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64, 6656 RTLIB::EXP_F80, RTLIB::EXP_PPCF128); 6657 break; 6658 case ISD::FEXP2: 6659 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 6660 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128); 6661 break; 6662 case ISD::FTRUNC: 6663 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 6664 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 6665 break; 6666 case ISD::FFLOOR: 6667 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 6668 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 6669 break; 6670 case ISD::FCEIL: 6671 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 6672 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 6673 break; 6674 case ISD::FRINT: 6675 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 6676 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 6677 break; 6678 case ISD::FNEARBYINT: 6679 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 6680 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 6681 break; 6682 case ISD::FPOW: 6683 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 6684 RTLIB::POW_PPCF128); 6685 break; 6686 case ISD::FPOWI: 6687 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80, 6688 RTLIB::POWI_PPCF128); 6689 break; 6690 default: assert(0 && "Unreachable!"); 6691 } 6692 Lo = ExpandLibCall(LC, Node, false, Hi); 6693 break; 6694 } 6695 case ISD::FABS: { 6696 if (VT == MVT::ppcf128) { 6697 SDValue Tmp; 6698 ExpandOp(Node->getOperand(0), Lo, Tmp); 6699 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 6700 // lo = hi==fabs(hi) ? lo : -lo; 6701 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 6702 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 6703 DAG.getCondCode(ISD::SETEQ)); 6704 break; 6705 } 6706 SDValue Mask = (VT == MVT::f64) 6707 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 6708 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 6709 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6710 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6711 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 6712 if (getTypeAction(NVT) == Expand) 6713 ExpandOp(Lo, Lo, Hi); 6714 break; 6715 } 6716 case ISD::FNEG: { 6717 if (VT == MVT::ppcf128) { 6718 ExpandOp(Node->getOperand(0), Lo, Hi); 6719 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 6720 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 6721 break; 6722 } 6723 SDValue Mask = (VT == MVT::f64) 6724 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 6725 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 6726 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 6727 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6728 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 6729 if (getTypeAction(NVT) == Expand) 6730 ExpandOp(Lo, Lo, Hi); 6731 break; 6732 } 6733 case ISD::FCOPYSIGN: { 6734 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 6735 if (getTypeAction(NVT) == Expand) 6736 ExpandOp(Lo, Lo, Hi); 6737 break; 6738 } 6739 case ISD::SINT_TO_FP: 6740 case ISD::UINT_TO_FP: { 6741 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 6742 MVT SrcVT = Node->getOperand(0).getValueType(); 6743 6744 // Promote the operand if needed. Do this before checking for 6745 // ppcf128 so conversions of i16 and i8 work. 6746 if (getTypeAction(SrcVT) == Promote) { 6747 SDValue Tmp = PromoteOp(Node->getOperand(0)); 6748 Tmp = isSigned 6749 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 6750 DAG.getValueType(SrcVT)) 6751 : DAG.getZeroExtendInReg(Tmp, SrcVT); 6752 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode(); 6753 SrcVT = Node->getOperand(0).getValueType(); 6754 } 6755 6756 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 6757 static const uint64_t zero = 0; 6758 if (isSigned) { 6759 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6760 Node->getOperand(0))); 6761 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6762 } else { 6763 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 6764 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 6765 Node->getOperand(0))); 6766 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 6767 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6768 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 6769 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6770 DAG.getConstant(0, MVT::i32), 6771 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6772 DAG.getConstantFP( 6773 APFloat(APInt(128, 2, TwoE32)), 6774 MVT::ppcf128)), 6775 Hi, 6776 DAG.getCondCode(ISD::SETLT)), 6777 Lo, Hi); 6778 } 6779 break; 6780 } 6781 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 6782 // si64->ppcf128 done by libcall, below 6783 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 6784 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 6785 Lo, Hi); 6786 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 6787 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 6788 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 6789 DAG.getConstant(0, MVT::i64), 6790 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 6791 DAG.getConstantFP( 6792 APFloat(APInt(128, 2, TwoE64)), 6793 MVT::ppcf128)), 6794 Hi, 6795 DAG.getCondCode(ISD::SETLT)), 6796 Lo, Hi); 6797 break; 6798 } 6799 6800 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 6801 Node->getOperand(0)); 6802 if (getTypeAction(Lo.getValueType()) == Expand) 6803 // float to i32 etc. can be 'expanded' to a single node. 6804 ExpandOp(Lo, Lo, Hi); 6805 break; 6806 } 6807 } 6808 6809 // Make sure the resultant values have been legalized themselves, unless this 6810 // is a type that requires multi-step expansion. 6811 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 6812 Lo = LegalizeOp(Lo); 6813 if (Hi.getNode()) 6814 // Don't legalize the high part if it is expanded to a single node. 6815 Hi = LegalizeOp(Hi); 6816 } 6817 6818 // Remember in a map if the values will be reused later. 6819 bool isNew = 6820 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 6821 assert(isNew && "Value already expanded?!?"); 6822} 6823 6824/// SplitVectorOp - Given an operand of vector type, break it down into 6825/// two smaller values, still of vector type. 6826void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo, 6827 SDValue &Hi) { 6828 assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); 6829 SDNode *Node = Op.getNode(); 6830 unsigned NumElements = Op.getValueType().getVectorNumElements(); 6831 assert(NumElements > 1 && "Cannot split a single element vector!"); 6832 6833 MVT NewEltVT = Op.getValueType().getVectorElementType(); 6834 6835 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 6836 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 6837 6838 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); 6839 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); 6840 6841 // See if we already split it. 6842 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I 6843 = SplitNodes.find(Op); 6844 if (I != SplitNodes.end()) { 6845 Lo = I->second.first; 6846 Hi = I->second.second; 6847 return; 6848 } 6849 6850 switch (Node->getOpcode()) { 6851 default: 6852#ifndef NDEBUG 6853 Node->dump(&DAG); 6854#endif 6855 assert(0 && "Unhandled operation in SplitVectorOp!"); 6856 case ISD::UNDEF: 6857 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 6858 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 6859 break; 6860 case ISD::BUILD_PAIR: 6861 Lo = Node->getOperand(0); 6862 Hi = Node->getOperand(1); 6863 break; 6864 case ISD::INSERT_VECTOR_ELT: { 6865 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 6866 SplitVectorOp(Node->getOperand(0), Lo, Hi); 6867 unsigned Index = Idx->getZExtValue(); 6868 SDValue ScalarOp = Node->getOperand(1); 6869 if (Index < NewNumElts_Lo) 6870 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 6871 DAG.getIntPtrConstant(Index)); 6872 else 6873 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 6874 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 6875 break; 6876 } 6877 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 6878 Node->getOperand(1), 6879 Node->getOperand(2)); 6880 SplitVectorOp(Tmp, Lo, Hi); 6881 break; 6882 } 6883 case ISD::VECTOR_SHUFFLE: { 6884 // Build the low part. 6885 SDValue Mask = Node->getOperand(2); 6886 SmallVector<SDValue, 8> Ops; 6887 MVT PtrVT = TLI.getPointerTy(); 6888 6889 // Insert all of the elements from the input that are needed. We use 6890 // buildvector of extractelement here because the input vectors will have 6891 // to be legalized, so this makes the code simpler. 6892 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 6893 SDValue IdxNode = Mask.getOperand(i); 6894 if (IdxNode.getOpcode() == ISD::UNDEF) { 6895 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6896 continue; 6897 } 6898 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); 6899 SDValue InVec = Node->getOperand(0); 6900 if (Idx >= NumElements) { 6901 InVec = Node->getOperand(1); 6902 Idx -= NumElements; 6903 } 6904 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6905 DAG.getConstant(Idx, PtrVT))); 6906 } 6907 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 6908 Ops.clear(); 6909 6910 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 6911 SDValue IdxNode = Mask.getOperand(i); 6912 if (IdxNode.getOpcode() == ISD::UNDEF) { 6913 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 6914 continue; 6915 } 6916 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); 6917 SDValue InVec = Node->getOperand(0); 6918 if (Idx >= NumElements) { 6919 InVec = Node->getOperand(1); 6920 Idx -= NumElements; 6921 } 6922 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 6923 DAG.getConstant(Idx, PtrVT))); 6924 } 6925 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size()); 6926 break; 6927 } 6928 case ISD::BUILD_VECTOR: { 6929 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 6930 Node->op_begin()+NewNumElts_Lo); 6931 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 6932 6933 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 6934 Node->op_end()); 6935 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 6936 break; 6937 } 6938 case ISD::CONCAT_VECTORS: { 6939 // FIXME: Handle non-power-of-two vectors? 6940 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 6941 if (NewNumSubvectors == 1) { 6942 Lo = Node->getOperand(0); 6943 Hi = Node->getOperand(1); 6944 } else { 6945 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 6946 Node->op_begin()+NewNumSubvectors); 6947 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 6948 6949 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors, 6950 Node->op_end()); 6951 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 6952 } 6953 break; 6954 } 6955 case ISD::SELECT: { 6956 SDValue Cond = Node->getOperand(0); 6957 6958 SDValue LL, LH, RL, RH; 6959 SplitVectorOp(Node->getOperand(1), LL, LH); 6960 SplitVectorOp(Node->getOperand(2), RL, RH); 6961 6962 if (Cond.getValueType().isVector()) { 6963 // Handle a vector merge. 6964 SDValue CL, CH; 6965 SplitVectorOp(Cond, CL, CH); 6966 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 6967 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 6968 } else { 6969 // Handle a simple select with vector operands. 6970 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 6971 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 6972 } 6973 break; 6974 } 6975 case ISD::SELECT_CC: { 6976 SDValue CondLHS = Node->getOperand(0); 6977 SDValue CondRHS = Node->getOperand(1); 6978 SDValue CondCode = Node->getOperand(4); 6979 6980 SDValue LL, LH, RL, RH; 6981 SplitVectorOp(Node->getOperand(2), LL, LH); 6982 SplitVectorOp(Node->getOperand(3), RL, RH); 6983 6984 // Handle a simple select with vector operands. 6985 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS, 6986 LL, RL, CondCode); 6987 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS, 6988 LH, RH, CondCode); 6989 break; 6990 } 6991 case ISD::VSETCC: { 6992 SDValue LL, LH, RL, RH; 6993 SplitVectorOp(Node->getOperand(0), LL, LH); 6994 SplitVectorOp(Node->getOperand(1), RL, RH); 6995 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2)); 6996 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2)); 6997 break; 6998 } 6999 case ISD::ADD: 7000 case ISD::SUB: 7001 case ISD::MUL: 7002 case ISD::FADD: 7003 case ISD::FSUB: 7004 case ISD::FMUL: 7005 case ISD::SDIV: 7006 case ISD::UDIV: 7007 case ISD::FDIV: 7008 case ISD::FPOW: 7009 case ISD::AND: 7010 case ISD::OR: 7011 case ISD::XOR: 7012 case ISD::UREM: 7013 case ISD::SREM: 7014 case ISD::FREM: { 7015 SDValue LL, LH, RL, RH; 7016 SplitVectorOp(Node->getOperand(0), LL, LH); 7017 SplitVectorOp(Node->getOperand(1), RL, RH); 7018 7019 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 7020 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 7021 break; 7022 } 7023 case ISD::FP_ROUND: 7024 case ISD::FPOWI: { 7025 SDValue L, H; 7026 SplitVectorOp(Node->getOperand(0), L, H); 7027 7028 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 7029 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 7030 break; 7031 } 7032 case ISD::CTTZ: 7033 case ISD::CTLZ: 7034 case ISD::CTPOP: 7035 case ISD::FNEG: 7036 case ISD::FABS: 7037 case ISD::FSQRT: 7038 case ISD::FSIN: 7039 case ISD::FCOS: 7040 case ISD::FLOG: 7041 case ISD::FLOG2: 7042 case ISD::FLOG10: 7043 case ISD::FEXP: 7044 case ISD::FEXP2: 7045 case ISD::FP_TO_SINT: 7046 case ISD::FP_TO_UINT: 7047 case ISD::SINT_TO_FP: 7048 case ISD::UINT_TO_FP: 7049 case ISD::TRUNCATE: 7050 case ISD::ANY_EXTEND: 7051 case ISD::SIGN_EXTEND: 7052 case ISD::ZERO_EXTEND: 7053 case ISD::FP_EXTEND: { 7054 SDValue L, H; 7055 SplitVectorOp(Node->getOperand(0), L, H); 7056 7057 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 7058 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 7059 break; 7060 } 7061 case ISD::LOAD: { 7062 LoadSDNode *LD = cast<LoadSDNode>(Node); 7063 SDValue Ch = LD->getChain(); 7064 SDValue Ptr = LD->getBasePtr(); 7065 ISD::LoadExtType ExtType = LD->getExtensionType(); 7066 const Value *SV = LD->getSrcValue(); 7067 int SVOffset = LD->getSrcValueOffset(); 7068 MVT MemoryVT = LD->getMemoryVT(); 7069 unsigned Alignment = LD->getAlignment(); 7070 bool isVolatile = LD->isVolatile(); 7071 7072 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7073 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); 7074 7075 MVT MemNewEltVT = MemoryVT.getVectorElementType(); 7076 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo); 7077 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi); 7078 7079 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, 7080 NewVT_Lo, Ch, Ptr, Offset, 7081 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment); 7082 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8; 7083 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 7084 DAG.getIntPtrConstant(IncrementSize)); 7085 SVOffset += IncrementSize; 7086 Alignment = MinAlign(Alignment, IncrementSize); 7087 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, 7088 NewVT_Hi, Ch, Ptr, Offset, 7089 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment); 7090 7091 // Build a factor node to remember that this load is independent of the 7092 // other one. 7093 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 7094 Hi.getValue(1)); 7095 7096 // Remember that we legalized the chain. 7097 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 7098 break; 7099 } 7100 case ISD::BIT_CONVERT: { 7101 // We know the result is a vector. The input may be either a vector or a 7102 // scalar value. 7103 SDValue InOp = Node->getOperand(0); 7104 if (!InOp.getValueType().isVector() || 7105 InOp.getValueType().getVectorNumElements() == 1) { 7106 // The input is a scalar or single-element vector. 7107 // Lower to a store/load so that it can be split. 7108 // FIXME: this could be improved probably. 7109 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment( 7110 Op.getValueType().getTypeForMVT()); 7111 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign); 7112 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex(); 7113 7114 SDValue St = DAG.getStore(DAG.getEntryNode(), 7115 InOp, Ptr, 7116 PseudoSourceValue::getFixedStack(FI), 0); 7117 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 7118 PseudoSourceValue::getFixedStack(FI), 0); 7119 } 7120 // Split the vector and convert each of the pieces now. 7121 SplitVectorOp(InOp, Lo, Hi); 7122 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 7123 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 7124 break; 7125 } 7126 } 7127 7128 // Remember in a map if the values will be reused later. 7129 bool isNew = 7130 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7131 assert(isNew && "Value already split?!?"); 7132} 7133 7134 7135/// ScalarizeVectorOp - Given an operand of single-element vector type 7136/// (e.g. v1f32), convert it into the equivalent operation that returns a 7137/// scalar (e.g. f32) value. 7138SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) { 7139 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); 7140 SDNode *Node = Op.getNode(); 7141 MVT NewVT = Op.getValueType().getVectorElementType(); 7142 assert(Op.getValueType().getVectorNumElements() == 1); 7143 7144 // See if we already scalarized it. 7145 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op); 7146 if (I != ScalarizedNodes.end()) return I->second; 7147 7148 SDValue Result; 7149 switch (Node->getOpcode()) { 7150 default: 7151#ifndef NDEBUG 7152 Node->dump(&DAG); cerr << "\n"; 7153#endif 7154 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7155 case ISD::ADD: 7156 case ISD::FADD: 7157 case ISD::SUB: 7158 case ISD::FSUB: 7159 case ISD::MUL: 7160 case ISD::FMUL: 7161 case ISD::SDIV: 7162 case ISD::UDIV: 7163 case ISD::FDIV: 7164 case ISD::SREM: 7165 case ISD::UREM: 7166 case ISD::FREM: 7167 case ISD::FPOW: 7168 case ISD::AND: 7169 case ISD::OR: 7170 case ISD::XOR: 7171 Result = DAG.getNode(Node->getOpcode(), 7172 NewVT, 7173 ScalarizeVectorOp(Node->getOperand(0)), 7174 ScalarizeVectorOp(Node->getOperand(1))); 7175 break; 7176 case ISD::FNEG: 7177 case ISD::FABS: 7178 case ISD::FSQRT: 7179 case ISD::FSIN: 7180 case ISD::FCOS: 7181 case ISD::FLOG: 7182 case ISD::FLOG2: 7183 case ISD::FLOG10: 7184 case ISD::FEXP: 7185 case ISD::FEXP2: 7186 case ISD::FP_TO_SINT: 7187 case ISD::FP_TO_UINT: 7188 case ISD::SINT_TO_FP: 7189 case ISD::UINT_TO_FP: 7190 case ISD::SIGN_EXTEND: 7191 case ISD::ZERO_EXTEND: 7192 case ISD::ANY_EXTEND: 7193 case ISD::TRUNCATE: 7194 case ISD::FP_EXTEND: 7195 Result = DAG.getNode(Node->getOpcode(), 7196 NewVT, 7197 ScalarizeVectorOp(Node->getOperand(0))); 7198 break; 7199 case ISD::FPOWI: 7200 case ISD::FP_ROUND: 7201 Result = DAG.getNode(Node->getOpcode(), 7202 NewVT, 7203 ScalarizeVectorOp(Node->getOperand(0)), 7204 Node->getOperand(1)); 7205 break; 7206 case ISD::LOAD: { 7207 LoadSDNode *LD = cast<LoadSDNode>(Node); 7208 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7209 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7210 ISD::LoadExtType ExtType = LD->getExtensionType(); 7211 const Value *SV = LD->getSrcValue(); 7212 int SVOffset = LD->getSrcValueOffset(); 7213 MVT MemoryVT = LD->getMemoryVT(); 7214 unsigned Alignment = LD->getAlignment(); 7215 bool isVolatile = LD->isVolatile(); 7216 7217 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7218 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); 7219 7220 Result = DAG.getLoad(ISD::UNINDEXED, ExtType, 7221 NewVT, Ch, Ptr, Offset, SV, SVOffset, 7222 MemoryVT.getVectorElementType(), 7223 isVolatile, Alignment); 7224 7225 // Remember that we legalized the chain. 7226 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7227 break; 7228 } 7229 case ISD::BUILD_VECTOR: 7230 Result = Node->getOperand(0); 7231 break; 7232 case ISD::INSERT_VECTOR_ELT: 7233 // Returning the inserted scalar element. 7234 Result = Node->getOperand(1); 7235 break; 7236 case ISD::CONCAT_VECTORS: 7237 assert(Node->getOperand(0).getValueType() == NewVT && 7238 "Concat of non-legal vectors not yet supported!"); 7239 Result = Node->getOperand(0); 7240 break; 7241 case ISD::VECTOR_SHUFFLE: { 7242 // Figure out if the scalar is the LHS or RHS and return it. 7243 SDValue EltNum = Node->getOperand(2).getOperand(0); 7244 if (cast<ConstantSDNode>(EltNum)->getZExtValue()) 7245 Result = ScalarizeVectorOp(Node->getOperand(1)); 7246 else 7247 Result = ScalarizeVectorOp(Node->getOperand(0)); 7248 break; 7249 } 7250 case ISD::EXTRACT_SUBVECTOR: 7251 Result = Node->getOperand(0); 7252 assert(Result.getValueType() == NewVT); 7253 break; 7254 case ISD::BIT_CONVERT: { 7255 SDValue Op0 = Op.getOperand(0); 7256 if (Op0.getValueType().getVectorNumElements() == 1) 7257 Op0 = ScalarizeVectorOp(Op0); 7258 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); 7259 break; 7260 } 7261 case ISD::SELECT: 7262 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 7263 ScalarizeVectorOp(Op.getOperand(1)), 7264 ScalarizeVectorOp(Op.getOperand(2))); 7265 break; 7266 case ISD::SELECT_CC: 7267 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0), 7268 Node->getOperand(1), 7269 ScalarizeVectorOp(Op.getOperand(2)), 7270 ScalarizeVectorOp(Op.getOperand(3)), 7271 Node->getOperand(4)); 7272 break; 7273 case ISD::VSETCC: { 7274 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0)); 7275 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1)); 7276 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1, 7277 Op.getOperand(2)); 7278 Result = DAG.getNode(ISD::SELECT, NewVT, Result, 7279 DAG.getConstant(-1ULL, NewVT), 7280 DAG.getConstant(0ULL, NewVT)); 7281 break; 7282 } 7283 } 7284 7285 if (TLI.isTypeLegal(NewVT)) 7286 Result = LegalizeOp(Result); 7287 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7288 assert(isNew && "Value already scalarized?"); 7289 return Result; 7290} 7291 7292 7293// SelectionDAG::Legalize - This is the entry point for the file. 7294// 7295void SelectionDAG::Legalize() { 7296 /// run - This is the main entry point to this class. 7297 /// 7298 SelectionDAGLegalize(*this).LegalizeDAG(); 7299} 7300 7301