LegalizeDAG.cpp revision fd6673cf7fd5c0c1e6817e5fcf460a289712ee57
1//===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::Legalize method. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/SelectionDAG.h" 15#include "llvm/CodeGen/MachineFunction.h" 16#include "llvm/CodeGen/MachineFrameInfo.h" 17#include "llvm/CodeGen/MachineJumpTableInfo.h" 18#include "llvm/CodeGen/MachineModuleInfo.h" 19#include "llvm/CodeGen/PseudoSourceValue.h" 20#include "llvm/Target/TargetFrameInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetData.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/Target/TargetSubtarget.h" 26#include "llvm/CallingConv.h" 27#include "llvm/Constants.h" 28#include "llvm/DerivedTypes.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Compiler.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/ADT/DenseMap.h" 33#include "llvm/ADT/SmallVector.h" 34#include "llvm/ADT/SmallPtrSet.h" 35#include <map> 36using namespace llvm; 37 38//===----------------------------------------------------------------------===// 39/// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 40/// hacks on it until the target machine can handle it. This involves 41/// eliminating value sizes the machine cannot handle (promoting small sizes to 42/// large sizes or splitting up large values into small values) as well as 43/// eliminating operations the machine cannot handle. 44/// 45/// This code also does a small amount of optimization and recognition of idioms 46/// as part of its processing. For example, if a target does not support a 47/// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 48/// will attempt merge setcc and brc instructions into brcc's. 49/// 50namespace { 51class VISIBILITY_HIDDEN SelectionDAGLegalize { 52 TargetLowering &TLI; 53 SelectionDAG &DAG; 54 55 // Libcall insertion helpers. 56 57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been 58 /// legalized. We use this to ensure that calls are properly serialized 59 /// against each other, including inserted libcalls. 60 SDValue LastCALLSEQ_END; 61 62 /// IsLegalizingCall - This member is used *only* for purposes of providing 63 /// helpful assertions that a libcall isn't created while another call is 64 /// being legalized (which could lead to non-serialized call sequences). 65 bool IsLegalizingCall; 66 67 enum LegalizeAction { 68 Legal, // The target natively supports this operation. 69 Promote, // This operation should be executed in a larger type. 70 Expand // Try to expand this to other ops, otherwise use a libcall. 71 }; 72 73 /// ValueTypeActions - This is a bitvector that contains two bits for each 74 /// value type, where the two bits correspond to the LegalizeAction enum. 75 /// This can be queried with "getTypeAction(VT)". 76 TargetLowering::ValueTypeActionImpl ValueTypeActions; 77 78 /// LegalizedNodes - For nodes that are of legal width, and that have more 79 /// than one use, this map indicates what regularized operand to use. This 80 /// allows us to avoid legalizing the same thing more than once. 81 DenseMap<SDValue, SDValue> LegalizedNodes; 82 83 /// PromotedNodes - For nodes that are below legal width, and that have more 84 /// than one use, this map indicates what promoted value to use. This allows 85 /// us to avoid promoting the same thing more than once. 86 DenseMap<SDValue, SDValue> PromotedNodes; 87 88 /// ExpandedNodes - For nodes that need to be expanded this map indicates 89 /// which operands are the expanded version of the input. This allows 90 /// us to avoid expanding the same node more than once. 91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes; 92 93 /// SplitNodes - For vector nodes that need to be split, this map indicates 94 /// which operands are the split version of the input. This allows us 95 /// to avoid splitting the same node more than once. 96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes; 97 98 /// ScalarizedNodes - For nodes that need to be converted from vector types to 99 /// scalar types, this contains the mapping of ones we have already 100 /// processed to the result. 101 std::map<SDValue, SDValue> ScalarizedNodes; 102 103 /// WidenNodes - For nodes that need to be widened from one vector type to 104 /// another, this contains the mapping of those that we have already widen. 105 /// This allows us to avoid widening more than once. 106 std::map<SDValue, SDValue> WidenNodes; 107 108 void AddLegalizedOperand(SDValue From, SDValue To) { 109 LegalizedNodes.insert(std::make_pair(From, To)); 110 // If someone requests legalization of the new node, return itself. 111 if (From != To) 112 LegalizedNodes.insert(std::make_pair(To, To)); 113 } 114 void AddPromotedOperand(SDValue From, SDValue To) { 115 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second; 116 assert(isNew && "Got into the map somehow?"); 117 isNew = isNew; 118 // If someone requests legalization of the new node, return itself. 119 LegalizedNodes.insert(std::make_pair(To, To)); 120 } 121 void AddWidenedOperand(SDValue From, SDValue To) { 122 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second; 123 assert(isNew && "Got into the map somehow?"); 124 isNew = isNew; 125 // If someone requests legalization of the new node, return itself. 126 LegalizedNodes.insert(std::make_pair(To, To)); 127 } 128 129public: 130 explicit SelectionDAGLegalize(SelectionDAG &DAG); 131 132 /// getTypeAction - Return how we should legalize values of this type, either 133 /// it is already legal or we need to expand it into multiple registers of 134 /// smaller integer type, or we need to promote it to a larger type. 135 LegalizeAction getTypeAction(MVT VT) const { 136 return (LegalizeAction)ValueTypeActions.getTypeAction(VT); 137 } 138 139 /// isTypeLegal - Return true if this type is legal on this target. 140 /// 141 bool isTypeLegal(MVT VT) const { 142 return getTypeAction(VT) == Legal; 143 } 144 145 void LegalizeDAG(); 146 147private: 148 /// HandleOp - Legalize, Promote, or Expand the specified operand as 149 /// appropriate for its type. 150 void HandleOp(SDValue Op); 151 152 /// LegalizeOp - We know that the specified value has a legal type. 153 /// Recursively ensure that the operands have legal types, then return the 154 /// result. 155 SDValue LegalizeOp(SDValue O); 156 157 /// UnrollVectorOp - We know that the given vector has a legal type, however 158 /// the operation it performs is not legal and is an operation that we have 159 /// no way of lowering. "Unroll" the vector, splitting out the scalars and 160 /// operating on each element individually. 161 SDValue UnrollVectorOp(SDValue O); 162 163 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 164 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 165 /// is necessary to spill the vector being inserted into to memory, perform 166 /// the insert there, and then read the result back. 167 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 168 SDValue Idx); 169 170 /// PromoteOp - Given an operation that produces a value in an invalid type, 171 /// promote it to compute the value into a larger type. The produced value 172 /// will have the correct bits for the low portion of the register, but no 173 /// guarantee is made about the top bits: it may be zero, sign-extended, or 174 /// garbage. 175 SDValue PromoteOp(SDValue O); 176 177 /// ExpandOp - Expand the specified SDValue into its two component pieces 178 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, 179 /// the LegalizedNodes map is filled in for any results that are not expanded, 180 /// the ExpandedNodes map is filled in for any results that are expanded, and 181 /// the Lo/Hi values are returned. This applies to integer types and Vector 182 /// types. 183 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi); 184 185 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT 186 /// (e.g., v3i32 to v4i32). The produced value will have the correct value 187 /// for the existing elements but no guarantee is made about the new elements 188 /// at the end of the vector: it may be zero, ones, or garbage. This is useful 189 /// when we have an instruction operating on an illegal vector type and we 190 /// want to widen it to do the computation on a legal wider vector type. 191 SDValue WidenVectorOp(SDValue Op, MVT WidenVT); 192 193 /// SplitVectorOp - Given an operand of vector type, break it down into 194 /// two smaller values. 195 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi); 196 197 /// ScalarizeVectorOp - Given an operand of single-element vector type 198 /// (e.g. v1f32), convert it into the equivalent operation that returns a 199 /// scalar (e.g. f32) value. 200 SDValue ScalarizeVectorOp(SDValue O); 201 202 /// Useful 16 element vector type that is used to pass operands for widening. 203 typedef SmallVector<SDValue, 16> SDValueVector; 204 205 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if 206 /// the LdChain contains a single load and false if it contains a token 207 /// factor for multiple loads. It takes 208 /// Result: location to return the result 209 /// LdChain: location to return the load chain 210 /// Op: load operation to widen 211 /// NVT: widen vector result type we want for the load 212 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain, 213 SDValue Op, MVT NVT); 214 215 /// Helper genWidenVectorLoads - Helper function to generate a set of 216 /// loads to load a vector with a resulting wider type. It takes 217 /// LdChain: list of chains for the load we have generated 218 /// Chain: incoming chain for the ld vector 219 /// BasePtr: base pointer to load from 220 /// SV: memory disambiguation source value 221 /// SVOffset: memory disambiugation offset 222 /// Alignment: alignment of the memory 223 /// isVolatile: volatile load 224 /// LdWidth: width of memory that we want to load 225 /// ResType: the wider result result type for the resulting loaded vector 226 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain, 227 SDValue BasePtr, const Value *SV, 228 int SVOffset, unsigned Alignment, 229 bool isVolatile, unsigned LdWidth, 230 MVT ResType); 231 232 /// StoreWidenVectorOp - Stores a widen vector into non widen memory 233 /// location. It takes 234 /// ST: store node that we want to replace 235 /// Chain: incoming store chain 236 /// BasePtr: base address of where we want to store into 237 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain, 238 SDValue BasePtr); 239 240 /// Helper genWidenVectorStores - Helper function to generate a set of 241 /// stores to store a widen vector into non widen memory 242 // It takes 243 // StChain: list of chains for the stores we have generated 244 // Chain: incoming chain for the ld vector 245 // BasePtr: base pointer to load from 246 // SV: memory disambiguation source value 247 // SVOffset: memory disambiugation offset 248 // Alignment: alignment of the memory 249 // isVolatile: volatile lod 250 // ValOp: value to store 251 // StWidth: width of memory that we want to store 252 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain, 253 SDValue BasePtr, const Value *SV, 254 int SVOffset, unsigned Alignment, 255 bool isVolatile, SDValue ValOp, 256 unsigned StWidth); 257 258 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the 259 /// specified mask and type. Targets can specify exactly which masks they 260 /// support and the code generator is tasked with not creating illegal masks. 261 /// 262 /// Note that this will also return true for shuffles that are promoted to a 263 /// different type. 264 /// 265 /// If this is a legal shuffle, this method returns the (possibly promoted) 266 /// build_vector Mask. If it's not a legal shuffle, it returns null. 267 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const; 268 269 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 270 SmallPtrSet<SDNode*, 32> &NodesLeadingTo); 271 272 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC); 273 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC); 274 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) { 275 LegalizeSetCCOperands(LHS, RHS, CC); 276 LegalizeSetCCCondCode(VT, LHS, RHS, CC); 277 } 278 279 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned, 280 SDValue &Hi); 281 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source); 282 283 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT); 284 SDValue ExpandBUILD_VECTOR(SDNode *Node); 285 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 286 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op); 287 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT); 288 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned); 289 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned); 290 291 SDValue ExpandBSWAP(SDValue Op); 292 SDValue ExpandBitCount(unsigned Opc, SDValue Op); 293 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt, 294 SDValue &Lo, SDValue &Hi); 295 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt, 296 SDValue &Lo, SDValue &Hi); 297 298 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op); 299 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op); 300 301 // Returns the legalized (truncated or extended) shift amount. 302 SDValue LegalizeShiftAmount(SDValue ShiftAmt); 303}; 304} 305 306/// isVectorShuffleLegal - Return true if a vector shuffle is legal with the 307/// specified mask and type. Targets can specify exactly which masks they 308/// support and the code generator is tasked with not creating illegal masks. 309/// 310/// Note that this will also return true for shuffles that are promoted to a 311/// different type. 312SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const { 313 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) { 314 default: return 0; 315 case TargetLowering::Legal: 316 case TargetLowering::Custom: 317 break; 318 case TargetLowering::Promote: { 319 // If this is promoted to a different type, convert the shuffle mask and 320 // ask if it is legal in the promoted type! 321 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT); 322 MVT EltVT = NVT.getVectorElementType(); 323 324 // If we changed # elements, change the shuffle mask. 325 unsigned NumEltsGrowth = 326 NVT.getVectorNumElements() / VT.getVectorNumElements(); 327 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 328 if (NumEltsGrowth > 1) { 329 // Renumber the elements. 330 SmallVector<SDValue, 8> Ops; 331 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) { 332 SDValue InOp = Mask.getOperand(i); 333 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 334 if (InOp.getOpcode() == ISD::UNDEF) 335 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 336 else { 337 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue(); 338 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT)); 339 } 340 } 341 } 342 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size()); 343 } 344 VT = NVT; 345 break; 346 } 347 } 348 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0; 349} 350 351SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 352 : TLI(dag.getTargetLoweringInfo()), DAG(dag), 353 ValueTypeActions(TLI.getValueTypeActions()) { 354 assert(MVT::LAST_VALUETYPE <= 32 && 355 "Too many value types for ValueTypeActions to hold!"); 356} 357 358void SelectionDAGLegalize::LegalizeDAG() { 359 LastCALLSEQ_END = DAG.getEntryNode(); 360 IsLegalizingCall = false; 361 362 // The legalize process is inherently a bottom-up recursive process (users 363 // legalize their uses before themselves). Given infinite stack space, we 364 // could just start legalizing on the root and traverse the whole graph. In 365 // practice however, this causes us to run out of stack space on large basic 366 // blocks. To avoid this problem, compute an ordering of the nodes where each 367 // node is only legalized after all of its operands are legalized. 368 DAG.AssignTopologicalOrder(); 369 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 370 E = prior(DAG.allnodes_end()); I != next(E); ++I) 371 HandleOp(SDValue(I, 0)); 372 373 // Finally, it's possible the root changed. Get the new root. 374 SDValue OldRoot = DAG.getRoot(); 375 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 376 DAG.setRoot(LegalizedNodes[OldRoot]); 377 378 ExpandedNodes.clear(); 379 LegalizedNodes.clear(); 380 PromotedNodes.clear(); 381 SplitNodes.clear(); 382 ScalarizedNodes.clear(); 383 WidenNodes.clear(); 384 385 // Remove dead nodes now. 386 DAG.RemoveDeadNodes(); 387} 388 389 390/// FindCallEndFromCallStart - Given a chained node that is part of a call 391/// sequence, find the CALLSEQ_END node that terminates the call sequence. 392static SDNode *FindCallEndFromCallStart(SDNode *Node) { 393 if (Node->getOpcode() == ISD::CALLSEQ_END) 394 return Node; 395 if (Node->use_empty()) 396 return 0; // No CallSeqEnd 397 398 // The chain is usually at the end. 399 SDValue TheChain(Node, Node->getNumValues()-1); 400 if (TheChain.getValueType() != MVT::Other) { 401 // Sometimes it's at the beginning. 402 TheChain = SDValue(Node, 0); 403 if (TheChain.getValueType() != MVT::Other) { 404 // Otherwise, hunt for it. 405 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) 406 if (Node->getValueType(i) == MVT::Other) { 407 TheChain = SDValue(Node, i); 408 break; 409 } 410 411 // Otherwise, we walked into a node without a chain. 412 if (TheChain.getValueType() != MVT::Other) 413 return 0; 414 } 415 } 416 417 for (SDNode::use_iterator UI = Node->use_begin(), 418 E = Node->use_end(); UI != E; ++UI) { 419 420 // Make sure to only follow users of our token chain. 421 SDNode *User = *UI; 422 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) 423 if (User->getOperand(i) == TheChain) 424 if (SDNode *Result = FindCallEndFromCallStart(User)) 425 return Result; 426 } 427 return 0; 428} 429 430/// FindCallStartFromCallEnd - Given a chained node that is part of a call 431/// sequence, find the CALLSEQ_START node that initiates the call sequence. 432static SDNode *FindCallStartFromCallEnd(SDNode *Node) { 433 assert(Node && "Didn't find callseq_start for a call??"); 434 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; 435 436 assert(Node->getOperand(0).getValueType() == MVT::Other && 437 "Node doesn't have a token chain argument!"); 438 return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); 439} 440 441/// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to 442/// see if any uses can reach Dest. If no dest operands can get to dest, 443/// legalize them, legalize ourself, and return false, otherwise, return true. 444/// 445/// Keep track of the nodes we fine that actually do lead to Dest in 446/// NodesLeadingTo. This avoids retraversing them exponential number of times. 447/// 448bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, 449 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) { 450 if (N == Dest) return true; // N certainly leads to Dest :) 451 452 // If we've already processed this node and it does lead to Dest, there is no 453 // need to reprocess it. 454 if (NodesLeadingTo.count(N)) return true; 455 456 // If the first result of this node has been already legalized, then it cannot 457 // reach N. 458 switch (getTypeAction(N->getValueType(0))) { 459 case Legal: 460 if (LegalizedNodes.count(SDValue(N, 0))) return false; 461 break; 462 case Promote: 463 if (PromotedNodes.count(SDValue(N, 0))) return false; 464 break; 465 case Expand: 466 if (ExpandedNodes.count(SDValue(N, 0))) return false; 467 break; 468 } 469 470 // Okay, this node has not already been legalized. Check and legalize all 471 // operands. If none lead to Dest, then we can legalize this node. 472 bool OperandsLeadToDest = false; 473 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 474 OperandsLeadToDest |= // If an operand leads to Dest, so do we. 475 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo); 476 477 if (OperandsLeadToDest) { 478 NodesLeadingTo.insert(N); 479 return true; 480 } 481 482 // Okay, this node looks safe, legalize it and return false. 483 HandleOp(SDValue(N, 0)); 484 return false; 485} 486 487/// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as 488/// appropriate for its type. 489void SelectionDAGLegalize::HandleOp(SDValue Op) { 490 MVT VT = Op.getValueType(); 491 switch (getTypeAction(VT)) { 492 default: assert(0 && "Bad type action!"); 493 case Legal: (void)LegalizeOp(Op); break; 494 case Promote: 495 if (!VT.isVector()) { 496 (void)PromoteOp(Op); 497 break; 498 } 499 else { 500 // See if we can widen otherwise use Expand to either scalarize or split 501 MVT WidenVT = TLI.getWidenVectorType(VT); 502 if (WidenVT != MVT::Other) { 503 (void) WidenVectorOp(Op, WidenVT); 504 break; 505 } 506 // else fall thru to expand since we can't widen the vector 507 } 508 case Expand: 509 if (!VT.isVector()) { 510 // If this is an illegal scalar, expand it into its two component 511 // pieces. 512 SDValue X, Y; 513 if (Op.getOpcode() == ISD::TargetConstant) 514 break; // Allow illegal target nodes. 515 ExpandOp(Op, X, Y); 516 } else if (VT.getVectorNumElements() == 1) { 517 // If this is an illegal single element vector, convert it to a 518 // scalar operation. 519 (void)ScalarizeVectorOp(Op); 520 } else { 521 // This is an illegal multiple element vector. 522 // Split it in half and legalize both parts. 523 SDValue X, Y; 524 SplitVectorOp(Op, X, Y); 525 } 526 break; 527 } 528} 529 530/// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 531/// a load from the constant pool. 532static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, 533 SelectionDAG &DAG, TargetLowering &TLI) { 534 bool Extend = false; 535 536 // If a FP immediate is precise when represented as a float and if the 537 // target can do an extending load from float to double, we put it into 538 // the constant pool as a float, even if it's is statically typed as a 539 // double. This shrinks FP constants and canonicalizes them for targets where 540 // an FP extending load is the same cost as a normal load (such as on the x87 541 // fp stack or PPC FP unit). 542 MVT VT = CFP->getValueType(0); 543 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 544 if (!UseCP) { 545 if (VT!=MVT::f64 && VT!=MVT::f32) 546 assert(0 && "Invalid type expansion"); 547 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 548 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 549 } 550 551 MVT OrigVT = VT; 552 MVT SVT = VT; 553 while (SVT != MVT::f32) { 554 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); 555 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && 556 // Only do this if the target has a native EXTLOAD instruction from 557 // smaller type. 558 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 559 TLI.ShouldShrinkFPConstant(OrigVT)) { 560 const Type *SType = SVT.getTypeForMVT(); 561 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 562 VT = SVT; 563 Extend = true; 564 } 565 } 566 567 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 568 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 569 if (Extend) 570 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(), 571 CPIdx, PseudoSourceValue::getConstantPool(), 572 0, VT, false, Alignment); 573 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx, 574 PseudoSourceValue::getConstantPool(), 0, false, Alignment); 575} 576 577 578/// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise 579/// operations. 580static 581SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT, 582 SelectionDAG &DAG, TargetLowering &TLI) { 583 MVT VT = Node->getValueType(0); 584 MVT SrcVT = Node->getOperand(1).getValueType(); 585 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) && 586 "fcopysign expansion only supported for f32 and f64"); 587 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32; 588 589 // First get the sign bit of second operand. 590 SDValue Mask1 = (SrcVT == MVT::f64) 591 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT) 592 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT); 593 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1); 594 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1)); 595 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1); 596 // Shift right or sign-extend it if the two operands have different types. 597 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits(); 598 if (SizeDiff > 0) { 599 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit, 600 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy())); 601 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit); 602 } else if (SizeDiff < 0) { 603 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit); 604 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit, 605 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy())); 606 } 607 608 // Clear the sign bit of first operand. 609 SDValue Mask2 = (VT == MVT::f64) 610 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 611 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 612 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2); 613 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 614 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2); 615 616 // Or the value with the sign bit. 617 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit); 618 return Result; 619} 620 621/// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 622static 623SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 624 TargetLowering &TLI) { 625 SDValue Chain = ST->getChain(); 626 SDValue Ptr = ST->getBasePtr(); 627 SDValue Val = ST->getValue(); 628 MVT VT = Val.getValueType(); 629 int Alignment = ST->getAlignment(); 630 int SVOffset = ST->getSrcValueOffset(); 631 if (ST->getMemoryVT().isFloatingPoint() || 632 ST->getMemoryVT().isVector()) { 633 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits()); 634 if (TLI.isTypeLegal(intVT)) { 635 // Expand to a bitconvert of the value to the integer type of the 636 // same size, then a (misaligned) int store. 637 // FIXME: Does not handle truncating floating point stores! 638 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val); 639 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(), 640 SVOffset, ST->isVolatile(), Alignment); 641 } else { 642 // Do a (aligned) store to a stack slot, then copy from the stack slot 643 // to the final destination using (unaligned) integer loads and stores. 644 MVT StoredVT = ST->getMemoryVT(); 645 MVT RegVT = 646 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits())); 647 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 648 unsigned RegBytes = RegVT.getSizeInBits() / 8; 649 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 650 651 // Make sure the stack slot is also aligned for the register type. 652 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 653 654 // Perform the original store, only redirected to the stack slot. 655 SDValue Store = DAG.getTruncStore(Chain, Val, StackPtr, NULL, 0,StoredVT); 656 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 657 SmallVector<SDValue, 8> Stores; 658 unsigned Offset = 0; 659 660 // Do all but one copies using the full register width. 661 for (unsigned i = 1; i < NumRegs; i++) { 662 // Load one integer register's worth from the stack slot. 663 SDValue Load = DAG.getLoad(RegVT, Store, StackPtr, NULL, 0); 664 // Store it to the final location. Remember the store. 665 Stores.push_back(DAG.getStore(Load.getValue(1), Load, Ptr, 666 ST->getSrcValue(), SVOffset + Offset, 667 ST->isVolatile(), 668 MinAlign(ST->getAlignment(), Offset))); 669 // Increment the pointers. 670 Offset += RegBytes; 671 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr, 672 Increment); 673 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment); 674 } 675 676 // The last store may be partial. Do a truncating store. On big-endian 677 // machines this requires an extending load from the stack slot to ensure 678 // that the bits are in the right place. 679 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset)); 680 681 // Load from the stack slot. 682 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Store, StackPtr, 683 NULL, 0, MemVT); 684 685 Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, Ptr, 686 ST->getSrcValue(), SVOffset + Offset, 687 MemVT, ST->isVolatile(), 688 MinAlign(ST->getAlignment(), Offset))); 689 // The order of the stores doesn't matter - say it with a TokenFactor. 690 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], 691 Stores.size()); 692 } 693 } 694 assert(ST->getMemoryVT().isInteger() && 695 !ST->getMemoryVT().isVector() && 696 "Unaligned store of unknown type."); 697 // Get the half-size VT 698 MVT NewStoredVT = 699 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); 700 int NumBits = NewStoredVT.getSizeInBits(); 701 int IncrementSize = NumBits / 8; 702 703 // Divide the stored value in two parts. 704 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 705 SDValue Lo = Val; 706 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount); 707 708 // Store the two parts 709 SDValue Store1, Store2; 710 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr, 711 ST->getSrcValue(), SVOffset, NewStoredVT, 712 ST->isVolatile(), Alignment); 713 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 714 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 715 Alignment = MinAlign(Alignment, IncrementSize); 716 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr, 717 ST->getSrcValue(), SVOffset + IncrementSize, 718 NewStoredVT, ST->isVolatile(), Alignment); 719 720 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2); 721} 722 723/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 724static 725SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 726 TargetLowering &TLI) { 727 int SVOffset = LD->getSrcValueOffset(); 728 SDValue Chain = LD->getChain(); 729 SDValue Ptr = LD->getBasePtr(); 730 MVT VT = LD->getValueType(0); 731 MVT LoadedVT = LD->getMemoryVT(); 732 if (VT.isFloatingPoint() || VT.isVector()) { 733 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits()); 734 if (TLI.isTypeLegal(intVT)) { 735 // Expand to a (misaligned) integer load of the same size, 736 // then bitconvert to floating point or vector. 737 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(), 738 SVOffset, LD->isVolatile(), 739 LD->getAlignment()); 740 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad); 741 if (VT.isFloatingPoint() && LoadedVT != VT) 742 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result); 743 744 SDValue Ops[] = { Result, Chain }; 745 return DAG.getMergeValues(Ops, 2); 746 } else { 747 // Copy the value to a (aligned) stack slot using (unaligned) integer 748 // loads and stores, then do a (aligned) load from the stack slot. 749 MVT RegVT = TLI.getRegisterType(intVT); 750 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 751 unsigned RegBytes = RegVT.getSizeInBits() / 8; 752 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 753 754 // Make sure the stack slot is also aligned for the register type. 755 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 756 757 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 758 SmallVector<SDValue, 8> Stores; 759 SDValue StackPtr = StackBase; 760 unsigned Offset = 0; 761 762 // Do all but one copies using the full register width. 763 for (unsigned i = 1; i < NumRegs; i++) { 764 // Load one integer register's worth from the original location. 765 SDValue Load = DAG.getLoad(RegVT, Chain, Ptr, LD->getSrcValue(), 766 SVOffset + Offset, LD->isVolatile(), 767 MinAlign(LD->getAlignment(), Offset)); 768 // Follow the load with a store to the stack slot. Remember the store. 769 Stores.push_back(DAG.getStore(Load.getValue(1), Load, StackPtr, 770 NULL, 0)); 771 // Increment the pointers. 772 Offset += RegBytes; 773 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment); 774 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr, 775 Increment); 776 } 777 778 // The last copy may be partial. Do an extending load. 779 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset)); 780 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Chain, Ptr, 781 LD->getSrcValue(), SVOffset + Offset, 782 MemVT, LD->isVolatile(), 783 MinAlign(LD->getAlignment(), Offset)); 784 // Follow the load with a store to the stack slot. Remember the store. 785 // On big-endian machines this requires a truncating store to ensure 786 // that the bits end up in the right place. 787 Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, StackPtr, 788 NULL, 0, MemVT)); 789 790 // The order of the stores doesn't matter - say it with a TokenFactor. 791 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0], 792 Stores.size()); 793 794 // Finally, perform the original load only redirected to the stack slot. 795 Load = DAG.getExtLoad(LD->getExtensionType(), VT, TF, StackBase, 796 NULL, 0, LoadedVT); 797 798 // Callers expect a MERGE_VALUES node. 799 SDValue Ops[] = { Load, TF }; 800 return DAG.getMergeValues(Ops, 2); 801 } 802 } 803 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 804 "Unaligned load of unsupported type."); 805 806 // Compute the new VT that is half the size of the old one. This is an 807 // integer MVT. 808 unsigned NumBits = LoadedVT.getSizeInBits(); 809 MVT NewLoadedVT; 810 NewLoadedVT = MVT::getIntegerVT(NumBits/2); 811 NumBits >>= 1; 812 813 unsigned Alignment = LD->getAlignment(); 814 unsigned IncrementSize = NumBits / 8; 815 ISD::LoadExtType HiExtType = LD->getExtensionType(); 816 817 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 818 if (HiExtType == ISD::NON_EXTLOAD) 819 HiExtType = ISD::ZEXTLOAD; 820 821 // Load the value in two parts 822 SDValue Lo, Hi; 823 if (TLI.isLittleEndian()) { 824 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 825 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment); 826 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 827 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 828 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), 829 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 830 MinAlign(Alignment, IncrementSize)); 831 } else { 832 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset, 833 NewLoadedVT,LD->isVolatile(), Alignment); 834 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 835 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 836 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(), 837 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(), 838 MinAlign(Alignment, IncrementSize)); 839 } 840 841 // aggregate the two parts 842 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy()); 843 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount); 844 Result = DAG.getNode(ISD::OR, VT, Result, Lo); 845 846 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 847 Hi.getValue(1)); 848 849 SDValue Ops[] = { Result, TF }; 850 return DAG.getMergeValues(Ops, 2); 851} 852 853/// UnrollVectorOp - We know that the given vector has a legal type, however 854/// the operation it performs is not legal and is an operation that we have 855/// no way of lowering. "Unroll" the vector, splitting out the scalars and 856/// operating on each element individually. 857SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) { 858 MVT VT = Op.getValueType(); 859 assert(isTypeLegal(VT) && 860 "Caller should expand or promote operands that are not legal!"); 861 assert(Op.getNode()->getNumValues() == 1 && 862 "Can't unroll a vector with multiple results!"); 863 unsigned NE = VT.getVectorNumElements(); 864 MVT EltVT = VT.getVectorElementType(); 865 866 SmallVector<SDValue, 8> Scalars; 867 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 868 for (unsigned i = 0; i != NE; ++i) { 869 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 870 SDValue Operand = Op.getOperand(j); 871 MVT OperandVT = Operand.getValueType(); 872 if (OperandVT.isVector()) { 873 // A vector operand; extract a single element. 874 MVT OperandEltVT = OperandVT.getVectorElementType(); 875 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 876 OperandEltVT, 877 Operand, 878 DAG.getConstant(i, MVT::i32)); 879 } else { 880 // A scalar operand; just use it as is. 881 Operands[j] = Operand; 882 } 883 } 884 885 switch (Op.getOpcode()) { 886 default: 887 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, 888 &Operands[0], Operands.size())); 889 break; 890 case ISD::SHL: 891 case ISD::SRA: 892 case ISD::SRL: 893 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, Operands[0], 894 LegalizeShiftAmount(Operands[1]))); 895 break; 896 } 897 } 898 899 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size()); 900} 901 902/// GetFPLibCall - Return the right libcall for the given floating point type. 903static RTLIB::Libcall GetFPLibCall(MVT VT, 904 RTLIB::Libcall Call_F32, 905 RTLIB::Libcall Call_F64, 906 RTLIB::Libcall Call_F80, 907 RTLIB::Libcall Call_PPCF128) { 908 return 909 VT == MVT::f32 ? Call_F32 : 910 VT == MVT::f64 ? Call_F64 : 911 VT == MVT::f80 ? Call_F80 : 912 VT == MVT::ppcf128 ? Call_PPCF128 : 913 RTLIB::UNKNOWN_LIBCALL; 914} 915 916/// PerformInsertVectorEltInMemory - Some target cannot handle a variable 917/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 918/// is necessary to spill the vector being inserted into to memory, perform 919/// the insert there, and then read the result back. 920SDValue SelectionDAGLegalize:: 921PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) { 922 SDValue Tmp1 = Vec; 923 SDValue Tmp2 = Val; 924 SDValue Tmp3 = Idx; 925 926 // If the target doesn't support this, we have to spill the input vector 927 // to a temporary stack slot, update the element, then reload it. This is 928 // badness. We could also load the value into a vector register (either 929 // with a "move to register" or "extload into register" instruction, then 930 // permute it into place, if the idx is a constant and if the idx is 931 // supported by the target. 932 MVT VT = Tmp1.getValueType(); 933 MVT EltVT = VT.getVectorElementType(); 934 MVT IdxVT = Tmp3.getValueType(); 935 MVT PtrVT = TLI.getPointerTy(); 936 SDValue StackPtr = DAG.CreateStackTemporary(VT); 937 938 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 939 940 // Store the vector. 941 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, 942 PseudoSourceValue::getFixedStack(SPFI), 0); 943 944 // Truncate or zero extend offset to target pointer type. 945 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 946 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3); 947 // Add the offset to the index. 948 unsigned EltSize = EltVT.getSizeInBits()/8; 949 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 950 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr); 951 // Store the scalar value. 952 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2, 953 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT); 954 // Load the updated vector. 955 return DAG.getLoad(VT, Ch, StackPtr, 956 PseudoSourceValue::getFixedStack(SPFI), 0); 957} 958 959SDValue SelectionDAGLegalize::LegalizeShiftAmount(SDValue ShiftAmt) { 960 if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType())) 961 return DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt); 962 963 if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType())) 964 return DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt); 965 966 return ShiftAmt; 967} 968 969 970/// LegalizeOp - We know that the specified value has a legal type, and 971/// that its operands are legal. Now ensure that the operation itself 972/// is legal, recursively ensuring that the operands' operations remain 973/// legal. 974SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { 975 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 976 return Op; 977 978 assert(isTypeLegal(Op.getValueType()) && 979 "Caller should expand or promote operands that are not legal!"); 980 SDNode *Node = Op.getNode(); 981 982 // If this operation defines any values that cannot be represented in a 983 // register on this target, make sure to expand or promote them. 984 if (Node->getNumValues() > 1) { 985 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 986 if (getTypeAction(Node->getValueType(i)) != Legal) { 987 HandleOp(Op.getValue(i)); 988 assert(LegalizedNodes.count(Op) && 989 "Handling didn't add legal operands!"); 990 return LegalizedNodes[Op]; 991 } 992 } 993 994 // Note that LegalizeOp may be reentered even from single-use nodes, which 995 // means that we always must cache transformed nodes. 996 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 997 if (I != LegalizedNodes.end()) return I->second; 998 999 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 1000 SDValue Result = Op; 1001 bool isCustom = false; 1002 1003 switch (Node->getOpcode()) { 1004 case ISD::FrameIndex: 1005 case ISD::EntryToken: 1006 case ISD::Register: 1007 case ISD::BasicBlock: 1008 case ISD::TargetFrameIndex: 1009 case ISD::TargetJumpTable: 1010 case ISD::TargetConstant: 1011 case ISD::TargetConstantFP: 1012 case ISD::TargetConstantPool: 1013 case ISD::TargetGlobalAddress: 1014 case ISD::TargetGlobalTLSAddress: 1015 case ISD::TargetExternalSymbol: 1016 case ISD::VALUETYPE: 1017 case ISD::SRCVALUE: 1018 case ISD::MEMOPERAND: 1019 case ISD::CONDCODE: 1020 case ISD::ARG_FLAGS: 1021 // Primitives must all be legal. 1022 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 1023 "This must be legal!"); 1024 break; 1025 default: 1026 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 1027 // If this is a target node, legalize it by legalizing the operands then 1028 // passing it through. 1029 SmallVector<SDValue, 8> Ops; 1030 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1031 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1032 1033 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size()); 1034 1035 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1036 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 1037 return Result.getValue(Op.getResNo()); 1038 } 1039 // Otherwise this is an unhandled builtin node. splat. 1040#ifndef NDEBUG 1041 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 1042#endif 1043 assert(0 && "Do not know how to legalize this operator!"); 1044 abort(); 1045 case ISD::GLOBAL_OFFSET_TABLE: 1046 case ISD::GlobalAddress: 1047 case ISD::GlobalTLSAddress: 1048 case ISD::ExternalSymbol: 1049 case ISD::ConstantPool: 1050 case ISD::JumpTable: // Nothing to do. 1051 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1052 default: assert(0 && "This action is not supported yet!"); 1053 case TargetLowering::Custom: 1054 Tmp1 = TLI.LowerOperation(Op, DAG); 1055 if (Tmp1.getNode()) Result = Tmp1; 1056 // FALLTHROUGH if the target doesn't want to lower this op after all. 1057 case TargetLowering::Legal: 1058 break; 1059 } 1060 break; 1061 case ISD::FRAMEADDR: 1062 case ISD::RETURNADDR: 1063 // The only option for these nodes is to custom lower them. If the target 1064 // does not custom lower them, then return zero. 1065 Tmp1 = TLI.LowerOperation(Op, DAG); 1066 if (Tmp1.getNode()) 1067 Result = Tmp1; 1068 else 1069 Result = DAG.getConstant(0, TLI.getPointerTy()); 1070 break; 1071 case ISD::FRAME_TO_ARGS_OFFSET: { 1072 MVT VT = Node->getValueType(0); 1073 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1074 default: assert(0 && "This action is not supported yet!"); 1075 case TargetLowering::Custom: 1076 Result = TLI.LowerOperation(Op, DAG); 1077 if (Result.getNode()) break; 1078 // Fall Thru 1079 case TargetLowering::Legal: 1080 Result = DAG.getConstant(0, VT); 1081 break; 1082 } 1083 } 1084 break; 1085 case ISD::EXCEPTIONADDR: { 1086 Tmp1 = LegalizeOp(Node->getOperand(0)); 1087 MVT VT = Node->getValueType(0); 1088 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1089 default: assert(0 && "This action is not supported yet!"); 1090 case TargetLowering::Expand: { 1091 unsigned Reg = TLI.getExceptionAddressRegister(); 1092 Result = DAG.getCopyFromReg(Tmp1, Reg, VT); 1093 } 1094 break; 1095 case TargetLowering::Custom: 1096 Result = TLI.LowerOperation(Op, DAG); 1097 if (Result.getNode()) break; 1098 // Fall Thru 1099 case TargetLowering::Legal: { 1100 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 }; 1101 Result = DAG.getMergeValues(Ops, 2); 1102 break; 1103 } 1104 } 1105 } 1106 if (Result.getNode()->getNumValues() == 1) break; 1107 1108 assert(Result.getNode()->getNumValues() == 2 && 1109 "Cannot return more than two values!"); 1110 1111 // Since we produced two values, make sure to remember that we 1112 // legalized both of them. 1113 Tmp1 = LegalizeOp(Result); 1114 Tmp2 = LegalizeOp(Result.getValue(1)); 1115 AddLegalizedOperand(Op.getValue(0), Tmp1); 1116 AddLegalizedOperand(Op.getValue(1), Tmp2); 1117 return Op.getResNo() ? Tmp2 : Tmp1; 1118 case ISD::EHSELECTION: { 1119 Tmp1 = LegalizeOp(Node->getOperand(0)); 1120 Tmp2 = LegalizeOp(Node->getOperand(1)); 1121 MVT VT = Node->getValueType(0); 1122 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1123 default: assert(0 && "This action is not supported yet!"); 1124 case TargetLowering::Expand: { 1125 unsigned Reg = TLI.getExceptionSelectorRegister(); 1126 Result = DAG.getCopyFromReg(Tmp2, Reg, VT); 1127 } 1128 break; 1129 case TargetLowering::Custom: 1130 Result = TLI.LowerOperation(Op, DAG); 1131 if (Result.getNode()) break; 1132 // Fall Thru 1133 case TargetLowering::Legal: { 1134 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 }; 1135 Result = DAG.getMergeValues(Ops, 2); 1136 break; 1137 } 1138 } 1139 } 1140 if (Result.getNode()->getNumValues() == 1) break; 1141 1142 assert(Result.getNode()->getNumValues() == 2 && 1143 "Cannot return more than two values!"); 1144 1145 // Since we produced two values, make sure to remember that we 1146 // legalized both of them. 1147 Tmp1 = LegalizeOp(Result); 1148 Tmp2 = LegalizeOp(Result.getValue(1)); 1149 AddLegalizedOperand(Op.getValue(0), Tmp1); 1150 AddLegalizedOperand(Op.getValue(1), Tmp2); 1151 return Op.getResNo() ? Tmp2 : Tmp1; 1152 case ISD::EH_RETURN: { 1153 MVT VT = Node->getValueType(0); 1154 // The only "good" option for this node is to custom lower it. 1155 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1156 default: assert(0 && "This action is not supported at all!"); 1157 case TargetLowering::Custom: 1158 Result = TLI.LowerOperation(Op, DAG); 1159 if (Result.getNode()) break; 1160 // Fall Thru 1161 case TargetLowering::Legal: 1162 // Target does not know, how to lower this, lower to noop 1163 Result = LegalizeOp(Node->getOperand(0)); 1164 break; 1165 } 1166 } 1167 break; 1168 case ISD::AssertSext: 1169 case ISD::AssertZext: 1170 Tmp1 = LegalizeOp(Node->getOperand(0)); 1171 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1172 break; 1173 case ISD::MERGE_VALUES: 1174 // Legalize eliminates MERGE_VALUES nodes. 1175 Result = Node->getOperand(Op.getResNo()); 1176 break; 1177 case ISD::CopyFromReg: 1178 Tmp1 = LegalizeOp(Node->getOperand(0)); 1179 Result = Op.getValue(0); 1180 if (Node->getNumValues() == 2) { 1181 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1182 } else { 1183 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!"); 1184 if (Node->getNumOperands() == 3) { 1185 Tmp2 = LegalizeOp(Node->getOperand(2)); 1186 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 1187 } else { 1188 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 1189 } 1190 AddLegalizedOperand(Op.getValue(2), Result.getValue(2)); 1191 } 1192 // Since CopyFromReg produces two values, make sure to remember that we 1193 // legalized both of them. 1194 AddLegalizedOperand(Op.getValue(0), Result); 1195 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1196 return Result.getValue(Op.getResNo()); 1197 case ISD::UNDEF: { 1198 MVT VT = Op.getValueType(); 1199 switch (TLI.getOperationAction(ISD::UNDEF, VT)) { 1200 default: assert(0 && "This action is not supported yet!"); 1201 case TargetLowering::Expand: 1202 if (VT.isInteger()) 1203 Result = DAG.getConstant(0, VT); 1204 else if (VT.isFloatingPoint()) 1205 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)), 1206 VT); 1207 else 1208 assert(0 && "Unknown value type!"); 1209 break; 1210 case TargetLowering::Legal: 1211 break; 1212 } 1213 break; 1214 } 1215 1216 case ISD::INTRINSIC_W_CHAIN: 1217 case ISD::INTRINSIC_WO_CHAIN: 1218 case ISD::INTRINSIC_VOID: { 1219 SmallVector<SDValue, 8> Ops; 1220 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1221 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1222 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1223 1224 // Allow the target to custom lower its intrinsics if it wants to. 1225 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) == 1226 TargetLowering::Custom) { 1227 Tmp3 = TLI.LowerOperation(Result, DAG); 1228 if (Tmp3.getNode()) Result = Tmp3; 1229 } 1230 1231 if (Result.getNode()->getNumValues() == 1) break; 1232 1233 // Must have return value and chain result. 1234 assert(Result.getNode()->getNumValues() == 2 && 1235 "Cannot return more than two values!"); 1236 1237 // Since loads produce two values, make sure to remember that we 1238 // legalized both of them. 1239 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1240 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1241 return Result.getValue(Op.getResNo()); 1242 } 1243 1244 case ISD::DBG_STOPPOINT: 1245 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!"); 1246 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain. 1247 1248 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) { 1249 case TargetLowering::Promote: 1250 default: assert(0 && "This action is not supported yet!"); 1251 case TargetLowering::Expand: { 1252 MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); 1253 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other); 1254 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other); 1255 1256 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); 1257 if (MMI && (useDEBUG_LOC || useLABEL)) { 1258 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit(); 1259 unsigned SrcFile = MMI->RecordSource(CompileUnit); 1260 1261 unsigned Line = DSP->getLine(); 1262 unsigned Col = DSP->getColumn(); 1263 1264 if (useDEBUG_LOC) { 1265 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32), 1266 DAG.getConstant(Col, MVT::i32), 1267 DAG.getConstant(SrcFile, MVT::i32) }; 1268 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4); 1269 } else { 1270 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile); 1271 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID); 1272 } 1273 } else { 1274 Result = Tmp1; // chain 1275 } 1276 break; 1277 } 1278 case TargetLowering::Legal: { 1279 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1280 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1281 break; 1282 1283 SmallVector<SDValue, 8> Ops; 1284 Ops.push_back(Tmp1); 1285 if (Action == Legal) { 1286 Ops.push_back(Node->getOperand(1)); // line # must be legal. 1287 Ops.push_back(Node->getOperand(2)); // col # must be legal. 1288 } else { 1289 // Otherwise promote them. 1290 Ops.push_back(PromoteOp(Node->getOperand(1))); 1291 Ops.push_back(PromoteOp(Node->getOperand(2))); 1292 } 1293 Ops.push_back(Node->getOperand(3)); // filename must be legal. 1294 Ops.push_back(Node->getOperand(4)); // working dir # must be legal. 1295 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1296 break; 1297 } 1298 } 1299 break; 1300 1301 case ISD::DECLARE: 1302 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!"); 1303 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) { 1304 default: assert(0 && "This action is not supported yet!"); 1305 case TargetLowering::Legal: 1306 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1307 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1308 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable. 1309 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1310 break; 1311 case TargetLowering::Expand: 1312 Result = LegalizeOp(Node->getOperand(0)); 1313 break; 1314 } 1315 break; 1316 1317 case ISD::DEBUG_LOC: 1318 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!"); 1319 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) { 1320 default: assert(0 && "This action is not supported yet!"); 1321 case TargetLowering::Legal: { 1322 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType()); 1323 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1324 if (Action == Legal && Tmp1 == Node->getOperand(0)) 1325 break; 1326 if (Action == Legal) { 1327 Tmp2 = Node->getOperand(1); 1328 Tmp3 = Node->getOperand(2); 1329 Tmp4 = Node->getOperand(3); 1330 } else { 1331 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #. 1332 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #. 1333 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id. 1334 } 1335 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1336 break; 1337 } 1338 } 1339 break; 1340 1341 case ISD::DBG_LABEL: 1342 case ISD::EH_LABEL: 1343 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!"); 1344 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 1345 default: assert(0 && "This action is not supported yet!"); 1346 case TargetLowering::Legal: 1347 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1348 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1349 break; 1350 case TargetLowering::Expand: 1351 Result = LegalizeOp(Node->getOperand(0)); 1352 break; 1353 } 1354 break; 1355 1356 case ISD::PREFETCH: 1357 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!"); 1358 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) { 1359 default: assert(0 && "This action is not supported yet!"); 1360 case TargetLowering::Legal: 1361 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1362 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address. 1363 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier. 1364 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier. 1365 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4); 1366 break; 1367 case TargetLowering::Expand: 1368 // It's a noop. 1369 Result = LegalizeOp(Node->getOperand(0)); 1370 break; 1371 } 1372 break; 1373 1374 case ISD::MEMBARRIER: { 1375 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!"); 1376 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) { 1377 default: assert(0 && "This action is not supported yet!"); 1378 case TargetLowering::Legal: { 1379 SDValue Ops[6]; 1380 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1381 for (int x = 1; x < 6; ++x) { 1382 Ops[x] = Node->getOperand(x); 1383 if (!isTypeLegal(Ops[x].getValueType())) 1384 Ops[x] = PromoteOp(Ops[x]); 1385 } 1386 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6); 1387 break; 1388 } 1389 case TargetLowering::Expand: 1390 //There is no libgcc call for this op 1391 Result = Node->getOperand(0); // Noop 1392 break; 1393 } 1394 break; 1395 } 1396 1397 case ISD::ATOMIC_CMP_SWAP_8: 1398 case ISD::ATOMIC_CMP_SWAP_16: 1399 case ISD::ATOMIC_CMP_SWAP_32: 1400 case ISD::ATOMIC_CMP_SWAP_64: { 1401 unsigned int num_operands = 4; 1402 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1403 SDValue Ops[4]; 1404 for (unsigned int x = 0; x < num_operands; ++x) 1405 Ops[x] = LegalizeOp(Node->getOperand(x)); 1406 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1407 1408 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1409 default: assert(0 && "This action is not supported yet!"); 1410 case TargetLowering::Custom: 1411 Result = TLI.LowerOperation(Result, DAG); 1412 break; 1413 case TargetLowering::Legal: 1414 break; 1415 } 1416 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1417 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1418 return Result.getValue(Op.getResNo()); 1419 } 1420 case ISD::ATOMIC_LOAD_ADD_8: 1421 case ISD::ATOMIC_LOAD_SUB_8: 1422 case ISD::ATOMIC_LOAD_AND_8: 1423 case ISD::ATOMIC_LOAD_OR_8: 1424 case ISD::ATOMIC_LOAD_XOR_8: 1425 case ISD::ATOMIC_LOAD_NAND_8: 1426 case ISD::ATOMIC_LOAD_MIN_8: 1427 case ISD::ATOMIC_LOAD_MAX_8: 1428 case ISD::ATOMIC_LOAD_UMIN_8: 1429 case ISD::ATOMIC_LOAD_UMAX_8: 1430 case ISD::ATOMIC_SWAP_8: 1431 case ISD::ATOMIC_LOAD_ADD_16: 1432 case ISD::ATOMIC_LOAD_SUB_16: 1433 case ISD::ATOMIC_LOAD_AND_16: 1434 case ISD::ATOMIC_LOAD_OR_16: 1435 case ISD::ATOMIC_LOAD_XOR_16: 1436 case ISD::ATOMIC_LOAD_NAND_16: 1437 case ISD::ATOMIC_LOAD_MIN_16: 1438 case ISD::ATOMIC_LOAD_MAX_16: 1439 case ISD::ATOMIC_LOAD_UMIN_16: 1440 case ISD::ATOMIC_LOAD_UMAX_16: 1441 case ISD::ATOMIC_SWAP_16: 1442 case ISD::ATOMIC_LOAD_ADD_32: 1443 case ISD::ATOMIC_LOAD_SUB_32: 1444 case ISD::ATOMIC_LOAD_AND_32: 1445 case ISD::ATOMIC_LOAD_OR_32: 1446 case ISD::ATOMIC_LOAD_XOR_32: 1447 case ISD::ATOMIC_LOAD_NAND_32: 1448 case ISD::ATOMIC_LOAD_MIN_32: 1449 case ISD::ATOMIC_LOAD_MAX_32: 1450 case ISD::ATOMIC_LOAD_UMIN_32: 1451 case ISD::ATOMIC_LOAD_UMAX_32: 1452 case ISD::ATOMIC_SWAP_32: 1453 case ISD::ATOMIC_LOAD_ADD_64: 1454 case ISD::ATOMIC_LOAD_SUB_64: 1455 case ISD::ATOMIC_LOAD_AND_64: 1456 case ISD::ATOMIC_LOAD_OR_64: 1457 case ISD::ATOMIC_LOAD_XOR_64: 1458 case ISD::ATOMIC_LOAD_NAND_64: 1459 case ISD::ATOMIC_LOAD_MIN_64: 1460 case ISD::ATOMIC_LOAD_MAX_64: 1461 case ISD::ATOMIC_LOAD_UMIN_64: 1462 case ISD::ATOMIC_LOAD_UMAX_64: 1463 case ISD::ATOMIC_SWAP_64: { 1464 unsigned int num_operands = 3; 1465 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!"); 1466 SDValue Ops[3]; 1467 for (unsigned int x = 0; x < num_operands; ++x) 1468 Ops[x] = LegalizeOp(Node->getOperand(x)); 1469 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands); 1470 1471 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 1472 default: assert(0 && "This action is not supported yet!"); 1473 case TargetLowering::Custom: 1474 Result = TLI.LowerOperation(Result, DAG); 1475 break; 1476 case TargetLowering::Legal: 1477 break; 1478 } 1479 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1480 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1481 return Result.getValue(Op.getResNo()); 1482 } 1483 case ISD::Constant: { 1484 ConstantSDNode *CN = cast<ConstantSDNode>(Node); 1485 unsigned opAction = 1486 TLI.getOperationAction(ISD::Constant, CN->getValueType(0)); 1487 1488 // We know we don't need to expand constants here, constants only have one 1489 // value and we check that it is fine above. 1490 1491 if (opAction == TargetLowering::Custom) { 1492 Tmp1 = TLI.LowerOperation(Result, DAG); 1493 if (Tmp1.getNode()) 1494 Result = Tmp1; 1495 } 1496 break; 1497 } 1498 case ISD::ConstantFP: { 1499 // Spill FP immediates to the constant pool if the target cannot directly 1500 // codegen them. Targets often have some immediate values that can be 1501 // efficiently generated into an FP register without a load. We explicitly 1502 // leave these constants as ConstantFP nodes for the target to deal with. 1503 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 1504 1505 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) { 1506 default: assert(0 && "This action is not supported yet!"); 1507 case TargetLowering::Legal: 1508 break; 1509 case TargetLowering::Custom: 1510 Tmp3 = TLI.LowerOperation(Result, DAG); 1511 if (Tmp3.getNode()) { 1512 Result = Tmp3; 1513 break; 1514 } 1515 // FALLTHROUGH 1516 case TargetLowering::Expand: { 1517 // Check to see if this FP immediate is already legal. 1518 bool isLegal = false; 1519 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(), 1520 E = TLI.legal_fpimm_end(); I != E; ++I) { 1521 if (CFP->isExactlyValue(*I)) { 1522 isLegal = true; 1523 break; 1524 } 1525 } 1526 // If this is a legal constant, turn it into a TargetConstantFP node. 1527 if (isLegal) 1528 break; 1529 Result = ExpandConstantFP(CFP, true, DAG, TLI); 1530 } 1531 } 1532 break; 1533 } 1534 case ISD::TokenFactor: 1535 if (Node->getNumOperands() == 2) { 1536 Tmp1 = LegalizeOp(Node->getOperand(0)); 1537 Tmp2 = LegalizeOp(Node->getOperand(1)); 1538 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1539 } else if (Node->getNumOperands() == 3) { 1540 Tmp1 = LegalizeOp(Node->getOperand(0)); 1541 Tmp2 = LegalizeOp(Node->getOperand(1)); 1542 Tmp3 = LegalizeOp(Node->getOperand(2)); 1543 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1544 } else { 1545 SmallVector<SDValue, 8> Ops; 1546 // Legalize the operands. 1547 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1548 Ops.push_back(LegalizeOp(Node->getOperand(i))); 1549 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1550 } 1551 break; 1552 1553 case ISD::FORMAL_ARGUMENTS: 1554 case ISD::CALL: 1555 // The only option for this is to custom lower it. 1556 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG); 1557 assert(Tmp3.getNode() && "Target didn't custom lower this node!"); 1558 // A call within a calling sequence must be legalized to something 1559 // other than the normal CALLSEQ_END. Violating this gets Legalize 1560 // into an infinite loop. 1561 assert ((!IsLegalizingCall || 1562 Node->getOpcode() != ISD::CALL || 1563 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) && 1564 "Nested CALLSEQ_START..CALLSEQ_END not supported."); 1565 1566 // The number of incoming and outgoing values should match; unless the final 1567 // outgoing value is a flag. 1568 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() || 1569 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 && 1570 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) == 1571 MVT::Flag)) && 1572 "Lowering call/formal_arguments produced unexpected # results!"); 1573 1574 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to 1575 // remember that we legalized all of them, so it doesn't get relegalized. 1576 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) { 1577 if (Tmp3.getNode()->getValueType(i) == MVT::Flag) 1578 continue; 1579 Tmp1 = LegalizeOp(Tmp3.getValue(i)); 1580 if (Op.getResNo() == i) 1581 Tmp2 = Tmp1; 1582 AddLegalizedOperand(SDValue(Node, i), Tmp1); 1583 } 1584 return Tmp2; 1585 case ISD::EXTRACT_SUBREG: { 1586 Tmp1 = LegalizeOp(Node->getOperand(0)); 1587 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1)); 1588 assert(idx && "Operand must be a constant"); 1589 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); 1590 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1591 } 1592 break; 1593 case ISD::INSERT_SUBREG: { 1594 Tmp1 = LegalizeOp(Node->getOperand(0)); 1595 Tmp2 = LegalizeOp(Node->getOperand(1)); 1596 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2)); 1597 assert(idx && "Operand must be a constant"); 1598 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0)); 1599 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1600 } 1601 break; 1602 case ISD::BUILD_VECTOR: 1603 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) { 1604 default: assert(0 && "This action is not supported yet!"); 1605 case TargetLowering::Custom: 1606 Tmp3 = TLI.LowerOperation(Result, DAG); 1607 if (Tmp3.getNode()) { 1608 Result = Tmp3; 1609 break; 1610 } 1611 // FALLTHROUGH 1612 case TargetLowering::Expand: 1613 Result = ExpandBUILD_VECTOR(Result.getNode()); 1614 break; 1615 } 1616 break; 1617 case ISD::INSERT_VECTOR_ELT: 1618 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec 1619 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo 1620 1621 // The type of the value to insert may not be legal, even though the vector 1622 // type is legal. Legalize/Promote accordingly. We do not handle Expand 1623 // here. 1624 switch (getTypeAction(Node->getOperand(1).getValueType())) { 1625 default: assert(0 && "Cannot expand insert element operand"); 1626 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 1627 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 1628 case Expand: 1629 // FIXME: An alternative would be to check to see if the target is not 1630 // going to custom lower this operation, we could bitcast to half elt 1631 // width and perform two inserts at that width, if that is legal. 1632 Tmp2 = Node->getOperand(1); 1633 break; 1634 } 1635 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1636 1637 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT, 1638 Node->getValueType(0))) { 1639 default: assert(0 && "This action is not supported yet!"); 1640 case TargetLowering::Legal: 1641 break; 1642 case TargetLowering::Custom: 1643 Tmp4 = TLI.LowerOperation(Result, DAG); 1644 if (Tmp4.getNode()) { 1645 Result = Tmp4; 1646 break; 1647 } 1648 // FALLTHROUGH 1649 case TargetLowering::Promote: 1650 // Fall thru for vector case 1651 case TargetLowering::Expand: { 1652 // If the insert index is a constant, codegen this as a scalar_to_vector, 1653 // then a shuffle that inserts it into the right position in the vector. 1654 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) { 1655 // SCALAR_TO_VECTOR requires that the type of the value being inserted 1656 // match the element type of the vector being created. 1657 if (Tmp2.getValueType() == 1658 Op.getValueType().getVectorElementType()) { 1659 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, 1660 Tmp1.getValueType(), Tmp2); 1661 1662 unsigned NumElts = Tmp1.getValueType().getVectorNumElements(); 1663 MVT ShufMaskVT = 1664 MVT::getIntVectorWithNumElements(NumElts); 1665 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType(); 1666 1667 // We generate a shuffle of InVec and ScVec, so the shuffle mask 1668 // should be 0,1,2,3,4,5... with the appropriate element replaced with 1669 // elt 0 of the RHS. 1670 SmallVector<SDValue, 8> ShufOps; 1671 for (unsigned i = 0; i != NumElts; ++i) { 1672 if (i != InsertPos->getZExtValue()) 1673 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT)); 1674 else 1675 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT)); 1676 } 1677 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT, 1678 &ShufOps[0], ShufOps.size()); 1679 1680 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(), 1681 Tmp1, ScVec, ShufMask); 1682 Result = LegalizeOp(Result); 1683 break; 1684 } 1685 } 1686 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3); 1687 break; 1688 } 1689 } 1690 break; 1691 case ISD::SCALAR_TO_VECTOR: 1692 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) { 1693 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1694 break; 1695 } 1696 1697 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal 1698 Result = DAG.UpdateNodeOperands(Result, Tmp1); 1699 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR, 1700 Node->getValueType(0))) { 1701 default: assert(0 && "This action is not supported yet!"); 1702 case TargetLowering::Legal: 1703 break; 1704 case TargetLowering::Custom: 1705 Tmp3 = TLI.LowerOperation(Result, DAG); 1706 if (Tmp3.getNode()) { 1707 Result = Tmp3; 1708 break; 1709 } 1710 // FALLTHROUGH 1711 case TargetLowering::Expand: 1712 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node)); 1713 break; 1714 } 1715 break; 1716 case ISD::VECTOR_SHUFFLE: 1717 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors, 1718 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask. 1719 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 1720 1721 // Allow targets to custom lower the SHUFFLEs they support. 1722 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) { 1723 default: assert(0 && "Unknown operation action!"); 1724 case TargetLowering::Legal: 1725 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) && 1726 "vector shuffle should not be created if not legal!"); 1727 break; 1728 case TargetLowering::Custom: 1729 Tmp3 = TLI.LowerOperation(Result, DAG); 1730 if (Tmp3.getNode()) { 1731 Result = Tmp3; 1732 break; 1733 } 1734 // FALLTHROUGH 1735 case TargetLowering::Expand: { 1736 MVT VT = Node->getValueType(0); 1737 MVT EltVT = VT.getVectorElementType(); 1738 MVT PtrVT = TLI.getPointerTy(); 1739 SDValue Mask = Node->getOperand(2); 1740 unsigned NumElems = Mask.getNumOperands(); 1741 SmallVector<SDValue,8> Ops; 1742 for (unsigned i = 0; i != NumElems; ++i) { 1743 SDValue Arg = Mask.getOperand(i); 1744 if (Arg.getOpcode() == ISD::UNDEF) { 1745 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT)); 1746 } else { 1747 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!"); 1748 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue(); 1749 if (Idx < NumElems) 1750 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, 1751 DAG.getConstant(Idx, PtrVT))); 1752 else 1753 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, 1754 DAG.getConstant(Idx - NumElems, PtrVT))); 1755 } 1756 } 1757 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1758 break; 1759 } 1760 case TargetLowering::Promote: { 1761 // Change base type to a different vector type. 1762 MVT OVT = Node->getValueType(0); 1763 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 1764 1765 // Cast the two input vectors. 1766 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 1767 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 1768 1769 // Convert the shuffle mask to the right # elements. 1770 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0); 1771 assert(Tmp3.getNode() && "Shuffle not legal?"); 1772 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3); 1773 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 1774 break; 1775 } 1776 } 1777 break; 1778 1779 case ISD::EXTRACT_VECTOR_ELT: 1780 Tmp1 = Node->getOperand(0); 1781 Tmp2 = LegalizeOp(Node->getOperand(1)); 1782 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1783 Result = ExpandEXTRACT_VECTOR_ELT(Result); 1784 break; 1785 1786 case ISD::EXTRACT_SUBVECTOR: 1787 Tmp1 = Node->getOperand(0); 1788 Tmp2 = LegalizeOp(Node->getOperand(1)); 1789 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 1790 Result = ExpandEXTRACT_SUBVECTOR(Result); 1791 break; 1792 1793 case ISD::CONCAT_VECTORS: { 1794 // Use extract/insert/build vector for now. We might try to be 1795 // more clever later. 1796 MVT PtrVT = TLI.getPointerTy(); 1797 SmallVector<SDValue, 8> Ops; 1798 unsigned NumOperands = Node->getNumOperands(); 1799 for (unsigned i=0; i < NumOperands; ++i) { 1800 SDValue SubOp = Node->getOperand(i); 1801 MVT VVT = SubOp.getNode()->getValueType(0); 1802 MVT EltVT = VVT.getVectorElementType(); 1803 unsigned NumSubElem = VVT.getVectorNumElements(); 1804 for (unsigned j=0; j < NumSubElem; ++j) { 1805 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp, 1806 DAG.getConstant(j, PtrVT))); 1807 } 1808 } 1809 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), 1810 &Ops[0], Ops.size())); 1811 } 1812 1813 case ISD::CALLSEQ_START: { 1814 SDNode *CallEnd = FindCallEndFromCallStart(Node); 1815 1816 // Recursively Legalize all of the inputs of the call end that do not lead 1817 // to this call start. This ensures that any libcalls that need be inserted 1818 // are inserted *before* the CALLSEQ_START. 1819 {SmallPtrSet<SDNode*, 32> NodesLeadingTo; 1820 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i) 1821 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node, 1822 NodesLeadingTo); 1823 } 1824 1825 // Now that we legalized all of the inputs (which may have inserted 1826 // libcalls) create the new CALLSEQ_START node. 1827 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1828 1829 // Merge in the last call, to ensure that this call start after the last 1830 // call ended. 1831 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { 1832 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1833 Tmp1 = LegalizeOp(Tmp1); 1834 } 1835 1836 // Do not try to legalize the target-specific arguments (#1+). 1837 if (Tmp1 != Node->getOperand(0)) { 1838 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1839 Ops[0] = Tmp1; 1840 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1841 } 1842 1843 // Remember that the CALLSEQ_START is legalized. 1844 AddLegalizedOperand(Op.getValue(0), Result); 1845 if (Node->getNumValues() == 2) // If this has a flag result, remember it. 1846 AddLegalizedOperand(Op.getValue(1), Result.getValue(1)); 1847 1848 // Now that the callseq_start and all of the non-call nodes above this call 1849 // sequence have been legalized, legalize the call itself. During this 1850 // process, no libcalls can/will be inserted, guaranteeing that no calls 1851 // can overlap. 1852 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!"); 1853 // Note that we are selecting this call! 1854 LastCALLSEQ_END = SDValue(CallEnd, 0); 1855 IsLegalizingCall = true; 1856 1857 // Legalize the call, starting from the CALLSEQ_END. 1858 LegalizeOp(LastCALLSEQ_END); 1859 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!"); 1860 return Result; 1861 } 1862 case ISD::CALLSEQ_END: 1863 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This 1864 // will cause this node to be legalized as well as handling libcalls right. 1865 if (LastCALLSEQ_END.getNode() != Node) { 1866 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0)); 1867 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 1868 assert(I != LegalizedNodes.end() && 1869 "Legalizing the call start should have legalized this node!"); 1870 return I->second; 1871 } 1872 1873 // Otherwise, the call start has been legalized and everything is going 1874 // according to plan. Just legalize ourselves normally here. 1875 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1876 // Do not try to legalize the target-specific arguments (#1+), except for 1877 // an optional flag input. 1878 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ 1879 if (Tmp1 != Node->getOperand(0)) { 1880 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1881 Ops[0] = Tmp1; 1882 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1883 } 1884 } else { 1885 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1)); 1886 if (Tmp1 != Node->getOperand(0) || 1887 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) { 1888 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1889 Ops[0] = Tmp1; 1890 Ops.back() = Tmp2; 1891 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1892 } 1893 } 1894 assert(IsLegalizingCall && "Call sequence imbalance between start/end?"); 1895 // This finishes up call legalization. 1896 IsLegalizingCall = false; 1897 1898 // If the CALLSEQ_END node has a flag, remember that we legalized it. 1899 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1900 if (Node->getNumValues() == 2) 1901 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1902 return Result.getValue(Op.getResNo()); 1903 case ISD::DYNAMIC_STACKALLOC: { 1904 MVT VT = Node->getValueType(0); 1905 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1906 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size. 1907 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment. 1908 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 1909 1910 Tmp1 = Result.getValue(0); 1911 Tmp2 = Result.getValue(1); 1912 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 1913 default: assert(0 && "This action is not supported yet!"); 1914 case TargetLowering::Expand: { 1915 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1916 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1917 " not tell us which reg is the stack pointer!"); 1918 SDValue Chain = Tmp1.getOperand(0); 1919 1920 // Chain the dynamic stack allocation so that it doesn't modify the stack 1921 // pointer when other instructions are using the stack. 1922 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1923 1924 SDValue Size = Tmp2.getOperand(1); 1925 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT); 1926 Chain = SP.getValue(1); 1927 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1928 unsigned StackAlign = 1929 TLI.getTargetMachine().getFrameInfo()->getStackAlignment(); 1930 if (Align > StackAlign) 1931 SP = DAG.getNode(ISD::AND, VT, SP, 1932 DAG.getConstant(-(uint64_t)Align, VT)); 1933 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value 1934 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain 1935 1936 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1937 DAG.getIntPtrConstant(0, true), SDValue()); 1938 1939 Tmp1 = LegalizeOp(Tmp1); 1940 Tmp2 = LegalizeOp(Tmp2); 1941 break; 1942 } 1943 case TargetLowering::Custom: 1944 Tmp3 = TLI.LowerOperation(Tmp1, DAG); 1945 if (Tmp3.getNode()) { 1946 Tmp1 = LegalizeOp(Tmp3); 1947 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 1948 } 1949 break; 1950 case TargetLowering::Legal: 1951 break; 1952 } 1953 // Since this op produce two values, make sure to remember that we 1954 // legalized both of them. 1955 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 1956 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 1957 return Op.getResNo() ? Tmp2 : Tmp1; 1958 } 1959 case ISD::INLINEASM: { 1960 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); 1961 bool Changed = false; 1962 // Legalize all of the operands of the inline asm, in case they are nodes 1963 // that need to be expanded or something. Note we skip the asm string and 1964 // all of the TargetConstant flags. 1965 SDValue Op = LegalizeOp(Ops[0]); 1966 Changed = Op != Ops[0]; 1967 Ops[0] = Op; 1968 1969 bool HasInFlag = Ops.back().getValueType() == MVT::Flag; 1970 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) { 1971 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3; 1972 for (++i; NumVals; ++i, --NumVals) { 1973 SDValue Op = LegalizeOp(Ops[i]); 1974 if (Op != Ops[i]) { 1975 Changed = true; 1976 Ops[i] = Op; 1977 } 1978 } 1979 } 1980 1981 if (HasInFlag) { 1982 Op = LegalizeOp(Ops.back()); 1983 Changed |= Op != Ops.back(); 1984 Ops.back() = Op; 1985 } 1986 1987 if (Changed) 1988 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 1989 1990 // INLINE asm returns a chain and flag, make sure to add both to the map. 1991 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 1992 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 1993 return Result.getValue(Op.getResNo()); 1994 } 1995 case ISD::BR: 1996 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 1997 // Ensure that libcalls are emitted before a branch. 1998 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 1999 Tmp1 = LegalizeOp(Tmp1); 2000 LastCALLSEQ_END = DAG.getEntryNode(); 2001 2002 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2003 break; 2004 case ISD::BRIND: 2005 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2006 // Ensure that libcalls are emitted before a branch. 2007 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2008 Tmp1 = LegalizeOp(Tmp1); 2009 LastCALLSEQ_END = DAG.getEntryNode(); 2010 2011 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2012 default: assert(0 && "Indirect target must be legal type (pointer)!"); 2013 case Legal: 2014 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 2015 break; 2016 } 2017 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2018 break; 2019 case ISD::BR_JT: 2020 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2021 // Ensure that libcalls are emitted before a branch. 2022 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2023 Tmp1 = LegalizeOp(Tmp1); 2024 LastCALLSEQ_END = DAG.getEntryNode(); 2025 2026 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node. 2027 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2028 2029 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) { 2030 default: assert(0 && "This action is not supported yet!"); 2031 case TargetLowering::Legal: break; 2032 case TargetLowering::Custom: 2033 Tmp1 = TLI.LowerOperation(Result, DAG); 2034 if (Tmp1.getNode()) Result = Tmp1; 2035 break; 2036 case TargetLowering::Expand: { 2037 SDValue Chain = Result.getOperand(0); 2038 SDValue Table = Result.getOperand(1); 2039 SDValue Index = Result.getOperand(2); 2040 2041 MVT PTy = TLI.getPointerTy(); 2042 MachineFunction &MF = DAG.getMachineFunction(); 2043 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); 2044 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy)); 2045 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 2046 2047 MVT MemVT = MVT::getIntegerVT(EntrySize * 8); 2048 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, Chain, Addr, 2049 PseudoSourceValue::getJumpTable(), 0, MemVT); 2050 Addr = LD; 2051 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2052 // For PIC, the sequence is: 2053 // BRIND(load(Jumptable + index) + RelocBase) 2054 // RelocBase can be JumpTable, GOT or some sort of global base. 2055 Addr = DAG.getNode(ISD::ADD, PTy, Addr, 2056 TLI.getPICJumpTableRelocBase(Table, DAG)); 2057 } 2058 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr); 2059 } 2060 } 2061 break; 2062 case ISD::BRCOND: 2063 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2064 // Ensure that libcalls are emitted before a return. 2065 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2066 Tmp1 = LegalizeOp(Tmp1); 2067 LastCALLSEQ_END = DAG.getEntryNode(); 2068 2069 switch (getTypeAction(Node->getOperand(1).getValueType())) { 2070 case Expand: assert(0 && "It's impossible to expand bools"); 2071 case Legal: 2072 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition. 2073 break; 2074 case Promote: { 2075 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition. 2076 2077 // The top bits of the promoted condition are not necessarily zero, ensure 2078 // that the value is properly zero extended. 2079 unsigned BitWidth = Tmp2.getValueSizeInBits(); 2080 if (!DAG.MaskedValueIsZero(Tmp2, 2081 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2082 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1); 2083 break; 2084 } 2085 } 2086 2087 // Basic block destination (Op#2) is always legal. 2088 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 2089 2090 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) { 2091 default: assert(0 && "This action is not supported yet!"); 2092 case TargetLowering::Legal: break; 2093 case TargetLowering::Custom: 2094 Tmp1 = TLI.LowerOperation(Result, DAG); 2095 if (Tmp1.getNode()) Result = Tmp1; 2096 break; 2097 case TargetLowering::Expand: 2098 // Expand brcond's setcc into its constituent parts and create a BR_CC 2099 // Node. 2100 if (Tmp2.getOpcode() == ISD::SETCC) { 2101 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2), 2102 Tmp2.getOperand(0), Tmp2.getOperand(1), 2103 Node->getOperand(2)); 2104 } else { 2105 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, 2106 DAG.getCondCode(ISD::SETNE), Tmp2, 2107 DAG.getConstant(0, Tmp2.getValueType()), 2108 Node->getOperand(2)); 2109 } 2110 break; 2111 } 2112 break; 2113 case ISD::BR_CC: 2114 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2115 // Ensure that libcalls are emitted before a branch. 2116 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2117 Tmp1 = LegalizeOp(Tmp1); 2118 Tmp2 = Node->getOperand(2); // LHS 2119 Tmp3 = Node->getOperand(3); // RHS 2120 Tmp4 = Node->getOperand(1); // CC 2121 2122 LegalizeSetCC(TLI.getSetCCResultType(Tmp2), Tmp2, Tmp3, Tmp4); 2123 LastCALLSEQ_END = DAG.getEntryNode(); 2124 2125 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 2126 // the LHS is a legal SETCC itself. In this case, we need to compare 2127 // the result against zero to select between true and false values. 2128 if (Tmp3.getNode() == 0) { 2129 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 2130 Tmp4 = DAG.getCondCode(ISD::SETNE); 2131 } 2132 2133 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3, 2134 Node->getOperand(4)); 2135 2136 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) { 2137 default: assert(0 && "Unexpected action for BR_CC!"); 2138 case TargetLowering::Legal: break; 2139 case TargetLowering::Custom: 2140 Tmp4 = TLI.LowerOperation(Result, DAG); 2141 if (Tmp4.getNode()) Result = Tmp4; 2142 break; 2143 } 2144 break; 2145 case ISD::LOAD: { 2146 LoadSDNode *LD = cast<LoadSDNode>(Node); 2147 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain. 2148 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer. 2149 2150 ISD::LoadExtType ExtType = LD->getExtensionType(); 2151 if (ExtType == ISD::NON_EXTLOAD) { 2152 MVT VT = Node->getValueType(0); 2153 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2154 Tmp3 = Result.getValue(0); 2155 Tmp4 = Result.getValue(1); 2156 2157 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 2158 default: assert(0 && "This action is not supported yet!"); 2159 case TargetLowering::Legal: 2160 // If this is an unaligned load and the target doesn't support it, 2161 // expand it. 2162 if (!TLI.allowsUnalignedMemoryAccesses()) { 2163 unsigned ABIAlignment = TLI.getTargetData()-> 2164 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2165 if (LD->getAlignment() < ABIAlignment){ 2166 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 2167 TLI); 2168 Tmp3 = Result.getOperand(0); 2169 Tmp4 = Result.getOperand(1); 2170 Tmp3 = LegalizeOp(Tmp3); 2171 Tmp4 = LegalizeOp(Tmp4); 2172 } 2173 } 2174 break; 2175 case TargetLowering::Custom: 2176 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 2177 if (Tmp1.getNode()) { 2178 Tmp3 = LegalizeOp(Tmp1); 2179 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 2180 } 2181 break; 2182 case TargetLowering::Promote: { 2183 // Only promote a load of vector type to another. 2184 assert(VT.isVector() && "Cannot promote this load!"); 2185 // Change base type to a different vector type. 2186 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 2187 2188 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(), 2189 LD->getSrcValueOffset(), 2190 LD->isVolatile(), LD->getAlignment()); 2191 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1)); 2192 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 2193 break; 2194 } 2195 } 2196 // Since loads produce two values, make sure to remember that we 2197 // legalized both of them. 2198 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 2199 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 2200 return Op.getResNo() ? Tmp4 : Tmp3; 2201 } else { 2202 MVT SrcVT = LD->getMemoryVT(); 2203 unsigned SrcWidth = SrcVT.getSizeInBits(); 2204 int SVOffset = LD->getSrcValueOffset(); 2205 unsigned Alignment = LD->getAlignment(); 2206 bool isVolatile = LD->isVolatile(); 2207 2208 if (SrcWidth != SrcVT.getStoreSizeInBits() && 2209 // Some targets pretend to have an i1 loading operation, and actually 2210 // load an i8. This trick is correct for ZEXTLOAD because the top 7 2211 // bits are guaranteed to be zero; it helps the optimizers understand 2212 // that these bits are zero. It is also useful for EXTLOAD, since it 2213 // tells the optimizers that those bits are undefined. It would be 2214 // nice to have an effective generic way of getting these benefits... 2215 // Until such a way is found, don't insist on promoting i1 here. 2216 (SrcVT != MVT::i1 || 2217 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 2218 // Promote to a byte-sized load if not loading an integral number of 2219 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 2220 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 2221 MVT NVT = MVT::getIntegerVT(NewWidth); 2222 SDValue Ch; 2223 2224 // The extra bits are guaranteed to be zero, since we stored them that 2225 // way. A zext load from NVT thus automatically gives zext from SrcVT. 2226 2227 ISD::LoadExtType NewExtType = 2228 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 2229 2230 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), 2231 Tmp1, Tmp2, LD->getSrcValue(), SVOffset, 2232 NVT, isVolatile, Alignment); 2233 2234 Ch = Result.getValue(1); // The chain. 2235 2236 if (ExtType == ISD::SEXTLOAD) 2237 // Having the top bits zero doesn't help when sign extending. 2238 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2239 Result, DAG.getValueType(SrcVT)); 2240 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 2241 // All the top bits are guaranteed to be zero - inform the optimizers. 2242 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result, 2243 DAG.getValueType(SrcVT)); 2244 2245 Tmp1 = LegalizeOp(Result); 2246 Tmp2 = LegalizeOp(Ch); 2247 } else if (SrcWidth & (SrcWidth - 1)) { 2248 // If not loading a power-of-2 number of bits, expand as two loads. 2249 assert(SrcVT.isExtended() && !SrcVT.isVector() && 2250 "Unsupported extload!"); 2251 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 2252 assert(RoundWidth < SrcWidth); 2253 unsigned ExtraWidth = SrcWidth - RoundWidth; 2254 assert(ExtraWidth < RoundWidth); 2255 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2256 "Load size not an integral number of bytes!"); 2257 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2258 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2259 SDValue Lo, Hi, Ch; 2260 unsigned IncrementSize; 2261 2262 if (TLI.isLittleEndian()) { 2263 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 2264 // Load the bottom RoundWidth bits. 2265 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2266 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2267 Alignment); 2268 2269 // Load the remaining ExtraWidth bits. 2270 IncrementSize = RoundWidth / 8; 2271 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2272 DAG.getIntPtrConstant(IncrementSize)); 2273 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2274 LD->getSrcValue(), SVOffset + IncrementSize, 2275 ExtraVT, isVolatile, 2276 MinAlign(Alignment, IncrementSize)); 2277 2278 // Build a factor node to remember that this load is independent of the 2279 // other one. 2280 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2281 Hi.getValue(1)); 2282 2283 // Move the top bits to the right place. 2284 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2285 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2286 2287 // Join the hi and lo parts. 2288 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2289 } else { 2290 // Big endian - avoid unaligned loads. 2291 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 2292 // Load the top RoundWidth bits. 2293 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2, 2294 LD->getSrcValue(), SVOffset, RoundVT, isVolatile, 2295 Alignment); 2296 2297 // Load the remaining ExtraWidth bits. 2298 IncrementSize = RoundWidth / 8; 2299 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2300 DAG.getIntPtrConstant(IncrementSize)); 2301 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2, 2302 LD->getSrcValue(), SVOffset + IncrementSize, 2303 ExtraVT, isVolatile, 2304 MinAlign(Alignment, IncrementSize)); 2305 2306 // Build a factor node to remember that this load is independent of the 2307 // other one. 2308 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 2309 Hi.getValue(1)); 2310 2311 // Move the top bits to the right place. 2312 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi, 2313 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2314 2315 // Join the hi and lo parts. 2316 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi); 2317 } 2318 2319 Tmp1 = LegalizeOp(Result); 2320 Tmp2 = LegalizeOp(Ch); 2321 } else { 2322 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 2323 default: assert(0 && "This action is not supported yet!"); 2324 case TargetLowering::Custom: 2325 isCustom = true; 2326 // FALLTHROUGH 2327 case TargetLowering::Legal: 2328 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); 2329 Tmp1 = Result.getValue(0); 2330 Tmp2 = Result.getValue(1); 2331 2332 if (isCustom) { 2333 Tmp3 = TLI.LowerOperation(Result, DAG); 2334 if (Tmp3.getNode()) { 2335 Tmp1 = LegalizeOp(Tmp3); 2336 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2337 } 2338 } else { 2339 // If this is an unaligned load and the target doesn't support it, 2340 // expand it. 2341 if (!TLI.allowsUnalignedMemoryAccesses()) { 2342 unsigned ABIAlignment = TLI.getTargetData()-> 2343 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); 2344 if (LD->getAlignment() < ABIAlignment){ 2345 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, 2346 TLI); 2347 Tmp1 = Result.getOperand(0); 2348 Tmp2 = Result.getOperand(1); 2349 Tmp1 = LegalizeOp(Tmp1); 2350 Tmp2 = LegalizeOp(Tmp2); 2351 } 2352 } 2353 } 2354 break; 2355 case TargetLowering::Expand: 2356 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 2357 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { 2358 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(), 2359 LD->getSrcValueOffset(), 2360 LD->isVolatile(), LD->getAlignment()); 2361 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load); 2362 Tmp1 = LegalizeOp(Result); // Relegalize new nodes. 2363 Tmp2 = LegalizeOp(Load.getValue(1)); 2364 break; 2365 } 2366 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!"); 2367 // Turn the unsupported load into an EXTLOAD followed by an explicit 2368 // zero/sign extend inreg. 2369 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), 2370 Tmp1, Tmp2, LD->getSrcValue(), 2371 LD->getSrcValueOffset(), SrcVT, 2372 LD->isVolatile(), LD->getAlignment()); 2373 SDValue ValRes; 2374 if (ExtType == ISD::SEXTLOAD) 2375 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 2376 Result, DAG.getValueType(SrcVT)); 2377 else 2378 ValRes = DAG.getZeroExtendInReg(Result, SrcVT); 2379 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. 2380 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. 2381 break; 2382 } 2383 } 2384 2385 // Since loads produce two values, make sure to remember that we legalized 2386 // both of them. 2387 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2388 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2389 return Op.getResNo() ? Tmp2 : Tmp1; 2390 } 2391 } 2392 case ISD::EXTRACT_ELEMENT: { 2393 MVT OpTy = Node->getOperand(0).getValueType(); 2394 switch (getTypeAction(OpTy)) { 2395 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!"); 2396 case Legal: 2397 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2398 // 1 -> Hi 2399 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0), 2400 DAG.getConstant(OpTy.getSizeInBits()/2, 2401 TLI.getShiftAmountTy())); 2402 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result); 2403 } else { 2404 // 0 -> Lo 2405 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), 2406 Node->getOperand(0)); 2407 } 2408 break; 2409 case Expand: 2410 // Get both the low and high parts. 2411 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 2412 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) 2413 Result = Tmp2; // 1 -> Hi 2414 else 2415 Result = Tmp1; // 0 -> Lo 2416 break; 2417 } 2418 break; 2419 } 2420 2421 case ISD::CopyToReg: 2422 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2423 2424 assert(isTypeLegal(Node->getOperand(2).getValueType()) && 2425 "Register type must be legal!"); 2426 // Legalize the incoming value (must be a legal type). 2427 Tmp2 = LegalizeOp(Node->getOperand(2)); 2428 if (Node->getNumValues() == 1) { 2429 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2); 2430 } else { 2431 assert(Node->getNumValues() == 2 && "Unknown CopyToReg"); 2432 if (Node->getNumOperands() == 4) { 2433 Tmp3 = LegalizeOp(Node->getOperand(3)); 2434 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2, 2435 Tmp3); 2436 } else { 2437 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2); 2438 } 2439 2440 // Since this produces two values, make sure to remember that we legalized 2441 // both of them. 2442 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0)); 2443 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1)); 2444 return Result; 2445 } 2446 break; 2447 2448 case ISD::RET: 2449 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2450 2451 // Ensure that libcalls are emitted before a return. 2452 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END); 2453 Tmp1 = LegalizeOp(Tmp1); 2454 LastCALLSEQ_END = DAG.getEntryNode(); 2455 2456 switch (Node->getNumOperands()) { 2457 case 3: // ret val 2458 Tmp2 = Node->getOperand(1); 2459 Tmp3 = Node->getOperand(2); // Signness 2460 switch (getTypeAction(Tmp2.getValueType())) { 2461 case Legal: 2462 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3); 2463 break; 2464 case Expand: 2465 if (!Tmp2.getValueType().isVector()) { 2466 SDValue Lo, Hi; 2467 ExpandOp(Tmp2, Lo, Hi); 2468 2469 // Big endian systems want the hi reg first. 2470 if (TLI.isBigEndian()) 2471 std::swap(Lo, Hi); 2472 2473 if (Hi.getNode()) 2474 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2475 else 2476 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3); 2477 Result = LegalizeOp(Result); 2478 } else { 2479 SDNode *InVal = Tmp2.getNode(); 2480 int InIx = Tmp2.getResNo(); 2481 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 2482 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 2483 2484 // Figure out if there is a simple type corresponding to this Vector 2485 // type. If so, convert to the vector type. 2486 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2487 if (TLI.isTypeLegal(TVT)) { 2488 // Turn this into a return of the vector type. 2489 Tmp2 = LegalizeOp(Tmp2); 2490 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2491 } else if (NumElems == 1) { 2492 // Turn this into a return of the scalar type. 2493 Tmp2 = ScalarizeVectorOp(Tmp2); 2494 Tmp2 = LegalizeOp(Tmp2); 2495 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2496 2497 // FIXME: Returns of gcc generic vectors smaller than a legal type 2498 // should be returned in integer registers! 2499 2500 // The scalarized value type may not be legal, e.g. it might require 2501 // promotion or expansion. Relegalize the return. 2502 Result = LegalizeOp(Result); 2503 } else { 2504 // FIXME: Returns of gcc generic vectors larger than a legal vector 2505 // type should be returned by reference! 2506 SDValue Lo, Hi; 2507 SplitVectorOp(Tmp2, Lo, Hi); 2508 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3); 2509 Result = LegalizeOp(Result); 2510 } 2511 } 2512 break; 2513 case Promote: 2514 Tmp2 = PromoteOp(Node->getOperand(1)); 2515 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2516 Result = LegalizeOp(Result); 2517 break; 2518 } 2519 break; 2520 case 1: // ret void 2521 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2522 break; 2523 default: { // ret <values> 2524 SmallVector<SDValue, 8> NewValues; 2525 NewValues.push_back(Tmp1); 2526 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) 2527 switch (getTypeAction(Node->getOperand(i).getValueType())) { 2528 case Legal: 2529 NewValues.push_back(LegalizeOp(Node->getOperand(i))); 2530 NewValues.push_back(Node->getOperand(i+1)); 2531 break; 2532 case Expand: { 2533 SDValue Lo, Hi; 2534 assert(!Node->getOperand(i).getValueType().isExtended() && 2535 "FIXME: TODO: implement returning non-legal vector types!"); 2536 ExpandOp(Node->getOperand(i), Lo, Hi); 2537 NewValues.push_back(Lo); 2538 NewValues.push_back(Node->getOperand(i+1)); 2539 if (Hi.getNode()) { 2540 NewValues.push_back(Hi); 2541 NewValues.push_back(Node->getOperand(i+1)); 2542 } 2543 break; 2544 } 2545 case Promote: 2546 assert(0 && "Can't promote multiple return value yet!"); 2547 } 2548 2549 if (NewValues.size() == Node->getNumOperands()) 2550 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size()); 2551 else 2552 Result = DAG.getNode(ISD::RET, MVT::Other, 2553 &NewValues[0], NewValues.size()); 2554 break; 2555 } 2556 } 2557 2558 if (Result.getOpcode() == ISD::RET) { 2559 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) { 2560 default: assert(0 && "This action is not supported yet!"); 2561 case TargetLowering::Legal: break; 2562 case TargetLowering::Custom: 2563 Tmp1 = TLI.LowerOperation(Result, DAG); 2564 if (Tmp1.getNode()) Result = Tmp1; 2565 break; 2566 } 2567 } 2568 break; 2569 case ISD::STORE: { 2570 StoreSDNode *ST = cast<StoreSDNode>(Node); 2571 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain. 2572 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer. 2573 int SVOffset = ST->getSrcValueOffset(); 2574 unsigned Alignment = ST->getAlignment(); 2575 bool isVolatile = ST->isVolatile(); 2576 2577 if (!ST->isTruncatingStore()) { 2578 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 2579 // FIXME: We shouldn't do this for TargetConstantFP's. 2580 // FIXME: move this to the DAG Combiner! Note that we can't regress due 2581 // to phase ordering between legalized code and the dag combiner. This 2582 // probably means that we need to integrate dag combiner and legalizer 2583 // together. 2584 // We generally can't do this one for long doubles. 2585 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 2586 if (CFP->getValueType(0) == MVT::f32 && 2587 getTypeAction(MVT::i32) == Legal) { 2588 Tmp3 = DAG.getConstant(CFP->getValueAPF(). 2589 bitcastToAPInt().zextOrTrunc(32), 2590 MVT::i32); 2591 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2592 SVOffset, isVolatile, Alignment); 2593 break; 2594 } else if (CFP->getValueType(0) == MVT::f64) { 2595 // If this target supports 64-bit registers, do a single 64-bit store. 2596 if (getTypeAction(MVT::i64) == Legal) { 2597 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 2598 zextOrTrunc(64), MVT::i64); 2599 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2600 SVOffset, isVolatile, Alignment); 2601 break; 2602 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { 2603 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 2604 // stores. If the target supports neither 32- nor 64-bits, this 2605 // xform is certainly not worth it. 2606 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 2607 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); 2608 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 2609 if (TLI.isBigEndian()) std::swap(Lo, Hi); 2610 2611 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2612 SVOffset, isVolatile, Alignment); 2613 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2614 DAG.getIntPtrConstant(4)); 2615 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, 2616 isVolatile, MinAlign(Alignment, 4U)); 2617 2618 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2619 break; 2620 } 2621 } 2622 } 2623 2624 switch (getTypeAction(ST->getMemoryVT())) { 2625 case Legal: { 2626 Tmp3 = LegalizeOp(ST->getValue()); 2627 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2628 ST->getOffset()); 2629 2630 MVT VT = Tmp3.getValueType(); 2631 switch (TLI.getOperationAction(ISD::STORE, VT)) { 2632 default: assert(0 && "This action is not supported yet!"); 2633 case TargetLowering::Legal: 2634 // If this is an unaligned store and the target doesn't support it, 2635 // expand it. 2636 if (!TLI.allowsUnalignedMemoryAccesses()) { 2637 unsigned ABIAlignment = TLI.getTargetData()-> 2638 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2639 if (ST->getAlignment() < ABIAlignment) 2640 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 2641 TLI); 2642 } 2643 break; 2644 case TargetLowering::Custom: 2645 Tmp1 = TLI.LowerOperation(Result, DAG); 2646 if (Tmp1.getNode()) Result = Tmp1; 2647 break; 2648 case TargetLowering::Promote: 2649 assert(VT.isVector() && "Unknown legal promote case!"); 2650 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, 2651 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3); 2652 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, 2653 ST->getSrcValue(), SVOffset, isVolatile, 2654 Alignment); 2655 break; 2656 } 2657 break; 2658 } 2659 case Promote: 2660 if (!ST->getMemoryVT().isVector()) { 2661 // Truncate the value and store the result. 2662 Tmp3 = PromoteOp(ST->getValue()); 2663 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2664 SVOffset, ST->getMemoryVT(), 2665 isVolatile, Alignment); 2666 break; 2667 } 2668 // Fall thru to expand for vector 2669 case Expand: { 2670 unsigned IncrementSize = 0; 2671 SDValue Lo, Hi; 2672 2673 // If this is a vector type, then we have to calculate the increment as 2674 // the product of the element size in bytes, and the number of elements 2675 // in the high half of the vector. 2676 if (ST->getValue().getValueType().isVector()) { 2677 SDNode *InVal = ST->getValue().getNode(); 2678 int InIx = ST->getValue().getResNo(); 2679 MVT InVT = InVal->getValueType(InIx); 2680 unsigned NumElems = InVT.getVectorNumElements(); 2681 MVT EVT = InVT.getVectorElementType(); 2682 2683 // Figure out if there is a simple type corresponding to this Vector 2684 // type. If so, convert to the vector type. 2685 MVT TVT = MVT::getVectorVT(EVT, NumElems); 2686 if (TLI.isTypeLegal(TVT)) { 2687 // Turn this into a normal store of the vector type. 2688 Tmp3 = LegalizeOp(ST->getValue()); 2689 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2690 SVOffset, isVolatile, Alignment); 2691 Result = LegalizeOp(Result); 2692 break; 2693 } else if (NumElems == 1) { 2694 // Turn this into a normal store of the scalar type. 2695 Tmp3 = ScalarizeVectorOp(ST->getValue()); 2696 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2697 SVOffset, isVolatile, Alignment); 2698 // The scalarized value type may not be legal, e.g. it might require 2699 // promotion or expansion. Relegalize the scalar store. 2700 Result = LegalizeOp(Result); 2701 break; 2702 } else { 2703 // Check if we have widen this node with another value 2704 std::map<SDValue, SDValue>::iterator I = 2705 WidenNodes.find(ST->getValue()); 2706 if (I != WidenNodes.end()) { 2707 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2); 2708 break; 2709 } 2710 else { 2711 SplitVectorOp(ST->getValue(), Lo, Hi); 2712 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() * 2713 EVT.getSizeInBits()/8; 2714 } 2715 } 2716 } else { 2717 ExpandOp(ST->getValue(), Lo, Hi); 2718 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0; 2719 2720 if (Hi.getNode() && TLI.isBigEndian()) 2721 std::swap(Lo, Hi); 2722 } 2723 2724 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(), 2725 SVOffset, isVolatile, Alignment); 2726 2727 if (Hi.getNode() == NULL) { 2728 // Must be int <-> float one-to-one expansion. 2729 Result = Lo; 2730 break; 2731 } 2732 2733 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2734 DAG.getIntPtrConstant(IncrementSize)); 2735 assert(isTypeLegal(Tmp2.getValueType()) && 2736 "Pointers must be legal!"); 2737 SVOffset += IncrementSize; 2738 Alignment = MinAlign(Alignment, IncrementSize); 2739 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2740 SVOffset, isVolatile, Alignment); 2741 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2742 break; 2743 } // case Expand 2744 } 2745 } else { 2746 switch (getTypeAction(ST->getValue().getValueType())) { 2747 case Legal: 2748 Tmp3 = LegalizeOp(ST->getValue()); 2749 break; 2750 case Promote: 2751 if (!ST->getValue().getValueType().isVector()) { 2752 // We can promote the value, the truncstore will still take care of it. 2753 Tmp3 = PromoteOp(ST->getValue()); 2754 break; 2755 } 2756 // Vector case falls through to expand 2757 case Expand: 2758 // Just store the low part. This may become a non-trunc store, so make 2759 // sure to use getTruncStore, not UpdateNodeOperands below. 2760 ExpandOp(ST->getValue(), Tmp3, Tmp4); 2761 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2762 SVOffset, MVT::i8, isVolatile, Alignment); 2763 } 2764 2765 MVT StVT = ST->getMemoryVT(); 2766 unsigned StWidth = StVT.getSizeInBits(); 2767 2768 if (StWidth != StVT.getStoreSizeInBits()) { 2769 // Promote to a byte-sized store with upper bits zero if not 2770 // storing an integral number of bytes. For example, promote 2771 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2772 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); 2773 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT); 2774 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2775 SVOffset, NVT, isVolatile, Alignment); 2776 } else if (StWidth & (StWidth - 1)) { 2777 // If not storing a power-of-2 number of bits, expand as two stores. 2778 assert(StVT.isExtended() && !StVT.isVector() && 2779 "Unsupported truncstore!"); 2780 unsigned RoundWidth = 1 << Log2_32(StWidth); 2781 assert(RoundWidth < StWidth); 2782 unsigned ExtraWidth = StWidth - RoundWidth; 2783 assert(ExtraWidth < RoundWidth); 2784 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 2785 "Store size not an integral number of bytes!"); 2786 MVT RoundVT = MVT::getIntegerVT(RoundWidth); 2787 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); 2788 SDValue Lo, Hi; 2789 unsigned IncrementSize; 2790 2791 if (TLI.isLittleEndian()) { 2792 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 2793 // Store the bottom RoundWidth bits. 2794 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2795 SVOffset, RoundVT, 2796 isVolatile, Alignment); 2797 2798 // Store the remaining ExtraWidth bits. 2799 IncrementSize = RoundWidth / 8; 2800 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2801 DAG.getIntPtrConstant(IncrementSize)); 2802 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2803 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy())); 2804 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), 2805 SVOffset + IncrementSize, ExtraVT, isVolatile, 2806 MinAlign(Alignment, IncrementSize)); 2807 } else { 2808 // Big endian - avoid unaligned stores. 2809 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 2810 // Store the top RoundWidth bits. 2811 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3, 2812 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy())); 2813 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset, 2814 RoundVT, isVolatile, Alignment); 2815 2816 // Store the remaining ExtraWidth bits. 2817 IncrementSize = RoundWidth / 8; 2818 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, 2819 DAG.getIntPtrConstant(IncrementSize)); 2820 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), 2821 SVOffset + IncrementSize, ExtraVT, isVolatile, 2822 MinAlign(Alignment, IncrementSize)); 2823 } 2824 2825 // The order of the stores doesn't matter. 2826 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2827 } else { 2828 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || 2829 Tmp2 != ST->getBasePtr()) 2830 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, 2831 ST->getOffset()); 2832 2833 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 2834 default: assert(0 && "This action is not supported yet!"); 2835 case TargetLowering::Legal: 2836 // If this is an unaligned store and the target doesn't support it, 2837 // expand it. 2838 if (!TLI.allowsUnalignedMemoryAccesses()) { 2839 unsigned ABIAlignment = TLI.getTargetData()-> 2840 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); 2841 if (ST->getAlignment() < ABIAlignment) 2842 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, 2843 TLI); 2844 } 2845 break; 2846 case TargetLowering::Custom: 2847 Result = TLI.LowerOperation(Result, DAG); 2848 break; 2849 case Expand: 2850 // TRUNCSTORE:i16 i32 -> STORE i16 2851 assert(isTypeLegal(StVT) && "Do not know how to expand this store!"); 2852 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3); 2853 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, 2854 isVolatile, Alignment); 2855 break; 2856 } 2857 } 2858 } 2859 break; 2860 } 2861 case ISD::PCMARKER: 2862 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2863 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 2864 break; 2865 case ISD::STACKSAVE: 2866 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2867 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2868 Tmp1 = Result.getValue(0); 2869 Tmp2 = Result.getValue(1); 2870 2871 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) { 2872 default: assert(0 && "This action is not supported yet!"); 2873 case TargetLowering::Legal: break; 2874 case TargetLowering::Custom: 2875 Tmp3 = TLI.LowerOperation(Result, DAG); 2876 if (Tmp3.getNode()) { 2877 Tmp1 = LegalizeOp(Tmp3); 2878 Tmp2 = LegalizeOp(Tmp3.getValue(1)); 2879 } 2880 break; 2881 case TargetLowering::Expand: 2882 // Expand to CopyFromReg if the target set 2883 // StackPointerRegisterToSaveRestore. 2884 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2885 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP, 2886 Node->getValueType(0)); 2887 Tmp2 = Tmp1.getValue(1); 2888 } else { 2889 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 2890 Tmp2 = Node->getOperand(0); 2891 } 2892 break; 2893 } 2894 2895 // Since stacksave produce two values, make sure to remember that we 2896 // legalized both of them. 2897 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2898 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2899 return Op.getResNo() ? Tmp2 : Tmp1; 2900 2901 case ISD::STACKRESTORE: 2902 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 2903 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 2904 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 2905 2906 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) { 2907 default: assert(0 && "This action is not supported yet!"); 2908 case TargetLowering::Legal: break; 2909 case TargetLowering::Custom: 2910 Tmp1 = TLI.LowerOperation(Result, DAG); 2911 if (Tmp1.getNode()) Result = Tmp1; 2912 break; 2913 case TargetLowering::Expand: 2914 // Expand to CopyToReg if the target set 2915 // StackPointerRegisterToSaveRestore. 2916 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2917 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2); 2918 } else { 2919 Result = Tmp1; 2920 } 2921 break; 2922 } 2923 break; 2924 2925 case ISD::READCYCLECOUNTER: 2926 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain 2927 Result = DAG.UpdateNodeOperands(Result, Tmp1); 2928 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER, 2929 Node->getValueType(0))) { 2930 default: assert(0 && "This action is not supported yet!"); 2931 case TargetLowering::Legal: 2932 Tmp1 = Result.getValue(0); 2933 Tmp2 = Result.getValue(1); 2934 break; 2935 case TargetLowering::Custom: 2936 Result = TLI.LowerOperation(Result, DAG); 2937 Tmp1 = LegalizeOp(Result.getValue(0)); 2938 Tmp2 = LegalizeOp(Result.getValue(1)); 2939 break; 2940 } 2941 2942 // Since rdcc produce two values, make sure to remember that we legalized 2943 // both of them. 2944 AddLegalizedOperand(SDValue(Node, 0), Tmp1); 2945 AddLegalizedOperand(SDValue(Node, 1), Tmp2); 2946 return Result; 2947 2948 case ISD::SELECT: 2949 switch (getTypeAction(Node->getOperand(0).getValueType())) { 2950 case Expand: assert(0 && "It's impossible to expand bools"); 2951 case Legal: 2952 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition. 2953 break; 2954 case Promote: { 2955 assert(!Node->getOperand(0).getValueType().isVector() && "not possible"); 2956 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition. 2957 // Make sure the condition is either zero or one. 2958 unsigned BitWidth = Tmp1.getValueSizeInBits(); 2959 if (!DAG.MaskedValueIsZero(Tmp1, 2960 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 2961 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1); 2962 break; 2963 } 2964 } 2965 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal 2966 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal 2967 2968 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 2969 2970 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) { 2971 default: assert(0 && "This action is not supported yet!"); 2972 case TargetLowering::Legal: break; 2973 case TargetLowering::Custom: { 2974 Tmp1 = TLI.LowerOperation(Result, DAG); 2975 if (Tmp1.getNode()) Result = Tmp1; 2976 break; 2977 } 2978 case TargetLowering::Expand: 2979 if (Tmp1.getOpcode() == ISD::SETCC) { 2980 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1), 2981 Tmp2, Tmp3, 2982 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 2983 } else { 2984 Result = DAG.getSelectCC(Tmp1, 2985 DAG.getConstant(0, Tmp1.getValueType()), 2986 Tmp2, Tmp3, ISD::SETNE); 2987 } 2988 break; 2989 case TargetLowering::Promote: { 2990 MVT NVT = 2991 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType()); 2992 unsigned ExtOp, TruncOp; 2993 if (Tmp2.getValueType().isVector()) { 2994 ExtOp = ISD::BIT_CONVERT; 2995 TruncOp = ISD::BIT_CONVERT; 2996 } else if (Tmp2.getValueType().isInteger()) { 2997 ExtOp = ISD::ANY_EXTEND; 2998 TruncOp = ISD::TRUNCATE; 2999 } else { 3000 ExtOp = ISD::FP_EXTEND; 3001 TruncOp = ISD::FP_ROUND; 3002 } 3003 // Promote each of the values to the new type. 3004 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2); 3005 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3); 3006 // Perform the larger operation, then round down. 3007 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3); 3008 if (TruncOp != ISD::FP_ROUND) 3009 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result); 3010 else 3011 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result, 3012 DAG.getIntPtrConstant(0)); 3013 break; 3014 } 3015 } 3016 break; 3017 case ISD::SELECT_CC: { 3018 Tmp1 = Node->getOperand(0); // LHS 3019 Tmp2 = Node->getOperand(1); // RHS 3020 Tmp3 = LegalizeOp(Node->getOperand(2)); // True 3021 Tmp4 = LegalizeOp(Node->getOperand(3)); // False 3022 SDValue CC = Node->getOperand(4); 3023 3024 LegalizeSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, CC); 3025 3026 // If we didn't get both a LHS and RHS back from LegalizeSetCC, 3027 // the LHS is a legal SETCC itself. In this case, we need to compare 3028 // the result against zero to select between true and false values. 3029 if (Tmp2.getNode() == 0) { 3030 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3031 CC = DAG.getCondCode(ISD::SETNE); 3032 } 3033 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC); 3034 3035 // Everything is legal, see if we should expand this op or something. 3036 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) { 3037 default: assert(0 && "This action is not supported yet!"); 3038 case TargetLowering::Legal: break; 3039 case TargetLowering::Custom: 3040 Tmp1 = TLI.LowerOperation(Result, DAG); 3041 if (Tmp1.getNode()) Result = Tmp1; 3042 break; 3043 } 3044 break; 3045 } 3046 case ISD::SETCC: 3047 Tmp1 = Node->getOperand(0); 3048 Tmp2 = Node->getOperand(1); 3049 Tmp3 = Node->getOperand(2); 3050 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3); 3051 3052 // If we had to Expand the SetCC operands into a SELECT node, then it may 3053 // not always be possible to return a true LHS & RHS. In this case, just 3054 // return the value we legalized, returned in the LHS 3055 if (Tmp2.getNode() == 0) { 3056 Result = Tmp1; 3057 break; 3058 } 3059 3060 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) { 3061 default: assert(0 && "Cannot handle this action for SETCC yet!"); 3062 case TargetLowering::Custom: 3063 isCustom = true; 3064 // FALLTHROUGH. 3065 case TargetLowering::Legal: 3066 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3067 if (isCustom) { 3068 Tmp4 = TLI.LowerOperation(Result, DAG); 3069 if (Tmp4.getNode()) Result = Tmp4; 3070 } 3071 break; 3072 case TargetLowering::Promote: { 3073 // First step, figure out the appropriate operation to use. 3074 // Allow SETCC to not be supported for all legal data types 3075 // Mostly this targets FP 3076 MVT NewInTy = Node->getOperand(0).getValueType(); 3077 MVT OldVT = NewInTy; OldVT = OldVT; 3078 3079 // Scan for the appropriate larger type to use. 3080 while (1) { 3081 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 3082 3083 assert(NewInTy.isInteger() == OldVT.isInteger() && 3084 "Fell off of the edge of the integer world"); 3085 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() && 3086 "Fell off of the edge of the floating point world"); 3087 3088 // If the target supports SETCC of this type, use it. 3089 if (TLI.isOperationLegal(ISD::SETCC, NewInTy)) 3090 break; 3091 } 3092 if (NewInTy.isInteger()) 3093 assert(0 && "Cannot promote Legal Integer SETCC yet"); 3094 else { 3095 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1); 3096 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2); 3097 } 3098 Tmp1 = LegalizeOp(Tmp1); 3099 Tmp2 = LegalizeOp(Tmp2); 3100 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3101 Result = LegalizeOp(Result); 3102 break; 3103 } 3104 case TargetLowering::Expand: 3105 // Expand a setcc node into a select_cc of the same condition, lhs, and 3106 // rhs that selects between const 1 (true) and const 0 (false). 3107 MVT VT = Node->getValueType(0); 3108 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2, 3109 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3110 Tmp3); 3111 break; 3112 } 3113 break; 3114 case ISD::VSETCC: { 3115 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3116 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3117 SDValue CC = Node->getOperand(2); 3118 3119 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC); 3120 3121 // Everything is legal, see if we should expand this op or something. 3122 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) { 3123 default: assert(0 && "This action is not supported yet!"); 3124 case TargetLowering::Legal: break; 3125 case TargetLowering::Custom: 3126 Tmp1 = TLI.LowerOperation(Result, DAG); 3127 if (Tmp1.getNode()) Result = Tmp1; 3128 break; 3129 } 3130 break; 3131 } 3132 3133 case ISD::SHL_PARTS: 3134 case ISD::SRA_PARTS: 3135 case ISD::SRL_PARTS: { 3136 SmallVector<SDValue, 8> Ops; 3137 bool Changed = false; 3138 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 3139 Ops.push_back(LegalizeOp(Node->getOperand(i))); 3140 Changed |= Ops.back() != Node->getOperand(i); 3141 } 3142 if (Changed) 3143 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size()); 3144 3145 switch (TLI.getOperationAction(Node->getOpcode(), 3146 Node->getValueType(0))) { 3147 default: assert(0 && "This action is not supported yet!"); 3148 case TargetLowering::Legal: break; 3149 case TargetLowering::Custom: 3150 Tmp1 = TLI.LowerOperation(Result, DAG); 3151 if (Tmp1.getNode()) { 3152 SDValue Tmp2, RetVal(0, 0); 3153 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 3154 Tmp2 = LegalizeOp(Tmp1.getValue(i)); 3155 AddLegalizedOperand(SDValue(Node, i), Tmp2); 3156 if (i == Op.getResNo()) 3157 RetVal = Tmp2; 3158 } 3159 assert(RetVal.getNode() && "Illegal result number"); 3160 return RetVal; 3161 } 3162 break; 3163 } 3164 3165 // Since these produce multiple values, make sure to remember that we 3166 // legalized all of them. 3167 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 3168 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i)); 3169 return Result.getValue(Op.getResNo()); 3170 } 3171 3172 // Binary operators 3173 case ISD::ADD: 3174 case ISD::SUB: 3175 case ISD::MUL: 3176 case ISD::MULHS: 3177 case ISD::MULHU: 3178 case ISD::UDIV: 3179 case ISD::SDIV: 3180 case ISD::AND: 3181 case ISD::OR: 3182 case ISD::XOR: 3183 case ISD::SHL: 3184 case ISD::SRL: 3185 case ISD::SRA: 3186 case ISD::FADD: 3187 case ISD::FSUB: 3188 case ISD::FMUL: 3189 case ISD::FDIV: 3190 case ISD::FPOW: 3191 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3192 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3193 case Expand: assert(0 && "Not possible"); 3194 case Legal: 3195 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3196 break; 3197 case Promote: 3198 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3199 break; 3200 } 3201 3202 if ((Node->getOpcode() == ISD::SHL || 3203 Node->getOpcode() == ISD::SRL || 3204 Node->getOpcode() == ISD::SRA) && 3205 !Node->getValueType(0).isVector()) { 3206 Tmp2 = LegalizeShiftAmount(Tmp2); 3207 } 3208 3209 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3210 3211 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3212 default: assert(0 && "BinOp legalize operation not supported"); 3213 case TargetLowering::Legal: break; 3214 case TargetLowering::Custom: 3215 Tmp1 = TLI.LowerOperation(Result, DAG); 3216 if (Tmp1.getNode()) { 3217 Result = Tmp1; 3218 break; 3219 } 3220 // Fall through if the custom lower can't deal with the operation 3221 case TargetLowering::Expand: { 3222 MVT VT = Op.getValueType(); 3223 3224 // See if multiply or divide can be lowered using two-result operations. 3225 SDVTList VTs = DAG.getVTList(VT, VT); 3226 if (Node->getOpcode() == ISD::MUL) { 3227 // We just need the low half of the multiply; try both the signed 3228 // and unsigned forms. If the target supports both SMUL_LOHI and 3229 // UMUL_LOHI, form a preference by checking which forms of plain 3230 // MULH it supports. 3231 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT); 3232 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT); 3233 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT); 3234 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT); 3235 unsigned OpToUse = 0; 3236 if (HasSMUL_LOHI && !HasMULHS) { 3237 OpToUse = ISD::SMUL_LOHI; 3238 } else if (HasUMUL_LOHI && !HasMULHU) { 3239 OpToUse = ISD::UMUL_LOHI; 3240 } else if (HasSMUL_LOHI) { 3241 OpToUse = ISD::SMUL_LOHI; 3242 } else if (HasUMUL_LOHI) { 3243 OpToUse = ISD::UMUL_LOHI; 3244 } 3245 if (OpToUse) { 3246 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0); 3247 break; 3248 } 3249 } 3250 if (Node->getOpcode() == ISD::MULHS && 3251 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) { 3252 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 3253 1); 3254 break; 3255 } 3256 if (Node->getOpcode() == ISD::MULHU && 3257 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) { 3258 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(), 3259 1); 3260 break; 3261 } 3262 if (Node->getOpcode() == ISD::SDIV && 3263 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3264 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 3265 0); 3266 break; 3267 } 3268 if (Node->getOpcode() == ISD::UDIV && 3269 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3270 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 3271 0); 3272 break; 3273 } 3274 3275 // Check to see if we have a libcall for this operator. 3276 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3277 bool isSigned = false; 3278 switch (Node->getOpcode()) { 3279 case ISD::UDIV: 3280 case ISD::SDIV: 3281 if (VT == MVT::i32) { 3282 LC = Node->getOpcode() == ISD::UDIV 3283 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32; 3284 isSigned = Node->getOpcode() == ISD::SDIV; 3285 } 3286 break; 3287 case ISD::MUL: 3288 if (VT == MVT::i32) 3289 LC = RTLIB::MUL_I32; 3290 break; 3291 case ISD::FPOW: 3292 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 3293 RTLIB::POW_PPCF128); 3294 break; 3295 default: break; 3296 } 3297 if (LC != RTLIB::UNKNOWN_LIBCALL) { 3298 SDValue Dummy; 3299 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3300 break; 3301 } 3302 3303 assert(Node->getValueType(0).isVector() && 3304 "Cannot expand this binary operator!"); 3305 // Expand the operation into a bunch of nasty scalar code. 3306 Result = LegalizeOp(UnrollVectorOp(Op)); 3307 break; 3308 } 3309 case TargetLowering::Promote: { 3310 switch (Node->getOpcode()) { 3311 default: assert(0 && "Do not know how to promote this BinOp!"); 3312 case ISD::AND: 3313 case ISD::OR: 3314 case ISD::XOR: { 3315 MVT OVT = Node->getValueType(0); 3316 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3317 assert(OVT.isVector() && "Cannot promote this BinOp!"); 3318 // Bit convert each of the values to the new type. 3319 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1); 3320 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2); 3321 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 3322 // Bit convert the result back the original type. 3323 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result); 3324 break; 3325 } 3326 } 3327 } 3328 } 3329 break; 3330 3331 case ISD::SMUL_LOHI: 3332 case ISD::UMUL_LOHI: 3333 case ISD::SDIVREM: 3334 case ISD::UDIVREM: 3335 // These nodes will only be produced by target-specific lowering, so 3336 // they shouldn't be here if they aren't legal. 3337 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) && 3338 "This must be legal!"); 3339 3340 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3341 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3342 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3343 break; 3344 3345 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type! 3346 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3347 switch (getTypeAction(Node->getOperand(1).getValueType())) { 3348 case Expand: assert(0 && "Not possible"); 3349 case Legal: 3350 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS. 3351 break; 3352 case Promote: 3353 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. 3354 break; 3355 } 3356 3357 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3358 3359 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3360 default: assert(0 && "Operation not supported"); 3361 case TargetLowering::Custom: 3362 Tmp1 = TLI.LowerOperation(Result, DAG); 3363 if (Tmp1.getNode()) Result = Tmp1; 3364 break; 3365 case TargetLowering::Legal: break; 3366 case TargetLowering::Expand: { 3367 // If this target supports fabs/fneg natively and select is cheap, 3368 // do this efficiently. 3369 if (!TLI.isSelectExpensive() && 3370 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) == 3371 TargetLowering::Legal && 3372 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) == 3373 TargetLowering::Legal) { 3374 // Get the sign bit of the RHS. 3375 MVT IVT = 3376 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64; 3377 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2); 3378 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit), 3379 SignBit, DAG.getConstant(0, IVT), ISD::SETLT); 3380 // Get the absolute value of the result. 3381 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1); 3382 // Select between the nabs and abs value based on the sign bit of 3383 // the input. 3384 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit, 3385 DAG.getNode(ISD::FNEG, AbsVal.getValueType(), 3386 AbsVal), 3387 AbsVal); 3388 Result = LegalizeOp(Result); 3389 break; 3390 } 3391 3392 // Otherwise, do bitwise ops! 3393 MVT NVT = 3394 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64; 3395 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 3396 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result); 3397 Result = LegalizeOp(Result); 3398 break; 3399 } 3400 } 3401 break; 3402 3403 case ISD::ADDC: 3404 case ISD::SUBC: 3405 Tmp1 = LegalizeOp(Node->getOperand(0)); 3406 Tmp2 = LegalizeOp(Node->getOperand(1)); 3407 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3408 Tmp3 = Result.getValue(0); 3409 Tmp4 = Result.getValue(1); 3410 3411 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3412 default: assert(0 && "This action is not supported yet!"); 3413 case TargetLowering::Legal: 3414 break; 3415 case TargetLowering::Custom: 3416 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 3417 if (Tmp1.getNode() != NULL) { 3418 Tmp3 = LegalizeOp(Tmp1); 3419 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 3420 } 3421 break; 3422 } 3423 // Since this produces two values, make sure to remember that we legalized 3424 // both of them. 3425 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 3426 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 3427 return Op.getResNo() ? Tmp4 : Tmp3; 3428 3429 case ISD::ADDE: 3430 case ISD::SUBE: 3431 Tmp1 = LegalizeOp(Node->getOperand(0)); 3432 Tmp2 = LegalizeOp(Node->getOperand(1)); 3433 Tmp3 = LegalizeOp(Node->getOperand(2)); 3434 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3); 3435 Tmp3 = Result.getValue(0); 3436 Tmp4 = Result.getValue(1); 3437 3438 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3439 default: assert(0 && "This action is not supported yet!"); 3440 case TargetLowering::Legal: 3441 break; 3442 case TargetLowering::Custom: 3443 Tmp1 = TLI.LowerOperation(Tmp3, DAG); 3444 if (Tmp1.getNode() != NULL) { 3445 Tmp3 = LegalizeOp(Tmp1); 3446 Tmp4 = LegalizeOp(Tmp1.getValue(1)); 3447 } 3448 break; 3449 } 3450 // Since this produces two values, make sure to remember that we legalized 3451 // both of them. 3452 AddLegalizedOperand(SDValue(Node, 0), Tmp3); 3453 AddLegalizedOperand(SDValue(Node, 1), Tmp4); 3454 return Op.getResNo() ? Tmp4 : Tmp3; 3455 3456 case ISD::BUILD_PAIR: { 3457 MVT PairTy = Node->getValueType(0); 3458 // TODO: handle the case where the Lo and Hi operands are not of legal type 3459 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo 3460 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi 3461 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) { 3462 case TargetLowering::Promote: 3463 case TargetLowering::Custom: 3464 assert(0 && "Cannot promote/custom this yet!"); 3465 case TargetLowering::Legal: 3466 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) 3467 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2); 3468 break; 3469 case TargetLowering::Expand: 3470 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1); 3471 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2); 3472 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2, 3473 DAG.getConstant(PairTy.getSizeInBits()/2, 3474 TLI.getShiftAmountTy())); 3475 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2); 3476 break; 3477 } 3478 break; 3479 } 3480 3481 case ISD::UREM: 3482 case ISD::SREM: 3483 case ISD::FREM: 3484 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3485 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3486 3487 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3488 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!"); 3489 case TargetLowering::Custom: 3490 isCustom = true; 3491 // FALLTHROUGH 3492 case TargetLowering::Legal: 3493 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3494 if (isCustom) { 3495 Tmp1 = TLI.LowerOperation(Result, DAG); 3496 if (Tmp1.getNode()) Result = Tmp1; 3497 } 3498 break; 3499 case TargetLowering::Expand: { 3500 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV; 3501 bool isSigned = DivOpc == ISD::SDIV; 3502 MVT VT = Node->getValueType(0); 3503 3504 // See if remainder can be lowered using two-result operations. 3505 SDVTList VTs = DAG.getVTList(VT, VT); 3506 if (Node->getOpcode() == ISD::SREM && 3507 TLI.isOperationLegal(ISD::SDIVREM, VT)) { 3508 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1); 3509 break; 3510 } 3511 if (Node->getOpcode() == ISD::UREM && 3512 TLI.isOperationLegal(ISD::UDIVREM, VT)) { 3513 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1); 3514 break; 3515 } 3516 3517 if (VT.isInteger()) { 3518 if (TLI.getOperationAction(DivOpc, VT) == 3519 TargetLowering::Legal) { 3520 // X % Y -> X-X/Y*Y 3521 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2); 3522 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2); 3523 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result); 3524 } else if (VT.isVector()) { 3525 Result = LegalizeOp(UnrollVectorOp(Op)); 3526 } else { 3527 assert(VT == MVT::i32 && 3528 "Cannot expand this binary operator!"); 3529 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM 3530 ? RTLIB::UREM_I32 : RTLIB::SREM_I32; 3531 SDValue Dummy; 3532 Result = ExpandLibCall(LC, Node, isSigned, Dummy); 3533 } 3534 } else { 3535 assert(VT.isFloatingPoint() && 3536 "remainder op must have integer or floating-point type"); 3537 if (VT.isVector()) { 3538 Result = LegalizeOp(UnrollVectorOp(Op)); 3539 } else { 3540 // Floating point mod -> fmod libcall. 3541 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64, 3542 RTLIB::REM_F80, RTLIB::REM_PPCF128); 3543 SDValue Dummy; 3544 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3545 } 3546 } 3547 break; 3548 } 3549 } 3550 break; 3551 case ISD::VAARG: { 3552 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3553 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3554 3555 MVT VT = Node->getValueType(0); 3556 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) { 3557 default: assert(0 && "This action is not supported yet!"); 3558 case TargetLowering::Custom: 3559 isCustom = true; 3560 // FALLTHROUGH 3561 case TargetLowering::Legal: 3562 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3563 Result = Result.getValue(0); 3564 Tmp1 = Result.getValue(1); 3565 3566 if (isCustom) { 3567 Tmp2 = TLI.LowerOperation(Result, DAG); 3568 if (Tmp2.getNode()) { 3569 Result = LegalizeOp(Tmp2); 3570 Tmp1 = LegalizeOp(Tmp2.getValue(1)); 3571 } 3572 } 3573 break; 3574 case TargetLowering::Expand: { 3575 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 3576 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 3577 // Increment the pointer, VAList, to the next vaarg 3578 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 3579 DAG.getConstant(TLI.getTargetData()->getABITypeSize(VT.getTypeForMVT()), 3580 TLI.getPointerTy())); 3581 // Store the incremented VAList to the legalized pointer 3582 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 3583 // Load the actual argument out of the pointer VAList 3584 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0); 3585 Tmp1 = LegalizeOp(Result.getValue(1)); 3586 Result = LegalizeOp(Result); 3587 break; 3588 } 3589 } 3590 // Since VAARG produces two values, make sure to remember that we 3591 // legalized both of them. 3592 AddLegalizedOperand(SDValue(Node, 0), Result); 3593 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 3594 return Op.getResNo() ? Tmp1 : Result; 3595 } 3596 3597 case ISD::VACOPY: 3598 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3599 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer. 3600 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer. 3601 3602 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) { 3603 default: assert(0 && "This action is not supported yet!"); 3604 case TargetLowering::Custom: 3605 isCustom = true; 3606 // FALLTHROUGH 3607 case TargetLowering::Legal: 3608 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, 3609 Node->getOperand(3), Node->getOperand(4)); 3610 if (isCustom) { 3611 Tmp1 = TLI.LowerOperation(Result, DAG); 3612 if (Tmp1.getNode()) Result = Tmp1; 3613 } 3614 break; 3615 case TargetLowering::Expand: 3616 // This defaults to loading a pointer from the input and storing it to the 3617 // output, returning the chain. 3618 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 3619 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 3620 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0); 3621 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0); 3622 break; 3623 } 3624 break; 3625 3626 case ISD::VAEND: 3627 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3628 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3629 3630 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) { 3631 default: assert(0 && "This action is not supported yet!"); 3632 case TargetLowering::Custom: 3633 isCustom = true; 3634 // FALLTHROUGH 3635 case TargetLowering::Legal: 3636 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3637 if (isCustom) { 3638 Tmp1 = TLI.LowerOperation(Tmp1, DAG); 3639 if (Tmp1.getNode()) Result = Tmp1; 3640 } 3641 break; 3642 case TargetLowering::Expand: 3643 Result = Tmp1; // Default to a no-op, return the chain 3644 break; 3645 } 3646 break; 3647 3648 case ISD::VASTART: 3649 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. 3650 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer. 3651 3652 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2)); 3653 3654 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) { 3655 default: assert(0 && "This action is not supported yet!"); 3656 case TargetLowering::Legal: break; 3657 case TargetLowering::Custom: 3658 Tmp1 = TLI.LowerOperation(Result, DAG); 3659 if (Tmp1.getNode()) Result = Tmp1; 3660 break; 3661 } 3662 break; 3663 3664 case ISD::ROTL: 3665 case ISD::ROTR: 3666 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS 3667 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS 3668 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2); 3669 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3670 default: 3671 assert(0 && "ROTL/ROTR legalize operation not supported"); 3672 break; 3673 case TargetLowering::Legal: 3674 break; 3675 case TargetLowering::Custom: 3676 Tmp1 = TLI.LowerOperation(Result, DAG); 3677 if (Tmp1.getNode()) Result = Tmp1; 3678 break; 3679 case TargetLowering::Promote: 3680 assert(0 && "Do not know how to promote ROTL/ROTR"); 3681 break; 3682 case TargetLowering::Expand: 3683 assert(0 && "Do not know how to expand ROTL/ROTR"); 3684 break; 3685 } 3686 break; 3687 3688 case ISD::BSWAP: 3689 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3690 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3691 case TargetLowering::Custom: 3692 assert(0 && "Cannot custom legalize this yet!"); 3693 case TargetLowering::Legal: 3694 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3695 break; 3696 case TargetLowering::Promote: { 3697 MVT OVT = Tmp1.getValueType(); 3698 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3699 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3700 3701 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3702 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 3703 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 3704 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 3705 break; 3706 } 3707 case TargetLowering::Expand: 3708 Result = ExpandBSWAP(Tmp1); 3709 break; 3710 } 3711 break; 3712 3713 case ISD::CTPOP: 3714 case ISD::CTTZ: 3715 case ISD::CTLZ: 3716 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op 3717 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3718 case TargetLowering::Custom: 3719 case TargetLowering::Legal: 3720 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3721 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3722 TargetLowering::Custom) { 3723 Tmp1 = TLI.LowerOperation(Result, DAG); 3724 if (Tmp1.getNode()) { 3725 Result = Tmp1; 3726 } 3727 } 3728 break; 3729 case TargetLowering::Promote: { 3730 MVT OVT = Tmp1.getValueType(); 3731 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3732 3733 // Zero extend the argument. 3734 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 3735 // Perform the larger operation, then subtract if needed. 3736 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1); 3737 switch (Node->getOpcode()) { 3738 case ISD::CTPOP: 3739 Result = Tmp1; 3740 break; 3741 case ISD::CTTZ: 3742 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 3743 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 3744 DAG.getConstant(NVT.getSizeInBits(), NVT), 3745 ISD::SETEQ); 3746 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 3747 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3748 break; 3749 case ISD::CTLZ: 3750 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3751 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 3752 DAG.getConstant(NVT.getSizeInBits() - 3753 OVT.getSizeInBits(), NVT)); 3754 break; 3755 } 3756 break; 3757 } 3758 case TargetLowering::Expand: 3759 Result = ExpandBitCount(Node->getOpcode(), Tmp1); 3760 break; 3761 } 3762 break; 3763 3764 // Unary operators 3765 case ISD::FABS: 3766 case ISD::FNEG: 3767 case ISD::FSQRT: 3768 case ISD::FSIN: 3769 case ISD::FCOS: 3770 case ISD::FLOG: 3771 case ISD::FLOG2: 3772 case ISD::FLOG10: 3773 case ISD::FEXP: 3774 case ISD::FEXP2: 3775 case ISD::FTRUNC: 3776 case ISD::FFLOOR: 3777 case ISD::FCEIL: 3778 case ISD::FRINT: 3779 case ISD::FNEARBYINT: 3780 Tmp1 = LegalizeOp(Node->getOperand(0)); 3781 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 3782 case TargetLowering::Promote: 3783 case TargetLowering::Custom: 3784 isCustom = true; 3785 // FALLTHROUGH 3786 case TargetLowering::Legal: 3787 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3788 if (isCustom) { 3789 Tmp1 = TLI.LowerOperation(Result, DAG); 3790 if (Tmp1.getNode()) Result = Tmp1; 3791 } 3792 break; 3793 case TargetLowering::Expand: 3794 switch (Node->getOpcode()) { 3795 default: assert(0 && "Unreachable!"); 3796 case ISD::FNEG: 3797 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 3798 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 3799 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1); 3800 break; 3801 case ISD::FABS: { 3802 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 3803 MVT VT = Node->getValueType(0); 3804 Tmp2 = DAG.getConstantFP(0.0, VT); 3805 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 3806 ISD::SETUGT); 3807 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1); 3808 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3); 3809 break; 3810 } 3811 case ISD::FSQRT: 3812 case ISD::FSIN: 3813 case ISD::FCOS: 3814 case ISD::FLOG: 3815 case ISD::FLOG2: 3816 case ISD::FLOG10: 3817 case ISD::FEXP: 3818 case ISD::FEXP2: 3819 case ISD::FTRUNC: 3820 case ISD::FFLOOR: 3821 case ISD::FCEIL: 3822 case ISD::FRINT: 3823 case ISD::FNEARBYINT: { 3824 MVT VT = Node->getValueType(0); 3825 3826 // Expand unsupported unary vector operators by unrolling them. 3827 if (VT.isVector()) { 3828 Result = LegalizeOp(UnrollVectorOp(Op)); 3829 break; 3830 } 3831 3832 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3833 switch(Node->getOpcode()) { 3834 case ISD::FSQRT: 3835 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 3836 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 3837 break; 3838 case ISD::FSIN: 3839 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 3840 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 3841 break; 3842 case ISD::FCOS: 3843 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 3844 RTLIB::COS_F80, RTLIB::COS_PPCF128); 3845 break; 3846 case ISD::FLOG: 3847 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64, 3848 RTLIB::LOG_F80, RTLIB::LOG_PPCF128); 3849 break; 3850 case ISD::FLOG2: 3851 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 3852 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128); 3853 break; 3854 case ISD::FLOG10: 3855 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 3856 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128); 3857 break; 3858 case ISD::FEXP: 3859 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64, 3860 RTLIB::EXP_F80, RTLIB::EXP_PPCF128); 3861 break; 3862 case ISD::FEXP2: 3863 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 3864 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128); 3865 break; 3866 case ISD::FTRUNC: 3867 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 3868 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 3869 break; 3870 case ISD::FFLOOR: 3871 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 3872 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 3873 break; 3874 case ISD::FCEIL: 3875 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 3876 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 3877 break; 3878 case ISD::FRINT: 3879 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 3880 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 3881 break; 3882 case ISD::FNEARBYINT: 3883 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 3884 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 3885 break; 3886 break; 3887 default: assert(0 && "Unreachable!"); 3888 } 3889 SDValue Dummy; 3890 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3891 break; 3892 } 3893 } 3894 break; 3895 } 3896 break; 3897 case ISD::FPOWI: { 3898 MVT VT = Node->getValueType(0); 3899 3900 // Expand unsupported unary vector operators by unrolling them. 3901 if (VT.isVector()) { 3902 Result = LegalizeOp(UnrollVectorOp(Op)); 3903 break; 3904 } 3905 3906 // We always lower FPOWI into a libcall. No target support for it yet. 3907 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, 3908 RTLIB::POWI_F80, RTLIB::POWI_PPCF128); 3909 SDValue Dummy; 3910 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 3911 break; 3912 } 3913 case ISD::BIT_CONVERT: 3914 if (!isTypeLegal(Node->getOperand(0).getValueType())) { 3915 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3916 Node->getValueType(0)); 3917 } else if (Op.getOperand(0).getValueType().isVector()) { 3918 // The input has to be a vector type, we have to either scalarize it, pack 3919 // it, or convert it based on whether the input vector type is legal. 3920 SDNode *InVal = Node->getOperand(0).getNode(); 3921 int InIx = Node->getOperand(0).getResNo(); 3922 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements(); 3923 MVT EVT = InVal->getValueType(InIx).getVectorElementType(); 3924 3925 // Figure out if there is a simple type corresponding to this Vector 3926 // type. If so, convert to the vector type. 3927 MVT TVT = MVT::getVectorVT(EVT, NumElems); 3928 if (TLI.isTypeLegal(TVT)) { 3929 // Turn this into a bit convert of the vector input. 3930 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3931 LegalizeOp(Node->getOperand(0))); 3932 break; 3933 } else if (NumElems == 1) { 3934 // Turn this into a bit convert of the scalar input. 3935 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), 3936 ScalarizeVectorOp(Node->getOperand(0))); 3937 break; 3938 } else { 3939 // FIXME: UNIMP! Store then reload 3940 assert(0 && "Cast from unsupported vector type not implemented yet!"); 3941 } 3942 } else { 3943 switch (TLI.getOperationAction(ISD::BIT_CONVERT, 3944 Node->getOperand(0).getValueType())) { 3945 default: assert(0 && "Unknown operation action!"); 3946 case TargetLowering::Expand: 3947 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 3948 Node->getValueType(0)); 3949 break; 3950 case TargetLowering::Legal: 3951 Tmp1 = LegalizeOp(Node->getOperand(0)); 3952 Result = DAG.UpdateNodeOperands(Result, Tmp1); 3953 break; 3954 } 3955 } 3956 break; 3957 case ISD::CONVERT_RNDSAT: { 3958 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 3959 switch (CvtCode) { 3960 default: assert(0 && "Unknown cvt code!"); 3961 case ISD::CVT_SF: 3962 case ISD::CVT_UF: 3963 case ISD::CVT_FF: 3964 break; 3965 case ISD::CVT_FS: 3966 case ISD::CVT_FU: 3967 case ISD::CVT_SS: 3968 case ISD::CVT_SU: 3969 case ISD::CVT_US: 3970 case ISD::CVT_UU: { 3971 SDValue DTyOp = Node->getOperand(1); 3972 SDValue STyOp = Node->getOperand(2); 3973 SDValue RndOp = Node->getOperand(3); 3974 SDValue SatOp = Node->getOperand(4); 3975 switch (getTypeAction(Node->getOperand(0).getValueType())) { 3976 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 3977 case Legal: 3978 Tmp1 = LegalizeOp(Node->getOperand(0)); 3979 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp, 3980 RndOp, SatOp); 3981 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 3982 TargetLowering::Custom) { 3983 Tmp1 = TLI.LowerOperation(Result, DAG); 3984 if (Tmp1.getNode()) Result = Tmp1; 3985 } 3986 break; 3987 case Promote: 3988 Result = PromoteOp(Node->getOperand(0)); 3989 // For FP, make Op1 a i32 3990 3991 Result = DAG.getConvertRndSat(Op.getValueType(), Result, 3992 DTyOp, STyOp, RndOp, SatOp, CvtCode); 3993 break; 3994 } 3995 break; 3996 } 3997 } // end switch CvtCode 3998 break; 3999 } 4000 // Conversion operators. The source and destination have different types. 4001 case ISD::SINT_TO_FP: 4002 case ISD::UINT_TO_FP: { 4003 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 4004 Result = LegalizeINT_TO_FP(Result, isSigned, 4005 Node->getValueType(0), Node->getOperand(0)); 4006 break; 4007 } 4008 case ISD::TRUNCATE: 4009 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4010 case Legal: 4011 Tmp1 = LegalizeOp(Node->getOperand(0)); 4012 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { 4013 default: assert(0 && "Unknown TRUNCATE legalization operation action!"); 4014 case TargetLowering::Custom: 4015 isCustom = true; 4016 // FALLTHROUGH 4017 case TargetLowering::Legal: 4018 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4019 if (isCustom) { 4020 Tmp1 = TLI.LowerOperation(Result, DAG); 4021 if (Tmp1.getNode()) Result = Tmp1; 4022 } 4023 break; 4024 case TargetLowering::Expand: 4025 assert(Result.getValueType().isVector() && "must be vector type"); 4026 // Unroll the truncate. We should do better. 4027 Result = LegalizeOp(UnrollVectorOp(Result)); 4028 } 4029 break; 4030 case Expand: 4031 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4032 4033 // Since the result is legal, we should just be able to truncate the low 4034 // part of the source. 4035 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1); 4036 break; 4037 case Promote: 4038 Result = PromoteOp(Node->getOperand(0)); 4039 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result); 4040 break; 4041 } 4042 break; 4043 4044 case ISD::FP_TO_SINT: 4045 case ISD::FP_TO_UINT: 4046 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4047 case Legal: 4048 Tmp1 = LegalizeOp(Node->getOperand(0)); 4049 4050 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){ 4051 default: assert(0 && "Unknown operation action!"); 4052 case TargetLowering::Custom: 4053 isCustom = true; 4054 // FALLTHROUGH 4055 case TargetLowering::Legal: 4056 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4057 if (isCustom) { 4058 Tmp1 = TLI.LowerOperation(Result, DAG); 4059 if (Tmp1.getNode()) Result = Tmp1; 4060 } 4061 break; 4062 case TargetLowering::Promote: 4063 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0), 4064 Node->getOpcode() == ISD::FP_TO_SINT); 4065 break; 4066 case TargetLowering::Expand: 4067 if (Node->getOpcode() == ISD::FP_TO_UINT) { 4068 SDValue True, False; 4069 MVT VT = Node->getOperand(0).getValueType(); 4070 MVT NVT = Node->getValueType(0); 4071 const uint64_t zero[] = {0, 0}; 4072 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); 4073 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 4074 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 4075 Tmp2 = DAG.getConstantFP(apf, VT); 4076 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)), 4077 Node->getOperand(0), Tmp2, ISD::SETLT); 4078 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0)); 4079 False = DAG.getNode(ISD::FP_TO_SINT, NVT, 4080 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0), 4081 Tmp2)); 4082 False = DAG.getNode(ISD::XOR, NVT, False, 4083 DAG.getConstant(x, NVT)); 4084 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False); 4085 break; 4086 } else { 4087 assert(0 && "Do not know how to expand FP_TO_SINT yet!"); 4088 } 4089 break; 4090 } 4091 break; 4092 case Expand: { 4093 MVT VT = Op.getValueType(); 4094 MVT OVT = Node->getOperand(0).getValueType(); 4095 // Convert ppcf128 to i32 4096 if (OVT == MVT::ppcf128 && VT == MVT::i32) { 4097 if (Node->getOpcode() == ISD::FP_TO_SINT) { 4098 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, 4099 Node->getOperand(0), DAG.getValueType(MVT::f64)); 4100 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result, 4101 DAG.getIntPtrConstant(1)); 4102 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result); 4103 } else { 4104 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; 4105 APFloat apf = APFloat(APInt(128, 2, TwoE31)); 4106 Tmp2 = DAG.getConstantFP(apf, OVT); 4107 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X 4108 // FIXME: generated code sucks. 4109 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2, 4110 DAG.getNode(ISD::ADD, MVT::i32, 4111 DAG.getNode(ISD::FP_TO_SINT, VT, 4112 DAG.getNode(ISD::FSUB, OVT, 4113 Node->getOperand(0), Tmp2)), 4114 DAG.getConstant(0x80000000, MVT::i32)), 4115 DAG.getNode(ISD::FP_TO_SINT, VT, 4116 Node->getOperand(0)), 4117 DAG.getCondCode(ISD::SETGE)); 4118 } 4119 break; 4120 } 4121 // Convert f32 / f64 to i32 / i64 / i128. 4122 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ? 4123 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT); 4124 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!"); 4125 SDValue Dummy; 4126 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy); 4127 break; 4128 } 4129 case Promote: 4130 Tmp1 = PromoteOp(Node->getOperand(0)); 4131 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1)); 4132 Result = LegalizeOp(Result); 4133 break; 4134 } 4135 break; 4136 4137 case ISD::FP_EXTEND: { 4138 MVT DstVT = Op.getValueType(); 4139 MVT SrcVT = Op.getOperand(0).getValueType(); 4140 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 4141 // The only other way we can lower this is to turn it into a STORE, 4142 // LOAD pair, targetting a temporary location (a stack slot). 4143 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT); 4144 break; 4145 } 4146 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4147 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4148 case Legal: 4149 Tmp1 = LegalizeOp(Node->getOperand(0)); 4150 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4151 break; 4152 case Promote: 4153 Tmp1 = PromoteOp(Node->getOperand(0)); 4154 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1); 4155 break; 4156 } 4157 break; 4158 } 4159 case ISD::FP_ROUND: { 4160 MVT DstVT = Op.getValueType(); 4161 MVT SrcVT = Op.getOperand(0).getValueType(); 4162 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) { 4163 if (SrcVT == MVT::ppcf128) { 4164 SDValue Lo; 4165 ExpandOp(Node->getOperand(0), Lo, Result); 4166 // Round it the rest of the way (e.g. to f32) if needed. 4167 if (DstVT!=MVT::f64) 4168 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1)); 4169 break; 4170 } 4171 // The only other way we can lower this is to turn it into a STORE, 4172 // LOAD pair, targetting a temporary location (a stack slot). 4173 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT); 4174 break; 4175 } 4176 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4177 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4178 case Legal: 4179 Tmp1 = LegalizeOp(Node->getOperand(0)); 4180 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 4181 break; 4182 case Promote: 4183 Tmp1 = PromoteOp(Node->getOperand(0)); 4184 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1, 4185 Node->getOperand(1)); 4186 break; 4187 } 4188 break; 4189 } 4190 case ISD::ANY_EXTEND: 4191 case ISD::ZERO_EXTEND: 4192 case ISD::SIGN_EXTEND: 4193 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4194 case Expand: assert(0 && "Shouldn't need to expand other operators here!"); 4195 case Legal: 4196 Tmp1 = LegalizeOp(Node->getOperand(0)); 4197 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4198 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) == 4199 TargetLowering::Custom) { 4200 Tmp1 = TLI.LowerOperation(Result, DAG); 4201 if (Tmp1.getNode()) Result = Tmp1; 4202 } 4203 break; 4204 case Promote: 4205 switch (Node->getOpcode()) { 4206 case ISD::ANY_EXTEND: 4207 Tmp1 = PromoteOp(Node->getOperand(0)); 4208 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1); 4209 break; 4210 case ISD::ZERO_EXTEND: 4211 Result = PromoteOp(Node->getOperand(0)); 4212 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 4213 Result = DAG.getZeroExtendInReg(Result, 4214 Node->getOperand(0).getValueType()); 4215 break; 4216 case ISD::SIGN_EXTEND: 4217 Result = PromoteOp(Node->getOperand(0)); 4218 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result); 4219 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4220 Result, 4221 DAG.getValueType(Node->getOperand(0).getValueType())); 4222 break; 4223 } 4224 } 4225 break; 4226 case ISD::FP_ROUND_INREG: 4227 case ISD::SIGN_EXTEND_INREG: { 4228 Tmp1 = LegalizeOp(Node->getOperand(0)); 4229 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 4230 4231 // If this operation is not supported, convert it to a shl/shr or load/store 4232 // pair. 4233 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) { 4234 default: assert(0 && "This action not supported for this op yet!"); 4235 case TargetLowering::Legal: 4236 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1)); 4237 break; 4238 case TargetLowering::Expand: 4239 // If this is an integer extend and shifts are supported, do that. 4240 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) { 4241 // NOTE: we could fall back on load/store here too for targets without 4242 // SAR. However, it is doubtful that any exist. 4243 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - 4244 ExtraVT.getSizeInBits(); 4245 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); 4246 Result = DAG.getNode(ISD::SHL, Node->getValueType(0), 4247 Node->getOperand(0), ShiftCst); 4248 Result = DAG.getNode(ISD::SRA, Node->getValueType(0), 4249 Result, ShiftCst); 4250 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) { 4251 // The only way we can lower this is to turn it into a TRUNCSTORE, 4252 // EXTLOAD pair, targetting a temporary location (a stack slot). 4253 4254 // NOTE: there is a choice here between constantly creating new stack 4255 // slots and always reusing the same one. We currently always create 4256 // new ones, as reuse may inhibit scheduling. 4257 Result = EmitStackConvert(Node->getOperand(0), ExtraVT, 4258 Node->getValueType(0)); 4259 } else { 4260 assert(0 && "Unknown op"); 4261 } 4262 break; 4263 } 4264 break; 4265 } 4266 case ISD::TRAMPOLINE: { 4267 SDValue Ops[6]; 4268 for (unsigned i = 0; i != 6; ++i) 4269 Ops[i] = LegalizeOp(Node->getOperand(i)); 4270 Result = DAG.UpdateNodeOperands(Result, Ops, 6); 4271 // The only option for this node is to custom lower it. 4272 Result = TLI.LowerOperation(Result, DAG); 4273 assert(Result.getNode() && "Should always custom lower!"); 4274 4275 // Since trampoline produces two values, make sure to remember that we 4276 // legalized both of them. 4277 Tmp1 = LegalizeOp(Result.getValue(1)); 4278 Result = LegalizeOp(Result); 4279 AddLegalizedOperand(SDValue(Node, 0), Result); 4280 AddLegalizedOperand(SDValue(Node, 1), Tmp1); 4281 return Op.getResNo() ? Tmp1 : Result; 4282 } 4283 case ISD::FLT_ROUNDS_: { 4284 MVT VT = Node->getValueType(0); 4285 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4286 default: assert(0 && "This action not supported for this op yet!"); 4287 case TargetLowering::Custom: 4288 Result = TLI.LowerOperation(Op, DAG); 4289 if (Result.getNode()) break; 4290 // Fall Thru 4291 case TargetLowering::Legal: 4292 // If this operation is not supported, lower it to constant 1 4293 Result = DAG.getConstant(1, VT); 4294 break; 4295 } 4296 break; 4297 } 4298 case ISD::TRAP: { 4299 MVT VT = Node->getValueType(0); 4300 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4301 default: assert(0 && "This action not supported for this op yet!"); 4302 case TargetLowering::Legal: 4303 Tmp1 = LegalizeOp(Node->getOperand(0)); 4304 Result = DAG.UpdateNodeOperands(Result, Tmp1); 4305 break; 4306 case TargetLowering::Custom: 4307 Result = TLI.LowerOperation(Op, DAG); 4308 if (Result.getNode()) break; 4309 // Fall Thru 4310 case TargetLowering::Expand: 4311 // If this operation is not supported, lower it to 'abort()' call 4312 Tmp1 = LegalizeOp(Node->getOperand(0)); 4313 TargetLowering::ArgListTy Args; 4314 std::pair<SDValue,SDValue> CallResult = 4315 TLI.LowerCallTo(Tmp1, Type::VoidTy, 4316 false, false, false, false, CallingConv::C, false, 4317 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 4318 Args, DAG); 4319 Result = CallResult.second; 4320 break; 4321 } 4322 break; 4323 } 4324 4325 case ISD::SADDO: 4326 case ISD::SSUBO: { 4327 MVT VT = Node->getValueType(0); 4328 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4329 default: assert(0 && "This action not supported for this op yet!"); 4330 case TargetLowering::Custom: 4331 Result = TLI.LowerOperation(Op, DAG); 4332 if (Result.getNode()) break; 4333 // FALLTHROUGH 4334 case TargetLowering::Legal: { 4335 SDValue LHS = LegalizeOp(Node->getOperand(0)); 4336 SDValue RHS = LegalizeOp(Node->getOperand(1)); 4337 4338 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 4339 ISD::ADD : ISD::SUB, LHS.getValueType(), 4340 LHS, RHS); 4341 MVT OType = Node->getValueType(1); 4342 4343 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 4344 4345 // LHSSign -> LHS >= 0 4346 // RHSSign -> RHS >= 0 4347 // SumSign -> Sum >= 0 4348 // 4349 // Add: 4350 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 4351 // Sub: 4352 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 4353 // 4354 SDValue LHSSign = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE); 4355 SDValue RHSSign = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE); 4356 SDValue SignsMatch = DAG.getSetCC(OType, LHSSign, RHSSign, 4357 Node->getOpcode() == ISD::SADDO ? 4358 ISD::SETEQ : ISD::SETNE); 4359 4360 SDValue SumSign = DAG.getSetCC(OType, Sum, Zero, ISD::SETGE); 4361 SDValue SumSignNE = DAG.getSetCC(OType, LHSSign, SumSign, ISD::SETNE); 4362 4363 SDValue Cmp = DAG.getNode(ISD::AND, OType, SignsMatch, SumSignNE); 4364 4365 MVT ValueVTs[] = { LHS.getValueType(), OType }; 4366 SDValue Ops[] = { Sum, Cmp }; 4367 4368 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2), 4369 &Ops[0], 2); 4370 SDNode *RNode = Result.getNode(); 4371 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0)); 4372 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1)); 4373 break; 4374 } 4375 } 4376 4377 break; 4378 } 4379 case ISD::UADDO: 4380 case ISD::USUBO: { 4381 MVT VT = Node->getValueType(0); 4382 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4383 default: assert(0 && "This action not supported for this op yet!"); 4384 case TargetLowering::Custom: 4385 Result = TLI.LowerOperation(Op, DAG); 4386 if (Result.getNode()) break; 4387 // FALLTHROUGH 4388 case TargetLowering::Legal: { 4389 SDValue LHS = LegalizeOp(Node->getOperand(0)); 4390 SDValue RHS = LegalizeOp(Node->getOperand(1)); 4391 4392 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 4393 ISD::ADD : ISD::SUB, LHS.getValueType(), 4394 LHS, RHS); 4395 MVT OType = Node->getValueType(1); 4396 SDValue Cmp = DAG.getSetCC(OType, Sum, LHS, 4397 Node->getOpcode () == ISD::UADDO ? 4398 ISD::SETULT : ISD::SETUGT); 4399 4400 MVT ValueVTs[] = { LHS.getValueType(), OType }; 4401 SDValue Ops[] = { Sum, Cmp }; 4402 4403 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2), 4404 &Ops[0], 2); 4405 SDNode *RNode = Result.getNode(); 4406 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0)); 4407 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1)); 4408 break; 4409 } 4410 } 4411 4412 break; 4413 } 4414 case ISD::SMULO: 4415 case ISD::UMULO: { 4416 MVT VT = Node->getValueType(0); 4417 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 4418 default: assert(0 && "This action is not supported at all!"); 4419 case TargetLowering::Custom: 4420 Result = TLI.LowerOperation(Op, DAG); 4421 if (Result.getNode()) break; 4422 // Fall Thru 4423 case TargetLowering::Legal: 4424 // FIXME: According to Hacker's Delight, this can be implemented in 4425 // target independent lowering, but it would be inefficient, since it 4426 // requires a division + a branch. 4427 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!"); 4428 break; 4429 } 4430 break; 4431 } 4432 4433 } 4434 4435 assert(Result.getValueType() == Op.getValueType() && 4436 "Bad legalization!"); 4437 4438 // Make sure that the generated code is itself legal. 4439 if (Result != Op) 4440 Result = LegalizeOp(Result); 4441 4442 // Note that LegalizeOp may be reentered even from single-use nodes, which 4443 // means that we always must cache transformed nodes. 4444 AddLegalizedOperand(Op, Result); 4445 return Result; 4446} 4447 4448/// PromoteOp - Given an operation that produces a value in an invalid type, 4449/// promote it to compute the value into a larger type. The produced value will 4450/// have the correct bits for the low portion of the register, but no guarantee 4451/// is made about the top bits: it may be zero, sign-extended, or garbage. 4452SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) { 4453 MVT VT = Op.getValueType(); 4454 MVT NVT = TLI.getTypeToTransformTo(VT); 4455 assert(getTypeAction(VT) == Promote && 4456 "Caller should expand or legalize operands that are not promotable!"); 4457 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() && 4458 "Cannot promote to smaller type!"); 4459 4460 SDValue Tmp1, Tmp2, Tmp3; 4461 SDValue Result; 4462 SDNode *Node = Op.getNode(); 4463 4464 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op); 4465 if (I != PromotedNodes.end()) return I->second; 4466 4467 switch (Node->getOpcode()) { 4468 case ISD::CopyFromReg: 4469 assert(0 && "CopyFromReg must be legal!"); 4470 default: 4471#ifndef NDEBUG 4472 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 4473#endif 4474 assert(0 && "Do not know how to promote this operator!"); 4475 abort(); 4476 case ISD::UNDEF: 4477 Result = DAG.getNode(ISD::UNDEF, NVT); 4478 break; 4479 case ISD::Constant: 4480 if (VT != MVT::i1) 4481 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op); 4482 else 4483 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op); 4484 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?"); 4485 break; 4486 case ISD::ConstantFP: 4487 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op); 4488 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?"); 4489 break; 4490 4491 case ISD::SETCC: 4492 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0))) 4493 && "SetCC type is not legal??"); 4494 Result = DAG.getNode(ISD::SETCC, 4495 TLI.getSetCCResultType(Node->getOperand(0)), 4496 Node->getOperand(0), Node->getOperand(1), 4497 Node->getOperand(2)); 4498 break; 4499 4500 case ISD::TRUNCATE: 4501 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4502 case Legal: 4503 Result = LegalizeOp(Node->getOperand(0)); 4504 assert(Result.getValueType().bitsGE(NVT) && 4505 "This truncation doesn't make sense!"); 4506 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT 4507 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result); 4508 break; 4509 case Promote: 4510 // The truncation is not required, because we don't guarantee anything 4511 // about high bits anyway. 4512 Result = PromoteOp(Node->getOperand(0)); 4513 break; 4514 case Expand: 4515 ExpandOp(Node->getOperand(0), Tmp1, Tmp2); 4516 // Truncate the low part of the expanded value to the result type 4517 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1); 4518 } 4519 break; 4520 case ISD::SIGN_EXTEND: 4521 case ISD::ZERO_EXTEND: 4522 case ISD::ANY_EXTEND: 4523 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4524 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!"); 4525 case Legal: 4526 // Input is legal? Just do extend all the way to the larger type. 4527 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4528 break; 4529 case Promote: 4530 // Promote the reg if it's smaller. 4531 Result = PromoteOp(Node->getOperand(0)); 4532 // The high bits are not guaranteed to be anything. Insert an extend. 4533 if (Node->getOpcode() == ISD::SIGN_EXTEND) 4534 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4535 DAG.getValueType(Node->getOperand(0).getValueType())); 4536 else if (Node->getOpcode() == ISD::ZERO_EXTEND) 4537 Result = DAG.getZeroExtendInReg(Result, 4538 Node->getOperand(0).getValueType()); 4539 break; 4540 } 4541 break; 4542 case ISD::CONVERT_RNDSAT: { 4543 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 4544 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 4545 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 4546 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 4547 "can only promote integers"); 4548 Result = DAG.getConvertRndSat(NVT, Node->getOperand(0), 4549 Node->getOperand(1), Node->getOperand(2), 4550 Node->getOperand(3), Node->getOperand(4), 4551 CvtCode); 4552 break; 4553 4554 } 4555 case ISD::BIT_CONVERT: 4556 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 4557 Node->getValueType(0)); 4558 Result = PromoteOp(Result); 4559 break; 4560 4561 case ISD::FP_EXTEND: 4562 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 4563 case ISD::FP_ROUND: 4564 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4565 case Expand: assert(0 && "BUG: Cannot expand FP regs!"); 4566 case Promote: assert(0 && "Unreachable with 2 FP types!"); 4567 case Legal: 4568 if (Node->getConstantOperandVal(1) == 0) { 4569 // Input is legal? Do an FP_ROUND_INREG. 4570 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0), 4571 DAG.getValueType(VT)); 4572 } else { 4573 // Just remove the truncate, it isn't affecting the value. 4574 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0), 4575 Node->getOperand(1)); 4576 } 4577 break; 4578 } 4579 break; 4580 case ISD::SINT_TO_FP: 4581 case ISD::UINT_TO_FP: 4582 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4583 case Legal: 4584 // No extra round required here. 4585 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0)); 4586 break; 4587 4588 case Promote: 4589 Result = PromoteOp(Node->getOperand(0)); 4590 if (Node->getOpcode() == ISD::SINT_TO_FP) 4591 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(), 4592 Result, 4593 DAG.getValueType(Node->getOperand(0).getValueType())); 4594 else 4595 Result = DAG.getZeroExtendInReg(Result, 4596 Node->getOperand(0).getValueType()); 4597 // No extra round required here. 4598 Result = DAG.getNode(Node->getOpcode(), NVT, Result); 4599 break; 4600 case Expand: 4601 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT, 4602 Node->getOperand(0)); 4603 // Round if we cannot tolerate excess precision. 4604 if (NoExcessFPPrecision) 4605 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4606 DAG.getValueType(VT)); 4607 break; 4608 } 4609 break; 4610 4611 case ISD::SIGN_EXTEND_INREG: 4612 Result = PromoteOp(Node->getOperand(0)); 4613 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result, 4614 Node->getOperand(1)); 4615 break; 4616 case ISD::FP_TO_SINT: 4617 case ISD::FP_TO_UINT: 4618 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4619 case Legal: 4620 case Expand: 4621 Tmp1 = Node->getOperand(0); 4622 break; 4623 case Promote: 4624 // The input result is prerounded, so we don't have to do anything 4625 // special. 4626 Tmp1 = PromoteOp(Node->getOperand(0)); 4627 break; 4628 } 4629 // If we're promoting a UINT to a larger size, check to see if the new node 4630 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 4631 // we can use that instead. This allows us to generate better code for 4632 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 4633 // legal, such as PowerPC. 4634 if (Node->getOpcode() == ISD::FP_TO_UINT && 4635 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 4636 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 4637 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){ 4638 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1); 4639 } else { 4640 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4641 } 4642 break; 4643 4644 case ISD::FABS: 4645 case ISD::FNEG: 4646 Tmp1 = PromoteOp(Node->getOperand(0)); 4647 assert(Tmp1.getValueType() == NVT); 4648 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4649 // NOTE: we do not have to do any extra rounding here for 4650 // NoExcessFPPrecision, because we know the input will have the appropriate 4651 // precision, and these operations don't modify precision at all. 4652 break; 4653 4654 case ISD::FLOG: 4655 case ISD::FLOG2: 4656 case ISD::FLOG10: 4657 case ISD::FEXP: 4658 case ISD::FEXP2: 4659 case ISD::FSQRT: 4660 case ISD::FSIN: 4661 case ISD::FCOS: 4662 case ISD::FTRUNC: 4663 case ISD::FFLOOR: 4664 case ISD::FCEIL: 4665 case ISD::FRINT: 4666 case ISD::FNEARBYINT: 4667 Tmp1 = PromoteOp(Node->getOperand(0)); 4668 assert(Tmp1.getValueType() == NVT); 4669 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4670 if (NoExcessFPPrecision) 4671 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4672 DAG.getValueType(VT)); 4673 break; 4674 4675 case ISD::FPOW: 4676 case ISD::FPOWI: { 4677 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall 4678 // directly as well, which may be better. 4679 Tmp1 = PromoteOp(Node->getOperand(0)); 4680 Tmp2 = Node->getOperand(1); 4681 if (Node->getOpcode() == ISD::FPOW) 4682 Tmp2 = PromoteOp(Tmp2); 4683 assert(Tmp1.getValueType() == NVT); 4684 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4685 if (NoExcessFPPrecision) 4686 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4687 DAG.getValueType(VT)); 4688 break; 4689 } 4690 4691 case ISD::ATOMIC_CMP_SWAP_8: 4692 case ISD::ATOMIC_CMP_SWAP_16: 4693 case ISD::ATOMIC_CMP_SWAP_32: 4694 case ISD::ATOMIC_CMP_SWAP_64: { 4695 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4696 Tmp2 = PromoteOp(Node->getOperand(2)); 4697 Tmp3 = PromoteOp(Node->getOperand(3)); 4698 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 4699 AtomNode->getBasePtr(), Tmp2, Tmp3, 4700 AtomNode->getSrcValue(), 4701 AtomNode->getAlignment()); 4702 // Remember that we legalized the chain. 4703 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4704 break; 4705 } 4706 case ISD::ATOMIC_LOAD_ADD_8: 4707 case ISD::ATOMIC_LOAD_SUB_8: 4708 case ISD::ATOMIC_LOAD_AND_8: 4709 case ISD::ATOMIC_LOAD_OR_8: 4710 case ISD::ATOMIC_LOAD_XOR_8: 4711 case ISD::ATOMIC_LOAD_NAND_8: 4712 case ISD::ATOMIC_LOAD_MIN_8: 4713 case ISD::ATOMIC_LOAD_MAX_8: 4714 case ISD::ATOMIC_LOAD_UMIN_8: 4715 case ISD::ATOMIC_LOAD_UMAX_8: 4716 case ISD::ATOMIC_SWAP_8: 4717 case ISD::ATOMIC_LOAD_ADD_16: 4718 case ISD::ATOMIC_LOAD_SUB_16: 4719 case ISD::ATOMIC_LOAD_AND_16: 4720 case ISD::ATOMIC_LOAD_OR_16: 4721 case ISD::ATOMIC_LOAD_XOR_16: 4722 case ISD::ATOMIC_LOAD_NAND_16: 4723 case ISD::ATOMIC_LOAD_MIN_16: 4724 case ISD::ATOMIC_LOAD_MAX_16: 4725 case ISD::ATOMIC_LOAD_UMIN_16: 4726 case ISD::ATOMIC_LOAD_UMAX_16: 4727 case ISD::ATOMIC_SWAP_16: 4728 case ISD::ATOMIC_LOAD_ADD_32: 4729 case ISD::ATOMIC_LOAD_SUB_32: 4730 case ISD::ATOMIC_LOAD_AND_32: 4731 case ISD::ATOMIC_LOAD_OR_32: 4732 case ISD::ATOMIC_LOAD_XOR_32: 4733 case ISD::ATOMIC_LOAD_NAND_32: 4734 case ISD::ATOMIC_LOAD_MIN_32: 4735 case ISD::ATOMIC_LOAD_MAX_32: 4736 case ISD::ATOMIC_LOAD_UMIN_32: 4737 case ISD::ATOMIC_LOAD_UMAX_32: 4738 case ISD::ATOMIC_SWAP_32: 4739 case ISD::ATOMIC_LOAD_ADD_64: 4740 case ISD::ATOMIC_LOAD_SUB_64: 4741 case ISD::ATOMIC_LOAD_AND_64: 4742 case ISD::ATOMIC_LOAD_OR_64: 4743 case ISD::ATOMIC_LOAD_XOR_64: 4744 case ISD::ATOMIC_LOAD_NAND_64: 4745 case ISD::ATOMIC_LOAD_MIN_64: 4746 case ISD::ATOMIC_LOAD_MAX_64: 4747 case ISD::ATOMIC_LOAD_UMIN_64: 4748 case ISD::ATOMIC_LOAD_UMAX_64: 4749 case ISD::ATOMIC_SWAP_64: { 4750 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node); 4751 Tmp2 = PromoteOp(Node->getOperand(2)); 4752 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(), 4753 AtomNode->getBasePtr(), Tmp2, 4754 AtomNode->getSrcValue(), 4755 AtomNode->getAlignment()); 4756 // Remember that we legalized the chain. 4757 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4758 break; 4759 } 4760 4761 case ISD::AND: 4762 case ISD::OR: 4763 case ISD::XOR: 4764 case ISD::ADD: 4765 case ISD::SUB: 4766 case ISD::MUL: 4767 // The input may have strange things in the top bits of the registers, but 4768 // these operations don't care. They may have weird bits going out, but 4769 // that too is okay if they are integer operations. 4770 Tmp1 = PromoteOp(Node->getOperand(0)); 4771 Tmp2 = PromoteOp(Node->getOperand(1)); 4772 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4773 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4774 break; 4775 case ISD::FADD: 4776 case ISD::FSUB: 4777 case ISD::FMUL: 4778 Tmp1 = PromoteOp(Node->getOperand(0)); 4779 Tmp2 = PromoteOp(Node->getOperand(1)); 4780 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT); 4781 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4782 4783 // Floating point operations will give excess precision that we may not be 4784 // able to tolerate. If we DO allow excess precision, just leave it, 4785 // otherwise excise it. 4786 // FIXME: Why would we need to round FP ops more than integer ones? 4787 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C)) 4788 if (NoExcessFPPrecision) 4789 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4790 DAG.getValueType(VT)); 4791 break; 4792 4793 case ISD::SDIV: 4794 case ISD::SREM: 4795 // These operators require that their input be sign extended. 4796 Tmp1 = PromoteOp(Node->getOperand(0)); 4797 Tmp2 = PromoteOp(Node->getOperand(1)); 4798 if (NVT.isInteger()) { 4799 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4800 DAG.getValueType(VT)); 4801 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 4802 DAG.getValueType(VT)); 4803 } 4804 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4805 4806 // Perform FP_ROUND: this is probably overly pessimistic. 4807 if (NVT.isFloatingPoint() && NoExcessFPPrecision) 4808 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4809 DAG.getValueType(VT)); 4810 break; 4811 case ISD::FDIV: 4812 case ISD::FREM: 4813 case ISD::FCOPYSIGN: 4814 // These operators require that their input be fp extended. 4815 switch (getTypeAction(Node->getOperand(0).getValueType())) { 4816 case Expand: assert(0 && "not implemented"); 4817 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break; 4818 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break; 4819 } 4820 switch (getTypeAction(Node->getOperand(1).getValueType())) { 4821 case Expand: assert(0 && "not implemented"); 4822 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break; 4823 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break; 4824 } 4825 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4826 4827 // Perform FP_ROUND: this is probably overly pessimistic. 4828 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN) 4829 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, 4830 DAG.getValueType(VT)); 4831 break; 4832 4833 case ISD::UDIV: 4834 case ISD::UREM: 4835 // These operators require that their input be zero extended. 4836 Tmp1 = PromoteOp(Node->getOperand(0)); 4837 Tmp2 = PromoteOp(Node->getOperand(1)); 4838 assert(NVT.isInteger() && "Operators don't apply to FP!"); 4839 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4840 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 4841 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2); 4842 break; 4843 4844 case ISD::SHL: 4845 Tmp1 = PromoteOp(Node->getOperand(0)); 4846 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1)); 4847 break; 4848 case ISD::SRA: 4849 // The input value must be properly sign extended. 4850 Tmp1 = PromoteOp(Node->getOperand(0)); 4851 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 4852 DAG.getValueType(VT)); 4853 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1)); 4854 break; 4855 case ISD::SRL: 4856 // The input value must be properly zero extended. 4857 Tmp1 = PromoteOp(Node->getOperand(0)); 4858 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 4859 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1)); 4860 break; 4861 4862 case ISD::VAARG: 4863 Tmp1 = Node->getOperand(0); // Get the chain. 4864 Tmp2 = Node->getOperand(1); // Get the pointer. 4865 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) { 4866 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2)); 4867 Result = TLI.LowerOperation(Tmp3, DAG); 4868 } else { 4869 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 4870 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0); 4871 // Increment the pointer, VAList, to the next vaarg 4872 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 4873 DAG.getConstant(VT.getSizeInBits()/8, 4874 TLI.getPointerTy())); 4875 // Store the incremented VAList to the legalized pointer 4876 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0); 4877 // Load the actual argument out of the pointer VAList 4878 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT); 4879 } 4880 // Remember that we legalized the chain. 4881 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4882 break; 4883 4884 case ISD::LOAD: { 4885 LoadSDNode *LD = cast<LoadSDNode>(Node); 4886 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node) 4887 ? ISD::EXTLOAD : LD->getExtensionType(); 4888 Result = DAG.getExtLoad(ExtType, NVT, 4889 LD->getChain(), LD->getBasePtr(), 4890 LD->getSrcValue(), LD->getSrcValueOffset(), 4891 LD->getMemoryVT(), 4892 LD->isVolatile(), 4893 LD->getAlignment()); 4894 // Remember that we legalized the chain. 4895 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 4896 break; 4897 } 4898 case ISD::SELECT: { 4899 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0 4900 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1 4901 4902 MVT VT2 = Tmp2.getValueType(); 4903 assert(VT2 == Tmp3.getValueType() 4904 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match"); 4905 // Ensure that the resulting node is at least the same size as the operands' 4906 // value types, because we cannot assume that TLI.getSetCCValueType() is 4907 // constant. 4908 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3); 4909 break; 4910 } 4911 case ISD::SELECT_CC: 4912 Tmp2 = PromoteOp(Node->getOperand(2)); // True 4913 Tmp3 = PromoteOp(Node->getOperand(3)); // False 4914 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 4915 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4)); 4916 break; 4917 case ISD::BSWAP: 4918 Tmp1 = Node->getOperand(0); 4919 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1); 4920 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1); 4921 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, 4922 DAG.getConstant(NVT.getSizeInBits() - 4923 VT.getSizeInBits(), 4924 TLI.getShiftAmountTy())); 4925 break; 4926 case ISD::CTPOP: 4927 case ISD::CTTZ: 4928 case ISD::CTLZ: 4929 // Zero extend the argument 4930 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 4931 // Perform the larger operation, then subtract if needed. 4932 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1); 4933 switch(Node->getOpcode()) { 4934 case ISD::CTPOP: 4935 Result = Tmp1; 4936 break; 4937 case ISD::CTTZ: 4938 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT) 4939 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, 4940 DAG.getConstant(NVT.getSizeInBits(), NVT), 4941 ISD::SETEQ); 4942 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2, 4943 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1); 4944 break; 4945 case ISD::CTLZ: 4946 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 4947 Result = DAG.getNode(ISD::SUB, NVT, Tmp1, 4948 DAG.getConstant(NVT.getSizeInBits() - 4949 VT.getSizeInBits(), NVT)); 4950 break; 4951 } 4952 break; 4953 case ISD::EXTRACT_SUBVECTOR: 4954 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op)); 4955 break; 4956 case ISD::EXTRACT_VECTOR_ELT: 4957 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op)); 4958 break; 4959 } 4960 4961 assert(Result.getNode() && "Didn't set a result!"); 4962 4963 // Make sure the result is itself legal. 4964 Result = LegalizeOp(Result); 4965 4966 // Remember that we promoted this! 4967 AddPromotedOperand(Op, Result); 4968 return Result; 4969} 4970 4971/// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into 4972/// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic, 4973/// based on the vector type. The return type of this matches the element type 4974/// of the vector, which may not be legal for the target. 4975SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) { 4976 // We know that operand #0 is the Vec vector. If the index is a constant 4977 // or if the invec is a supported hardware type, we can use it. Otherwise, 4978 // lower to a store then an indexed load. 4979 SDValue Vec = Op.getOperand(0); 4980 SDValue Idx = Op.getOperand(1); 4981 4982 MVT TVT = Vec.getValueType(); 4983 unsigned NumElems = TVT.getVectorNumElements(); 4984 4985 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) { 4986 default: assert(0 && "This action is not supported yet!"); 4987 case TargetLowering::Custom: { 4988 Vec = LegalizeOp(Vec); 4989 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4990 SDValue Tmp3 = TLI.LowerOperation(Op, DAG); 4991 if (Tmp3.getNode()) 4992 return Tmp3; 4993 break; 4994 } 4995 case TargetLowering::Legal: 4996 if (isTypeLegal(TVT)) { 4997 Vec = LegalizeOp(Vec); 4998 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 4999 return Op; 5000 } 5001 break; 5002 case TargetLowering::Promote: 5003 assert(TVT.isVector() && "not vector type"); 5004 // fall thru to expand since vectors are by default are promote 5005 case TargetLowering::Expand: 5006 break; 5007 } 5008 5009 if (NumElems == 1) { 5010 // This must be an access of the only element. Return it. 5011 Op = ScalarizeVectorOp(Vec); 5012 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) { 5013 unsigned NumLoElts = 1 << Log2_32(NumElems-1); 5014 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 5015 SDValue Lo, Hi; 5016 SplitVectorOp(Vec, Lo, Hi); 5017 if (CIdx->getZExtValue() < NumLoElts) { 5018 Vec = Lo; 5019 } else { 5020 Vec = Hi; 5021 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts, 5022 Idx.getValueType()); 5023 } 5024 5025 // It's now an extract from the appropriate high or low part. Recurse. 5026 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 5027 Op = ExpandEXTRACT_VECTOR_ELT(Op); 5028 } else { 5029 // Store the value to a temporary stack slot, then LOAD the scalar 5030 // element back out. 5031 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 5032 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0); 5033 5034 // Add the offset to the index. 5035 unsigned EltSize = Op.getValueType().getSizeInBits()/8; 5036 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx, 5037 DAG.getConstant(EltSize, Idx.getValueType())); 5038 5039 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 5040 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx); 5041 else 5042 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx); 5043 5044 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr); 5045 5046 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0); 5047 } 5048 return Op; 5049} 5050 5051/// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now 5052/// we assume the operation can be split if it is not already legal. 5053SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) { 5054 // We know that operand #0 is the Vec vector. For now we assume the index 5055 // is a constant and that the extracted result is a supported hardware type. 5056 SDValue Vec = Op.getOperand(0); 5057 SDValue Idx = LegalizeOp(Op.getOperand(1)); 5058 5059 unsigned NumElems = Vec.getValueType().getVectorNumElements(); 5060 5061 if (NumElems == Op.getValueType().getVectorNumElements()) { 5062 // This must be an access of the desired vector length. Return it. 5063 return Vec; 5064 } 5065 5066 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx); 5067 SDValue Lo, Hi; 5068 SplitVectorOp(Vec, Lo, Hi); 5069 if (CIdx->getZExtValue() < NumElems/2) { 5070 Vec = Lo; 5071 } else { 5072 Vec = Hi; 5073 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2, 5074 Idx.getValueType()); 5075 } 5076 5077 // It's now an extract from the appropriate high or low part. Recurse. 5078 Op = DAG.UpdateNodeOperands(Op, Vec, Idx); 5079 return ExpandEXTRACT_SUBVECTOR(Op); 5080} 5081 5082/// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC 5083/// with condition CC on the current target. This usually involves legalizing 5084/// or promoting the arguments. In the case where LHS and RHS must be expanded, 5085/// there may be no choice but to create a new SetCC node to represent the 5086/// legalized value of setcc lhs, rhs. In this case, the value is returned in 5087/// LHS, and the SDValue returned in RHS has a nil SDNode value. 5088void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS, 5089 SDValue &RHS, 5090 SDValue &CC) { 5091 SDValue Tmp1, Tmp2, Tmp3, Result; 5092 5093 switch (getTypeAction(LHS.getValueType())) { 5094 case Legal: 5095 Tmp1 = LegalizeOp(LHS); // LHS 5096 Tmp2 = LegalizeOp(RHS); // RHS 5097 break; 5098 case Promote: 5099 Tmp1 = PromoteOp(LHS); // LHS 5100 Tmp2 = PromoteOp(RHS); // RHS 5101 5102 // If this is an FP compare, the operands have already been extended. 5103 if (LHS.getValueType().isInteger()) { 5104 MVT VT = LHS.getValueType(); 5105 MVT NVT = TLI.getTypeToTransformTo(VT); 5106 5107 // Otherwise, we have to insert explicit sign or zero extends. Note 5108 // that we could insert sign extends for ALL conditions, but zero extend 5109 // is cheaper on many machines (an AND instead of two shifts), so prefer 5110 // it. 5111 switch (cast<CondCodeSDNode>(CC)->get()) { 5112 default: assert(0 && "Unknown integer comparison!"); 5113 case ISD::SETEQ: 5114 case ISD::SETNE: 5115 case ISD::SETUGE: 5116 case ISD::SETUGT: 5117 case ISD::SETULE: 5118 case ISD::SETULT: 5119 // ALL of these operations will work if we either sign or zero extend 5120 // the operands (including the unsigned comparisons!). Zero extend is 5121 // usually a simpler/cheaper operation, so prefer it. 5122 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT); 5123 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT); 5124 break; 5125 case ISD::SETGE: 5126 case ISD::SETGT: 5127 case ISD::SETLT: 5128 case ISD::SETLE: 5129 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, 5130 DAG.getValueType(VT)); 5131 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, 5132 DAG.getValueType(VT)); 5133 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes. 5134 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes. 5135 break; 5136 } 5137 } 5138 break; 5139 case Expand: { 5140 MVT VT = LHS.getValueType(); 5141 if (VT == MVT::f32 || VT == MVT::f64) { 5142 // Expand into one or more soft-fp libcall(s). 5143 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; 5144 switch (cast<CondCodeSDNode>(CC)->get()) { 5145 case ISD::SETEQ: 5146 case ISD::SETOEQ: 5147 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 5148 break; 5149 case ISD::SETNE: 5150 case ISD::SETUNE: 5151 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; 5152 break; 5153 case ISD::SETGE: 5154 case ISD::SETOGE: 5155 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 5156 break; 5157 case ISD::SETLT: 5158 case ISD::SETOLT: 5159 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5160 break; 5161 case ISD::SETLE: 5162 case ISD::SETOLE: 5163 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 5164 break; 5165 case ISD::SETGT: 5166 case ISD::SETOGT: 5167 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 5168 break; 5169 case ISD::SETUO: 5170 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 5171 break; 5172 case ISD::SETO: 5173 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; 5174 break; 5175 default: 5176 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; 5177 switch (cast<CondCodeSDNode>(CC)->get()) { 5178 case ISD::SETONE: 5179 // SETONE = SETOLT | SETOGT 5180 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5181 // Fallthrough 5182 case ISD::SETUGT: 5183 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; 5184 break; 5185 case ISD::SETUGE: 5186 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; 5187 break; 5188 case ISD::SETULT: 5189 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; 5190 break; 5191 case ISD::SETULE: 5192 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; 5193 break; 5194 case ISD::SETUEQ: 5195 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; 5196 break; 5197 default: assert(0 && "Unsupported FP setcc!"); 5198 } 5199 } 5200 5201 SDValue Dummy; 5202 SDValue Ops[2] = { LHS, RHS }; 5203 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(), 5204 false /*sign irrelevant*/, Dummy); 5205 Tmp2 = DAG.getConstant(0, MVT::i32); 5206 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1)); 5207 if (LC2 != RTLIB::UNKNOWN_LIBCALL) { 5208 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, 5209 CC); 5210 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(), 5211 false /*sign irrelevant*/, Dummy); 5212 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2, 5213 DAG.getCondCode(TLI.getCmpLibcallCC(LC2))); 5214 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 5215 Tmp2 = SDValue(); 5216 } 5217 LHS = LegalizeOp(Tmp1); 5218 RHS = Tmp2; 5219 return; 5220 } 5221 5222 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 5223 ExpandOp(LHS, LHSLo, LHSHi); 5224 ExpandOp(RHS, RHSLo, RHSHi); 5225 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 5226 5227 if (VT==MVT::ppcf128) { 5228 // FIXME: This generated code sucks. We want to generate 5229 // FCMPU crN, hi1, hi2 5230 // BNE crN, L: 5231 // FCMPU crN, lo1, lo2 5232 // The following can be improved, but not that much. 5233 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 5234 ISD::SETOEQ); 5235 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode); 5236 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 5237 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 5238 ISD::SETUNE); 5239 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode); 5240 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2); 5241 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3); 5242 Tmp2 = SDValue(); 5243 break; 5244 } 5245 5246 switch (CCCode) { 5247 case ISD::SETEQ: 5248 case ISD::SETNE: 5249 if (RHSLo == RHSHi) 5250 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) 5251 if (RHSCST->isAllOnesValue()) { 5252 // Comparison to -1. 5253 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 5254 Tmp2 = RHSLo; 5255 break; 5256 } 5257 5258 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 5259 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 5260 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2); 5261 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 5262 break; 5263 default: 5264 // If this is a comparison of the sign bit, just look at the top part. 5265 // X > -1, x < 0 5266 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS)) 5267 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT && 5268 CST->isNullValue()) || // X < 0 5269 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT && 5270 CST->isAllOnesValue())) { // X > -1 5271 Tmp1 = LHSHi; 5272 Tmp2 = RHSHi; 5273 break; 5274 } 5275 5276 // FIXME: This generated code sucks. 5277 ISD::CondCode LowCC; 5278 switch (CCCode) { 5279 default: assert(0 && "Unknown integer setcc!"); 5280 case ISD::SETLT: 5281 case ISD::SETULT: LowCC = ISD::SETULT; break; 5282 case ISD::SETGT: 5283 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 5284 case ISD::SETLE: 5285 case ISD::SETULE: LowCC = ISD::SETULE; break; 5286 case ISD::SETGE: 5287 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 5288 } 5289 5290 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 5291 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 5292 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 5293 5294 // NOTE: on targets without efficient SELECT of bools, we can always use 5295 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 5296 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 5297 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, 5298 LowCC, false, DagCombineInfo); 5299 if (!Tmp1.getNode()) 5300 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 5301 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 5302 CCCode, false, DagCombineInfo); 5303 if (!Tmp2.getNode()) 5304 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, 5305 RHSHi,CC); 5306 5307 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 5308 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 5309 if ((Tmp1C && Tmp1C->isNullValue()) || 5310 (Tmp2C && Tmp2C->isNullValue() && 5311 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 5312 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 5313 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 5314 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 5315 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 5316 // low part is known false, returns high part. 5317 // For LE / GE, if high part is known false, ignore the low part. 5318 // For LT / GT, if high part is known true, ignore the low part. 5319 Tmp1 = Tmp2; 5320 Tmp2 = SDValue(); 5321 } else { 5322 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 5323 ISD::SETEQ, false, DagCombineInfo); 5324 if (!Result.getNode()) 5325 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 5326 ISD::SETEQ); 5327 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 5328 Result, Tmp1, Tmp2)); 5329 Tmp1 = Result; 5330 Tmp2 = SDValue(); 5331 } 5332 } 5333 } 5334 } 5335 LHS = Tmp1; 5336 RHS = Tmp2; 5337} 5338 5339/// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 5340/// condition code CC on the current target. This routine assumes LHS and rHS 5341/// have already been legalized by LegalizeSetCCOperands. It expands SETCC with 5342/// illegal condition code into AND / OR of multiple SETCC values. 5343void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, 5344 SDValue &LHS, SDValue &RHS, 5345 SDValue &CC) { 5346 MVT OpVT = LHS.getValueType(); 5347 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 5348 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 5349 default: assert(0 && "Unknown condition code action!"); 5350 case TargetLowering::Legal: 5351 // Nothing to do. 5352 break; 5353 case TargetLowering::Expand: { 5354 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 5355 unsigned Opc = 0; 5356 switch (CCCode) { 5357 default: assert(0 && "Don't know how to expand this condition!"); abort(); 5358 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 5359 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 5360 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5361 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 5362 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5363 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 5364 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5365 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5366 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5367 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5368 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5369 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 5370 // FIXME: Implement more expansions. 5371 } 5372 5373 SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1); 5374 SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2); 5375 LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2); 5376 RHS = SDValue(); 5377 CC = SDValue(); 5378 break; 5379 } 5380 } 5381} 5382 5383/// EmitStackConvert - Emit a store/load combination to the stack. This stores 5384/// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 5385/// a load from the stack slot to DestVT, extending it if needed. 5386/// The resultant code need not be legal. 5387SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 5388 MVT SlotVT, 5389 MVT DestVT) { 5390 // Create the stack frame object. 5391 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment( 5392 SrcOp.getValueType().getTypeForMVT()); 5393 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 5394 5395 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 5396 int SPFI = StackPtrFI->getIndex(); 5397 5398 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 5399 unsigned SlotSize = SlotVT.getSizeInBits(); 5400 unsigned DestSize = DestVT.getSizeInBits(); 5401 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment( 5402 DestVT.getTypeForMVT()); 5403 5404 // Emit a store to the stack slot. Use a truncstore if the input value is 5405 // later than DestVT. 5406 SDValue Store; 5407 5408 if (SrcSize > SlotSize) 5409 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr, 5410 PseudoSourceValue::getFixedStack(SPFI), 0, 5411 SlotVT, false, SrcAlign); 5412 else { 5413 assert(SrcSize == SlotSize && "Invalid store"); 5414 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, 5415 PseudoSourceValue::getFixedStack(SPFI), 0, 5416 false, SrcAlign); 5417 } 5418 5419 // Result is a load from the stack slot. 5420 if (SlotSize == DestSize) 5421 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign); 5422 5423 assert(SlotSize < DestSize && "Unknown extension!"); 5424 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT, 5425 false, DestAlign); 5426} 5427 5428SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 5429 // Create a vector sized/aligned stack slot, store the value to element #0, 5430 // then load the whole vector back out. 5431 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 5432 5433 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 5434 int SPFI = StackPtrFI->getIndex(); 5435 5436 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr, 5437 PseudoSourceValue::getFixedStack(SPFI), 0); 5438 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, 5439 PseudoSourceValue::getFixedStack(SPFI), 0); 5440} 5441 5442 5443/// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 5444/// support the operation, but do support the resultant vector type. 5445SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 5446 5447 // If the only non-undef value is the low element, turn this into a 5448 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 5449 unsigned NumElems = Node->getNumOperands(); 5450 bool isOnlyLowElement = true; 5451 SDValue SplatValue = Node->getOperand(0); 5452 5453 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t> 5454 // and use a bitmask instead of a list of elements. 5455 std::map<SDValue, std::vector<unsigned> > Values; 5456 Values[SplatValue].push_back(0); 5457 bool isConstant = true; 5458 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) && 5459 SplatValue.getOpcode() != ISD::UNDEF) 5460 isConstant = false; 5461 5462 for (unsigned i = 1; i < NumElems; ++i) { 5463 SDValue V = Node->getOperand(i); 5464 Values[V].push_back(i); 5465 if (V.getOpcode() != ISD::UNDEF) 5466 isOnlyLowElement = false; 5467 if (SplatValue != V) 5468 SplatValue = SDValue(0,0); 5469 5470 // If this isn't a constant element or an undef, we can't use a constant 5471 // pool load. 5472 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) && 5473 V.getOpcode() != ISD::UNDEF) 5474 isConstant = false; 5475 } 5476 5477 if (isOnlyLowElement) { 5478 // If the low element is an undef too, then this whole things is an undef. 5479 if (Node->getOperand(0).getOpcode() == ISD::UNDEF) 5480 return DAG.getNode(ISD::UNDEF, Node->getValueType(0)); 5481 // Otherwise, turn this into a scalar_to_vector node. 5482 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), 5483 Node->getOperand(0)); 5484 } 5485 5486 // If all elements are constants, create a load from the constant pool. 5487 if (isConstant) { 5488 MVT VT = Node->getValueType(0); 5489 std::vector<Constant*> CV; 5490 for (unsigned i = 0, e = NumElems; i != e; ++i) { 5491 if (ConstantFPSDNode *V = 5492 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 5493 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 5494 } else if (ConstantSDNode *V = 5495 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 5496 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 5497 } else { 5498 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 5499 const Type *OpNTy = 5500 Node->getOperand(0).getValueType().getTypeForMVT(); 5501 CV.push_back(UndefValue::get(OpNTy)); 5502 } 5503 } 5504 Constant *CP = ConstantVector::get(CV); 5505 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 5506 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5507 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, 5508 PseudoSourceValue::getConstantPool(), 0, 5509 false, Alignment); 5510 } 5511 5512 if (SplatValue.getNode()) { // Splat of one value? 5513 // Build the shuffle constant vector: <0, 0, 0, 0> 5514 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5515 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType()); 5516 std::vector<SDValue> ZeroVec(NumElems, Zero); 5517 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5518 &ZeroVec[0], ZeroVec.size()); 5519 5520 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it. 5521 if (isShuffleLegal(Node->getValueType(0), SplatMask)) { 5522 // Get the splatted value into the low element of a vector register. 5523 SDValue LowValVec = 5524 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue); 5525 5526 // Return shuffle(LowValVec, undef, <0,0,0,0>) 5527 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec, 5528 DAG.getNode(ISD::UNDEF, Node->getValueType(0)), 5529 SplatMask); 5530 } 5531 } 5532 5533 // If there are only two unique elements, we may be able to turn this into a 5534 // vector shuffle. 5535 if (Values.size() == 2) { 5536 // Get the two values in deterministic order. 5537 SDValue Val1 = Node->getOperand(1); 5538 SDValue Val2; 5539 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin(); 5540 if (MI->first != Val1) 5541 Val2 = MI->first; 5542 else 5543 Val2 = (++MI)->first; 5544 5545 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our 5546 // vector shuffle has the undef vector on the RHS. 5547 if (Val1.getOpcode() == ISD::UNDEF) 5548 std::swap(Val1, Val2); 5549 5550 // Build the shuffle constant vector: e.g. <0, 4, 0, 4> 5551 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems); 5552 MVT MaskEltVT = MaskVT.getVectorElementType(); 5553 std::vector<SDValue> MaskVec(NumElems); 5554 5555 // Set elements of the shuffle mask for Val1. 5556 std::vector<unsigned> &Val1Elts = Values[Val1]; 5557 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i) 5558 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT); 5559 5560 // Set elements of the shuffle mask for Val2. 5561 std::vector<unsigned> &Val2Elts = Values[Val2]; 5562 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i) 5563 if (Val2.getOpcode() != ISD::UNDEF) 5564 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT); 5565 else 5566 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT); 5567 5568 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5569 &MaskVec[0], MaskVec.size()); 5570 5571 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it. 5572 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) && 5573 isShuffleLegal(Node->getValueType(0), ShuffleMask)) { 5574 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1); 5575 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2); 5576 SDValue Ops[] = { Val1, Val2, ShuffleMask }; 5577 5578 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>) 5579 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3); 5580 } 5581 } 5582 5583 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently 5584 // aligned object on the stack, store each element into it, then load 5585 // the result as a vector. 5586 MVT VT = Node->getValueType(0); 5587 // Create the stack frame object. 5588 SDValue FIPtr = DAG.CreateStackTemporary(VT); 5589 5590 // Emit a store of each element to the stack slot. 5591 SmallVector<SDValue, 8> Stores; 5592 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8; 5593 // Store (in the right endianness) the elements to memory. 5594 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5595 // Ignore undef elements. 5596 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5597 5598 unsigned Offset = TypeByteSize*i; 5599 5600 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 5601 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx); 5602 5603 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx, 5604 NULL, 0)); 5605 } 5606 5607 SDValue StoreChain; 5608 if (!Stores.empty()) // Not all undef elements? 5609 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5610 &Stores[0], Stores.size()); 5611 else 5612 StoreChain = DAG.getEntryNode(); 5613 5614 // Result is a load from the stack slot. 5615 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0); 5616} 5617 5618void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp, 5619 SDValue Op, SDValue Amt, 5620 SDValue &Lo, SDValue &Hi) { 5621 // Expand the subcomponents. 5622 SDValue LHSL, LHSH; 5623 ExpandOp(Op, LHSL, LHSH); 5624 5625 SDValue Ops[] = { LHSL, LHSH, Amt }; 5626 MVT VT = LHSL.getValueType(); 5627 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 5628 Hi = Lo.getValue(1); 5629} 5630 5631 5632/// ExpandShift - Try to find a clever way to expand this shift operation out to 5633/// smaller elements. If we can't find a way that is more efficient than a 5634/// libcall on this target, return false. Otherwise, return true with the 5635/// low-parts expanded into Lo and Hi. 5636bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt, 5637 SDValue &Lo, SDValue &Hi) { 5638 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && 5639 "This is not a shift!"); 5640 5641 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); 5642 SDValue ShAmt = LegalizeOp(Amt); 5643 MVT ShTy = ShAmt.getValueType(); 5644 unsigned ShBits = ShTy.getSizeInBits(); 5645 unsigned VTBits = Op.getValueType().getSizeInBits(); 5646 unsigned NVTBits = NVT.getSizeInBits(); 5647 5648 // Handle the case when Amt is an immediate. 5649 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) { 5650 unsigned Cst = CN->getZExtValue(); 5651 // Expand the incoming operand to be shifted, so that we have its parts 5652 SDValue InL, InH; 5653 ExpandOp(Op, InL, InH); 5654 switch(Opc) { 5655 case ISD::SHL: 5656 if (Cst > VTBits) { 5657 Lo = DAG.getConstant(0, NVT); 5658 Hi = DAG.getConstant(0, NVT); 5659 } else if (Cst > NVTBits) { 5660 Lo = DAG.getConstant(0, NVT); 5661 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy)); 5662 } else if (Cst == NVTBits) { 5663 Lo = DAG.getConstant(0, NVT); 5664 Hi = InL; 5665 } else { 5666 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy)); 5667 Hi = DAG.getNode(ISD::OR, NVT, 5668 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)), 5669 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy))); 5670 } 5671 return true; 5672 case ISD::SRL: 5673 if (Cst > VTBits) { 5674 Lo = DAG.getConstant(0, NVT); 5675 Hi = DAG.getConstant(0, NVT); 5676 } else if (Cst > NVTBits) { 5677 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy)); 5678 Hi = DAG.getConstant(0, NVT); 5679 } else if (Cst == NVTBits) { 5680 Lo = InH; 5681 Hi = DAG.getConstant(0, NVT); 5682 } else { 5683 Lo = DAG.getNode(ISD::OR, NVT, 5684 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5685 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5686 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy)); 5687 } 5688 return true; 5689 case ISD::SRA: 5690 if (Cst > VTBits) { 5691 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 5692 DAG.getConstant(NVTBits-1, ShTy)); 5693 } else if (Cst > NVTBits) { 5694 Lo = DAG.getNode(ISD::SRA, NVT, InH, 5695 DAG.getConstant(Cst-NVTBits, ShTy)); 5696 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5697 DAG.getConstant(NVTBits-1, ShTy)); 5698 } else if (Cst == NVTBits) { 5699 Lo = InH; 5700 Hi = DAG.getNode(ISD::SRA, NVT, InH, 5701 DAG.getConstant(NVTBits-1, ShTy)); 5702 } else { 5703 Lo = DAG.getNode(ISD::OR, NVT, 5704 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)), 5705 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy))); 5706 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy)); 5707 } 5708 return true; 5709 } 5710 } 5711 5712 // Okay, the shift amount isn't constant. However, if we can tell that it is 5713 // >= 32 or < 32, we can still simplify it, without knowing the actual value. 5714 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 5715 APInt KnownZero, KnownOne; 5716 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne); 5717 5718 // If we know that if any of the high bits of the shift amount are one, then 5719 // we can do this as a couple of simple shifts. 5720 if (KnownOne.intersects(Mask)) { 5721 // Mask out the high bit, which we know is set. 5722 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt, 5723 DAG.getConstant(~Mask, Amt.getValueType())); 5724 5725 // Expand the incoming operand to be shifted, so that we have its parts 5726 SDValue InL, InH; 5727 ExpandOp(Op, InL, InH); 5728 switch(Opc) { 5729 case ISD::SHL: 5730 Lo = DAG.getConstant(0, NVT); // Low part is zero. 5731 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 5732 return true; 5733 case ISD::SRL: 5734 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 5735 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 5736 return true; 5737 case ISD::SRA: 5738 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 5739 DAG.getConstant(NVTBits-1, Amt.getValueType())); 5740 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 5741 return true; 5742 } 5743 } 5744 5745 // If we know that the high bits of the shift amount are all zero, then we can 5746 // do this as a couple of simple shifts. 5747 if ((KnownZero & Mask) == Mask) { 5748 // Compute 32-amt. 5749 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(), 5750 DAG.getConstant(NVTBits, Amt.getValueType()), 5751 Amt); 5752 5753 // Expand the incoming operand to be shifted, so that we have its parts 5754 SDValue InL, InH; 5755 ExpandOp(Op, InL, InH); 5756 switch(Opc) { 5757 case ISD::SHL: 5758 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt); 5759 Hi = DAG.getNode(ISD::OR, NVT, 5760 DAG.getNode(ISD::SHL, NVT, InH, Amt), 5761 DAG.getNode(ISD::SRL, NVT, InL, Amt2)); 5762 return true; 5763 case ISD::SRL: 5764 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt); 5765 Lo = DAG.getNode(ISD::OR, NVT, 5766 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5767 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5768 return true; 5769 case ISD::SRA: 5770 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt); 5771 Lo = DAG.getNode(ISD::OR, NVT, 5772 DAG.getNode(ISD::SRL, NVT, InL, Amt), 5773 DAG.getNode(ISD::SHL, NVT, InH, Amt2)); 5774 return true; 5775 } 5776 } 5777 5778 return false; 5779} 5780 5781 5782// ExpandLibCall - Expand a node into a call to a libcall. If the result value 5783// does not fit into a register, return the lo part and set the hi part to the 5784// by-reg argument. If it does fit into a single register, return the result 5785// and leave the Hi part unset. 5786SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 5787 bool isSigned, SDValue &Hi) { 5788 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!"); 5789 // The input chain to this libcall is the entry node of the function. 5790 // Legalizing the call will automatically add the previous call to the 5791 // dependence. 5792 SDValue InChain = DAG.getEntryNode(); 5793 5794 TargetLowering::ArgListTy Args; 5795 TargetLowering::ArgListEntry Entry; 5796 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 5797 MVT ArgVT = Node->getOperand(i).getValueType(); 5798 const Type *ArgTy = ArgVT.getTypeForMVT(); 5799 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 5800 Entry.isSExt = isSigned; 5801 Entry.isZExt = !isSigned; 5802 Args.push_back(Entry); 5803 } 5804 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 5805 TLI.getPointerTy()); 5806 5807 // Splice the libcall in wherever FindInputOutputChains tells us to. 5808 const Type *RetTy = Node->getValueType(0).getTypeForMVT(); 5809 std::pair<SDValue,SDValue> CallInfo = 5810 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 5811 CallingConv::C, false, Callee, Args, DAG); 5812 5813 // Legalize the call sequence, starting with the chain. This will advance 5814 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that 5815 // was added by LowerCallTo (guaranteeing proper serialization of calls). 5816 LegalizeOp(CallInfo.second); 5817 SDValue Result; 5818 switch (getTypeAction(CallInfo.first.getValueType())) { 5819 default: assert(0 && "Unknown thing"); 5820 case Legal: 5821 Result = CallInfo.first; 5822 break; 5823 case Expand: 5824 ExpandOp(CallInfo.first, Result, Hi); 5825 break; 5826 } 5827 return Result; 5828} 5829 5830/// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation. 5831/// 5832SDValue SelectionDAGLegalize:: 5833LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) { 5834 bool isCustom = false; 5835 SDValue Tmp1; 5836 switch (getTypeAction(Op.getValueType())) { 5837 case Legal: 5838 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5839 Op.getValueType())) { 5840 default: assert(0 && "Unknown operation action!"); 5841 case TargetLowering::Custom: 5842 isCustom = true; 5843 // FALLTHROUGH 5844 case TargetLowering::Legal: 5845 Tmp1 = LegalizeOp(Op); 5846 if (Result.getNode()) 5847 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5848 else 5849 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5850 DestTy, Tmp1); 5851 if (isCustom) { 5852 Tmp1 = TLI.LowerOperation(Result, DAG); 5853 if (Tmp1.getNode()) Result = Tmp1; 5854 } 5855 break; 5856 case TargetLowering::Expand: 5857 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy); 5858 break; 5859 case TargetLowering::Promote: 5860 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned); 5861 break; 5862 } 5863 break; 5864 case Expand: 5865 Result = ExpandIntToFP(isSigned, DestTy, Op); 5866 break; 5867 case Promote: 5868 Tmp1 = PromoteOp(Op); 5869 if (isSigned) { 5870 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(), 5871 Tmp1, DAG.getValueType(Op.getValueType())); 5872 } else { 5873 Tmp1 = DAG.getZeroExtendInReg(Tmp1, 5874 Op.getValueType()); 5875 } 5876 if (Result.getNode()) 5877 Result = DAG.UpdateNodeOperands(Result, Tmp1); 5878 else 5879 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, 5880 DestTy, Tmp1); 5881 Result = LegalizeOp(Result); // The 'op' is not necessarily legal! 5882 break; 5883 } 5884 return Result; 5885} 5886 5887/// ExpandIntToFP - Expand a [US]INT_TO_FP operation. 5888/// 5889SDValue SelectionDAGLegalize:: 5890ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) { 5891 MVT SourceVT = Source.getValueType(); 5892 bool ExpandSource = getTypeAction(SourceVT) == Expand; 5893 5894 // Expand unsupported int-to-fp vector casts by unrolling them. 5895 if (DestTy.isVector()) { 5896 if (!ExpandSource) 5897 return LegalizeOp(UnrollVectorOp(Source)); 5898 MVT DestEltTy = DestTy.getVectorElementType(); 5899 if (DestTy.getVectorNumElements() == 1) { 5900 SDValue Scalar = ScalarizeVectorOp(Source); 5901 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned, 5902 DestEltTy, Scalar); 5903 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result); 5904 } 5905 SDValue Lo, Hi; 5906 SplitVectorOp(Source, Lo, Hi); 5907 MVT SplitDestTy = MVT::getVectorVT(DestEltTy, 5908 DestTy.getVectorNumElements() / 2); 5909 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo); 5910 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi); 5911 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult, 5912 HiResult)); 5913 } 5914 5915 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc. 5916 if (!isSigned && SourceVT != MVT::i32) { 5917 // The integer value loaded will be incorrectly if the 'sign bit' of the 5918 // incoming integer is set. To handle this, we dynamically test to see if 5919 // it is set, and, if so, add a fudge factor. 5920 SDValue Hi; 5921 if (ExpandSource) { 5922 SDValue Lo; 5923 ExpandOp(Source, Lo, Hi); 5924 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi); 5925 } else { 5926 // The comparison for the sign bit will use the entire operand. 5927 Hi = Source; 5928 } 5929 5930 // Check to see if the target has a custom way to lower this. If so, use 5931 // it. (Note we've already expanded the operand in this case.) 5932 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) { 5933 default: assert(0 && "This action not implemented for this operation!"); 5934 case TargetLowering::Legal: 5935 case TargetLowering::Expand: 5936 break; // This case is handled below. 5937 case TargetLowering::Custom: { 5938 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy, 5939 Source), DAG); 5940 if (NV.getNode()) 5941 return LegalizeOp(NV); 5942 break; // The target decided this was legal after all 5943 } 5944 } 5945 5946 // If this is unsigned, and not supported, first perform the conversion to 5947 // signed, then adjust the result if the sign bit is set. 5948 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source); 5949 5950 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 5951 DAG.getConstant(0, Hi.getValueType()), 5952 ISD::SETLT); 5953 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 5954 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 5955 SignSet, Four, Zero); 5956 uint64_t FF = 0x5f800000ULL; 5957 if (TLI.isLittleEndian()) FF <<= 32; 5958 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 5959 5960 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 5961 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5962 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 5963 Alignment = std::min(Alignment, 4u); 5964 SDValue FudgeInReg; 5965 if (DestTy == MVT::f32) 5966 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 5967 PseudoSourceValue::getConstantPool(), 0, 5968 false, Alignment); 5969 else if (DestTy.bitsGT(MVT::f32)) 5970 // FIXME: Avoid the extend by construction the right constantpool? 5971 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 5972 CPIdx, 5973 PseudoSourceValue::getConstantPool(), 0, 5974 MVT::f32, false, Alignment); 5975 else 5976 assert(0 && "Unexpected conversion"); 5977 5978 MVT SCVT = SignedConv.getValueType(); 5979 if (SCVT != DestTy) { 5980 // Destination type needs to be expanded as well. The FADD now we are 5981 // constructing will be expanded into a libcall. 5982 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) { 5983 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits()); 5984 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy, 5985 SignedConv, SignedConv.getValue(1)); 5986 } 5987 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv); 5988 } 5989 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 5990 } 5991 5992 // Check to see if the target has a custom way to lower this. If so, use it. 5993 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 5994 default: assert(0 && "This action not implemented for this operation!"); 5995 case TargetLowering::Legal: 5996 case TargetLowering::Expand: 5997 break; // This case is handled below. 5998 case TargetLowering::Custom: { 5999 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 6000 Source), DAG); 6001 if (NV.getNode()) 6002 return LegalizeOp(NV); 6003 break; // The target decided this was legal after all 6004 } 6005 } 6006 6007 // Expand the source, then glue it back together for the call. We must expand 6008 // the source in case it is shared (this pass of legalize must traverse it). 6009 if (ExpandSource) { 6010 SDValue SrcLo, SrcHi; 6011 ExpandOp(Source, SrcLo, SrcHi); 6012 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi); 6013 } 6014 6015 RTLIB::Libcall LC = isSigned ? 6016 RTLIB::getSINTTOFP(SourceVT, DestTy) : 6017 RTLIB::getUINTTOFP(SourceVT, DestTy); 6018 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type"); 6019 6020 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source); 6021 SDValue HiPart; 6022 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart); 6023 if (Result.getValueType() != DestTy && HiPart.getNode()) 6024 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart); 6025 return Result; 6026} 6027 6028/// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 6029/// INT_TO_FP operation of the specified operand when the target requests that 6030/// we expand it. At this point, we know that the result and operand types are 6031/// legal for the target. 6032SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 6033 SDValue Op0, 6034 MVT DestVT) { 6035 if (Op0.getValueType() == MVT::i32) { 6036 // simple 32-bit [signed|unsigned] integer to float/double expansion 6037 6038 // Get the stack frame index of a 8 byte buffer. 6039 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 6040 6041 // word offset constant for Hi/Lo address computation 6042 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 6043 // set up Hi and Lo (into buffer) address based on endian 6044 SDValue Hi = StackSlot; 6045 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff); 6046 if (TLI.isLittleEndian()) 6047 std::swap(Hi, Lo); 6048 6049 // if signed map to unsigned space 6050 SDValue Op0Mapped; 6051 if (isSigned) { 6052 // constant used to invert sign bit (signed to unsigned mapping) 6053 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 6054 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit); 6055 } else { 6056 Op0Mapped = Op0; 6057 } 6058 // store the lo of the constructed double - based on integer input 6059 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), 6060 Op0Mapped, Lo, NULL, 0); 6061 // initial hi portion of constructed double 6062 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 6063 // store the hi of the constructed double - biased exponent 6064 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0); 6065 // load the constructed double 6066 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0); 6067 // FP constant to bias correct the final result 6068 SDValue Bias = DAG.getConstantFP(isSigned ? 6069 BitsToDouble(0x4330000080000000ULL) 6070 : BitsToDouble(0x4330000000000000ULL), 6071 MVT::f64); 6072 // subtract the bias 6073 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias); 6074 // final result 6075 SDValue Result; 6076 // handle final rounding 6077 if (DestVT == MVT::f64) { 6078 // do nothing 6079 Result = Sub; 6080 } else if (DestVT.bitsLT(MVT::f64)) { 6081 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub, 6082 DAG.getIntPtrConstant(0)); 6083 } else if (DestVT.bitsGT(MVT::f64)) { 6084 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub); 6085 } 6086 return Result; 6087 } 6088 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 6089 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0); 6090 6091 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0, 6092 DAG.getConstant(0, Op0.getValueType()), 6093 ISD::SETLT); 6094 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 6095 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 6096 SignSet, Four, Zero); 6097 6098 // If the sign bit of the integer is set, the large number will be treated 6099 // as a negative number. To counteract this, the dynamic code adds an 6100 // offset depending on the data type. 6101 uint64_t FF; 6102 switch (Op0.getValueType().getSimpleVT()) { 6103 default: assert(0 && "Unsupported integer type!"); 6104 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 6105 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 6106 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 6107 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 6108 } 6109 if (TLI.isLittleEndian()) FF <<= 32; 6110 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); 6111 6112 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 6113 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6114 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 6115 Alignment = std::min(Alignment, 4u); 6116 SDValue FudgeInReg; 6117 if (DestVT == MVT::f32) 6118 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, 6119 PseudoSourceValue::getConstantPool(), 0, 6120 false, Alignment); 6121 else { 6122 FudgeInReg = 6123 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, 6124 DAG.getEntryNode(), CPIdx, 6125 PseudoSourceValue::getConstantPool(), 0, 6126 MVT::f32, false, Alignment)); 6127 } 6128 6129 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg); 6130} 6131 6132/// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 6133/// *INT_TO_FP operation of the specified operand when the target requests that 6134/// we promote it. At this point, we know that the result and operand types are 6135/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 6136/// operation that takes a larger input. 6137SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 6138 MVT DestVT, 6139 bool isSigned) { 6140 // First step, figure out the appropriate *INT_TO_FP operation to use. 6141 MVT NewInTy = LegalOp.getValueType(); 6142 6143 unsigned OpToUse = 0; 6144 6145 // Scan for the appropriate larger type to use. 6146 while (1) { 6147 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); 6148 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 6149 6150 // If the target supports SINT_TO_FP of this type, use it. 6151 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) { 6152 default: break; 6153 case TargetLowering::Legal: 6154 if (!TLI.isTypeLegal(NewInTy)) 6155 break; // Can't use this datatype. 6156 // FALL THROUGH. 6157 case TargetLowering::Custom: 6158 OpToUse = ISD::SINT_TO_FP; 6159 break; 6160 } 6161 if (OpToUse) break; 6162 if (isSigned) continue; 6163 6164 // If the target supports UINT_TO_FP of this type, use it. 6165 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) { 6166 default: break; 6167 case TargetLowering::Legal: 6168 if (!TLI.isTypeLegal(NewInTy)) 6169 break; // Can't use this datatype. 6170 // FALL THROUGH. 6171 case TargetLowering::Custom: 6172 OpToUse = ISD::UINT_TO_FP; 6173 break; 6174 } 6175 if (OpToUse) break; 6176 6177 // Otherwise, try a larger type. 6178 } 6179 6180 // Okay, we found the operation and type to use. Zero extend our input to the 6181 // desired type then run the operation on it. 6182 return DAG.getNode(OpToUse, DestVT, 6183 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 6184 NewInTy, LegalOp)); 6185} 6186 6187/// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 6188/// FP_TO_*INT operation of the specified operand when the target requests that 6189/// we promote it. At this point, we know that the result and operand types are 6190/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 6191/// operation that returns a larger result. 6192SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 6193 MVT DestVT, 6194 bool isSigned) { 6195 // First step, figure out the appropriate FP_TO*INT operation to use. 6196 MVT NewOutTy = DestVT; 6197 6198 unsigned OpToUse = 0; 6199 6200 // Scan for the appropriate larger type to use. 6201 while (1) { 6202 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); 6203 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 6204 6205 // If the target supports FP_TO_SINT returning this type, use it. 6206 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) { 6207 default: break; 6208 case TargetLowering::Legal: 6209 if (!TLI.isTypeLegal(NewOutTy)) 6210 break; // Can't use this datatype. 6211 // FALL THROUGH. 6212 case TargetLowering::Custom: 6213 OpToUse = ISD::FP_TO_SINT; 6214 break; 6215 } 6216 if (OpToUse) break; 6217 6218 // If the target supports FP_TO_UINT of this type, use it. 6219 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) { 6220 default: break; 6221 case TargetLowering::Legal: 6222 if (!TLI.isTypeLegal(NewOutTy)) 6223 break; // Can't use this datatype. 6224 // FALL THROUGH. 6225 case TargetLowering::Custom: 6226 OpToUse = ISD::FP_TO_UINT; 6227 break; 6228 } 6229 if (OpToUse) break; 6230 6231 // Otherwise, try a larger type. 6232 } 6233 6234 6235 // Okay, we found the operation and type to use. 6236 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp); 6237 6238 // If the operation produces an invalid type, it must be custom lowered. Use 6239 // the target lowering hooks to expand it. Just keep the low part of the 6240 // expanded operation, we know that we're truncating anyway. 6241 if (getTypeAction(NewOutTy) == Expand) { 6242 SmallVector<SDValue, 2> Results; 6243 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG); 6244 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!"); 6245 Operation = Results[0]; 6246 } 6247 6248 // Truncate the result of the extended FP_TO_*INT operation to the desired 6249 // size. 6250 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation); 6251} 6252 6253/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 6254/// 6255SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) { 6256 MVT VT = Op.getValueType(); 6257 MVT SHVT = TLI.getShiftAmountTy(); 6258 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 6259 switch (VT.getSimpleVT()) { 6260 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort(); 6261 case MVT::i16: 6262 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 6263 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 6264 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2); 6265 case MVT::i32: 6266 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 6267 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 6268 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 6269 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 6270 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 6271 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 6272 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 6273 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 6274 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 6275 case MVT::i64: 6276 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT)); 6277 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT)); 6278 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT)); 6279 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT)); 6280 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT)); 6281 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT)); 6282 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT)); 6283 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT)); 6284 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 6285 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 6286 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 6287 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 6288 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 6289 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 6290 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7); 6291 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5); 6292 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3); 6293 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1); 6294 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6); 6295 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2); 6296 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4); 6297 } 6298} 6299 6300/// ExpandBitCount - Expand the specified bitcount instruction into operations. 6301/// 6302SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) { 6303 switch (Opc) { 6304 default: assert(0 && "Cannot expand this yet!"); 6305 case ISD::CTPOP: { 6306 static const uint64_t mask[6] = { 6307 0x5555555555555555ULL, 0x3333333333333333ULL, 6308 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 6309 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL 6310 }; 6311 MVT VT = Op.getValueType(); 6312 MVT ShVT = TLI.getShiftAmountTy(); 6313 unsigned len = VT.getSizeInBits(); 6314 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 6315 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) 6316 SDValue Tmp2 = DAG.getConstant(mask[i], VT); 6317 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 6318 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2), 6319 DAG.getNode(ISD::AND, VT, 6320 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2)); 6321 } 6322 return Op; 6323 } 6324 case ISD::CTLZ: { 6325 // for now, we do this: 6326 // x = x | (x >> 1); 6327 // x = x | (x >> 2); 6328 // ... 6329 // x = x | (x >>16); 6330 // x = x | (x >>32); // for 64-bit input 6331 // return popcount(~x); 6332 // 6333 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 6334 MVT VT = Op.getValueType(); 6335 MVT ShVT = TLI.getShiftAmountTy(); 6336 unsigned len = VT.getSizeInBits(); 6337 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 6338 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 6339 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3)); 6340 } 6341 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT)); 6342 return DAG.getNode(ISD::CTPOP, VT, Op); 6343 } 6344 case ISD::CTTZ: { 6345 // for now, we use: { return popcount(~x & (x - 1)); } 6346 // unless the target has ctlz but not ctpop, in which case we use: 6347 // { return 32 - nlz(~x & (x-1)); } 6348 // see also http://www.hackersdelight.org/HDcode/ntz.cc 6349 MVT VT = Op.getValueType(); 6350 SDValue Tmp2 = DAG.getConstant(~0ULL, VT); 6351 SDValue Tmp3 = DAG.getNode(ISD::AND, VT, 6352 DAG.getNode(ISD::XOR, VT, Op, Tmp2), 6353 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT))); 6354 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 6355 if (!TLI.isOperationLegal(ISD::CTPOP, VT) && 6356 TLI.isOperationLegal(ISD::CTLZ, VT)) 6357 return DAG.getNode(ISD::SUB, VT, 6358 DAG.getConstant(VT.getSizeInBits(), VT), 6359 DAG.getNode(ISD::CTLZ, VT, Tmp3)); 6360 return DAG.getNode(ISD::CTPOP, VT, Tmp3); 6361 } 6362 } 6363} 6364 6365/// ExpandOp - Expand the specified SDValue into its two component pieces 6366/// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the 6367/// LegalizedNodes map is filled in for any results that are not expanded, the 6368/// ExpandedNodes map is filled in for any results that are expanded, and the 6369/// Lo/Hi values are returned. 6370void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){ 6371 MVT VT = Op.getValueType(); 6372 MVT NVT = TLI.getTypeToTransformTo(VT); 6373 SDNode *Node = Op.getNode(); 6374 assert(getTypeAction(VT) == Expand && "Not an expanded type!"); 6375 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() || 6376 VT.isVector()) && "Cannot expand to FP value or to larger int value!"); 6377 6378 // See if we already expanded it. 6379 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I 6380 = ExpandedNodes.find(Op); 6381 if (I != ExpandedNodes.end()) { 6382 Lo = I->second.first; 6383 Hi = I->second.second; 6384 return; 6385 } 6386 6387 switch (Node->getOpcode()) { 6388 case ISD::CopyFromReg: 6389 assert(0 && "CopyFromReg must be legal!"); 6390 case ISD::FP_ROUND_INREG: 6391 if (VT == MVT::ppcf128 && 6392 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) == 6393 TargetLowering::Custom) { 6394 SDValue SrcLo, SrcHi, Src; 6395 ExpandOp(Op.getOperand(0), SrcLo, SrcHi); 6396 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi); 6397 SDValue Result = TLI.LowerOperation( 6398 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG); 6399 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR); 6400 Lo = Result.getNode()->getOperand(0); 6401 Hi = Result.getNode()->getOperand(1); 6402 break; 6403 } 6404 // fall through 6405 default: 6406#ifndef NDEBUG 6407 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n"; 6408#endif 6409 assert(0 && "Do not know how to expand this operator!"); 6410 abort(); 6411 case ISD::EXTRACT_ELEMENT: 6412 ExpandOp(Node->getOperand(0), Lo, Hi); 6413 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) 6414 return ExpandOp(Hi, Lo, Hi); 6415 return ExpandOp(Lo, Lo, Hi); 6416 case ISD::EXTRACT_VECTOR_ELT: 6417 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types. 6418 Lo = ExpandEXTRACT_VECTOR_ELT(Op); 6419 return ExpandOp(Lo, Lo, Hi); 6420 case ISD::UNDEF: 6421 Lo = DAG.getNode(ISD::UNDEF, NVT); 6422 Hi = DAG.getNode(ISD::UNDEF, NVT); 6423 break; 6424 case ISD::Constant: { 6425 unsigned NVTBits = NVT.getSizeInBits(); 6426 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue(); 6427 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT); 6428 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT); 6429 break; 6430 } 6431 case ISD::ConstantFP: { 6432 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 6433 if (CFP->getValueType(0) == MVT::ppcf128) { 6434 APInt api = CFP->getValueAPF().bitcastToAPInt(); 6435 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])), 6436 MVT::f64); 6437 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])), 6438 MVT::f64); 6439 break; 6440 } 6441 Lo = ExpandConstantFP(CFP, false, DAG, TLI); 6442 if (getTypeAction(Lo.getValueType()) == Expand) 6443 ExpandOp(Lo, Lo, Hi); 6444 break; 6445 } 6446 case ISD::BUILD_PAIR: 6447 // Return the operands. 6448 Lo = Node->getOperand(0); 6449 Hi = Node->getOperand(1); 6450 break; 6451 6452 case ISD::MERGE_VALUES: 6453 if (Node->getNumValues() == 1) { 6454 ExpandOp(Op.getOperand(0), Lo, Hi); 6455 break; 6456 } 6457 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y) 6458 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 && 6459 Op.getValue(1).getValueType() == MVT::Other && 6460 "unhandled MERGE_VALUES"); 6461 ExpandOp(Op.getOperand(0), Lo, Hi); 6462 // Remember that we legalized the chain. 6463 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1))); 6464 break; 6465 6466 case ISD::SIGN_EXTEND_INREG: 6467 ExpandOp(Node->getOperand(0), Lo, Hi); 6468 // sext_inreg the low part if needed. 6469 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1)); 6470 6471 // The high part gets the sign extension from the lo-part. This handles 6472 // things like sextinreg V:i64 from i8. 6473 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6474 DAG.getConstant(NVT.getSizeInBits()-1, 6475 TLI.getShiftAmountTy())); 6476 break; 6477 6478 case ISD::BSWAP: { 6479 ExpandOp(Node->getOperand(0), Lo, Hi); 6480 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi); 6481 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo); 6482 Lo = TempLo; 6483 break; 6484 } 6485 6486 case ISD::CTPOP: 6487 ExpandOp(Node->getOperand(0), Lo, Hi); 6488 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L) 6489 DAG.getNode(ISD::CTPOP, NVT, Lo), 6490 DAG.getNode(ISD::CTPOP, NVT, Hi)); 6491 Hi = DAG.getConstant(0, NVT); 6492 break; 6493 6494 case ISD::CTLZ: { 6495 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32) 6496 ExpandOp(Node->getOperand(0), Lo, Hi); 6497 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 6498 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 6499 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC, 6500 ISD::SETNE); 6501 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo); 6502 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC); 6503 6504 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart); 6505 Hi = DAG.getConstant(0, NVT); 6506 break; 6507 } 6508 6509 case ISD::CTTZ: { 6510 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32) 6511 ExpandOp(Node->getOperand(0), Lo, Hi); 6512 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT); 6513 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 6514 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC, 6515 ISD::SETNE); 6516 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi); 6517 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC); 6518 6519 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart); 6520 Hi = DAG.getConstant(0, NVT); 6521 break; 6522 } 6523 6524 case ISD::VAARG: { 6525 SDValue Ch = Node->getOperand(0); // Legalize the chain. 6526 SDValue Ptr = Node->getOperand(1); // Legalize the pointer. 6527 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2)); 6528 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2)); 6529 6530 // Remember that we legalized the chain. 6531 Hi = LegalizeOp(Hi); 6532 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1)); 6533 if (TLI.isBigEndian()) 6534 std::swap(Lo, Hi); 6535 break; 6536 } 6537 6538 case ISD::LOAD: { 6539 LoadSDNode *LD = cast<LoadSDNode>(Node); 6540 SDValue Ch = LD->getChain(); // Legalize the chain. 6541 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer. 6542 ISD::LoadExtType ExtType = LD->getExtensionType(); 6543 const Value *SV = LD->getSrcValue(); 6544 int SVOffset = LD->getSrcValueOffset(); 6545 unsigned Alignment = LD->getAlignment(); 6546 bool isVolatile = LD->isVolatile(); 6547 6548 if (ExtType == ISD::NON_EXTLOAD) { 6549 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset, 6550 isVolatile, Alignment); 6551 if (VT == MVT::f32 || VT == MVT::f64) { 6552 // f32->i32 or f64->i64 one to one expansion. 6553 // Remember that we legalized the chain. 6554 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 6555 // Recursively expand the new load. 6556 if (getTypeAction(NVT) == Expand) 6557 ExpandOp(Lo, Lo, Hi); 6558 break; 6559 } 6560 6561 // Increment the pointer to the other half. 6562 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8; 6563 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 6564 DAG.getIntPtrConstant(IncrementSize)); 6565 SVOffset += IncrementSize; 6566 Alignment = MinAlign(Alignment, IncrementSize); 6567 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset, 6568 isVolatile, Alignment); 6569 6570 // Build a factor node to remember that this load is independent of the 6571 // other one. 6572 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 6573 Hi.getValue(1)); 6574 6575 // Remember that we legalized the chain. 6576 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 6577 if (TLI.isBigEndian()) 6578 std::swap(Lo, Hi); 6579 } else { 6580 MVT EVT = LD->getMemoryVT(); 6581 6582 if ((VT == MVT::f64 && EVT == MVT::f32) || 6583 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) { 6584 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND 6585 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV, 6586 SVOffset, isVolatile, Alignment); 6587 // Remember that we legalized the chain. 6588 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1))); 6589 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi); 6590 break; 6591 } 6592 6593 if (EVT == NVT) 6594 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, 6595 SVOffset, isVolatile, Alignment); 6596 else 6597 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV, 6598 SVOffset, EVT, isVolatile, 6599 Alignment); 6600 6601 // Remember that we legalized the chain. 6602 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1))); 6603 6604 if (ExtType == ISD::SEXTLOAD) { 6605 // The high part is obtained by SRA'ing all but one of the bits of the 6606 // lo part. 6607 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6608 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6609 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6610 } else if (ExtType == ISD::ZEXTLOAD) { 6611 // The high part is just a zero. 6612 Hi = DAG.getConstant(0, NVT); 6613 } else /* if (ExtType == ISD::EXTLOAD) */ { 6614 // The high part is undefined. 6615 Hi = DAG.getNode(ISD::UNDEF, NVT); 6616 } 6617 } 6618 break; 6619 } 6620 case ISD::AND: 6621 case ISD::OR: 6622 case ISD::XOR: { // Simple logical operators -> two trivial pieces. 6623 SDValue LL, LH, RL, RH; 6624 ExpandOp(Node->getOperand(0), LL, LH); 6625 ExpandOp(Node->getOperand(1), RL, RH); 6626 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL); 6627 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH); 6628 break; 6629 } 6630 case ISD::SELECT: { 6631 SDValue LL, LH, RL, RH; 6632 ExpandOp(Node->getOperand(1), LL, LH); 6633 ExpandOp(Node->getOperand(2), RL, RH); 6634 if (getTypeAction(NVT) == Expand) 6635 NVT = TLI.getTypeToExpandTo(NVT); 6636 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL); 6637 if (VT != MVT::f32) 6638 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH); 6639 break; 6640 } 6641 case ISD::SELECT_CC: { 6642 SDValue TL, TH, FL, FH; 6643 ExpandOp(Node->getOperand(2), TL, TH); 6644 ExpandOp(Node->getOperand(3), FL, FH); 6645 if (getTypeAction(NVT) == Expand) 6646 NVT = TLI.getTypeToExpandTo(NVT); 6647 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6648 Node->getOperand(1), TL, FL, Node->getOperand(4)); 6649 if (VT != MVT::f32) 6650 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0), 6651 Node->getOperand(1), TH, FH, Node->getOperand(4)); 6652 break; 6653 } 6654 case ISD::ANY_EXTEND: 6655 // The low part is any extension of the input (which degenerates to a copy). 6656 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0)); 6657 // The high part is undefined. 6658 Hi = DAG.getNode(ISD::UNDEF, NVT); 6659 break; 6660 case ISD::SIGN_EXTEND: { 6661 // The low part is just a sign extension of the input (which degenerates to 6662 // a copy). 6663 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0)); 6664 6665 // The high part is obtained by SRA'ing all but one of the bits of the lo 6666 // part. 6667 unsigned LoSize = Lo.getValueType().getSizeInBits(); 6668 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 6669 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 6670 break; 6671 } 6672 case ISD::ZERO_EXTEND: 6673 // The low part is just a zero extension of the input (which degenerates to 6674 // a copy). 6675 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0)); 6676 6677 // The high part is just a zero. 6678 Hi = DAG.getConstant(0, NVT); 6679 break; 6680 6681 case ISD::TRUNCATE: { 6682 // The input value must be larger than this value. Expand *it*. 6683 SDValue NewLo; 6684 ExpandOp(Node->getOperand(0), NewLo, Hi); 6685 6686 // The low part is now either the right size, or it is closer. If not the 6687 // right size, make an illegal truncate so we recursively expand it. 6688 if (NewLo.getValueType() != Node->getValueType(0)) 6689 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo); 6690 ExpandOp(NewLo, Lo, Hi); 6691 break; 6692 } 6693 6694 case ISD::BIT_CONVERT: { 6695 SDValue Tmp; 6696 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){ 6697 // If the target wants to, allow it to lower this itself. 6698 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6699 case Expand: assert(0 && "cannot expand FP!"); 6700 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break; 6701 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break; 6702 } 6703 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG); 6704 } 6705 6706 // f32 / f64 must be expanded to i32 / i64. 6707 if (VT == MVT::f32 || VT == MVT::f64) { 6708 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 6709 if (getTypeAction(NVT) == Expand) 6710 ExpandOp(Lo, Lo, Hi); 6711 break; 6712 } 6713 6714 // If source operand will be expanded to the same type as VT, i.e. 6715 // i64 <- f64, i32 <- f32, expand the source operand instead. 6716 MVT VT0 = Node->getOperand(0).getValueType(); 6717 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) { 6718 ExpandOp(Node->getOperand(0), Lo, Hi); 6719 break; 6720 } 6721 6722 // Turn this into a load/store pair by default. 6723 if (Tmp.getNode() == 0) 6724 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT); 6725 6726 ExpandOp(Tmp, Lo, Hi); 6727 break; 6728 } 6729 6730 case ISD::READCYCLECOUNTER: { 6731 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) == 6732 TargetLowering::Custom && 6733 "Must custom expand ReadCycleCounter"); 6734 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6735 assert(Tmp.getNode() && "Node must be custom expanded!"); 6736 ExpandOp(Tmp.getValue(0), Lo, Hi); 6737 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6738 LegalizeOp(Tmp.getValue(1))); 6739 break; 6740 } 6741 6742 case ISD::ATOMIC_CMP_SWAP_64: { 6743 // This operation does not need a loop. 6744 SDValue Tmp = TLI.LowerOperation(Op, DAG); 6745 assert(Tmp.getNode() && "Node must be custom expanded!"); 6746 ExpandOp(Tmp.getValue(0), Lo, Hi); 6747 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain. 6748 LegalizeOp(Tmp.getValue(1))); 6749 break; 6750 } 6751 6752 case ISD::ATOMIC_LOAD_ADD_64: 6753 case ISD::ATOMIC_LOAD_SUB_64: 6754 case ISD::ATOMIC_LOAD_AND_64: 6755 case ISD::ATOMIC_LOAD_OR_64: 6756 case ISD::ATOMIC_LOAD_XOR_64: 6757 case ISD::ATOMIC_LOAD_NAND_64: 6758 case ISD::ATOMIC_SWAP_64: { 6759 // These operations require a loop to be generated. We can't do that yet, 6760 // so substitute a target-dependent pseudo and expand that later. 6761 SDValue In2Lo, In2Hi, In2; 6762 ExpandOp(Op.getOperand(2), In2Lo, In2Hi); 6763 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi); 6764 AtomicSDNode* Anode = cast<AtomicSDNode>(Node); 6765 SDValue Replace = 6766 DAG.getAtomic(Op.getOpcode(), Op.getOperand(0), Op.getOperand(1), In2, 6767 Anode->getSrcValue(), Anode->getAlignment()); 6768 SDValue Result = TLI.LowerOperation(Replace, DAG); 6769 ExpandOp(Result.getValue(0), Lo, Hi); 6770 // Remember that we legalized the chain. 6771 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1))); 6772 break; 6773 } 6774 6775 // These operators cannot be expanded directly, emit them as calls to 6776 // library functions. 6777 case ISD::FP_TO_SINT: { 6778 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) { 6779 SDValue Op; 6780 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6781 case Expand: assert(0 && "cannot expand FP!"); 6782 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6783 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6784 } 6785 6786 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG); 6787 6788 // Now that the custom expander is done, expand the result, which is still 6789 // VT. 6790 if (Op.getNode()) { 6791 ExpandOp(Op, Lo, Hi); 6792 break; 6793 } 6794 } 6795 6796 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(), 6797 VT); 6798 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!"); 6799 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6800 break; 6801 } 6802 6803 case ISD::FP_TO_UINT: { 6804 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) { 6805 SDValue Op; 6806 switch (getTypeAction(Node->getOperand(0).getValueType())) { 6807 case Expand: assert(0 && "cannot expand FP!"); 6808 case Legal: Op = LegalizeOp(Node->getOperand(0)); break; 6809 case Promote: Op = PromoteOp (Node->getOperand(0)); break; 6810 } 6811 6812 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG); 6813 6814 // Now that the custom expander is done, expand the result. 6815 if (Op.getNode()) { 6816 ExpandOp(Op, Lo, Hi); 6817 break; 6818 } 6819 } 6820 6821 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(), 6822 VT); 6823 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 6824 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi); 6825 break; 6826 } 6827 6828 case ISD::SHL: { 6829 // If the target wants custom lowering, do so. 6830 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6831 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) { 6832 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt); 6833 Op = TLI.LowerOperation(Op, DAG); 6834 if (Op.getNode()) { 6835 // Now that the custom expander is done, expand the result, which is 6836 // still VT. 6837 ExpandOp(Op, Lo, Hi); 6838 break; 6839 } 6840 } 6841 6842 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit 6843 // this X << 1 as X+X. 6844 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) { 6845 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) && 6846 TLI.isOperationLegal(ISD::ADDE, NVT)) { 6847 SDValue LoOps[2], HiOps[3]; 6848 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]); 6849 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag); 6850 LoOps[1] = LoOps[0]; 6851 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6852 6853 HiOps[1] = HiOps[0]; 6854 HiOps[2] = Lo.getValue(1); 6855 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6856 break; 6857 } 6858 } 6859 6860 // If we can emit an efficient shift operation, do so now. 6861 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6862 break; 6863 6864 // If this target supports SHL_PARTS, use it. 6865 TargetLowering::LegalizeAction Action = 6866 TLI.getOperationAction(ISD::SHL_PARTS, NVT); 6867 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6868 Action == TargetLowering::Custom) { 6869 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6870 break; 6871 } 6872 6873 // Otherwise, emit a libcall. 6874 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi); 6875 break; 6876 } 6877 6878 case ISD::SRA: { 6879 // If the target wants custom lowering, do so. 6880 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6881 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) { 6882 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt); 6883 Op = TLI.LowerOperation(Op, DAG); 6884 if (Op.getNode()) { 6885 // Now that the custom expander is done, expand the result, which is 6886 // still VT. 6887 ExpandOp(Op, Lo, Hi); 6888 break; 6889 } 6890 } 6891 6892 // If we can emit an efficient shift operation, do so now. 6893 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6894 break; 6895 6896 // If this target supports SRA_PARTS, use it. 6897 TargetLowering::LegalizeAction Action = 6898 TLI.getOperationAction(ISD::SRA_PARTS, NVT); 6899 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6900 Action == TargetLowering::Custom) { 6901 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6902 break; 6903 } 6904 6905 // Otherwise, emit a libcall. 6906 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi); 6907 break; 6908 } 6909 6910 case ISD::SRL: { 6911 // If the target wants custom lowering, do so. 6912 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1)); 6913 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) { 6914 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt); 6915 Op = TLI.LowerOperation(Op, DAG); 6916 if (Op.getNode()) { 6917 // Now that the custom expander is done, expand the result, which is 6918 // still VT. 6919 ExpandOp(Op, Lo, Hi); 6920 break; 6921 } 6922 } 6923 6924 // If we can emit an efficient shift operation, do so now. 6925 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi)) 6926 break; 6927 6928 // If this target supports SRL_PARTS, use it. 6929 TargetLowering::LegalizeAction Action = 6930 TLI.getOperationAction(ISD::SRL_PARTS, NVT); 6931 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 6932 Action == TargetLowering::Custom) { 6933 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi); 6934 break; 6935 } 6936 6937 // Otherwise, emit a libcall. 6938 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi); 6939 break; 6940 } 6941 6942 case ISD::ADD: 6943 case ISD::SUB: { 6944 // If the target wants to custom expand this, let them. 6945 if (TLI.getOperationAction(Node->getOpcode(), VT) == 6946 TargetLowering::Custom) { 6947 SDValue Result = TLI.LowerOperation(Op, DAG); 6948 if (Result.getNode()) { 6949 ExpandOp(Result, Lo, Hi); 6950 break; 6951 } 6952 } 6953 // Expand the subcomponents. 6954 SDValue LHSL, LHSH, RHSL, RHSH; 6955 ExpandOp(Node->getOperand(0), LHSL, LHSH); 6956 ExpandOp(Node->getOperand(1), RHSL, RHSH); 6957 SDValue LoOps[2], HiOps[3]; 6958 LoOps[0] = LHSL; 6959 LoOps[1] = RHSL; 6960 HiOps[0] = LHSH; 6961 HiOps[1] = RHSH; 6962 6963 //cascaded check to see if any smaller size has a a carry flag. 6964 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC; 6965 bool hasCarry = false; 6966 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) { 6967 MVT AVT = MVT::getIntegerVT(BitSize); 6968 if (TLI.isOperationLegal(OpV, AVT)) { 6969 hasCarry = true; 6970 break; 6971 } 6972 } 6973 6974 if(hasCarry) { 6975 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 6976 if (Node->getOpcode() == ISD::ADD) { 6977 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 6978 HiOps[2] = Lo.getValue(1); 6979 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 6980 } else { 6981 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 6982 HiOps[2] = Lo.getValue(1); 6983 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 6984 } 6985 break; 6986 } else { 6987 if (Node->getOpcode() == ISD::ADD) { 6988 Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2); 6989 Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2); 6990 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), 6991 Lo, LoOps[0], ISD::SETULT); 6992 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, 6993 DAG.getConstant(1, NVT), 6994 DAG.getConstant(0, NVT)); 6995 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), 6996 Lo, LoOps[1], ISD::SETULT); 6997 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2, 6998 DAG.getConstant(1, NVT), 6999 Carry1); 7000 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2); 7001 } else { 7002 Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2); 7003 Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2); 7004 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT); 7005 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp, 7006 DAG.getConstant(1, NVT), 7007 DAG.getConstant(0, NVT)); 7008 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow); 7009 } 7010 break; 7011 } 7012 } 7013 7014 case ISD::ADDC: 7015 case ISD::SUBC: { 7016 // Expand the subcomponents. 7017 SDValue LHSL, LHSH, RHSL, RHSH; 7018 ExpandOp(Node->getOperand(0), LHSL, LHSH); 7019 ExpandOp(Node->getOperand(1), RHSL, RHSH); 7020 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 7021 SDValue LoOps[2] = { LHSL, RHSL }; 7022 SDValue HiOps[3] = { LHSH, RHSH }; 7023 7024 if (Node->getOpcode() == ISD::ADDC) { 7025 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 7026 HiOps[2] = Lo.getValue(1); 7027 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 7028 } else { 7029 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 7030 HiOps[2] = Lo.getValue(1); 7031 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 7032 } 7033 // Remember that we legalized the flag. 7034 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 7035 break; 7036 } 7037 case ISD::ADDE: 7038 case ISD::SUBE: { 7039 // Expand the subcomponents. 7040 SDValue LHSL, LHSH, RHSL, RHSH; 7041 ExpandOp(Node->getOperand(0), LHSL, LHSH); 7042 ExpandOp(Node->getOperand(1), RHSL, RHSH); 7043 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 7044 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) }; 7045 SDValue HiOps[3] = { LHSH, RHSH }; 7046 7047 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3); 7048 HiOps[2] = Lo.getValue(1); 7049 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3); 7050 7051 // Remember that we legalized the flag. 7052 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1))); 7053 break; 7054 } 7055 case ISD::MUL: { 7056 // If the target wants to custom expand this, let them. 7057 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) { 7058 SDValue New = TLI.LowerOperation(Op, DAG); 7059 if (New.getNode()) { 7060 ExpandOp(New, Lo, Hi); 7061 break; 7062 } 7063 } 7064 7065 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 7066 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 7067 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 7068 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 7069 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 7070 SDValue LL, LH, RL, RH; 7071 ExpandOp(Node->getOperand(0), LL, LH); 7072 ExpandOp(Node->getOperand(1), RL, RH); 7073 unsigned OuterBitSize = Op.getValueSizeInBits(); 7074 unsigned InnerBitSize = RH.getValueSizeInBits(); 7075 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0)); 7076 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1)); 7077 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 7078 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) && 7079 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) { 7080 // The inputs are both zero-extended. 7081 if (HasUMUL_LOHI) { 7082 // We can emit a umul_lohi. 7083 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 7084 Hi = SDValue(Lo.getNode(), 1); 7085 break; 7086 } 7087 if (HasMULHU) { 7088 // We can emit a mulhu+mul. 7089 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 7090 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 7091 break; 7092 } 7093 } 7094 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 7095 // The input values are both sign-extended. 7096 if (HasSMUL_LOHI) { 7097 // We can emit a smul_lohi. 7098 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 7099 Hi = SDValue(Lo.getNode(), 1); 7100 break; 7101 } 7102 if (HasMULHS) { 7103 // We can emit a mulhs+mul. 7104 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 7105 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 7106 break; 7107 } 7108 } 7109 if (HasUMUL_LOHI) { 7110 // Lo,Hi = umul LHS, RHS. 7111 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 7112 DAG.getVTList(NVT, NVT), LL, RL); 7113 Lo = UMulLOHI; 7114 Hi = UMulLOHI.getValue(1); 7115 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 7116 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 7117 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 7118 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 7119 break; 7120 } 7121 if (HasMULHU) { 7122 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 7123 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 7124 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 7125 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 7126 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 7127 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 7128 break; 7129 } 7130 } 7131 7132 // If nothing else, we can make a libcall. 7133 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi); 7134 break; 7135 } 7136 case ISD::SDIV: 7137 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi); 7138 break; 7139 case ISD::UDIV: 7140 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi); 7141 break; 7142 case ISD::SREM: 7143 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi); 7144 break; 7145 case ISD::UREM: 7146 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi); 7147 break; 7148 7149 case ISD::FADD: 7150 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32, 7151 RTLIB::ADD_F64, 7152 RTLIB::ADD_F80, 7153 RTLIB::ADD_PPCF128), 7154 Node, false, Hi); 7155 break; 7156 case ISD::FSUB: 7157 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32, 7158 RTLIB::SUB_F64, 7159 RTLIB::SUB_F80, 7160 RTLIB::SUB_PPCF128), 7161 Node, false, Hi); 7162 break; 7163 case ISD::FMUL: 7164 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32, 7165 RTLIB::MUL_F64, 7166 RTLIB::MUL_F80, 7167 RTLIB::MUL_PPCF128), 7168 Node, false, Hi); 7169 break; 7170 case ISD::FDIV: 7171 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32, 7172 RTLIB::DIV_F64, 7173 RTLIB::DIV_F80, 7174 RTLIB::DIV_PPCF128), 7175 Node, false, Hi); 7176 break; 7177 case ISD::FP_EXTEND: { 7178 if (VT == MVT::ppcf128) { 7179 assert(Node->getOperand(0).getValueType()==MVT::f32 || 7180 Node->getOperand(0).getValueType()==MVT::f64); 7181 const uint64_t zero = 0; 7182 if (Node->getOperand(0).getValueType()==MVT::f32) 7183 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0)); 7184 else 7185 Hi = Node->getOperand(0); 7186 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7187 break; 7188 } 7189 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT); 7190 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!"); 7191 Lo = ExpandLibCall(LC, Node, true, Hi); 7192 break; 7193 } 7194 case ISD::FP_ROUND: { 7195 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(), 7196 VT); 7197 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!"); 7198 Lo = ExpandLibCall(LC, Node, true, Hi); 7199 break; 7200 } 7201 case ISD::FSQRT: 7202 case ISD::FSIN: 7203 case ISD::FCOS: 7204 case ISD::FLOG: 7205 case ISD::FLOG2: 7206 case ISD::FLOG10: 7207 case ISD::FEXP: 7208 case ISD::FEXP2: 7209 case ISD::FTRUNC: 7210 case ISD::FFLOOR: 7211 case ISD::FCEIL: 7212 case ISD::FRINT: 7213 case ISD::FNEARBYINT: 7214 case ISD::FPOW: 7215 case ISD::FPOWI: { 7216 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 7217 switch(Node->getOpcode()) { 7218 case ISD::FSQRT: 7219 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 7220 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128); 7221 break; 7222 case ISD::FSIN: 7223 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64, 7224 RTLIB::SIN_F80, RTLIB::SIN_PPCF128); 7225 break; 7226 case ISD::FCOS: 7227 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64, 7228 RTLIB::COS_F80, RTLIB::COS_PPCF128); 7229 break; 7230 case ISD::FLOG: 7231 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64, 7232 RTLIB::LOG_F80, RTLIB::LOG_PPCF128); 7233 break; 7234 case ISD::FLOG2: 7235 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 7236 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128); 7237 break; 7238 case ISD::FLOG10: 7239 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 7240 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128); 7241 break; 7242 case ISD::FEXP: 7243 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64, 7244 RTLIB::EXP_F80, RTLIB::EXP_PPCF128); 7245 break; 7246 case ISD::FEXP2: 7247 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 7248 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128); 7249 break; 7250 case ISD::FTRUNC: 7251 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 7252 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128); 7253 break; 7254 case ISD::FFLOOR: 7255 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 7256 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128); 7257 break; 7258 case ISD::FCEIL: 7259 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 7260 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128); 7261 break; 7262 case ISD::FRINT: 7263 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64, 7264 RTLIB::RINT_F80, RTLIB::RINT_PPCF128); 7265 break; 7266 case ISD::FNEARBYINT: 7267 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64, 7268 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128); 7269 break; 7270 case ISD::FPOW: 7271 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80, 7272 RTLIB::POW_PPCF128); 7273 break; 7274 case ISD::FPOWI: 7275 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80, 7276 RTLIB::POWI_PPCF128); 7277 break; 7278 default: assert(0 && "Unreachable!"); 7279 } 7280 Lo = ExpandLibCall(LC, Node, false, Hi); 7281 break; 7282 } 7283 case ISD::FABS: { 7284 if (VT == MVT::ppcf128) { 7285 SDValue Tmp; 7286 ExpandOp(Node->getOperand(0), Lo, Tmp); 7287 Hi = DAG.getNode(ISD::FABS, NVT, Tmp); 7288 // lo = hi==fabs(hi) ? lo : -lo; 7289 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp, 7290 Lo, DAG.getNode(ISD::FNEG, NVT, Lo), 7291 DAG.getCondCode(ISD::SETEQ)); 7292 break; 7293 } 7294 SDValue Mask = (VT == MVT::f64) 7295 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT) 7296 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT); 7297 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 7298 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 7299 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask); 7300 if (getTypeAction(NVT) == Expand) 7301 ExpandOp(Lo, Lo, Hi); 7302 break; 7303 } 7304 case ISD::FNEG: { 7305 if (VT == MVT::ppcf128) { 7306 ExpandOp(Node->getOperand(0), Lo, Hi); 7307 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo); 7308 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi); 7309 break; 7310 } 7311 SDValue Mask = (VT == MVT::f64) 7312 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT) 7313 : DAG.getConstantFP(BitsToFloat(1U << 31), VT); 7314 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask); 7315 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0)); 7316 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask); 7317 if (getTypeAction(NVT) == Expand) 7318 ExpandOp(Lo, Lo, Hi); 7319 break; 7320 } 7321 case ISD::FCOPYSIGN: { 7322 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI); 7323 if (getTypeAction(NVT) == Expand) 7324 ExpandOp(Lo, Lo, Hi); 7325 break; 7326 } 7327 case ISD::SINT_TO_FP: 7328 case ISD::UINT_TO_FP: { 7329 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP; 7330 MVT SrcVT = Node->getOperand(0).getValueType(); 7331 7332 // Promote the operand if needed. Do this before checking for 7333 // ppcf128 so conversions of i16 and i8 work. 7334 if (getTypeAction(SrcVT) == Promote) { 7335 SDValue Tmp = PromoteOp(Node->getOperand(0)); 7336 Tmp = isSigned 7337 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp, 7338 DAG.getValueType(SrcVT)) 7339 : DAG.getZeroExtendInReg(Tmp, SrcVT); 7340 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode(); 7341 SrcVT = Node->getOperand(0).getValueType(); 7342 } 7343 7344 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) { 7345 static const uint64_t zero = 0; 7346 if (isSigned) { 7347 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 7348 Node->getOperand(0))); 7349 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7350 } else { 7351 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 }; 7352 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64, 7353 Node->getOperand(0))); 7354 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64); 7355 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 7356 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32 7357 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 7358 DAG.getConstant(0, MVT::i32), 7359 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 7360 DAG.getConstantFP( 7361 APFloat(APInt(128, 2, TwoE32)), 7362 MVT::ppcf128)), 7363 Hi, 7364 DAG.getCondCode(ISD::SETLT)), 7365 Lo, Hi); 7366 } 7367 break; 7368 } 7369 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) { 7370 // si64->ppcf128 done by libcall, below 7371 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 }; 7372 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)), 7373 Lo, Hi); 7374 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi); 7375 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64 7376 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0), 7377 DAG.getConstant(0, MVT::i64), 7378 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi, 7379 DAG.getConstantFP( 7380 APFloat(APInt(128, 2, TwoE64)), 7381 MVT::ppcf128)), 7382 Hi, 7383 DAG.getCondCode(ISD::SETLT)), 7384 Lo, Hi); 7385 break; 7386 } 7387 7388 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT, 7389 Node->getOperand(0)); 7390 if (getTypeAction(Lo.getValueType()) == Expand) 7391 // float to i32 etc. can be 'expanded' to a single node. 7392 ExpandOp(Lo, Lo, Hi); 7393 break; 7394 } 7395 } 7396 7397 // Make sure the resultant values have been legalized themselves, unless this 7398 // is a type that requires multi-step expansion. 7399 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) { 7400 Lo = LegalizeOp(Lo); 7401 if (Hi.getNode()) 7402 // Don't legalize the high part if it is expanded to a single node. 7403 Hi = LegalizeOp(Hi); 7404 } 7405 7406 // Remember in a map if the values will be reused later. 7407 bool isNew = 7408 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7409 assert(isNew && "Value already expanded?!?"); 7410 isNew = isNew; 7411} 7412 7413/// SplitVectorOp - Given an operand of vector type, break it down into 7414/// two smaller values, still of vector type. 7415void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo, 7416 SDValue &Hi) { 7417 assert(Op.getValueType().isVector() && "Cannot split non-vector type!"); 7418 SDNode *Node = Op.getNode(); 7419 unsigned NumElements = Op.getValueType().getVectorNumElements(); 7420 assert(NumElements > 1 && "Cannot split a single element vector!"); 7421 7422 MVT NewEltVT = Op.getValueType().getVectorElementType(); 7423 7424 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1); 7425 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo; 7426 7427 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo); 7428 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi); 7429 7430 // See if we already split it. 7431 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I 7432 = SplitNodes.find(Op); 7433 if (I != SplitNodes.end()) { 7434 Lo = I->second.first; 7435 Hi = I->second.second; 7436 return; 7437 } 7438 7439 switch (Node->getOpcode()) { 7440 default: 7441#ifndef NDEBUG 7442 Node->dump(&DAG); 7443#endif 7444 assert(0 && "Unhandled operation in SplitVectorOp!"); 7445 case ISD::UNDEF: 7446 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo); 7447 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi); 7448 break; 7449 case ISD::BUILD_PAIR: 7450 Lo = Node->getOperand(0); 7451 Hi = Node->getOperand(1); 7452 break; 7453 case ISD::INSERT_VECTOR_ELT: { 7454 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) { 7455 SplitVectorOp(Node->getOperand(0), Lo, Hi); 7456 unsigned Index = Idx->getZExtValue(); 7457 SDValue ScalarOp = Node->getOperand(1); 7458 if (Index < NewNumElts_Lo) 7459 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp, 7460 DAG.getIntPtrConstant(Index)); 7461 else 7462 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp, 7463 DAG.getIntPtrConstant(Index - NewNumElts_Lo)); 7464 break; 7465 } 7466 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0), 7467 Node->getOperand(1), 7468 Node->getOperand(2)); 7469 SplitVectorOp(Tmp, Lo, Hi); 7470 break; 7471 } 7472 case ISD::VECTOR_SHUFFLE: { 7473 // Build the low part. 7474 SDValue Mask = Node->getOperand(2); 7475 SmallVector<SDValue, 8> Ops; 7476 MVT PtrVT = TLI.getPointerTy(); 7477 7478 // Insert all of the elements from the input that are needed. We use 7479 // buildvector of extractelement here because the input vectors will have 7480 // to be legalized, so this makes the code simpler. 7481 for (unsigned i = 0; i != NewNumElts_Lo; ++i) { 7482 SDValue IdxNode = Mask.getOperand(i); 7483 if (IdxNode.getOpcode() == ISD::UNDEF) { 7484 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 7485 continue; 7486 } 7487 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); 7488 SDValue InVec = Node->getOperand(0); 7489 if (Idx >= NumElements) { 7490 InVec = Node->getOperand(1); 7491 Idx -= NumElements; 7492 } 7493 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 7494 DAG.getConstant(Idx, PtrVT))); 7495 } 7496 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size()); 7497 Ops.clear(); 7498 7499 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) { 7500 SDValue IdxNode = Mask.getOperand(i); 7501 if (IdxNode.getOpcode() == ISD::UNDEF) { 7502 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT)); 7503 continue; 7504 } 7505 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue(); 7506 SDValue InVec = Node->getOperand(0); 7507 if (Idx >= NumElements) { 7508 InVec = Node->getOperand(1); 7509 Idx -= NumElements; 7510 } 7511 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec, 7512 DAG.getConstant(Idx, PtrVT))); 7513 } 7514 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size()); 7515 break; 7516 } 7517 case ISD::BUILD_VECTOR: { 7518 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 7519 Node->op_begin()+NewNumElts_Lo); 7520 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size()); 7521 7522 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo, 7523 Node->op_end()); 7524 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size()); 7525 break; 7526 } 7527 case ISD::CONCAT_VECTORS: { 7528 // FIXME: Handle non-power-of-two vectors? 7529 unsigned NewNumSubvectors = Node->getNumOperands() / 2; 7530 if (NewNumSubvectors == 1) { 7531 Lo = Node->getOperand(0); 7532 Hi = Node->getOperand(1); 7533 } else { 7534 SmallVector<SDValue, 8> LoOps(Node->op_begin(), 7535 Node->op_begin()+NewNumSubvectors); 7536 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size()); 7537 7538 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors, 7539 Node->op_end()); 7540 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size()); 7541 } 7542 break; 7543 } 7544 case ISD::EXTRACT_SUBVECTOR: { 7545 SDValue Vec = Op.getOperand(0); 7546 SDValue Idx = Op.getOperand(1); 7547 MVT IdxVT = Idx.getValueType(); 7548 7549 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Lo, Vec, Idx); 7550 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx); 7551 if (CIdx) { 7552 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, 7553 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo, 7554 IdxVT)); 7555 } else { 7556 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx, 7557 DAG.getConstant(NewNumElts_Lo, IdxVT)); 7558 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, Idx); 7559 } 7560 break; 7561 } 7562 case ISD::SELECT: { 7563 SDValue Cond = Node->getOperand(0); 7564 7565 SDValue LL, LH, RL, RH; 7566 SplitVectorOp(Node->getOperand(1), LL, LH); 7567 SplitVectorOp(Node->getOperand(2), RL, RH); 7568 7569 if (Cond.getValueType().isVector()) { 7570 // Handle a vector merge. 7571 SDValue CL, CH; 7572 SplitVectorOp(Cond, CL, CH); 7573 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL); 7574 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH); 7575 } else { 7576 // Handle a simple select with vector operands. 7577 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL); 7578 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH); 7579 } 7580 break; 7581 } 7582 case ISD::SELECT_CC: { 7583 SDValue CondLHS = Node->getOperand(0); 7584 SDValue CondRHS = Node->getOperand(1); 7585 SDValue CondCode = Node->getOperand(4); 7586 7587 SDValue LL, LH, RL, RH; 7588 SplitVectorOp(Node->getOperand(2), LL, LH); 7589 SplitVectorOp(Node->getOperand(3), RL, RH); 7590 7591 // Handle a simple select with vector operands. 7592 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS, 7593 LL, RL, CondCode); 7594 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS, 7595 LH, RH, CondCode); 7596 break; 7597 } 7598 case ISD::VSETCC: { 7599 SDValue LL, LH, RL, RH; 7600 SplitVectorOp(Node->getOperand(0), LL, LH); 7601 SplitVectorOp(Node->getOperand(1), RL, RH); 7602 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2)); 7603 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2)); 7604 break; 7605 } 7606 case ISD::ADD: 7607 case ISD::SUB: 7608 case ISD::MUL: 7609 case ISD::FADD: 7610 case ISD::FSUB: 7611 case ISD::FMUL: 7612 case ISD::SDIV: 7613 case ISD::UDIV: 7614 case ISD::FDIV: 7615 case ISD::FPOW: 7616 case ISD::AND: 7617 case ISD::OR: 7618 case ISD::XOR: 7619 case ISD::UREM: 7620 case ISD::SREM: 7621 case ISD::FREM: { 7622 SDValue LL, LH, RL, RH; 7623 SplitVectorOp(Node->getOperand(0), LL, LH); 7624 SplitVectorOp(Node->getOperand(1), RL, RH); 7625 7626 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL); 7627 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH); 7628 break; 7629 } 7630 case ISD::FP_ROUND: 7631 case ISD::FPOWI: { 7632 SDValue L, H; 7633 SplitVectorOp(Node->getOperand(0), L, H); 7634 7635 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1)); 7636 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1)); 7637 break; 7638 } 7639 case ISD::CTTZ: 7640 case ISD::CTLZ: 7641 case ISD::CTPOP: 7642 case ISD::FNEG: 7643 case ISD::FABS: 7644 case ISD::FSQRT: 7645 case ISD::FSIN: 7646 case ISD::FCOS: 7647 case ISD::FLOG: 7648 case ISD::FLOG2: 7649 case ISD::FLOG10: 7650 case ISD::FEXP: 7651 case ISD::FEXP2: 7652 case ISD::FP_TO_SINT: 7653 case ISD::FP_TO_UINT: 7654 case ISD::SINT_TO_FP: 7655 case ISD::UINT_TO_FP: 7656 case ISD::TRUNCATE: 7657 case ISD::ANY_EXTEND: 7658 case ISD::SIGN_EXTEND: 7659 case ISD::ZERO_EXTEND: 7660 case ISD::FP_EXTEND: { 7661 SDValue L, H; 7662 SplitVectorOp(Node->getOperand(0), L, H); 7663 7664 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L); 7665 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H); 7666 break; 7667 } 7668 case ISD::CONVERT_RNDSAT: { 7669 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 7670 SDValue L, H; 7671 SplitVectorOp(Node->getOperand(0), L, H); 7672 SDValue DTyOpL = DAG.getValueType(NewVT_Lo); 7673 SDValue DTyOpH = DAG.getValueType(NewVT_Hi); 7674 SDValue STyOpL = DAG.getValueType(L.getValueType()); 7675 SDValue STyOpH = DAG.getValueType(H.getValueType()); 7676 7677 SDValue RndOp = Node->getOperand(3); 7678 SDValue SatOp = Node->getOperand(4); 7679 7680 Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL, 7681 RndOp, SatOp, CvtCode); 7682 Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH, 7683 RndOp, SatOp, CvtCode); 7684 break; 7685 } 7686 case ISD::LOAD: { 7687 LoadSDNode *LD = cast<LoadSDNode>(Node); 7688 SDValue Ch = LD->getChain(); 7689 SDValue Ptr = LD->getBasePtr(); 7690 ISD::LoadExtType ExtType = LD->getExtensionType(); 7691 const Value *SV = LD->getSrcValue(); 7692 int SVOffset = LD->getSrcValueOffset(); 7693 MVT MemoryVT = LD->getMemoryVT(); 7694 unsigned Alignment = LD->getAlignment(); 7695 bool isVolatile = LD->isVolatile(); 7696 7697 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7698 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); 7699 7700 MVT MemNewEltVT = MemoryVT.getVectorElementType(); 7701 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo); 7702 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi); 7703 7704 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, 7705 NewVT_Lo, Ch, Ptr, Offset, 7706 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment); 7707 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8; 7708 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 7709 DAG.getIntPtrConstant(IncrementSize)); 7710 SVOffset += IncrementSize; 7711 Alignment = MinAlign(Alignment, IncrementSize); 7712 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, 7713 NewVT_Hi, Ch, Ptr, Offset, 7714 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment); 7715 7716 // Build a factor node to remember that this load is independent of the 7717 // other one. 7718 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 7719 Hi.getValue(1)); 7720 7721 // Remember that we legalized the chain. 7722 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF)); 7723 break; 7724 } 7725 case ISD::BIT_CONVERT: { 7726 // We know the result is a vector. The input may be either a vector or a 7727 // scalar value. 7728 SDValue InOp = Node->getOperand(0); 7729 if (!InOp.getValueType().isVector() || 7730 InOp.getValueType().getVectorNumElements() == 1) { 7731 // The input is a scalar or single-element vector. 7732 // Lower to a store/load so that it can be split. 7733 // FIXME: this could be improved probably. 7734 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment( 7735 Op.getValueType().getTypeForMVT()); 7736 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign); 7737 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex(); 7738 7739 SDValue St = DAG.getStore(DAG.getEntryNode(), 7740 InOp, Ptr, 7741 PseudoSourceValue::getFixedStack(FI), 0); 7742 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, 7743 PseudoSourceValue::getFixedStack(FI), 0); 7744 } 7745 // Split the vector and convert each of the pieces now. 7746 SplitVectorOp(InOp, Lo, Hi); 7747 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo); 7748 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi); 7749 break; 7750 } 7751 } 7752 7753 // Remember in a map if the values will be reused later. 7754 bool isNew = 7755 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second; 7756 assert(isNew && "Value already split?!?"); 7757 isNew = isNew; 7758} 7759 7760 7761/// ScalarizeVectorOp - Given an operand of single-element vector type 7762/// (e.g. v1f32), convert it into the equivalent operation that returns a 7763/// scalar (e.g. f32) value. 7764SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) { 7765 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!"); 7766 SDNode *Node = Op.getNode(); 7767 MVT NewVT = Op.getValueType().getVectorElementType(); 7768 assert(Op.getValueType().getVectorNumElements() == 1); 7769 7770 // See if we already scalarized it. 7771 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op); 7772 if (I != ScalarizedNodes.end()) return I->second; 7773 7774 SDValue Result; 7775 switch (Node->getOpcode()) { 7776 default: 7777#ifndef NDEBUG 7778 Node->dump(&DAG); cerr << "\n"; 7779#endif 7780 assert(0 && "Unknown vector operation in ScalarizeVectorOp!"); 7781 case ISD::ADD: 7782 case ISD::FADD: 7783 case ISD::SUB: 7784 case ISD::FSUB: 7785 case ISD::MUL: 7786 case ISD::FMUL: 7787 case ISD::SDIV: 7788 case ISD::UDIV: 7789 case ISD::FDIV: 7790 case ISD::SREM: 7791 case ISD::UREM: 7792 case ISD::FREM: 7793 case ISD::FPOW: 7794 case ISD::AND: 7795 case ISD::OR: 7796 case ISD::XOR: 7797 Result = DAG.getNode(Node->getOpcode(), 7798 NewVT, 7799 ScalarizeVectorOp(Node->getOperand(0)), 7800 ScalarizeVectorOp(Node->getOperand(1))); 7801 break; 7802 case ISD::FNEG: 7803 case ISD::FABS: 7804 case ISD::FSQRT: 7805 case ISD::FSIN: 7806 case ISD::FCOS: 7807 case ISD::FLOG: 7808 case ISD::FLOG2: 7809 case ISD::FLOG10: 7810 case ISD::FEXP: 7811 case ISD::FEXP2: 7812 case ISD::FP_TO_SINT: 7813 case ISD::FP_TO_UINT: 7814 case ISD::SINT_TO_FP: 7815 case ISD::UINT_TO_FP: 7816 case ISD::SIGN_EXTEND: 7817 case ISD::ZERO_EXTEND: 7818 case ISD::ANY_EXTEND: 7819 case ISD::TRUNCATE: 7820 case ISD::FP_EXTEND: 7821 Result = DAG.getNode(Node->getOpcode(), 7822 NewVT, 7823 ScalarizeVectorOp(Node->getOperand(0))); 7824 break; 7825 case ISD::CONVERT_RNDSAT: { 7826 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0)); 7827 Result = DAG.getConvertRndSat(NewVT, Op0, 7828 DAG.getValueType(NewVT), 7829 DAG.getValueType(Op0.getValueType()), 7830 Node->getOperand(3), 7831 Node->getOperand(4), 7832 cast<CvtRndSatSDNode>(Node)->getCvtCode()); 7833 break; 7834 } 7835 case ISD::FPOWI: 7836 case ISD::FP_ROUND: 7837 Result = DAG.getNode(Node->getOpcode(), 7838 NewVT, 7839 ScalarizeVectorOp(Node->getOperand(0)), 7840 Node->getOperand(1)); 7841 break; 7842 case ISD::LOAD: { 7843 LoadSDNode *LD = cast<LoadSDNode>(Node); 7844 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain. 7845 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer. 7846 ISD::LoadExtType ExtType = LD->getExtensionType(); 7847 const Value *SV = LD->getSrcValue(); 7848 int SVOffset = LD->getSrcValueOffset(); 7849 MVT MemoryVT = LD->getMemoryVT(); 7850 unsigned Alignment = LD->getAlignment(); 7851 bool isVolatile = LD->isVolatile(); 7852 7853 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!"); 7854 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType()); 7855 7856 Result = DAG.getLoad(ISD::UNINDEXED, ExtType, 7857 NewVT, Ch, Ptr, Offset, SV, SVOffset, 7858 MemoryVT.getVectorElementType(), 7859 isVolatile, Alignment); 7860 7861 // Remember that we legalized the chain. 7862 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); 7863 break; 7864 } 7865 case ISD::BUILD_VECTOR: 7866 Result = Node->getOperand(0); 7867 break; 7868 case ISD::INSERT_VECTOR_ELT: 7869 // Returning the inserted scalar element. 7870 Result = Node->getOperand(1); 7871 break; 7872 case ISD::CONCAT_VECTORS: 7873 assert(Node->getOperand(0).getValueType() == NewVT && 7874 "Concat of non-legal vectors not yet supported!"); 7875 Result = Node->getOperand(0); 7876 break; 7877 case ISD::VECTOR_SHUFFLE: { 7878 // Figure out if the scalar is the LHS or RHS and return it. 7879 SDValue EltNum = Node->getOperand(2).getOperand(0); 7880 if (cast<ConstantSDNode>(EltNum)->getZExtValue()) 7881 Result = ScalarizeVectorOp(Node->getOperand(1)); 7882 else 7883 Result = ScalarizeVectorOp(Node->getOperand(0)); 7884 break; 7885 } 7886 case ISD::EXTRACT_SUBVECTOR: 7887 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, Node->getOperand(0), 7888 Node->getOperand(1)); 7889 break; 7890 case ISD::BIT_CONVERT: { 7891 SDValue Op0 = Op.getOperand(0); 7892 if (Op0.getValueType().getVectorNumElements() == 1) 7893 Op0 = ScalarizeVectorOp(Op0); 7894 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0); 7895 break; 7896 } 7897 case ISD::SELECT: 7898 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0), 7899 ScalarizeVectorOp(Op.getOperand(1)), 7900 ScalarizeVectorOp(Op.getOperand(2))); 7901 break; 7902 case ISD::SELECT_CC: 7903 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0), 7904 Node->getOperand(1), 7905 ScalarizeVectorOp(Op.getOperand(2)), 7906 ScalarizeVectorOp(Op.getOperand(3)), 7907 Node->getOperand(4)); 7908 break; 7909 case ISD::VSETCC: { 7910 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0)); 7911 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1)); 7912 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1, 7913 Op.getOperand(2)); 7914 Result = DAG.getNode(ISD::SELECT, NewVT, Result, 7915 DAG.getConstant(-1ULL, NewVT), 7916 DAG.getConstant(0ULL, NewVT)); 7917 break; 7918 } 7919 } 7920 7921 if (TLI.isTypeLegal(NewVT)) 7922 Result = LegalizeOp(Result); 7923 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second; 7924 assert(isNew && "Value already scalarized?"); 7925 isNew = isNew; 7926 return Result; 7927} 7928 7929 7930SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) { 7931 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op); 7932 if (I != WidenNodes.end()) return I->second; 7933 7934 MVT VT = Op.getValueType(); 7935 assert(VT.isVector() && "Cannot widen non-vector type!"); 7936 7937 SDValue Result; 7938 SDNode *Node = Op.getNode(); 7939 MVT EVT = VT.getVectorElementType(); 7940 7941 unsigned NumElts = VT.getVectorNumElements(); 7942 unsigned NewNumElts = WidenVT.getVectorNumElements(); 7943 assert(NewNumElts > NumElts && "Cannot widen to smaller type!"); 7944 assert(NewNumElts < 17); 7945 7946 // When widen is called, it is assumed that it is more efficient to use a 7947 // wide type. The default action is to widen to operation to a wider legal 7948 // vector type and then do the operation if it is legal by calling LegalizeOp 7949 // again. If there is no vector equivalent, we will unroll the operation, do 7950 // it, and rebuild the vector. If most of the operations are vectorizible to 7951 // the legal type, the resulting code will be more efficient. If this is not 7952 // the case, the resulting code will preform badly as we end up generating 7953 // code to pack/unpack the results. It is the function that calls widen 7954 // that is responsible for seeing this doesn't happen. 7955 switch (Node->getOpcode()) { 7956 default: 7957#ifndef NDEBUG 7958 Node->dump(&DAG); 7959#endif 7960 assert(0 && "Unexpected operation in WidenVectorOp!"); 7961 break; 7962 case ISD::CopyFromReg: 7963 assert(0 && "CopyFromReg doesn't need widening!"); 7964 case ISD::Constant: 7965 case ISD::ConstantFP: 7966 // To build a vector of these elements, clients should call BuildVector 7967 // and with each element instead of creating a node with a vector type 7968 assert(0 && "Unexpected operation in WidenVectorOp!"); 7969 case ISD::VAARG: 7970 // Variable Arguments with vector types doesn't make any sense to me 7971 assert(0 && "Unexpected operation in WidenVectorOp!"); 7972 break; 7973 case ISD::UNDEF: 7974 Result = DAG.getNode(ISD::UNDEF, WidenVT); 7975 break; 7976 case ISD::BUILD_VECTOR: { 7977 // Build a vector with undefined for the new nodes 7978 SDValueVector NewOps(Node->op_begin(), Node->op_end()); 7979 for (unsigned i = NumElts; i < NewNumElts; ++i) { 7980 NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT)); 7981 } 7982 Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size()); 7983 break; 7984 } 7985 case ISD::INSERT_VECTOR_ELT: { 7986 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 7987 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1, 7988 Node->getOperand(1), Node->getOperand(2)); 7989 break; 7990 } 7991 case ISD::VECTOR_SHUFFLE: { 7992 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 7993 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT); 7994 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is 7995 // used as permutation array. We build the vector here instead of widening 7996 // because we don't want to legalize and have it turned to something else. 7997 SDValue PermOp = Node->getOperand(2); 7998 SDValueVector NewOps; 7999 MVT PVT = PermOp.getValueType().getVectorElementType(); 8000 for (unsigned i = 0; i < NumElts; ++i) { 8001 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) { 8002 NewOps.push_back(PermOp.getOperand(i)); 8003 } else { 8004 unsigned Idx = 8005 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue(); 8006 if (Idx < NumElts) { 8007 NewOps.push_back(PermOp.getOperand(i)); 8008 } 8009 else { 8010 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts, 8011 PermOp.getOperand(i).getValueType())); 8012 } 8013 } 8014 } 8015 for (unsigned i = NumElts; i < NewNumElts; ++i) { 8016 NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT)); 8017 } 8018 8019 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, 8020 MVT::getVectorVT(PVT, NewOps.size()), 8021 &NewOps[0], NewOps.size()); 8022 8023 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3); 8024 break; 8025 } 8026 case ISD::LOAD: { 8027 // If the load widen returns true, we can use a single load for the 8028 // vector. Otherwise, it is returning a token factor for multiple 8029 // loads. 8030 SDValue TFOp; 8031 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT)) 8032 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1))); 8033 else 8034 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0))); 8035 break; 8036 } 8037 8038 case ISD::BIT_CONVERT: { 8039 SDValue Tmp1 = Node->getOperand(0); 8040 // Converts between two different types so we need to determine 8041 // the correct widen type for the input operand. 8042 MVT TVT = Tmp1.getValueType(); 8043 assert(TVT.isVector() && "can not widen non vector type"); 8044 MVT TEVT = TVT.getVectorElementType(); 8045 assert(WidenVT.getSizeInBits() % EVT.getSizeInBits() == 0 && 8046 "can not widen bit bit convert that are not multiple of element type"); 8047 MVT TWidenVT = MVT::getVectorVT(TEVT, 8048 WidenVT.getSizeInBits()/EVT.getSizeInBits()); 8049 Tmp1 = WidenVectorOp(Tmp1, TWidenVT); 8050 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits()); 8051 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1); 8052 8053 TargetLowering::LegalizeAction action = 8054 TLI.getOperationAction(Node->getOpcode(), WidenVT); 8055 switch (action) { 8056 default: assert(0 && "action not supported"); 8057 case TargetLowering::Legal: 8058 break; 8059 case TargetLowering::Promote: 8060 // We defer the promotion to when we legalize the op 8061 break; 8062 case TargetLowering::Expand: 8063 // Expand the operation into a bunch of nasty scalar code. 8064 Result = LegalizeOp(UnrollVectorOp(Result)); 8065 break; 8066 } 8067 break; 8068 } 8069 8070 case ISD::SINT_TO_FP: 8071 case ISD::UINT_TO_FP: 8072 case ISD::FP_TO_SINT: 8073 case ISD::FP_TO_UINT: { 8074 SDValue Tmp1 = Node->getOperand(0); 8075 // Converts between two different types so we need to determine 8076 // the correct widen type for the input operand. 8077 MVT TVT = Tmp1.getValueType(); 8078 assert(TVT.isVector() && "can not widen non vector type"); 8079 MVT TEVT = TVT.getVectorElementType(); 8080 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts); 8081 Tmp1 = WidenVectorOp(Tmp1, TWidenVT); 8082 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts); 8083 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1); 8084 break; 8085 } 8086 8087 case ISD::FP_EXTEND: 8088 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!"); 8089 case ISD::TRUNCATE: 8090 case ISD::SIGN_EXTEND: 8091 case ISD::ZERO_EXTEND: 8092 case ISD::ANY_EXTEND: 8093 case ISD::FP_ROUND: 8094 case ISD::SIGN_EXTEND_INREG: 8095 case ISD::FABS: 8096 case ISD::FNEG: 8097 case ISD::FSQRT: 8098 case ISD::FSIN: 8099 case ISD::FCOS: 8100 case ISD::CTPOP: 8101 case ISD::CTTZ: 8102 case ISD::CTLZ: { 8103 // Unary op widening 8104 SDValue Tmp1; 8105 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8106 assert(Tmp1.getValueType() == WidenVT); 8107 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1); 8108 break; 8109 } 8110 case ISD::CONVERT_RNDSAT: { 8111 SDValue RndOp = Node->getOperand(3); 8112 SDValue SatOp = Node->getOperand(4); 8113 SDValue SrcOp = Node->getOperand(0); 8114 8115 // Converts between two different types so we need to determine 8116 // the correct widen type for the input operand. 8117 MVT SVT = SrcOp.getValueType(); 8118 assert(SVT.isVector() && "can not widen non vector type"); 8119 MVT SEVT = SVT.getVectorElementType(); 8120 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts); 8121 8122 SrcOp = WidenVectorOp(SrcOp, SWidenVT); 8123 assert(SrcOp.getValueType() == WidenVT); 8124 SDValue DTyOp = DAG.getValueType(WidenVT); 8125 SDValue STyOp = DAG.getValueType(SrcOp.getValueType()); 8126 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode(); 8127 8128 Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp, 8129 RndOp, SatOp, CvtCode); 8130 break; 8131 } 8132 case ISD::FPOW: 8133 case ISD::FPOWI: 8134 case ISD::ADD: 8135 case ISD::SUB: 8136 case ISD::MUL: 8137 case ISD::MULHS: 8138 case ISD::MULHU: 8139 case ISD::AND: 8140 case ISD::OR: 8141 case ISD::XOR: 8142 case ISD::FADD: 8143 case ISD::FSUB: 8144 case ISD::FMUL: 8145 case ISD::SDIV: 8146 case ISD::SREM: 8147 case ISD::FDIV: 8148 case ISD::FREM: 8149 case ISD::FCOPYSIGN: 8150 case ISD::UDIV: 8151 case ISD::UREM: 8152 case ISD::BSWAP: { 8153 // Binary op widening 8154 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8155 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT); 8156 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT); 8157 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2); 8158 break; 8159 } 8160 8161 case ISD::SHL: 8162 case ISD::SRA: 8163 case ISD::SRL: { 8164 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8165 assert(Tmp1.getValueType() == WidenVT); 8166 SDValue ShOp = Node->getOperand(1); 8167 MVT ShVT = ShOp.getValueType(); 8168 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(), 8169 WidenVT.getVectorNumElements()); 8170 ShOp = WidenVectorOp(ShOp, NewShVT); 8171 assert(ShOp.getValueType() == NewShVT); 8172 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, ShOp); 8173 break; 8174 } 8175 8176 case ISD::EXTRACT_VECTOR_ELT: { 8177 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT); 8178 assert(Tmp1.getValueType() == WidenVT); 8179 Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1)); 8180 break; 8181 } 8182 case ISD::CONCAT_VECTORS: { 8183 // We concurrently support only widen on a multiple of the incoming vector. 8184 // We could widen on a multiple of the incoming operand if necessary. 8185 unsigned NumConcat = NewNumElts / NumElts; 8186 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector"); 8187 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT); 8188 SmallVector<SDValue, 8> MOps; 8189 MOps.push_back(Op); 8190 for (unsigned i = 1; i != NumConcat; ++i) { 8191 MOps.push_back(UndefVal); 8192 } 8193 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT, 8194 &MOps[0], MOps.size())); 8195 break; 8196 } 8197 case ISD::EXTRACT_SUBVECTOR: { 8198 SDValue Tmp1 = Node->getOperand(0); 8199 SDValue Idx = Node->getOperand(1); 8200 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx); 8201 if (CIdx && CIdx->getZExtValue() == 0) { 8202 // Since we are access the start of the vector, the incoming 8203 // vector type might be the proper. 8204 MVT Tmp1VT = Tmp1.getValueType(); 8205 if (Tmp1VT == WidenVT) 8206 return Tmp1; 8207 else { 8208 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements(); 8209 if (Tmp1VTNumElts < NewNumElts) 8210 Result = WidenVectorOp(Tmp1, WidenVT); 8211 else 8212 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, Tmp1, Idx); 8213 } 8214 } else if (NewNumElts % NumElts == 0) { 8215 // Widen the extracted subvector. 8216 unsigned NumConcat = NewNumElts / NumElts; 8217 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT); 8218 SmallVector<SDValue, 8> MOps; 8219 MOps.push_back(Op); 8220 for (unsigned i = 1; i != NumConcat; ++i) { 8221 MOps.push_back(UndefVal); 8222 } 8223 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT, 8224 &MOps[0], MOps.size())); 8225 } else { 8226 assert(0 && "can not widen extract subvector"); 8227 // This could be implemented using insert and build vector but I would 8228 // like to see when this happens. 8229 } 8230 break; 8231 } 8232 8233 case ISD::SELECT: { 8234 // Determine new condition widen type and widen 8235 SDValue Cond1 = Node->getOperand(0); 8236 MVT CondVT = Cond1.getValueType(); 8237 assert(CondVT.isVector() && "can not widen non vector type"); 8238 MVT CondEVT = CondVT.getVectorElementType(); 8239 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts); 8240 Cond1 = WidenVectorOp(Cond1, CondWidenVT); 8241 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen"); 8242 8243 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT); 8244 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT); 8245 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT); 8246 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2); 8247 break; 8248 } 8249 8250 case ISD::SELECT_CC: { 8251 // Determine new condition widen type and widen 8252 SDValue Cond1 = Node->getOperand(0); 8253 SDValue Cond2 = Node->getOperand(1); 8254 MVT CondVT = Cond1.getValueType(); 8255 assert(CondVT.isVector() && "can not widen non vector type"); 8256 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs"); 8257 MVT CondEVT = CondVT.getVectorElementType(); 8258 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts); 8259 Cond1 = WidenVectorOp(Cond1, CondWidenVT); 8260 Cond2 = WidenVectorOp(Cond2, CondWidenVT); 8261 assert(Cond1.getValueType() == CondWidenVT && 8262 Cond2.getValueType() == CondWidenVT && "condition not widen"); 8263 8264 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT); 8265 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT); 8266 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT && 8267 "operands not widen"); 8268 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1, 8269 Tmp2, Node->getOperand(4)); 8270 break; 8271 } 8272 case ISD::VSETCC: { 8273 // Determine widen for the operand 8274 SDValue Tmp1 = Node->getOperand(0); 8275 MVT TmpVT = Tmp1.getValueType(); 8276 assert(TmpVT.isVector() && "can not widen non vector type"); 8277 MVT TmpEVT = TmpVT.getVectorElementType(); 8278 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts); 8279 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT); 8280 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT); 8281 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2, 8282 Node->getOperand(2)); 8283 break; 8284 } 8285 case ISD::ATOMIC_CMP_SWAP_8: 8286 case ISD::ATOMIC_CMP_SWAP_16: 8287 case ISD::ATOMIC_CMP_SWAP_32: 8288 case ISD::ATOMIC_CMP_SWAP_64: 8289 case ISD::ATOMIC_LOAD_ADD_8: 8290 case ISD::ATOMIC_LOAD_SUB_8: 8291 case ISD::ATOMIC_LOAD_AND_8: 8292 case ISD::ATOMIC_LOAD_OR_8: 8293 case ISD::ATOMIC_LOAD_XOR_8: 8294 case ISD::ATOMIC_LOAD_NAND_8: 8295 case ISD::ATOMIC_LOAD_MIN_8: 8296 case ISD::ATOMIC_LOAD_MAX_8: 8297 case ISD::ATOMIC_LOAD_UMIN_8: 8298 case ISD::ATOMIC_LOAD_UMAX_8: 8299 case ISD::ATOMIC_SWAP_8: 8300 case ISD::ATOMIC_LOAD_ADD_16: 8301 case ISD::ATOMIC_LOAD_SUB_16: 8302 case ISD::ATOMIC_LOAD_AND_16: 8303 case ISD::ATOMIC_LOAD_OR_16: 8304 case ISD::ATOMIC_LOAD_XOR_16: 8305 case ISD::ATOMIC_LOAD_NAND_16: 8306 case ISD::ATOMIC_LOAD_MIN_16: 8307 case ISD::ATOMIC_LOAD_MAX_16: 8308 case ISD::ATOMIC_LOAD_UMIN_16: 8309 case ISD::ATOMIC_LOAD_UMAX_16: 8310 case ISD::ATOMIC_SWAP_16: 8311 case ISD::ATOMIC_LOAD_ADD_32: 8312 case ISD::ATOMIC_LOAD_SUB_32: 8313 case ISD::ATOMIC_LOAD_AND_32: 8314 case ISD::ATOMIC_LOAD_OR_32: 8315 case ISD::ATOMIC_LOAD_XOR_32: 8316 case ISD::ATOMIC_LOAD_NAND_32: 8317 case ISD::ATOMIC_LOAD_MIN_32: 8318 case ISD::ATOMIC_LOAD_MAX_32: 8319 case ISD::ATOMIC_LOAD_UMIN_32: 8320 case ISD::ATOMIC_LOAD_UMAX_32: 8321 case ISD::ATOMIC_SWAP_32: 8322 case ISD::ATOMIC_LOAD_ADD_64: 8323 case ISD::ATOMIC_LOAD_SUB_64: 8324 case ISD::ATOMIC_LOAD_AND_64: 8325 case ISD::ATOMIC_LOAD_OR_64: 8326 case ISD::ATOMIC_LOAD_XOR_64: 8327 case ISD::ATOMIC_LOAD_NAND_64: 8328 case ISD::ATOMIC_LOAD_MIN_64: 8329 case ISD::ATOMIC_LOAD_MAX_64: 8330 case ISD::ATOMIC_LOAD_UMIN_64: 8331 case ISD::ATOMIC_LOAD_UMAX_64: 8332 case ISD::ATOMIC_SWAP_64: { 8333 // For now, we assume that using vectors for these operations don't make 8334 // much sense so we just split it. We return an empty result 8335 SDValue X, Y; 8336 SplitVectorOp(Op, X, Y); 8337 return Result; 8338 break; 8339 } 8340 8341 } // end switch (Node->getOpcode()) 8342 8343 assert(Result.getNode() && "Didn't set a result!"); 8344 if (Result != Op) 8345 Result = LegalizeOp(Result); 8346 8347 AddWidenedOperand(Op, Result); 8348 return Result; 8349} 8350 8351// Utility function to find a legal vector type and its associated element 8352// type from a preferred width and whose vector type must be the same size 8353// as the VVT. 8354// TLI: Target lowering used to determine legal types 8355// Width: Preferred width of element type 8356// VVT: Vector value type whose size we must match. 8357// Returns VecEVT and EVT - the vector type and its associated element type 8358static void FindWidenVecType(TargetLowering &TLI, unsigned Width, MVT VVT, 8359 MVT& EVT, MVT& VecEVT) { 8360 // We start with the preferred width, make it a power of 2 and see if 8361 // we can find a vector type of that width. If not, we reduce it by 8362 // another power of 2. If we have widen the type, a vector of bytes should 8363 // always be legal. 8364 assert(TLI.isTypeLegal(VVT)); 8365 unsigned EWidth = Width + 1; 8366 do { 8367 assert(EWidth > 0); 8368 EWidth = (1 << Log2_32(EWidth-1)); 8369 EVT = MVT::getIntegerVT(EWidth); 8370 unsigned NumEVT = VVT.getSizeInBits()/EWidth; 8371 VecEVT = MVT::getVectorVT(EVT, NumEVT); 8372 } while (!TLI.isTypeLegal(VecEVT) || 8373 VVT.getSizeInBits() != VecEVT.getSizeInBits()); 8374} 8375 8376SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain, 8377 SDValue Chain, 8378 SDValue BasePtr, 8379 const Value *SV, 8380 int SVOffset, 8381 unsigned Alignment, 8382 bool isVolatile, 8383 unsigned LdWidth, 8384 MVT ResType) { 8385 // We assume that we have good rules to handle loading power of two loads so 8386 // we break down the operations to power of 2 loads. The strategy is to 8387 // load the largest power of 2 that we can easily transform to a legal vector 8388 // and then insert into that vector, and the cast the result into the legal 8389 // vector that we want. This avoids unnecessary stack converts. 8390 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and 8391 // the load is nonvolatile, we an use a wider load for the value. 8392 // Find a vector length we can load a large chunk 8393 MVT EVT, VecEVT; 8394 unsigned EVTWidth; 8395 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT); 8396 EVTWidth = EVT.getSizeInBits(); 8397 8398 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset, 8399 isVolatile, Alignment); 8400 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp); 8401 LdChain.push_back(LdOp.getValue(1)); 8402 8403 // Check if we can load the element with one instruction 8404 if (LdWidth == EVTWidth) { 8405 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp); 8406 } 8407 8408 // The vector element order is endianness dependent. 8409 unsigned Idx = 1; 8410 LdWidth -= EVTWidth; 8411 unsigned Offset = 0; 8412 8413 while (LdWidth > 0) { 8414 unsigned Increment = EVTWidth / 8; 8415 Offset += Increment; 8416 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr, 8417 DAG.getIntPtrConstant(Increment)); 8418 8419 if (LdWidth < EVTWidth) { 8420 // Our current type we are using is too large, use a smaller size by 8421 // using a smaller power of 2 8422 unsigned oEVTWidth = EVTWidth; 8423 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT); 8424 EVTWidth = EVT.getSizeInBits(); 8425 // Readjust position and vector position based on new load type 8426 Idx = Idx * (oEVTWidth/EVTWidth); 8427 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp); 8428 } 8429 8430 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, 8431 SVOffset+Offset, isVolatile, 8432 MinAlign(Alignment, Offset)); 8433 LdChain.push_back(LdOp.getValue(1)); 8434 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp, 8435 DAG.getIntPtrConstant(Idx++)); 8436 8437 LdWidth -= EVTWidth; 8438 } 8439 8440 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp); 8441} 8442 8443bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result, 8444 SDValue& TFOp, 8445 SDValue Op, 8446 MVT NVT) { 8447 // TODO: Add support for ConcatVec and the ability to load many vector 8448 // types (e.g., v4i8). This will not work when a vector register 8449 // to memory mapping is strange (e.g., vector elements are not 8450 // stored in some sequential order). 8451 8452 // It must be true that the widen vector type is bigger than where 8453 // we need to load from. 8454 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); 8455 MVT LdVT = LD->getMemoryVT(); 8456 assert(LdVT.isVector() && NVT.isVector()); 8457 assert(LdVT.getVectorElementType() == NVT.getVectorElementType()); 8458 8459 // Load information 8460 SDValue Chain = LD->getChain(); 8461 SDValue BasePtr = LD->getBasePtr(); 8462 int SVOffset = LD->getSrcValueOffset(); 8463 unsigned Alignment = LD->getAlignment(); 8464 bool isVolatile = LD->isVolatile(); 8465 const Value *SV = LD->getSrcValue(); 8466 unsigned int LdWidth = LdVT.getSizeInBits(); 8467 8468 // Load value as a large register 8469 SDValueVector LdChain; 8470 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset, 8471 Alignment, isVolatile, LdWidth, NVT); 8472 8473 if (LdChain.size() == 1) { 8474 TFOp = LdChain[0]; 8475 return true; 8476 } 8477 else { 8478 TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size()); 8479 return false; 8480 } 8481} 8482 8483 8484void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain, 8485 SDValue Chain, 8486 SDValue BasePtr, 8487 const Value *SV, 8488 int SVOffset, 8489 unsigned Alignment, 8490 bool isVolatile, 8491 SDValue ValOp, 8492 unsigned StWidth) { 8493 // Breaks the stores into a series of power of 2 width stores. For any 8494 // width, we convert the vector to the vector of element size that we 8495 // want to store. This avoids requiring a stack convert. 8496 8497 // Find a width of the element type we can store with 8498 MVT VVT = ValOp.getValueType(); 8499 MVT EVT, VecEVT; 8500 unsigned EVTWidth; 8501 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT); 8502 EVTWidth = EVT.getSizeInBits(); 8503 8504 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp); 8505 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp, 8506 DAG.getIntPtrConstant(0)); 8507 SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset, 8508 isVolatile, Alignment); 8509 StChain.push_back(StOp); 8510 8511 // Check if we are done 8512 if (StWidth == EVTWidth) { 8513 return; 8514 } 8515 8516 unsigned Idx = 1; 8517 StWidth -= EVTWidth; 8518 unsigned Offset = 0; 8519 8520 while (StWidth > 0) { 8521 unsigned Increment = EVTWidth / 8; 8522 Offset += Increment; 8523 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr, 8524 DAG.getIntPtrConstant(Increment)); 8525 8526 if (StWidth < EVTWidth) { 8527 // Our current type we are using is too large, use a smaller size by 8528 // using a smaller power of 2 8529 unsigned oEVTWidth = EVTWidth; 8530 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT); 8531 EVTWidth = EVT.getSizeInBits(); 8532 // Readjust position and vector position based on new load type 8533 Idx = Idx * (oEVTWidth/EVTWidth); 8534 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp); 8535 } 8536 8537 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp, 8538 DAG.getIntPtrConstant(Idx++)); 8539 StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV, 8540 SVOffset + Offset, isVolatile, 8541 MinAlign(Alignment, Offset))); 8542 StWidth -= EVTWidth; 8543 } 8544} 8545 8546 8547SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST, 8548 SDValue Chain, 8549 SDValue BasePtr) { 8550 // TODO: It might be cleaner if we can use SplitVector and have more legal 8551 // vector types that can be stored into memory (e.g., v4xi8 can 8552 // be stored as a word). This will not work when a vector register 8553 // to memory mapping is strange (e.g., vector elements are not 8554 // stored in some sequential order). 8555 8556 MVT StVT = ST->getMemoryVT(); 8557 SDValue ValOp = ST->getValue(); 8558 8559 // Check if we have widen this node with another value 8560 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp); 8561 if (I != WidenNodes.end()) 8562 ValOp = I->second; 8563 8564 MVT VVT = ValOp.getValueType(); 8565 8566 // It must be true that we the widen vector type is bigger than where 8567 // we need to store. 8568 assert(StVT.isVector() && VVT.isVector()); 8569 assert(StVT.getSizeInBits() < VVT.getSizeInBits()); 8570 assert(StVT.getVectorElementType() == VVT.getVectorElementType()); 8571 8572 // Store value 8573 SDValueVector StChain; 8574 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(), 8575 ST->getSrcValueOffset(), ST->getAlignment(), 8576 ST->isVolatile(), ValOp, StVT.getSizeInBits()); 8577 if (StChain.size() == 1) 8578 return StChain[0]; 8579 else 8580 return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size()); 8581} 8582 8583 8584// SelectionDAG::Legalize - This is the entry point for the file. 8585// 8586void SelectionDAG::Legalize() { 8587 /// run - This is the main entry point to this class. 8588 /// 8589 SelectionDAGLegalize(*this).LegalizeDAG(); 8590} 8591 8592