LegalizeIntegerTypes.cpp revision 0be10b0b53610b5c543713acf5d4f3ff68ed8319
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22#include "llvm/CodeGen/PseudoSourceValue.h" 23#include "llvm/Support/ErrorHandling.h" 24#include "llvm/Support/raw_ostream.h" 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28// Integer Result Promotion 29//===----------------------------------------------------------------------===// 30 31/// PromoteIntegerResult - This method is called when a result of a node is 32/// found to be in need of promotion to a larger type. At this point, the node 33/// may also have invalid operands or may have other results that need 34/// expansion, we just know that (at least) one result needs promotion. 35void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 36 DEBUG(errs() << "Promote integer result: "; N->dump(&DAG); errs() << "\n"); 37 SDValue Res = SDValue(); 38 39 // See if the target wants to custom expand this node. 40 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 41 return; 42 43 switch (N->getOpcode()) { 44 default: 45#ifndef NDEBUG 46 errs() << "PromoteIntegerResult #" << ResNo << ": "; 47 N->dump(&DAG); errs() << "\n"; 48#endif 49 llvm_unreachable("Do not know how to promote this operator!"); 50 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 51 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 52 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break; 53 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 54 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 55 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 56 case ISD::CONVERT_RNDSAT: 57 Res = PromoteIntRes_CONVERT_RNDSAT(N); break; 58 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; 59 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break; 60 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; 61 case ISD::EXTRACT_VECTOR_ELT: 62 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 63 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 64 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break; 65 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; 66 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 67 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 68 case ISD::SIGN_EXTEND_INREG: 69 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 70 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 71 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 72 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; 73 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; 74 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; 75 76 case ISD::SIGN_EXTEND: 77 case ISD::ZERO_EXTEND: 78 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; 79 80 case ISD::FP_TO_SINT: 81 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; 82 83 case ISD::AND: 84 case ISD::OR: 85 case ISD::XOR: 86 case ISD::ADD: 87 case ISD::SUB: 88 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break; 89 90 case ISD::SDIV: 91 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; 92 93 case ISD::UDIV: 94 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break; 95 96 case ISD::SADDO: 97 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; 98 case ISD::UADDO: 99 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; 100 case ISD::SMULO: 101 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; 102 103 case ISD::ATOMIC_LOAD_ADD: 104 case ISD::ATOMIC_LOAD_SUB: 105 case ISD::ATOMIC_LOAD_AND: 106 case ISD::ATOMIC_LOAD_OR: 107 case ISD::ATOMIC_LOAD_XOR: 108 case ISD::ATOMIC_LOAD_NAND: 109 case ISD::ATOMIC_LOAD_MIN: 110 case ISD::ATOMIC_LOAD_MAX: 111 case ISD::ATOMIC_LOAD_UMIN: 112 case ISD::ATOMIC_LOAD_UMAX: 113 case ISD::ATOMIC_SWAP: 114 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 115 116 case ISD::ATOMIC_CMP_SWAP: 117 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 118 } 119 120 // If the result is null then the sub-method took care of registering it. 121 if (Res.getNode()) 122 SetPromotedInteger(SDValue(N, ResNo), Res); 123} 124 125SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 126 // Sign-extend the new bits, and continue the assertion. 127 SDValue Op = SExtPromotedInteger(N->getOperand(0)); 128 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), 129 Op.getValueType(), Op, N->getOperand(1)); 130} 131 132SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 133 // Zero the new bits, and continue the assertion. 134 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 135 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), 136 Op.getValueType(), Op, N->getOperand(1)); 137} 138 139SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 140 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 141 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 142 N->getMemoryVT(), 143 N->getChain(), N->getBasePtr(), 144 Op2, N->getSrcValue(), N->getAlignment()); 145 // Legalized the chain result - switch anything that used the old chain to 146 // use the new one. 147 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 148 return Res; 149} 150 151SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 152 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 153 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 154 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 155 N->getMemoryVT(), N->getChain(), N->getBasePtr(), 156 Op2, Op3, N->getSrcValue(), N->getAlignment()); 157 // Legalized the chain result - switch anything that used the old chain to 158 // use the new one. 159 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 160 return Res; 161} 162 163SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 164 SDValue InOp = N->getOperand(0); 165 MVT InVT = InOp.getValueType(); 166 MVT NInVT = TLI.getTypeToTransformTo(InVT); 167 MVT OutVT = N->getValueType(0); 168 MVT NOutVT = TLI.getTypeToTransformTo(OutVT); 169 DebugLoc dl = N->getDebugLoc(); 170 171 switch (getTypeAction(InVT)) { 172 default: 173 assert(false && "Unknown type action!"); 174 break; 175 case Legal: 176 break; 177 case PromoteInteger: 178 if (NOutVT.bitsEq(NInVT)) 179 // The input promotes to the same size. Convert the promoted value. 180 return DAG.getNode(ISD::BIT_CONVERT, dl, 181 NOutVT, GetPromotedInteger(InOp)); 182 break; 183 case SoftenFloat: 184 // Promote the integer operand by hand. 185 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); 186 case ExpandInteger: 187 case ExpandFloat: 188 break; 189 case ScalarizeVector: 190 // Convert the element to an integer and promote it by hand. 191 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 192 BitConvertToInteger(GetScalarizedVector(InOp))); 193 case SplitVector: { 194 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 195 // pieces of the input into integers and reassemble in the final type. 196 SDValue Lo, Hi; 197 GetSplitVector(N->getOperand(0), Lo, Hi); 198 Lo = BitConvertToInteger(Lo); 199 Hi = BitConvertToInteger(Hi); 200 201 if (TLI.isBigEndian()) 202 std::swap(Lo, Hi); 203 204 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, 205 MVT::getIntegerVT(NOutVT.getSizeInBits()), 206 JoinIntegers(Lo, Hi)); 207 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp); 208 } 209 case WidenVector: 210 if (OutVT.bitsEq(NInVT)) 211 // The input is widened to the same size. Convert to the widened value. 212 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp)); 213 } 214 215 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 216 CreateStackStoreLoad(InOp, OutVT)); 217} 218 219SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 220 SDValue Op = GetPromotedInteger(N->getOperand(0)); 221 MVT OVT = N->getValueType(0); 222 MVT NVT = Op.getValueType(); 223 DebugLoc dl = N->getDebugLoc(); 224 225 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 226 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 227 DAG.getConstant(DiffBits, TLI.getPointerTy())); 228} 229 230SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 231 // The pair element type may be legal, or may not promote to the same type as 232 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 233 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), 234 TLI.getTypeToTransformTo(N->getValueType(0)), 235 JoinIntegers(N->getOperand(0), N->getOperand(1))); 236} 237 238SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 239 MVT VT = N->getValueType(0); 240 // FIXME there is no actual debug info here 241 DebugLoc dl = N->getDebugLoc(); 242 // Zero extend things like i1, sign extend everything else. It shouldn't 243 // matter in theory which one we pick, but this tends to give better code? 244 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 245 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(VT), 246 SDValue(N, 0)); 247 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 248 return Result; 249} 250 251SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 252 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 253 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 254 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 255 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 256 "can only promote integers"); 257 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 258 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0), 259 N->getOperand(1), N->getOperand(2), 260 N->getOperand(3), N->getOperand(4), CvtCode); 261} 262 263SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 264 // Zero extend to the promoted type and do the count there. 265 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 266 DebugLoc dl = N->getDebugLoc(); 267 MVT OVT = N->getValueType(0); 268 MVT NVT = Op.getValueType(); 269 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op); 270 // Subtract off the extra leading bits in the bigger type. 271 return DAG.getNode(ISD::SUB, dl, NVT, Op, 272 DAG.getConstant(NVT.getSizeInBits() - 273 OVT.getSizeInBits(), NVT)); 274} 275 276SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 277 // Zero extend to the promoted type and do the count there. 278 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 279 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op); 280} 281 282SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 283 SDValue Op = GetPromotedInteger(N->getOperand(0)); 284 MVT OVT = N->getValueType(0); 285 MVT NVT = Op.getValueType(); 286 DebugLoc dl = N->getDebugLoc(); 287 // The count is the same in the promoted type except if the original 288 // value was zero. This can be handled by setting the bit just off 289 // the top of the original type. 290 APInt TopBit(NVT.getSizeInBits(), 0); 291 TopBit.set(OVT.getSizeInBits()); 292 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT)); 293 return DAG.getNode(ISD::CTTZ, dl, NVT, Op); 294} 295 296SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 297 DebugLoc dl = N->getDebugLoc(); 298 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 299 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0), 300 N->getOperand(1)); 301} 302 303SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 304 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 305 unsigned NewOpc = N->getOpcode(); 306 DebugLoc dl = N->getDebugLoc(); 307 308 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is 309 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT 310 // and SINT conversions are Custom, there is no way to tell which is preferable. 311 // We choose SINT because that's the right thing on PPC.) 312 if (N->getOpcode() == ISD::FP_TO_UINT && 313 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 314 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) 315 NewOpc = ISD::FP_TO_SINT; 316 317 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); 318 319 // Assert that the converted value fits in the original type. If it doesn't 320 // (eg: because the value being converted is too big), then the result of the 321 // original operation was undefined anyway, so the assert is still correct. 322 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 323 ISD::AssertZext : ISD::AssertSext, dl, 324 NVT, Res, DAG.getValueType(N->getValueType(0))); 325} 326 327SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 328 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 329 DebugLoc dl = N->getDebugLoc(); 330 331 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 332 SDValue Res = GetPromotedInteger(N->getOperand(0)); 333 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 334 335 // If the result and operand types are the same after promotion, simplify 336 // to an in-register extension. 337 if (NVT == Res.getValueType()) { 338 // The high bits are not guaranteed to be anything. Insert an extend. 339 if (N->getOpcode() == ISD::SIGN_EXTEND) 340 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 341 DAG.getValueType(N->getOperand(0).getValueType())); 342 if (N->getOpcode() == ISD::ZERO_EXTEND) 343 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType()); 344 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 345 return Res; 346 } 347 } 348 349 // Otherwise, just extend the original operand all the way to the larger type. 350 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 351} 352 353SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 354 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 355 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 356 ISD::LoadExtType ExtType = 357 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 358 DebugLoc dl = N->getDebugLoc(); 359 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), 360 N->getSrcValue(), N->getSrcValueOffset(), 361 N->getMemoryVT(), N->isVolatile(), 362 N->getAlignment()); 363 364 // Legalized the chain result - switch anything that used the old chain to 365 // use the new one. 366 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 367 return Res; 368} 369 370/// Promote the overflow flag of an overflowing arithmetic node. 371SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { 372 // Simply change the return type of the boolean result. 373 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); 374 MVT ValueVTs[] = { N->getValueType(0), NVT }; 375 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; 376 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), 377 DAG.getVTList(ValueVTs, 2), Ops, 2); 378 379 // Modified the sum result - switch anything that used the old sum to use 380 // the new one. 381 ReplaceValueWith(SDValue(N, 0), Res); 382 383 return SDValue(Res.getNode(), 1); 384} 385 386SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { 387 if (ResNo == 1) 388 return PromoteIntRes_Overflow(N); 389 390 // The operation overflowed iff the result in the larger type is not the 391 // sign extension of its truncation to the original type. 392 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 393 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 394 MVT OVT = N->getOperand(0).getValueType(); 395 MVT NVT = LHS.getValueType(); 396 DebugLoc dl = N->getDebugLoc(); 397 398 // Do the arithmetic in the larger type. 399 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 400 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 401 402 // Calculate the overflow flag: sign extend the arithmetic result from 403 // the original type. 404 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 405 DAG.getValueType(OVT)); 406 // Overflowed if and only if this is not equal to Res. 407 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 408 409 // Use the calculated overflow everywhere. 410 ReplaceValueWith(SDValue(N, 1), Ofl); 411 412 return Res; 413} 414 415SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 416 // Sign extend the input. 417 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 418 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 419 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 420 LHS.getValueType(), LHS, RHS); 421} 422 423SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 424 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 425 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 426 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 427 LHS.getValueType(), N->getOperand(0),LHS,RHS); 428} 429 430SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 431 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 432 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 433 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 434 LHS.getValueType(), N->getOperand(0), 435 N->getOperand(1), LHS, RHS, N->getOperand(4)); 436} 437 438SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 439 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); 440 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 441 DebugLoc dl = N->getDebugLoc(); 442 443 // Get the SETCC result using the canonical SETCC type. 444 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0), 445 N->getOperand(1), N->getOperand(2)); 446 447 // Convert to the expected type. 448 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 449 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 450 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 451} 452 453SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 454 return DAG.getNode(ISD::SHL, N->getDebugLoc(), 455 TLI.getTypeToTransformTo(N->getValueType(0)), 456 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 457} 458 459SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 460 SDValue Op = GetPromotedInteger(N->getOperand(0)); 461 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), 462 Op.getValueType(), Op, N->getOperand(1)); 463} 464 465SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 466 // The input may have strange things in the top bits of the registers, but 467 // these operations don't care. They may have weird bits going out, but 468 // that too is okay if they are integer operations. 469 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 470 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 471 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 472 LHS.getValueType(), LHS, RHS); 473} 474 475SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 476 // The input value must be properly sign extended. 477 SDValue Res = SExtPromotedInteger(N->getOperand(0)); 478 return DAG.getNode(ISD::SRA, N->getDebugLoc(), 479 Res.getValueType(), Res, N->getOperand(1)); 480} 481 482SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 483 // The input value must be properly zero extended. 484 MVT VT = N->getValueType(0); 485 MVT NVT = TLI.getTypeToTransformTo(VT); 486 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 487 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); 488} 489 490SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 491 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 492 SDValue Res; 493 494 switch (getTypeAction(N->getOperand(0).getValueType())) { 495 default: llvm_unreachable("Unknown type action!"); 496 case Legal: 497 case ExpandInteger: 498 Res = N->getOperand(0); 499 break; 500 case PromoteInteger: 501 Res = GetPromotedInteger(N->getOperand(0)); 502 break; 503 } 504 505 // Truncate to NVT instead of VT 506 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res); 507} 508 509SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { 510 if (ResNo == 1) 511 return PromoteIntRes_Overflow(N); 512 513 // The operation overflowed iff the result in the larger type is not the 514 // zero extension of its truncation to the original type. 515 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 516 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 517 MVT OVT = N->getOperand(0).getValueType(); 518 MVT NVT = LHS.getValueType(); 519 DebugLoc dl = N->getDebugLoc(); 520 521 // Do the arithmetic in the larger type. 522 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 523 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 524 525 // Calculate the overflow flag: zero extend the arithmetic result from 526 // the original type. 527 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); 528 // Overflowed if and only if this is not equal to Res. 529 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 530 531 // Use the calculated overflow everywhere. 532 ReplaceValueWith(SDValue(N, 1), Ofl); 533 534 return Res; 535} 536 537SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 538 // Zero extend the input. 539 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 540 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 541 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 542 LHS.getValueType(), LHS, RHS); 543} 544 545SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 546 return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0))); 547} 548 549SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 550 SDValue Chain = N->getOperand(0); // Get the chain. 551 SDValue Ptr = N->getOperand(1); // Get the pointer. 552 MVT VT = N->getValueType(0); 553 DebugLoc dl = N->getDebugLoc(); 554 555 MVT RegVT = TLI.getRegisterType(VT); 556 unsigned NumRegs = TLI.getNumRegisters(VT); 557 // The argument is passed as NumRegs registers of type RegVT. 558 559 SmallVector<SDValue, 8> Parts(NumRegs); 560 for (unsigned i = 0; i < NumRegs; ++i) { 561 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2)); 562 Chain = Parts[i].getValue(1); 563 } 564 565 // Handle endianness of the load. 566 if (TLI.isBigEndian()) 567 std::reverse(Parts.begin(), Parts.end()); 568 569 // Assemble the parts in the promoted type. 570 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 571 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); 572 for (unsigned i = 1; i < NumRegs; ++i) { 573 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); 574 // Shift it to the right position and "or" it in. 575 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, 576 DAG.getConstant(i * RegVT.getSizeInBits(), 577 TLI.getPointerTy())); 578 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); 579 } 580 581 // Modified the chain result - switch anything that used the old chain to 582 // use the new one. 583 ReplaceValueWith(SDValue(N, 1), Chain); 584 585 return Res; 586} 587 588SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) { 589 assert(ResNo == 1 && "Only boolean result promotion currently supported!"); 590 return PromoteIntRes_Overflow(N); 591} 592 593//===----------------------------------------------------------------------===// 594// Integer Operand Promotion 595//===----------------------------------------------------------------------===// 596 597/// PromoteIntegerOperand - This method is called when the specified operand of 598/// the specified node is found to need promotion. At this point, all of the 599/// result types of the node are known to be legal, but other operands of the 600/// node may need promotion or expansion as well as the specified one. 601bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 602 DEBUG(errs() << "Promote integer operand: "; N->dump(&DAG); errs() << "\n"); 603 SDValue Res = SDValue(); 604 605 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 606 return false; 607 608 switch (N->getOpcode()) { 609 default: 610 #ifndef NDEBUG 611 errs() << "PromoteIntegerOperand Op #" << OpNo << ": "; 612 N->dump(&DAG); errs() << "\n"; 613 #endif 614 llvm_unreachable("Do not know how to promote this operator's operand!"); 615 616 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 617 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break; 618 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 619 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 620 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 621 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 622 case ISD::CONVERT_RNDSAT: 623 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 624 case ISD::INSERT_VECTOR_ELT: 625 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 626 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 627 case ISD::SCALAR_TO_VECTOR: 628 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break; 629 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 630 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 631 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 632 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 633 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 634 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 635 OpNo); break; 636 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 637 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; 638 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 639 640 case ISD::SHL: 641 case ISD::SRA: 642 case ISD::SRL: 643 case ISD::ROTL: 644 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; 645 } 646 647 // If the result is null, the sub-method took care of registering results etc. 648 if (!Res.getNode()) return false; 649 650 // If the result is N, the sub-method updated N in place. Tell the legalizer 651 // core about this. 652 if (Res.getNode() == N) 653 return true; 654 655 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 656 "Invalid operand expansion"); 657 658 ReplaceValueWith(SDValue(N, 0), Res); 659 return false; 660} 661 662/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 663/// shared among BR_CC, SELECT_CC, and SETCC handlers. 664void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 665 ISD::CondCode CCCode) { 666 // We have to insert explicit sign or zero extends. Note that we could 667 // insert sign extends for ALL conditions, but zero extend is cheaper on 668 // many machines (an AND instead of two shifts), so prefer it. 669 switch (CCCode) { 670 default: llvm_unreachable("Unknown integer comparison!"); 671 case ISD::SETEQ: 672 case ISD::SETNE: 673 case ISD::SETUGE: 674 case ISD::SETUGT: 675 case ISD::SETULE: 676 case ISD::SETULT: 677 // ALL of these operations will work if we either sign or zero extend 678 // the operands (including the unsigned comparisons!). Zero extend is 679 // usually a simpler/cheaper operation, so prefer it. 680 NewLHS = ZExtPromotedInteger(NewLHS); 681 NewRHS = ZExtPromotedInteger(NewRHS); 682 break; 683 case ISD::SETGE: 684 case ISD::SETGT: 685 case ISD::SETLT: 686 case ISD::SETLE: 687 NewLHS = SExtPromotedInteger(NewLHS); 688 NewRHS = SExtPromotedInteger(NewRHS); 689 break; 690 } 691} 692 693SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 694 SDValue Op = GetPromotedInteger(N->getOperand(0)); 695 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); 696} 697 698SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) { 699 // This should only occur in unusual situations like bitcasting to an 700 // x86_fp80, so just turn it into a store+load 701 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0)); 702} 703 704SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 705 assert(OpNo == 2 && "Don't know how to promote this operand!"); 706 707 SDValue LHS = N->getOperand(2); 708 SDValue RHS = N->getOperand(3); 709 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 710 711 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 712 // legal types. 713 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 714 N->getOperand(1), LHS, RHS, N->getOperand(4)); 715} 716 717SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 718 assert(OpNo == 1 && "only know how to promote condition"); 719 720 // Promote all the way up to the canonical SetCC type. 721 MVT SVT = TLI.getSetCCResultType(MVT::Other); 722 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT); 723 724 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 725 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, 726 N->getOperand(2)); 727} 728 729SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 730 // Since the result type is legal, the operands must promote to it. 731 MVT OVT = N->getOperand(0).getValueType(); 732 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); 733 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 734 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 735 DebugLoc dl = N->getDebugLoc(); 736 737 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, 738 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy())); 739 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); 740} 741 742SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 743 // The vector type is legal but the element type is not. This implies 744 // that the vector is a power-of-two in length and that the element 745 // type does not have a strange size (eg: it is not i1). 746 MVT VecVT = N->getValueType(0); 747 unsigned NumElts = VecVT.getVectorNumElements(); 748 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 749 750 // Promote the inserted value. The type does not need to match the 751 // vector element type. Check that any extra bits introduced will be 752 // truncated away. 753 assert(N->getOperand(0).getValueType().getSizeInBits() >= 754 N->getValueType(0).getVectorElementType().getSizeInBits() && 755 "Type of inserted value narrower than vector element type!"); 756 757 SmallVector<SDValue, 16> NewOps; 758 for (unsigned i = 0; i < NumElts; ++i) 759 NewOps.push_back(GetPromotedInteger(N->getOperand(i))); 760 761 return DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NumElts); 762} 763 764SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 765 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 766 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 767 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 768 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 769 "can only promote integer arguments"); 770 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 771 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp, 772 N->getOperand(1), N->getOperand(2), 773 N->getOperand(3), N->getOperand(4), CvtCode); 774} 775 776SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 777 unsigned OpNo) { 778 if (OpNo == 1) { 779 // Promote the inserted value. This is valid because the type does not 780 // have to match the vector element type. 781 782 // Check that any extra bits introduced will be truncated away. 783 assert(N->getOperand(1).getValueType().getSizeInBits() >= 784 N->getValueType(0).getVectorElementType().getSizeInBits() && 785 "Type of inserted value narrower than vector element type!"); 786 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 787 GetPromotedInteger(N->getOperand(1)), 788 N->getOperand(2)); 789 } 790 791 assert(OpNo == 2 && "Different operand and result vector types?"); 792 793 // Promote the index. 794 SDValue Idx = ZExtPromotedInteger(N->getOperand(2)); 795 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 796 N->getOperand(1), Idx); 797} 798 799SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 800 SDValue NewOps[6]; 801 DebugLoc dl = N->getDebugLoc(); 802 NewOps[0] = N->getOperand(0); 803 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 804 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 805 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1); 806 } 807 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, 808 array_lengthof(NewOps)); 809} 810 811SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) { 812 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote 813 // the operand in place. 814 return DAG.UpdateNodeOperands(SDValue(N, 0), 815 GetPromotedInteger(N->getOperand(0))); 816} 817 818SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 819 assert(OpNo == 0 && "Only know how to promote condition"); 820 821 // Promote all the way up to the canonical SetCC type. 822 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType()); 823 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT); 824 825 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, 826 N->getOperand(1), N->getOperand(2)); 827} 828 829SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 830 assert(OpNo == 0 && "Don't know how to promote this operand!"); 831 832 SDValue LHS = N->getOperand(0); 833 SDValue RHS = N->getOperand(1); 834 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 835 836 // The CC (#4) and the possible return values (#2 and #3) have legal types. 837 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2), 838 N->getOperand(3), N->getOperand(4)); 839} 840 841SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 842 assert(OpNo == 0 && "Don't know how to promote this operand!"); 843 844 SDValue LHS = N->getOperand(0); 845 SDValue RHS = N->getOperand(1); 846 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 847 848 // The CC (#2) is always legal. 849 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); 850} 851 852SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) { 853 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 854 ZExtPromotedInteger(N->getOperand(1))); 855} 856 857SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 858 SDValue Op = GetPromotedInteger(N->getOperand(0)); 859 DebugLoc dl = N->getDebugLoc(); 860 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 861 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), 862 Op, DAG.getValueType(N->getOperand(0).getValueType())); 863} 864 865SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { 866 return DAG.UpdateNodeOperands(SDValue(N, 0), 867 SExtPromotedInteger(N->getOperand(0))); 868} 869 870SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 871 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 872 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 873 int SVOffset = N->getSrcValueOffset(); 874 unsigned Alignment = N->getAlignment(); 875 bool isVolatile = N->isVolatile(); 876 DebugLoc dl = N->getDebugLoc(); 877 878 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 879 880 // Truncate the value and store the result. 881 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(), 882 SVOffset, N->getMemoryVT(), 883 isVolatile, Alignment); 884} 885 886SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 887 SDValue Op = GetPromotedInteger(N->getOperand(0)); 888 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op); 889} 890 891SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { 892 return DAG.UpdateNodeOperands(SDValue(N, 0), 893 ZExtPromotedInteger(N->getOperand(0))); 894} 895 896SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 897 DebugLoc dl = N->getDebugLoc(); 898 SDValue Op = GetPromotedInteger(N->getOperand(0)); 899 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 900 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType()); 901} 902 903 904//===----------------------------------------------------------------------===// 905// Integer Result Expansion 906//===----------------------------------------------------------------------===// 907 908/// ExpandIntegerResult - This method is called when the specified result of the 909/// specified node is found to need expansion. At this point, the node may also 910/// have invalid operands or may have other results that need promotion, we just 911/// know that (at least) one result needs expansion. 912void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 913 DEBUG(errs() << "Expand integer result: "; N->dump(&DAG); errs() << "\n"); 914 SDValue Lo, Hi; 915 Lo = Hi = SDValue(); 916 917 // See if the target wants to custom expand this node. 918 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 919 return; 920 921 switch (N->getOpcode()) { 922 default: 923#ifndef NDEBUG 924 errs() << "ExpandIntegerResult #" << ResNo << ": "; 925 N->dump(&DAG); errs() << "\n"; 926#endif 927 llvm_unreachable("Do not know how to expand the result of this operator!"); 928 929 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 930 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 931 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 932 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 933 934 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 935 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 936 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 937 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 938 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 939 940 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 941 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 942 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 943 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 944 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 945 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 946 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 947 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 948 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 949 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 950 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 951 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 952 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 953 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 954 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 955 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 956 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 957 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 958 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 959 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 960 961 case ISD::AND: 962 case ISD::OR: 963 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 964 965 case ISD::ADD: 966 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 967 968 case ISD::ADDC: 969 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 970 971 case ISD::ADDE: 972 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 973 974 case ISD::SHL: 975 case ISD::SRA: 976 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 977 } 978 979 // If Lo/Hi is null, the sub-method took care of registering results etc. 980 if (Lo.getNode()) 981 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 982} 983 984/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 985/// and the shift amount is a constant 'Amt'. Expand the operation. 986void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 987 SDValue &Lo, SDValue &Hi) { 988 DebugLoc dl = N->getDebugLoc(); 989 // Expand the incoming operand to be shifted, so that we have its parts 990 SDValue InL, InH; 991 GetExpandedInteger(N->getOperand(0), InL, InH); 992 993 MVT NVT = InL.getValueType(); 994 unsigned VTBits = N->getValueType(0).getSizeInBits(); 995 unsigned NVTBits = NVT.getSizeInBits(); 996 MVT ShTy = N->getOperand(1).getValueType(); 997 998 if (N->getOpcode() == ISD::SHL) { 999 if (Amt > VTBits) { 1000 Lo = Hi = DAG.getConstant(0, NVT); 1001 } else if (Amt > NVTBits) { 1002 Lo = DAG.getConstant(0, NVT); 1003 Hi = DAG.getNode(ISD::SHL, dl, 1004 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1005 } else if (Amt == NVTBits) { 1006 Lo = DAG.getConstant(0, NVT); 1007 Hi = InL; 1008 } else if (Amt == 1 && 1009 TLI.isOperationLegalOrCustom(ISD::ADDC, 1010 TLI.getTypeToExpandTo(NVT))) { 1011 // Emit this X << 1 as X+X. 1012 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1013 SDValue LoOps[2] = { InL, InL }; 1014 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1015 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1016 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1017 } else { 1018 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy)); 1019 Hi = DAG.getNode(ISD::OR, dl, NVT, 1020 DAG.getNode(ISD::SHL, dl, NVT, InH, 1021 DAG.getConstant(Amt, ShTy)), 1022 DAG.getNode(ISD::SRL, dl, NVT, InL, 1023 DAG.getConstant(NVTBits-Amt, ShTy))); 1024 } 1025 return; 1026 } 1027 1028 if (N->getOpcode() == ISD::SRL) { 1029 if (Amt > VTBits) { 1030 Lo = DAG.getConstant(0, NVT); 1031 Hi = DAG.getConstant(0, NVT); 1032 } else if (Amt > NVTBits) { 1033 Lo = DAG.getNode(ISD::SRL, dl, 1034 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1035 Hi = DAG.getConstant(0, NVT); 1036 } else if (Amt == NVTBits) { 1037 Lo = InH; 1038 Hi = DAG.getConstant(0, NVT); 1039 } else { 1040 Lo = DAG.getNode(ISD::OR, dl, NVT, 1041 DAG.getNode(ISD::SRL, dl, NVT, InL, 1042 DAG.getConstant(Amt, ShTy)), 1043 DAG.getNode(ISD::SHL, dl, NVT, InH, 1044 DAG.getConstant(NVTBits-Amt, ShTy))); 1045 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); 1046 } 1047 return; 1048 } 1049 1050 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1051 if (Amt > VTBits) { 1052 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 1053 DAG.getConstant(NVTBits-1, ShTy)); 1054 } else if (Amt > NVTBits) { 1055 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 1056 DAG.getConstant(Amt-NVTBits, ShTy)); 1057 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 1058 DAG.getConstant(NVTBits-1, ShTy)); 1059 } else if (Amt == NVTBits) { 1060 Lo = InH; 1061 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 1062 DAG.getConstant(NVTBits-1, ShTy)); 1063 } else { 1064 Lo = DAG.getNode(ISD::OR, dl, NVT, 1065 DAG.getNode(ISD::SRL, dl, NVT, InL, 1066 DAG.getConstant(Amt, ShTy)), 1067 DAG.getNode(ISD::SHL, dl, NVT, InH, 1068 DAG.getConstant(NVTBits-Amt, ShTy))); 1069 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); 1070 } 1071} 1072 1073/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1074/// this shift based on knowledge of the high bit of the shift amount. If we 1075/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1076/// shift amount. 1077bool DAGTypeLegalizer:: 1078ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1079 SDValue Amt = N->getOperand(1); 1080 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1081 MVT ShTy = Amt.getValueType(); 1082 unsigned ShBits = ShTy.getSizeInBits(); 1083 unsigned NVTBits = NVT.getSizeInBits(); 1084 assert(isPowerOf2_32(NVTBits) && 1085 "Expanded integer type size not a power of two!"); 1086 DebugLoc dl = N->getDebugLoc(); 1087 1088 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1089 APInt KnownZero, KnownOne; 1090 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1091 1092 // If we don't know anything about the high bits, exit. 1093 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1094 return false; 1095 1096 // Get the incoming operand to be shifted. 1097 SDValue InL, InH; 1098 GetExpandedInteger(N->getOperand(0), InL, InH); 1099 1100 // If we know that any of the high bits of the shift amount are one, then we 1101 // can do this as a couple of simple shifts. 1102 if (KnownOne.intersects(HighBitMask)) { 1103 // Mask out the high bit, which we know is set. 1104 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, 1105 DAG.getConstant(~HighBitMask, ShTy)); 1106 1107 switch (N->getOpcode()) { 1108 default: llvm_unreachable("Unknown shift"); 1109 case ISD::SHL: 1110 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1111 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 1112 return true; 1113 case ISD::SRL: 1114 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1115 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 1116 return true; 1117 case ISD::SRA: 1118 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 1119 DAG.getConstant(NVTBits-1, ShTy)); 1120 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 1121 return true; 1122 } 1123 } 1124 1125#if 0 1126 // FIXME: This code is broken for shifts with a zero amount! 1127 // If we know that all of the high bits of the shift amount are zero, then we 1128 // can do this as a couple of simple shifts. 1129 if ((KnownZero & HighBitMask) == HighBitMask) { 1130 // Compute 32-amt. 1131 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1132 DAG.getConstant(NVTBits, ShTy), 1133 Amt); 1134 unsigned Op1, Op2; 1135 switch (N->getOpcode()) { 1136 default: llvm_unreachable("Unknown shift"); 1137 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1138 case ISD::SRL: 1139 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1140 } 1141 1142 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1143 Hi = DAG.getNode(ISD::OR, NVT, 1144 DAG.getNode(Op1, NVT, InH, Amt), 1145 DAG.getNode(Op2, NVT, InL, Amt2)); 1146 return true; 1147 } 1148#endif 1149 1150 return false; 1151} 1152 1153/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift 1154/// of any size. 1155bool DAGTypeLegalizer:: 1156ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1157 SDValue Amt = N->getOperand(1); 1158 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1159 MVT ShTy = Amt.getValueType(); 1160 unsigned NVTBits = NVT.getSizeInBits(); 1161 assert(isPowerOf2_32(NVTBits) && 1162 "Expanded integer type size not a power of two!"); 1163 DebugLoc dl = N->getDebugLoc(); 1164 1165 // Get the incoming operand to be shifted. 1166 SDValue InL, InH; 1167 GetExpandedInteger(N->getOperand(0), InL, InH); 1168 1169 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy); 1170 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt); 1171 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy), 1172 Amt, NVBitsNode, ISD::SETULT); 1173 1174 SDValue Lo1, Hi1, Lo2, Hi2; 1175 switch (N->getOpcode()) { 1176 default: llvm_unreachable("Unknown shift"); 1177 case ISD::SHL: 1178 // ShAmt < NVTBits 1179 Lo1 = DAG.getConstant(0, NVT); // Low part is zero. 1180 Hi1 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 1181 1182 // ShAmt >= NVTBits 1183 Lo2 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); 1184 Hi2 = DAG.getNode(ISD::OR, dl, NVT, 1185 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt), 1186 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2)); 1187 1188 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2); 1189 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2); 1190 return true; 1191 case ISD::SRL: 1192 // ShAmt < NVTBits 1193 Hi1 = DAG.getConstant(0, NVT); // Hi part is zero. 1194 Lo1 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 1195 1196 // ShAmt >= NVTBits 1197 Hi2 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); 1198 Lo2 = DAG.getNode(ISD::OR, dl, NVT, 1199 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1200 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2)); 1201 1202 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2); 1203 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2); 1204 return true; 1205 case ISD::SRA: 1206 // ShAmt < NVTBits 1207 Hi1 = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 1208 DAG.getConstant(NVTBits-1, ShTy)); 1209 Lo1 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 1210 1211 // ShAmt >= NVTBits 1212 Hi2 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); 1213 Lo2 = DAG.getNode(ISD::OR, dl, NVT, 1214 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1215 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2)); 1216 1217 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2); 1218 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2); 1219 return true; 1220 } 1221 1222 return false; 1223} 1224 1225void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1226 SDValue &Lo, SDValue &Hi) { 1227 DebugLoc dl = N->getDebugLoc(); 1228 // Expand the subcomponents. 1229 SDValue LHSL, LHSH, RHSL, RHSH; 1230 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1231 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1232 1233 MVT NVT = LHSL.getValueType(); 1234 SDValue LoOps[2] = { LHSL, RHSL }; 1235 SDValue HiOps[3] = { LHSH, RHSH }; 1236 1237 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1238 // them. TODO: Teach operation legalization how to expand unsupported 1239 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1240 // a carry of type MVT::Flag, but there doesn't seem to be any way to 1241 // generate a value of this type in the expanded code sequence. 1242 bool hasCarry = 1243 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? 1244 ISD::ADDC : ISD::SUBC, 1245 TLI.getTypeToExpandTo(NVT)); 1246 1247 if (hasCarry) { 1248 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1249 if (N->getOpcode() == ISD::ADD) { 1250 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1251 HiOps[2] = Lo.getValue(1); 1252 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1253 } else { 1254 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1255 HiOps[2] = Lo.getValue(1); 1256 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1257 } 1258 } else { 1259 if (N->getOpcode() == ISD::ADD) { 1260 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); 1261 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); 1262 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0], 1263 ISD::SETULT); 1264 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, 1265 DAG.getConstant(1, NVT), 1266 DAG.getConstant(0, NVT)); 1267 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1], 1268 ISD::SETULT); 1269 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, 1270 DAG.getConstant(1, NVT), Carry1); 1271 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); 1272 } else { 1273 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 1274 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); 1275 SDValue Cmp = 1276 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()), 1277 LoOps[0], LoOps[1], ISD::SETULT); 1278 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, 1279 DAG.getConstant(1, NVT), 1280 DAG.getConstant(0, NVT)); 1281 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); 1282 } 1283 } 1284} 1285 1286void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1287 SDValue &Lo, SDValue &Hi) { 1288 // Expand the subcomponents. 1289 SDValue LHSL, LHSH, RHSL, RHSH; 1290 DebugLoc dl = N->getDebugLoc(); 1291 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1292 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1293 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1294 SDValue LoOps[2] = { LHSL, RHSL }; 1295 SDValue HiOps[3] = { LHSH, RHSH }; 1296 1297 if (N->getOpcode() == ISD::ADDC) { 1298 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1299 HiOps[2] = Lo.getValue(1); 1300 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1301 } else { 1302 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1303 HiOps[2] = Lo.getValue(1); 1304 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1305 } 1306 1307 // Legalized the flag result - switch anything that used the old flag to 1308 // use the new one. 1309 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1310} 1311 1312void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1313 SDValue &Lo, SDValue &Hi) { 1314 // Expand the subcomponents. 1315 SDValue LHSL, LHSH, RHSL, RHSH; 1316 DebugLoc dl = N->getDebugLoc(); 1317 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1318 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1319 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1320 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1321 SDValue HiOps[3] = { LHSH, RHSH }; 1322 1323 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3); 1324 HiOps[2] = Lo.getValue(1); 1325 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); 1326 1327 // Legalized the flag result - switch anything that used the old flag to 1328 // use the new one. 1329 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1330} 1331 1332void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1333 SDValue &Lo, SDValue &Hi) { 1334 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1335 DebugLoc dl = N->getDebugLoc(); 1336 SDValue Op = N->getOperand(0); 1337 if (Op.getValueType().bitsLE(NVT)) { 1338 // The low part is any extension of the input (which degenerates to a copy). 1339 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); 1340 Hi = DAG.getUNDEF(NVT); // The high part is undefined. 1341 } else { 1342 // For example, extension of an i48 to an i64. The operand type necessarily 1343 // promotes to the result type, so will end up being expanded too. 1344 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1345 "Only know how to promote this result!"); 1346 SDValue Res = GetPromotedInteger(Op); 1347 assert(Res.getValueType() == N->getValueType(0) && 1348 "Operand over promoted?"); 1349 // Split the promoted operand. This will simplify when it is expanded. 1350 SplitInteger(Res, Lo, Hi); 1351 } 1352} 1353 1354void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1355 SDValue &Lo, SDValue &Hi) { 1356 DebugLoc dl = N->getDebugLoc(); 1357 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1358 MVT NVT = Lo.getValueType(); 1359 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1360 unsigned NVTBits = NVT.getSizeInBits(); 1361 unsigned EVTBits = EVT.getSizeInBits(); 1362 1363 if (NVTBits < EVTBits) { 1364 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, 1365 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1366 } else { 1367 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); 1368 // The high part replicates the sign bit of Lo, make it explicit. 1369 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1370 DAG.getConstant(NVTBits-1, TLI.getPointerTy())); 1371 } 1372} 1373 1374void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1375 SDValue &Lo, SDValue &Hi) { 1376 DebugLoc dl = N->getDebugLoc(); 1377 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1378 MVT NVT = Lo.getValueType(); 1379 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1380 unsigned NVTBits = NVT.getSizeInBits(); 1381 unsigned EVTBits = EVT.getSizeInBits(); 1382 1383 if (NVTBits < EVTBits) { 1384 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, 1385 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1386 } else { 1387 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); 1388 // The high part must be zero, make it explicit. 1389 Hi = DAG.getConstant(0, NVT); 1390 } 1391} 1392 1393void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1394 SDValue &Lo, SDValue &Hi) { 1395 DebugLoc dl = N->getDebugLoc(); 1396 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1397 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo); 1398 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi); 1399} 1400 1401void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1402 SDValue &Lo, SDValue &Hi) { 1403 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1404 unsigned NBitWidth = NVT.getSizeInBits(); 1405 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1406 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 1407 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1408} 1409 1410void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1411 SDValue &Lo, SDValue &Hi) { 1412 DebugLoc dl = N->getDebugLoc(); 1413 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1414 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1415 MVT NVT = Lo.getValueType(); 1416 1417 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi, 1418 DAG.getConstant(0, NVT), ISD::SETNE); 1419 1420 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo); 1421 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi); 1422 1423 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ, 1424 DAG.getNode(ISD::ADD, dl, NVT, LoLZ, 1425 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1426 Hi = DAG.getConstant(0, NVT); 1427} 1428 1429void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1430 SDValue &Lo, SDValue &Hi) { 1431 DebugLoc dl = N->getDebugLoc(); 1432 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1433 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1434 MVT NVT = Lo.getValueType(); 1435 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), 1436 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); 1437 Hi = DAG.getConstant(0, NVT); 1438} 1439 1440void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1441 SDValue &Lo, SDValue &Hi) { 1442 DebugLoc dl = N->getDebugLoc(); 1443 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1444 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1445 MVT NVT = Lo.getValueType(); 1446 1447 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, 1448 DAG.getConstant(0, NVT), ISD::SETNE); 1449 1450 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); 1451 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); 1452 1453 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ, 1454 DAG.getNode(ISD::ADD, dl, NVT, HiLZ, 1455 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1456 Hi = DAG.getConstant(0, NVT); 1457} 1458 1459void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1460 SDValue &Hi) { 1461 DebugLoc dl = N->getDebugLoc(); 1462 MVT VT = N->getValueType(0); 1463 SDValue Op = N->getOperand(0); 1464 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1465 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1466 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi); 1467} 1468 1469void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1470 SDValue &Hi) { 1471 DebugLoc dl = N->getDebugLoc(); 1472 MVT VT = N->getValueType(0); 1473 SDValue Op = N->getOperand(0); 1474 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1475 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1476 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi); 1477} 1478 1479void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1480 SDValue &Lo, SDValue &Hi) { 1481 if (ISD::isNormalLoad(N)) { 1482 ExpandRes_NormalLoad(N, Lo, Hi); 1483 return; 1484 } 1485 1486 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1487 1488 MVT VT = N->getValueType(0); 1489 MVT NVT = TLI.getTypeToTransformTo(VT); 1490 SDValue Ch = N->getChain(); 1491 SDValue Ptr = N->getBasePtr(); 1492 ISD::LoadExtType ExtType = N->getExtensionType(); 1493 int SVOffset = N->getSrcValueOffset(); 1494 unsigned Alignment = N->getAlignment(); 1495 bool isVolatile = N->isVolatile(); 1496 DebugLoc dl = N->getDebugLoc(); 1497 1498 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1499 1500 if (N->getMemoryVT().bitsLE(NVT)) { 1501 MVT EVT = N->getMemoryVT(); 1502 1503 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1504 EVT, isVolatile, Alignment); 1505 1506 // Remember the chain. 1507 Ch = Lo.getValue(1); 1508 1509 if (ExtType == ISD::SEXTLOAD) { 1510 // The high part is obtained by SRA'ing all but one of the bits of the 1511 // lo part. 1512 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1513 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1514 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1515 } else if (ExtType == ISD::ZEXTLOAD) { 1516 // The high part is just a zero. 1517 Hi = DAG.getConstant(0, NVT); 1518 } else { 1519 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1520 // The high part is undefined. 1521 Hi = DAG.getUNDEF(NVT); 1522 } 1523 } else if (TLI.isLittleEndian()) { 1524 // Little-endian - low bits are at low addresses. 1525 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset, 1526 isVolatile, Alignment); 1527 1528 unsigned ExcessBits = 1529 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1530 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1531 1532 // Increment the pointer to the other half. 1533 unsigned IncrementSize = NVT.getSizeInBits()/8; 1534 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1535 DAG.getIntPtrConstant(IncrementSize)); 1536 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), 1537 SVOffset+IncrementSize, NEVT, 1538 isVolatile, MinAlign(Alignment, IncrementSize)); 1539 1540 // Build a factor node to remember that this load is independent of the 1541 // other one. 1542 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1543 Hi.getValue(1)); 1544 } else { 1545 // Big-endian - high bits are at low addresses. Favor aligned loads at 1546 // the cost of some bit-fiddling. 1547 MVT EVT = N->getMemoryVT(); 1548 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1549 unsigned IncrementSize = NVT.getSizeInBits()/8; 1550 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1551 1552 // Load both the high bits and maybe some of the low bits. 1553 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1554 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1555 isVolatile, Alignment); 1556 1557 // Increment the pointer to the other half. 1558 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1559 DAG.getIntPtrConstant(IncrementSize)); 1560 // Load the rest of the low bits. 1561 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(), 1562 SVOffset+IncrementSize, 1563 MVT::getIntegerVT(ExcessBits), 1564 isVolatile, MinAlign(Alignment, IncrementSize)); 1565 1566 // Build a factor node to remember that this load is independent of the 1567 // other one. 1568 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1569 Hi.getValue(1)); 1570 1571 if (ExcessBits < NVT.getSizeInBits()) { 1572 // Transfer low bits from the bottom of Hi to the top of Lo. 1573 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, 1574 DAG.getNode(ISD::SHL, dl, NVT, Hi, 1575 DAG.getConstant(ExcessBits, 1576 TLI.getPointerTy()))); 1577 // Move high bits to the right position in Hi. 1578 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, 1579 NVT, Hi, 1580 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1581 TLI.getPointerTy())); 1582 } 1583 } 1584 1585 // Legalized the chain result - switch anything that used the old chain to 1586 // use the new one. 1587 ReplaceValueWith(SDValue(N, 1), Ch); 1588} 1589 1590void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1591 SDValue &Lo, SDValue &Hi) { 1592 DebugLoc dl = N->getDebugLoc(); 1593 SDValue LL, LH, RL, RH; 1594 GetExpandedInteger(N->getOperand(0), LL, LH); 1595 GetExpandedInteger(N->getOperand(1), RL, RH); 1596 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); 1597 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); 1598} 1599 1600void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1601 SDValue &Lo, SDValue &Hi) { 1602 MVT VT = N->getValueType(0); 1603 MVT NVT = TLI.getTypeToTransformTo(VT); 1604 DebugLoc dl = N->getDebugLoc(); 1605 1606 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 1607 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 1608 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 1609 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 1610 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1611 SDValue LL, LH, RL, RH; 1612 GetExpandedInteger(N->getOperand(0), LL, LH); 1613 GetExpandedInteger(N->getOperand(1), RL, RH); 1614 unsigned OuterBitSize = VT.getSizeInBits(); 1615 unsigned InnerBitSize = NVT.getSizeInBits(); 1616 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1617 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1618 1619 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1620 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1621 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1622 // The inputs are both zero-extended. 1623 if (HasUMUL_LOHI) { 1624 // We can emit a umul_lohi. 1625 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1626 Hi = SDValue(Lo.getNode(), 1); 1627 return; 1628 } 1629 if (HasMULHU) { 1630 // We can emit a mulhu+mul. 1631 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1632 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1633 return; 1634 } 1635 } 1636 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1637 // The input values are both sign-extended. 1638 if (HasSMUL_LOHI) { 1639 // We can emit a smul_lohi. 1640 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1641 Hi = SDValue(Lo.getNode(), 1); 1642 return; 1643 } 1644 if (HasMULHS) { 1645 // We can emit a mulhs+mul. 1646 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1647 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); 1648 return; 1649 } 1650 } 1651 if (HasUMUL_LOHI) { 1652 // Lo,Hi = umul LHS, RHS. 1653 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 1654 DAG.getVTList(NVT, NVT), LL, RL); 1655 Lo = UMulLOHI; 1656 Hi = UMulLOHI.getValue(1); 1657 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1658 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1659 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1660 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1661 return; 1662 } 1663 if (HasMULHU) { 1664 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1665 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1666 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1667 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1668 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1669 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1670 return; 1671 } 1672 } 1673 1674 // If nothing else, we can make a libcall. 1675 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1676 if (VT == MVT::i16) 1677 LC = RTLIB::MUL_I16; 1678 else if (VT == MVT::i32) 1679 LC = RTLIB::MUL_I32; 1680 else if (VT == MVT::i64) 1681 LC = RTLIB::MUL_I64; 1682 else if (VT == MVT::i128) 1683 LC = RTLIB::MUL_I128; 1684 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1685 1686 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1687 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi); 1688} 1689 1690void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1691 SDValue &Lo, SDValue &Hi) { 1692 MVT VT = N->getValueType(0); 1693 DebugLoc dl = N->getDebugLoc(); 1694 1695 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1696 if (VT == MVT::i16) 1697 LC = RTLIB::SDIV_I16; 1698 else if (VT == MVT::i32) 1699 LC = RTLIB::SDIV_I32; 1700 else if (VT == MVT::i64) 1701 LC = RTLIB::SDIV_I64; 1702 else if (VT == MVT::i128) 1703 LC = RTLIB::SDIV_I128; 1704 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1705 1706 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1707 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1708} 1709 1710void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1711 SDValue &Lo, SDValue &Hi) { 1712 MVT VT = N->getValueType(0); 1713 DebugLoc dl = N->getDebugLoc(); 1714 1715 // If we can emit an efficient shift operation, do so now. Check to see if 1716 // the RHS is a constant. 1717 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1718 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1719 1720 // If we can determine that the high bit of the shift is zero or one, even if 1721 // the low bits are variable, emit this shift in an optimized form. 1722 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1723 return; 1724 1725 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1726 unsigned PartsOpc; 1727 if (N->getOpcode() == ISD::SHL) { 1728 PartsOpc = ISD::SHL_PARTS; 1729 } else if (N->getOpcode() == ISD::SRL) { 1730 PartsOpc = ISD::SRL_PARTS; 1731 } else { 1732 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1733 PartsOpc = ISD::SRA_PARTS; 1734 } 1735 1736 // Next check to see if the target supports this SHL_PARTS operation or if it 1737 // will custom expand it. 1738 MVT NVT = TLI.getTypeToTransformTo(VT); 1739 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1740 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1741 Action == TargetLowering::Custom) { 1742 // Expand the subcomponents. 1743 SDValue LHSL, LHSH; 1744 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1745 1746 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1747 MVT VT = LHSL.getValueType(); 1748 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3); 1749 Hi = Lo.getValue(1); 1750 return; 1751 } 1752 1753 // Otherwise, emit a libcall. 1754 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1755 bool isSigned; 1756 if (N->getOpcode() == ISD::SHL) { 1757 isSigned = false; /*sign irrelevant*/ 1758 if (VT == MVT::i16) 1759 LC = RTLIB::SHL_I16; 1760 else if (VT == MVT::i32) 1761 LC = RTLIB::SHL_I32; 1762 else if (VT == MVT::i64) 1763 LC = RTLIB::SHL_I64; 1764 else if (VT == MVT::i128) 1765 LC = RTLIB::SHL_I128; 1766 } else if (N->getOpcode() == ISD::SRL) { 1767 isSigned = false; 1768 if (VT == MVT::i16) 1769 LC = RTLIB::SRL_I16; 1770 else if (VT == MVT::i32) 1771 LC = RTLIB::SRL_I32; 1772 else if (VT == MVT::i64) 1773 LC = RTLIB::SRL_I64; 1774 else if (VT == MVT::i128) 1775 LC = RTLIB::SRL_I128; 1776 } else { 1777 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1778 isSigned = true; 1779 if (VT == MVT::i16) 1780 LC = RTLIB::SRA_I16; 1781 else if (VT == MVT::i32) 1782 LC = RTLIB::SRA_I32; 1783 else if (VT == MVT::i64) 1784 LC = RTLIB::SRA_I64; 1785 else if (VT == MVT::i128) 1786 LC = RTLIB::SRA_I128; 1787 } 1788 1789 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) { 1790 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1791 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi); 1792 return; 1793 } 1794 1795 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi)) 1796 llvm_unreachable("Unsupported shift!"); 1797} 1798 1799void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 1800 SDValue &Lo, SDValue &Hi) { 1801 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1802 DebugLoc dl = N->getDebugLoc(); 1803 SDValue Op = N->getOperand(0); 1804 if (Op.getValueType().bitsLE(NVT)) { 1805 // The low part is sign extension of the input (degenerates to a copy). 1806 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); 1807 // The high part is obtained by SRA'ing all but one of the bits of low part. 1808 unsigned LoSize = NVT.getSizeInBits(); 1809 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1810 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1811 } else { 1812 // For example, extension of an i48 to an i64. The operand type necessarily 1813 // promotes to the result type, so will end up being expanded too. 1814 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1815 "Only know how to promote this result!"); 1816 SDValue Res = GetPromotedInteger(Op); 1817 assert(Res.getValueType() == N->getValueType(0) && 1818 "Operand over promoted?"); 1819 // Split the promoted operand. This will simplify when it is expanded. 1820 SplitInteger(Res, Lo, Hi); 1821 unsigned ExcessBits = 1822 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1823 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 1824 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1825 } 1826} 1827 1828void DAGTypeLegalizer:: 1829ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 1830 DebugLoc dl = N->getDebugLoc(); 1831 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1832 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1833 1834 if (EVT.bitsLE(Lo.getValueType())) { 1835 // sext_inreg the low part if needed. 1836 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, 1837 N->getOperand(1)); 1838 1839 // The high part gets the sign extension from the lo-part. This handles 1840 // things like sextinreg V:i64 from i8. 1841 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, 1842 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 1843 TLI.getPointerTy())); 1844 } else { 1845 // For example, extension of an i48 to an i64. Leave the low part alone, 1846 // sext_inreg the high part. 1847 unsigned ExcessBits = 1848 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 1849 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 1850 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1851 } 1852} 1853 1854void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1855 SDValue &Lo, SDValue &Hi) { 1856 MVT VT = N->getValueType(0); 1857 DebugLoc dl = N->getDebugLoc(); 1858 1859 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1860 if (VT == MVT::i16) 1861 LC = RTLIB::SREM_I16; 1862 else if (VT == MVT::i32) 1863 LC = RTLIB::SREM_I32; 1864 else if (VT == MVT::i64) 1865 LC = RTLIB::SREM_I64; 1866 else if (VT == MVT::i128) 1867 LC = RTLIB::SREM_I128; 1868 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1869 1870 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1871 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1872} 1873 1874void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 1875 SDValue &Lo, SDValue &Hi) { 1876 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1877 DebugLoc dl = N->getDebugLoc(); 1878 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); 1879 Hi = DAG.getNode(ISD::SRL, dl, 1880 N->getOperand(0).getValueType(), N->getOperand(0), 1881 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy())); 1882 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); 1883} 1884 1885void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1886 SDValue &Lo, SDValue &Hi) { 1887 MVT VT = N->getValueType(0); 1888 DebugLoc dl = N->getDebugLoc(); 1889 1890 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1891 if (VT == MVT::i16) 1892 LC = RTLIB::UDIV_I16; 1893 else if (VT == MVT::i32) 1894 LC = RTLIB::UDIV_I32; 1895 else if (VT == MVT::i64) 1896 LC = RTLIB::UDIV_I64; 1897 else if (VT == MVT::i128) 1898 LC = RTLIB::UDIV_I128; 1899 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 1900 1901 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1902 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 1903} 1904 1905void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1906 SDValue &Lo, SDValue &Hi) { 1907 MVT VT = N->getValueType(0); 1908 DebugLoc dl = N->getDebugLoc(); 1909 1910 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1911 if (VT == MVT::i16) 1912 LC = RTLIB::UREM_I16; 1913 else if (VT == MVT::i32) 1914 LC = RTLIB::UREM_I32; 1915 else if (VT == MVT::i64) 1916 LC = RTLIB::UREM_I64; 1917 else if (VT == MVT::i128) 1918 LC = RTLIB::UREM_I128; 1919 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 1920 1921 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1922 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 1923} 1924 1925void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 1926 SDValue &Lo, SDValue &Hi) { 1927 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1928 DebugLoc dl = N->getDebugLoc(); 1929 SDValue Op = N->getOperand(0); 1930 if (Op.getValueType().bitsLE(NVT)) { 1931 // The low part is zero extension of the input (degenerates to a copy). 1932 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); 1933 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 1934 } else { 1935 // For example, extension of an i48 to an i64. The operand type necessarily 1936 // promotes to the result type, so will end up being expanded too. 1937 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1938 "Only know how to promote this result!"); 1939 SDValue Res = GetPromotedInteger(Op); 1940 assert(Res.getValueType() == N->getValueType(0) && 1941 "Operand over promoted?"); 1942 // Split the promoted operand. This will simplify when it is expanded. 1943 SplitInteger(Res, Lo, Hi); 1944 unsigned ExcessBits = 1945 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1946 Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits)); 1947 } 1948} 1949 1950 1951//===----------------------------------------------------------------------===// 1952// Integer Operand Expansion 1953//===----------------------------------------------------------------------===// 1954 1955/// ExpandIntegerOperand - This method is called when the specified operand of 1956/// the specified node is found to need expansion. At this point, all of the 1957/// result types of the node are known to be legal, but other operands of the 1958/// node may need promotion or expansion as well as the specified one. 1959bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1960 DEBUG(errs() << "Expand integer operand: "; N->dump(&DAG); errs() << "\n"); 1961 SDValue Res = SDValue(); 1962 1963 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 1964 return false; 1965 1966 switch (N->getOpcode()) { 1967 default: 1968 #ifndef NDEBUG 1969 errs() << "ExpandIntegerOperand Op #" << OpNo << ": "; 1970 N->dump(&DAG); errs() << "\n"; 1971 #endif 1972 llvm_unreachable("Do not know how to expand this operator's operand!"); 1973 1974 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1975 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1976 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1977 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1978 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 1979 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; 1980 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1981 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1982 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 1983 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break; 1984 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1985 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 1986 1987 case ISD::SHL: 1988 case ISD::SRA: 1989 case ISD::SRL: 1990 case ISD::ROTL: 1991 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break; 1992 } 1993 1994 // If the result is null, the sub-method took care of registering results etc. 1995 if (!Res.getNode()) return false; 1996 1997 // If the result is N, the sub-method updated N in place. Tell the legalizer 1998 // core about this. 1999 if (Res.getNode() == N) 2000 return true; 2001 2002 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2003 "Invalid operand expansion"); 2004 2005 ReplaceValueWith(SDValue(N, 0), Res); 2006 return false; 2007} 2008 2009/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 2010/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 2011void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 2012 SDValue &NewRHS, 2013 ISD::CondCode &CCCode, 2014 DebugLoc dl) { 2015 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 2016 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 2017 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 2018 2019 MVT VT = NewLHS.getValueType(); 2020 2021 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 2022 if (RHSLo == RHSHi) { 2023 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 2024 if (RHSCST->isAllOnesValue()) { 2025 // Equality comparison to -1. 2026 NewLHS = DAG.getNode(ISD::AND, dl, 2027 LHSLo.getValueType(), LHSLo, LHSHi); 2028 NewRHS = RHSLo; 2029 return; 2030 } 2031 } 2032 } 2033 2034 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 2035 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 2036 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS); 2037 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2038 return; 2039 } 2040 2041 // If this is a comparison of the sign bit, just look at the top part. 2042 // X > -1, x < 0 2043 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 2044 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 2045 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 2046 NewLHS = LHSHi; 2047 NewRHS = RHSHi; 2048 return; 2049 } 2050 2051 // FIXME: This generated code sucks. 2052 ISD::CondCode LowCC; 2053 switch (CCCode) { 2054 default: llvm_unreachable("Unknown integer setcc!"); 2055 case ISD::SETLT: 2056 case ISD::SETULT: LowCC = ISD::SETULT; break; 2057 case ISD::SETGT: 2058 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2059 case ISD::SETLE: 2060 case ISD::SETULE: LowCC = ISD::SETULE; break; 2061 case ISD::SETGE: 2062 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2063 } 2064 2065 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2066 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2067 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2068 2069 // NOTE: on targets without efficient SELECT of bools, we can always use 2070 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2071 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL); 2072 SDValue Tmp1, Tmp2; 2073 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), 2074 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl); 2075 if (!Tmp1.getNode()) 2076 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 2077 LHSLo, RHSLo, LowCC); 2078 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2079 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl); 2080 if (!Tmp2.getNode()) 2081 Tmp2 = DAG.getNode(ISD::SETCC, dl, 2082 TLI.getSetCCResultType(LHSHi.getValueType()), 2083 LHSHi, RHSHi, DAG.getCondCode(CCCode)); 2084 2085 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2086 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2087 if ((Tmp1C && Tmp1C->isNullValue()) || 2088 (Tmp2C && Tmp2C->isNullValue() && 2089 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2090 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2091 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2092 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2093 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2094 // low part is known false, returns high part. 2095 // For LE / GE, if high part is known false, ignore the low part. 2096 // For LT / GT, if high part is known true, ignore the low part. 2097 NewLHS = Tmp2; 2098 NewRHS = SDValue(); 2099 return; 2100 } 2101 2102 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2103 LHSHi, RHSHi, ISD::SETEQ, false, 2104 DagCombineInfo, dl); 2105 if (!NewLHS.getNode()) 2106 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 2107 LHSHi, RHSHi, ISD::SETEQ); 2108 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), 2109 NewLHS, Tmp1, Tmp2); 2110 NewRHS = SDValue(); 2111} 2112 2113SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2114 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2115 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2116 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2117 2118 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2119 // against zero to select between true and false values. 2120 if (NewRHS.getNode() == 0) { 2121 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2122 CCCode = ISD::SETNE; 2123 } 2124 2125 // Update N to have the operands specified. 2126 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 2127 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2128 N->getOperand(4)); 2129} 2130 2131SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2132 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2133 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2134 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2135 2136 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2137 // against zero to select between true and false values. 2138 if (NewRHS.getNode() == 0) { 2139 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2140 CCCode = ISD::SETNE; 2141 } 2142 2143 // Update N to have the operands specified. 2144 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2145 N->getOperand(2), N->getOperand(3), 2146 DAG.getCondCode(CCCode)); 2147} 2148 2149SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2150 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2151 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2152 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2153 2154 // If ExpandSetCCOperands returned a scalar, use it. 2155 if (NewRHS.getNode() == 0) { 2156 assert(NewLHS.getValueType() == N->getValueType(0) && 2157 "Unexpected setcc expansion!"); 2158 return NewLHS; 2159 } 2160 2161 // Otherwise, update N to have the operands specified. 2162 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2163 DAG.getCondCode(CCCode)); 2164} 2165 2166SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) { 2167 // The value being shifted is legal, but the shift amount is too big. 2168 // It follows that either the result of the shift is undefined, or the 2169 // upper half of the shift amount is zero. Just use the lower half. 2170 SDValue Lo, Hi; 2171 GetExpandedInteger(N->getOperand(1), Lo, Hi); 2172 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo); 2173} 2174 2175SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2176 SDValue Op = N->getOperand(0); 2177 MVT DstVT = N->getValueType(0); 2178 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2179 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2180 "Don't know how to expand this SINT_TO_FP!"); 2181 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc()); 2182} 2183 2184SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2185 if (ISD::isNormalStore(N)) 2186 return ExpandOp_NormalStore(N, OpNo); 2187 2188 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2189 assert(OpNo == 1 && "Can only expand the stored value so far"); 2190 2191 MVT VT = N->getOperand(1).getValueType(); 2192 MVT NVT = TLI.getTypeToTransformTo(VT); 2193 SDValue Ch = N->getChain(); 2194 SDValue Ptr = N->getBasePtr(); 2195 int SVOffset = N->getSrcValueOffset(); 2196 unsigned Alignment = N->getAlignment(); 2197 bool isVolatile = N->isVolatile(); 2198 DebugLoc dl = N->getDebugLoc(); 2199 SDValue Lo, Hi; 2200 2201 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2202 2203 if (N->getMemoryVT().bitsLE(NVT)) { 2204 GetExpandedInteger(N->getValue(), Lo, Hi); 2205 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, 2206 N->getMemoryVT(), isVolatile, Alignment); 2207 } else if (TLI.isLittleEndian()) { 2208 // Little-endian - low bits are at low addresses. 2209 GetExpandedInteger(N->getValue(), Lo, Hi); 2210 2211 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, 2212 isVolatile, Alignment); 2213 2214 unsigned ExcessBits = 2215 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2216 MVT NEVT = MVT::getIntegerVT(ExcessBits); 2217 2218 // Increment the pointer to the other half. 2219 unsigned IncrementSize = NVT.getSizeInBits()/8; 2220 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2221 DAG.getIntPtrConstant(IncrementSize)); 2222 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), 2223 SVOffset+IncrementSize, NEVT, 2224 isVolatile, MinAlign(Alignment, IncrementSize)); 2225 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2226 } else { 2227 // Big-endian - high bits are at low addresses. Favor aligned stores at 2228 // the cost of some bit-fiddling. 2229 GetExpandedInteger(N->getValue(), Lo, Hi); 2230 2231 MVT EVT = N->getMemoryVT(); 2232 unsigned EBytes = EVT.getStoreSizeInBits()/8; 2233 unsigned IncrementSize = NVT.getSizeInBits()/8; 2234 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2235 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 2236 2237 if (ExcessBits < NVT.getSizeInBits()) { 2238 // Transfer high bits from the top of Lo to the bottom of Hi. 2239 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, 2240 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2241 TLI.getPointerTy())); 2242 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, 2243 DAG.getNode(ISD::SRL, dl, NVT, Lo, 2244 DAG.getConstant(ExcessBits, 2245 TLI.getPointerTy()))); 2246 } 2247 2248 // Store both the high bits and maybe some of the low bits. 2249 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), 2250 SVOffset, HiVT, isVolatile, Alignment); 2251 2252 // Increment the pointer to the other half. 2253 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2254 DAG.getIntPtrConstant(IncrementSize)); 2255 // Store the lowest ExcessBits bits in the second half. 2256 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), 2257 SVOffset+IncrementSize, 2258 MVT::getIntegerVT(ExcessBits), 2259 isVolatile, MinAlign(Alignment, IncrementSize)); 2260 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2261 } 2262} 2263 2264SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2265 SDValue InL, InH; 2266 GetExpandedInteger(N->getOperand(0), InL, InH); 2267 // Just truncate the low part of the source. 2268 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL); 2269} 2270 2271SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2272 SDValue Op = N->getOperand(0); 2273 MVT SrcVT = Op.getValueType(); 2274 MVT DstVT = N->getValueType(0); 2275 DebugLoc dl = N->getDebugLoc(); 2276 2277 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2278 // Do a signed conversion then adjust the result. 2279 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); 2280 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2281 2282 // The result of the signed conversion needs adjusting if the 'sign bit' of 2283 // the incoming integer was set. To handle this, we dynamically test to see 2284 // if it is set, and, if so, add a fudge factor. 2285 2286 const uint64_t F32TwoE32 = 0x4F800000ULL; 2287 const uint64_t F32TwoE64 = 0x5F800000ULL; 2288 const uint64_t F32TwoE128 = 0x7F800000ULL; 2289 2290 APInt FF(32, 0); 2291 if (SrcVT == MVT::i32) 2292 FF = APInt(32, F32TwoE32); 2293 else if (SrcVT == MVT::i64) 2294 FF = APInt(32, F32TwoE64); 2295 else if (SrcVT == MVT::i128) 2296 FF = APInt(32, F32TwoE128); 2297 else 2298 assert(false && "Unsupported UINT_TO_FP!"); 2299 2300 // Check whether the sign bit is set. 2301 SDValue Lo, Hi; 2302 GetExpandedInteger(Op, Lo, Hi); 2303 SDValue SignSet = DAG.getSetCC(dl, 2304 TLI.getSetCCResultType(Hi.getValueType()), 2305 Hi, DAG.getConstant(0, Hi.getValueType()), 2306 ISD::SETLT); 2307 2308 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2309 SDValue FudgePtr = DAG.getConstantPool( 2310 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 2311 TLI.getPointerTy()); 2312 2313 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2314 SDValue Zero = DAG.getIntPtrConstant(0); 2315 SDValue Four = DAG.getIntPtrConstant(4); 2316 if (TLI.isBigEndian()) std::swap(Zero, Four); 2317 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 2318 Zero, Four); 2319 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2320 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset); 2321 Alignment = std::min(Alignment, 4u); 2322 2323 // Load the value out, extending it from f32 to the destination float type. 2324 // FIXME: Avoid the extend by constructing the right constant pool? 2325 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), 2326 FudgePtr, NULL, 0, MVT::f32, 2327 false, Alignment); 2328 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); 2329 } 2330 2331 // Otherwise, use a libcall. 2332 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2333 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2334 "Don't know how to expand this UINT_TO_FP!"); 2335 return MakeLibCall(LC, DstVT, &Op, 1, true, dl); 2336} 2337