LegalizeIntegerTypes.cpp revision 268637ed0f34e10e4125e94c44ff3e2975a19166
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22#include "llvm/CodeGen/PseudoSourceValue.h" 23#include "llvm/Support/ErrorHandling.h" 24#include "llvm/Support/raw_ostream.h" 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28// Integer Result Promotion 29//===----------------------------------------------------------------------===// 30 31/// PromoteIntegerResult - This method is called when a result of a node is 32/// found to be in need of promotion to a larger type. At this point, the node 33/// may also have invalid operands or may have other results that need 34/// expansion, we just know that (at least) one result needs promotion. 35void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n"); 37 SDValue Res = SDValue(); 38 39 // See if the target wants to custom expand this node. 40 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 41 return; 42 43 switch (N->getOpcode()) { 44 default: 45#ifndef NDEBUG 46 dbgs() << "PromoteIntegerResult #" << ResNo << ": "; 47 N->dump(&DAG); dbgs() << "\n"; 48#endif 49 llvm_unreachable("Do not know how to promote this operator!"); 50 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 51 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 52 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break; 53 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 54 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 55 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 56 case ISD::CONVERT_RNDSAT: 57 Res = PromoteIntRes_CONVERT_RNDSAT(N); break; 58 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; 59 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break; 60 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; 61 case ISD::EXTRACT_VECTOR_ELT: 62 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 63 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 64 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break; 65 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; 66 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 67 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 68 case ISD::SIGN_EXTEND_INREG: 69 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 70 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 71 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 72 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; 73 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; 74 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; 75 76 case ISD::SIGN_EXTEND: 77 case ISD::ZERO_EXTEND: 78 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; 79 80 case ISD::FP_TO_SINT: 81 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; 82 83 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break; 84 85 case ISD::AND: 86 case ISD::OR: 87 case ISD::XOR: 88 case ISD::ADD: 89 case ISD::SUB: 90 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break; 91 92 case ISD::SDIV: 93 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; 94 95 case ISD::UDIV: 96 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break; 97 98 case ISD::SADDO: 99 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; 100 case ISD::UADDO: 101 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; 102 case ISD::SMULO: 103 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; 104 105 case ISD::ATOMIC_LOAD_ADD: 106 case ISD::ATOMIC_LOAD_SUB: 107 case ISD::ATOMIC_LOAD_AND: 108 case ISD::ATOMIC_LOAD_OR: 109 case ISD::ATOMIC_LOAD_XOR: 110 case ISD::ATOMIC_LOAD_NAND: 111 case ISD::ATOMIC_LOAD_MIN: 112 case ISD::ATOMIC_LOAD_MAX: 113 case ISD::ATOMIC_LOAD_UMIN: 114 case ISD::ATOMIC_LOAD_UMAX: 115 case ISD::ATOMIC_SWAP: 116 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 117 118 case ISD::ATOMIC_CMP_SWAP: 119 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 120 } 121 122 // If the result is null then the sub-method took care of registering it. 123 if (Res.getNode()) 124 SetPromotedInteger(SDValue(N, ResNo), Res); 125} 126 127SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 128 // Sign-extend the new bits, and continue the assertion. 129 SDValue Op = SExtPromotedInteger(N->getOperand(0)); 130 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), 131 Op.getValueType(), Op, N->getOperand(1)); 132} 133 134SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 135 // Zero the new bits, and continue the assertion. 136 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 137 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), 138 Op.getValueType(), Op, N->getOperand(1)); 139} 140 141SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 142 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 143 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 144 N->getMemoryVT(), 145 N->getChain(), N->getBasePtr(), 146 Op2, N->getSrcValue(), N->getAlignment()); 147 // Legalized the chain result - switch anything that used the old chain to 148 // use the new one. 149 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 150 return Res; 151} 152 153SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 154 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 155 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 156 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 157 N->getMemoryVT(), N->getChain(), N->getBasePtr(), 158 Op2, Op3, N->getSrcValue(), N->getAlignment()); 159 // Legalized the chain result - switch anything that used the old chain to 160 // use the new one. 161 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 162 return Res; 163} 164 165SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 166 SDValue InOp = N->getOperand(0); 167 EVT InVT = InOp.getValueType(); 168 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); 169 EVT OutVT = N->getValueType(0); 170 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 171 DebugLoc dl = N->getDebugLoc(); 172 173 switch (getTypeAction(InVT)) { 174 default: 175 assert(false && "Unknown type action!"); 176 break; 177 case Legal: 178 break; 179 case PromoteInteger: 180 if (NOutVT.bitsEq(NInVT)) 181 // The input promotes to the same size. Convert the promoted value. 182 return DAG.getNode(ISD::BIT_CONVERT, dl, 183 NOutVT, GetPromotedInteger(InOp)); 184 break; 185 case SoftenFloat: 186 // Promote the integer operand by hand. 187 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); 188 case ExpandInteger: 189 case ExpandFloat: 190 break; 191 case ScalarizeVector: 192 // Convert the element to an integer and promote it by hand. 193 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 194 BitConvertToInteger(GetScalarizedVector(InOp))); 195 case SplitVector: { 196 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 197 // pieces of the input into integers and reassemble in the final type. 198 SDValue Lo, Hi; 199 GetSplitVector(N->getOperand(0), Lo, Hi); 200 Lo = BitConvertToInteger(Lo); 201 Hi = BitConvertToInteger(Hi); 202 203 if (TLI.isBigEndian()) 204 std::swap(Lo, Hi); 205 206 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, 207 EVT::getIntegerVT(*DAG.getContext(), 208 NOutVT.getSizeInBits()), 209 JoinIntegers(Lo, Hi)); 210 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp); 211 } 212 case WidenVector: 213 if (OutVT.bitsEq(NInVT)) 214 // The input is widened to the same size. Convert to the widened value. 215 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp)); 216 } 217 218 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 219 CreateStackStoreLoad(InOp, OutVT)); 220} 221 222SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 223 SDValue Op = GetPromotedInteger(N->getOperand(0)); 224 EVT OVT = N->getValueType(0); 225 EVT NVT = Op.getValueType(); 226 DebugLoc dl = N->getDebugLoc(); 227 228 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 229 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 230 DAG.getConstant(DiffBits, TLI.getPointerTy())); 231} 232 233SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 234 // The pair element type may be legal, or may not promote to the same type as 235 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 236 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), 237 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)), 238 JoinIntegers(N->getOperand(0), N->getOperand(1))); 239} 240 241SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 242 EVT VT = N->getValueType(0); 243 // FIXME there is no actual debug info here 244 DebugLoc dl = N->getDebugLoc(); 245 // Zero extend things like i1, sign extend everything else. It shouldn't 246 // matter in theory which one we pick, but this tends to give better code? 247 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 248 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(*DAG.getContext(), VT), 249 SDValue(N, 0)); 250 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 251 return Result; 252} 253 254SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 255 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 256 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 257 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 258 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 259 "can only promote integers"); 260 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 261 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0), 262 N->getOperand(1), N->getOperand(2), 263 N->getOperand(3), N->getOperand(4), CvtCode); 264} 265 266SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 267 // Zero extend to the promoted type and do the count there. 268 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 269 DebugLoc dl = N->getDebugLoc(); 270 EVT OVT = N->getValueType(0); 271 EVT NVT = Op.getValueType(); 272 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op); 273 // Subtract off the extra leading bits in the bigger type. 274 return DAG.getNode(ISD::SUB, dl, NVT, Op, 275 DAG.getConstant(NVT.getSizeInBits() - 276 OVT.getSizeInBits(), NVT)); 277} 278 279SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 280 // Zero extend to the promoted type and do the count there. 281 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 282 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op); 283} 284 285SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 286 SDValue Op = GetPromotedInteger(N->getOperand(0)); 287 EVT OVT = N->getValueType(0); 288 EVT NVT = Op.getValueType(); 289 DebugLoc dl = N->getDebugLoc(); 290 // The count is the same in the promoted type except if the original 291 // value was zero. This can be handled by setting the bit just off 292 // the top of the original type. 293 APInt TopBit(NVT.getSizeInBits(), 0); 294 TopBit.set(OVT.getSizeInBits()); 295 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT)); 296 return DAG.getNode(ISD::CTTZ, dl, NVT, Op); 297} 298 299SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 300 DebugLoc dl = N->getDebugLoc(); 301 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 302 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0), 303 N->getOperand(1)); 304} 305 306SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 307 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 308 unsigned NewOpc = N->getOpcode(); 309 DebugLoc dl = N->getDebugLoc(); 310 311 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is 312 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT 313 // and SINT conversions are Custom, there is no way to tell which is preferable. 314 // We choose SINT because that's the right thing on PPC.) 315 if (N->getOpcode() == ISD::FP_TO_UINT && 316 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 317 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) 318 NewOpc = ISD::FP_TO_SINT; 319 320 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); 321 322 // Assert that the converted value fits in the original type. If it doesn't 323 // (eg: because the value being converted is too big), then the result of the 324 // original operation was undefined anyway, so the assert is still correct. 325 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 326 ISD::AssertZext : ISD::AssertSext, dl, 327 NVT, Res, DAG.getValueType(N->getValueType(0))); 328} 329 330SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) { 331 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 332 DebugLoc dl = N->getDebugLoc(); 333 334 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 335 336 return DAG.getNode(ISD::AssertZext, dl, 337 NVT, Res, DAG.getValueType(N->getValueType(0))); 338} 339 340SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 341 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 342 DebugLoc dl = N->getDebugLoc(); 343 344 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 345 SDValue Res = GetPromotedInteger(N->getOperand(0)); 346 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 347 348 // If the result and operand types are the same after promotion, simplify 349 // to an in-register extension. 350 if (NVT == Res.getValueType()) { 351 // The high bits are not guaranteed to be anything. Insert an extend. 352 if (N->getOpcode() == ISD::SIGN_EXTEND) 353 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 354 DAG.getValueType(N->getOperand(0).getValueType())); 355 if (N->getOpcode() == ISD::ZERO_EXTEND) 356 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType()); 357 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 358 return Res; 359 } 360 } 361 362 // Otherwise, just extend the original operand all the way to the larger type. 363 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 364} 365 366SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 367 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 368 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 369 ISD::LoadExtType ExtType = 370 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 371 DebugLoc dl = N->getDebugLoc(); 372 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), 373 N->getSrcValue(), N->getSrcValueOffset(), 374 N->getMemoryVT(), N->isVolatile(), 375 N->isNonTemporal(), N->getAlignment()); 376 377 // Legalized the chain result - switch anything that used the old chain to 378 // use the new one. 379 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 380 return Res; 381} 382 383/// Promote the overflow flag of an overflowing arithmetic node. 384SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { 385 // Simply change the return type of the boolean result. 386 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1)); 387 EVT ValueVTs[] = { N->getValueType(0), NVT }; 388 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; 389 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), 390 DAG.getVTList(ValueVTs, 2), Ops, 2); 391 392 // Modified the sum result - switch anything that used the old sum to use 393 // the new one. 394 ReplaceValueWith(SDValue(N, 0), Res); 395 396 return SDValue(Res.getNode(), 1); 397} 398 399SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { 400 if (ResNo == 1) 401 return PromoteIntRes_Overflow(N); 402 403 // The operation overflowed iff the result in the larger type is not the 404 // sign extension of its truncation to the original type. 405 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 406 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 407 EVT OVT = N->getOperand(0).getValueType(); 408 EVT NVT = LHS.getValueType(); 409 DebugLoc dl = N->getDebugLoc(); 410 411 // Do the arithmetic in the larger type. 412 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 413 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 414 415 // Calculate the overflow flag: sign extend the arithmetic result from 416 // the original type. 417 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 418 DAG.getValueType(OVT)); 419 // Overflowed if and only if this is not equal to Res. 420 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 421 422 // Use the calculated overflow everywhere. 423 ReplaceValueWith(SDValue(N, 1), Ofl); 424 425 return Res; 426} 427 428SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 429 // Sign extend the input. 430 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 431 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 432 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 433 LHS.getValueType(), LHS, RHS); 434} 435 436SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 437 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 438 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 439 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 440 LHS.getValueType(), N->getOperand(0),LHS,RHS); 441} 442 443SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 444 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 445 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 446 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 447 LHS.getValueType(), N->getOperand(0), 448 N->getOperand(1), LHS, RHS, N->getOperand(4)); 449} 450 451SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 452 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); 453 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 454 DebugLoc dl = N->getDebugLoc(); 455 456 // Get the SETCC result using the canonical SETCC type. 457 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0), 458 N->getOperand(1), N->getOperand(2)); 459 460 // Convert to the expected type. 461 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 462 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 463 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 464} 465 466SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 467 return DAG.getNode(ISD::SHL, N->getDebugLoc(), 468 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)), 469 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 470} 471 472SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 473 SDValue Op = GetPromotedInteger(N->getOperand(0)); 474 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), 475 Op.getValueType(), Op, N->getOperand(1)); 476} 477 478SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 479 // The input may have strange things in the top bits of the registers, but 480 // these operations don't care. They may have weird bits going out, but 481 // that too is okay if they are integer operations. 482 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 483 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 484 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 485 LHS.getValueType(), LHS, RHS); 486} 487 488SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 489 // The input value must be properly sign extended. 490 SDValue Res = SExtPromotedInteger(N->getOperand(0)); 491 return DAG.getNode(ISD::SRA, N->getDebugLoc(), 492 Res.getValueType(), Res, N->getOperand(1)); 493} 494 495SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 496 // The input value must be properly zero extended. 497 EVT VT = N->getValueType(0); 498 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 499 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 500 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); 501} 502 503SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 504 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 505 SDValue Res; 506 507 switch (getTypeAction(N->getOperand(0).getValueType())) { 508 default: llvm_unreachable("Unknown type action!"); 509 case Legal: 510 case ExpandInteger: 511 Res = N->getOperand(0); 512 break; 513 case PromoteInteger: 514 Res = GetPromotedInteger(N->getOperand(0)); 515 break; 516 } 517 518 // Truncate to NVT instead of VT 519 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res); 520} 521 522SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { 523 if (ResNo == 1) 524 return PromoteIntRes_Overflow(N); 525 526 // The operation overflowed iff the result in the larger type is not the 527 // zero extension of its truncation to the original type. 528 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 529 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 530 EVT OVT = N->getOperand(0).getValueType(); 531 EVT NVT = LHS.getValueType(); 532 DebugLoc dl = N->getDebugLoc(); 533 534 // Do the arithmetic in the larger type. 535 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 536 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 537 538 // Calculate the overflow flag: zero extend the arithmetic result from 539 // the original type. 540 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); 541 // Overflowed if and only if this is not equal to Res. 542 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 543 544 // Use the calculated overflow everywhere. 545 ReplaceValueWith(SDValue(N, 1), Ofl); 546 547 return Res; 548} 549 550SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 551 // Zero extend the input. 552 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 553 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 554 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 555 LHS.getValueType(), LHS, RHS); 556} 557 558SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 559 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(), 560 N->getValueType(0))); 561} 562 563SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 564 SDValue Chain = N->getOperand(0); // Get the chain. 565 SDValue Ptr = N->getOperand(1); // Get the pointer. 566 EVT VT = N->getValueType(0); 567 DebugLoc dl = N->getDebugLoc(); 568 569 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); 570 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT); 571 // The argument is passed as NumRegs registers of type RegVT. 572 573 SmallVector<SDValue, 8> Parts(NumRegs); 574 for (unsigned i = 0; i < NumRegs; ++i) { 575 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2)); 576 Chain = Parts[i].getValue(1); 577 } 578 579 // Handle endianness of the load. 580 if (TLI.isBigEndian()) 581 std::reverse(Parts.begin(), Parts.end()); 582 583 // Assemble the parts in the promoted type. 584 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 585 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); 586 for (unsigned i = 1; i < NumRegs; ++i) { 587 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); 588 // Shift it to the right position and "or" it in. 589 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, 590 DAG.getConstant(i * RegVT.getSizeInBits(), 591 TLI.getPointerTy())); 592 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); 593 } 594 595 // Modified the chain result - switch anything that used the old chain to 596 // use the new one. 597 ReplaceValueWith(SDValue(N, 1), Chain); 598 599 return Res; 600} 601 602SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) { 603 assert(ResNo == 1 && "Only boolean result promotion currently supported!"); 604 return PromoteIntRes_Overflow(N); 605} 606 607//===----------------------------------------------------------------------===// 608// Integer Operand Promotion 609//===----------------------------------------------------------------------===// 610 611/// PromoteIntegerOperand - This method is called when the specified operand of 612/// the specified node is found to need promotion. At this point, all of the 613/// result types of the node are known to be legal, but other operands of the 614/// node may need promotion or expansion as well as the specified one. 615bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 616 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n"); 617 SDValue Res = SDValue(); 618 619 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 620 return false; 621 622 switch (N->getOpcode()) { 623 default: 624 #ifndef NDEBUG 625 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": "; 626 N->dump(&DAG); dbgs() << "\n"; 627 #endif 628 llvm_unreachable("Do not know how to promote this operator's operand!"); 629 630 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 631 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break; 632 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 633 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 634 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 635 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 636 case ISD::CONVERT_RNDSAT: 637 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 638 case ISD::INSERT_VECTOR_ELT: 639 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 640 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 641 case ISD::SCALAR_TO_VECTOR: 642 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break; 643 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 644 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 645 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 646 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 647 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 648 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 649 OpNo); break; 650 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 651 case ISD::FP16_TO_FP32: 652 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; 653 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 654 655 case ISD::SHL: 656 case ISD::SRA: 657 case ISD::SRL: 658 case ISD::ROTL: 659 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; 660 } 661 662 // If the result is null, the sub-method took care of registering results etc. 663 if (!Res.getNode()) return false; 664 665 // If the result is N, the sub-method updated N in place. Tell the legalizer 666 // core about this. 667 if (Res.getNode() == N) 668 return true; 669 670 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 671 "Invalid operand expansion"); 672 673 ReplaceValueWith(SDValue(N, 0), Res); 674 return false; 675} 676 677/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 678/// shared among BR_CC, SELECT_CC, and SETCC handlers. 679void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 680 ISD::CondCode CCCode) { 681 // We have to insert explicit sign or zero extends. Note that we could 682 // insert sign extends for ALL conditions, but zero extend is cheaper on 683 // many machines (an AND instead of two shifts), so prefer it. 684 switch (CCCode) { 685 default: llvm_unreachable("Unknown integer comparison!"); 686 case ISD::SETEQ: 687 case ISD::SETNE: 688 case ISD::SETUGE: 689 case ISD::SETUGT: 690 case ISD::SETULE: 691 case ISD::SETULT: 692 // ALL of these operations will work if we either sign or zero extend 693 // the operands (including the unsigned comparisons!). Zero extend is 694 // usually a simpler/cheaper operation, so prefer it. 695 NewLHS = ZExtPromotedInteger(NewLHS); 696 NewRHS = ZExtPromotedInteger(NewRHS); 697 break; 698 case ISD::SETGE: 699 case ISD::SETGT: 700 case ISD::SETLT: 701 case ISD::SETLE: 702 NewLHS = SExtPromotedInteger(NewLHS); 703 NewRHS = SExtPromotedInteger(NewRHS); 704 break; 705 } 706} 707 708SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 709 SDValue Op = GetPromotedInteger(N->getOperand(0)); 710 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); 711} 712 713SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) { 714 // This should only occur in unusual situations like bitcasting to an 715 // x86_fp80, so just turn it into a store+load 716 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0)); 717} 718 719SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 720 assert(OpNo == 2 && "Don't know how to promote this operand!"); 721 722 SDValue LHS = N->getOperand(2); 723 SDValue RHS = N->getOperand(3); 724 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 725 726 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 727 // legal types. 728 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 729 N->getOperand(1), LHS, RHS, N->getOperand(4)); 730} 731 732SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 733 assert(OpNo == 1 && "only know how to promote condition"); 734 735 // Promote all the way up to the canonical SetCC type. 736 EVT SVT = TLI.getSetCCResultType(MVT::Other); 737 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT); 738 739 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 740 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, 741 N->getOperand(2)); 742} 743 744SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 745 // Since the result type is legal, the operands must promote to it. 746 EVT OVT = N->getOperand(0).getValueType(); 747 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); 748 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 749 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 750 DebugLoc dl = N->getDebugLoc(); 751 752 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, 753 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy())); 754 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); 755} 756 757SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 758 // The vector type is legal but the element type is not. This implies 759 // that the vector is a power-of-two in length and that the element 760 // type does not have a strange size (eg: it is not i1). 761 EVT VecVT = N->getValueType(0); 762 unsigned NumElts = VecVT.getVectorNumElements(); 763 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 764 765 // Promote the inserted value. The type does not need to match the 766 // vector element type. Check that any extra bits introduced will be 767 // truncated away. 768 assert(N->getOperand(0).getValueType().getSizeInBits() >= 769 N->getValueType(0).getVectorElementType().getSizeInBits() && 770 "Type of inserted value narrower than vector element type!"); 771 772 SmallVector<SDValue, 16> NewOps; 773 for (unsigned i = 0; i < NumElts; ++i) 774 NewOps.push_back(GetPromotedInteger(N->getOperand(i))); 775 776 return DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NumElts); 777} 778 779SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 780 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 781 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 782 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 783 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 784 "can only promote integer arguments"); 785 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 786 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp, 787 N->getOperand(1), N->getOperand(2), 788 N->getOperand(3), N->getOperand(4), CvtCode); 789} 790 791SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 792 unsigned OpNo) { 793 if (OpNo == 1) { 794 // Promote the inserted value. This is valid because the type does not 795 // have to match the vector element type. 796 797 // Check that any extra bits introduced will be truncated away. 798 assert(N->getOperand(1).getValueType().getSizeInBits() >= 799 N->getValueType(0).getVectorElementType().getSizeInBits() && 800 "Type of inserted value narrower than vector element type!"); 801 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 802 GetPromotedInteger(N->getOperand(1)), 803 N->getOperand(2)); 804 } 805 806 assert(OpNo == 2 && "Different operand and result vector types?"); 807 808 // Promote the index. 809 SDValue Idx = ZExtPromotedInteger(N->getOperand(2)); 810 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 811 N->getOperand(1), Idx); 812} 813 814SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 815 SDValue NewOps[6]; 816 DebugLoc dl = N->getDebugLoc(); 817 NewOps[0] = N->getOperand(0); 818 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 819 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 820 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1); 821 } 822 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, 823 array_lengthof(NewOps)); 824} 825 826SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) { 827 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote 828 // the operand in place. 829 return DAG.UpdateNodeOperands(SDValue(N, 0), 830 GetPromotedInteger(N->getOperand(0))); 831} 832 833SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 834 assert(OpNo == 0 && "Only know how to promote condition"); 835 836 // Promote all the way up to the canonical SetCC type. 837 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType()); 838 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT); 839 840 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, 841 N->getOperand(1), N->getOperand(2)); 842} 843 844SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 845 assert(OpNo == 0 && "Don't know how to promote this operand!"); 846 847 SDValue LHS = N->getOperand(0); 848 SDValue RHS = N->getOperand(1); 849 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 850 851 // The CC (#4) and the possible return values (#2 and #3) have legal types. 852 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2), 853 N->getOperand(3), N->getOperand(4)); 854} 855 856SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 857 assert(OpNo == 0 && "Don't know how to promote this operand!"); 858 859 SDValue LHS = N->getOperand(0); 860 SDValue RHS = N->getOperand(1); 861 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 862 863 // The CC (#2) is always legal. 864 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); 865} 866 867SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) { 868 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 869 ZExtPromotedInteger(N->getOperand(1))); 870} 871 872SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 873 SDValue Op = GetPromotedInteger(N->getOperand(0)); 874 DebugLoc dl = N->getDebugLoc(); 875 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 876 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), 877 Op, DAG.getValueType(N->getOperand(0).getValueType())); 878} 879 880SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { 881 return DAG.UpdateNodeOperands(SDValue(N, 0), 882 SExtPromotedInteger(N->getOperand(0))); 883} 884 885SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 886 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 887 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 888 int SVOffset = N->getSrcValueOffset(); 889 unsigned Alignment = N->getAlignment(); 890 bool isVolatile = N->isVolatile(); 891 bool isNonTemporal = N->isNonTemporal(); 892 DebugLoc dl = N->getDebugLoc(); 893 894 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 895 896 // Truncate the value and store the result. 897 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(), 898 SVOffset, N->getMemoryVT(), 899 isVolatile, isNonTemporal, Alignment); 900} 901 902SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 903 SDValue Op = GetPromotedInteger(N->getOperand(0)); 904 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op); 905} 906 907SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { 908 return DAG.UpdateNodeOperands(SDValue(N, 0), 909 ZExtPromotedInteger(N->getOperand(0))); 910} 911 912SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 913 DebugLoc dl = N->getDebugLoc(); 914 SDValue Op = GetPromotedInteger(N->getOperand(0)); 915 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 916 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType()); 917} 918 919 920//===----------------------------------------------------------------------===// 921// Integer Result Expansion 922//===----------------------------------------------------------------------===// 923 924/// ExpandIntegerResult - This method is called when the specified result of the 925/// specified node is found to need expansion. At this point, the node may also 926/// have invalid operands or may have other results that need promotion, we just 927/// know that (at least) one result needs expansion. 928void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 929 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n"); 930 SDValue Lo, Hi; 931 Lo = Hi = SDValue(); 932 933 // See if the target wants to custom expand this node. 934 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 935 return; 936 937 switch (N->getOpcode()) { 938 default: 939#ifndef NDEBUG 940 dbgs() << "ExpandIntegerResult #" << ResNo << ": "; 941 N->dump(&DAG); dbgs() << "\n"; 942#endif 943 llvm_unreachable("Do not know how to expand the result of this operator!"); 944 945 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 946 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 947 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 948 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 949 950 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 951 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 952 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 953 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 954 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 955 956 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 957 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 958 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 959 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 960 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 961 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 962 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 963 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 964 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 965 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 966 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 967 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 968 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 969 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 970 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 971 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 972 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 973 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 974 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 975 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 976 977 case ISD::AND: 978 case ISD::OR: 979 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 980 981 case ISD::ADD: 982 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 983 984 case ISD::ADDC: 985 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 986 987 case ISD::ADDE: 988 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 989 990 case ISD::SHL: 991 case ISD::SRA: 992 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 993 994 case ISD::SADDO: 995 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break; 996 case ISD::UADDO: 997 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break; 998 } 999 1000 // If Lo/Hi is null, the sub-method took care of registering results etc. 1001 if (Lo.getNode()) 1002 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1003} 1004 1005/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1006/// and the shift amount is a constant 'Amt'. Expand the operation. 1007void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1008 SDValue &Lo, SDValue &Hi) { 1009 DebugLoc dl = N->getDebugLoc(); 1010 // Expand the incoming operand to be shifted, so that we have its parts 1011 SDValue InL, InH; 1012 GetExpandedInteger(N->getOperand(0), InL, InH); 1013 1014 EVT NVT = InL.getValueType(); 1015 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1016 unsigned NVTBits = NVT.getSizeInBits(); 1017 EVT ShTy = N->getOperand(1).getValueType(); 1018 1019 if (N->getOpcode() == ISD::SHL) { 1020 if (Amt > VTBits) { 1021 Lo = Hi = DAG.getConstant(0, NVT); 1022 } else if (Amt > NVTBits) { 1023 Lo = DAG.getConstant(0, NVT); 1024 Hi = DAG.getNode(ISD::SHL, dl, 1025 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1026 } else if (Amt == NVTBits) { 1027 Lo = DAG.getConstant(0, NVT); 1028 Hi = InL; 1029 } else if (Amt == 1 && 1030 TLI.isOperationLegalOrCustom(ISD::ADDC, 1031 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) { 1032 // Emit this X << 1 as X+X. 1033 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1034 SDValue LoOps[2] = { InL, InL }; 1035 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1036 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1037 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1038 } else { 1039 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy)); 1040 Hi = DAG.getNode(ISD::OR, dl, NVT, 1041 DAG.getNode(ISD::SHL, dl, NVT, InH, 1042 DAG.getConstant(Amt, ShTy)), 1043 DAG.getNode(ISD::SRL, dl, NVT, InL, 1044 DAG.getConstant(NVTBits-Amt, ShTy))); 1045 } 1046 return; 1047 } 1048 1049 if (N->getOpcode() == ISD::SRL) { 1050 if (Amt > VTBits) { 1051 Lo = DAG.getConstant(0, NVT); 1052 Hi = DAG.getConstant(0, NVT); 1053 } else if (Amt > NVTBits) { 1054 Lo = DAG.getNode(ISD::SRL, dl, 1055 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1056 Hi = DAG.getConstant(0, NVT); 1057 } else if (Amt == NVTBits) { 1058 Lo = InH; 1059 Hi = DAG.getConstant(0, NVT); 1060 } else { 1061 Lo = DAG.getNode(ISD::OR, dl, NVT, 1062 DAG.getNode(ISD::SRL, dl, NVT, InL, 1063 DAG.getConstant(Amt, ShTy)), 1064 DAG.getNode(ISD::SHL, dl, NVT, InH, 1065 DAG.getConstant(NVTBits-Amt, ShTy))); 1066 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); 1067 } 1068 return; 1069 } 1070 1071 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1072 if (Amt > VTBits) { 1073 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 1074 DAG.getConstant(NVTBits-1, ShTy)); 1075 } else if (Amt > NVTBits) { 1076 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, 1077 DAG.getConstant(Amt-NVTBits, ShTy)); 1078 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 1079 DAG.getConstant(NVTBits-1, ShTy)); 1080 } else if (Amt == NVTBits) { 1081 Lo = InH; 1082 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, 1083 DAG.getConstant(NVTBits-1, ShTy)); 1084 } else { 1085 Lo = DAG.getNode(ISD::OR, dl, NVT, 1086 DAG.getNode(ISD::SRL, dl, NVT, InL, 1087 DAG.getConstant(Amt, ShTy)), 1088 DAG.getNode(ISD::SHL, dl, NVT, InH, 1089 DAG.getConstant(NVTBits-Amt, ShTy))); 1090 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy)); 1091 } 1092} 1093 1094/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1095/// this shift based on knowledge of the high bit of the shift amount. If we 1096/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1097/// shift amount. 1098bool DAGTypeLegalizer:: 1099ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1100 SDValue Amt = N->getOperand(1); 1101 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1102 EVT ShTy = Amt.getValueType(); 1103 unsigned ShBits = ShTy.getScalarType().getSizeInBits(); 1104 unsigned NVTBits = NVT.getScalarType().getSizeInBits(); 1105 assert(isPowerOf2_32(NVTBits) && 1106 "Expanded integer type size not a power of two!"); 1107 DebugLoc dl = N->getDebugLoc(); 1108 1109 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1110 APInt KnownZero, KnownOne; 1111 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1112 1113 // If we don't know anything about the high bits, exit. 1114 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1115 return false; 1116 1117 // Get the incoming operand to be shifted. 1118 SDValue InL, InH; 1119 GetExpandedInteger(N->getOperand(0), InL, InH); 1120 1121 // If we know that any of the high bits of the shift amount are one, then we 1122 // can do this as a couple of simple shifts. 1123 if (KnownOne.intersects(HighBitMask)) { 1124 // Mask out the high bit, which we know is set. 1125 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, 1126 DAG.getConstant(~HighBitMask, ShTy)); 1127 1128 switch (N->getOpcode()) { 1129 default: llvm_unreachable("Unknown shift"); 1130 case ISD::SHL: 1131 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1132 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 1133 return true; 1134 case ISD::SRL: 1135 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1136 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 1137 return true; 1138 case ISD::SRA: 1139 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 1140 DAG.getConstant(NVTBits-1, ShTy)); 1141 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 1142 return true; 1143 } 1144 } 1145 1146#if 0 1147 // FIXME: This code is broken for shifts with a zero amount! 1148 // If we know that all of the high bits of the shift amount are zero, then we 1149 // can do this as a couple of simple shifts. 1150 if ((KnownZero & HighBitMask) == HighBitMask) { 1151 // Compute 32-amt. 1152 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1153 DAG.getConstant(NVTBits, ShTy), 1154 Amt); 1155 unsigned Op1, Op2; 1156 switch (N->getOpcode()) { 1157 default: llvm_unreachable("Unknown shift"); 1158 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1159 case ISD::SRL: 1160 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1161 } 1162 1163 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1164 Hi = DAG.getNode(ISD::OR, NVT, 1165 DAG.getNode(Op1, NVT, InH, Amt), 1166 DAG.getNode(Op2, NVT, InL, Amt2)); 1167 return true; 1168 } 1169#endif 1170 1171 return false; 1172} 1173 1174/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift 1175/// of any size. 1176bool DAGTypeLegalizer:: 1177ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1178 SDValue Amt = N->getOperand(1); 1179 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1180 EVT ShTy = Amt.getValueType(); 1181 unsigned NVTBits = NVT.getSizeInBits(); 1182 assert(isPowerOf2_32(NVTBits) && 1183 "Expanded integer type size not a power of two!"); 1184 DebugLoc dl = N->getDebugLoc(); 1185 1186 // Get the incoming operand to be shifted. 1187 SDValue InL, InH; 1188 GetExpandedInteger(N->getOperand(0), InL, InH); 1189 1190 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy); 1191 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode); 1192 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt); 1193 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy), 1194 Amt, NVBitsNode, ISD::SETULT); 1195 1196 SDValue LoS, HiS, LoL, HiL; 1197 switch (N->getOpcode()) { 1198 default: llvm_unreachable("Unknown shift"); 1199 case ISD::SHL: 1200 // Short: ShAmt < NVTBits 1201 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); 1202 HiS = DAG.getNode(ISD::OR, dl, NVT, 1203 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt), 1204 // FIXME: If Amt is zero, the following shift generates an undefined result 1205 // on some architectures. 1206 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack)); 1207 1208 // Long: ShAmt >= NVTBits 1209 LoL = DAG.getConstant(0, NVT); // Lo part is zero. 1210 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part. 1211 1212 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1213 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1214 return true; 1215 case ISD::SRL: 1216 // Short: ShAmt < NVTBits 1217 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); 1218 LoS = DAG.getNode(ISD::OR, dl, NVT, 1219 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1220 // FIXME: If Amt is zero, the following shift generates an undefined result 1221 // on some architectures. 1222 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); 1223 1224 // Long: ShAmt >= NVTBits 1225 HiL = DAG.getConstant(0, NVT); // Hi part is zero. 1226 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part. 1227 1228 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1229 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1230 return true; 1231 case ISD::SRA: 1232 // Short: ShAmt < NVTBits 1233 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); 1234 LoS = DAG.getNode(ISD::OR, dl, NVT, 1235 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1236 // FIXME: If Amt is zero, the following shift generates an undefined result 1237 // on some architectures. 1238 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); 1239 1240 // Long: ShAmt >= NVTBits 1241 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part. 1242 DAG.getConstant(NVTBits-1, ShTy)); 1243 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part. 1244 1245 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1246 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1247 return true; 1248 } 1249 1250 return false; 1251} 1252 1253void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1254 SDValue &Lo, SDValue &Hi) { 1255 DebugLoc dl = N->getDebugLoc(); 1256 // Expand the subcomponents. 1257 SDValue LHSL, LHSH, RHSL, RHSH; 1258 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1259 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1260 1261 EVT NVT = LHSL.getValueType(); 1262 SDValue LoOps[2] = { LHSL, RHSL }; 1263 SDValue HiOps[3] = { LHSH, RHSH }; 1264 1265 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1266 // them. TODO: Teach operation legalization how to expand unsupported 1267 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1268 // a carry of type MVT::Flag, but there doesn't seem to be any way to 1269 // generate a value of this type in the expanded code sequence. 1270 bool hasCarry = 1271 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? 1272 ISD::ADDC : ISD::SUBC, 1273 TLI.getTypeToExpandTo(*DAG.getContext(), NVT)); 1274 1275 if (hasCarry) { 1276 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1277 if (N->getOpcode() == ISD::ADD) { 1278 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1279 HiOps[2] = Lo.getValue(1); 1280 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1281 } else { 1282 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1283 HiOps[2] = Lo.getValue(1); 1284 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1285 } 1286 } else { 1287 if (N->getOpcode() == ISD::ADD) { 1288 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); 1289 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); 1290 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0], 1291 ISD::SETULT); 1292 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, 1293 DAG.getConstant(1, NVT), 1294 DAG.getConstant(0, NVT)); 1295 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1], 1296 ISD::SETULT); 1297 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, 1298 DAG.getConstant(1, NVT), Carry1); 1299 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); 1300 } else { 1301 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 1302 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); 1303 SDValue Cmp = 1304 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()), 1305 LoOps[0], LoOps[1], ISD::SETULT); 1306 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, 1307 DAG.getConstant(1, NVT), 1308 DAG.getConstant(0, NVT)); 1309 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); 1310 } 1311 } 1312} 1313 1314void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1315 SDValue &Lo, SDValue &Hi) { 1316 // Expand the subcomponents. 1317 SDValue LHSL, LHSH, RHSL, RHSH; 1318 DebugLoc dl = N->getDebugLoc(); 1319 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1320 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1321 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1322 SDValue LoOps[2] = { LHSL, RHSL }; 1323 SDValue HiOps[3] = { LHSH, RHSH }; 1324 1325 if (N->getOpcode() == ISD::ADDC) { 1326 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1327 HiOps[2] = Lo.getValue(1); 1328 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1329 } else { 1330 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1331 HiOps[2] = Lo.getValue(1); 1332 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1333 } 1334 1335 // Legalized the flag result - switch anything that used the old flag to 1336 // use the new one. 1337 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1338} 1339 1340void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1341 SDValue &Lo, SDValue &Hi) { 1342 // Expand the subcomponents. 1343 SDValue LHSL, LHSH, RHSL, RHSH; 1344 DebugLoc dl = N->getDebugLoc(); 1345 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1346 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1347 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1348 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1349 SDValue HiOps[3] = { LHSH, RHSH }; 1350 1351 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3); 1352 HiOps[2] = Lo.getValue(1); 1353 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); 1354 1355 // Legalized the flag result - switch anything that used the old flag to 1356 // use the new one. 1357 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1358} 1359 1360void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1361 SDValue &Lo, SDValue &Hi) { 1362 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1363 DebugLoc dl = N->getDebugLoc(); 1364 SDValue Op = N->getOperand(0); 1365 if (Op.getValueType().bitsLE(NVT)) { 1366 // The low part is any extension of the input (which degenerates to a copy). 1367 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); 1368 Hi = DAG.getUNDEF(NVT); // The high part is undefined. 1369 } else { 1370 // For example, extension of an i48 to an i64. The operand type necessarily 1371 // promotes to the result type, so will end up being expanded too. 1372 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1373 "Only know how to promote this result!"); 1374 SDValue Res = GetPromotedInteger(Op); 1375 assert(Res.getValueType() == N->getValueType(0) && 1376 "Operand over promoted?"); 1377 // Split the promoted operand. This will simplify when it is expanded. 1378 SplitInteger(Res, Lo, Hi); 1379 } 1380} 1381 1382void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1383 SDValue &Lo, SDValue &Hi) { 1384 DebugLoc dl = N->getDebugLoc(); 1385 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1386 EVT NVT = Lo.getValueType(); 1387 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1388 unsigned NVTBits = NVT.getSizeInBits(); 1389 unsigned EVTBits = EVT.getSizeInBits(); 1390 1391 if (NVTBits < EVTBits) { 1392 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, 1393 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1394 EVTBits - NVTBits))); 1395 } else { 1396 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); 1397 // The high part replicates the sign bit of Lo, make it explicit. 1398 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1399 DAG.getConstant(NVTBits-1, TLI.getPointerTy())); 1400 } 1401} 1402 1403void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1404 SDValue &Lo, SDValue &Hi) { 1405 DebugLoc dl = N->getDebugLoc(); 1406 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1407 EVT NVT = Lo.getValueType(); 1408 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1409 unsigned NVTBits = NVT.getSizeInBits(); 1410 unsigned EVTBits = EVT.getSizeInBits(); 1411 1412 if (NVTBits < EVTBits) { 1413 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, 1414 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1415 EVTBits - NVTBits))); 1416 } else { 1417 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); 1418 // The high part must be zero, make it explicit. 1419 Hi = DAG.getConstant(0, NVT); 1420 } 1421} 1422 1423void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1424 SDValue &Lo, SDValue &Hi) { 1425 DebugLoc dl = N->getDebugLoc(); 1426 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1427 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo); 1428 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi); 1429} 1430 1431void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1432 SDValue &Lo, SDValue &Hi) { 1433 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1434 unsigned NBitWidth = NVT.getSizeInBits(); 1435 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1436 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 1437 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1438} 1439 1440void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1441 SDValue &Lo, SDValue &Hi) { 1442 DebugLoc dl = N->getDebugLoc(); 1443 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1444 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1445 EVT NVT = Lo.getValueType(); 1446 1447 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi, 1448 DAG.getConstant(0, NVT), ISD::SETNE); 1449 1450 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo); 1451 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi); 1452 1453 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ, 1454 DAG.getNode(ISD::ADD, dl, NVT, LoLZ, 1455 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1456 Hi = DAG.getConstant(0, NVT); 1457} 1458 1459void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1460 SDValue &Lo, SDValue &Hi) { 1461 DebugLoc dl = N->getDebugLoc(); 1462 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1463 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1464 EVT NVT = Lo.getValueType(); 1465 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), 1466 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); 1467 Hi = DAG.getConstant(0, NVT); 1468} 1469 1470void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1471 SDValue &Lo, SDValue &Hi) { 1472 DebugLoc dl = N->getDebugLoc(); 1473 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1474 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1475 EVT NVT = Lo.getValueType(); 1476 1477 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, 1478 DAG.getConstant(0, NVT), ISD::SETNE); 1479 1480 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); 1481 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); 1482 1483 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ, 1484 DAG.getNode(ISD::ADD, dl, NVT, HiLZ, 1485 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1486 Hi = DAG.getConstant(0, NVT); 1487} 1488 1489void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1490 SDValue &Hi) { 1491 DebugLoc dl = N->getDebugLoc(); 1492 EVT VT = N->getValueType(0); 1493 SDValue Op = N->getOperand(0); 1494 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1495 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1496 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi); 1497} 1498 1499void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1500 SDValue &Hi) { 1501 DebugLoc dl = N->getDebugLoc(); 1502 EVT VT = N->getValueType(0); 1503 SDValue Op = N->getOperand(0); 1504 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1505 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1506 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi); 1507} 1508 1509void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1510 SDValue &Lo, SDValue &Hi) { 1511 if (ISD::isNormalLoad(N)) { 1512 ExpandRes_NormalLoad(N, Lo, Hi); 1513 return; 1514 } 1515 1516 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1517 1518 EVT VT = N->getValueType(0); 1519 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1520 SDValue Ch = N->getChain(); 1521 SDValue Ptr = N->getBasePtr(); 1522 ISD::LoadExtType ExtType = N->getExtensionType(); 1523 int SVOffset = N->getSrcValueOffset(); 1524 unsigned Alignment = N->getAlignment(); 1525 bool isVolatile = N->isVolatile(); 1526 bool isNonTemporal = N->isNonTemporal(); 1527 DebugLoc dl = N->getDebugLoc(); 1528 1529 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1530 1531 if (N->getMemoryVT().bitsLE(NVT)) { 1532 EVT MemVT = N->getMemoryVT(); 1533 1534 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1535 MemVT, isVolatile, isNonTemporal, Alignment); 1536 1537 // Remember the chain. 1538 Ch = Lo.getValue(1); 1539 1540 if (ExtType == ISD::SEXTLOAD) { 1541 // The high part is obtained by SRA'ing all but one of the bits of the 1542 // lo part. 1543 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1544 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1545 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1546 } else if (ExtType == ISD::ZEXTLOAD) { 1547 // The high part is just a zero. 1548 Hi = DAG.getConstant(0, NVT); 1549 } else { 1550 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1551 // The high part is undefined. 1552 Hi = DAG.getUNDEF(NVT); 1553 } 1554 } else if (TLI.isLittleEndian()) { 1555 // Little-endian - low bits are at low addresses. 1556 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset, 1557 isVolatile, isNonTemporal, Alignment); 1558 1559 unsigned ExcessBits = 1560 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1561 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits); 1562 1563 // Increment the pointer to the other half. 1564 unsigned IncrementSize = NVT.getSizeInBits()/8; 1565 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1566 DAG.getIntPtrConstant(IncrementSize)); 1567 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), 1568 SVOffset+IncrementSize, NEVT, 1569 isVolatile, isNonTemporal, 1570 MinAlign(Alignment, IncrementSize)); 1571 1572 // Build a factor node to remember that this load is independent of the 1573 // other one. 1574 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1575 Hi.getValue(1)); 1576 } else { 1577 // Big-endian - high bits are at low addresses. Favor aligned loads at 1578 // the cost of some bit-fiddling. 1579 EVT MemVT = N->getMemoryVT(); 1580 unsigned EBytes = MemVT.getStoreSize(); 1581 unsigned IncrementSize = NVT.getSizeInBits()/8; 1582 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1583 1584 // Load both the high bits and maybe some of the low bits. 1585 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1586 EVT::getIntegerVT(*DAG.getContext(), 1587 MemVT.getSizeInBits() - ExcessBits), 1588 isVolatile, isNonTemporal, Alignment); 1589 1590 // Increment the pointer to the other half. 1591 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1592 DAG.getIntPtrConstant(IncrementSize)); 1593 // Load the rest of the low bits. 1594 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(), 1595 SVOffset+IncrementSize, 1596 EVT::getIntegerVT(*DAG.getContext(), ExcessBits), 1597 isVolatile, isNonTemporal, 1598 MinAlign(Alignment, IncrementSize)); 1599 1600 // Build a factor node to remember that this load is independent of the 1601 // other one. 1602 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1603 Hi.getValue(1)); 1604 1605 if (ExcessBits < NVT.getSizeInBits()) { 1606 // Transfer low bits from the bottom of Hi to the top of Lo. 1607 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, 1608 DAG.getNode(ISD::SHL, dl, NVT, Hi, 1609 DAG.getConstant(ExcessBits, 1610 TLI.getPointerTy()))); 1611 // Move high bits to the right position in Hi. 1612 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, 1613 NVT, Hi, 1614 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1615 TLI.getPointerTy())); 1616 } 1617 } 1618 1619 // Legalized the chain result - switch anything that used the old chain to 1620 // use the new one. 1621 ReplaceValueWith(SDValue(N, 1), Ch); 1622} 1623 1624void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1625 SDValue &Lo, SDValue &Hi) { 1626 DebugLoc dl = N->getDebugLoc(); 1627 SDValue LL, LH, RL, RH; 1628 GetExpandedInteger(N->getOperand(0), LL, LH); 1629 GetExpandedInteger(N->getOperand(1), RL, RH); 1630 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); 1631 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); 1632} 1633 1634void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1635 SDValue &Lo, SDValue &Hi) { 1636 EVT VT = N->getValueType(0); 1637 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1638 DebugLoc dl = N->getDebugLoc(); 1639 1640 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 1641 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 1642 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 1643 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 1644 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1645 SDValue LL, LH, RL, RH; 1646 GetExpandedInteger(N->getOperand(0), LL, LH); 1647 GetExpandedInteger(N->getOperand(1), RL, RH); 1648 unsigned OuterBitSize = VT.getSizeInBits(); 1649 unsigned InnerBitSize = NVT.getSizeInBits(); 1650 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1651 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1652 1653 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1654 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1655 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1656 // The inputs are both zero-extended. 1657 if (HasUMUL_LOHI) { 1658 // We can emit a umul_lohi. 1659 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1660 Hi = SDValue(Lo.getNode(), 1); 1661 return; 1662 } 1663 if (HasMULHU) { 1664 // We can emit a mulhu+mul. 1665 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1666 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1667 return; 1668 } 1669 } 1670 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1671 // The input values are both sign-extended. 1672 if (HasSMUL_LOHI) { 1673 // We can emit a smul_lohi. 1674 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1675 Hi = SDValue(Lo.getNode(), 1); 1676 return; 1677 } 1678 if (HasMULHS) { 1679 // We can emit a mulhs+mul. 1680 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1681 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); 1682 return; 1683 } 1684 } 1685 if (HasUMUL_LOHI) { 1686 // Lo,Hi = umul LHS, RHS. 1687 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 1688 DAG.getVTList(NVT, NVT), LL, RL); 1689 Lo = UMulLOHI; 1690 Hi = UMulLOHI.getValue(1); 1691 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1692 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1693 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1694 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1695 return; 1696 } 1697 if (HasMULHU) { 1698 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1699 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1700 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1701 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1702 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1703 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1704 return; 1705 } 1706 } 1707 1708 // If nothing else, we can make a libcall. 1709 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1710 if (VT == MVT::i16) 1711 LC = RTLIB::MUL_I16; 1712 else if (VT == MVT::i32) 1713 LC = RTLIB::MUL_I32; 1714 else if (VT == MVT::i64) 1715 LC = RTLIB::MUL_I64; 1716 else if (VT == MVT::i128) 1717 LC = RTLIB::MUL_I128; 1718 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1719 1720 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1721 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi); 1722} 1723 1724void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node, 1725 SDValue &Lo, SDValue &Hi) { 1726 SDValue LHS = Node->getOperand(0); 1727 SDValue RHS = Node->getOperand(1); 1728 DebugLoc dl = Node->getDebugLoc(); 1729 1730 // Expand the result by simply replacing it with the equivalent 1731 // non-overflow-checking operation. 1732 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 1733 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 1734 LHS, RHS); 1735 SplitInteger(Sum, Lo, Hi); 1736 1737 // Compute the overflow. 1738 // 1739 // LHSSign -> LHS >= 0 1740 // RHSSign -> RHS >= 0 1741 // SumSign -> Sum >= 0 1742 // 1743 // Add: 1744 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 1745 // Sub: 1746 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 1747 // 1748 EVT OType = Node->getValueType(1); 1749 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 1750 1751 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 1752 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 1753 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 1754 Node->getOpcode() == ISD::SADDO ? 1755 ISD::SETEQ : ISD::SETNE); 1756 1757 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 1758 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 1759 1760 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 1761 1762 // Use the calculated overflow everywhere. 1763 ReplaceValueWith(SDValue(Node, 1), Cmp); 1764} 1765 1766void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1767 SDValue &Lo, SDValue &Hi) { 1768 EVT VT = N->getValueType(0); 1769 DebugLoc dl = N->getDebugLoc(); 1770 1771 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1772 if (VT == MVT::i16) 1773 LC = RTLIB::SDIV_I16; 1774 else if (VT == MVT::i32) 1775 LC = RTLIB::SDIV_I32; 1776 else if (VT == MVT::i64) 1777 LC = RTLIB::SDIV_I64; 1778 else if (VT == MVT::i128) 1779 LC = RTLIB::SDIV_I128; 1780 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1781 1782 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1783 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1784} 1785 1786void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1787 SDValue &Lo, SDValue &Hi) { 1788 EVT VT = N->getValueType(0); 1789 DebugLoc dl = N->getDebugLoc(); 1790 1791 // If we can emit an efficient shift operation, do so now. Check to see if 1792 // the RHS is a constant. 1793 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1794 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1795 1796 // If we can determine that the high bit of the shift is zero or one, even if 1797 // the low bits are variable, emit this shift in an optimized form. 1798 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1799 return; 1800 1801 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1802 unsigned PartsOpc; 1803 if (N->getOpcode() == ISD::SHL) { 1804 PartsOpc = ISD::SHL_PARTS; 1805 } else if (N->getOpcode() == ISD::SRL) { 1806 PartsOpc = ISD::SRL_PARTS; 1807 } else { 1808 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1809 PartsOpc = ISD::SRA_PARTS; 1810 } 1811 1812 // Next check to see if the target supports this SHL_PARTS operation or if it 1813 // will custom expand it. 1814 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1815 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1816 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1817 Action == TargetLowering::Custom) { 1818 // Expand the subcomponents. 1819 SDValue LHSL, LHSH; 1820 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1821 1822 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1823 EVT VT = LHSL.getValueType(); 1824 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3); 1825 Hi = Lo.getValue(1); 1826 return; 1827 } 1828 1829 // Otherwise, emit a libcall. 1830 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1831 bool isSigned; 1832 if (N->getOpcode() == ISD::SHL) { 1833 isSigned = false; /*sign irrelevant*/ 1834 if (VT == MVT::i16) 1835 LC = RTLIB::SHL_I16; 1836 else if (VT == MVT::i32) 1837 LC = RTLIB::SHL_I32; 1838 else if (VT == MVT::i64) 1839 LC = RTLIB::SHL_I64; 1840 else if (VT == MVT::i128) 1841 LC = RTLIB::SHL_I128; 1842 } else if (N->getOpcode() == ISD::SRL) { 1843 isSigned = false; 1844 if (VT == MVT::i16) 1845 LC = RTLIB::SRL_I16; 1846 else if (VT == MVT::i32) 1847 LC = RTLIB::SRL_I32; 1848 else if (VT == MVT::i64) 1849 LC = RTLIB::SRL_I64; 1850 else if (VT == MVT::i128) 1851 LC = RTLIB::SRL_I128; 1852 } else { 1853 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1854 isSigned = true; 1855 if (VT == MVT::i16) 1856 LC = RTLIB::SRA_I16; 1857 else if (VT == MVT::i32) 1858 LC = RTLIB::SRA_I32; 1859 else if (VT == MVT::i64) 1860 LC = RTLIB::SRA_I64; 1861 else if (VT == MVT::i128) 1862 LC = RTLIB::SRA_I128; 1863 } 1864 1865 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) { 1866 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1867 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi); 1868 return; 1869 } 1870 1871 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi)) 1872 llvm_unreachable("Unsupported shift!"); 1873} 1874 1875void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 1876 SDValue &Lo, SDValue &Hi) { 1877 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1878 DebugLoc dl = N->getDebugLoc(); 1879 SDValue Op = N->getOperand(0); 1880 if (Op.getValueType().bitsLE(NVT)) { 1881 // The low part is sign extension of the input (degenerates to a copy). 1882 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); 1883 // The high part is obtained by SRA'ing all but one of the bits of low part. 1884 unsigned LoSize = NVT.getSizeInBits(); 1885 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1886 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1887 } else { 1888 // For example, extension of an i48 to an i64. The operand type necessarily 1889 // promotes to the result type, so will end up being expanded too. 1890 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1891 "Only know how to promote this result!"); 1892 SDValue Res = GetPromotedInteger(Op); 1893 assert(Res.getValueType() == N->getValueType(0) && 1894 "Operand over promoted?"); 1895 // Split the promoted operand. This will simplify when it is expanded. 1896 SplitInteger(Res, Lo, Hi); 1897 unsigned ExcessBits = 1898 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1899 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 1900 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1901 ExcessBits))); 1902 } 1903} 1904 1905void DAGTypeLegalizer:: 1906ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 1907 DebugLoc dl = N->getDebugLoc(); 1908 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1909 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1910 1911 if (EVT.bitsLE(Lo.getValueType())) { 1912 // sext_inreg the low part if needed. 1913 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, 1914 N->getOperand(1)); 1915 1916 // The high part gets the sign extension from the lo-part. This handles 1917 // things like sextinreg V:i64 from i8. 1918 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, 1919 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 1920 TLI.getPointerTy())); 1921 } else { 1922 // For example, extension of an i48 to an i64. Leave the low part alone, 1923 // sext_inreg the high part. 1924 unsigned ExcessBits = 1925 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 1926 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 1927 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), ExcessBits))); 1928 } 1929} 1930 1931void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1932 SDValue &Lo, SDValue &Hi) { 1933 EVT VT = N->getValueType(0); 1934 DebugLoc dl = N->getDebugLoc(); 1935 1936 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1937 if (VT == MVT::i16) 1938 LC = RTLIB::SREM_I16; 1939 else if (VT == MVT::i32) 1940 LC = RTLIB::SREM_I32; 1941 else if (VT == MVT::i64) 1942 LC = RTLIB::SREM_I64; 1943 else if (VT == MVT::i128) 1944 LC = RTLIB::SREM_I128; 1945 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1946 1947 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1948 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1949} 1950 1951void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 1952 SDValue &Lo, SDValue &Hi) { 1953 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1954 DebugLoc dl = N->getDebugLoc(); 1955 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); 1956 Hi = DAG.getNode(ISD::SRL, dl, 1957 N->getOperand(0).getValueType(), N->getOperand(0), 1958 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy())); 1959 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); 1960} 1961 1962void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N, 1963 SDValue &Lo, SDValue &Hi) { 1964 SDValue LHS = N->getOperand(0); 1965 SDValue RHS = N->getOperand(1); 1966 DebugLoc dl = N->getDebugLoc(); 1967 1968 // Expand the result by simply replacing it with the equivalent 1969 // non-overflow-checking operation. 1970 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ? 1971 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 1972 LHS, RHS); 1973 SplitInteger(Sum, Lo, Hi); 1974 1975 // Calculate the overflow: addition overflows iff a + b < a, and subtraction 1976 // overflows iff a - b > a. 1977 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, 1978 N->getOpcode () == ISD::UADDO ? 1979 ISD::SETULT : ISD::SETUGT); 1980 1981 // Use the calculated overflow everywhere. 1982 ReplaceValueWith(SDValue(N, 1), Ofl); 1983} 1984 1985void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1986 SDValue &Lo, SDValue &Hi) { 1987 EVT VT = N->getValueType(0); 1988 DebugLoc dl = N->getDebugLoc(); 1989 1990 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1991 if (VT == MVT::i16) 1992 LC = RTLIB::UDIV_I16; 1993 else if (VT == MVT::i32) 1994 LC = RTLIB::UDIV_I32; 1995 else if (VT == MVT::i64) 1996 LC = RTLIB::UDIV_I64; 1997 else if (VT == MVT::i128) 1998 LC = RTLIB::UDIV_I128; 1999 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 2000 2001 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2002 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 2003} 2004 2005void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 2006 SDValue &Lo, SDValue &Hi) { 2007 EVT VT = N->getValueType(0); 2008 DebugLoc dl = N->getDebugLoc(); 2009 2010 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2011 if (VT == MVT::i16) 2012 LC = RTLIB::UREM_I16; 2013 else if (VT == MVT::i32) 2014 LC = RTLIB::UREM_I32; 2015 else if (VT == MVT::i64) 2016 LC = RTLIB::UREM_I64; 2017 else if (VT == MVT::i128) 2018 LC = RTLIB::UREM_I128; 2019 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 2020 2021 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2022 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 2023} 2024 2025void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 2026 SDValue &Lo, SDValue &Hi) { 2027 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2028 DebugLoc dl = N->getDebugLoc(); 2029 SDValue Op = N->getOperand(0); 2030 if (Op.getValueType().bitsLE(NVT)) { 2031 // The low part is zero extension of the input (degenerates to a copy). 2032 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); 2033 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 2034 } else { 2035 // For example, extension of an i48 to an i64. The operand type necessarily 2036 // promotes to the result type, so will end up being expanded too. 2037 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 2038 "Only know how to promote this result!"); 2039 SDValue Res = GetPromotedInteger(Op); 2040 assert(Res.getValueType() == N->getValueType(0) && 2041 "Operand over promoted?"); 2042 // Split the promoted operand. This will simplify when it is expanded. 2043 SplitInteger(Res, Lo, Hi); 2044 unsigned ExcessBits = 2045 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 2046 Hi = DAG.getZeroExtendInReg(Hi, dl, 2047 EVT::getIntegerVT(*DAG.getContext(), ExcessBits)); 2048 } 2049} 2050 2051 2052//===----------------------------------------------------------------------===// 2053// Integer Operand Expansion 2054//===----------------------------------------------------------------------===// 2055 2056/// ExpandIntegerOperand - This method is called when the specified operand of 2057/// the specified node is found to need expansion. At this point, all of the 2058/// result types of the node are known to be legal, but other operands of the 2059/// node may need promotion or expansion as well as the specified one. 2060bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 2061 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n"); 2062 SDValue Res = SDValue(); 2063 2064 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 2065 return false; 2066 2067 switch (N->getOpcode()) { 2068 default: 2069 #ifndef NDEBUG 2070 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": "; 2071 N->dump(&DAG); dbgs() << "\n"; 2072 #endif 2073 llvm_unreachable("Do not know how to expand this operator's operand!"); 2074 2075 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 2076 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 2077 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 2078 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 2079 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 2080 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; 2081 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 2082 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 2083 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 2084 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break; 2085 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 2086 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 2087 2088 case ISD::SHL: 2089 case ISD::SRA: 2090 case ISD::SRL: 2091 case ISD::ROTL: 2092 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break; 2093 case ISD::RETURNADDR: 2094 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break; 2095 } 2096 2097 // If the result is null, the sub-method took care of registering results etc. 2098 if (!Res.getNode()) return false; 2099 2100 // If the result is N, the sub-method updated N in place. Tell the legalizer 2101 // core about this. 2102 if (Res.getNode() == N) 2103 return true; 2104 2105 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2106 "Invalid operand expansion"); 2107 2108 ReplaceValueWith(SDValue(N, 0), Res); 2109 return false; 2110} 2111 2112/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 2113/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 2114void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 2115 SDValue &NewRHS, 2116 ISD::CondCode &CCCode, 2117 DebugLoc dl) { 2118 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 2119 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 2120 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 2121 2122 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 2123 if (RHSLo == RHSHi) { 2124 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 2125 if (RHSCST->isAllOnesValue()) { 2126 // Equality comparison to -1. 2127 NewLHS = DAG.getNode(ISD::AND, dl, 2128 LHSLo.getValueType(), LHSLo, LHSHi); 2129 NewRHS = RHSLo; 2130 return; 2131 } 2132 } 2133 } 2134 2135 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 2136 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 2137 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS); 2138 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2139 return; 2140 } 2141 2142 // If this is a comparison of the sign bit, just look at the top part. 2143 // X > -1, x < 0 2144 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 2145 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 2146 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 2147 NewLHS = LHSHi; 2148 NewRHS = RHSHi; 2149 return; 2150 } 2151 2152 // FIXME: This generated code sucks. 2153 ISD::CondCode LowCC; 2154 switch (CCCode) { 2155 default: llvm_unreachable("Unknown integer setcc!"); 2156 case ISD::SETLT: 2157 case ISD::SETULT: LowCC = ISD::SETULT; break; 2158 case ISD::SETGT: 2159 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2160 case ISD::SETLE: 2161 case ISD::SETULE: LowCC = ISD::SETULE; break; 2162 case ISD::SETGE: 2163 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2164 } 2165 2166 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2167 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2168 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2169 2170 // NOTE: on targets without efficient SELECT of bools, we can always use 2171 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2172 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL); 2173 SDValue Tmp1, Tmp2; 2174 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), 2175 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl); 2176 if (!Tmp1.getNode()) 2177 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 2178 LHSLo, RHSLo, LowCC); 2179 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2180 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl); 2181 if (!Tmp2.getNode()) 2182 Tmp2 = DAG.getNode(ISD::SETCC, dl, 2183 TLI.getSetCCResultType(LHSHi.getValueType()), 2184 LHSHi, RHSHi, DAG.getCondCode(CCCode)); 2185 2186 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2187 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2188 if ((Tmp1C && Tmp1C->isNullValue()) || 2189 (Tmp2C && Tmp2C->isNullValue() && 2190 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2191 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2192 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2193 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2194 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2195 // low part is known false, returns high part. 2196 // For LE / GE, if high part is known false, ignore the low part. 2197 // For LT / GT, if high part is known true, ignore the low part. 2198 NewLHS = Tmp2; 2199 NewRHS = SDValue(); 2200 return; 2201 } 2202 2203 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2204 LHSHi, RHSHi, ISD::SETEQ, false, 2205 DagCombineInfo, dl); 2206 if (!NewLHS.getNode()) 2207 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 2208 LHSHi, RHSHi, ISD::SETEQ); 2209 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), 2210 NewLHS, Tmp1, Tmp2); 2211 NewRHS = SDValue(); 2212} 2213 2214SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2215 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2216 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2217 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2218 2219 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2220 // against zero to select between true and false values. 2221 if (NewRHS.getNode() == 0) { 2222 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2223 CCCode = ISD::SETNE; 2224 } 2225 2226 // Update N to have the operands specified. 2227 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 2228 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2229 N->getOperand(4)); 2230} 2231 2232SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2233 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2234 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2235 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2236 2237 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2238 // against zero to select between true and false values. 2239 if (NewRHS.getNode() == 0) { 2240 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2241 CCCode = ISD::SETNE; 2242 } 2243 2244 // Update N to have the operands specified. 2245 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2246 N->getOperand(2), N->getOperand(3), 2247 DAG.getCondCode(CCCode)); 2248} 2249 2250SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2251 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2252 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2253 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2254 2255 // If ExpandSetCCOperands returned a scalar, use it. 2256 if (NewRHS.getNode() == 0) { 2257 assert(NewLHS.getValueType() == N->getValueType(0) && 2258 "Unexpected setcc expansion!"); 2259 return NewLHS; 2260 } 2261 2262 // Otherwise, update N to have the operands specified. 2263 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2264 DAG.getCondCode(CCCode)); 2265} 2266 2267SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) { 2268 // The value being shifted is legal, but the shift amount is too big. 2269 // It follows that either the result of the shift is undefined, or the 2270 // upper half of the shift amount is zero. Just use the lower half. 2271 SDValue Lo, Hi; 2272 GetExpandedInteger(N->getOperand(1), Lo, Hi); 2273 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo); 2274} 2275 2276SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) { 2277 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This 2278 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this 2279 // constant to valid type. 2280 SDValue Lo, Hi; 2281 GetExpandedInteger(N->getOperand(0), Lo, Hi); 2282 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo); 2283} 2284 2285SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2286 SDValue Op = N->getOperand(0); 2287 EVT DstVT = N->getValueType(0); 2288 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2289 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2290 "Don't know how to expand this SINT_TO_FP!"); 2291 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc()); 2292} 2293 2294SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2295 if (ISD::isNormalStore(N)) 2296 return ExpandOp_NormalStore(N, OpNo); 2297 2298 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2299 assert(OpNo == 1 && "Can only expand the stored value so far"); 2300 2301 EVT VT = N->getOperand(1).getValueType(); 2302 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2303 SDValue Ch = N->getChain(); 2304 SDValue Ptr = N->getBasePtr(); 2305 int SVOffset = N->getSrcValueOffset(); 2306 unsigned Alignment = N->getAlignment(); 2307 bool isVolatile = N->isVolatile(); 2308 bool isNonTemporal = N->isNonTemporal(); 2309 DebugLoc dl = N->getDebugLoc(); 2310 SDValue Lo, Hi; 2311 2312 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2313 2314 if (N->getMemoryVT().bitsLE(NVT)) { 2315 GetExpandedInteger(N->getValue(), Lo, Hi); 2316 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, 2317 N->getMemoryVT(), isVolatile, isNonTemporal, 2318 Alignment); 2319 } else if (TLI.isLittleEndian()) { 2320 // Little-endian - low bits are at low addresses. 2321 GetExpandedInteger(N->getValue(), Lo, Hi); 2322 2323 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset, 2324 isVolatile, isNonTemporal, Alignment); 2325 2326 unsigned ExcessBits = 2327 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2328 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits); 2329 2330 // Increment the pointer to the other half. 2331 unsigned IncrementSize = NVT.getSizeInBits()/8; 2332 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2333 DAG.getIntPtrConstant(IncrementSize)); 2334 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), 2335 SVOffset+IncrementSize, NEVT, 2336 isVolatile, isNonTemporal, 2337 MinAlign(Alignment, IncrementSize)); 2338 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2339 } else { 2340 // Big-endian - high bits are at low addresses. Favor aligned stores at 2341 // the cost of some bit-fiddling. 2342 GetExpandedInteger(N->getValue(), Lo, Hi); 2343 2344 EVT ExtVT = N->getMemoryVT(); 2345 unsigned EBytes = ExtVT.getStoreSize(); 2346 unsigned IncrementSize = NVT.getSizeInBits()/8; 2347 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2348 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(), 2349 ExtVT.getSizeInBits() - ExcessBits); 2350 2351 if (ExcessBits < NVT.getSizeInBits()) { 2352 // Transfer high bits from the top of Lo to the bottom of Hi. 2353 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, 2354 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2355 TLI.getPointerTy())); 2356 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, 2357 DAG.getNode(ISD::SRL, dl, NVT, Lo, 2358 DAG.getConstant(ExcessBits, 2359 TLI.getPointerTy()))); 2360 } 2361 2362 // Store both the high bits and maybe some of the low bits. 2363 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), 2364 SVOffset, HiVT, isVolatile, isNonTemporal, 2365 Alignment); 2366 2367 // Increment the pointer to the other half. 2368 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2369 DAG.getIntPtrConstant(IncrementSize)); 2370 // Store the lowest ExcessBits bits in the second half. 2371 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), 2372 SVOffset+IncrementSize, 2373 EVT::getIntegerVT(*DAG.getContext(), ExcessBits), 2374 isVolatile, isNonTemporal, 2375 MinAlign(Alignment, IncrementSize)); 2376 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2377 } 2378} 2379 2380SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2381 SDValue InL, InH; 2382 GetExpandedInteger(N->getOperand(0), InL, InH); 2383 // Just truncate the low part of the source. 2384 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL); 2385} 2386 2387static const fltSemantics *EVTToAPFloatSemantics(EVT VT) { 2388 switch (VT.getSimpleVT().SimpleTy) { 2389 default: llvm_unreachable("Unknown FP format"); 2390 case MVT::f32: return &APFloat::IEEEsingle; 2391 case MVT::f64: return &APFloat::IEEEdouble; 2392 case MVT::f80: return &APFloat::x87DoubleExtended; 2393 case MVT::f128: return &APFloat::IEEEquad; 2394 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 2395 } 2396} 2397 2398SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2399 SDValue Op = N->getOperand(0); 2400 EVT SrcVT = Op.getValueType(); 2401 EVT DstVT = N->getValueType(0); 2402 DebugLoc dl = N->getDebugLoc(); 2403 2404 // The following optimization is valid only if every value in SrcVT (when 2405 // treated as signed) is representable in DstVT. Check that the mantissa 2406 // size of DstVT is >= than the number of bits in SrcVT -1. 2407 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT); 2408 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 && 2409 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2410 // Do a signed conversion then adjust the result. 2411 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); 2412 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2413 2414 // The result of the signed conversion needs adjusting if the 'sign bit' of 2415 // the incoming integer was set. To handle this, we dynamically test to see 2416 // if it is set, and, if so, add a fudge factor. 2417 2418 const uint64_t F32TwoE32 = 0x4F800000ULL; 2419 const uint64_t F32TwoE64 = 0x5F800000ULL; 2420 const uint64_t F32TwoE128 = 0x7F800000ULL; 2421 2422 APInt FF(32, 0); 2423 if (SrcVT == MVT::i32) 2424 FF = APInt(32, F32TwoE32); 2425 else if (SrcVT == MVT::i64) 2426 FF = APInt(32, F32TwoE64); 2427 else if (SrcVT == MVT::i128) 2428 FF = APInt(32, F32TwoE128); 2429 else 2430 assert(false && "Unsupported UINT_TO_FP!"); 2431 2432 // Check whether the sign bit is set. 2433 SDValue Lo, Hi; 2434 GetExpandedInteger(Op, Lo, Hi); 2435 SDValue SignSet = DAG.getSetCC(dl, 2436 TLI.getSetCCResultType(Hi.getValueType()), 2437 Hi, DAG.getConstant(0, Hi.getValueType()), 2438 ISD::SETLT); 2439 2440 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2441 SDValue FudgePtr = DAG.getConstantPool( 2442 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 2443 TLI.getPointerTy()); 2444 2445 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2446 SDValue Zero = DAG.getIntPtrConstant(0); 2447 SDValue Four = DAG.getIntPtrConstant(4); 2448 if (TLI.isBigEndian()) std::swap(Zero, Four); 2449 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 2450 Zero, Four); 2451 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2452 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset); 2453 Alignment = std::min(Alignment, 4u); 2454 2455 // Load the value out, extending it from f32 to the destination float type. 2456 // FIXME: Avoid the extend by constructing the right constant pool? 2457 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), 2458 FudgePtr, NULL, 0, MVT::f32, 2459 false, false, Alignment); 2460 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); 2461 } 2462 2463 // Otherwise, use a libcall. 2464 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2465 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2466 "Don't know how to expand this UINT_TO_FP!"); 2467 return MakeLibCall(LC, DstVT, &Op, 1, true, dl); 2468} 2469