LegalizeIntegerTypes.cpp revision 2db81e0008fac6b3e715de44ed2cdd7e05cf97ed
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22using namespace llvm; 23 24//===----------------------------------------------------------------------===// 25// Integer Result Promotion 26//===----------------------------------------------------------------------===// 27 28/// PromoteIntegerResult - This method is called when a result of a node is 29/// found to be in need of promotion to a larger type. At this point, the node 30/// may also have invalid operands or may have other results that need 31/// expansion, we just know that (at least) one result needs promotion. 32void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); 34 SDValue Result = SDValue(); 35 36 // See if the target wants to custom expand this node. 37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 38 TargetLowering::Custom) { 39 // If the target wants to, allow it to lower this itself. 40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 41 // Everything that once used N now uses P. We are guaranteed that the 42 // result value types of N and the result value types of P match. 43 ReplaceNodeWith(N, P); 44 return; 45 } 46 } 47 48 switch (N->getOpcode()) { 49 default: 50#ifndef NDEBUG 51 cerr << "PromoteIntegerResult #" << ResNo << ": "; 52 N->dump(&DAG); cerr << "\n"; 53#endif 54 assert(0 && "Do not know how to promote this operator!"); 55 abort(); 56 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break; 57 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break; 58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break; 59 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break; 60 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break; 61 case ISD::Constant: Result = PromoteIntRes_Constant(N); break; 62 case ISD::CONVERT_RNDSAT: 63 Result = PromoteIntRes_CONVERT_RNDSAT(N); break; 64 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break; 65 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break; 66 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break; 67 case ISD::EXTRACT_VECTOR_ELT: 68 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 69 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 70 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break; 71 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break; 72 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break; 73 case ISD::SHL: Result = PromoteIntRes_SHL(N); break; 74 case ISD::SIGN_EXTEND_INREG: 75 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 76 case ISD::SRA: Result = PromoteIntRes_SRA(N); break; 77 case ISD::SRL: Result = PromoteIntRes_SRL(N); break; 78 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break; 79 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break; 80 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break; 81 82 case ISD::SIGN_EXTEND: 83 case ISD::ZERO_EXTEND: 84 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break; 85 86 case ISD::FP_TO_SINT: 87 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break; 88 89 case ISD::AND: 90 case ISD::OR: 91 case ISD::XOR: 92 case ISD::ADD: 93 case ISD::SUB: 94 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break; 95 96 case ISD::SDIV: 97 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break; 98 99 case ISD::UDIV: 100 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break; 101 102 case ISD::ATOMIC_LOAD_ADD_8: 103 case ISD::ATOMIC_LOAD_SUB_8: 104 case ISD::ATOMIC_LOAD_AND_8: 105 case ISD::ATOMIC_LOAD_OR_8: 106 case ISD::ATOMIC_LOAD_XOR_8: 107 case ISD::ATOMIC_LOAD_NAND_8: 108 case ISD::ATOMIC_LOAD_MIN_8: 109 case ISD::ATOMIC_LOAD_MAX_8: 110 case ISD::ATOMIC_LOAD_UMIN_8: 111 case ISD::ATOMIC_LOAD_UMAX_8: 112 case ISD::ATOMIC_SWAP_8: 113 case ISD::ATOMIC_LOAD_ADD_16: 114 case ISD::ATOMIC_LOAD_SUB_16: 115 case ISD::ATOMIC_LOAD_AND_16: 116 case ISD::ATOMIC_LOAD_OR_16: 117 case ISD::ATOMIC_LOAD_XOR_16: 118 case ISD::ATOMIC_LOAD_NAND_16: 119 case ISD::ATOMIC_LOAD_MIN_16: 120 case ISD::ATOMIC_LOAD_MAX_16: 121 case ISD::ATOMIC_LOAD_UMIN_16: 122 case ISD::ATOMIC_LOAD_UMAX_16: 123 case ISD::ATOMIC_SWAP_16: 124 case ISD::ATOMIC_LOAD_ADD_32: 125 case ISD::ATOMIC_LOAD_SUB_32: 126 case ISD::ATOMIC_LOAD_AND_32: 127 case ISD::ATOMIC_LOAD_OR_32: 128 case ISD::ATOMIC_LOAD_XOR_32: 129 case ISD::ATOMIC_LOAD_NAND_32: 130 case ISD::ATOMIC_LOAD_MIN_32: 131 case ISD::ATOMIC_LOAD_MAX_32: 132 case ISD::ATOMIC_LOAD_UMIN_32: 133 case ISD::ATOMIC_LOAD_UMAX_32: 134 case ISD::ATOMIC_SWAP_32: 135 case ISD::ATOMIC_LOAD_ADD_64: 136 case ISD::ATOMIC_LOAD_SUB_64: 137 case ISD::ATOMIC_LOAD_AND_64: 138 case ISD::ATOMIC_LOAD_OR_64: 139 case ISD::ATOMIC_LOAD_XOR_64: 140 case ISD::ATOMIC_LOAD_NAND_64: 141 case ISD::ATOMIC_LOAD_MIN_64: 142 case ISD::ATOMIC_LOAD_MAX_64: 143 case ISD::ATOMIC_LOAD_UMIN_64: 144 case ISD::ATOMIC_LOAD_UMAX_64: 145 case ISD::ATOMIC_SWAP_64: 146 Result = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 147 148 case ISD::ATOMIC_CMP_SWAP_8: 149 case ISD::ATOMIC_CMP_SWAP_16: 150 case ISD::ATOMIC_CMP_SWAP_32: 151 case ISD::ATOMIC_CMP_SWAP_64: 152 Result = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 153 } 154 155 // If Result is null, the sub-method took care of registering the result. 156 if (Result.getNode()) 157 SetPromotedInteger(SDValue(N, ResNo), Result); 158} 159 160SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 161 // Sign-extend the new bits, and continue the assertion. 162 MVT OldVT = N->getValueType(0); 163 SDValue Op = GetPromotedInteger(N->getOperand(0)); 164 return DAG.getNode(ISD::AssertSext, Op.getValueType(), 165 DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, 166 DAG.getValueType(OldVT)), N->getOperand(1)); 167} 168 169SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 170 // Zero the new bits, and continue the assertion. 171 MVT OldVT = N->getValueType(0); 172 SDValue Op = GetPromotedInteger(N->getOperand(0)); 173 return DAG.getNode(ISD::AssertZext, Op.getValueType(), 174 DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1)); 175} 176 177SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 178 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 179 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(), 180 Op2, N->getSrcValue(), N->getAlignment()); 181 // Legalized the chain result - switch anything that used the old chain to 182 // use the new one. 183 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 184 return Res; 185} 186 187SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 188 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 189 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 190 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(), 191 Op2, Op3, N->getSrcValue(), N->getAlignment()); 192 // Legalized the chain result - switch anything that used the old chain to 193 // use the new one. 194 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 195 return Res; 196} 197 198SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 199 SDValue InOp = N->getOperand(0); 200 MVT InVT = InOp.getValueType(); 201 MVT NInVT = TLI.getTypeToTransformTo(InVT); 202 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 203 204 switch (getTypeAction(InVT)) { 205 default: 206 assert(false && "Unknown type action!"); 207 break; 208 case Legal: 209 break; 210 case PromoteInteger: 211 if (OutVT.bitsEq(NInVT)) 212 // The input promotes to the same size. Convert the promoted value. 213 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp)); 214 break; 215 case SoftenFloat: 216 // Promote the integer operand by hand. 217 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp)); 218 case ExpandInteger: 219 case ExpandFloat: 220 break; 221 case ScalarizeVector: 222 // Convert the element to an integer and promote it by hand. 223 return DAG.getNode(ISD::ANY_EXTEND, OutVT, 224 BitConvertToInteger(GetScalarizedVector(InOp))); 225 case SplitVector: 226 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 227 // pieces of the input into integers and reassemble in the final type. 228 SDValue Lo, Hi; 229 GetSplitVector(N->getOperand(0), Lo, Hi); 230 Lo = BitConvertToInteger(Lo); 231 Hi = BitConvertToInteger(Hi); 232 233 if (TLI.isBigEndian()) 234 std::swap(Lo, Hi); 235 236 InOp = DAG.getNode(ISD::ANY_EXTEND, 237 MVT::getIntegerVT(OutVT.getSizeInBits()), 238 JoinIntegers(Lo, Hi)); 239 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp); 240 } 241 242 // Otherwise, lower the bit-convert to a store/load from the stack, then 243 // promote the load. 244 SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0)); 245 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode())); 246} 247 248SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 249 SDValue Op = GetPromotedInteger(N->getOperand(0)); 250 MVT OVT = N->getValueType(0); 251 MVT NVT = Op.getValueType(); 252 253 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 254 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op), 255 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 256} 257 258SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 259 // The pair element type may be legal, or may not promote to the same type as 260 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 261 return DAG.getNode(ISD::ANY_EXTEND, 262 TLI.getTypeToTransformTo(N->getValueType(0)), 263 JoinIntegers(N->getOperand(0), N->getOperand(1))); 264} 265 266SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 267 MVT VT = N->getValueType(0); 268 // Zero extend things like i1, sign extend everything else. It shouldn't 269 // matter in theory which one we pick, but this tends to give better code? 270 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 271 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), 272 SDValue(N, 0)); 273 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 274 return Result; 275} 276 277SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 278 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 279 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 280 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 281 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 282 "can only promote integers"); 283 SDValue InOp = N->getOperand(0); 284 285 MVT InVT = InOp.getValueType(); 286 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 287 switch (getTypeAction(InVT)) { 288 default: 289 assert(false && "Unknown type action!"); 290 break; 291 case Legal: 292 break; 293 case PromoteInteger: 294 return DAG.getConvertRndSat(OutVT, GetPromotedInteger(InOp), 295 N->getOperand(1), N->getOperand(2), 296 N->getOperand(3), N->getOperand(4), CvtCode); 297 break; 298 case SoftenFloat: 299 case ExpandInteger: 300 case ExpandFloat: 301 break; 302 case ScalarizeVector: 303 case SplitVector: 304 assert(false && "can not convert a vector to a scalar!"); 305 } 306 return DAG.getConvertRndSat(OutVT, InOp, 307 N->getOperand(1), N->getOperand(2), 308 N->getOperand(3), N->getOperand(4), CvtCode); 309} 310 311 312SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 313 SDValue Op = GetPromotedInteger(N->getOperand(0)); 314 MVT OVT = N->getValueType(0); 315 MVT NVT = Op.getValueType(); 316 // Zero extend to the promoted type and do the count there. 317 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT)); 318 // Subtract off the extra leading bits in the bigger type. 319 return DAG.getNode(ISD::SUB, NVT, Op, 320 DAG.getConstant(NVT.getSizeInBits() - 321 OVT.getSizeInBits(), NVT)); 322} 323 324SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 325 SDValue Op = GetPromotedInteger(N->getOperand(0)); 326 MVT OVT = N->getValueType(0); 327 MVT NVT = Op.getValueType(); 328 // Zero extend to the promoted type and do the count there. 329 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT)); 330} 331 332SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 333 SDValue Op = GetPromotedInteger(N->getOperand(0)); 334 MVT OVT = N->getValueType(0); 335 MVT NVT = Op.getValueType(); 336 // The count is the same in the promoted type except if the original 337 // value was zero. This can be handled by setting the bit just off 338 // the top of the original type. 339 APInt TopBit(NVT.getSizeInBits(), 0); 340 TopBit.set(OVT.getSizeInBits()); 341 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT)); 342 return DAG.getNode(ISD::CTTZ, NVT, Op); 343} 344 345SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 346 MVT OldVT = N->getValueType(0); 347 SDValue OldVec = N->getOperand(0); 348 unsigned OldElts = OldVec.getValueType().getVectorNumElements(); 349 350 if (OldElts == 1) { 351 assert(!isTypeLegal(OldVec.getValueType()) && 352 "Legal one-element vector of a type needing promotion!"); 353 // It is tempting to follow GetScalarizedVector by a call to 354 // GetPromotedInteger, but this would be wrong because the 355 // scalarized value may not yet have been processed. 356 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), 357 GetScalarizedVector(OldVec)); 358 } 359 360 // Convert to a vector half as long with an element type of twice the width, 361 // for example <4 x i16> -> <2 x i32>. 362 assert(!(OldElts & 1) && "Odd length vectors not supported!"); 363 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 364 assert(OldVT.isSimple() && NewVT.isSimple()); 365 366 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, 367 MVT::getVectorVT(NewVT, OldElts / 2), 368 OldVec); 369 370 // Extract the element at OldIdx / 2 from the new vector. 371 SDValue OldIdx = N->getOperand(1); 372 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx, 373 DAG.getConstant(1, TLI.getShiftAmountTy())); 374 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx); 375 376 // Select the appropriate half of the element: Lo if OldIdx was even, 377 // Hi if it was odd. 378 SDValue Lo = Elt; 379 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt, 380 DAG.getConstant(OldVT.getSizeInBits(), 381 TLI.getShiftAmountTy())); 382 if (TLI.isBigEndian()) 383 std::swap(Lo, Hi); 384 385 SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx); 386 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo); 387} 388 389SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 390 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 391 unsigned NewOpc = N->getOpcode(); 392 393 // If we're promoting a UINT to a larger size, check to see if the new node 394 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 395 // we can use that instead. This allows us to generate better code for 396 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 397 // legal, such as PowerPC. 398 if (N->getOpcode() == ISD::FP_TO_UINT && 399 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 400 TLI.isOperationLegal(ISD::FP_TO_SINT, NVT)) 401 NewOpc = ISD::FP_TO_SINT; 402 403 SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0)); 404 405 // Assert that the converted value fits in the original type. If it doesn't 406 // (eg: because the value being converted is too big), then the result of the 407 // original operation was undefined anyway, so the assert is still correct. 408 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 409 ISD::AssertZext : ISD::AssertSext, 410 NVT, Res, DAG.getValueType(N->getValueType(0))); 411} 412 413SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 414 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 415 416 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 417 SDValue Res = GetPromotedInteger(N->getOperand(0)); 418 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 419 420 // If the result and operand types are the same after promotion, simplify 421 // to an in-register extension. 422 if (NVT == Res.getValueType()) { 423 // The high bits are not guaranteed to be anything. Insert an extend. 424 if (N->getOpcode() == ISD::SIGN_EXTEND) 425 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, 426 DAG.getValueType(N->getOperand(0).getValueType())); 427 if (N->getOpcode() == ISD::ZERO_EXTEND) 428 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); 429 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 430 return Res; 431 } 432 } 433 434 // Otherwise, just extend the original operand all the way to the larger type. 435 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0)); 436} 437 438SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 439 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 440 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 441 ISD::LoadExtType ExtType = 442 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 443 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(), 444 N->getSrcValue(), N->getSrcValueOffset(), 445 N->getMemoryVT(), N->isVolatile(), 446 N->getAlignment()); 447 448 // Legalized the chain result - switch anything that used the old chain to 449 // use the new one. 450 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 451 return Res; 452} 453 454SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 455 // Sign extend the input. 456 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 457 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 458 MVT VT = N->getValueType(0); 459 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS, 460 DAG.getValueType(VT)); 461 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS, 462 DAG.getValueType(VT)); 463 464 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 465} 466 467SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 468 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 469 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 470 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS); 471} 472 473SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 474 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 475 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 476 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0), 477 N->getOperand(1), LHS, RHS, N->getOperand(4)); 478} 479 480SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 481 MVT SVT = TLI.getSetCCResultType(N->getOperand(0)); 482 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 483 484 // Get the SETCC result using the canonical SETCC type. 485 SDValue SetCC = DAG.getNode(ISD::SETCC, SVT, N->getOperand(0), 486 N->getOperand(1), N->getOperand(2)); 487 488 // Convert to the expected type. 489 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 490 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 491 return DAG.getNode(ISD::TRUNCATE, NVT, SetCC); 492} 493 494SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 495 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)), 496 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 497} 498 499SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 500 SDValue Op = GetPromotedInteger(N->getOperand(0)); 501 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, 502 N->getOperand(1)); 503} 504 505SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 506 // The input may have strange things in the top bits of the registers, but 507 // these operations don't care. They may have weird bits going out, but 508 // that too is okay if they are integer operations. 509 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 510 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 511 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 512} 513 514SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 515 // The input value must be properly sign extended. 516 MVT VT = N->getValueType(0); 517 MVT NVT = TLI.getTypeToTransformTo(VT); 518 SDValue Res = GetPromotedInteger(N->getOperand(0)); 519 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT)); 520 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1)); 521} 522 523SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 524 // The input value must be properly zero extended. 525 MVT VT = N->getValueType(0); 526 MVT NVT = TLI.getTypeToTransformTo(VT); 527 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 528 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1)); 529} 530 531SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 532 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 533 SDValue Res; 534 535 switch (getTypeAction(N->getOperand(0).getValueType())) { 536 default: assert(0 && "Unknown type action!"); 537 case Legal: 538 case ExpandInteger: 539 Res = N->getOperand(0); 540 break; 541 case PromoteInteger: 542 Res = GetPromotedInteger(N->getOperand(0)); 543 break; 544 } 545 546 // Truncate to NVT instead of VT 547 return DAG.getNode(ISD::TRUNCATE, NVT, Res); 548} 549 550SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 551 // Zero extend the input. 552 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 553 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 554 MVT VT = N->getValueType(0); 555 LHS = DAG.getZeroExtendInReg(LHS, VT); 556 RHS = DAG.getZeroExtendInReg(RHS, VT); 557 558 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 559} 560 561SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 562 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0))); 563} 564 565SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 566 SDValue Chain = N->getOperand(0); // Get the chain. 567 SDValue Ptr = N->getOperand(1); // Get the pointer. 568 MVT VT = N->getValueType(0); 569 570 MVT RegVT = TLI.getRegisterType(VT); 571 unsigned NumRegs = TLI.getNumRegisters(VT); 572 // The argument is passed as NumRegs registers of type RegVT. 573 574 SmallVector<SDValue, 8> Parts(NumRegs); 575 for (unsigned i = 0; i < NumRegs; ++i) { 576 Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2)); 577 Chain = Parts[i].getValue(1); 578 } 579 580 // Handle endianness of the load. 581 if (TLI.isBigEndian()) 582 std::reverse(Parts.begin(), Parts.end()); 583 584 // Assemble the parts in the promoted type. 585 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 586 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[0]); 587 for (unsigned i = 1; i < NumRegs; ++i) { 588 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[i]); 589 // Shift it to the right position and "or" it in. 590 Part = DAG.getNode(ISD::SHL, NVT, Part, 591 DAG.getConstant(i * RegVT.getSizeInBits(), 592 TLI.getShiftAmountTy())); 593 Res = DAG.getNode(ISD::OR, NVT, Res, Part); 594 } 595 596 // Modified the chain result - switch anything that used the old chain to 597 // use the new one. 598 ReplaceValueWith(SDValue(N, 1), Chain); 599 600 return Res; 601} 602 603 604//===----------------------------------------------------------------------===// 605// Integer Operand Promotion 606//===----------------------------------------------------------------------===// 607 608/// PromoteIntegerOperand - This method is called when the specified operand of 609/// the specified node is found to need promotion. At this point, all of the 610/// result types of the node are known to be legal, but other operands of the 611/// node may need promotion or expansion as well as the specified one. 612bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 613 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); 614 SDValue Res = SDValue(); 615 616 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 617 == TargetLowering::Custom) 618 Res = TLI.LowerOperation(SDValue(N, 0), DAG); 619 620 if (Res.getNode() == 0) { 621 switch (N->getOpcode()) { 622 default: 623 #ifndef NDEBUG 624 cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; 625 N->dump(&DAG); cerr << "\n"; 626 #endif 627 assert(0 && "Do not know how to promote this operator's operand!"); 628 abort(); 629 630 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 631 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 632 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 633 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 634 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 635 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break; 636 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break; 637 case ISD::INSERT_VECTOR_ELT: 638 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 639 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 640 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 641 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 642 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 643 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 644 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 645 OpNo); break; 646 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 647 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 648 649 case ISD::SINT_TO_FP: 650 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break; 651 } 652 } 653 654 // If the result is null, the sub-method took care of registering results etc. 655 if (!Res.getNode()) return false; 656 // If the result is N, the sub-method updated N in place. 657 if (Res.getNode() == N) { 658 // Mark N as new and remark N and its operands. This allows us to correctly 659 // revisit N if it needs another step of promotion and allows us to visit 660 // any new operands to N. 661 ReanalyzeNode(N); 662 return true; 663 } 664 665 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 666 "Invalid operand expansion"); 667 668 ReplaceValueWith(SDValue(N, 0), Res); 669 return false; 670} 671 672/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 673/// shared among BR_CC, SELECT_CC, and SETCC handlers. 674void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 675 ISD::CondCode CCCode) { 676 MVT VT = NewLHS.getValueType(); 677 678 // Get the promoted values. 679 NewLHS = GetPromotedInteger(NewLHS); 680 NewRHS = GetPromotedInteger(NewRHS); 681 682 // We have to insert explicit sign or zero extends. Note that we could 683 // insert sign extends for ALL conditions, but zero extend is cheaper on 684 // many machines (an AND instead of two shifts), so prefer it. 685 switch (CCCode) { 686 default: assert(0 && "Unknown integer comparison!"); 687 case ISD::SETEQ: 688 case ISD::SETNE: 689 case ISD::SETUGE: 690 case ISD::SETUGT: 691 case ISD::SETULE: 692 case ISD::SETULT: 693 // ALL of these operations will work if we either sign or zero extend 694 // the operands (including the unsigned comparisons!). Zero extend is 695 // usually a simpler/cheaper operation, so prefer it. 696 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT); 697 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT); 698 break; 699 case ISD::SETGE: 700 case ISD::SETGT: 701 case ISD::SETLT: 702 case ISD::SETLE: 703 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS, 704 DAG.getValueType(VT)); 705 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS, 706 DAG.getValueType(VT)); 707 break; 708 } 709} 710 711SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 712 SDValue Op = GetPromotedInteger(N->getOperand(0)); 713 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 714} 715 716SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 717 assert(OpNo == 2 && "Don't know how to promote this operand!"); 718 719 SDValue LHS = N->getOperand(2); 720 SDValue RHS = N->getOperand(3); 721 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 722 723 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 724 // legal types. 725 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 726 N->getOperand(1), LHS, RHS, N->getOperand(4)); 727} 728 729SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 730 assert(OpNo == 1 && "only know how to promote condition"); 731 SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition. 732 733 // Make sure the extra bits coming from type promotion conform to 734 // getSetCCResultContents. 735 unsigned CondBits = Cond.getValueSizeInBits(); 736 switch (TLI.getSetCCResultContents()) { 737 default: 738 assert(false && "Unknown SetCCResultValue!"); 739 case TargetLowering::UndefinedSetCCResult: 740 // The promoted value, which may contain rubbish in the upper bits, is fine. 741 break; 742 case TargetLowering::ZeroOrOneSetCCResult: 743 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1))) 744 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); 745 break; 746 case TargetLowering::ZeroOrNegativeOneSetCCResult: 747 if (DAG.ComputeNumSignBits(Cond) != CondBits) 748 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond, 749 DAG.getValueType(MVT::i1)); 750 break; 751 } 752 753 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 754 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, 755 N->getOperand(2)); 756} 757 758SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 759 // Since the result type is legal, the operands must promote to it. 760 MVT OVT = N->getOperand(0).getValueType(); 761 SDValue Lo = GetPromotedInteger(N->getOperand(0)); 762 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 763 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 764 765 Lo = DAG.getZeroExtendInReg(Lo, OVT); 766 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi, 767 DAG.getConstant(OVT.getSizeInBits(), 768 TLI.getShiftAmountTy())); 769 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi); 770} 771 772SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 773 // The vector type is legal but the element type is not. This implies 774 // that the vector is a power-of-two in length and that the element 775 // type does not have a strange size (eg: it is not i1). 776 MVT VecVT = N->getValueType(0); 777 unsigned NumElts = VecVT.getVectorNumElements(); 778 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 779 780 // Build a vector of half the length out of elements of twice the bitwidth. 781 // For example <4 x i16> -> <2 x i32>. 782 MVT OldVT = N->getOperand(0).getValueType(); 783 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 784 assert(OldVT.isSimple() && NewVT.isSimple()); 785 786 std::vector<SDValue> NewElts; 787 NewElts.reserve(NumElts/2); 788 789 for (unsigned i = 0; i < NumElts; i += 2) { 790 // Combine two successive elements into one promoted element. 791 SDValue Lo = N->getOperand(i); 792 SDValue Hi = N->getOperand(i+1); 793 if (TLI.isBigEndian()) 794 std::swap(Lo, Hi); 795 NewElts.push_back(JoinIntegers(Lo, Hi)); 796 } 797 798 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, 799 MVT::getVectorVT(NewVT, NewElts.size()), 800 &NewElts[0], NewElts.size()); 801 802 // Convert the new vector to the old vector type. 803 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); 804} 805 806SDValue DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) { 807 SDValue Op = GetPromotedInteger(N->getOperand(0)); 808 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op); 809} 810 811SDValue DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) { 812 SDValue Op = GetPromotedInteger(N->getOperand(0)); 813 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op, 814 DAG.getIntPtrConstant(0)); 815} 816 817SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 818 unsigned OpNo) { 819 if (OpNo == 1) { 820 // Promote the inserted value. This is valid because the type does not 821 // have to match the vector element type. 822 823 // Check that any extra bits introduced will be truncated away. 824 assert(N->getOperand(1).getValueType().getSizeInBits() >= 825 N->getValueType(0).getVectorElementType().getSizeInBits() && 826 "Type of inserted value narrower than vector element type!"); 827 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 828 GetPromotedInteger(N->getOperand(1)), 829 N->getOperand(2)); 830 } 831 832 assert(OpNo == 2 && "Different operand and result vector types?"); 833 834 // Promote the index. 835 SDValue Idx = N->getOperand(2); 836 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType()); 837 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 838 N->getOperand(1), Idx); 839} 840 841SDValue DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) { 842 SDValue In = GetPromotedInteger(N->getOperand(0)); 843 MVT OpVT = N->getOperand(0).getValueType(); 844 if (N->getOpcode() == ISD::UINT_TO_FP) 845 In = DAG.getZeroExtendInReg(In, OpVT); 846 else 847 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), 848 In, DAG.getValueType(OpVT)); 849 850 return DAG.UpdateNodeOperands(SDValue(N, 0), In); 851} 852 853SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 854 SDValue NewOps[6]; 855 NewOps[0] = N->getOperand(0); 856 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 857 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 858 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); 859 } 860 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, 861 array_lengthof(NewOps)); 862} 863 864SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 865 assert(OpNo == 0 && "Only know how to promote condition"); 866 SDValue Cond = GetPromotedInteger(N->getOperand(0)); 867 868 // Promote all the way up to SVT, the canonical SetCC type. 869 // FIXME: Not clear what value to pass to getSetCCResultType. 870 // [This only matters for CellSPU since all other targets 871 // ignore the argument.] We used to pass Cond, resulting in 872 // SVT = MVT::i8, but CellSPU has no select patterns for i8, 873 // causing an abort later. Passing the result type works 874 // around the problem. 875 MVT SVT = TLI.getSetCCResultType(N->getOperand(1)); 876 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 877 assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!"); 878 879 // Make sure the extra bits conform to getSetCCResultContents. There are 880 // two sets of extra bits: those in Cond, which come from type promotion, 881 // and those we need to add to have the final type be SVT (for most targets 882 // this last set of bits is empty). 883 unsigned CondBits = Cond.getValueSizeInBits(); 884 ISD::NodeType ExtendCode; 885 switch (TLI.getSetCCResultContents()) { 886 default: 887 assert(false && "Unknown SetCCResultValue!"); 888 case TargetLowering::UndefinedSetCCResult: 889 // Extend to SVT by adding rubbish. 890 ExtendCode = ISD::ANY_EXTEND; 891 break; 892 case TargetLowering::ZeroOrOneSetCCResult: 893 ExtendCode = ISD::ZERO_EXTEND; 894 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1))) 895 // All extra bits need to be cleared. Do this by zero extending the 896 // original condition value all the way to SVT. 897 Cond = N->getOperand(0); 898 break; 899 case TargetLowering::ZeroOrNegativeOneSetCCResult: { 900 ExtendCode = ISD::SIGN_EXTEND; 901 unsigned SignBits = DAG.ComputeNumSignBits(Cond); 902 if (SignBits != CondBits) 903 // All extra bits need to be sign extended. Do this by sign extending the 904 // original condition value all the way to SVT. 905 Cond = N->getOperand(0); 906 break; 907 } 908 } 909 Cond = DAG.getNode(ExtendCode, SVT, Cond); 910 911 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, 912 N->getOperand(1), N->getOperand(2)); 913} 914 915SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 916 assert(OpNo == 0 && "Don't know how to promote this operand!"); 917 918 SDValue LHS = N->getOperand(0); 919 SDValue RHS = N->getOperand(1); 920 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 921 922 // The CC (#4) and the possible return values (#2 and #3) have legal types. 923 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2), 924 N->getOperand(3), N->getOperand(4)); 925} 926 927SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 928 assert(OpNo == 0 && "Don't know how to promote this operand!"); 929 930 SDValue LHS = N->getOperand(0); 931 SDValue RHS = N->getOperand(1); 932 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 933 934 // The CC (#2) is always legal. 935 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); 936} 937 938SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 939 SDValue Op = GetPromotedInteger(N->getOperand(0)); 940 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 941 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), 942 Op, DAG.getValueType(N->getOperand(0).getValueType())); 943} 944 945SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 946 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 947 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 948 int SVOffset = N->getSrcValueOffset(); 949 unsigned Alignment = N->getAlignment(); 950 bool isVolatile = N->isVolatile(); 951 952 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 953 954 assert(!N->isTruncatingStore() && "Cannot promote this store operand!"); 955 956 // Truncate the value and store the result. 957 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(), 958 SVOffset, N->getMemoryVT(), 959 isVolatile, Alignment); 960} 961 962SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 963 SDValue Op = GetPromotedInteger(N->getOperand(0)); 964 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op); 965} 966 967SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 968 SDValue Op = GetPromotedInteger(N->getOperand(0)); 969 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 970 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); 971} 972 973 974//===----------------------------------------------------------------------===// 975// Integer Result Expansion 976//===----------------------------------------------------------------------===// 977 978/// ExpandIntegerResult - This method is called when the specified result of the 979/// specified node is found to need expansion. At this point, the node may also 980/// have invalid operands or may have other results that need promotion, we just 981/// know that (at least) one result needs expansion. 982void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 983 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n"); 984 SDValue Lo, Hi; 985 Lo = Hi = SDValue(); 986 987 // See if the target wants to custom expand this node. 988 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 989 TargetLowering::Custom) { 990 // If the target wants to, allow it to lower this itself. 991 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 992 // Everything that once used N now uses P. We are guaranteed that the 993 // result value types of N and the result value types of P match. 994 ReplaceNodeWith(N, P); 995 return; 996 } 997 } 998 999 switch (N->getOpcode()) { 1000 default: 1001#ifndef NDEBUG 1002 cerr << "ExpandIntegerResult #" << ResNo << ": "; 1003 N->dump(&DAG); cerr << "\n"; 1004#endif 1005 assert(0 && "Do not know how to expand the result of this operator!"); 1006 abort(); 1007 1008 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 1009 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 1010 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 1011 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 1012 1013 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 1014 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 1015 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 1016 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 1017 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 1018 1019 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 1020 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 1021 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 1022 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 1023 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 1024 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 1025 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 1026 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 1027 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 1028 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 1029 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 1030 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 1031 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 1032 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 1033 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 1034 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 1035 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 1036 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 1037 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 1038 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 1039 1040 case ISD::AND: 1041 case ISD::OR: 1042 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 1043 1044 case ISD::ADD: 1045 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1046 1047 case ISD::ADDC: 1048 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1049 1050 case ISD::ADDE: 1051 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1052 1053 case ISD::SHL: 1054 case ISD::SRA: 1055 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1056 } 1057 1058 // If Lo/Hi is null, the sub-method took care of registering results etc. 1059 if (Lo.getNode()) 1060 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1061} 1062 1063/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1064/// and the shift amount is a constant 'Amt'. Expand the operation. 1065void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1066 SDValue &Lo, SDValue &Hi) { 1067 // Expand the incoming operand to be shifted, so that we have its parts 1068 SDValue InL, InH; 1069 GetExpandedInteger(N->getOperand(0), InL, InH); 1070 1071 MVT NVT = InL.getValueType(); 1072 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1073 unsigned NVTBits = NVT.getSizeInBits(); 1074 MVT ShTy = N->getOperand(1).getValueType(); 1075 1076 if (N->getOpcode() == ISD::SHL) { 1077 if (Amt > VTBits) { 1078 Lo = Hi = DAG.getConstant(0, NVT); 1079 } else if (Amt > NVTBits) { 1080 Lo = DAG.getConstant(0, NVT); 1081 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1082 } else if (Amt == NVTBits) { 1083 Lo = DAG.getConstant(0, NVT); 1084 Hi = InL; 1085 } else if (Amt == 1) { 1086 // Emit this X << 1 as X+X. 1087 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1088 SDValue LoOps[2] = { InL, InL }; 1089 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1090 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1091 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1092 } else { 1093 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1094 Hi = DAG.getNode(ISD::OR, NVT, 1095 DAG.getNode(ISD::SHL, NVT, InH, 1096 DAG.getConstant(Amt, ShTy)), 1097 DAG.getNode(ISD::SRL, NVT, InL, 1098 DAG.getConstant(NVTBits-Amt, ShTy))); 1099 } 1100 return; 1101 } 1102 1103 if (N->getOpcode() == ISD::SRL) { 1104 if (Amt > VTBits) { 1105 Lo = DAG.getConstant(0, NVT); 1106 Hi = DAG.getConstant(0, NVT); 1107 } else if (Amt > NVTBits) { 1108 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1109 Hi = DAG.getConstant(0, NVT); 1110 } else if (Amt == NVTBits) { 1111 Lo = InH; 1112 Hi = DAG.getConstant(0, NVT); 1113 } else { 1114 Lo = DAG.getNode(ISD::OR, NVT, 1115 DAG.getNode(ISD::SRL, NVT, InL, 1116 DAG.getConstant(Amt, ShTy)), 1117 DAG.getNode(ISD::SHL, NVT, InH, 1118 DAG.getConstant(NVTBits-Amt, ShTy))); 1119 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1120 } 1121 return; 1122 } 1123 1124 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1125 if (Amt > VTBits) { 1126 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 1127 DAG.getConstant(NVTBits-1, ShTy)); 1128 } else if (Amt > NVTBits) { 1129 Lo = DAG.getNode(ISD::SRA, NVT, InH, 1130 DAG.getConstant(Amt-NVTBits, ShTy)); 1131 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1132 DAG.getConstant(NVTBits-1, ShTy)); 1133 } else if (Amt == NVTBits) { 1134 Lo = InH; 1135 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1136 DAG.getConstant(NVTBits-1, ShTy)); 1137 } else { 1138 Lo = DAG.getNode(ISD::OR, NVT, 1139 DAG.getNode(ISD::SRL, NVT, InL, 1140 DAG.getConstant(Amt, ShTy)), 1141 DAG.getNode(ISD::SHL, NVT, InH, 1142 DAG.getConstant(NVTBits-Amt, ShTy))); 1143 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy)); 1144 } 1145} 1146 1147/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1148/// this shift based on knowledge of the high bit of the shift amount. If we 1149/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1150/// shift amount. 1151bool DAGTypeLegalizer:: 1152ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1153 SDValue Amt = N->getOperand(1); 1154 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1155 MVT ShTy = Amt.getValueType(); 1156 unsigned ShBits = ShTy.getSizeInBits(); 1157 unsigned NVTBits = NVT.getSizeInBits(); 1158 assert(isPowerOf2_32(NVTBits) && 1159 "Expanded integer type size not a power of two!"); 1160 1161 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1162 APInt KnownZero, KnownOne; 1163 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1164 1165 // If we don't know anything about the high bits, exit. 1166 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1167 return false; 1168 1169 // Get the incoming operand to be shifted. 1170 SDValue InL, InH; 1171 GetExpandedInteger(N->getOperand(0), InL, InH); 1172 1173 // If we know that any of the high bits of the shift amount are one, then we 1174 // can do this as a couple of simple shifts. 1175 if (KnownOne.intersects(HighBitMask)) { 1176 // Mask out the high bit, which we know is set. 1177 Amt = DAG.getNode(ISD::AND, ShTy, Amt, 1178 DAG.getConstant(~HighBitMask, ShTy)); 1179 1180 switch (N->getOpcode()) { 1181 default: assert(0 && "Unknown shift"); 1182 case ISD::SHL: 1183 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1184 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 1185 return true; 1186 case ISD::SRL: 1187 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1188 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 1189 return true; 1190 case ISD::SRA: 1191 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 1192 DAG.getConstant(NVTBits-1, ShTy)); 1193 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 1194 return true; 1195 } 1196 } 1197 1198 // If we know that all of the high bits of the shift amount are zero, then we 1199 // can do this as a couple of simple shifts. 1200 if ((KnownZero & HighBitMask) == HighBitMask) { 1201 // Compute 32-amt. 1202 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1203 DAG.getConstant(NVTBits, ShTy), 1204 Amt); 1205 unsigned Op1, Op2; 1206 switch (N->getOpcode()) { 1207 default: assert(0 && "Unknown shift"); 1208 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1209 case ISD::SRL: 1210 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1211 } 1212 1213 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1214 Hi = DAG.getNode(ISD::OR, NVT, 1215 DAG.getNode(Op1, NVT, InH, Amt), 1216 DAG.getNode(Op2, NVT, InL, Amt2)); 1217 return true; 1218 } 1219 1220 return false; 1221} 1222 1223void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1224 SDValue &Lo, SDValue &Hi) { 1225 // Expand the subcomponents. 1226 SDValue LHSL, LHSH, RHSL, RHSH; 1227 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1228 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1229 1230 MVT NVT = LHSL.getValueType(); 1231 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1232 SDValue LoOps[2] = { LHSL, RHSL }; 1233 SDValue HiOps[3] = { LHSH, RHSH }; 1234 1235 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1236 // them. TODO: Teach operation legalization how to expand unsupported 1237 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1238 // a carry of type MVT::Flag, but there doesn't seem to be any way to 1239 // generate a value of this type in the expanded code sequence. 1240 bool hasCarry = 1241 TLI.isOperationLegal(N->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC, 1242 TLI.getTypeToExpandTo(NVT)); 1243 1244 if (hasCarry) { 1245 if (N->getOpcode() == ISD::ADD) { 1246 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1247 HiOps[2] = Lo.getValue(1); 1248 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1249 } else { 1250 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1251 HiOps[2] = Lo.getValue(1); 1252 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1253 } 1254 } else { 1255 if (N->getOpcode() == ISD::ADD) { 1256 Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2); 1257 Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2); 1258 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0], 1259 ISD::SETULT); 1260 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, 1261 DAG.getConstant(1, NVT), 1262 DAG.getConstant(0, NVT)); 1263 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[1], 1264 ISD::SETULT); 1265 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2, 1266 DAG.getConstant(1, NVT), Carry1); 1267 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2); 1268 } else { 1269 Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2); 1270 Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2); 1271 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT); 1272 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp, 1273 DAG.getConstant(1, NVT), 1274 DAG.getConstant(0, NVT)); 1275 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow); 1276 } 1277 } 1278} 1279 1280void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1281 SDValue &Lo, SDValue &Hi) { 1282 // Expand the subcomponents. 1283 SDValue LHSL, LHSH, RHSL, RHSH; 1284 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1285 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1286 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1287 SDValue LoOps[2] = { LHSL, RHSL }; 1288 SDValue HiOps[3] = { LHSH, RHSH }; 1289 1290 if (N->getOpcode() == ISD::ADDC) { 1291 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1292 HiOps[2] = Lo.getValue(1); 1293 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1294 } else { 1295 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1296 HiOps[2] = Lo.getValue(1); 1297 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1298 } 1299 1300 // Legalized the flag result - switch anything that used the old flag to 1301 // use the new one. 1302 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1303} 1304 1305void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1306 SDValue &Lo, SDValue &Hi) { 1307 // Expand the subcomponents. 1308 SDValue LHSL, LHSH, RHSL, RHSH; 1309 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1310 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1311 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1312 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1313 SDValue HiOps[3] = { LHSH, RHSH }; 1314 1315 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3); 1316 HiOps[2] = Lo.getValue(1); 1317 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3); 1318 1319 // Legalized the flag result - switch anything that used the old flag to 1320 // use the new one. 1321 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1322} 1323 1324void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1325 SDValue &Lo, SDValue &Hi) { 1326 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1327 SDValue Op = N->getOperand(0); 1328 if (Op.getValueType().bitsLE(NVT)) { 1329 // The low part is any extension of the input (which degenerates to a copy). 1330 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op); 1331 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined. 1332 } else { 1333 // For example, extension of an i48 to an i64. The operand type necessarily 1334 // promotes to the result type, so will end up being expanded too. 1335 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1336 "Only know how to promote this result!"); 1337 SDValue Res = GetPromotedInteger(Op); 1338 assert(Res.getValueType() == N->getValueType(0) && 1339 "Operand over promoted?"); 1340 // Split the promoted operand. This will simplify when it is expanded. 1341 SplitInteger(Res, Lo, Hi); 1342 } 1343} 1344 1345void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1346 SDValue &Lo, SDValue &Hi) { 1347 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1348 MVT NVT = Lo.getValueType(); 1349 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1350 unsigned NVTBits = NVT.getSizeInBits(); 1351 unsigned EVTBits = EVT.getSizeInBits(); 1352 1353 if (NVTBits < EVTBits) { 1354 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi, 1355 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1356 } else { 1357 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT)); 1358 // The high part replicates the sign bit of Lo, make it explicit. 1359 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1360 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy())); 1361 } 1362} 1363 1364void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1365 SDValue &Lo, SDValue &Hi) { 1366 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1367 MVT NVT = Lo.getValueType(); 1368 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1369 unsigned NVTBits = NVT.getSizeInBits(); 1370 unsigned EVTBits = EVT.getSizeInBits(); 1371 1372 if (NVTBits < EVTBits) { 1373 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, 1374 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1375 } else { 1376 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); 1377 // The high part must be zero, make it explicit. 1378 Hi = DAG.getConstant(0, NVT); 1379 } 1380} 1381 1382void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1383 SDValue &Lo, SDValue &Hi) { 1384 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1385 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo); 1386 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi); 1387} 1388 1389void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1390 SDValue &Lo, SDValue &Hi) { 1391 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1392 unsigned NBitWidth = NVT.getSizeInBits(); 1393 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1394 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 1395 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1396} 1397 1398void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1399 SDValue &Lo, SDValue &Hi) { 1400 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1401 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1402 MVT NVT = Lo.getValueType(); 1403 1404 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 1405 DAG.getConstant(0, NVT), ISD::SETNE); 1406 1407 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo); 1408 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 1409 1410 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ, 1411 DAG.getNode(ISD::ADD, NVT, LoLZ, 1412 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1413 Hi = DAG.getConstant(0, NVT); 1414} 1415 1416void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1417 SDValue &Lo, SDValue &Hi) { 1418 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1419 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1420 MVT NVT = Lo.getValueType(); 1421 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), 1422 DAG.getNode(ISD::CTPOP, NVT, Hi)); 1423 Hi = DAG.getConstant(0, NVT); 1424} 1425 1426void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1427 SDValue &Lo, SDValue &Hi) { 1428 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1429 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1430 MVT NVT = Lo.getValueType(); 1431 1432 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, 1433 DAG.getConstant(0, NVT), ISD::SETNE); 1434 1435 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 1436 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi); 1437 1438 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ, 1439 DAG.getNode(ISD::ADD, NVT, HiLZ, 1440 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1441 Hi = DAG.getConstant(0, NVT); 1442} 1443 1444void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1445 SDValue &Hi) { 1446 MVT VT = N->getValueType(0); 1447 SDValue Op = N->getOperand(0); 1448 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1449 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1450 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi); 1451} 1452 1453void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1454 SDValue &Hi) { 1455 MVT VT = N->getValueType(0); 1456 SDValue Op = N->getOperand(0); 1457 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1458 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1459 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi); 1460} 1461 1462void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1463 SDValue &Lo, SDValue &Hi) { 1464 if (ISD::isNormalLoad(N)) { 1465 ExpandRes_NormalLoad(N, Lo, Hi); 1466 return; 1467 } 1468 1469 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1470 1471 MVT VT = N->getValueType(0); 1472 MVT NVT = TLI.getTypeToTransformTo(VT); 1473 SDValue Ch = N->getChain(); 1474 SDValue Ptr = N->getBasePtr(); 1475 ISD::LoadExtType ExtType = N->getExtensionType(); 1476 int SVOffset = N->getSrcValueOffset(); 1477 unsigned Alignment = N->getAlignment(); 1478 bool isVolatile = N->isVolatile(); 1479 1480 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1481 1482 if (N->getMemoryVT().bitsLE(NVT)) { 1483 MVT EVT = N->getMemoryVT(); 1484 1485 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, 1486 isVolatile, Alignment); 1487 1488 // Remember the chain. 1489 Ch = Lo.getValue(1); 1490 1491 if (ExtType == ISD::SEXTLOAD) { 1492 // The high part is obtained by SRA'ing all but one of the bits of the 1493 // lo part. 1494 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1495 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1496 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1497 } else if (ExtType == ISD::ZEXTLOAD) { 1498 // The high part is just a zero. 1499 Hi = DAG.getConstant(0, NVT); 1500 } else { 1501 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1502 // The high part is undefined. 1503 Hi = DAG.getNode(ISD::UNDEF, NVT); 1504 } 1505 } else if (TLI.isLittleEndian()) { 1506 // Little-endian - low bits are at low addresses. 1507 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1508 isVolatile, Alignment); 1509 1510 unsigned ExcessBits = 1511 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1512 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1513 1514 // Increment the pointer to the other half. 1515 unsigned IncrementSize = NVT.getSizeInBits()/8; 1516 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1517 DAG.getIntPtrConstant(IncrementSize)); 1518 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), 1519 SVOffset+IncrementSize, NEVT, 1520 isVolatile, MinAlign(Alignment, IncrementSize)); 1521 1522 // Build a factor node to remember that this load is independent of the 1523 // other one. 1524 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1525 Hi.getValue(1)); 1526 } else { 1527 // Big-endian - high bits are at low addresses. Favor aligned loads at 1528 // the cost of some bit-fiddling. 1529 MVT EVT = N->getMemoryVT(); 1530 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1531 unsigned IncrementSize = NVT.getSizeInBits()/8; 1532 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1533 1534 // Load both the high bits and maybe some of the low bits. 1535 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1536 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1537 isVolatile, Alignment); 1538 1539 // Increment the pointer to the other half. 1540 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1541 DAG.getIntPtrConstant(IncrementSize)); 1542 // Load the rest of the low bits. 1543 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(), 1544 SVOffset+IncrementSize, 1545 MVT::getIntegerVT(ExcessBits), 1546 isVolatile, MinAlign(Alignment, IncrementSize)); 1547 1548 // Build a factor node to remember that this load is independent of the 1549 // other one. 1550 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1551 Hi.getValue(1)); 1552 1553 if (ExcessBits < NVT.getSizeInBits()) { 1554 // Transfer low bits from the bottom of Hi to the top of Lo. 1555 Lo = DAG.getNode(ISD::OR, NVT, Lo, 1556 DAG.getNode(ISD::SHL, NVT, Hi, 1557 DAG.getConstant(ExcessBits, 1558 TLI.getShiftAmountTy()))); 1559 // Move high bits to the right position in Hi. 1560 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi, 1561 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1562 TLI.getShiftAmountTy())); 1563 } 1564 } 1565 1566 // Legalized the chain result - switch anything that used the old chain to 1567 // use the new one. 1568 ReplaceValueWith(SDValue(N, 1), Ch); 1569} 1570 1571void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1572 SDValue &Lo, SDValue &Hi) { 1573 SDValue LL, LH, RL, RH; 1574 GetExpandedInteger(N->getOperand(0), LL, LH); 1575 GetExpandedInteger(N->getOperand(1), RL, RH); 1576 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL); 1577 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH); 1578} 1579 1580void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1581 SDValue &Lo, SDValue &Hi) { 1582 MVT VT = N->getValueType(0); 1583 MVT NVT = TLI.getTypeToTransformTo(VT); 1584 1585 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 1586 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 1587 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 1588 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 1589 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1590 SDValue LL, LH, RL, RH; 1591 GetExpandedInteger(N->getOperand(0), LL, LH); 1592 GetExpandedInteger(N->getOperand(1), RL, RH); 1593 unsigned OuterBitSize = VT.getSizeInBits(); 1594 unsigned InnerBitSize = NVT.getSizeInBits(); 1595 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1596 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1597 1598 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1599 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1600 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1601 // The inputs are both zero-extended. 1602 if (HasUMUL_LOHI) { 1603 // We can emit a umul_lohi. 1604 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1605 Hi = SDValue(Lo.getNode(), 1); 1606 return; 1607 } 1608 if (HasMULHU) { 1609 // We can emit a mulhu+mul. 1610 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1611 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1612 return; 1613 } 1614 } 1615 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1616 // The input values are both sign-extended. 1617 if (HasSMUL_LOHI) { 1618 // We can emit a smul_lohi. 1619 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1620 Hi = SDValue(Lo.getNode(), 1); 1621 return; 1622 } 1623 if (HasMULHS) { 1624 // We can emit a mulhs+mul. 1625 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1626 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 1627 return; 1628 } 1629 } 1630 if (HasUMUL_LOHI) { 1631 // Lo,Hi = umul LHS, RHS. 1632 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 1633 DAG.getVTList(NVT, NVT), LL, RL); 1634 Lo = UMulLOHI; 1635 Hi = UMulLOHI.getValue(1); 1636 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1637 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1638 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1639 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1640 return; 1641 } 1642 if (HasMULHU) { 1643 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1644 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1645 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1646 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1647 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1648 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1649 return; 1650 } 1651 } 1652 1653 // If nothing else, we can make a libcall. 1654 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1655 if (VT == MVT::i32) 1656 LC = RTLIB::MUL_I32; 1657 else if (VT == MVT::i64) 1658 LC = RTLIB::MUL_I64; 1659 else if (VT == MVT::i128) 1660 LC = RTLIB::MUL_I128; 1661 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1662 1663 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1664 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi); 1665} 1666 1667void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1668 SDValue &Lo, SDValue &Hi) { 1669 MVT VT = N->getValueType(0); 1670 1671 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1672 if (VT == MVT::i32) 1673 LC = RTLIB::SDIV_I32; 1674 else if (VT == MVT::i64) 1675 LC = RTLIB::SDIV_I64; 1676 else if (VT == MVT::i128) 1677 LC = RTLIB::SDIV_I128; 1678 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1679 1680 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1681 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1682} 1683 1684void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1685 SDValue &Lo, SDValue &Hi) { 1686 MVT VT = N->getValueType(0); 1687 1688 // If we can emit an efficient shift operation, do so now. Check to see if 1689 // the RHS is a constant. 1690 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1691 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1692 1693 // If we can determine that the high bit of the shift is zero or one, even if 1694 // the low bits are variable, emit this shift in an optimized form. 1695 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1696 return; 1697 1698 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1699 unsigned PartsOpc; 1700 if (N->getOpcode() == ISD::SHL) { 1701 PartsOpc = ISD::SHL_PARTS; 1702 } else if (N->getOpcode() == ISD::SRL) { 1703 PartsOpc = ISD::SRL_PARTS; 1704 } else { 1705 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1706 PartsOpc = ISD::SRA_PARTS; 1707 } 1708 1709 // Next check to see if the target supports this SHL_PARTS operation or if it 1710 // will custom expand it. 1711 MVT NVT = TLI.getTypeToTransformTo(VT); 1712 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1713 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1714 Action == TargetLowering::Custom) { 1715 // Expand the subcomponents. 1716 SDValue LHSL, LHSH; 1717 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1718 1719 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1720 MVT VT = LHSL.getValueType(); 1721 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 1722 Hi = Lo.getValue(1); 1723 return; 1724 } 1725 1726 // Otherwise, emit a libcall. 1727 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1728 bool isSigned; 1729 if (N->getOpcode() == ISD::SHL) { 1730 isSigned = false; /*sign irrelevant*/ 1731 if (VT == MVT::i32) 1732 LC = RTLIB::SHL_I32; 1733 else if (VT == MVT::i64) 1734 LC = RTLIB::SHL_I64; 1735 else if (VT == MVT::i128) 1736 LC = RTLIB::SHL_I128; 1737 } else if (N->getOpcode() == ISD::SRL) { 1738 isSigned = false; 1739 if (VT == MVT::i32) 1740 LC = RTLIB::SRL_I32; 1741 else if (VT == MVT::i64) 1742 LC = RTLIB::SRL_I64; 1743 else if (VT == MVT::i128) 1744 LC = RTLIB::SRL_I128; 1745 } else { 1746 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1747 isSigned = true; 1748 if (VT == MVT::i32) 1749 LC = RTLIB::SRA_I32; 1750 else if (VT == MVT::i64) 1751 LC = RTLIB::SRA_I64; 1752 else if (VT == MVT::i128) 1753 LC = RTLIB::SRA_I128; 1754 } 1755 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!"); 1756 1757 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1758 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi); 1759} 1760 1761void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 1762 SDValue &Lo, SDValue &Hi) { 1763 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1764 SDValue Op = N->getOperand(0); 1765 if (Op.getValueType().bitsLE(NVT)) { 1766 // The low part is sign extension of the input (degenerates to a copy). 1767 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); 1768 // The high part is obtained by SRA'ing all but one of the bits of low part. 1769 unsigned LoSize = NVT.getSizeInBits(); 1770 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1771 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1772 } else { 1773 // For example, extension of an i48 to an i64. The operand type necessarily 1774 // promotes to the result type, so will end up being expanded too. 1775 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1776 "Only know how to promote this result!"); 1777 SDValue Res = GetPromotedInteger(Op); 1778 assert(Res.getValueType() == N->getValueType(0) && 1779 "Operand over promoted?"); 1780 // Split the promoted operand. This will simplify when it is expanded. 1781 SplitInteger(Res, Lo, Hi); 1782 unsigned ExcessBits = 1783 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1784 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 1785 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1786 } 1787} 1788 1789void DAGTypeLegalizer:: 1790ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 1791 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1792 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1793 1794 if (EVT.bitsLE(Lo.getValueType())) { 1795 // sext_inreg the low part if needed. 1796 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo, 1797 N->getOperand(1)); 1798 1799 // The high part gets the sign extension from the lo-part. This handles 1800 // things like sextinreg V:i64 from i8. 1801 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo, 1802 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 1803 TLI.getShiftAmountTy())); 1804 } else { 1805 // For example, extension of an i48 to an i64. Leave the low part alone, 1806 // sext_inreg the high part. 1807 unsigned ExcessBits = 1808 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 1809 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 1810 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1811 } 1812} 1813 1814void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1815 SDValue &Lo, SDValue &Hi) { 1816 MVT VT = N->getValueType(0); 1817 1818 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1819 if (VT == MVT::i32) 1820 LC = RTLIB::SREM_I32; 1821 else if (VT == MVT::i64) 1822 LC = RTLIB::SREM_I64; 1823 else if (VT == MVT::i128) 1824 LC = RTLIB::SREM_I128; 1825 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1826 1827 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1828 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1829} 1830 1831void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 1832 SDValue &Lo, SDValue &Hi) { 1833 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1834 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); 1835 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), 1836 DAG.getConstant(NVT.getSizeInBits(), 1837 TLI.getShiftAmountTy())); 1838 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); 1839} 1840 1841void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1842 SDValue &Lo, SDValue &Hi) { 1843 MVT VT = N->getValueType(0); 1844 1845 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1846 if (VT == MVT::i32) 1847 LC = RTLIB::UDIV_I32; 1848 else if (VT == MVT::i64) 1849 LC = RTLIB::UDIV_I64; 1850 else if (VT == MVT::i128) 1851 LC = RTLIB::UDIV_I128; 1852 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 1853 1854 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1855 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1856} 1857 1858void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1859 SDValue &Lo, SDValue &Hi) { 1860 MVT VT = N->getValueType(0); 1861 1862 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1863 if (VT == MVT::i32) 1864 LC = RTLIB::UREM_I32; 1865 else if (VT == MVT::i64) 1866 LC = RTLIB::UREM_I64; 1867 else if (VT == MVT::i128) 1868 LC = RTLIB::UREM_I128; 1869 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 1870 1871 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1872 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1873} 1874 1875void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 1876 SDValue &Lo, SDValue &Hi) { 1877 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1878 SDValue Op = N->getOperand(0); 1879 if (Op.getValueType().bitsLE(NVT)) { 1880 // The low part is zero extension of the input (degenerates to a copy). 1881 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); 1882 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 1883 } else { 1884 // For example, extension of an i48 to an i64. The operand type necessarily 1885 // promotes to the result type, so will end up being expanded too. 1886 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1887 "Only know how to promote this result!"); 1888 SDValue Res = GetPromotedInteger(Op); 1889 assert(Res.getValueType() == N->getValueType(0) && 1890 "Operand over promoted?"); 1891 // Split the promoted operand. This will simplify when it is expanded. 1892 SplitInteger(Res, Lo, Hi); 1893 unsigned ExcessBits = 1894 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1895 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); 1896 } 1897} 1898 1899 1900//===----------------------------------------------------------------------===// 1901// Integer Operand Expansion 1902//===----------------------------------------------------------------------===// 1903 1904/// ExpandIntegerOperand - This method is called when the specified operand of 1905/// the specified node is found to need expansion. At this point, all of the 1906/// result types of the node are known to be legal, but other operands of the 1907/// node may need promotion or expansion as well as the specified one. 1908bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1909 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); 1910 SDValue Res = SDValue(); 1911 1912 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 1913 == TargetLowering::Custom) 1914 Res = TLI.LowerOperation(SDValue(N, 0), DAG); 1915 1916 if (Res.getNode() == 0) { 1917 switch (N->getOpcode()) { 1918 default: 1919 #ifndef NDEBUG 1920 cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; 1921 N->dump(&DAG); cerr << "\n"; 1922 #endif 1923 assert(0 && "Do not know how to expand this operator's operand!"); 1924 abort(); 1925 1926 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1927 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1928 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1929 1930 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1931 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1932 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1933 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 1934 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); 1935 break; 1936 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1937 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 1938 } 1939 } 1940 1941 // If the result is null, the sub-method took care of registering results etc. 1942 if (!Res.getNode()) return false; 1943 // If the result is N, the sub-method updated N in place. Check to see if any 1944 // operands are new, and if so, mark them. 1945 if (Res.getNode() == N) { 1946 // Mark N as new and remark N and its operands. This allows us to correctly 1947 // revisit N if it needs another step of expansion and allows us to visit 1948 // any new operands to N. 1949 ReanalyzeNode(N); 1950 return true; 1951 } 1952 1953 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1954 "Invalid operand expansion"); 1955 1956 ReplaceValueWith(SDValue(N, 0), Res); 1957 return false; 1958} 1959 1960/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 1961/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1962void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 1963 SDValue &NewRHS, 1964 ISD::CondCode &CCCode) { 1965 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 1966 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 1967 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 1968 1969 MVT VT = NewLHS.getValueType(); 1970 1971 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 1972 if (RHSLo == RHSHi) { 1973 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 1974 if (RHSCST->isAllOnesValue()) { 1975 // Equality comparison to -1. 1976 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1977 NewRHS = RHSLo; 1978 return; 1979 } 1980 } 1981 } 1982 1983 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1984 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1985 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS); 1986 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1987 return; 1988 } 1989 1990 // If this is a comparison of the sign bit, just look at the top part. 1991 // X > -1, x < 0 1992 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 1993 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 1994 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 1995 NewLHS = LHSHi; 1996 NewRHS = RHSHi; 1997 return; 1998 } 1999 2000 // FIXME: This generated code sucks. 2001 ISD::CondCode LowCC; 2002 switch (CCCode) { 2003 default: assert(0 && "Unknown integer setcc!"); 2004 case ISD::SETLT: 2005 case ISD::SETULT: LowCC = ISD::SETULT; break; 2006 case ISD::SETGT: 2007 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2008 case ISD::SETLE: 2009 case ISD::SETULE: LowCC = ISD::SETULE; break; 2010 case ISD::SETGE: 2011 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2012 } 2013 2014 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2015 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2016 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2017 2018 // NOTE: on targets without efficient SELECT of bools, we can always use 2019 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2020 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 2021 SDValue Tmp1, Tmp2; 2022 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC, 2023 false, DagCombineInfo); 2024 if (!Tmp1.getNode()) 2025 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 2026 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2027 CCCode, false, DagCombineInfo); 2028 if (!Tmp2.getNode()) 2029 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2030 DAG.getCondCode(CCCode)); 2031 2032 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2033 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2034 if ((Tmp1C && Tmp1C->isNullValue()) || 2035 (Tmp2C && Tmp2C->isNullValue() && 2036 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2037 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2038 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2039 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2040 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2041 // low part is known false, returns high part. 2042 // For LE / GE, if high part is known false, ignore the low part. 2043 // For LT / GT, if high part is known true, ignore the low part. 2044 NewLHS = Tmp2; 2045 NewRHS = SDValue(); 2046 return; 2047 } 2048 2049 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2050 ISD::SETEQ, false, DagCombineInfo); 2051 if (!NewLHS.getNode()) 2052 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2053 ISD::SETEQ); 2054 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 2055 NewLHS, Tmp1, Tmp2); 2056 NewRHS = SDValue(); 2057} 2058 2059SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2060 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2061 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2062 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2063 2064 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2065 // against zero to select between true and false values. 2066 if (NewRHS.getNode() == 0) { 2067 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2068 CCCode = ISD::SETNE; 2069 } 2070 2071 // Update N to have the operands specified. 2072 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 2073 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2074 N->getOperand(4)); 2075} 2076 2077SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2078 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2079 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2080 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2081 2082 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2083 // against zero to select between true and false values. 2084 if (NewRHS.getNode() == 0) { 2085 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2086 CCCode = ISD::SETNE; 2087 } 2088 2089 // Update N to have the operands specified. 2090 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2091 N->getOperand(2), N->getOperand(3), 2092 DAG.getCondCode(CCCode)); 2093} 2094 2095SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2096 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2097 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2098 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2099 2100 // If ExpandSetCCOperands returned a scalar, use it. 2101 if (NewRHS.getNode() == 0) { 2102 assert(NewLHS.getValueType() == N->getValueType(0) && 2103 "Unexpected setcc expansion!"); 2104 return NewLHS; 2105 } 2106 2107 // Otherwise, update N to have the operands specified. 2108 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2109 DAG.getCondCode(CCCode)); 2110} 2111 2112SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2113 SDValue Op = N->getOperand(0); 2114 MVT DstVT = N->getValueType(0); 2115 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2116 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2117 "Don't know how to expand this SINT_TO_FP!"); 2118 return MakeLibCall(LC, DstVT, &Op, 1, true); 2119} 2120 2121SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2122 if (ISD::isNormalStore(N)) 2123 return ExpandOp_NormalStore(N, OpNo); 2124 2125 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2126 assert(OpNo == 1 && "Can only expand the stored value so far"); 2127 2128 MVT VT = N->getOperand(1).getValueType(); 2129 MVT NVT = TLI.getTypeToTransformTo(VT); 2130 SDValue Ch = N->getChain(); 2131 SDValue Ptr = N->getBasePtr(); 2132 int SVOffset = N->getSrcValueOffset(); 2133 unsigned Alignment = N->getAlignment(); 2134 bool isVolatile = N->isVolatile(); 2135 SDValue Lo, Hi; 2136 2137 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2138 2139 if (N->getMemoryVT().bitsLE(NVT)) { 2140 GetExpandedInteger(N->getValue(), Lo, Hi); 2141 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 2142 N->getMemoryVT(), isVolatile, Alignment); 2143 } else if (TLI.isLittleEndian()) { 2144 // Little-endian - low bits are at low addresses. 2145 GetExpandedInteger(N->getValue(), Lo, Hi); 2146 2147 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 2148 isVolatile, Alignment); 2149 2150 unsigned ExcessBits = 2151 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2152 MVT NEVT = MVT::getIntegerVT(ExcessBits); 2153 2154 // Increment the pointer to the other half. 2155 unsigned IncrementSize = NVT.getSizeInBits()/8; 2156 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2157 DAG.getIntPtrConstant(IncrementSize)); 2158 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2159 SVOffset+IncrementSize, NEVT, 2160 isVolatile, MinAlign(Alignment, IncrementSize)); 2161 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2162 } else { 2163 // Big-endian - high bits are at low addresses. Favor aligned stores at 2164 // the cost of some bit-fiddling. 2165 GetExpandedInteger(N->getValue(), Lo, Hi); 2166 2167 MVT EVT = N->getMemoryVT(); 2168 unsigned EBytes = EVT.getStoreSizeInBits()/8; 2169 unsigned IncrementSize = NVT.getSizeInBits()/8; 2170 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2171 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 2172 2173 if (ExcessBits < NVT.getSizeInBits()) { 2174 // Transfer high bits from the top of Lo to the bottom of Hi. 2175 Hi = DAG.getNode(ISD::SHL, NVT, Hi, 2176 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2177 TLI.getShiftAmountTy())); 2178 Hi = DAG.getNode(ISD::OR, NVT, Hi, 2179 DAG.getNode(ISD::SRL, NVT, Lo, 2180 DAG.getConstant(ExcessBits, 2181 TLI.getShiftAmountTy()))); 2182 } 2183 2184 // Store both the high bits and maybe some of the low bits. 2185 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2186 SVOffset, HiVT, isVolatile, Alignment); 2187 2188 // Increment the pointer to the other half. 2189 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2190 DAG.getIntPtrConstant(IncrementSize)); 2191 // Store the lowest ExcessBits bits in the second half. 2192 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), 2193 SVOffset+IncrementSize, 2194 MVT::getIntegerVT(ExcessBits), 2195 isVolatile, MinAlign(Alignment, IncrementSize)); 2196 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2197 } 2198} 2199 2200SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2201 SDValue InL, InH; 2202 GetExpandedInteger(N->getOperand(0), InL, InH); 2203 // Just truncate the low part of the source. 2204 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL); 2205} 2206 2207SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2208 SDValue Op = N->getOperand(0); 2209 MVT SrcVT = Op.getValueType(); 2210 MVT DstVT = N->getValueType(0); 2211 2212 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2213 // Do a signed conversion then adjust the result. 2214 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op); 2215 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2216 2217 // The result of the signed conversion needs adjusting if the 'sign bit' of 2218 // the incoming integer was set. To handle this, we dynamically test to see 2219 // if it is set, and, if so, add a fudge factor. 2220 2221 const uint64_t F32TwoE32 = 0x4F800000ULL; 2222 const uint64_t F32TwoE64 = 0x5F800000ULL; 2223 const uint64_t F32TwoE128 = 0x7F800000ULL; 2224 2225 APInt FF(32, 0); 2226 if (SrcVT == MVT::i32) 2227 FF = APInt(32, F32TwoE32); 2228 else if (SrcVT == MVT::i64) 2229 FF = APInt(32, F32TwoE64); 2230 else if (SrcVT == MVT::i128) 2231 FF = APInt(32, F32TwoE128); 2232 else 2233 assert(false && "Unsupported UINT_TO_FP!"); 2234 2235 // Check whether the sign bit is set. 2236 SDValue Lo, Hi; 2237 GetExpandedInteger(Op, Lo, Hi); 2238 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 2239 DAG.getConstant(0, Hi.getValueType()), 2240 ISD::SETLT); 2241 2242 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2243 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)), 2244 TLI.getPointerTy()); 2245 2246 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2247 SDValue Zero = DAG.getIntPtrConstant(0); 2248 SDValue Four = DAG.getIntPtrConstant(4); 2249 if (TLI.isBigEndian()) std::swap(Zero, Four); 2250 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet, 2251 Zero, Four); 2252 unsigned Alignment = 2253 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2254 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset); 2255 Alignment = std::min(Alignment, 4u); 2256 2257 // Load the value out, extending it from f32 to the destination float type. 2258 // FIXME: Avoid the extend by constructing the right constant pool? 2259 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(), 2260 FudgePtr, NULL, 0, MVT::f32, 2261 false, Alignment); 2262 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge); 2263 } 2264 2265 // Otherwise, use a libcall. 2266 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2267 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2268 "Don't know how to expand this UINT_TO_FP!"); 2269 return MakeLibCall(LC, DstVT, &Op, 1, true); 2270} 2271