LegalizeIntegerTypes.cpp revision 33a8d20d065c549ab1d216c0cdfeece754a4cc57
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22using namespace llvm; 23 24//===----------------------------------------------------------------------===// 25// Integer Result Promotion 26//===----------------------------------------------------------------------===// 27 28/// PromoteIntegerResult - This method is called when a result of a node is 29/// found to be in need of promotion to a larger type. At this point, the node 30/// may also have invalid operands or may have other results that need 31/// expansion, we just know that (at least) one result needs promotion. 32void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); 34 SDValue Result = SDValue(); 35 36 // See if the target wants to custom expand this node. 37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 38 TargetLowering::Custom) { 39 // If the target wants to, allow it to lower this itself. 40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 41 // Everything that once used N now uses P. We are guaranteed that the 42 // result value types of N and the result value types of P match. 43 ReplaceNodeWith(N, P); 44 return; 45 } 46 } 47 48 switch (N->getOpcode()) { 49 default: 50#ifndef NDEBUG 51 cerr << "PromoteIntegerResult #" << ResNo << ": "; 52 N->dump(&DAG); cerr << "\n"; 53#endif 54 assert(0 && "Do not know how to promote this operator!"); 55 abort(); 56 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break; 57 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break; 58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break; 59 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break; 60 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break; 61 case ISD::Constant: Result = PromoteIntRes_Constant(N); break; 62 case ISD::CONVERT_RNDSAT: 63 Result = PromoteIntRes_CONVERT_RNDSAT(N); break; 64 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break; 65 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break; 66 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break; 67 case ISD::EXTRACT_VECTOR_ELT: 68 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 69 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 70 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break; 71 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break; 72 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break; 73 case ISD::SHL: Result = PromoteIntRes_SHL(N); break; 74 case ISD::SIGN_EXTEND_INREG: 75 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 76 case ISD::SRA: Result = PromoteIntRes_SRA(N); break; 77 case ISD::SRL: Result = PromoteIntRes_SRL(N); break; 78 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break; 79 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break; 80 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break; 81 82 case ISD::SIGN_EXTEND: 83 case ISD::ZERO_EXTEND: 84 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break; 85 86 case ISD::FP_TO_SINT: 87 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break; 88 89 case ISD::AND: 90 case ISD::OR: 91 case ISD::XOR: 92 case ISD::ADD: 93 case ISD::SUB: 94 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break; 95 96 case ISD::SDIV: 97 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break; 98 99 case ISD::UDIV: 100 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break; 101 102 case ISD::ATOMIC_LOAD_ADD_8: 103 case ISD::ATOMIC_LOAD_SUB_8: 104 case ISD::ATOMIC_LOAD_AND_8: 105 case ISD::ATOMIC_LOAD_OR_8: 106 case ISD::ATOMIC_LOAD_XOR_8: 107 case ISD::ATOMIC_LOAD_NAND_8: 108 case ISD::ATOMIC_LOAD_MIN_8: 109 case ISD::ATOMIC_LOAD_MAX_8: 110 case ISD::ATOMIC_LOAD_UMIN_8: 111 case ISD::ATOMIC_LOAD_UMAX_8: 112 case ISD::ATOMIC_SWAP_8: 113 case ISD::ATOMIC_LOAD_ADD_16: 114 case ISD::ATOMIC_LOAD_SUB_16: 115 case ISD::ATOMIC_LOAD_AND_16: 116 case ISD::ATOMIC_LOAD_OR_16: 117 case ISD::ATOMIC_LOAD_XOR_16: 118 case ISD::ATOMIC_LOAD_NAND_16: 119 case ISD::ATOMIC_LOAD_MIN_16: 120 case ISD::ATOMIC_LOAD_MAX_16: 121 case ISD::ATOMIC_LOAD_UMIN_16: 122 case ISD::ATOMIC_LOAD_UMAX_16: 123 case ISD::ATOMIC_SWAP_16: 124 case ISD::ATOMIC_LOAD_ADD_32: 125 case ISD::ATOMIC_LOAD_SUB_32: 126 case ISD::ATOMIC_LOAD_AND_32: 127 case ISD::ATOMIC_LOAD_OR_32: 128 case ISD::ATOMIC_LOAD_XOR_32: 129 case ISD::ATOMIC_LOAD_NAND_32: 130 case ISD::ATOMIC_LOAD_MIN_32: 131 case ISD::ATOMIC_LOAD_MAX_32: 132 case ISD::ATOMIC_LOAD_UMIN_32: 133 case ISD::ATOMIC_LOAD_UMAX_32: 134 case ISD::ATOMIC_SWAP_32: 135 case ISD::ATOMIC_LOAD_ADD_64: 136 case ISD::ATOMIC_LOAD_SUB_64: 137 case ISD::ATOMIC_LOAD_AND_64: 138 case ISD::ATOMIC_LOAD_OR_64: 139 case ISD::ATOMIC_LOAD_XOR_64: 140 case ISD::ATOMIC_LOAD_NAND_64: 141 case ISD::ATOMIC_LOAD_MIN_64: 142 case ISD::ATOMIC_LOAD_MAX_64: 143 case ISD::ATOMIC_LOAD_UMIN_64: 144 case ISD::ATOMIC_LOAD_UMAX_64: 145 case ISD::ATOMIC_SWAP_64: 146 Result = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 147 148 case ISD::ATOMIC_CMP_SWAP_8: 149 case ISD::ATOMIC_CMP_SWAP_16: 150 case ISD::ATOMIC_CMP_SWAP_32: 151 case ISD::ATOMIC_CMP_SWAP_64: 152 Result = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 153 } 154 155 // If Result is null, the sub-method took care of registering the result. 156 if (Result.getNode()) 157 SetPromotedInteger(SDValue(N, ResNo), Result); 158} 159 160SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 161 // Sign-extend the new bits, and continue the assertion. 162 MVT OldVT = N->getValueType(0); 163 SDValue Op = GetPromotedInteger(N->getOperand(0)); 164 return DAG.getNode(ISD::AssertSext, Op.getValueType(), 165 DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, 166 DAG.getValueType(OldVT)), N->getOperand(1)); 167} 168 169SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 170 // Zero the new bits, and continue the assertion. 171 MVT OldVT = N->getValueType(0); 172 SDValue Op = GetPromotedInteger(N->getOperand(0)); 173 return DAG.getNode(ISD::AssertZext, Op.getValueType(), 174 DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1)); 175} 176 177SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 178 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 179 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(), 180 Op2, N->getSrcValue(), N->getAlignment()); 181 // Legalized the chain result - switch anything that used the old chain to 182 // use the new one. 183 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 184 return Res; 185} 186 187SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 188 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 189 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 190 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(), 191 Op2, Op3, N->getSrcValue(), N->getAlignment()); 192 // Legalized the chain result - switch anything that used the old chain to 193 // use the new one. 194 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 195 return Res; 196} 197 198SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 199 SDValue InOp = N->getOperand(0); 200 MVT InVT = InOp.getValueType(); 201 MVT NInVT = TLI.getTypeToTransformTo(InVT); 202 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 203 204 switch (getTypeAction(InVT)) { 205 default: 206 assert(false && "Unknown type action!"); 207 break; 208 case Legal: 209 break; 210 case PromoteInteger: 211 if (OutVT.bitsEq(NInVT)) 212 // The input promotes to the same size. Convert the promoted value. 213 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp)); 214 break; 215 case SoftenFloat: 216 // Promote the integer operand by hand. 217 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp)); 218 case ExpandInteger: 219 case ExpandFloat: 220 break; 221 case ScalarizeVector: 222 // Convert the element to an integer and promote it by hand. 223 return DAG.getNode(ISD::ANY_EXTEND, OutVT, 224 BitConvertToInteger(GetScalarizedVector(InOp))); 225 case SplitVector: 226 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 227 // pieces of the input into integers and reassemble in the final type. 228 SDValue Lo, Hi; 229 GetSplitVector(N->getOperand(0), Lo, Hi); 230 Lo = BitConvertToInteger(Lo); 231 Hi = BitConvertToInteger(Hi); 232 233 if (TLI.isBigEndian()) 234 std::swap(Lo, Hi); 235 236 InOp = DAG.getNode(ISD::ANY_EXTEND, 237 MVT::getIntegerVT(OutVT.getSizeInBits()), 238 JoinIntegers(Lo, Hi)); 239 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp); 240 } 241 242 // Otherwise, lower the bit-convert to a store/load from the stack, then 243 // promote the load. 244 SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0)); 245 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode())); 246} 247 248SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 249 SDValue Op = GetPromotedInteger(N->getOperand(0)); 250 MVT OVT = N->getValueType(0); 251 MVT NVT = Op.getValueType(); 252 253 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 254 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op), 255 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 256} 257 258SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 259 // The pair element type may be legal, or may not promote to the same type as 260 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 261 return DAG.getNode(ISD::ANY_EXTEND, 262 TLI.getTypeToTransformTo(N->getValueType(0)), 263 JoinIntegers(N->getOperand(0), N->getOperand(1))); 264} 265 266SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 267 MVT VT = N->getValueType(0); 268 // Zero extend things like i1, sign extend everything else. It shouldn't 269 // matter in theory which one we pick, but this tends to give better code? 270 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 271 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), 272 SDValue(N, 0)); 273 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 274 return Result; 275} 276 277SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 278 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 279 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 280 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 281 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 282 "can only promote integers"); 283 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 284 return DAG.getConvertRndSat(OutVT, N->getOperand(0), 285 N->getOperand(1), N->getOperand(2), 286 N->getOperand(3), N->getOperand(4), CvtCode); 287} 288 289SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 290 SDValue Op = GetPromotedInteger(N->getOperand(0)); 291 MVT OVT = N->getValueType(0); 292 MVT NVT = Op.getValueType(); 293 // Zero extend to the promoted type and do the count there. 294 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT)); 295 // Subtract off the extra leading bits in the bigger type. 296 return DAG.getNode(ISD::SUB, NVT, Op, 297 DAG.getConstant(NVT.getSizeInBits() - 298 OVT.getSizeInBits(), NVT)); 299} 300 301SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 302 SDValue Op = GetPromotedInteger(N->getOperand(0)); 303 MVT OVT = N->getValueType(0); 304 MVT NVT = Op.getValueType(); 305 // Zero extend to the promoted type and do the count there. 306 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT)); 307} 308 309SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 310 SDValue Op = GetPromotedInteger(N->getOperand(0)); 311 MVT OVT = N->getValueType(0); 312 MVT NVT = Op.getValueType(); 313 // The count is the same in the promoted type except if the original 314 // value was zero. This can be handled by setting the bit just off 315 // the top of the original type. 316 APInt TopBit(NVT.getSizeInBits(), 0); 317 TopBit.set(OVT.getSizeInBits()); 318 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT)); 319 return DAG.getNode(ISD::CTTZ, NVT, Op); 320} 321 322SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 323 MVT OldVT = N->getValueType(0); 324 SDValue OldVec = N->getOperand(0); 325 unsigned OldElts = OldVec.getValueType().getVectorNumElements(); 326 327 if (OldElts == 1) { 328 assert(!isTypeLegal(OldVec.getValueType()) && 329 "Legal one-element vector of a type needing promotion!"); 330 // It is tempting to follow GetScalarizedVector by a call to 331 // GetPromotedInteger, but this would be wrong because the 332 // scalarized value may not yet have been processed. 333 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), 334 GetScalarizedVector(OldVec)); 335 } 336 337 // Convert to a vector half as long with an element type of twice the width, 338 // for example <4 x i16> -> <2 x i32>. 339 assert(!(OldElts & 1) && "Odd length vectors not supported!"); 340 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 341 assert(OldVT.isSimple() && NewVT.isSimple()); 342 343 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, 344 MVT::getVectorVT(NewVT, OldElts / 2), 345 OldVec); 346 347 // Extract the element at OldIdx / 2 from the new vector. 348 SDValue OldIdx = N->getOperand(1); 349 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx, 350 DAG.getConstant(1, TLI.getShiftAmountTy())); 351 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx); 352 353 // Select the appropriate half of the element: Lo if OldIdx was even, 354 // Hi if it was odd. 355 SDValue Lo = Elt; 356 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt, 357 DAG.getConstant(OldVT.getSizeInBits(), 358 TLI.getShiftAmountTy())); 359 if (TLI.isBigEndian()) 360 std::swap(Lo, Hi); 361 362 SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx); 363 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo); 364} 365 366SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 367 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 368 unsigned NewOpc = N->getOpcode(); 369 370 // If we're promoting a UINT to a larger size, check to see if the new node 371 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 372 // we can use that instead. This allows us to generate better code for 373 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 374 // legal, such as PowerPC. 375 if (N->getOpcode() == ISD::FP_TO_UINT && 376 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 377 TLI.isOperationLegal(ISD::FP_TO_SINT, NVT)) 378 NewOpc = ISD::FP_TO_SINT; 379 380 SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0)); 381 382 // Assert that the converted value fits in the original type. If it doesn't 383 // (eg: because the value being converted is too big), then the result of the 384 // original operation was undefined anyway, so the assert is still correct. 385 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 386 ISD::AssertZext : ISD::AssertSext, 387 NVT, Res, DAG.getValueType(N->getValueType(0))); 388} 389 390SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 391 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 392 393 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 394 SDValue Res = GetPromotedInteger(N->getOperand(0)); 395 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 396 397 // If the result and operand types are the same after promotion, simplify 398 // to an in-register extension. 399 if (NVT == Res.getValueType()) { 400 // The high bits are not guaranteed to be anything. Insert an extend. 401 if (N->getOpcode() == ISD::SIGN_EXTEND) 402 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, 403 DAG.getValueType(N->getOperand(0).getValueType())); 404 if (N->getOpcode() == ISD::ZERO_EXTEND) 405 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); 406 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 407 return Res; 408 } 409 } 410 411 // Otherwise, just extend the original operand all the way to the larger type. 412 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0)); 413} 414 415SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 416 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 417 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 418 ISD::LoadExtType ExtType = 419 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 420 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(), 421 N->getSrcValue(), N->getSrcValueOffset(), 422 N->getMemoryVT(), N->isVolatile(), 423 N->getAlignment()); 424 425 // Legalized the chain result - switch anything that used the old chain to 426 // use the new one. 427 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 428 return Res; 429} 430 431SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 432 // Sign extend the input. 433 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 434 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 435 MVT VT = N->getValueType(0); 436 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS, 437 DAG.getValueType(VT)); 438 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS, 439 DAG.getValueType(VT)); 440 441 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 442} 443 444SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 445 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 446 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 447 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS); 448} 449 450SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 451 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 452 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 453 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0), 454 N->getOperand(1), LHS, RHS, N->getOperand(4)); 455} 456 457SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 458 MVT SVT = TLI.getSetCCResultType(N->getOperand(0)); 459 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 460 461 // Get the SETCC result using the canonical SETCC type. 462 SDValue SetCC = DAG.getNode(ISD::SETCC, SVT, N->getOperand(0), 463 N->getOperand(1), N->getOperand(2)); 464 465 // Convert to the expected type. 466 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 467 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 468 return DAG.getNode(ISD::TRUNCATE, NVT, SetCC); 469} 470 471SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 472 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)), 473 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 474} 475 476SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 477 SDValue Op = GetPromotedInteger(N->getOperand(0)); 478 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, 479 N->getOperand(1)); 480} 481 482SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 483 // The input may have strange things in the top bits of the registers, but 484 // these operations don't care. They may have weird bits going out, but 485 // that too is okay if they are integer operations. 486 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 487 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 488 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 489} 490 491SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 492 // The input value must be properly sign extended. 493 MVT VT = N->getValueType(0); 494 MVT NVT = TLI.getTypeToTransformTo(VT); 495 SDValue Res = GetPromotedInteger(N->getOperand(0)); 496 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT)); 497 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1)); 498} 499 500SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 501 // The input value must be properly zero extended. 502 MVT VT = N->getValueType(0); 503 MVT NVT = TLI.getTypeToTransformTo(VT); 504 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 505 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1)); 506} 507 508SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 509 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 510 SDValue Res; 511 512 switch (getTypeAction(N->getOperand(0).getValueType())) { 513 default: assert(0 && "Unknown type action!"); 514 case Legal: 515 case ExpandInteger: 516 Res = N->getOperand(0); 517 break; 518 case PromoteInteger: 519 Res = GetPromotedInteger(N->getOperand(0)); 520 break; 521 } 522 523 // Truncate to NVT instead of VT 524 return DAG.getNode(ISD::TRUNCATE, NVT, Res); 525} 526 527SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 528 // Zero extend the input. 529 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 530 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 531 MVT VT = N->getValueType(0); 532 LHS = DAG.getZeroExtendInReg(LHS, VT); 533 RHS = DAG.getZeroExtendInReg(RHS, VT); 534 535 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 536} 537 538SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 539 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0))); 540} 541 542SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 543 SDValue Chain = N->getOperand(0); // Get the chain. 544 SDValue Ptr = N->getOperand(1); // Get the pointer. 545 MVT VT = N->getValueType(0); 546 547 MVT RegVT = TLI.getRegisterType(VT); 548 unsigned NumRegs = TLI.getNumRegisters(VT); 549 // The argument is passed as NumRegs registers of type RegVT. 550 551 SmallVector<SDValue, 8> Parts(NumRegs); 552 for (unsigned i = 0; i < NumRegs; ++i) { 553 Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2)); 554 Chain = Parts[i].getValue(1); 555 } 556 557 // Handle endianness of the load. 558 if (TLI.isBigEndian()) 559 std::reverse(Parts.begin(), Parts.end()); 560 561 // Assemble the parts in the promoted type. 562 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 563 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[0]); 564 for (unsigned i = 1; i < NumRegs; ++i) { 565 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[i]); 566 // Shift it to the right position and "or" it in. 567 Part = DAG.getNode(ISD::SHL, NVT, Part, 568 DAG.getConstant(i * RegVT.getSizeInBits(), 569 TLI.getShiftAmountTy())); 570 Res = DAG.getNode(ISD::OR, NVT, Res, Part); 571 } 572 573 // Modified the chain result - switch anything that used the old chain to 574 // use the new one. 575 ReplaceValueWith(SDValue(N, 1), Chain); 576 577 return Res; 578} 579 580 581//===----------------------------------------------------------------------===// 582// Integer Operand Promotion 583//===----------------------------------------------------------------------===// 584 585/// PromoteIntegerOperand - This method is called when the specified operand of 586/// the specified node is found to need promotion. At this point, all of the 587/// result types of the node are known to be legal, but other operands of the 588/// node may need promotion or expansion as well as the specified one. 589bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 590 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); 591 SDValue Res = SDValue(); 592 593 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 594 == TargetLowering::Custom) 595 Res = TLI.LowerOperation(SDValue(N, 0), DAG); 596 597 if (Res.getNode() == 0) { 598 switch (N->getOpcode()) { 599 default: 600 #ifndef NDEBUG 601 cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; 602 N->dump(&DAG); cerr << "\n"; 603 #endif 604 assert(0 && "Do not know how to promote this operator's operand!"); 605 abort(); 606 607 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 608 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 609 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 610 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 611 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 612 case ISD::CONVERT_RNDSAT: 613 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 614 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break; 615 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break; 616 case ISD::INSERT_VECTOR_ELT: 617 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 618 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 619 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 620 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 621 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 622 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 623 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 624 OpNo); break; 625 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 626 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 627 628 case ISD::SINT_TO_FP: 629 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break; 630 } 631 } 632 633 // If the result is null, the sub-method took care of registering results etc. 634 if (!Res.getNode()) return false; 635 // If the result is N, the sub-method updated N in place. 636 if (Res.getNode() == N) { 637 // Mark N as new and remark N and its operands. This allows us to correctly 638 // revisit N if it needs another step of promotion and allows us to visit 639 // any new operands to N. 640 ReanalyzeNode(N); 641 return true; 642 } 643 644 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 645 "Invalid operand expansion"); 646 647 ReplaceValueWith(SDValue(N, 0), Res); 648 return false; 649} 650 651/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 652/// shared among BR_CC, SELECT_CC, and SETCC handlers. 653void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 654 ISD::CondCode CCCode) { 655 MVT VT = NewLHS.getValueType(); 656 657 // Get the promoted values. 658 NewLHS = GetPromotedInteger(NewLHS); 659 NewRHS = GetPromotedInteger(NewRHS); 660 661 // We have to insert explicit sign or zero extends. Note that we could 662 // insert sign extends for ALL conditions, but zero extend is cheaper on 663 // many machines (an AND instead of two shifts), so prefer it. 664 switch (CCCode) { 665 default: assert(0 && "Unknown integer comparison!"); 666 case ISD::SETEQ: 667 case ISD::SETNE: 668 case ISD::SETUGE: 669 case ISD::SETUGT: 670 case ISD::SETULE: 671 case ISD::SETULT: 672 // ALL of these operations will work if we either sign or zero extend 673 // the operands (including the unsigned comparisons!). Zero extend is 674 // usually a simpler/cheaper operation, so prefer it. 675 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT); 676 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT); 677 break; 678 case ISD::SETGE: 679 case ISD::SETGT: 680 case ISD::SETLT: 681 case ISD::SETLE: 682 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS, 683 DAG.getValueType(VT)); 684 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS, 685 DAG.getValueType(VT)); 686 break; 687 } 688} 689 690SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 691 SDValue Op = GetPromotedInteger(N->getOperand(0)); 692 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 693} 694 695SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 696 assert(OpNo == 2 && "Don't know how to promote this operand!"); 697 698 SDValue LHS = N->getOperand(2); 699 SDValue RHS = N->getOperand(3); 700 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 701 702 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 703 // legal types. 704 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 705 N->getOperand(1), LHS, RHS, N->getOperand(4)); 706} 707 708SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 709 assert(OpNo == 1 && "only know how to promote condition"); 710 SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition. 711 712 // Make sure the extra bits coming from type promotion conform to 713 // getSetCCResultContents. 714 unsigned CondBits = Cond.getValueSizeInBits(); 715 switch (TLI.getSetCCResultContents()) { 716 default: 717 assert(false && "Unknown SetCCResultValue!"); 718 case TargetLowering::UndefinedSetCCResult: 719 // The promoted value, which may contain rubbish in the upper bits, is fine. 720 break; 721 case TargetLowering::ZeroOrOneSetCCResult: 722 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1))) 723 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); 724 break; 725 case TargetLowering::ZeroOrNegativeOneSetCCResult: 726 if (DAG.ComputeNumSignBits(Cond) != CondBits) 727 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond, 728 DAG.getValueType(MVT::i1)); 729 break; 730 } 731 732 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 733 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, 734 N->getOperand(2)); 735} 736 737SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 738 // Since the result type is legal, the operands must promote to it. 739 MVT OVT = N->getOperand(0).getValueType(); 740 SDValue Lo = GetPromotedInteger(N->getOperand(0)); 741 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 742 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 743 744 Lo = DAG.getZeroExtendInReg(Lo, OVT); 745 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi, 746 DAG.getConstant(OVT.getSizeInBits(), 747 TLI.getShiftAmountTy())); 748 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi); 749} 750 751SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 752 // The vector type is legal but the element type is not. This implies 753 // that the vector is a power-of-two in length and that the element 754 // type does not have a strange size (eg: it is not i1). 755 MVT VecVT = N->getValueType(0); 756 unsigned NumElts = VecVT.getVectorNumElements(); 757 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 758 759 // Build a vector of half the length out of elements of twice the bitwidth. 760 // For example <4 x i16> -> <2 x i32>. 761 MVT OldVT = N->getOperand(0).getValueType(); 762 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 763 assert(OldVT.isSimple() && NewVT.isSimple()); 764 765 std::vector<SDValue> NewElts; 766 NewElts.reserve(NumElts/2); 767 768 for (unsigned i = 0; i < NumElts; i += 2) { 769 // Combine two successive elements into one promoted element. 770 SDValue Lo = N->getOperand(i); 771 SDValue Hi = N->getOperand(i+1); 772 if (TLI.isBigEndian()) 773 std::swap(Lo, Hi); 774 NewElts.push_back(JoinIntegers(Lo, Hi)); 775 } 776 777 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, 778 MVT::getVectorVT(NewVT, NewElts.size()), 779 &NewElts[0], NewElts.size()); 780 781 // Convert the new vector to the old vector type. 782 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); 783} 784 785SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 786 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 787 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 788 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 789 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 790 "can only promote integer arguments"); 791 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 792 return DAG.getConvertRndSat(N->getValueType(0), InOp, 793 N->getOperand(1), N->getOperand(2), 794 N->getOperand(3), N->getOperand(4), CvtCode); 795} 796 797SDValue DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) { 798 SDValue Op = GetPromotedInteger(N->getOperand(0)); 799 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op); 800} 801 802SDValue DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) { 803 SDValue Op = GetPromotedInteger(N->getOperand(0)); 804 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op, 805 DAG.getIntPtrConstant(0)); 806} 807 808SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 809 unsigned OpNo) { 810 if (OpNo == 1) { 811 // Promote the inserted value. This is valid because the type does not 812 // have to match the vector element type. 813 814 // Check that any extra bits introduced will be truncated away. 815 assert(N->getOperand(1).getValueType().getSizeInBits() >= 816 N->getValueType(0).getVectorElementType().getSizeInBits() && 817 "Type of inserted value narrower than vector element type!"); 818 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 819 GetPromotedInteger(N->getOperand(1)), 820 N->getOperand(2)); 821 } 822 823 assert(OpNo == 2 && "Different operand and result vector types?"); 824 825 // Promote the index. 826 SDValue Idx = N->getOperand(2); 827 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType()); 828 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 829 N->getOperand(1), Idx); 830} 831 832SDValue DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) { 833 SDValue In = GetPromotedInteger(N->getOperand(0)); 834 MVT OpVT = N->getOperand(0).getValueType(); 835 if (N->getOpcode() == ISD::UINT_TO_FP) 836 In = DAG.getZeroExtendInReg(In, OpVT); 837 else 838 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), 839 In, DAG.getValueType(OpVT)); 840 841 return DAG.UpdateNodeOperands(SDValue(N, 0), In); 842} 843 844SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 845 SDValue NewOps[6]; 846 NewOps[0] = N->getOperand(0); 847 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 848 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 849 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); 850 } 851 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, 852 array_lengthof(NewOps)); 853} 854 855SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 856 assert(OpNo == 0 && "Only know how to promote condition"); 857 SDValue Cond = GetPromotedInteger(N->getOperand(0)); 858 859 // Promote all the way up to SVT, the canonical SetCC type. 860 // FIXME: Not clear what value to pass to getSetCCResultType. 861 // [This only matters for CellSPU since all other targets 862 // ignore the argument.] We used to pass Cond, resulting in 863 // SVT = MVT::i8, but CellSPU has no select patterns for i8, 864 // causing an abort later. Passing the result type works 865 // around the problem. 866 MVT SVT = TLI.getSetCCResultType(N->getOperand(1)); 867 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 868 assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!"); 869 870 // Make sure the extra bits conform to getSetCCResultContents. There are 871 // two sets of extra bits: those in Cond, which come from type promotion, 872 // and those we need to add to have the final type be SVT (for most targets 873 // this last set of bits is empty). 874 unsigned CondBits = Cond.getValueSizeInBits(); 875 ISD::NodeType ExtendCode; 876 switch (TLI.getSetCCResultContents()) { 877 default: 878 assert(false && "Unknown SetCCResultValue!"); 879 case TargetLowering::UndefinedSetCCResult: 880 // Extend to SVT by adding rubbish. 881 ExtendCode = ISD::ANY_EXTEND; 882 break; 883 case TargetLowering::ZeroOrOneSetCCResult: 884 ExtendCode = ISD::ZERO_EXTEND; 885 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1))) 886 // All extra bits need to be cleared. Do this by zero extending the 887 // original condition value all the way to SVT. 888 Cond = N->getOperand(0); 889 break; 890 case TargetLowering::ZeroOrNegativeOneSetCCResult: { 891 ExtendCode = ISD::SIGN_EXTEND; 892 unsigned SignBits = DAG.ComputeNumSignBits(Cond); 893 if (SignBits != CondBits) 894 // All extra bits need to be sign extended. Do this by sign extending the 895 // original condition value all the way to SVT. 896 Cond = N->getOperand(0); 897 break; 898 } 899 } 900 Cond = DAG.getNode(ExtendCode, SVT, Cond); 901 902 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, 903 N->getOperand(1), N->getOperand(2)); 904} 905 906SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 907 assert(OpNo == 0 && "Don't know how to promote this operand!"); 908 909 SDValue LHS = N->getOperand(0); 910 SDValue RHS = N->getOperand(1); 911 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 912 913 // The CC (#4) and the possible return values (#2 and #3) have legal types. 914 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2), 915 N->getOperand(3), N->getOperand(4)); 916} 917 918SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 919 assert(OpNo == 0 && "Don't know how to promote this operand!"); 920 921 SDValue LHS = N->getOperand(0); 922 SDValue RHS = N->getOperand(1); 923 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 924 925 // The CC (#2) is always legal. 926 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); 927} 928 929SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 930 SDValue Op = GetPromotedInteger(N->getOperand(0)); 931 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 932 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), 933 Op, DAG.getValueType(N->getOperand(0).getValueType())); 934} 935 936SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 937 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 938 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 939 int SVOffset = N->getSrcValueOffset(); 940 unsigned Alignment = N->getAlignment(); 941 bool isVolatile = N->isVolatile(); 942 943 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 944 945 assert(!N->isTruncatingStore() && "Cannot promote this store operand!"); 946 947 // Truncate the value and store the result. 948 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(), 949 SVOffset, N->getMemoryVT(), 950 isVolatile, Alignment); 951} 952 953SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 954 SDValue Op = GetPromotedInteger(N->getOperand(0)); 955 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op); 956} 957 958SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 959 SDValue Op = GetPromotedInteger(N->getOperand(0)); 960 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 961 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); 962} 963 964 965//===----------------------------------------------------------------------===// 966// Integer Result Expansion 967//===----------------------------------------------------------------------===// 968 969/// ExpandIntegerResult - This method is called when the specified result of the 970/// specified node is found to need expansion. At this point, the node may also 971/// have invalid operands or may have other results that need promotion, we just 972/// know that (at least) one result needs expansion. 973void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 974 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n"); 975 SDValue Lo, Hi; 976 Lo = Hi = SDValue(); 977 978 // See if the target wants to custom expand this node. 979 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 980 TargetLowering::Custom) { 981 // If the target wants to, allow it to lower this itself. 982 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 983 // Everything that once used N now uses P. We are guaranteed that the 984 // result value types of N and the result value types of P match. 985 ReplaceNodeWith(N, P); 986 return; 987 } 988 } 989 990 switch (N->getOpcode()) { 991 default: 992#ifndef NDEBUG 993 cerr << "ExpandIntegerResult #" << ResNo << ": "; 994 N->dump(&DAG); cerr << "\n"; 995#endif 996 assert(0 && "Do not know how to expand the result of this operator!"); 997 abort(); 998 999 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 1000 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 1001 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 1002 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 1003 1004 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 1005 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 1006 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 1007 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 1008 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 1009 1010 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 1011 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 1012 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 1013 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 1014 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 1015 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 1016 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 1017 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 1018 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 1019 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 1020 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 1021 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 1022 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 1023 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 1024 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 1025 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 1026 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 1027 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 1028 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 1029 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 1030 1031 case ISD::AND: 1032 case ISD::OR: 1033 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 1034 1035 case ISD::ADD: 1036 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1037 1038 case ISD::ADDC: 1039 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1040 1041 case ISD::ADDE: 1042 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1043 1044 case ISD::SHL: 1045 case ISD::SRA: 1046 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1047 } 1048 1049 // If Lo/Hi is null, the sub-method took care of registering results etc. 1050 if (Lo.getNode()) 1051 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1052} 1053 1054/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1055/// and the shift amount is a constant 'Amt'. Expand the operation. 1056void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1057 SDValue &Lo, SDValue &Hi) { 1058 // Expand the incoming operand to be shifted, so that we have its parts 1059 SDValue InL, InH; 1060 GetExpandedInteger(N->getOperand(0), InL, InH); 1061 1062 MVT NVT = InL.getValueType(); 1063 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1064 unsigned NVTBits = NVT.getSizeInBits(); 1065 MVT ShTy = N->getOperand(1).getValueType(); 1066 1067 if (N->getOpcode() == ISD::SHL) { 1068 if (Amt > VTBits) { 1069 Lo = Hi = DAG.getConstant(0, NVT); 1070 } else if (Amt > NVTBits) { 1071 Lo = DAG.getConstant(0, NVT); 1072 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1073 } else if (Amt == NVTBits) { 1074 Lo = DAG.getConstant(0, NVT); 1075 Hi = InL; 1076 } else if (Amt == 1 && 1077 TLI.isOperationLegal(ISD::ADDC, TLI.getTypeToExpandTo(NVT))) { 1078 // Emit this X << 1 as X+X. 1079 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1080 SDValue LoOps[2] = { InL, InL }; 1081 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1082 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1083 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1084 } else { 1085 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1086 Hi = DAG.getNode(ISD::OR, NVT, 1087 DAG.getNode(ISD::SHL, NVT, InH, 1088 DAG.getConstant(Amt, ShTy)), 1089 DAG.getNode(ISD::SRL, NVT, InL, 1090 DAG.getConstant(NVTBits-Amt, ShTy))); 1091 } 1092 return; 1093 } 1094 1095 if (N->getOpcode() == ISD::SRL) { 1096 if (Amt > VTBits) { 1097 Lo = DAG.getConstant(0, NVT); 1098 Hi = DAG.getConstant(0, NVT); 1099 } else if (Amt > NVTBits) { 1100 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1101 Hi = DAG.getConstant(0, NVT); 1102 } else if (Amt == NVTBits) { 1103 Lo = InH; 1104 Hi = DAG.getConstant(0, NVT); 1105 } else { 1106 Lo = DAG.getNode(ISD::OR, NVT, 1107 DAG.getNode(ISD::SRL, NVT, InL, 1108 DAG.getConstant(Amt, ShTy)), 1109 DAG.getNode(ISD::SHL, NVT, InH, 1110 DAG.getConstant(NVTBits-Amt, ShTy))); 1111 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1112 } 1113 return; 1114 } 1115 1116 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1117 if (Amt > VTBits) { 1118 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 1119 DAG.getConstant(NVTBits-1, ShTy)); 1120 } else if (Amt > NVTBits) { 1121 Lo = DAG.getNode(ISD::SRA, NVT, InH, 1122 DAG.getConstant(Amt-NVTBits, ShTy)); 1123 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1124 DAG.getConstant(NVTBits-1, ShTy)); 1125 } else if (Amt == NVTBits) { 1126 Lo = InH; 1127 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1128 DAG.getConstant(NVTBits-1, ShTy)); 1129 } else { 1130 Lo = DAG.getNode(ISD::OR, NVT, 1131 DAG.getNode(ISD::SRL, NVT, InL, 1132 DAG.getConstant(Amt, ShTy)), 1133 DAG.getNode(ISD::SHL, NVT, InH, 1134 DAG.getConstant(NVTBits-Amt, ShTy))); 1135 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy)); 1136 } 1137} 1138 1139/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1140/// this shift based on knowledge of the high bit of the shift amount. If we 1141/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1142/// shift amount. 1143bool DAGTypeLegalizer:: 1144ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1145 SDValue Amt = N->getOperand(1); 1146 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1147 MVT ShTy = Amt.getValueType(); 1148 unsigned ShBits = ShTy.getSizeInBits(); 1149 unsigned NVTBits = NVT.getSizeInBits(); 1150 assert(isPowerOf2_32(NVTBits) && 1151 "Expanded integer type size not a power of two!"); 1152 1153 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1154 APInt KnownZero, KnownOne; 1155 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1156 1157 // If we don't know anything about the high bits, exit. 1158 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1159 return false; 1160 1161 // Get the incoming operand to be shifted. 1162 SDValue InL, InH; 1163 GetExpandedInteger(N->getOperand(0), InL, InH); 1164 1165 // If we know that any of the high bits of the shift amount are one, then we 1166 // can do this as a couple of simple shifts. 1167 if (KnownOne.intersects(HighBitMask)) { 1168 // Mask out the high bit, which we know is set. 1169 Amt = DAG.getNode(ISD::AND, ShTy, Amt, 1170 DAG.getConstant(~HighBitMask, ShTy)); 1171 1172 switch (N->getOpcode()) { 1173 default: assert(0 && "Unknown shift"); 1174 case ISD::SHL: 1175 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1176 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 1177 return true; 1178 case ISD::SRL: 1179 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1180 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 1181 return true; 1182 case ISD::SRA: 1183 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 1184 DAG.getConstant(NVTBits-1, ShTy)); 1185 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 1186 return true; 1187 } 1188 } 1189 1190 // If we know that all of the high bits of the shift amount are zero, then we 1191 // can do this as a couple of simple shifts. 1192 if ((KnownZero & HighBitMask) == HighBitMask) { 1193 // Compute 32-amt. 1194 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1195 DAG.getConstant(NVTBits, ShTy), 1196 Amt); 1197 unsigned Op1, Op2; 1198 switch (N->getOpcode()) { 1199 default: assert(0 && "Unknown shift"); 1200 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1201 case ISD::SRL: 1202 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1203 } 1204 1205 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1206 Hi = DAG.getNode(ISD::OR, NVT, 1207 DAG.getNode(Op1, NVT, InH, Amt), 1208 DAG.getNode(Op2, NVT, InL, Amt2)); 1209 return true; 1210 } 1211 1212 return false; 1213} 1214 1215void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1216 SDValue &Lo, SDValue &Hi) { 1217 // Expand the subcomponents. 1218 SDValue LHSL, LHSH, RHSL, RHSH; 1219 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1220 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1221 1222 MVT NVT = LHSL.getValueType(); 1223 SDValue LoOps[2] = { LHSL, RHSL }; 1224 SDValue HiOps[3] = { LHSH, RHSH }; 1225 1226 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1227 // them. TODO: Teach operation legalization how to expand unsupported 1228 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1229 // a carry of type MVT::Flag, but there doesn't seem to be any way to 1230 // generate a value of this type in the expanded code sequence. 1231 bool hasCarry = 1232 TLI.isOperationLegal(N->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC, 1233 TLI.getTypeToExpandTo(NVT)); 1234 1235 if (hasCarry) { 1236 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1237 if (N->getOpcode() == ISD::ADD) { 1238 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1239 HiOps[2] = Lo.getValue(1); 1240 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1241 } else { 1242 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1243 HiOps[2] = Lo.getValue(1); 1244 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1245 } 1246 } else { 1247 if (N->getOpcode() == ISD::ADD) { 1248 Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2); 1249 Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2); 1250 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0], 1251 ISD::SETULT); 1252 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, 1253 DAG.getConstant(1, NVT), 1254 DAG.getConstant(0, NVT)); 1255 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[1], 1256 ISD::SETULT); 1257 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2, 1258 DAG.getConstant(1, NVT), Carry1); 1259 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2); 1260 } else { 1261 Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2); 1262 Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2); 1263 SDValue Cmp = DAG.getSetCC(TLI.getSetCCResultType(LoOps[0]), 1264 LoOps[0], LoOps[1], ISD::SETULT); 1265 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp, 1266 DAG.getConstant(1, NVT), 1267 DAG.getConstant(0, NVT)); 1268 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow); 1269 } 1270 } 1271} 1272 1273void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1274 SDValue &Lo, SDValue &Hi) { 1275 // Expand the subcomponents. 1276 SDValue LHSL, LHSH, RHSL, RHSH; 1277 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1278 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1279 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1280 SDValue LoOps[2] = { LHSL, RHSL }; 1281 SDValue HiOps[3] = { LHSH, RHSH }; 1282 1283 if (N->getOpcode() == ISD::ADDC) { 1284 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1285 HiOps[2] = Lo.getValue(1); 1286 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1287 } else { 1288 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1289 HiOps[2] = Lo.getValue(1); 1290 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1291 } 1292 1293 // Legalized the flag result - switch anything that used the old flag to 1294 // use the new one. 1295 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1296} 1297 1298void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1299 SDValue &Lo, SDValue &Hi) { 1300 // Expand the subcomponents. 1301 SDValue LHSL, LHSH, RHSL, RHSH; 1302 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1303 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1304 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1305 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1306 SDValue HiOps[3] = { LHSH, RHSH }; 1307 1308 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3); 1309 HiOps[2] = Lo.getValue(1); 1310 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3); 1311 1312 // Legalized the flag result - switch anything that used the old flag to 1313 // use the new one. 1314 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1315} 1316 1317void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1318 SDValue &Lo, SDValue &Hi) { 1319 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1320 SDValue Op = N->getOperand(0); 1321 if (Op.getValueType().bitsLE(NVT)) { 1322 // The low part is any extension of the input (which degenerates to a copy). 1323 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op); 1324 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined. 1325 } else { 1326 // For example, extension of an i48 to an i64. The operand type necessarily 1327 // promotes to the result type, so will end up being expanded too. 1328 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1329 "Only know how to promote this result!"); 1330 SDValue Res = GetPromotedInteger(Op); 1331 assert(Res.getValueType() == N->getValueType(0) && 1332 "Operand over promoted?"); 1333 // Split the promoted operand. This will simplify when it is expanded. 1334 SplitInteger(Res, Lo, Hi); 1335 } 1336} 1337 1338void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1339 SDValue &Lo, SDValue &Hi) { 1340 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1341 MVT NVT = Lo.getValueType(); 1342 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1343 unsigned NVTBits = NVT.getSizeInBits(); 1344 unsigned EVTBits = EVT.getSizeInBits(); 1345 1346 if (NVTBits < EVTBits) { 1347 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi, 1348 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1349 } else { 1350 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT)); 1351 // The high part replicates the sign bit of Lo, make it explicit. 1352 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1353 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy())); 1354 } 1355} 1356 1357void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1358 SDValue &Lo, SDValue &Hi) { 1359 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1360 MVT NVT = Lo.getValueType(); 1361 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1362 unsigned NVTBits = NVT.getSizeInBits(); 1363 unsigned EVTBits = EVT.getSizeInBits(); 1364 1365 if (NVTBits < EVTBits) { 1366 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, 1367 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1368 } else { 1369 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); 1370 // The high part must be zero, make it explicit. 1371 Hi = DAG.getConstant(0, NVT); 1372 } 1373} 1374 1375void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1376 SDValue &Lo, SDValue &Hi) { 1377 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1378 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo); 1379 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi); 1380} 1381 1382void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1383 SDValue &Lo, SDValue &Hi) { 1384 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1385 unsigned NBitWidth = NVT.getSizeInBits(); 1386 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1387 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 1388 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1389} 1390 1391void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1392 SDValue &Lo, SDValue &Hi) { 1393 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1394 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1395 MVT NVT = Lo.getValueType(); 1396 1397 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 1398 DAG.getConstant(0, NVT), ISD::SETNE); 1399 1400 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo); 1401 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 1402 1403 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ, 1404 DAG.getNode(ISD::ADD, NVT, LoLZ, 1405 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1406 Hi = DAG.getConstant(0, NVT); 1407} 1408 1409void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1410 SDValue &Lo, SDValue &Hi) { 1411 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1412 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1413 MVT NVT = Lo.getValueType(); 1414 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), 1415 DAG.getNode(ISD::CTPOP, NVT, Hi)); 1416 Hi = DAG.getConstant(0, NVT); 1417} 1418 1419void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1420 SDValue &Lo, SDValue &Hi) { 1421 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1422 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1423 MVT NVT = Lo.getValueType(); 1424 1425 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, 1426 DAG.getConstant(0, NVT), ISD::SETNE); 1427 1428 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 1429 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi); 1430 1431 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ, 1432 DAG.getNode(ISD::ADD, NVT, HiLZ, 1433 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1434 Hi = DAG.getConstant(0, NVT); 1435} 1436 1437void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1438 SDValue &Hi) { 1439 MVT VT = N->getValueType(0); 1440 SDValue Op = N->getOperand(0); 1441 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1442 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1443 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi); 1444} 1445 1446void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1447 SDValue &Hi) { 1448 MVT VT = N->getValueType(0); 1449 SDValue Op = N->getOperand(0); 1450 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1451 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1452 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi); 1453} 1454 1455void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1456 SDValue &Lo, SDValue &Hi) { 1457 if (ISD::isNormalLoad(N)) { 1458 ExpandRes_NormalLoad(N, Lo, Hi); 1459 return; 1460 } 1461 1462 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1463 1464 MVT VT = N->getValueType(0); 1465 MVT NVT = TLI.getTypeToTransformTo(VT); 1466 SDValue Ch = N->getChain(); 1467 SDValue Ptr = N->getBasePtr(); 1468 ISD::LoadExtType ExtType = N->getExtensionType(); 1469 int SVOffset = N->getSrcValueOffset(); 1470 unsigned Alignment = N->getAlignment(); 1471 bool isVolatile = N->isVolatile(); 1472 1473 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1474 1475 if (N->getMemoryVT().bitsLE(NVT)) { 1476 MVT EVT = N->getMemoryVT(); 1477 1478 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, 1479 isVolatile, Alignment); 1480 1481 // Remember the chain. 1482 Ch = Lo.getValue(1); 1483 1484 if (ExtType == ISD::SEXTLOAD) { 1485 // The high part is obtained by SRA'ing all but one of the bits of the 1486 // lo part. 1487 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1488 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1489 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1490 } else if (ExtType == ISD::ZEXTLOAD) { 1491 // The high part is just a zero. 1492 Hi = DAG.getConstant(0, NVT); 1493 } else { 1494 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1495 // The high part is undefined. 1496 Hi = DAG.getNode(ISD::UNDEF, NVT); 1497 } 1498 } else if (TLI.isLittleEndian()) { 1499 // Little-endian - low bits are at low addresses. 1500 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1501 isVolatile, Alignment); 1502 1503 unsigned ExcessBits = 1504 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1505 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1506 1507 // Increment the pointer to the other half. 1508 unsigned IncrementSize = NVT.getSizeInBits()/8; 1509 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1510 DAG.getIntPtrConstant(IncrementSize)); 1511 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), 1512 SVOffset+IncrementSize, NEVT, 1513 isVolatile, MinAlign(Alignment, IncrementSize)); 1514 1515 // Build a factor node to remember that this load is independent of the 1516 // other one. 1517 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1518 Hi.getValue(1)); 1519 } else { 1520 // Big-endian - high bits are at low addresses. Favor aligned loads at 1521 // the cost of some bit-fiddling. 1522 MVT EVT = N->getMemoryVT(); 1523 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1524 unsigned IncrementSize = NVT.getSizeInBits()/8; 1525 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1526 1527 // Load both the high bits and maybe some of the low bits. 1528 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1529 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1530 isVolatile, Alignment); 1531 1532 // Increment the pointer to the other half. 1533 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1534 DAG.getIntPtrConstant(IncrementSize)); 1535 // Load the rest of the low bits. 1536 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(), 1537 SVOffset+IncrementSize, 1538 MVT::getIntegerVT(ExcessBits), 1539 isVolatile, MinAlign(Alignment, IncrementSize)); 1540 1541 // Build a factor node to remember that this load is independent of the 1542 // other one. 1543 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1544 Hi.getValue(1)); 1545 1546 if (ExcessBits < NVT.getSizeInBits()) { 1547 // Transfer low bits from the bottom of Hi to the top of Lo. 1548 Lo = DAG.getNode(ISD::OR, NVT, Lo, 1549 DAG.getNode(ISD::SHL, NVT, Hi, 1550 DAG.getConstant(ExcessBits, 1551 TLI.getShiftAmountTy()))); 1552 // Move high bits to the right position in Hi. 1553 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi, 1554 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1555 TLI.getShiftAmountTy())); 1556 } 1557 } 1558 1559 // Legalized the chain result - switch anything that used the old chain to 1560 // use the new one. 1561 ReplaceValueWith(SDValue(N, 1), Ch); 1562} 1563 1564void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1565 SDValue &Lo, SDValue &Hi) { 1566 SDValue LL, LH, RL, RH; 1567 GetExpandedInteger(N->getOperand(0), LL, LH); 1568 GetExpandedInteger(N->getOperand(1), RL, RH); 1569 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL); 1570 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH); 1571} 1572 1573void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1574 SDValue &Lo, SDValue &Hi) { 1575 MVT VT = N->getValueType(0); 1576 MVT NVT = TLI.getTypeToTransformTo(VT); 1577 1578 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 1579 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 1580 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 1581 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 1582 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1583 SDValue LL, LH, RL, RH; 1584 GetExpandedInteger(N->getOperand(0), LL, LH); 1585 GetExpandedInteger(N->getOperand(1), RL, RH); 1586 unsigned OuterBitSize = VT.getSizeInBits(); 1587 unsigned InnerBitSize = NVT.getSizeInBits(); 1588 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1589 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1590 1591 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1592 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1593 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1594 // The inputs are both zero-extended. 1595 if (HasUMUL_LOHI) { 1596 // We can emit a umul_lohi. 1597 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1598 Hi = SDValue(Lo.getNode(), 1); 1599 return; 1600 } 1601 if (HasMULHU) { 1602 // We can emit a mulhu+mul. 1603 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1604 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1605 return; 1606 } 1607 } 1608 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1609 // The input values are both sign-extended. 1610 if (HasSMUL_LOHI) { 1611 // We can emit a smul_lohi. 1612 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1613 Hi = SDValue(Lo.getNode(), 1); 1614 return; 1615 } 1616 if (HasMULHS) { 1617 // We can emit a mulhs+mul. 1618 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1619 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 1620 return; 1621 } 1622 } 1623 if (HasUMUL_LOHI) { 1624 // Lo,Hi = umul LHS, RHS. 1625 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 1626 DAG.getVTList(NVT, NVT), LL, RL); 1627 Lo = UMulLOHI; 1628 Hi = UMulLOHI.getValue(1); 1629 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1630 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1631 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1632 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1633 return; 1634 } 1635 if (HasMULHU) { 1636 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1637 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1638 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1639 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1640 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1641 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1642 return; 1643 } 1644 } 1645 1646 // If nothing else, we can make a libcall. 1647 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1648 if (VT == MVT::i32) 1649 LC = RTLIB::MUL_I32; 1650 else if (VT == MVT::i64) 1651 LC = RTLIB::MUL_I64; 1652 else if (VT == MVT::i128) 1653 LC = RTLIB::MUL_I128; 1654 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1655 1656 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1657 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi); 1658} 1659 1660void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1661 SDValue &Lo, SDValue &Hi) { 1662 MVT VT = N->getValueType(0); 1663 1664 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1665 if (VT == MVT::i32) 1666 LC = RTLIB::SDIV_I32; 1667 else if (VT == MVT::i64) 1668 LC = RTLIB::SDIV_I64; 1669 else if (VT == MVT::i128) 1670 LC = RTLIB::SDIV_I128; 1671 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1672 1673 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1674 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1675} 1676 1677void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1678 SDValue &Lo, SDValue &Hi) { 1679 MVT VT = N->getValueType(0); 1680 1681 // If we can emit an efficient shift operation, do so now. Check to see if 1682 // the RHS is a constant. 1683 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1684 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1685 1686 // If we can determine that the high bit of the shift is zero or one, even if 1687 // the low bits are variable, emit this shift in an optimized form. 1688 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1689 return; 1690 1691 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1692 unsigned PartsOpc; 1693 if (N->getOpcode() == ISD::SHL) { 1694 PartsOpc = ISD::SHL_PARTS; 1695 } else if (N->getOpcode() == ISD::SRL) { 1696 PartsOpc = ISD::SRL_PARTS; 1697 } else { 1698 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1699 PartsOpc = ISD::SRA_PARTS; 1700 } 1701 1702 // Next check to see if the target supports this SHL_PARTS operation or if it 1703 // will custom expand it. 1704 MVT NVT = TLI.getTypeToTransformTo(VT); 1705 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1706 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1707 Action == TargetLowering::Custom) { 1708 // Expand the subcomponents. 1709 SDValue LHSL, LHSH; 1710 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1711 1712 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1713 MVT VT = LHSL.getValueType(); 1714 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 1715 Hi = Lo.getValue(1); 1716 return; 1717 } 1718 1719 // Otherwise, emit a libcall. 1720 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1721 bool isSigned; 1722 if (N->getOpcode() == ISD::SHL) { 1723 isSigned = false; /*sign irrelevant*/ 1724 if (VT == MVT::i32) 1725 LC = RTLIB::SHL_I32; 1726 else if (VT == MVT::i64) 1727 LC = RTLIB::SHL_I64; 1728 else if (VT == MVT::i128) 1729 LC = RTLIB::SHL_I128; 1730 } else if (N->getOpcode() == ISD::SRL) { 1731 isSigned = false; 1732 if (VT == MVT::i32) 1733 LC = RTLIB::SRL_I32; 1734 else if (VT == MVT::i64) 1735 LC = RTLIB::SRL_I64; 1736 else if (VT == MVT::i128) 1737 LC = RTLIB::SRL_I128; 1738 } else { 1739 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1740 isSigned = true; 1741 if (VT == MVT::i32) 1742 LC = RTLIB::SRA_I32; 1743 else if (VT == MVT::i64) 1744 LC = RTLIB::SRA_I64; 1745 else if (VT == MVT::i128) 1746 LC = RTLIB::SRA_I128; 1747 } 1748 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!"); 1749 1750 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1751 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi); 1752} 1753 1754void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 1755 SDValue &Lo, SDValue &Hi) { 1756 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1757 SDValue Op = N->getOperand(0); 1758 if (Op.getValueType().bitsLE(NVT)) { 1759 // The low part is sign extension of the input (degenerates to a copy). 1760 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); 1761 // The high part is obtained by SRA'ing all but one of the bits of low part. 1762 unsigned LoSize = NVT.getSizeInBits(); 1763 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1764 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1765 } else { 1766 // For example, extension of an i48 to an i64. The operand type necessarily 1767 // promotes to the result type, so will end up being expanded too. 1768 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1769 "Only know how to promote this result!"); 1770 SDValue Res = GetPromotedInteger(Op); 1771 assert(Res.getValueType() == N->getValueType(0) && 1772 "Operand over promoted?"); 1773 // Split the promoted operand. This will simplify when it is expanded. 1774 SplitInteger(Res, Lo, Hi); 1775 unsigned ExcessBits = 1776 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1777 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 1778 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1779 } 1780} 1781 1782void DAGTypeLegalizer:: 1783ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 1784 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1785 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1786 1787 if (EVT.bitsLE(Lo.getValueType())) { 1788 // sext_inreg the low part if needed. 1789 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo, 1790 N->getOperand(1)); 1791 1792 // The high part gets the sign extension from the lo-part. This handles 1793 // things like sextinreg V:i64 from i8. 1794 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo, 1795 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 1796 TLI.getShiftAmountTy())); 1797 } else { 1798 // For example, extension of an i48 to an i64. Leave the low part alone, 1799 // sext_inreg the high part. 1800 unsigned ExcessBits = 1801 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 1802 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 1803 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1804 } 1805} 1806 1807void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1808 SDValue &Lo, SDValue &Hi) { 1809 MVT VT = N->getValueType(0); 1810 1811 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1812 if (VT == MVT::i32) 1813 LC = RTLIB::SREM_I32; 1814 else if (VT == MVT::i64) 1815 LC = RTLIB::SREM_I64; 1816 else if (VT == MVT::i128) 1817 LC = RTLIB::SREM_I128; 1818 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1819 1820 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1821 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1822} 1823 1824void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 1825 SDValue &Lo, SDValue &Hi) { 1826 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1827 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); 1828 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), 1829 DAG.getConstant(NVT.getSizeInBits(), 1830 TLI.getShiftAmountTy())); 1831 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); 1832} 1833 1834void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1835 SDValue &Lo, SDValue &Hi) { 1836 MVT VT = N->getValueType(0); 1837 1838 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1839 if (VT == MVT::i32) 1840 LC = RTLIB::UDIV_I32; 1841 else if (VT == MVT::i64) 1842 LC = RTLIB::UDIV_I64; 1843 else if (VT == MVT::i128) 1844 LC = RTLIB::UDIV_I128; 1845 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 1846 1847 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1848 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1849} 1850 1851void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1852 SDValue &Lo, SDValue &Hi) { 1853 MVT VT = N->getValueType(0); 1854 1855 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1856 if (VT == MVT::i32) 1857 LC = RTLIB::UREM_I32; 1858 else if (VT == MVT::i64) 1859 LC = RTLIB::UREM_I64; 1860 else if (VT == MVT::i128) 1861 LC = RTLIB::UREM_I128; 1862 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 1863 1864 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1865 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1866} 1867 1868void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 1869 SDValue &Lo, SDValue &Hi) { 1870 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1871 SDValue Op = N->getOperand(0); 1872 if (Op.getValueType().bitsLE(NVT)) { 1873 // The low part is zero extension of the input (degenerates to a copy). 1874 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); 1875 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 1876 } else { 1877 // For example, extension of an i48 to an i64. The operand type necessarily 1878 // promotes to the result type, so will end up being expanded too. 1879 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1880 "Only know how to promote this result!"); 1881 SDValue Res = GetPromotedInteger(Op); 1882 assert(Res.getValueType() == N->getValueType(0) && 1883 "Operand over promoted?"); 1884 // Split the promoted operand. This will simplify when it is expanded. 1885 SplitInteger(Res, Lo, Hi); 1886 unsigned ExcessBits = 1887 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1888 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); 1889 } 1890} 1891 1892 1893//===----------------------------------------------------------------------===// 1894// Integer Operand Expansion 1895//===----------------------------------------------------------------------===// 1896 1897/// ExpandIntegerOperand - This method is called when the specified operand of 1898/// the specified node is found to need expansion. At this point, all of the 1899/// result types of the node are known to be legal, but other operands of the 1900/// node may need promotion or expansion as well as the specified one. 1901bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1902 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); 1903 SDValue Res = SDValue(); 1904 1905 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 1906 == TargetLowering::Custom) 1907 Res = TLI.LowerOperation(SDValue(N, 0), DAG); 1908 1909 if (Res.getNode() == 0) { 1910 switch (N->getOpcode()) { 1911 default: 1912 #ifndef NDEBUG 1913 cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; 1914 N->dump(&DAG); cerr << "\n"; 1915 #endif 1916 assert(0 && "Do not know how to expand this operator's operand!"); 1917 abort(); 1918 1919 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1920 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1921 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1922 1923 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1924 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1925 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1926 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 1927 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); 1928 break; 1929 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1930 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 1931 } 1932 } 1933 1934 // If the result is null, the sub-method took care of registering results etc. 1935 if (!Res.getNode()) return false; 1936 // If the result is N, the sub-method updated N in place. Check to see if any 1937 // operands are new, and if so, mark them. 1938 if (Res.getNode() == N) { 1939 // Mark N as new and remark N and its operands. This allows us to correctly 1940 // revisit N if it needs another step of expansion and allows us to visit 1941 // any new operands to N. 1942 ReanalyzeNode(N); 1943 return true; 1944 } 1945 1946 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1947 "Invalid operand expansion"); 1948 1949 ReplaceValueWith(SDValue(N, 0), Res); 1950 return false; 1951} 1952 1953/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 1954/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1955void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 1956 SDValue &NewRHS, 1957 ISD::CondCode &CCCode) { 1958 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 1959 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 1960 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 1961 1962 MVT VT = NewLHS.getValueType(); 1963 1964 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 1965 if (RHSLo == RHSHi) { 1966 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 1967 if (RHSCST->isAllOnesValue()) { 1968 // Equality comparison to -1. 1969 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1970 NewRHS = RHSLo; 1971 return; 1972 } 1973 } 1974 } 1975 1976 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1977 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1978 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS); 1979 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1980 return; 1981 } 1982 1983 // If this is a comparison of the sign bit, just look at the top part. 1984 // X > -1, x < 0 1985 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 1986 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 1987 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 1988 NewLHS = LHSHi; 1989 NewRHS = RHSHi; 1990 return; 1991 } 1992 1993 // FIXME: This generated code sucks. 1994 ISD::CondCode LowCC; 1995 switch (CCCode) { 1996 default: assert(0 && "Unknown integer setcc!"); 1997 case ISD::SETLT: 1998 case ISD::SETULT: LowCC = ISD::SETULT; break; 1999 case ISD::SETGT: 2000 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2001 case ISD::SETLE: 2002 case ISD::SETULE: LowCC = ISD::SETULE; break; 2003 case ISD::SETGE: 2004 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2005 } 2006 2007 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2008 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2009 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2010 2011 // NOTE: on targets without efficient SELECT of bools, we can always use 2012 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2013 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 2014 SDValue Tmp1, Tmp2; 2015 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC, 2016 false, DagCombineInfo); 2017 if (!Tmp1.getNode()) 2018 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 2019 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2020 CCCode, false, DagCombineInfo); 2021 if (!Tmp2.getNode()) 2022 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2023 DAG.getCondCode(CCCode)); 2024 2025 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2026 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2027 if ((Tmp1C && Tmp1C->isNullValue()) || 2028 (Tmp2C && Tmp2C->isNullValue() && 2029 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2030 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2031 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2032 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2033 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2034 // low part is known false, returns high part. 2035 // For LE / GE, if high part is known false, ignore the low part. 2036 // For LT / GT, if high part is known true, ignore the low part. 2037 NewLHS = Tmp2; 2038 NewRHS = SDValue(); 2039 return; 2040 } 2041 2042 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2043 ISD::SETEQ, false, DagCombineInfo); 2044 if (!NewLHS.getNode()) 2045 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2046 ISD::SETEQ); 2047 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 2048 NewLHS, Tmp1, Tmp2); 2049 NewRHS = SDValue(); 2050} 2051 2052SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2053 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2054 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2055 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2056 2057 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2058 // against zero to select between true and false values. 2059 if (NewRHS.getNode() == 0) { 2060 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2061 CCCode = ISD::SETNE; 2062 } 2063 2064 // Update N to have the operands specified. 2065 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 2066 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2067 N->getOperand(4)); 2068} 2069 2070SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2071 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2072 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2073 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2074 2075 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2076 // against zero to select between true and false values. 2077 if (NewRHS.getNode() == 0) { 2078 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2079 CCCode = ISD::SETNE; 2080 } 2081 2082 // Update N to have the operands specified. 2083 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2084 N->getOperand(2), N->getOperand(3), 2085 DAG.getCondCode(CCCode)); 2086} 2087 2088SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2089 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2090 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2091 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2092 2093 // If ExpandSetCCOperands returned a scalar, use it. 2094 if (NewRHS.getNode() == 0) { 2095 assert(NewLHS.getValueType() == N->getValueType(0) && 2096 "Unexpected setcc expansion!"); 2097 return NewLHS; 2098 } 2099 2100 // Otherwise, update N to have the operands specified. 2101 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2102 DAG.getCondCode(CCCode)); 2103} 2104 2105SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2106 SDValue Op = N->getOperand(0); 2107 MVT DstVT = N->getValueType(0); 2108 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2109 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2110 "Don't know how to expand this SINT_TO_FP!"); 2111 return MakeLibCall(LC, DstVT, &Op, 1, true); 2112} 2113 2114SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2115 if (ISD::isNormalStore(N)) 2116 return ExpandOp_NormalStore(N, OpNo); 2117 2118 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2119 assert(OpNo == 1 && "Can only expand the stored value so far"); 2120 2121 MVT VT = N->getOperand(1).getValueType(); 2122 MVT NVT = TLI.getTypeToTransformTo(VT); 2123 SDValue Ch = N->getChain(); 2124 SDValue Ptr = N->getBasePtr(); 2125 int SVOffset = N->getSrcValueOffset(); 2126 unsigned Alignment = N->getAlignment(); 2127 bool isVolatile = N->isVolatile(); 2128 SDValue Lo, Hi; 2129 2130 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2131 2132 if (N->getMemoryVT().bitsLE(NVT)) { 2133 GetExpandedInteger(N->getValue(), Lo, Hi); 2134 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 2135 N->getMemoryVT(), isVolatile, Alignment); 2136 } else if (TLI.isLittleEndian()) { 2137 // Little-endian - low bits are at low addresses. 2138 GetExpandedInteger(N->getValue(), Lo, Hi); 2139 2140 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 2141 isVolatile, Alignment); 2142 2143 unsigned ExcessBits = 2144 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2145 MVT NEVT = MVT::getIntegerVT(ExcessBits); 2146 2147 // Increment the pointer to the other half. 2148 unsigned IncrementSize = NVT.getSizeInBits()/8; 2149 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2150 DAG.getIntPtrConstant(IncrementSize)); 2151 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2152 SVOffset+IncrementSize, NEVT, 2153 isVolatile, MinAlign(Alignment, IncrementSize)); 2154 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2155 } else { 2156 // Big-endian - high bits are at low addresses. Favor aligned stores at 2157 // the cost of some bit-fiddling. 2158 GetExpandedInteger(N->getValue(), Lo, Hi); 2159 2160 MVT EVT = N->getMemoryVT(); 2161 unsigned EBytes = EVT.getStoreSizeInBits()/8; 2162 unsigned IncrementSize = NVT.getSizeInBits()/8; 2163 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2164 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 2165 2166 if (ExcessBits < NVT.getSizeInBits()) { 2167 // Transfer high bits from the top of Lo to the bottom of Hi. 2168 Hi = DAG.getNode(ISD::SHL, NVT, Hi, 2169 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2170 TLI.getShiftAmountTy())); 2171 Hi = DAG.getNode(ISD::OR, NVT, Hi, 2172 DAG.getNode(ISD::SRL, NVT, Lo, 2173 DAG.getConstant(ExcessBits, 2174 TLI.getShiftAmountTy()))); 2175 } 2176 2177 // Store both the high bits and maybe some of the low bits. 2178 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2179 SVOffset, HiVT, isVolatile, Alignment); 2180 2181 // Increment the pointer to the other half. 2182 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2183 DAG.getIntPtrConstant(IncrementSize)); 2184 // Store the lowest ExcessBits bits in the second half. 2185 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), 2186 SVOffset+IncrementSize, 2187 MVT::getIntegerVT(ExcessBits), 2188 isVolatile, MinAlign(Alignment, IncrementSize)); 2189 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2190 } 2191} 2192 2193SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2194 SDValue InL, InH; 2195 GetExpandedInteger(N->getOperand(0), InL, InH); 2196 // Just truncate the low part of the source. 2197 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL); 2198} 2199 2200SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2201 SDValue Op = N->getOperand(0); 2202 MVT SrcVT = Op.getValueType(); 2203 MVT DstVT = N->getValueType(0); 2204 2205 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2206 // Do a signed conversion then adjust the result. 2207 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op); 2208 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2209 2210 // The result of the signed conversion needs adjusting if the 'sign bit' of 2211 // the incoming integer was set. To handle this, we dynamically test to see 2212 // if it is set, and, if so, add a fudge factor. 2213 2214 const uint64_t F32TwoE32 = 0x4F800000ULL; 2215 const uint64_t F32TwoE64 = 0x5F800000ULL; 2216 const uint64_t F32TwoE128 = 0x7F800000ULL; 2217 2218 APInt FF(32, 0); 2219 if (SrcVT == MVT::i32) 2220 FF = APInt(32, F32TwoE32); 2221 else if (SrcVT == MVT::i64) 2222 FF = APInt(32, F32TwoE64); 2223 else if (SrcVT == MVT::i128) 2224 FF = APInt(32, F32TwoE128); 2225 else 2226 assert(false && "Unsupported UINT_TO_FP!"); 2227 2228 // Check whether the sign bit is set. 2229 SDValue Lo, Hi; 2230 GetExpandedInteger(Op, Lo, Hi); 2231 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 2232 DAG.getConstant(0, Hi.getValueType()), 2233 ISD::SETLT); 2234 2235 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2236 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)), 2237 TLI.getPointerTy()); 2238 2239 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2240 SDValue Zero = DAG.getIntPtrConstant(0); 2241 SDValue Four = DAG.getIntPtrConstant(4); 2242 if (TLI.isBigEndian()) std::swap(Zero, Four); 2243 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet, 2244 Zero, Four); 2245 unsigned Alignment = 2246 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2247 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset); 2248 Alignment = std::min(Alignment, 4u); 2249 2250 // Load the value out, extending it from f32 to the destination float type. 2251 // FIXME: Avoid the extend by constructing the right constant pool? 2252 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(), 2253 FudgePtr, NULL, 0, MVT::f32, 2254 false, Alignment); 2255 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge); 2256 } 2257 2258 // Otherwise, use a libcall. 2259 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2260 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2261 "Don't know how to expand this UINT_TO_FP!"); 2262 return MakeLibCall(LC, DstVT, &Op, 1, true); 2263} 2264