LegalizeIntegerTypes.cpp revision 3e1c701db4f40baa420d7e829d92b2e7ed003e3f
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22using namespace llvm; 23 24//===----------------------------------------------------------------------===// 25// Integer Result Promotion 26//===----------------------------------------------------------------------===// 27 28/// PromoteIntegerResult - This method is called when a result of a node is 29/// found to be in need of promotion to a larger type. At this point, the node 30/// may also have invalid operands or may have other results that need 31/// expansion, we just know that (at least) one result needs promotion. 32void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); 34 SDOperand Result = SDOperand(); 35 36 // See if the target wants to custom expand this node. 37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 38 TargetLowering::Custom) { 39 // If the target wants to, allow it to lower this itself. 40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 41 // Everything that once used N now uses P. We are guaranteed that the 42 // result value types of N and the result value types of P match. 43 ReplaceNodeWith(N, P); 44 return; 45 } 46 } 47 48 switch (N->getOpcode()) { 49 default: 50#ifndef NDEBUG 51 cerr << "PromoteIntegerResult #" << ResNo << ": "; 52 N->dump(&DAG); cerr << "\n"; 53#endif 54 assert(0 && "Do not know how to promote this operator!"); 55 abort(); 56 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break; 57 case ISD::Constant: Result = PromoteIntRes_Constant(N); break; 58 59 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break; 60 case ISD::SIGN_EXTEND: 61 case ISD::ZERO_EXTEND: 62 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break; 63 case ISD::FP_TO_SINT: 64 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break; 65 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break; 66 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break; 67 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break; 68 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break; 69 70 case ISD::AND: 71 case ISD::OR: 72 case ISD::XOR: 73 case ISD::ADD: 74 case ISD::SUB: 75 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break; 76 77 case ISD::SDIV: 78 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break; 79 80 case ISD::UDIV: 81 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break; 82 83 case ISD::SHL: Result = PromoteIntRes_SHL(N); break; 84 case ISD::SRA: Result = PromoteIntRes_SRA(N); break; 85 case ISD::SRL: Result = PromoteIntRes_SRL(N); break; 86 87 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break; 88 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break; 89 90 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break; 91 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break; 92 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break; 93 94 case ISD::EXTRACT_VECTOR_ELT: 95 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); 96 break; 97 98 case ISD::VAARG : Result = PromoteIntRes_VAARG(N); break; 99 } 100 101 // If Result is null, the sub-method took care of registering the result. 102 if (Result.Val) 103 SetPromotedInteger(SDOperand(N, ResNo), Result); 104} 105 106SDOperand DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 107 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0))); 108} 109 110SDOperand DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 111 MVT VT = N->getValueType(0); 112 // Zero extend things like i1, sign extend everything else. It shouldn't 113 // matter in theory which one we pick, but this tends to give better code? 114 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 115 SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), 116 SDOperand(N, 0)); 117 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 118 return Result; 119} 120 121SDOperand DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 122 SDOperand Res; 123 124 switch (getTypeAction(N->getOperand(0).getValueType())) { 125 default: assert(0 && "Unknown type action!"); 126 case Legal: 127 case ExpandInteger: 128 Res = N->getOperand(0); 129 break; 130 case PromoteInteger: 131 Res = GetPromotedInteger(N->getOperand(0)); 132 break; 133 } 134 135 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 136 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() && 137 "Truncation doesn't make sense!"); 138 if (Res.getValueType() == NVT) 139 return Res; 140 141 // Truncate to NVT instead of VT 142 return DAG.getNode(ISD::TRUNCATE, NVT, Res); 143} 144 145SDOperand DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 146 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 147 148 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 149 SDOperand Res = GetPromotedInteger(N->getOperand(0)); 150 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() && 151 "Extension doesn't make sense!"); 152 153 // If the result and operand types are the same after promotion, simplify 154 // to an in-register extension. 155 if (NVT == Res.getValueType()) { 156 // The high bits are not guaranteed to be anything. Insert an extend. 157 if (N->getOpcode() == ISD::SIGN_EXTEND) 158 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, 159 DAG.getValueType(N->getOperand(0).getValueType())); 160 if (N->getOpcode() == ISD::ZERO_EXTEND) 161 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); 162 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 163 return Res; 164 } 165 } 166 167 // Otherwise, just extend the original operand all the way to the larger type. 168 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0)); 169} 170 171SDOperand DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 172 unsigned NewOpc = N->getOpcode(); 173 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 174 175 // If we're promoting a UINT to a larger size, check to see if the new node 176 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 177 // we can use that instead. This allows us to generate better code for 178 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 179 // legal, such as PowerPC. 180 if (N->getOpcode() == ISD::FP_TO_UINT) { 181 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 182 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 183 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)) 184 NewOpc = ISD::FP_TO_SINT; 185 } 186 187 return DAG.getNode(NewOpc, NVT, N->getOperand(0)); 188} 189 190SDOperand DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 191 assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0))) 192 && "SetCC type is not legal??"); 193 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)), 194 N->getOperand(0), N->getOperand(1), N->getOperand(2)); 195} 196 197SDOperand DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 198 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 199 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 200 ISD::LoadExtType ExtType = 201 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 202 SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(), 203 N->getSrcValue(), N->getSrcValueOffset(), 204 N->getMemoryVT(), N->isVolatile(), 205 N->getAlignment()); 206 207 // Legalized the chain result - switch anything that used the old chain to 208 // use the new one. 209 ReplaceValueWith(SDOperand(N, 1), Res.getValue(1)); 210 return Res; 211} 212 213SDOperand DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 214 // The pair element type may be legal, or may not promote to the same type as 215 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 216 return DAG.getNode(ISD::ANY_EXTEND, 217 TLI.getTypeToTransformTo(N->getValueType(0)), 218 JoinIntegers(N->getOperand(0), N->getOperand(1))); 219} 220 221SDOperand DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 222 SDOperand InOp = N->getOperand(0); 223 MVT InVT = InOp.getValueType(); 224 MVT NInVT = TLI.getTypeToTransformTo(InVT); 225 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 226 227 switch (getTypeAction(InVT)) { 228 default: 229 assert(false && "Unknown type action!"); 230 break; 231 case Legal: 232 break; 233 case PromoteInteger: 234 if (OutVT.getSizeInBits() == NInVT.getSizeInBits()) 235 // The input promotes to the same size. Convert the promoted value. 236 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp)); 237 break; 238 case SoftenFloat: 239 // Promote the integer operand by hand. 240 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp)); 241 case ExpandInteger: 242 case ExpandFloat: 243 break; 244 case ScalarizeVector: 245 // Convert the element to an integer and promote it by hand. 246 return DAG.getNode(ISD::ANY_EXTEND, OutVT, 247 BitConvertToInteger(GetScalarizedVector(InOp))); 248 case SplitVector: 249 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 250 // pieces of the input into integers and reassemble in the final type. 251 SDOperand Lo, Hi; 252 GetSplitVector(N->getOperand(0), Lo, Hi); 253 Lo = BitConvertToInteger(Lo); 254 Hi = BitConvertToInteger(Hi); 255 256 if (TLI.isBigEndian()) 257 std::swap(Lo, Hi); 258 259 InOp = DAG.getNode(ISD::ANY_EXTEND, 260 MVT::getIntegerVT(OutVT.getSizeInBits()), 261 JoinIntegers(Lo, Hi)); 262 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp); 263 } 264 265 // Otherwise, lower the bit-convert to a store/load from the stack, then 266 // promote the load. 267 SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0)); 268 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val)); 269} 270 271SDOperand DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 272 // The input may have strange things in the top bits of the registers, but 273 // these operations don't care. They may have weird bits going out, but 274 // that too is okay if they are integer operations. 275 SDOperand LHS = GetPromotedInteger(N->getOperand(0)); 276 SDOperand RHS = GetPromotedInteger(N->getOperand(1)); 277 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 278} 279 280SDOperand DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 281 // Sign extend the input. 282 SDOperand LHS = GetPromotedInteger(N->getOperand(0)); 283 SDOperand RHS = GetPromotedInteger(N->getOperand(1)); 284 MVT VT = N->getValueType(0); 285 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS, 286 DAG.getValueType(VT)); 287 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS, 288 DAG.getValueType(VT)); 289 290 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 291} 292 293SDOperand DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 294 // Zero extend the input. 295 SDOperand LHS = GetPromotedInteger(N->getOperand(0)); 296 SDOperand RHS = GetPromotedInteger(N->getOperand(1)); 297 MVT VT = N->getValueType(0); 298 LHS = DAG.getZeroExtendInReg(LHS, VT); 299 RHS = DAG.getZeroExtendInReg(RHS, VT); 300 301 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 302} 303 304SDOperand DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 305 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)), 306 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 307} 308 309SDOperand DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 310 // The input value must be properly sign extended. 311 MVT VT = N->getValueType(0); 312 MVT NVT = TLI.getTypeToTransformTo(VT); 313 SDOperand Res = GetPromotedInteger(N->getOperand(0)); 314 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT)); 315 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1)); 316} 317 318SDOperand DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 319 // The input value must be properly zero extended. 320 MVT VT = N->getValueType(0); 321 MVT NVT = TLI.getTypeToTransformTo(VT); 322 SDOperand Res = ZExtPromotedInteger(N->getOperand(0)); 323 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1)); 324} 325 326SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 327 SDOperand LHS = GetPromotedInteger(N->getOperand(1)); 328 SDOperand RHS = GetPromotedInteger(N->getOperand(2)); 329 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS); 330} 331 332SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 333 SDOperand LHS = GetPromotedInteger(N->getOperand(2)); 334 SDOperand RHS = GetPromotedInteger(N->getOperand(3)); 335 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0), 336 N->getOperand(1), LHS, RHS, N->getOperand(4)); 337} 338 339SDOperand DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 340 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 341 MVT OVT = N->getValueType(0); 342 MVT NVT = Op.getValueType(); 343 // Zero extend to the promoted type and do the count there. 344 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT)); 345 // Subtract off the extra leading bits in the bigger type. 346 return DAG.getNode(ISD::SUB, NVT, Op, 347 DAG.getConstant(NVT.getSizeInBits() - 348 OVT.getSizeInBits(), NVT)); 349} 350 351SDOperand DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 352 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 353 MVT OVT = N->getValueType(0); 354 MVT NVT = Op.getValueType(); 355 // Zero extend to the promoted type and do the count there. 356 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT)); 357} 358 359SDOperand DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 360 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 361 MVT OVT = N->getValueType(0); 362 MVT NVT = Op.getValueType(); 363 // The count is the same in the promoted type except if the original 364 // value was zero. This can be handled by setting the bit just off 365 // the top of the original type. 366 APInt TopBit(NVT.getSizeInBits(), 0); 367 TopBit.set(OVT.getSizeInBits()); 368 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT)); 369 return DAG.getNode(ISD::CTTZ, NVT, Op); 370} 371 372SDOperand DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 373 MVT OldVT = N->getValueType(0); 374 SDOperand OldVec = N->getOperand(0); 375 unsigned OldElts = OldVec.getValueType().getVectorNumElements(); 376 377 if (OldElts == 1) { 378 assert(!isTypeLegal(OldVec.getValueType()) && 379 "Legal one-element vector of a type needing promotion!"); 380 // It is tempting to follow GetScalarizedVector by a call to 381 // GetPromotedInteger, but this would be wrong because the 382 // scalarized value may not yet have been processed. 383 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), 384 GetScalarizedVector(OldVec)); 385 } 386 387 // Convert to a vector half as long with an element type of twice the width, 388 // for example <4 x i16> -> <2 x i32>. 389 assert(!(OldElts & 1) && "Odd length vectors not supported!"); 390 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 391 assert(OldVT.isSimple() && NewVT.isSimple()); 392 393 SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT, 394 MVT::getVectorVT(NewVT, OldElts / 2), 395 OldVec); 396 397 // Extract the element at OldIdx / 2 from the new vector. 398 SDOperand OldIdx = N->getOperand(1); 399 SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx, 400 DAG.getConstant(1, TLI.getShiftAmountTy())); 401 SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx); 402 403 // Select the appropriate half of the element: Lo if OldIdx was even, 404 // Hi if it was odd. 405 SDOperand Lo = Elt; 406 SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt, 407 DAG.getConstant(OldVT.getSizeInBits(), 408 TLI.getShiftAmountTy())); 409 if (TLI.isBigEndian()) 410 std::swap(Lo, Hi); 411 412 SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx, 413 DAG.getConstant(1, TLI.getShiftAmountTy())); 414 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo); 415} 416 417SDOperand DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 418 SDOperand Chain = N->getOperand(0); // Get the chain. 419 SDOperand Ptr = N->getOperand(1); // Get the pointer. 420 MVT VT = N->getValueType(0); 421 422 const Value *V = cast<SrcValueSDNode>(N->getOperand(2))->getValue(); 423 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0); 424 425 // Increment the arg pointer, VAList, to the next vaarg 426 // FIXME: should the ABI size be used for the increment? Think of 427 // x86 long double (10 bytes long, but aligned on 4 or 8 bytes) or 428 // integers of unusual size (such MVT::i1, which gives an increment 429 // of zero here!). 430 unsigned Increment = VT.getSizeInBits() / 8; 431 SDOperand Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 432 DAG.getConstant(Increment, TLI.getPointerTy())); 433 434 // Store the incremented VAList to the pointer. 435 Tmp = DAG.getStore(VAList.getValue(1), Tmp, Ptr, V, 0); 436 437 // Load the actual argument out of the arg pointer VAList. 438 Tmp = DAG.getExtLoad(ISD::EXTLOAD, TLI.getTypeToTransformTo(VT), Tmp, 439 VAList, NULL, 0, VT); 440 441 // Legalized the chain result - switch anything that used the old chain to 442 // use the new one. 443 ReplaceValueWith(SDOperand(N, 1), Tmp.getValue(1)); 444 return Tmp; 445} 446 447//===----------------------------------------------------------------------===// 448// Integer Operand Promotion 449//===----------------------------------------------------------------------===// 450 451/// PromoteIntegerOperand - This method is called when the specified operand of 452/// the specified node is found to need promotion. At this point, all of the 453/// result types of the node are known to be legal, but other operands of the 454/// node may need promotion or expansion as well as the specified one. 455bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 456 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); 457 SDOperand Res = SDOperand(); 458 459 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 460 == TargetLowering::Custom) 461 Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG); 462 463 if (Res.Val == 0) { 464 switch (N->getOpcode()) { 465 default: 466 #ifndef NDEBUG 467 cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; 468 N->dump(&DAG); cerr << "\n"; 469 #endif 470 assert(0 && "Do not know how to promote this operator's operand!"); 471 abort(); 472 473 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 474 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 475 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 476 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 477 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break; 478 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break; 479 case ISD::SINT_TO_FP: 480 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break; 481 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 482 483 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 484 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 485 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 486 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 487 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 488 489 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 490 OpNo); break; 491 492 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 493 case ISD::INSERT_VECTOR_ELT: 494 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo); 495 break; 496 497 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 498 } 499 } 500 501 // If the result is null, the sub-method took care of registering results etc. 502 if (!Res.Val) return false; 503 // If the result is N, the sub-method updated N in place. 504 if (Res.Val == N) { 505 // Mark N as new and remark N and its operands. This allows us to correctly 506 // revisit N if it needs another step of promotion and allows us to visit 507 // any new operands to N. 508 ReanalyzeNode(N); 509 return true; 510 } 511 512 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 513 "Invalid operand expansion"); 514 515 ReplaceValueWith(SDOperand(N, 0), Res); 516 return false; 517} 518 519SDOperand DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 520 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 521 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 522} 523 524SDOperand DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 525 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 526 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 527 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); 528} 529 530SDOperand DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 531 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 532 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 533 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), 534 Op, DAG.getValueType(N->getOperand(0).getValueType())); 535} 536 537SDOperand DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 538 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 539 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op); 540} 541 542SDOperand DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) { 543 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 544 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op); 545} 546 547SDOperand DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) { 548 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 549 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op, 550 DAG.getIntPtrConstant(0)); 551} 552 553SDOperand DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) { 554 SDOperand In = GetPromotedInteger(N->getOperand(0)); 555 MVT OpVT = N->getOperand(0).getValueType(); 556 if (N->getOpcode() == ISD::UINT_TO_FP) 557 In = DAG.getZeroExtendInReg(In, OpVT); 558 else 559 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), 560 In, DAG.getValueType(OpVT)); 561 562 return DAG.UpdateNodeOperands(SDOperand(N, 0), In); 563} 564 565SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 566 // Since the result type is legal, the operands must promote to it. 567 MVT OVT = N->getOperand(0).getValueType(); 568 SDOperand Lo = GetPromotedInteger(N->getOperand(0)); 569 SDOperand Hi = GetPromotedInteger(N->getOperand(1)); 570 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 571 572 Lo = DAG.getZeroExtendInReg(Lo, OVT); 573 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi, 574 DAG.getConstant(OVT.getSizeInBits(), 575 TLI.getShiftAmountTy())); 576 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi); 577} 578 579SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 580 assert(OpNo == 0 && "Only know how to promote condition"); 581 SDOperand Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition. 582 583 // The top bits of the promoted condition are not necessarily zero, ensure 584 // that the value is properly zero extended. 585 unsigned BitWidth = Cond.getValueSizeInBits(); 586 if (!DAG.MaskedValueIsZero(Cond, 587 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 588 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); 589 590 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 591 return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1), 592 N->getOperand(2)); 593} 594 595SDOperand DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 596 assert(OpNo == 1 && "only know how to promote condition"); 597 SDOperand Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition. 598 599 // The top bits of the promoted condition are not necessarily zero, ensure 600 // that the value is properly zero extended. 601 unsigned BitWidth = Cond.getValueSizeInBits(); 602 if (!DAG.MaskedValueIsZero(Cond, 603 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 604 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); 605 606 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 607 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond, 608 N->getOperand(2)); 609} 610 611SDOperand DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 612 assert(OpNo == 2 && "Don't know how to promote this operand!"); 613 614 SDOperand LHS = N->getOperand(2); 615 SDOperand RHS = N->getOperand(3); 616 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 617 618 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 619 // legal types. 620 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), 621 N->getOperand(1), LHS, RHS, N->getOperand(4)); 622} 623 624SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 625 assert(OpNo == 0 && "Don't know how to promote this operand!"); 626 627 SDOperand LHS = N->getOperand(0); 628 SDOperand RHS = N->getOperand(1); 629 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 630 631 // The CC (#4) and the possible return values (#2 and #3) have legal types. 632 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2), 633 N->getOperand(3), N->getOperand(4)); 634} 635 636SDOperand DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 637 assert(OpNo == 0 && "Don't know how to promote this operand!"); 638 639 SDOperand LHS = N->getOperand(0); 640 SDOperand RHS = N->getOperand(1); 641 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 642 643 // The CC (#2) is always legal. 644 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2)); 645} 646 647/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 648/// shared among BR_CC, SELECT_CC, and SETCC handlers. 649void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS, 650 ISD::CondCode CCCode) { 651 MVT VT = NewLHS.getValueType(); 652 653 // Get the promoted values. 654 NewLHS = GetPromotedInteger(NewLHS); 655 NewRHS = GetPromotedInteger(NewRHS); 656 657 // Otherwise, we have to insert explicit sign or zero extends. Note 658 // that we could insert sign extends for ALL conditions, but zero extend 659 // is cheaper on many machines (an AND instead of two shifts), so prefer 660 // it. 661 switch (CCCode) { 662 default: assert(0 && "Unknown integer comparison!"); 663 case ISD::SETEQ: 664 case ISD::SETNE: 665 case ISD::SETUGE: 666 case ISD::SETUGT: 667 case ISD::SETULE: 668 case ISD::SETULT: 669 // ALL of these operations will work if we either sign or zero extend 670 // the operands (including the unsigned comparisons!). Zero extend is 671 // usually a simpler/cheaper operation, so prefer it. 672 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT); 673 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT); 674 break; 675 case ISD::SETGE: 676 case ISD::SETGT: 677 case ISD::SETLT: 678 case ISD::SETLE: 679 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS, 680 DAG.getValueType(VT)); 681 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS, 682 DAG.getValueType(VT)); 683 break; 684 } 685} 686 687SDOperand DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 688 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 689 SDOperand Ch = N->getChain(), Ptr = N->getBasePtr(); 690 int SVOffset = N->getSrcValueOffset(); 691 unsigned Alignment = N->getAlignment(); 692 bool isVolatile = N->isVolatile(); 693 694 SDOperand Val = GetPromotedInteger(N->getValue()); // Get promoted value. 695 696 assert(!N->isTruncatingStore() && "Cannot promote this store operand!"); 697 698 // Truncate the value and store the result. 699 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(), 700 SVOffset, N->getMemoryVT(), 701 isVolatile, Alignment); 702} 703 704SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 705 // The vector type is legal but the element type is not. This implies 706 // that the vector is a power-of-two in length and that the element 707 // type does not have a strange size (eg: it is not i1). 708 MVT VecVT = N->getValueType(0); 709 unsigned NumElts = VecVT.getVectorNumElements(); 710 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 711 712 // Build a vector of half the length out of elements of twice the bitwidth. 713 // For example <4 x i16> -> <2 x i32>. 714 MVT OldVT = N->getOperand(0).getValueType(); 715 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 716 assert(OldVT.isSimple() && NewVT.isSimple()); 717 718 std::vector<SDOperand> NewElts; 719 NewElts.reserve(NumElts/2); 720 721 for (unsigned i = 0; i < NumElts; i += 2) { 722 // Combine two successive elements into one promoted element. 723 SDOperand Lo = N->getOperand(i); 724 SDOperand Hi = N->getOperand(i+1); 725 if (TLI.isBigEndian()) 726 std::swap(Lo, Hi); 727 NewElts.push_back(JoinIntegers(Lo, Hi)); 728 } 729 730 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR, 731 MVT::getVectorVT(NewVT, NewElts.size()), 732 &NewElts[0], NewElts.size()); 733 734 // Convert the new vector to the old vector type. 735 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); 736} 737 738SDOperand DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 739 unsigned OpNo) { 740 if (OpNo == 1) { 741 // Promote the inserted value. This is valid because the type does not 742 // have to match the vector element type. 743 744 // Check that any extra bits introduced will be truncated away. 745 assert(N->getOperand(1).getValueType().getSizeInBits() >= 746 N->getValueType(0).getVectorElementType().getSizeInBits() && 747 "Type of inserted value narrower than vector element type!"); 748 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), 749 GetPromotedInteger(N->getOperand(1)), 750 N->getOperand(2)); 751 } 752 753 assert(OpNo == 2 && "Different operand and result vector types?"); 754 755 // Promote the index. 756 SDOperand Idx = N->getOperand(2); 757 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType()); 758 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), 759 N->getOperand(1), Idx); 760} 761 762SDOperand DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 763 SDOperand NewOps[6]; 764 NewOps[0] = N->getOperand(0); 765 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 766 SDOperand Flag = GetPromotedInteger(N->getOperand(i)); 767 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); 768 } 769 return DAG.UpdateNodeOperands(SDOperand (N, 0), NewOps, 770 array_lengthof(NewOps)); 771} 772 773 774//===----------------------------------------------------------------------===// 775// Integer Result Expansion 776//===----------------------------------------------------------------------===// 777 778/// ExpandIntegerResult - This method is called when the specified result of the 779/// specified node is found to need expansion. At this point, the node may also 780/// have invalid operands or may have other results that need promotion, we just 781/// know that (at least) one result needs expansion. 782void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 783 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n"); 784 SDOperand Lo, Hi; 785 Lo = Hi = SDOperand(); 786 787 // See if the target wants to custom expand this node. 788 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 789 TargetLowering::Custom) { 790 // If the target wants to, allow it to lower this itself. 791 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 792 // Everything that once used N now uses P. We are guaranteed that the 793 // result value types of N and the result value types of P match. 794 ReplaceNodeWith(N, P); 795 return; 796 } 797 } 798 799 switch (N->getOpcode()) { 800 default: 801#ifndef NDEBUG 802 cerr << "ExpandIntegerResult #" << ResNo << ": "; 803 N->dump(&DAG); cerr << "\n"; 804#endif 805 assert(0 && "Do not know how to expand the result of this operator!"); 806 abort(); 807 808 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 809 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 810 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 811 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 812 813 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 814 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 815 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 816 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 817 818 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 819 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 820 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 821 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 822 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 823 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 824 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 825 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 826 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 827 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 828 829 case ISD::AND: 830 case ISD::OR: 831 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 832 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 833 case ISD::ADD: 834 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 835 case ISD::ADDC: 836 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 837 case ISD::ADDE: 838 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 839 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 840 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 841 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 842 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 843 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 844 case ISD::SHL: 845 case ISD::SRA: 846 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 847 848 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 849 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 850 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 851 } 852 853 // If Lo/Hi is null, the sub-method took care of registering results etc. 854 if (Lo.Val) 855 SetExpandedInteger(SDOperand(N, ResNo), Lo, Hi); 856} 857 858void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 859 SDOperand &Lo, SDOperand &Hi) { 860 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 861 unsigned NBitWidth = NVT.getSizeInBits(); 862 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 863 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 864 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 865} 866 867void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 868 SDOperand &Lo, SDOperand &Hi) { 869 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 870 SDOperand Op = N->getOperand(0); 871 if (Op.getValueType().bitsLE(NVT)) { 872 // The low part is any extension of the input (which degenerates to a copy). 873 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op); 874 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined. 875 } else { 876 // For example, extension of an i48 to an i64. The operand type necessarily 877 // promotes to the result type, so will end up being expanded too. 878 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 879 "Only know how to promote this result!"); 880 SDOperand Res = GetPromotedInteger(Op); 881 assert(Res.getValueType() == N->getValueType(0) && 882 "Operand over promoted?"); 883 // Split the promoted operand. This will simplify when it is expanded. 884 SplitInteger(Res, Lo, Hi); 885 } 886} 887 888void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 889 SDOperand &Lo, SDOperand &Hi) { 890 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 891 SDOperand Op = N->getOperand(0); 892 if (Op.getValueType().bitsLE(NVT)) { 893 // The low part is zero extension of the input (which degenerates to a copy). 894 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); 895 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 896 } else { 897 // For example, extension of an i48 to an i64. The operand type necessarily 898 // promotes to the result type, so will end up being expanded too. 899 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 900 "Only know how to promote this result!"); 901 SDOperand Res = GetPromotedInteger(Op); 902 assert(Res.getValueType() == N->getValueType(0) && 903 "Operand over promoted?"); 904 // Split the promoted operand. This will simplify when it is expanded. 905 SplitInteger(Res, Lo, Hi); 906 unsigned ExcessBits = 907 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 908 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); 909 } 910} 911 912void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 913 SDOperand &Lo, SDOperand &Hi) { 914 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 915 SDOperand Op = N->getOperand(0); 916 if (Op.getValueType().bitsLE(NVT)) { 917 // The low part is sign extension of the input (which degenerates to a copy). 918 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); 919 // The high part is obtained by SRA'ing all but one of the bits of low part. 920 unsigned LoSize = NVT.getSizeInBits(); 921 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 922 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 923 } else { 924 // For example, extension of an i48 to an i64. The operand type necessarily 925 // promotes to the result type, so will end up being expanded too. 926 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 927 "Only know how to promote this result!"); 928 SDOperand Res = GetPromotedInteger(Op); 929 assert(Res.getValueType() == N->getValueType(0) && 930 "Operand over promoted?"); 931 // Split the promoted operand. This will simplify when it is expanded. 932 SplitInteger(Res, Lo, Hi); 933 unsigned ExcessBits = 934 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 935 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 936 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 937 } 938} 939 940void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 941 SDOperand &Lo, SDOperand &Hi) { 942 GetExpandedInteger(N->getOperand(0), Lo, Hi); 943 MVT NVT = Lo.getValueType(); 944 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 945 unsigned NVTBits = NVT.getSizeInBits(); 946 unsigned EVTBits = EVT.getSizeInBits(); 947 948 if (NVTBits < EVTBits) { 949 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, 950 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 951 } else { 952 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); 953 // The high part must be zero, make it explicit. 954 Hi = DAG.getConstant(0, NVT); 955 } 956} 957 958void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 959 SDOperand &Lo, SDOperand &Hi) { 960 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 961 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); 962 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), 963 DAG.getConstant(NVT.getSizeInBits(), 964 TLI.getShiftAmountTy())); 965 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); 966} 967 968void DAGTypeLegalizer:: 969ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) { 970 GetExpandedInteger(N->getOperand(0), Lo, Hi); 971 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 972 973 if (EVT.bitsLE(Lo.getValueType())) { 974 // sext_inreg the low part if needed. 975 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo, 976 N->getOperand(1)); 977 978 // The high part gets the sign extension from the lo-part. This handles 979 // things like sextinreg V:i64 from i8. 980 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo, 981 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 982 TLI.getShiftAmountTy())); 983 } else { 984 // For example, extension of an i48 to an i64. Leave the low part alone, 985 // sext_inreg the high part. 986 unsigned ExcessBits = 987 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 988 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 989 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 990 } 991} 992 993void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo, 994 SDOperand &Hi) { 995 MVT VT = N->getValueType(0); 996 SDOperand Op = N->getOperand(0); 997 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 998 if (VT == MVT::i64) { 999 if (Op.getValueType() == MVT::f32) 1000 LC = RTLIB::FPTOSINT_F32_I64; 1001 else if (Op.getValueType() == MVT::f64) 1002 LC = RTLIB::FPTOSINT_F64_I64; 1003 else if (Op.getValueType() == MVT::f80) 1004 LC = RTLIB::FPTOSINT_F80_I64; 1005 else if (Op.getValueType() == MVT::ppcf128) 1006 LC = RTLIB::FPTOSINT_PPCF128_I64; 1007 } else if (VT == MVT::i128) { 1008 if (Op.getValueType() == MVT::f32) 1009 LC = RTLIB::FPTOSINT_F32_I128; 1010 else if (Op.getValueType() == MVT::f64) 1011 LC = RTLIB::FPTOSINT_F64_I128; 1012 else if (Op.getValueType() == MVT::f80) 1013 LC = RTLIB::FPTOSINT_F80_I128; 1014 else if (Op.getValueType() == MVT::ppcf128) 1015 LC = RTLIB::FPTOSINT_PPCF128_I128; 1016 } else { 1017 assert(0 && "Unexpected fp-to-sint conversion!"); 1018 } 1019 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi); 1020} 1021 1022void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo, 1023 SDOperand &Hi) { 1024 MVT VT = N->getValueType(0); 1025 SDOperand Op = N->getOperand(0); 1026 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1027 if (VT == MVT::i64) { 1028 if (Op.getValueType() == MVT::f32) 1029 LC = RTLIB::FPTOUINT_F32_I64; 1030 else if (Op.getValueType() == MVT::f64) 1031 LC = RTLIB::FPTOUINT_F64_I64; 1032 else if (Op.getValueType() == MVT::f80) 1033 LC = RTLIB::FPTOUINT_F80_I64; 1034 else if (Op.getValueType() == MVT::ppcf128) 1035 LC = RTLIB::FPTOUINT_PPCF128_I64; 1036 } else if (VT == MVT::i128) { 1037 if (Op.getValueType() == MVT::f32) 1038 LC = RTLIB::FPTOUINT_F32_I128; 1039 else if (Op.getValueType() == MVT::f64) 1040 LC = RTLIB::FPTOUINT_F64_I128; 1041 else if (Op.getValueType() == MVT::f80) 1042 LC = RTLIB::FPTOUINT_F80_I128; 1043 else if (Op.getValueType() == MVT::ppcf128) 1044 LC = RTLIB::FPTOUINT_PPCF128_I128; 1045 } else { 1046 assert(0 && "Unexpected fp-to-uint conversion!"); 1047 } 1048 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi); 1049} 1050 1051void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1052 SDOperand &Lo, SDOperand &Hi) { 1053 if (ISD::isNormalLoad(N)) { 1054 ExpandRes_NormalLoad(N, Lo, Hi); 1055 return; 1056 } 1057 1058 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1059 1060 MVT VT = N->getValueType(0); 1061 MVT NVT = TLI.getTypeToTransformTo(VT); 1062 SDOperand Ch = N->getChain(); // Legalize the chain. 1063 SDOperand Ptr = N->getBasePtr(); // Legalize the pointer. 1064 ISD::LoadExtType ExtType = N->getExtensionType(); 1065 int SVOffset = N->getSrcValueOffset(); 1066 unsigned Alignment = N->getAlignment(); 1067 bool isVolatile = N->isVolatile(); 1068 1069 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1070 1071 if (N->getMemoryVT().bitsLE(NVT)) { 1072 MVT EVT = N->getMemoryVT(); 1073 1074 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, 1075 isVolatile, Alignment); 1076 1077 // Remember the chain. 1078 Ch = Lo.getValue(1); 1079 1080 if (ExtType == ISD::SEXTLOAD) { 1081 // The high part is obtained by SRA'ing all but one of the bits of the 1082 // lo part. 1083 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1084 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1085 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1086 } else if (ExtType == ISD::ZEXTLOAD) { 1087 // The high part is just a zero. 1088 Hi = DAG.getConstant(0, NVT); 1089 } else { 1090 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1091 // The high part is undefined. 1092 Hi = DAG.getNode(ISD::UNDEF, NVT); 1093 } 1094 } else if (TLI.isLittleEndian()) { 1095 // Little-endian - low bits are at low addresses. 1096 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1097 isVolatile, Alignment); 1098 1099 unsigned ExcessBits = 1100 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1101 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1102 1103 // Increment the pointer to the other half. 1104 unsigned IncrementSize = NVT.getSizeInBits()/8; 1105 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1106 DAG.getIntPtrConstant(IncrementSize)); 1107 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), 1108 SVOffset+IncrementSize, NEVT, 1109 isVolatile, MinAlign(Alignment, IncrementSize)); 1110 1111 // Build a factor node to remember that this load is independent of the 1112 // other one. 1113 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1114 Hi.getValue(1)); 1115 } else { 1116 // Big-endian - high bits are at low addresses. Favor aligned loads at 1117 // the cost of some bit-fiddling. 1118 MVT EVT = N->getMemoryVT(); 1119 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1120 unsigned IncrementSize = NVT.getSizeInBits()/8; 1121 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1122 1123 // Load both the high bits and maybe some of the low bits. 1124 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1125 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1126 isVolatile, Alignment); 1127 1128 // Increment the pointer to the other half. 1129 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1130 DAG.getIntPtrConstant(IncrementSize)); 1131 // Load the rest of the low bits. 1132 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(), 1133 SVOffset+IncrementSize, 1134 MVT::getIntegerVT(ExcessBits), 1135 isVolatile, MinAlign(Alignment, IncrementSize)); 1136 1137 // Build a factor node to remember that this load is independent of the 1138 // other one. 1139 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1140 Hi.getValue(1)); 1141 1142 if (ExcessBits < NVT.getSizeInBits()) { 1143 // Transfer low bits from the bottom of Hi to the top of Lo. 1144 Lo = DAG.getNode(ISD::OR, NVT, Lo, 1145 DAG.getNode(ISD::SHL, NVT, Hi, 1146 DAG.getConstant(ExcessBits, 1147 TLI.getShiftAmountTy()))); 1148 // Move high bits to the right position in Hi. 1149 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi, 1150 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1151 TLI.getShiftAmountTy())); 1152 } 1153 } 1154 1155 // Legalized the chain result - switch anything that used the old chain to 1156 // use the new one. 1157 ReplaceValueWith(SDOperand(N, 1), Ch); 1158} 1159 1160void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1161 SDOperand &Lo, SDOperand &Hi) { 1162 SDOperand LL, LH, RL, RH; 1163 GetExpandedInteger(N->getOperand(0), LL, LH); 1164 GetExpandedInteger(N->getOperand(1), RL, RH); 1165 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL); 1166 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH); 1167} 1168 1169void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1170 SDOperand &Lo, SDOperand &Hi) { 1171 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1172 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo); 1173 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi); 1174} 1175 1176void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1177 SDOperand &Lo, SDOperand &Hi) { 1178 // Expand the subcomponents. 1179 SDOperand LHSL, LHSH, RHSL, RHSH; 1180 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1181 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1182 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1183 SDOperand LoOps[2] = { LHSL, RHSL }; 1184 SDOperand HiOps[3] = { LHSH, RHSH }; 1185 1186 if (N->getOpcode() == ISD::ADD) { 1187 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1188 HiOps[2] = Lo.getValue(1); 1189 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1190 } else { 1191 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1192 HiOps[2] = Lo.getValue(1); 1193 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1194 } 1195} 1196 1197void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1198 SDOperand &Lo, SDOperand &Hi) { 1199 // Expand the subcomponents. 1200 SDOperand LHSL, LHSH, RHSL, RHSH; 1201 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1202 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1203 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1204 SDOperand LoOps[2] = { LHSL, RHSL }; 1205 SDOperand HiOps[3] = { LHSH, RHSH }; 1206 1207 if (N->getOpcode() == ISD::ADDC) { 1208 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1209 HiOps[2] = Lo.getValue(1); 1210 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1211 } else { 1212 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1213 HiOps[2] = Lo.getValue(1); 1214 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1215 } 1216 1217 // Legalized the flag result - switch anything that used the old flag to 1218 // use the new one. 1219 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1)); 1220} 1221 1222void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1223 SDOperand &Lo, SDOperand &Hi) { 1224 // Expand the subcomponents. 1225 SDOperand LHSL, LHSH, RHSL, RHSH; 1226 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1227 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1228 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1229 SDOperand LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1230 SDOperand HiOps[3] = { LHSH, RHSH }; 1231 1232 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3); 1233 HiOps[2] = Lo.getValue(1); 1234 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3); 1235 1236 // Legalized the flag result - switch anything that used the old flag to 1237 // use the new one. 1238 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1)); 1239} 1240 1241void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1242 SDOperand &Lo, SDOperand &Hi) { 1243 MVT VT = N->getValueType(0); 1244 MVT NVT = TLI.getTypeToTransformTo(VT); 1245 1246 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 1247 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 1248 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 1249 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 1250 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1251 SDOperand LL, LH, RL, RH; 1252 GetExpandedInteger(N->getOperand(0), LL, LH); 1253 GetExpandedInteger(N->getOperand(1), RL, RH); 1254 unsigned OuterBitSize = VT.getSizeInBits(); 1255 unsigned InnerBitSize = NVT.getSizeInBits(); 1256 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1257 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1258 1259 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1260 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1261 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1262 // The inputs are both zero-extended. 1263 if (HasUMUL_LOHI) { 1264 // We can emit a umul_lohi. 1265 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1266 Hi = SDOperand(Lo.Val, 1); 1267 return; 1268 } 1269 if (HasMULHU) { 1270 // We can emit a mulhu+mul. 1271 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1272 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1273 return; 1274 } 1275 } 1276 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1277 // The input values are both sign-extended. 1278 if (HasSMUL_LOHI) { 1279 // We can emit a smul_lohi. 1280 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1281 Hi = SDOperand(Lo.Val, 1); 1282 return; 1283 } 1284 if (HasMULHS) { 1285 // We can emit a mulhs+mul. 1286 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1287 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 1288 return; 1289 } 1290 } 1291 if (HasUMUL_LOHI) { 1292 // Lo,Hi = umul LHS, RHS. 1293 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 1294 DAG.getVTList(NVT, NVT), LL, RL); 1295 Lo = UMulLOHI; 1296 Hi = UMulLOHI.getValue(1); 1297 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1298 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1299 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1300 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1301 return; 1302 } 1303 if (HasMULHU) { 1304 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1305 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1306 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1307 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1308 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1309 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1310 return; 1311 } 1312 } 1313 1314 // If nothing else, we can make a libcall. 1315 RTLIB::Libcall LC; 1316 switch (VT.getSimpleVT()) { 1317 default: 1318 assert(false && "Unsupported MUL!"); 1319 case MVT::i64: 1320 LC = RTLIB::MUL_I64; 1321 break; 1322 } 1323 1324 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1325 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi); 1326} 1327 1328void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1329 SDOperand &Lo, SDOperand &Hi) { 1330 assert(N->getValueType(0) == MVT::i64 && "Unsupported sdiv!"); 1331 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1332 SplitInteger(MakeLibCall(RTLIB::SDIV_I64, N->getValueType(0), Ops, 2, true), 1333 Lo, Hi); 1334} 1335 1336void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1337 SDOperand &Lo, SDOperand &Hi) { 1338 assert(N->getValueType(0) == MVT::i64 && "Unsupported srem!"); 1339 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1340 SplitInteger(MakeLibCall(RTLIB::SREM_I64, N->getValueType(0), Ops, 2, true), 1341 Lo, Hi); 1342} 1343 1344void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1345 SDOperand &Lo, SDOperand &Hi) { 1346 assert(N->getValueType(0) == MVT::i64 && "Unsupported udiv!"); 1347 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1348 SplitInteger(MakeLibCall(RTLIB::UDIV_I64, N->getValueType(0), Ops, 2, false), 1349 Lo, Hi); 1350} 1351 1352void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1353 SDOperand &Lo, SDOperand &Hi) { 1354 assert(N->getValueType(0) == MVT::i64 && "Unsupported urem!"); 1355 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1356 SplitInteger(MakeLibCall(RTLIB::UREM_I64, N->getValueType(0), Ops, 2, false), 1357 Lo, Hi); 1358} 1359 1360void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1361 SDOperand &Lo, SDOperand &Hi) { 1362 MVT VT = N->getValueType(0); 1363 1364 // If we can emit an efficient shift operation, do so now. Check to see if 1365 // the RHS is a constant. 1366 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1367 return ExpandShiftByConstant(N, CN->getValue(), Lo, Hi); 1368 1369 // If we can determine that the high bit of the shift is zero or one, even if 1370 // the low bits are variable, emit this shift in an optimized form. 1371 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1372 return; 1373 1374 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1375 unsigned PartsOpc; 1376 if (N->getOpcode() == ISD::SHL) { 1377 PartsOpc = ISD::SHL_PARTS; 1378 } else if (N->getOpcode() == ISD::SRL) { 1379 PartsOpc = ISD::SRL_PARTS; 1380 } else { 1381 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1382 PartsOpc = ISD::SRA_PARTS; 1383 } 1384 1385 // Next check to see if the target supports this SHL_PARTS operation or if it 1386 // will custom expand it. 1387 MVT NVT = TLI.getTypeToTransformTo(VT); 1388 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1389 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1390 Action == TargetLowering::Custom) { 1391 // Expand the subcomponents. 1392 SDOperand LHSL, LHSH; 1393 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1394 1395 SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1396 MVT VT = LHSL.getValueType(); 1397 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 1398 Hi = Lo.getValue(1); 1399 return; 1400 } 1401 1402 // Otherwise, emit a libcall. 1403 assert(VT == MVT::i64 && "Unsupported shift!"); 1404 1405 RTLIB::Libcall LC; 1406 bool isSigned; 1407 if (N->getOpcode() == ISD::SHL) { 1408 LC = RTLIB::SHL_I64; 1409 isSigned = false; /*sign irrelevant*/ 1410 } else if (N->getOpcode() == ISD::SRL) { 1411 LC = RTLIB::SRL_I64; 1412 isSigned = false; 1413 } else { 1414 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1415 LC = RTLIB::SRA_I64; 1416 isSigned = true; 1417 } 1418 1419 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1420 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi); 1421} 1422 1423void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1424 SDOperand &Lo, SDOperand &Hi) { 1425 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1426 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1427 MVT NVT = Lo.getValueType(); 1428 1429 SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 1430 DAG.getConstant(0, NVT), ISD::SETNE); 1431 1432 SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo); 1433 SDOperand HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 1434 1435 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ, 1436 DAG.getNode(ISD::ADD, NVT, LoLZ, 1437 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1438 Hi = DAG.getConstant(0, NVT); 1439} 1440 1441void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1442 SDOperand &Lo, SDOperand &Hi) { 1443 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1444 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1445 MVT NVT = Lo.getValueType(); 1446 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), 1447 DAG.getNode(ISD::CTPOP, NVT, Hi)); 1448 Hi = DAG.getConstant(0, NVT); 1449} 1450 1451void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1452 SDOperand &Lo, SDOperand &Hi) { 1453 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1454 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1455 MVT NVT = Lo.getValueType(); 1456 1457 SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, 1458 DAG.getConstant(0, NVT), ISD::SETNE); 1459 1460 SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 1461 SDOperand HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi); 1462 1463 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ, 1464 DAG.getNode(ISD::ADD, NVT, HiLZ, 1465 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1466 Hi = DAG.getConstant(0, NVT); 1467} 1468 1469/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1470/// and the shift amount is a constant 'Amt'. Expand the operation. 1471void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1472 SDOperand &Lo, SDOperand &Hi) { 1473 // Expand the incoming operand to be shifted, so that we have its parts 1474 SDOperand InL, InH; 1475 GetExpandedInteger(N->getOperand(0), InL, InH); 1476 1477 MVT NVT = InL.getValueType(); 1478 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1479 unsigned NVTBits = NVT.getSizeInBits(); 1480 MVT ShTy = N->getOperand(1).getValueType(); 1481 1482 if (N->getOpcode() == ISD::SHL) { 1483 if (Amt > VTBits) { 1484 Lo = Hi = DAG.getConstant(0, NVT); 1485 } else if (Amt > NVTBits) { 1486 Lo = DAG.getConstant(0, NVT); 1487 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1488 } else if (Amt == NVTBits) { 1489 Lo = DAG.getConstant(0, NVT); 1490 Hi = InL; 1491 } else { 1492 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1493 Hi = DAG.getNode(ISD::OR, NVT, 1494 DAG.getNode(ISD::SHL, NVT, InH, 1495 DAG.getConstant(Amt, ShTy)), 1496 DAG.getNode(ISD::SRL, NVT, InL, 1497 DAG.getConstant(NVTBits-Amt, ShTy))); 1498 } 1499 return; 1500 } 1501 1502 if (N->getOpcode() == ISD::SRL) { 1503 if (Amt > VTBits) { 1504 Lo = DAG.getConstant(0, NVT); 1505 Hi = DAG.getConstant(0, NVT); 1506 } else if (Amt > NVTBits) { 1507 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1508 Hi = DAG.getConstant(0, NVT); 1509 } else if (Amt == NVTBits) { 1510 Lo = InH; 1511 Hi = DAG.getConstant(0, NVT); 1512 } else { 1513 Lo = DAG.getNode(ISD::OR, NVT, 1514 DAG.getNode(ISD::SRL, NVT, InL, 1515 DAG.getConstant(Amt, ShTy)), 1516 DAG.getNode(ISD::SHL, NVT, InH, 1517 DAG.getConstant(NVTBits-Amt, ShTy))); 1518 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1519 } 1520 return; 1521 } 1522 1523 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1524 if (Amt > VTBits) { 1525 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 1526 DAG.getConstant(NVTBits-1, ShTy)); 1527 } else if (Amt > NVTBits) { 1528 Lo = DAG.getNode(ISD::SRA, NVT, InH, 1529 DAG.getConstant(Amt-NVTBits, ShTy)); 1530 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1531 DAG.getConstant(NVTBits-1, ShTy)); 1532 } else if (Amt == NVTBits) { 1533 Lo = InH; 1534 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1535 DAG.getConstant(NVTBits-1, ShTy)); 1536 } else { 1537 Lo = DAG.getNode(ISD::OR, NVT, 1538 DAG.getNode(ISD::SRL, NVT, InL, 1539 DAG.getConstant(Amt, ShTy)), 1540 DAG.getNode(ISD::SHL, NVT, InH, 1541 DAG.getConstant(NVTBits-Amt, ShTy))); 1542 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy)); 1543 } 1544} 1545 1546/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1547/// this shift based on knowledge of the high bit of the shift amount. If we 1548/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1549/// shift amount. 1550bool DAGTypeLegalizer:: 1551ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) { 1552 SDOperand Amt = N->getOperand(1); 1553 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1554 MVT ShTy = Amt.getValueType(); 1555 unsigned ShBits = ShTy.getSizeInBits(); 1556 unsigned NVTBits = NVT.getSizeInBits(); 1557 assert(isPowerOf2_32(NVTBits) && 1558 "Expanded integer type size not a power of two!"); 1559 1560 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1561 APInt KnownZero, KnownOne; 1562 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1563 1564 // If we don't know anything about the high bits, exit. 1565 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1566 return false; 1567 1568 // Get the incoming operand to be shifted. 1569 SDOperand InL, InH; 1570 GetExpandedInteger(N->getOperand(0), InL, InH); 1571 1572 // If we know that any of the high bits of the shift amount are one, then we 1573 // can do this as a couple of simple shifts. 1574 if (KnownOne.intersects(HighBitMask)) { 1575 // Mask out the high bit, which we know is set. 1576 Amt = DAG.getNode(ISD::AND, ShTy, Amt, 1577 DAG.getConstant(~HighBitMask, ShTy)); 1578 1579 switch (N->getOpcode()) { 1580 default: assert(0 && "Unknown shift"); 1581 case ISD::SHL: 1582 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1583 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 1584 return true; 1585 case ISD::SRL: 1586 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1587 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 1588 return true; 1589 case ISD::SRA: 1590 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 1591 DAG.getConstant(NVTBits-1, ShTy)); 1592 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 1593 return true; 1594 } 1595 } 1596 1597 // If we know that all of the high bits of the shift amount are zero, then we 1598 // can do this as a couple of simple shifts. 1599 if ((KnownZero & HighBitMask) == HighBitMask) { 1600 // Compute 32-amt. 1601 SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy, 1602 DAG.getConstant(NVTBits, ShTy), 1603 Amt); 1604 unsigned Op1, Op2; 1605 switch (N->getOpcode()) { 1606 default: assert(0 && "Unknown shift"); 1607 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1608 case ISD::SRL: 1609 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1610 } 1611 1612 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1613 Hi = DAG.getNode(ISD::OR, NVT, 1614 DAG.getNode(Op1, NVT, InH, Amt), 1615 DAG.getNode(Op2, NVT, InL, Amt2)); 1616 return true; 1617 } 1618 1619 return false; 1620} 1621 1622 1623//===----------------------------------------------------------------------===// 1624// Integer Operand Expansion 1625//===----------------------------------------------------------------------===// 1626 1627/// ExpandIntegerOperand - This method is called when the specified operand of 1628/// the specified node is found to need expansion. At this point, all of the 1629/// result types of the node are known to be legal, but other operands of the 1630/// node may need promotion or expansion as well as the specified one. 1631bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1632 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); 1633 SDOperand Res = SDOperand(); 1634 1635 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 1636 == TargetLowering::Custom) 1637 Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG); 1638 1639 if (Res.Val == 0) { 1640 switch (N->getOpcode()) { 1641 default: 1642 #ifndef NDEBUG 1643 cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; 1644 N->dump(&DAG); cerr << "\n"; 1645 #endif 1646 assert(0 && "Do not know how to expand this operator's operand!"); 1647 abort(); 1648 1649 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1650 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1651 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1652 1653 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1654 1655 case ISD::SINT_TO_FP: 1656 Res = ExpandIntOp_SINT_TO_FP(N->getOperand(0), N->getValueType(0)); 1657 break; 1658 case ISD::UINT_TO_FP: 1659 Res = ExpandIntOp_UINT_TO_FP(N->getOperand(0), N->getValueType(0)); 1660 break; 1661 1662 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1663 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1664 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1665 1666 case ISD::STORE: 1667 Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); 1668 break; 1669 } 1670 } 1671 1672 // If the result is null, the sub-method took care of registering results etc. 1673 if (!Res.Val) return false; 1674 // If the result is N, the sub-method updated N in place. Check to see if any 1675 // operands are new, and if so, mark them. 1676 if (Res.Val == N) { 1677 // Mark N as new and remark N and its operands. This allows us to correctly 1678 // revisit N if it needs another step of expansion and allows us to visit 1679 // any new operands to N. 1680 ReanalyzeNode(N); 1681 return true; 1682 } 1683 1684 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1685 "Invalid operand expansion"); 1686 1687 ReplaceValueWith(SDOperand(N, 0), Res); 1688 return false; 1689} 1690 1691SDOperand DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 1692 SDOperand InL, InH; 1693 GetExpandedInteger(N->getOperand(0), InL, InH); 1694 // Just truncate the low part of the source. 1695 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL); 1696} 1697 1698SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDOperand Source, 1699 MVT DestTy) { 1700 // We know the destination is legal, but that the input needs to be expanded. 1701 MVT SourceVT = Source.getValueType(); 1702 1703 // Check to see if the target has a custom way to lower this. If so, use it. 1704 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) { 1705 default: assert(0 && "This action not implemented for this operation!"); 1706 case TargetLowering::Legal: 1707 case TargetLowering::Expand: 1708 break; // This case is handled below. 1709 case TargetLowering::Custom: 1710 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy, 1711 Source), DAG); 1712 if (NV.Val) return NV; 1713 break; // The target lowered this. 1714 } 1715 1716 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1717 if (SourceVT == MVT::i64) { 1718 if (DestTy == MVT::f32) 1719 LC = RTLIB::SINTTOFP_I64_F32; 1720 else { 1721 assert(DestTy == MVT::f64 && "Unknown fp value type!"); 1722 LC = RTLIB::SINTTOFP_I64_F64; 1723 } 1724 } else if (SourceVT == MVT::i128) { 1725 if (DestTy == MVT::f32) 1726 LC = RTLIB::SINTTOFP_I128_F32; 1727 else if (DestTy == MVT::f64) 1728 LC = RTLIB::SINTTOFP_I128_F64; 1729 else if (DestTy == MVT::f80) 1730 LC = RTLIB::SINTTOFP_I128_F80; 1731 else { 1732 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!"); 1733 LC = RTLIB::SINTTOFP_I128_PPCF128; 1734 } 1735 } else { 1736 assert(0 && "Unknown int value type!"); 1737 } 1738 1739 assert(LC != RTLIB::UNKNOWN_LIBCALL && 1740 "Don't know how to expand this SINT_TO_FP!"); 1741 return MakeLibCall(LC, DestTy, &Source, 1, true); 1742} 1743 1744SDOperand DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDOperand Source, 1745 MVT DestTy) { 1746 // We know the destination is legal, but that the input needs to be expanded. 1747 assert(getTypeAction(Source.getValueType()) == ExpandInteger && 1748 "This is not an expansion!"); 1749 1750 // If this is unsigned, and not supported, first perform the conversion to 1751 // signed, then adjust the result if the sign bit is set. 1752 SDOperand SignedConv = ExpandIntOp_SINT_TO_FP(Source, DestTy); 1753 1754 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the 1755 // incoming integer is set. To handle this, we dynamically test to see if 1756 // it is set, and, if so, add a fudge factor. 1757 SDOperand Lo, Hi; 1758 GetExpandedInteger(Source, Lo, Hi); 1759 1760 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 1761 DAG.getConstant(0, Hi.getValueType()), 1762 ISD::SETLT); 1763 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 1764 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(), 1765 SignSet, Four, Zero); 1766 uint64_t FF = 0x5f800000ULL; 1767 if (TLI.isLittleEndian()) FF <<= 32; 1768 Constant *FudgeFactor = ConstantInt::get((Type*)Type::Int64Ty, FF); 1769 1770 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 1771 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset); 1772 SDOperand FudgeInReg; 1773 if (DestTy == MVT::f32) 1774 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); 1775 else if (DestTy.bitsGT(MVT::f32)) 1776 // FIXME: Avoid the extend by construction the right constantpool? 1777 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(), 1778 CPIdx, NULL, 0, MVT::f32); 1779 else 1780 assert(0 && "Unexpected conversion"); 1781 1782 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg); 1783} 1784 1785SDOperand DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 1786 SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 1787 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 1788 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 1789 1790 // If ExpandSetCCOperands returned a scalar, we need to compare the result 1791 // against zero to select between true and false values. 1792 if (NewRHS.Val == 0) { 1793 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1794 CCCode = ISD::SETNE; 1795 } 1796 1797 // Update N to have the operands specified. 1798 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), 1799 DAG.getCondCode(CCCode), NewLHS, NewRHS, 1800 N->getOperand(4)); 1801} 1802 1803SDOperand DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 1804 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 1805 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 1806 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 1807 1808 // If ExpandSetCCOperands returned a scalar, we need to compare the result 1809 // against zero to select between true and false values. 1810 if (NewRHS.Val == 0) { 1811 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1812 CCCode = ISD::SETNE; 1813 } 1814 1815 // Update N to have the operands specified. 1816 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS, 1817 N->getOperand(2), N->getOperand(3), 1818 DAG.getCondCode(CCCode)); 1819} 1820 1821SDOperand DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 1822 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 1823 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 1824 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 1825 1826 // If ExpandSetCCOperands returned a scalar, use it. 1827 if (NewRHS.Val == 0) { 1828 assert(NewLHS.getValueType() == N->getValueType(0) && 1829 "Unexpected setcc expansion!"); 1830 return NewLHS; 1831 } 1832 1833 // Otherwise, update N to have the operands specified. 1834 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS, 1835 DAG.getCondCode(CCCode)); 1836} 1837 1838/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 1839/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1840void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDOperand &NewLHS, 1841 SDOperand &NewRHS, 1842 ISD::CondCode &CCCode) { 1843 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1844 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 1845 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 1846 1847 MVT VT = NewLHS.getValueType(); 1848 1849 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 1850 if (RHSLo == RHSHi) { 1851 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 1852 if (RHSCST->isAllOnesValue()) { 1853 // Equality comparison to -1. 1854 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1855 NewRHS = RHSLo; 1856 return; 1857 } 1858 } 1859 } 1860 1861 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1862 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1863 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS); 1864 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1865 return; 1866 } 1867 1868 // If this is a comparison of the sign bit, just look at the top part. 1869 // X > -1, x < 0 1870 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 1871 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 1872 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 1873 NewLHS = LHSHi; 1874 NewRHS = RHSHi; 1875 return; 1876 } 1877 1878 // FIXME: This generated code sucks. 1879 ISD::CondCode LowCC; 1880 switch (CCCode) { 1881 default: assert(0 && "Unknown integer setcc!"); 1882 case ISD::SETLT: 1883 case ISD::SETULT: LowCC = ISD::SETULT; break; 1884 case ISD::SETGT: 1885 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1886 case ISD::SETLE: 1887 case ISD::SETULE: LowCC = ISD::SETULE; break; 1888 case ISD::SETGE: 1889 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1890 } 1891 1892 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1893 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1894 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1895 1896 // NOTE: on targets without efficient SELECT of bools, we can always use 1897 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1898 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 1899 SDOperand Tmp1, Tmp2; 1900 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC, 1901 false, DagCombineInfo); 1902 if (!Tmp1.Val) 1903 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 1904 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1905 CCCode, false, DagCombineInfo); 1906 if (!Tmp2.Val) 1907 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1908 DAG.getCondCode(CCCode)); 1909 1910 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 1911 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 1912 if ((Tmp1C && Tmp1C->isNullValue()) || 1913 (Tmp2C && Tmp2C->isNullValue() && 1914 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 1915 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 1916 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 1917 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 1918 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 1919 // low part is known false, returns high part. 1920 // For LE / GE, if high part is known false, ignore the low part. 1921 // For LT / GT, if high part is known true, ignore the low part. 1922 NewLHS = Tmp2; 1923 NewRHS = SDOperand(); 1924 return; 1925 } 1926 1927 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1928 ISD::SETEQ, false, DagCombineInfo); 1929 if (!NewLHS.Val) 1930 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1931 ISD::SETEQ); 1932 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 1933 NewLHS, Tmp1, Tmp2); 1934 NewRHS = SDOperand(); 1935} 1936 1937SDOperand DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 1938 if (ISD::isNormalStore(N)) 1939 return ExpandOp_NormalStore(N, OpNo); 1940 1941 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 1942 assert(OpNo == 1 && "Can only expand the stored value so far"); 1943 1944 MVT VT = N->getOperand(1).getValueType(); 1945 MVT NVT = TLI.getTypeToTransformTo(VT); 1946 SDOperand Ch = N->getChain(); 1947 SDOperand Ptr = N->getBasePtr(); 1948 int SVOffset = N->getSrcValueOffset(); 1949 unsigned Alignment = N->getAlignment(); 1950 bool isVolatile = N->isVolatile(); 1951 SDOperand Lo, Hi; 1952 1953 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1954 1955 if (N->getMemoryVT().bitsLE(NVT)) { 1956 GetExpandedInteger(N->getValue(), Lo, Hi); 1957 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 1958 N->getMemoryVT(), isVolatile, Alignment); 1959 } else if (TLI.isLittleEndian()) { 1960 // Little-endian - low bits are at low addresses. 1961 GetExpandedInteger(N->getValue(), Lo, Hi); 1962 1963 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 1964 isVolatile, Alignment); 1965 1966 unsigned ExcessBits = 1967 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1968 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1969 1970 // Increment the pointer to the other half. 1971 unsigned IncrementSize = NVT.getSizeInBits()/8; 1972 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1973 DAG.getIntPtrConstant(IncrementSize)); 1974 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 1975 SVOffset+IncrementSize, NEVT, 1976 isVolatile, MinAlign(Alignment, IncrementSize)); 1977 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 1978 } else { 1979 // Big-endian - high bits are at low addresses. Favor aligned stores at 1980 // the cost of some bit-fiddling. 1981 GetExpandedInteger(N->getValue(), Lo, Hi); 1982 1983 MVT EVT = N->getMemoryVT(); 1984 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1985 unsigned IncrementSize = NVT.getSizeInBits()/8; 1986 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1987 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 1988 1989 if (ExcessBits < NVT.getSizeInBits()) { 1990 // Transfer high bits from the top of Lo to the bottom of Hi. 1991 Hi = DAG.getNode(ISD::SHL, NVT, Hi, 1992 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1993 TLI.getShiftAmountTy())); 1994 Hi = DAG.getNode(ISD::OR, NVT, Hi, 1995 DAG.getNode(ISD::SRL, NVT, Lo, 1996 DAG.getConstant(ExcessBits, 1997 TLI.getShiftAmountTy()))); 1998 } 1999 2000 // Store both the high bits and maybe some of the low bits. 2001 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2002 SVOffset, HiVT, isVolatile, Alignment); 2003 2004 // Increment the pointer to the other half. 2005 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2006 DAG.getIntPtrConstant(IncrementSize)); 2007 // Store the lowest ExcessBits bits in the second half. 2008 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), 2009 SVOffset+IncrementSize, 2010 MVT::getIntegerVT(ExcessBits), 2011 isVolatile, MinAlign(Alignment, IncrementSize)); 2012 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2013 } 2014} 2015