LegalizeIntegerTypes.cpp revision 59fc626007185115f2ea3bc3e604b63910312e4f
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22using namespace llvm; 23 24//===----------------------------------------------------------------------===// 25// Integer Result Promotion 26//===----------------------------------------------------------------------===// 27 28/// PromoteIntegerResult - This method is called when a result of a node is 29/// found to be in need of promotion to a larger type. At this point, the node 30/// may also have invalid operands or may have other results that need 31/// expansion, we just know that (at least) one result needs promotion. 32void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); 34 SDValue Result = SDValue(); 35 36 // See if the target wants to custom expand this node. 37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 38 TargetLowering::Custom) { 39 // If the target wants to, allow it to lower this itself. 40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 41 // Everything that once used N now uses P. We are guaranteed that the 42 // result value types of N and the result value types of P match. 43 ReplaceNodeWith(N, P); 44 return; 45 } 46 } 47 48 switch (N->getOpcode()) { 49 default: 50#ifndef NDEBUG 51 cerr << "PromoteIntegerResult #" << ResNo << ": "; 52 N->dump(&DAG); cerr << "\n"; 53#endif 54 assert(0 && "Do not know how to promote this operator!"); 55 abort(); 56 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break; 57 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break; 58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break; 59 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break; 60 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break; 61 case ISD::Constant: Result = PromoteIntRes_Constant(N); break; 62 case ISD::CONVERT_RNDSAT: 63 Result = PromoteIntRes_CONVERT_RNDSAT(N); break; 64 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break; 65 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break; 66 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break; 67 case ISD::EXTRACT_VECTOR_ELT: 68 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 69 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 70 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break; 71 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break; 72 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break; 73 case ISD::SHL: Result = PromoteIntRes_SHL(N); break; 74 case ISD::SIGN_EXTEND_INREG: 75 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 76 case ISD::SRA: Result = PromoteIntRes_SRA(N); break; 77 case ISD::SRL: Result = PromoteIntRes_SRL(N); break; 78 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break; 79 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break; 80 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break; 81 82 case ISD::SIGN_EXTEND: 83 case ISD::ZERO_EXTEND: 84 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break; 85 86 case ISD::FP_TO_SINT: 87 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break; 88 89 case ISD::AND: 90 case ISD::OR: 91 case ISD::XOR: 92 case ISD::ADD: 93 case ISD::SUB: 94 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break; 95 96 case ISD::SDIV: 97 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break; 98 99 case ISD::UDIV: 100 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break; 101 102 case ISD::ATOMIC_LOAD_ADD_8: 103 case ISD::ATOMIC_LOAD_SUB_8: 104 case ISD::ATOMIC_LOAD_AND_8: 105 case ISD::ATOMIC_LOAD_OR_8: 106 case ISD::ATOMIC_LOAD_XOR_8: 107 case ISD::ATOMIC_LOAD_NAND_8: 108 case ISD::ATOMIC_LOAD_MIN_8: 109 case ISD::ATOMIC_LOAD_MAX_8: 110 case ISD::ATOMIC_LOAD_UMIN_8: 111 case ISD::ATOMIC_LOAD_UMAX_8: 112 case ISD::ATOMIC_SWAP_8: 113 case ISD::ATOMIC_LOAD_ADD_16: 114 case ISD::ATOMIC_LOAD_SUB_16: 115 case ISD::ATOMIC_LOAD_AND_16: 116 case ISD::ATOMIC_LOAD_OR_16: 117 case ISD::ATOMIC_LOAD_XOR_16: 118 case ISD::ATOMIC_LOAD_NAND_16: 119 case ISD::ATOMIC_LOAD_MIN_16: 120 case ISD::ATOMIC_LOAD_MAX_16: 121 case ISD::ATOMIC_LOAD_UMIN_16: 122 case ISD::ATOMIC_LOAD_UMAX_16: 123 case ISD::ATOMIC_SWAP_16: 124 case ISD::ATOMIC_LOAD_ADD_32: 125 case ISD::ATOMIC_LOAD_SUB_32: 126 case ISD::ATOMIC_LOAD_AND_32: 127 case ISD::ATOMIC_LOAD_OR_32: 128 case ISD::ATOMIC_LOAD_XOR_32: 129 case ISD::ATOMIC_LOAD_NAND_32: 130 case ISD::ATOMIC_LOAD_MIN_32: 131 case ISD::ATOMIC_LOAD_MAX_32: 132 case ISD::ATOMIC_LOAD_UMIN_32: 133 case ISD::ATOMIC_LOAD_UMAX_32: 134 case ISD::ATOMIC_SWAP_32: 135 case ISD::ATOMIC_LOAD_ADD_64: 136 case ISD::ATOMIC_LOAD_SUB_64: 137 case ISD::ATOMIC_LOAD_AND_64: 138 case ISD::ATOMIC_LOAD_OR_64: 139 case ISD::ATOMIC_LOAD_XOR_64: 140 case ISD::ATOMIC_LOAD_NAND_64: 141 case ISD::ATOMIC_LOAD_MIN_64: 142 case ISD::ATOMIC_LOAD_MAX_64: 143 case ISD::ATOMIC_LOAD_UMIN_64: 144 case ISD::ATOMIC_LOAD_UMAX_64: 145 case ISD::ATOMIC_SWAP_64: 146 Result = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 147 148 case ISD::ATOMIC_CMP_SWAP_8: 149 case ISD::ATOMIC_CMP_SWAP_16: 150 case ISD::ATOMIC_CMP_SWAP_32: 151 case ISD::ATOMIC_CMP_SWAP_64: 152 Result = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 153 } 154 155 // If Result is null, the sub-method took care of registering the result. 156 if (Result.getNode()) 157 SetPromotedInteger(SDValue(N, ResNo), Result); 158} 159 160SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 161 // Sign-extend the new bits, and continue the assertion. 162 MVT OldVT = N->getValueType(0); 163 SDValue Op = GetPromotedInteger(N->getOperand(0)); 164 return DAG.getNode(ISD::AssertSext, Op.getValueType(), 165 DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, 166 DAG.getValueType(OldVT)), N->getOperand(1)); 167} 168 169SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 170 // Zero the new bits, and continue the assertion. 171 MVT OldVT = N->getValueType(0); 172 SDValue Op = GetPromotedInteger(N->getOperand(0)); 173 return DAG.getNode(ISD::AssertZext, Op.getValueType(), 174 DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1)); 175} 176 177SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 178 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 179 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(), 180 Op2, N->getSrcValue(), N->getAlignment()); 181 // Legalized the chain result - switch anything that used the old chain to 182 // use the new one. 183 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 184 return Res; 185} 186 187SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 188 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 189 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 190 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(), 191 Op2, Op3, N->getSrcValue(), N->getAlignment()); 192 // Legalized the chain result - switch anything that used the old chain to 193 // use the new one. 194 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 195 return Res; 196} 197 198SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 199 SDValue InOp = N->getOperand(0); 200 MVT InVT = InOp.getValueType(); 201 MVT NInVT = TLI.getTypeToTransformTo(InVT); 202 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 203 204 switch (getTypeAction(InVT)) { 205 default: 206 assert(false && "Unknown type action!"); 207 break; 208 case Legal: 209 break; 210 case PromoteInteger: 211 if (OutVT.bitsEq(NInVT)) 212 // The input promotes to the same size. Convert the promoted value. 213 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp)); 214 break; 215 case SoftenFloat: 216 // Promote the integer operand by hand. 217 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp)); 218 case ExpandInteger: 219 case ExpandFloat: 220 break; 221 case ScalarizeVector: 222 // Convert the element to an integer and promote it by hand. 223 return DAG.getNode(ISD::ANY_EXTEND, OutVT, 224 BitConvertToInteger(GetScalarizedVector(InOp))); 225 case SplitVector: 226 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 227 // pieces of the input into integers and reassemble in the final type. 228 SDValue Lo, Hi; 229 GetSplitVector(N->getOperand(0), Lo, Hi); 230 Lo = BitConvertToInteger(Lo); 231 Hi = BitConvertToInteger(Hi); 232 233 if (TLI.isBigEndian()) 234 std::swap(Lo, Hi); 235 236 InOp = DAG.getNode(ISD::ANY_EXTEND, 237 MVT::getIntegerVT(OutVT.getSizeInBits()), 238 JoinIntegers(Lo, Hi)); 239 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp); 240 } 241 242 // Otherwise, lower the bit-convert to a store/load from the stack, then 243 // promote the load. 244 SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0)); 245 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode())); 246} 247 248SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 249 SDValue Op = GetPromotedInteger(N->getOperand(0)); 250 MVT OVT = N->getValueType(0); 251 MVT NVT = Op.getValueType(); 252 253 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 254 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op), 255 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 256} 257 258SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 259 // The pair element type may be legal, or may not promote to the same type as 260 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 261 return DAG.getNode(ISD::ANY_EXTEND, 262 TLI.getTypeToTransformTo(N->getValueType(0)), 263 JoinIntegers(N->getOperand(0), N->getOperand(1))); 264} 265 266SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 267 MVT VT = N->getValueType(0); 268 // Zero extend things like i1, sign extend everything else. It shouldn't 269 // matter in theory which one we pick, but this tends to give better code? 270 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 271 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), 272 SDValue(N, 0)); 273 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 274 return Result; 275} 276 277SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 278 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 279 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 280 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 281 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 282 "can only promote integers"); 283 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 284 return DAG.getConvertRndSat(OutVT, N->getOperand(0), 285 N->getOperand(1), N->getOperand(2), 286 N->getOperand(3), N->getOperand(4), CvtCode); 287} 288 289SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 290 SDValue Op = GetPromotedInteger(N->getOperand(0)); 291 MVT OVT = N->getValueType(0); 292 MVT NVT = Op.getValueType(); 293 // Zero extend to the promoted type and do the count there. 294 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT)); 295 // Subtract off the extra leading bits in the bigger type. 296 return DAG.getNode(ISD::SUB, NVT, Op, 297 DAG.getConstant(NVT.getSizeInBits() - 298 OVT.getSizeInBits(), NVT)); 299} 300 301SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 302 SDValue Op = GetPromotedInteger(N->getOperand(0)); 303 MVT OVT = N->getValueType(0); 304 MVT NVT = Op.getValueType(); 305 // Zero extend to the promoted type and do the count there. 306 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT)); 307} 308 309SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 310 SDValue Op = GetPromotedInteger(N->getOperand(0)); 311 MVT OVT = N->getValueType(0); 312 MVT NVT = Op.getValueType(); 313 // The count is the same in the promoted type except if the original 314 // value was zero. This can be handled by setting the bit just off 315 // the top of the original type. 316 APInt TopBit(NVT.getSizeInBits(), 0); 317 TopBit.set(OVT.getSizeInBits()); 318 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT)); 319 return DAG.getNode(ISD::CTTZ, NVT, Op); 320} 321 322SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 323 MVT OldVT = N->getValueType(0); 324 SDValue OldVec = N->getOperand(0); 325 unsigned OldElts = OldVec.getValueType().getVectorNumElements(); 326 327 if (OldElts == 1) { 328 assert(!isTypeLegal(OldVec.getValueType()) && 329 "Legal one-element vector of a type needing promotion!"); 330 // It is tempting to follow GetScalarizedVector by a call to 331 // GetPromotedInteger, but this would be wrong because the 332 // scalarized value may not yet have been processed. 333 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), 334 GetScalarizedVector(OldVec)); 335 } 336 337 // Convert to a vector half as long with an element type of twice the width, 338 // for example <4 x i16> -> <2 x i32>. 339 assert(!(OldElts & 1) && "Odd length vectors not supported!"); 340 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 341 assert(OldVT.isSimple() && NewVT.isSimple()); 342 343 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, 344 MVT::getVectorVT(NewVT, OldElts / 2), 345 OldVec); 346 347 // Extract the element at OldIdx / 2 from the new vector. 348 SDValue OldIdx = N->getOperand(1); 349 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx, 350 DAG.getConstant(1, TLI.getShiftAmountTy())); 351 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx); 352 353 // Select the appropriate half of the element: Lo if OldIdx was even, 354 // Hi if it was odd. 355 SDValue Lo = Elt; 356 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt, 357 DAG.getConstant(OldVT.getSizeInBits(), 358 TLI.getShiftAmountTy())); 359 if (TLI.isBigEndian()) 360 std::swap(Lo, Hi); 361 362 SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx); 363 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo); 364} 365 366SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 367 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 368 unsigned NewOpc = N->getOpcode(); 369 370 // If we're promoting a UINT to a larger size, check to see if the new node 371 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 372 // we can use that instead. This allows us to generate better code for 373 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 374 // legal, such as PowerPC. 375 if (N->getOpcode() == ISD::FP_TO_UINT && 376 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 377 TLI.isOperationLegal(ISD::FP_TO_SINT, NVT)) 378 NewOpc = ISD::FP_TO_SINT; 379 380 SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0)); 381 382 // Assert that the converted value fits in the original type. If it doesn't 383 // (eg: because the value being converted is too big), then the result of the 384 // original operation was undefined anyway, so the assert is still correct. 385 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 386 ISD::AssertZext : ISD::AssertSext, 387 NVT, Res, DAG.getValueType(N->getValueType(0))); 388} 389 390SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 391 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 392 393 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 394 SDValue Res = GetPromotedInteger(N->getOperand(0)); 395 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 396 397 // If the result and operand types are the same after promotion, simplify 398 // to an in-register extension. 399 if (NVT == Res.getValueType()) { 400 // The high bits are not guaranteed to be anything. Insert an extend. 401 if (N->getOpcode() == ISD::SIGN_EXTEND) 402 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, 403 DAG.getValueType(N->getOperand(0).getValueType())); 404 if (N->getOpcode() == ISD::ZERO_EXTEND) 405 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); 406 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 407 return Res; 408 } 409 } 410 411 // Otherwise, just extend the original operand all the way to the larger type. 412 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0)); 413} 414 415SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 416 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 417 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 418 ISD::LoadExtType ExtType = 419 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 420 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(), 421 N->getSrcValue(), N->getSrcValueOffset(), 422 N->getMemoryVT(), N->isVolatile(), 423 N->getAlignment()); 424 425 // Legalized the chain result - switch anything that used the old chain to 426 // use the new one. 427 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 428 return Res; 429} 430 431SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 432 // Sign extend the input. 433 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 434 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 435 MVT VT = N->getValueType(0); 436 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS, 437 DAG.getValueType(VT)); 438 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS, 439 DAG.getValueType(VT)); 440 441 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 442} 443 444SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 445 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 446 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 447 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS); 448} 449 450SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 451 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 452 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 453 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0), 454 N->getOperand(1), LHS, RHS, N->getOperand(4)); 455} 456 457SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 458 MVT SVT = TLI.getSetCCResultType(N->getOperand(0)); 459 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 460 461 // Get the SETCC result using the canonical SETCC type. 462 SDValue SetCC = DAG.getNode(ISD::SETCC, SVT, N->getOperand(0), 463 N->getOperand(1), N->getOperand(2)); 464 465 // Convert to the expected type. 466 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 467 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 468 return DAG.getNode(ISD::TRUNCATE, NVT, SetCC); 469} 470 471SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 472 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)), 473 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 474} 475 476SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 477 SDValue Op = GetPromotedInteger(N->getOperand(0)); 478 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, 479 N->getOperand(1)); 480} 481 482SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 483 // The input may have strange things in the top bits of the registers, but 484 // these operations don't care. They may have weird bits going out, but 485 // that too is okay if they are integer operations. 486 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 487 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 488 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 489} 490 491SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 492 // The input value must be properly sign extended. 493 MVT VT = N->getValueType(0); 494 MVT NVT = TLI.getTypeToTransformTo(VT); 495 SDValue Res = GetPromotedInteger(N->getOperand(0)); 496 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT)); 497 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1)); 498} 499 500SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 501 // The input value must be properly zero extended. 502 MVT VT = N->getValueType(0); 503 MVT NVT = TLI.getTypeToTransformTo(VT); 504 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 505 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1)); 506} 507 508SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 509 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 510 SDValue Res; 511 512 switch (getTypeAction(N->getOperand(0).getValueType())) { 513 default: assert(0 && "Unknown type action!"); 514 case Legal: 515 case ExpandInteger: 516 Res = N->getOperand(0); 517 break; 518 case PromoteInteger: 519 Res = GetPromotedInteger(N->getOperand(0)); 520 break; 521 } 522 523 // Truncate to NVT instead of VT 524 return DAG.getNode(ISD::TRUNCATE, NVT, Res); 525} 526 527SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 528 // Zero extend the input. 529 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 530 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 531 MVT VT = N->getValueType(0); 532 LHS = DAG.getZeroExtendInReg(LHS, VT); 533 RHS = DAG.getZeroExtendInReg(RHS, VT); 534 535 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 536} 537 538SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 539 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0))); 540} 541 542SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 543 SDValue Chain = N->getOperand(0); // Get the chain. 544 SDValue Ptr = N->getOperand(1); // Get the pointer. 545 MVT VT = N->getValueType(0); 546 547 MVT RegVT = TLI.getRegisterType(VT); 548 unsigned NumRegs = TLI.getNumRegisters(VT); 549 // The argument is passed as NumRegs registers of type RegVT. 550 551 SmallVector<SDValue, 8> Parts(NumRegs); 552 for (unsigned i = 0; i < NumRegs; ++i) { 553 Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2)); 554 Chain = Parts[i].getValue(1); 555 } 556 557 // Handle endianness of the load. 558 if (TLI.isBigEndian()) 559 std::reverse(Parts.begin(), Parts.end()); 560 561 // Assemble the parts in the promoted type. 562 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 563 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[0]); 564 for (unsigned i = 1; i < NumRegs; ++i) { 565 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[i]); 566 // Shift it to the right position and "or" it in. 567 Part = DAG.getNode(ISD::SHL, NVT, Part, 568 DAG.getConstant(i * RegVT.getSizeInBits(), 569 TLI.getShiftAmountTy())); 570 Res = DAG.getNode(ISD::OR, NVT, Res, Part); 571 } 572 573 // Modified the chain result - switch anything that used the old chain to 574 // use the new one. 575 ReplaceValueWith(SDValue(N, 1), Chain); 576 577 return Res; 578} 579 580 581//===----------------------------------------------------------------------===// 582// Integer Operand Promotion 583//===----------------------------------------------------------------------===// 584 585/// PromoteIntegerOperand - This method is called when the specified operand of 586/// the specified node is found to need promotion. At this point, all of the 587/// result types of the node are known to be legal, but other operands of the 588/// node may need promotion or expansion as well as the specified one. 589bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 590 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); 591 SDValue Res = SDValue(); 592 593 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 594 == TargetLowering::Custom) 595 Res = TLI.LowerOperation(SDValue(N, 0), DAG); 596 597 if (Res.getNode() == 0) { 598 switch (N->getOpcode()) { 599 default: 600 #ifndef NDEBUG 601 cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; 602 N->dump(&DAG); cerr << "\n"; 603 #endif 604 assert(0 && "Do not know how to promote this operator's operand!"); 605 abort(); 606 607 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 608 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 609 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 610 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 611 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 612 case ISD::CONVERT_RNDSAT: 613 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 614 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break; 615 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break; 616 case ISD::INSERT_VECTOR_ELT: 617 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 618 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 619 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 620 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 621 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 622 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 623 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 624 OpNo); break; 625 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 626 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 627 628 case ISD::SINT_TO_FP: 629 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break; 630 } 631 } 632 633 // If the result is null, the sub-method took care of registering results etc. 634 if (!Res.getNode()) return false; 635 // If the result is N, the sub-method updated N in place. 636 if (Res.getNode() == N) { 637 // Mark N as new and remark N and its operands. This allows us to correctly 638 // revisit N if it needs another step of promotion and allows us to visit 639 // any new operands to N. 640 ReanalyzeNode(N); 641 return true; 642 } 643 644 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 645 "Invalid operand expansion"); 646 647 ReplaceValueWith(SDValue(N, 0), Res); 648 return false; 649} 650 651/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 652/// shared among BR_CC, SELECT_CC, and SETCC handlers. 653void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 654 ISD::CondCode CCCode) { 655 MVT VT = NewLHS.getValueType(); 656 657 // Get the promoted values. 658 NewLHS = GetPromotedInteger(NewLHS); 659 NewRHS = GetPromotedInteger(NewRHS); 660 661 // We have to insert explicit sign or zero extends. Note that we could 662 // insert sign extends for ALL conditions, but zero extend is cheaper on 663 // many machines (an AND instead of two shifts), so prefer it. 664 switch (CCCode) { 665 default: assert(0 && "Unknown integer comparison!"); 666 case ISD::SETEQ: 667 case ISD::SETNE: 668 case ISD::SETUGE: 669 case ISD::SETUGT: 670 case ISD::SETULE: 671 case ISD::SETULT: 672 // ALL of these operations will work if we either sign or zero extend 673 // the operands (including the unsigned comparisons!). Zero extend is 674 // usually a simpler/cheaper operation, so prefer it. 675 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT); 676 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT); 677 break; 678 case ISD::SETGE: 679 case ISD::SETGT: 680 case ISD::SETLT: 681 case ISD::SETLE: 682 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS, 683 DAG.getValueType(VT)); 684 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS, 685 DAG.getValueType(VT)); 686 break; 687 } 688} 689 690SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 691 SDValue Op = GetPromotedInteger(N->getOperand(0)); 692 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 693} 694 695SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 696 assert(OpNo == 2 && "Don't know how to promote this operand!"); 697 698 SDValue LHS = N->getOperand(2); 699 SDValue RHS = N->getOperand(3); 700 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 701 702 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 703 // legal types. 704 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 705 N->getOperand(1), LHS, RHS, N->getOperand(4)); 706} 707 708SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 709 assert(OpNo == 1 && "only know how to promote condition"); 710 SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition. 711 712 // Make sure the extra bits coming from type promotion conform to 713 // getSetCCResultContents. 714 unsigned CondBits = Cond.getValueSizeInBits(); 715 switch (TLI.getSetCCResultContents()) { 716 default: 717 assert(false && "Unknown SetCCResultValue!"); 718 case TargetLowering::UndefinedSetCCResult: 719 // The promoted value, which may contain rubbish in the upper bits, is fine. 720 break; 721 case TargetLowering::ZeroOrOneSetCCResult: 722 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1))) 723 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); 724 break; 725 case TargetLowering::ZeroOrNegativeOneSetCCResult: 726 if (DAG.ComputeNumSignBits(Cond) != CondBits) 727 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond, 728 DAG.getValueType(MVT::i1)); 729 break; 730 } 731 732 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 733 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, 734 N->getOperand(2)); 735} 736 737SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 738 // Since the result type is legal, the operands must promote to it. 739 MVT OVT = N->getOperand(0).getValueType(); 740 SDValue Lo = GetPromotedInteger(N->getOperand(0)); 741 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 742 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 743 744 Lo = DAG.getZeroExtendInReg(Lo, OVT); 745 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi, 746 DAG.getConstant(OVT.getSizeInBits(), 747 TLI.getShiftAmountTy())); 748 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi); 749} 750 751SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 752 // The vector type is legal but the element type is not. This implies 753 // that the vector is a power-of-two in length and that the element 754 // type does not have a strange size (eg: it is not i1). 755 MVT VecVT = N->getValueType(0); 756 unsigned NumElts = VecVT.getVectorNumElements(); 757 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 758 759 // Build a vector of half the length out of elements of twice the bitwidth. 760 // For example <4 x i16> -> <2 x i32>. 761 MVT OldVT = N->getOperand(0).getValueType(); 762 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 763 assert(OldVT.isSimple() && NewVT.isSimple()); 764 765 std::vector<SDValue> NewElts; 766 NewElts.reserve(NumElts/2); 767 768 for (unsigned i = 0; i < NumElts; i += 2) { 769 // Combine two successive elements into one promoted element. 770 SDValue Lo = N->getOperand(i); 771 SDValue Hi = N->getOperand(i+1); 772 if (TLI.isBigEndian()) 773 std::swap(Lo, Hi); 774 NewElts.push_back(JoinIntegers(Lo, Hi)); 775 } 776 777 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, 778 MVT::getVectorVT(NewVT, NewElts.size()), 779 &NewElts[0], NewElts.size()); 780 781 // Convert the new vector to the old vector type. 782 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); 783} 784 785SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 786 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 787 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 788 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 789 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 790 "can only promote integer arguments"); 791 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 792 return DAG.getConvertRndSat(N->getValueType(0), InOp, 793 N->getOperand(1), N->getOperand(2), 794 N->getOperand(3), N->getOperand(4), CvtCode); 795} 796 797SDValue DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) { 798 SDValue Op = GetPromotedInteger(N->getOperand(0)); 799 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op); 800} 801 802SDValue DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) { 803 SDValue Op = GetPromotedInteger(N->getOperand(0)); 804 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op, 805 DAG.getIntPtrConstant(0)); 806} 807 808SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 809 unsigned OpNo) { 810 if (OpNo == 1) { 811 // Promote the inserted value. This is valid because the type does not 812 // have to match the vector element type. 813 814 // Check that any extra bits introduced will be truncated away. 815 assert(N->getOperand(1).getValueType().getSizeInBits() >= 816 N->getValueType(0).getVectorElementType().getSizeInBits() && 817 "Type of inserted value narrower than vector element type!"); 818 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 819 GetPromotedInteger(N->getOperand(1)), 820 N->getOperand(2)); 821 } 822 823 assert(OpNo == 2 && "Different operand and result vector types?"); 824 825 // Promote the index. 826 SDValue Idx = N->getOperand(2); 827 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType()); 828 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 829 N->getOperand(1), Idx); 830} 831 832SDValue DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) { 833 SDValue In = GetPromotedInteger(N->getOperand(0)); 834 MVT OpVT = N->getOperand(0).getValueType(); 835 if (N->getOpcode() == ISD::UINT_TO_FP) 836 In = DAG.getZeroExtendInReg(In, OpVT); 837 else 838 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), 839 In, DAG.getValueType(OpVT)); 840 841 return DAG.UpdateNodeOperands(SDValue(N, 0), In); 842} 843 844SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 845 SDValue NewOps[6]; 846 NewOps[0] = N->getOperand(0); 847 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 848 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 849 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); 850 } 851 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, 852 array_lengthof(NewOps)); 853} 854 855SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 856 assert(OpNo == 0 && "Only know how to promote condition"); 857 SDValue Cond = GetPromotedInteger(N->getOperand(0)); 858 859 // Promote all the way up to SVT, the canonical SetCC type. 860 // FIXME: Not clear what value to pass to getSetCCResultType. 861 // [This only matters for CellSPU since all other targets 862 // ignore the argument.] We used to pass Cond, resulting in 863 // SVT = MVT::i8, but CellSPU has no select patterns for i8, 864 // causing an abort later. Passing the result type works 865 // around the problem. 866 MVT SVT = TLI.getSetCCResultType(N->getOperand(1)); 867 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 868 assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!"); 869 870 // Make sure the extra bits conform to getSetCCResultContents. There are 871 // two sets of extra bits: those in Cond, which come from type promotion, 872 // and those we need to add to have the final type be SVT (for most targets 873 // this last set of bits is empty). 874 unsigned CondBits = Cond.getValueSizeInBits(); 875 ISD::NodeType ExtendCode; 876 switch (TLI.getSetCCResultContents()) { 877 default: 878 assert(false && "Unknown SetCCResultValue!"); 879 case TargetLowering::UndefinedSetCCResult: 880 // Extend to SVT by adding rubbish. 881 ExtendCode = ISD::ANY_EXTEND; 882 break; 883 case TargetLowering::ZeroOrOneSetCCResult: 884 ExtendCode = ISD::ZERO_EXTEND; 885 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1))) 886 // All extra bits need to be cleared. Do this by zero extending the 887 // original condition value all the way to SVT. 888 Cond = N->getOperand(0); 889 break; 890 case TargetLowering::ZeroOrNegativeOneSetCCResult: { 891 ExtendCode = ISD::SIGN_EXTEND; 892 unsigned SignBits = DAG.ComputeNumSignBits(Cond); 893 if (SignBits != CondBits) 894 // All extra bits need to be sign extended. Do this by sign extending the 895 // original condition value all the way to SVT. 896 Cond = N->getOperand(0); 897 break; 898 } 899 } 900 Cond = DAG.getNode(ExtendCode, SVT, Cond); 901 902 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, 903 N->getOperand(1), N->getOperand(2)); 904} 905 906SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 907 assert(OpNo == 0 && "Don't know how to promote this operand!"); 908 909 SDValue LHS = N->getOperand(0); 910 SDValue RHS = N->getOperand(1); 911 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 912 913 // The CC (#4) and the possible return values (#2 and #3) have legal types. 914 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2), 915 N->getOperand(3), N->getOperand(4)); 916} 917 918SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 919 assert(OpNo == 0 && "Don't know how to promote this operand!"); 920 921 SDValue LHS = N->getOperand(0); 922 SDValue RHS = N->getOperand(1); 923 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 924 925 // The CC (#2) is always legal. 926 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); 927} 928 929SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 930 SDValue Op = GetPromotedInteger(N->getOperand(0)); 931 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 932 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), 933 Op, DAG.getValueType(N->getOperand(0).getValueType())); 934} 935 936SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 937 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 938 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 939 int SVOffset = N->getSrcValueOffset(); 940 unsigned Alignment = N->getAlignment(); 941 bool isVolatile = N->isVolatile(); 942 943 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 944 945 assert(!N->isTruncatingStore() && "Cannot promote this store operand!"); 946 947 // Truncate the value and store the result. 948 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(), 949 SVOffset, N->getMemoryVT(), 950 isVolatile, Alignment); 951} 952 953SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 954 SDValue Op = GetPromotedInteger(N->getOperand(0)); 955 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op); 956} 957 958SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 959 SDValue Op = GetPromotedInteger(N->getOperand(0)); 960 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 961 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); 962} 963 964 965//===----------------------------------------------------------------------===// 966// Integer Result Expansion 967//===----------------------------------------------------------------------===// 968 969/// ExpandIntegerResult - This method is called when the specified result of the 970/// specified node is found to need expansion. At this point, the node may also 971/// have invalid operands or may have other results that need promotion, we just 972/// know that (at least) one result needs expansion. 973void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 974 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n"); 975 SDValue Lo, Hi; 976 Lo = Hi = SDValue(); 977 978 // See if the target wants to custom expand this node. 979 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 980 TargetLowering::Custom) { 981 // If the target wants to, allow it to lower this itself. 982 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 983 // Everything that once used N now uses P. We are guaranteed that the 984 // result value types of N and the result value types of P match. 985 ReplaceNodeWith(N, P); 986 return; 987 } 988 } 989 990 switch (N->getOpcode()) { 991 default: 992#ifndef NDEBUG 993 cerr << "ExpandIntegerResult #" << ResNo << ": "; 994 N->dump(&DAG); cerr << "\n"; 995#endif 996 assert(0 && "Do not know how to expand the result of this operator!"); 997 abort(); 998 999 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 1000 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 1001 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 1002 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 1003 1004 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 1005 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 1006 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 1007 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 1008 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 1009 1010 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 1011 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 1012 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 1013 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 1014 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 1015 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 1016 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 1017 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 1018 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 1019 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 1020 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 1021 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 1022 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 1023 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 1024 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 1025 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 1026 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 1027 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 1028 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 1029 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 1030 1031 case ISD::AND: 1032 case ISD::OR: 1033 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 1034 1035 case ISD::ADD: 1036 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1037 1038 case ISD::ADDC: 1039 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1040 1041 case ISD::ADDE: 1042 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1043 1044 case ISD::SHL: 1045 case ISD::SRA: 1046 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1047 } 1048 1049 // If Lo/Hi is null, the sub-method took care of registering results etc. 1050 if (Lo.getNode()) 1051 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1052} 1053 1054/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1055/// and the shift amount is a constant 'Amt'. Expand the operation. 1056void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1057 SDValue &Lo, SDValue &Hi) { 1058 // Expand the incoming operand to be shifted, so that we have its parts 1059 SDValue InL, InH; 1060 GetExpandedInteger(N->getOperand(0), InL, InH); 1061 1062 MVT NVT = InL.getValueType(); 1063 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1064 unsigned NVTBits = NVT.getSizeInBits(); 1065 MVT ShTy = N->getOperand(1).getValueType(); 1066 1067 if (N->getOpcode() == ISD::SHL) { 1068 if (Amt > VTBits) { 1069 Lo = Hi = DAG.getConstant(0, NVT); 1070 } else if (Amt > NVTBits) { 1071 Lo = DAG.getConstant(0, NVT); 1072 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1073 } else if (Amt == NVTBits) { 1074 Lo = DAG.getConstant(0, NVT); 1075 Hi = InL; 1076 } else if (Amt == 1) { 1077 // Emit this X << 1 as X+X. 1078 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1079 SDValue LoOps[2] = { InL, InL }; 1080 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1081 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1082 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1083 } else { 1084 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1085 Hi = DAG.getNode(ISD::OR, NVT, 1086 DAG.getNode(ISD::SHL, NVT, InH, 1087 DAG.getConstant(Amt, ShTy)), 1088 DAG.getNode(ISD::SRL, NVT, InL, 1089 DAG.getConstant(NVTBits-Amt, ShTy))); 1090 } 1091 return; 1092 } 1093 1094 if (N->getOpcode() == ISD::SRL) { 1095 if (Amt > VTBits) { 1096 Lo = DAG.getConstant(0, NVT); 1097 Hi = DAG.getConstant(0, NVT); 1098 } else if (Amt > NVTBits) { 1099 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1100 Hi = DAG.getConstant(0, NVT); 1101 } else if (Amt == NVTBits) { 1102 Lo = InH; 1103 Hi = DAG.getConstant(0, NVT); 1104 } else { 1105 Lo = DAG.getNode(ISD::OR, NVT, 1106 DAG.getNode(ISD::SRL, NVT, InL, 1107 DAG.getConstant(Amt, ShTy)), 1108 DAG.getNode(ISD::SHL, NVT, InH, 1109 DAG.getConstant(NVTBits-Amt, ShTy))); 1110 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1111 } 1112 return; 1113 } 1114 1115 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1116 if (Amt > VTBits) { 1117 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 1118 DAG.getConstant(NVTBits-1, ShTy)); 1119 } else if (Amt > NVTBits) { 1120 Lo = DAG.getNode(ISD::SRA, NVT, InH, 1121 DAG.getConstant(Amt-NVTBits, ShTy)); 1122 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1123 DAG.getConstant(NVTBits-1, ShTy)); 1124 } else if (Amt == NVTBits) { 1125 Lo = InH; 1126 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1127 DAG.getConstant(NVTBits-1, ShTy)); 1128 } else { 1129 Lo = DAG.getNode(ISD::OR, NVT, 1130 DAG.getNode(ISD::SRL, NVT, InL, 1131 DAG.getConstant(Amt, ShTy)), 1132 DAG.getNode(ISD::SHL, NVT, InH, 1133 DAG.getConstant(NVTBits-Amt, ShTy))); 1134 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy)); 1135 } 1136} 1137 1138/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1139/// this shift based on knowledge of the high bit of the shift amount. If we 1140/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1141/// shift amount. 1142bool DAGTypeLegalizer:: 1143ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1144 SDValue Amt = N->getOperand(1); 1145 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1146 MVT ShTy = Amt.getValueType(); 1147 unsigned ShBits = ShTy.getSizeInBits(); 1148 unsigned NVTBits = NVT.getSizeInBits(); 1149 assert(isPowerOf2_32(NVTBits) && 1150 "Expanded integer type size not a power of two!"); 1151 1152 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1153 APInt KnownZero, KnownOne; 1154 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1155 1156 // If we don't know anything about the high bits, exit. 1157 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1158 return false; 1159 1160 // Get the incoming operand to be shifted. 1161 SDValue InL, InH; 1162 GetExpandedInteger(N->getOperand(0), InL, InH); 1163 1164 // If we know that any of the high bits of the shift amount are one, then we 1165 // can do this as a couple of simple shifts. 1166 if (KnownOne.intersects(HighBitMask)) { 1167 // Mask out the high bit, which we know is set. 1168 Amt = DAG.getNode(ISD::AND, ShTy, Amt, 1169 DAG.getConstant(~HighBitMask, ShTy)); 1170 1171 switch (N->getOpcode()) { 1172 default: assert(0 && "Unknown shift"); 1173 case ISD::SHL: 1174 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1175 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 1176 return true; 1177 case ISD::SRL: 1178 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1179 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 1180 return true; 1181 case ISD::SRA: 1182 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 1183 DAG.getConstant(NVTBits-1, ShTy)); 1184 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 1185 return true; 1186 } 1187 } 1188 1189 // If we know that all of the high bits of the shift amount are zero, then we 1190 // can do this as a couple of simple shifts. 1191 if ((KnownZero & HighBitMask) == HighBitMask) { 1192 // Compute 32-amt. 1193 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1194 DAG.getConstant(NVTBits, ShTy), 1195 Amt); 1196 unsigned Op1, Op2; 1197 switch (N->getOpcode()) { 1198 default: assert(0 && "Unknown shift"); 1199 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1200 case ISD::SRL: 1201 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1202 } 1203 1204 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1205 Hi = DAG.getNode(ISD::OR, NVT, 1206 DAG.getNode(Op1, NVT, InH, Amt), 1207 DAG.getNode(Op2, NVT, InL, Amt2)); 1208 return true; 1209 } 1210 1211 return false; 1212} 1213 1214void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1215 SDValue &Lo, SDValue &Hi) { 1216 // Expand the subcomponents. 1217 SDValue LHSL, LHSH, RHSL, RHSH; 1218 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1219 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1220 1221 MVT NVT = LHSL.getValueType(); 1222 SDValue LoOps[2] = { LHSL, RHSL }; 1223 SDValue HiOps[3] = { LHSH, RHSH }; 1224 1225 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1226 // them. TODO: Teach operation legalization how to expand unsupported 1227 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1228 // a carry of type MVT::Flag, but there doesn't seem to be any way to 1229 // generate a value of this type in the expanded code sequence. 1230 bool hasCarry = 1231 TLI.isOperationLegal(N->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC, 1232 TLI.getTypeToExpandTo(NVT)); 1233 1234 if (hasCarry) { 1235 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1236 if (N->getOpcode() == ISD::ADD) { 1237 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1238 HiOps[2] = Lo.getValue(1); 1239 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1240 } else { 1241 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1242 HiOps[2] = Lo.getValue(1); 1243 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1244 } 1245 } else { 1246 if (N->getOpcode() == ISD::ADD) { 1247 Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2); 1248 Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2); 1249 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0], 1250 ISD::SETULT); 1251 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, 1252 DAG.getConstant(1, NVT), 1253 DAG.getConstant(0, NVT)); 1254 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[1], 1255 ISD::SETULT); 1256 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2, 1257 DAG.getConstant(1, NVT), Carry1); 1258 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2); 1259 } else { 1260 Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2); 1261 Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2); 1262 SDValue Cmp = DAG.getSetCC(TLI.getSetCCResultType(LoOps[0]), 1263 LoOps[0], LoOps[1], ISD::SETULT); 1264 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp, 1265 DAG.getConstant(1, NVT), 1266 DAG.getConstant(0, NVT)); 1267 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow); 1268 } 1269 } 1270} 1271 1272void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1273 SDValue &Lo, SDValue &Hi) { 1274 // Expand the subcomponents. 1275 SDValue LHSL, LHSH, RHSL, RHSH; 1276 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1277 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1278 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1279 SDValue LoOps[2] = { LHSL, RHSL }; 1280 SDValue HiOps[3] = { LHSH, RHSH }; 1281 1282 if (N->getOpcode() == ISD::ADDC) { 1283 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1284 HiOps[2] = Lo.getValue(1); 1285 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1286 } else { 1287 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1288 HiOps[2] = Lo.getValue(1); 1289 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1290 } 1291 1292 // Legalized the flag result - switch anything that used the old flag to 1293 // use the new one. 1294 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1295} 1296 1297void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1298 SDValue &Lo, SDValue &Hi) { 1299 // Expand the subcomponents. 1300 SDValue LHSL, LHSH, RHSL, RHSH; 1301 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1302 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1303 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1304 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1305 SDValue HiOps[3] = { LHSH, RHSH }; 1306 1307 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3); 1308 HiOps[2] = Lo.getValue(1); 1309 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3); 1310 1311 // Legalized the flag result - switch anything that used the old flag to 1312 // use the new one. 1313 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1314} 1315 1316void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1317 SDValue &Lo, SDValue &Hi) { 1318 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1319 SDValue Op = N->getOperand(0); 1320 if (Op.getValueType().bitsLE(NVT)) { 1321 // The low part is any extension of the input (which degenerates to a copy). 1322 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op); 1323 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined. 1324 } else { 1325 // For example, extension of an i48 to an i64. The operand type necessarily 1326 // promotes to the result type, so will end up being expanded too. 1327 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1328 "Only know how to promote this result!"); 1329 SDValue Res = GetPromotedInteger(Op); 1330 assert(Res.getValueType() == N->getValueType(0) && 1331 "Operand over promoted?"); 1332 // Split the promoted operand. This will simplify when it is expanded. 1333 SplitInteger(Res, Lo, Hi); 1334 } 1335} 1336 1337void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1338 SDValue &Lo, SDValue &Hi) { 1339 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1340 MVT NVT = Lo.getValueType(); 1341 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1342 unsigned NVTBits = NVT.getSizeInBits(); 1343 unsigned EVTBits = EVT.getSizeInBits(); 1344 1345 if (NVTBits < EVTBits) { 1346 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi, 1347 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1348 } else { 1349 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT)); 1350 // The high part replicates the sign bit of Lo, make it explicit. 1351 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1352 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy())); 1353 } 1354} 1355 1356void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1357 SDValue &Lo, SDValue &Hi) { 1358 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1359 MVT NVT = Lo.getValueType(); 1360 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1361 unsigned NVTBits = NVT.getSizeInBits(); 1362 unsigned EVTBits = EVT.getSizeInBits(); 1363 1364 if (NVTBits < EVTBits) { 1365 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, 1366 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1367 } else { 1368 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); 1369 // The high part must be zero, make it explicit. 1370 Hi = DAG.getConstant(0, NVT); 1371 } 1372} 1373 1374void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1375 SDValue &Lo, SDValue &Hi) { 1376 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1377 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo); 1378 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi); 1379} 1380 1381void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1382 SDValue &Lo, SDValue &Hi) { 1383 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1384 unsigned NBitWidth = NVT.getSizeInBits(); 1385 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1386 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 1387 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1388} 1389 1390void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1391 SDValue &Lo, SDValue &Hi) { 1392 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1393 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1394 MVT NVT = Lo.getValueType(); 1395 1396 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 1397 DAG.getConstant(0, NVT), ISD::SETNE); 1398 1399 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo); 1400 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 1401 1402 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ, 1403 DAG.getNode(ISD::ADD, NVT, LoLZ, 1404 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1405 Hi = DAG.getConstant(0, NVT); 1406} 1407 1408void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1409 SDValue &Lo, SDValue &Hi) { 1410 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1411 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1412 MVT NVT = Lo.getValueType(); 1413 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), 1414 DAG.getNode(ISD::CTPOP, NVT, Hi)); 1415 Hi = DAG.getConstant(0, NVT); 1416} 1417 1418void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1419 SDValue &Lo, SDValue &Hi) { 1420 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1421 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1422 MVT NVT = Lo.getValueType(); 1423 1424 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, 1425 DAG.getConstant(0, NVT), ISD::SETNE); 1426 1427 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 1428 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi); 1429 1430 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ, 1431 DAG.getNode(ISD::ADD, NVT, HiLZ, 1432 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1433 Hi = DAG.getConstant(0, NVT); 1434} 1435 1436void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1437 SDValue &Hi) { 1438 MVT VT = N->getValueType(0); 1439 SDValue Op = N->getOperand(0); 1440 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1441 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1442 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi); 1443} 1444 1445void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1446 SDValue &Hi) { 1447 MVT VT = N->getValueType(0); 1448 SDValue Op = N->getOperand(0); 1449 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1450 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1451 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi); 1452} 1453 1454void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1455 SDValue &Lo, SDValue &Hi) { 1456 if (ISD::isNormalLoad(N)) { 1457 ExpandRes_NormalLoad(N, Lo, Hi); 1458 return; 1459 } 1460 1461 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1462 1463 MVT VT = N->getValueType(0); 1464 MVT NVT = TLI.getTypeToTransformTo(VT); 1465 SDValue Ch = N->getChain(); 1466 SDValue Ptr = N->getBasePtr(); 1467 ISD::LoadExtType ExtType = N->getExtensionType(); 1468 int SVOffset = N->getSrcValueOffset(); 1469 unsigned Alignment = N->getAlignment(); 1470 bool isVolatile = N->isVolatile(); 1471 1472 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1473 1474 if (N->getMemoryVT().bitsLE(NVT)) { 1475 MVT EVT = N->getMemoryVT(); 1476 1477 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, 1478 isVolatile, Alignment); 1479 1480 // Remember the chain. 1481 Ch = Lo.getValue(1); 1482 1483 if (ExtType == ISD::SEXTLOAD) { 1484 // The high part is obtained by SRA'ing all but one of the bits of the 1485 // lo part. 1486 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1487 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1488 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1489 } else if (ExtType == ISD::ZEXTLOAD) { 1490 // The high part is just a zero. 1491 Hi = DAG.getConstant(0, NVT); 1492 } else { 1493 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1494 // The high part is undefined. 1495 Hi = DAG.getNode(ISD::UNDEF, NVT); 1496 } 1497 } else if (TLI.isLittleEndian()) { 1498 // Little-endian - low bits are at low addresses. 1499 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1500 isVolatile, Alignment); 1501 1502 unsigned ExcessBits = 1503 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1504 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1505 1506 // Increment the pointer to the other half. 1507 unsigned IncrementSize = NVT.getSizeInBits()/8; 1508 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1509 DAG.getIntPtrConstant(IncrementSize)); 1510 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), 1511 SVOffset+IncrementSize, NEVT, 1512 isVolatile, MinAlign(Alignment, IncrementSize)); 1513 1514 // Build a factor node to remember that this load is independent of the 1515 // other one. 1516 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1517 Hi.getValue(1)); 1518 } else { 1519 // Big-endian - high bits are at low addresses. Favor aligned loads at 1520 // the cost of some bit-fiddling. 1521 MVT EVT = N->getMemoryVT(); 1522 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1523 unsigned IncrementSize = NVT.getSizeInBits()/8; 1524 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1525 1526 // Load both the high bits and maybe some of the low bits. 1527 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1528 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1529 isVolatile, Alignment); 1530 1531 // Increment the pointer to the other half. 1532 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1533 DAG.getIntPtrConstant(IncrementSize)); 1534 // Load the rest of the low bits. 1535 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(), 1536 SVOffset+IncrementSize, 1537 MVT::getIntegerVT(ExcessBits), 1538 isVolatile, MinAlign(Alignment, IncrementSize)); 1539 1540 // Build a factor node to remember that this load is independent of the 1541 // other one. 1542 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1543 Hi.getValue(1)); 1544 1545 if (ExcessBits < NVT.getSizeInBits()) { 1546 // Transfer low bits from the bottom of Hi to the top of Lo. 1547 Lo = DAG.getNode(ISD::OR, NVT, Lo, 1548 DAG.getNode(ISD::SHL, NVT, Hi, 1549 DAG.getConstant(ExcessBits, 1550 TLI.getShiftAmountTy()))); 1551 // Move high bits to the right position in Hi. 1552 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi, 1553 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1554 TLI.getShiftAmountTy())); 1555 } 1556 } 1557 1558 // Legalized the chain result - switch anything that used the old chain to 1559 // use the new one. 1560 ReplaceValueWith(SDValue(N, 1), Ch); 1561} 1562 1563void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1564 SDValue &Lo, SDValue &Hi) { 1565 SDValue LL, LH, RL, RH; 1566 GetExpandedInteger(N->getOperand(0), LL, LH); 1567 GetExpandedInteger(N->getOperand(1), RL, RH); 1568 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL); 1569 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH); 1570} 1571 1572void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1573 SDValue &Lo, SDValue &Hi) { 1574 MVT VT = N->getValueType(0); 1575 MVT NVT = TLI.getTypeToTransformTo(VT); 1576 1577 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 1578 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 1579 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 1580 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 1581 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1582 SDValue LL, LH, RL, RH; 1583 GetExpandedInteger(N->getOperand(0), LL, LH); 1584 GetExpandedInteger(N->getOperand(1), RL, RH); 1585 unsigned OuterBitSize = VT.getSizeInBits(); 1586 unsigned InnerBitSize = NVT.getSizeInBits(); 1587 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1588 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1589 1590 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1591 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1592 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1593 // The inputs are both zero-extended. 1594 if (HasUMUL_LOHI) { 1595 // We can emit a umul_lohi. 1596 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1597 Hi = SDValue(Lo.getNode(), 1); 1598 return; 1599 } 1600 if (HasMULHU) { 1601 // We can emit a mulhu+mul. 1602 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1603 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1604 return; 1605 } 1606 } 1607 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1608 // The input values are both sign-extended. 1609 if (HasSMUL_LOHI) { 1610 // We can emit a smul_lohi. 1611 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1612 Hi = SDValue(Lo.getNode(), 1); 1613 return; 1614 } 1615 if (HasMULHS) { 1616 // We can emit a mulhs+mul. 1617 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1618 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 1619 return; 1620 } 1621 } 1622 if (HasUMUL_LOHI) { 1623 // Lo,Hi = umul LHS, RHS. 1624 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 1625 DAG.getVTList(NVT, NVT), LL, RL); 1626 Lo = UMulLOHI; 1627 Hi = UMulLOHI.getValue(1); 1628 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1629 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1630 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1631 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1632 return; 1633 } 1634 if (HasMULHU) { 1635 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1636 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1637 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1638 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1639 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1640 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1641 return; 1642 } 1643 } 1644 1645 // If nothing else, we can make a libcall. 1646 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1647 if (VT == MVT::i32) 1648 LC = RTLIB::MUL_I32; 1649 else if (VT == MVT::i64) 1650 LC = RTLIB::MUL_I64; 1651 else if (VT == MVT::i128) 1652 LC = RTLIB::MUL_I128; 1653 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1654 1655 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1656 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi); 1657} 1658 1659void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1660 SDValue &Lo, SDValue &Hi) { 1661 MVT VT = N->getValueType(0); 1662 1663 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1664 if (VT == MVT::i32) 1665 LC = RTLIB::SDIV_I32; 1666 else if (VT == MVT::i64) 1667 LC = RTLIB::SDIV_I64; 1668 else if (VT == MVT::i128) 1669 LC = RTLIB::SDIV_I128; 1670 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1671 1672 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1673 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1674} 1675 1676void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1677 SDValue &Lo, SDValue &Hi) { 1678 MVT VT = N->getValueType(0); 1679 1680 // If we can emit an efficient shift operation, do so now. Check to see if 1681 // the RHS is a constant. 1682 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1683 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1684 1685 // If we can determine that the high bit of the shift is zero or one, even if 1686 // the low bits are variable, emit this shift in an optimized form. 1687 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1688 return; 1689 1690 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1691 unsigned PartsOpc; 1692 if (N->getOpcode() == ISD::SHL) { 1693 PartsOpc = ISD::SHL_PARTS; 1694 } else if (N->getOpcode() == ISD::SRL) { 1695 PartsOpc = ISD::SRL_PARTS; 1696 } else { 1697 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1698 PartsOpc = ISD::SRA_PARTS; 1699 } 1700 1701 // Next check to see if the target supports this SHL_PARTS operation or if it 1702 // will custom expand it. 1703 MVT NVT = TLI.getTypeToTransformTo(VT); 1704 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1705 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1706 Action == TargetLowering::Custom) { 1707 // Expand the subcomponents. 1708 SDValue LHSL, LHSH; 1709 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1710 1711 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1712 MVT VT = LHSL.getValueType(); 1713 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 1714 Hi = Lo.getValue(1); 1715 return; 1716 } 1717 1718 // Otherwise, emit a libcall. 1719 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1720 bool isSigned; 1721 if (N->getOpcode() == ISD::SHL) { 1722 isSigned = false; /*sign irrelevant*/ 1723 if (VT == MVT::i32) 1724 LC = RTLIB::SHL_I32; 1725 else if (VT == MVT::i64) 1726 LC = RTLIB::SHL_I64; 1727 else if (VT == MVT::i128) 1728 LC = RTLIB::SHL_I128; 1729 } else if (N->getOpcode() == ISD::SRL) { 1730 isSigned = false; 1731 if (VT == MVT::i32) 1732 LC = RTLIB::SRL_I32; 1733 else if (VT == MVT::i64) 1734 LC = RTLIB::SRL_I64; 1735 else if (VT == MVT::i128) 1736 LC = RTLIB::SRL_I128; 1737 } else { 1738 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1739 isSigned = true; 1740 if (VT == MVT::i32) 1741 LC = RTLIB::SRA_I32; 1742 else if (VT == MVT::i64) 1743 LC = RTLIB::SRA_I64; 1744 else if (VT == MVT::i128) 1745 LC = RTLIB::SRA_I128; 1746 } 1747 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!"); 1748 1749 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1750 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi); 1751} 1752 1753void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 1754 SDValue &Lo, SDValue &Hi) { 1755 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1756 SDValue Op = N->getOperand(0); 1757 if (Op.getValueType().bitsLE(NVT)) { 1758 // The low part is sign extension of the input (degenerates to a copy). 1759 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); 1760 // The high part is obtained by SRA'ing all but one of the bits of low part. 1761 unsigned LoSize = NVT.getSizeInBits(); 1762 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1763 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1764 } else { 1765 // For example, extension of an i48 to an i64. The operand type necessarily 1766 // promotes to the result type, so will end up being expanded too. 1767 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1768 "Only know how to promote this result!"); 1769 SDValue Res = GetPromotedInteger(Op); 1770 assert(Res.getValueType() == N->getValueType(0) && 1771 "Operand over promoted?"); 1772 // Split the promoted operand. This will simplify when it is expanded. 1773 SplitInteger(Res, Lo, Hi); 1774 unsigned ExcessBits = 1775 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1776 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 1777 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1778 } 1779} 1780 1781void DAGTypeLegalizer:: 1782ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 1783 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1784 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1785 1786 if (EVT.bitsLE(Lo.getValueType())) { 1787 // sext_inreg the low part if needed. 1788 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo, 1789 N->getOperand(1)); 1790 1791 // The high part gets the sign extension from the lo-part. This handles 1792 // things like sextinreg V:i64 from i8. 1793 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo, 1794 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 1795 TLI.getShiftAmountTy())); 1796 } else { 1797 // For example, extension of an i48 to an i64. Leave the low part alone, 1798 // sext_inreg the high part. 1799 unsigned ExcessBits = 1800 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 1801 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 1802 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1803 } 1804} 1805 1806void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1807 SDValue &Lo, SDValue &Hi) { 1808 MVT VT = N->getValueType(0); 1809 1810 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1811 if (VT == MVT::i32) 1812 LC = RTLIB::SREM_I32; 1813 else if (VT == MVT::i64) 1814 LC = RTLIB::SREM_I64; 1815 else if (VT == MVT::i128) 1816 LC = RTLIB::SREM_I128; 1817 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1818 1819 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1820 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1821} 1822 1823void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 1824 SDValue &Lo, SDValue &Hi) { 1825 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1826 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); 1827 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), 1828 DAG.getConstant(NVT.getSizeInBits(), 1829 TLI.getShiftAmountTy())); 1830 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); 1831} 1832 1833void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1834 SDValue &Lo, SDValue &Hi) { 1835 MVT VT = N->getValueType(0); 1836 1837 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1838 if (VT == MVT::i32) 1839 LC = RTLIB::UDIV_I32; 1840 else if (VT == MVT::i64) 1841 LC = RTLIB::UDIV_I64; 1842 else if (VT == MVT::i128) 1843 LC = RTLIB::UDIV_I128; 1844 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 1845 1846 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1847 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1848} 1849 1850void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1851 SDValue &Lo, SDValue &Hi) { 1852 MVT VT = N->getValueType(0); 1853 1854 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1855 if (VT == MVT::i32) 1856 LC = RTLIB::UREM_I32; 1857 else if (VT == MVT::i64) 1858 LC = RTLIB::UREM_I64; 1859 else if (VT == MVT::i128) 1860 LC = RTLIB::UREM_I128; 1861 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 1862 1863 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1864 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1865} 1866 1867void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 1868 SDValue &Lo, SDValue &Hi) { 1869 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1870 SDValue Op = N->getOperand(0); 1871 if (Op.getValueType().bitsLE(NVT)) { 1872 // The low part is zero extension of the input (degenerates to a copy). 1873 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); 1874 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 1875 } else { 1876 // For example, extension of an i48 to an i64. The operand type necessarily 1877 // promotes to the result type, so will end up being expanded too. 1878 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1879 "Only know how to promote this result!"); 1880 SDValue Res = GetPromotedInteger(Op); 1881 assert(Res.getValueType() == N->getValueType(0) && 1882 "Operand over promoted?"); 1883 // Split the promoted operand. This will simplify when it is expanded. 1884 SplitInteger(Res, Lo, Hi); 1885 unsigned ExcessBits = 1886 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1887 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); 1888 } 1889} 1890 1891 1892//===----------------------------------------------------------------------===// 1893// Integer Operand Expansion 1894//===----------------------------------------------------------------------===// 1895 1896/// ExpandIntegerOperand - This method is called when the specified operand of 1897/// the specified node is found to need expansion. At this point, all of the 1898/// result types of the node are known to be legal, but other operands of the 1899/// node may need promotion or expansion as well as the specified one. 1900bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1901 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); 1902 SDValue Res = SDValue(); 1903 1904 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 1905 == TargetLowering::Custom) 1906 Res = TLI.LowerOperation(SDValue(N, 0), DAG); 1907 1908 if (Res.getNode() == 0) { 1909 switch (N->getOpcode()) { 1910 default: 1911 #ifndef NDEBUG 1912 cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; 1913 N->dump(&DAG); cerr << "\n"; 1914 #endif 1915 assert(0 && "Do not know how to expand this operator's operand!"); 1916 abort(); 1917 1918 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1919 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1920 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1921 1922 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1923 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1924 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1925 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 1926 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); 1927 break; 1928 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1929 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 1930 } 1931 } 1932 1933 // If the result is null, the sub-method took care of registering results etc. 1934 if (!Res.getNode()) return false; 1935 // If the result is N, the sub-method updated N in place. Check to see if any 1936 // operands are new, and if so, mark them. 1937 if (Res.getNode() == N) { 1938 // Mark N as new and remark N and its operands. This allows us to correctly 1939 // revisit N if it needs another step of expansion and allows us to visit 1940 // any new operands to N. 1941 ReanalyzeNode(N); 1942 return true; 1943 } 1944 1945 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1946 "Invalid operand expansion"); 1947 1948 ReplaceValueWith(SDValue(N, 0), Res); 1949 return false; 1950} 1951 1952/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 1953/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1954void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 1955 SDValue &NewRHS, 1956 ISD::CondCode &CCCode) { 1957 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 1958 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 1959 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 1960 1961 MVT VT = NewLHS.getValueType(); 1962 1963 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 1964 if (RHSLo == RHSHi) { 1965 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 1966 if (RHSCST->isAllOnesValue()) { 1967 // Equality comparison to -1. 1968 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1969 NewRHS = RHSLo; 1970 return; 1971 } 1972 } 1973 } 1974 1975 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1976 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1977 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS); 1978 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1979 return; 1980 } 1981 1982 // If this is a comparison of the sign bit, just look at the top part. 1983 // X > -1, x < 0 1984 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 1985 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 1986 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 1987 NewLHS = LHSHi; 1988 NewRHS = RHSHi; 1989 return; 1990 } 1991 1992 // FIXME: This generated code sucks. 1993 ISD::CondCode LowCC; 1994 switch (CCCode) { 1995 default: assert(0 && "Unknown integer setcc!"); 1996 case ISD::SETLT: 1997 case ISD::SETULT: LowCC = ISD::SETULT; break; 1998 case ISD::SETGT: 1999 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2000 case ISD::SETLE: 2001 case ISD::SETULE: LowCC = ISD::SETULE; break; 2002 case ISD::SETGE: 2003 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2004 } 2005 2006 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2007 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2008 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2009 2010 // NOTE: on targets without efficient SELECT of bools, we can always use 2011 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2012 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 2013 SDValue Tmp1, Tmp2; 2014 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC, 2015 false, DagCombineInfo); 2016 if (!Tmp1.getNode()) 2017 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 2018 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2019 CCCode, false, DagCombineInfo); 2020 if (!Tmp2.getNode()) 2021 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2022 DAG.getCondCode(CCCode)); 2023 2024 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2025 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2026 if ((Tmp1C && Tmp1C->isNullValue()) || 2027 (Tmp2C && Tmp2C->isNullValue() && 2028 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2029 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2030 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2031 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2032 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2033 // low part is known false, returns high part. 2034 // For LE / GE, if high part is known false, ignore the low part. 2035 // For LT / GT, if high part is known true, ignore the low part. 2036 NewLHS = Tmp2; 2037 NewRHS = SDValue(); 2038 return; 2039 } 2040 2041 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2042 ISD::SETEQ, false, DagCombineInfo); 2043 if (!NewLHS.getNode()) 2044 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2045 ISD::SETEQ); 2046 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 2047 NewLHS, Tmp1, Tmp2); 2048 NewRHS = SDValue(); 2049} 2050 2051SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2052 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2053 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2054 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2055 2056 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2057 // against zero to select between true and false values. 2058 if (NewRHS.getNode() == 0) { 2059 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2060 CCCode = ISD::SETNE; 2061 } 2062 2063 // Update N to have the operands specified. 2064 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 2065 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2066 N->getOperand(4)); 2067} 2068 2069SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2070 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2071 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2072 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2073 2074 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2075 // against zero to select between true and false values. 2076 if (NewRHS.getNode() == 0) { 2077 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2078 CCCode = ISD::SETNE; 2079 } 2080 2081 // Update N to have the operands specified. 2082 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2083 N->getOperand(2), N->getOperand(3), 2084 DAG.getCondCode(CCCode)); 2085} 2086 2087SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2088 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2089 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2090 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2091 2092 // If ExpandSetCCOperands returned a scalar, use it. 2093 if (NewRHS.getNode() == 0) { 2094 assert(NewLHS.getValueType() == N->getValueType(0) && 2095 "Unexpected setcc expansion!"); 2096 return NewLHS; 2097 } 2098 2099 // Otherwise, update N to have the operands specified. 2100 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2101 DAG.getCondCode(CCCode)); 2102} 2103 2104SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2105 SDValue Op = N->getOperand(0); 2106 MVT DstVT = N->getValueType(0); 2107 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2108 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2109 "Don't know how to expand this SINT_TO_FP!"); 2110 return MakeLibCall(LC, DstVT, &Op, 1, true); 2111} 2112 2113SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2114 if (ISD::isNormalStore(N)) 2115 return ExpandOp_NormalStore(N, OpNo); 2116 2117 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2118 assert(OpNo == 1 && "Can only expand the stored value so far"); 2119 2120 MVT VT = N->getOperand(1).getValueType(); 2121 MVT NVT = TLI.getTypeToTransformTo(VT); 2122 SDValue Ch = N->getChain(); 2123 SDValue Ptr = N->getBasePtr(); 2124 int SVOffset = N->getSrcValueOffset(); 2125 unsigned Alignment = N->getAlignment(); 2126 bool isVolatile = N->isVolatile(); 2127 SDValue Lo, Hi; 2128 2129 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2130 2131 if (N->getMemoryVT().bitsLE(NVT)) { 2132 GetExpandedInteger(N->getValue(), Lo, Hi); 2133 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 2134 N->getMemoryVT(), isVolatile, Alignment); 2135 } else if (TLI.isLittleEndian()) { 2136 // Little-endian - low bits are at low addresses. 2137 GetExpandedInteger(N->getValue(), Lo, Hi); 2138 2139 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 2140 isVolatile, Alignment); 2141 2142 unsigned ExcessBits = 2143 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2144 MVT NEVT = MVT::getIntegerVT(ExcessBits); 2145 2146 // Increment the pointer to the other half. 2147 unsigned IncrementSize = NVT.getSizeInBits()/8; 2148 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2149 DAG.getIntPtrConstant(IncrementSize)); 2150 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2151 SVOffset+IncrementSize, NEVT, 2152 isVolatile, MinAlign(Alignment, IncrementSize)); 2153 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2154 } else { 2155 // Big-endian - high bits are at low addresses. Favor aligned stores at 2156 // the cost of some bit-fiddling. 2157 GetExpandedInteger(N->getValue(), Lo, Hi); 2158 2159 MVT EVT = N->getMemoryVT(); 2160 unsigned EBytes = EVT.getStoreSizeInBits()/8; 2161 unsigned IncrementSize = NVT.getSizeInBits()/8; 2162 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2163 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 2164 2165 if (ExcessBits < NVT.getSizeInBits()) { 2166 // Transfer high bits from the top of Lo to the bottom of Hi. 2167 Hi = DAG.getNode(ISD::SHL, NVT, Hi, 2168 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2169 TLI.getShiftAmountTy())); 2170 Hi = DAG.getNode(ISD::OR, NVT, Hi, 2171 DAG.getNode(ISD::SRL, NVT, Lo, 2172 DAG.getConstant(ExcessBits, 2173 TLI.getShiftAmountTy()))); 2174 } 2175 2176 // Store both the high bits and maybe some of the low bits. 2177 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2178 SVOffset, HiVT, isVolatile, Alignment); 2179 2180 // Increment the pointer to the other half. 2181 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2182 DAG.getIntPtrConstant(IncrementSize)); 2183 // Store the lowest ExcessBits bits in the second half. 2184 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), 2185 SVOffset+IncrementSize, 2186 MVT::getIntegerVT(ExcessBits), 2187 isVolatile, MinAlign(Alignment, IncrementSize)); 2188 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2189 } 2190} 2191 2192SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2193 SDValue InL, InH; 2194 GetExpandedInteger(N->getOperand(0), InL, InH); 2195 // Just truncate the low part of the source. 2196 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL); 2197} 2198 2199SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2200 SDValue Op = N->getOperand(0); 2201 MVT SrcVT = Op.getValueType(); 2202 MVT DstVT = N->getValueType(0); 2203 2204 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2205 // Do a signed conversion then adjust the result. 2206 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op); 2207 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2208 2209 // The result of the signed conversion needs adjusting if the 'sign bit' of 2210 // the incoming integer was set. To handle this, we dynamically test to see 2211 // if it is set, and, if so, add a fudge factor. 2212 2213 const uint64_t F32TwoE32 = 0x4F800000ULL; 2214 const uint64_t F32TwoE64 = 0x5F800000ULL; 2215 const uint64_t F32TwoE128 = 0x7F800000ULL; 2216 2217 APInt FF(32, 0); 2218 if (SrcVT == MVT::i32) 2219 FF = APInt(32, F32TwoE32); 2220 else if (SrcVT == MVT::i64) 2221 FF = APInt(32, F32TwoE64); 2222 else if (SrcVT == MVT::i128) 2223 FF = APInt(32, F32TwoE128); 2224 else 2225 assert(false && "Unsupported UINT_TO_FP!"); 2226 2227 // Check whether the sign bit is set. 2228 SDValue Lo, Hi; 2229 GetExpandedInteger(Op, Lo, Hi); 2230 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 2231 DAG.getConstant(0, Hi.getValueType()), 2232 ISD::SETLT); 2233 2234 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2235 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)), 2236 TLI.getPointerTy()); 2237 2238 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2239 SDValue Zero = DAG.getIntPtrConstant(0); 2240 SDValue Four = DAG.getIntPtrConstant(4); 2241 if (TLI.isBigEndian()) std::swap(Zero, Four); 2242 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet, 2243 Zero, Four); 2244 unsigned Alignment = 2245 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2246 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset); 2247 Alignment = std::min(Alignment, 4u); 2248 2249 // Load the value out, extending it from f32 to the destination float type. 2250 // FIXME: Avoid the extend by constructing the right constant pool? 2251 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(), 2252 FudgePtr, NULL, 0, MVT::f32, 2253 false, Alignment); 2254 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge); 2255 } 2256 2257 // Otherwise, use a libcall. 2258 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2259 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2260 "Don't know how to expand this UINT_TO_FP!"); 2261 return MakeLibCall(LC, DstVT, &Op, 1, true); 2262} 2263