LegalizeIntegerTypes.cpp revision 63974b2144c87c962effdc0508c27643c8ad98b6
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Support/ErrorHandling.h" 24#include "llvm/Support/raw_ostream.h" 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28// Integer Result Promotion 29//===----------------------------------------------------------------------===// 30 31/// PromoteIntegerResult - This method is called when a result of a node is 32/// found to be in need of promotion to a larger type. At this point, the node 33/// may also have invalid operands or may have other results that need 34/// expansion, we just know that (at least) one result needs promotion. 35void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n"); 37 SDValue Res = SDValue(); 38 39 // See if the target wants to custom expand this node. 40 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 41 return; 42 43 switch (N->getOpcode()) { 44 default: 45#ifndef NDEBUG 46 dbgs() << "PromoteIntegerResult #" << ResNo << ": "; 47 N->dump(&DAG); dbgs() << "\n"; 48#endif 49 llvm_unreachable("Do not know how to promote this operator!"); 50 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; 51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; 54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 57 case ISD::CONVERT_RNDSAT: 58 Res = PromoteIntRes_CONVERT_RNDSAT(N); break; 59 case ISD::CTLZ_ZERO_UNDEF: 60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; 61 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break; 62 case ISD::CTTZ_ZERO_UNDEF: 63 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; 64 case ISD::EXTRACT_VECTOR_ELT: 65 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 66 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 67 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break; 68 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break; 69 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; 70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 71 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 72 case ISD::SIGN_EXTEND_INREG: 73 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 75 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 76 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; 77 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; 78 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; 79 80 case ISD::EXTRACT_SUBVECTOR: 81 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break; 82 case ISD::VECTOR_SHUFFLE: 83 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break; 84 case ISD::INSERT_VECTOR_ELT: 85 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break; 86 case ISD::BUILD_VECTOR: 87 Res = PromoteIntRes_BUILD_VECTOR(N); break; 88 case ISD::SCALAR_TO_VECTOR: 89 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break; 90 case ISD::CONCAT_VECTORS: 91 Res = PromoteIntRes_CONCAT_VECTORS(N); break; 92 93 case ISD::SIGN_EXTEND: 94 case ISD::ZERO_EXTEND: 95 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; 96 97 case ISD::FP_TO_SINT: 98 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; 99 100 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break; 101 102 case ISD::AND: 103 case ISD::OR: 104 case ISD::XOR: 105 case ISD::ADD: 106 case ISD::SUB: 107 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break; 108 109 case ISD::SDIV: 110 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; 111 112 case ISD::UDIV: 113 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break; 114 115 case ISD::SADDO: 116 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; 117 case ISD::UADDO: 118 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; 119 case ISD::SMULO: 120 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; 121 122 case ISD::ATOMIC_LOAD: 123 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break; 124 125 case ISD::ATOMIC_LOAD_ADD: 126 case ISD::ATOMIC_LOAD_SUB: 127 case ISD::ATOMIC_LOAD_AND: 128 case ISD::ATOMIC_LOAD_OR: 129 case ISD::ATOMIC_LOAD_XOR: 130 case ISD::ATOMIC_LOAD_NAND: 131 case ISD::ATOMIC_LOAD_MIN: 132 case ISD::ATOMIC_LOAD_MAX: 133 case ISD::ATOMIC_LOAD_UMIN: 134 case ISD::ATOMIC_LOAD_UMAX: 135 case ISD::ATOMIC_SWAP: 136 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 137 138 case ISD::ATOMIC_CMP_SWAP: 139 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 140 } 141 142 // If the result is null then the sub-method took care of registering it. 143 if (Res.getNode()) 144 SetPromotedInteger(SDValue(N, ResNo), Res); 145} 146 147SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N, 148 unsigned ResNo) { 149 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); 150 return GetPromotedInteger(Op); 151} 152 153SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 154 // Sign-extend the new bits, and continue the assertion. 155 SDValue Op = SExtPromotedInteger(N->getOperand(0)); 156 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), 157 Op.getValueType(), Op, N->getOperand(1)); 158} 159 160SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 161 // Zero the new bits, and continue the assertion. 162 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 163 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), 164 Op.getValueType(), Op, N->getOperand(1)); 165} 166 167SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) { 168 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 169 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 170 N->getMemoryVT(), ResVT, 171 N->getChain(), N->getBasePtr(), 172 N->getMemOperand(), N->getOrdering(), 173 N->getSynchScope()); 174 // Legalized the chain result - switch anything that used the old chain to 175 // use the new one. 176 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 177 return Res; 178} 179 180SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 181 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 182 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 183 N->getMemoryVT(), 184 N->getChain(), N->getBasePtr(), 185 Op2, N->getMemOperand(), N->getOrdering(), 186 N->getSynchScope()); 187 // Legalized the chain result - switch anything that used the old chain to 188 // use the new one. 189 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 190 return Res; 191} 192 193SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 194 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 195 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 196 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 197 N->getMemoryVT(), N->getChain(), N->getBasePtr(), 198 Op2, Op3, N->getMemOperand(), N->getOrdering(), 199 N->getSynchScope()); 200 // Legalized the chain result - switch anything that used the old chain to 201 // use the new one. 202 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 203 return Res; 204} 205 206SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) { 207 SDValue InOp = N->getOperand(0); 208 EVT InVT = InOp.getValueType(); 209 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); 210 EVT OutVT = N->getValueType(0); 211 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 212 DebugLoc dl = N->getDebugLoc(); 213 214 switch (getTypeAction(InVT)) { 215 default: 216 assert(false && "Unknown type action!"); 217 break; 218 case TargetLowering::TypeLegal: 219 break; 220 case TargetLowering::TypePromoteInteger: 221 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector()) 222 // The input promotes to the same size. Convert the promoted value. 223 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); 224 break; 225 case TargetLowering::TypeSoftenFloat: 226 // Promote the integer operand by hand. 227 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); 228 case TargetLowering::TypeExpandInteger: 229 case TargetLowering::TypeExpandFloat: 230 break; 231 case TargetLowering::TypeScalarizeVector: 232 // Convert the element to an integer and promote it by hand. 233 if (!NOutVT.isVector()) 234 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 235 BitConvertToInteger(GetScalarizedVector(InOp))); 236 break; 237 case TargetLowering::TypeSplitVector: { 238 // For example, i32 = BITCAST v2i16 on alpha. Convert the split 239 // pieces of the input into integers and reassemble in the final type. 240 SDValue Lo, Hi; 241 GetSplitVector(N->getOperand(0), Lo, Hi); 242 Lo = BitConvertToInteger(Lo); 243 Hi = BitConvertToInteger(Hi); 244 245 if (TLI.isBigEndian()) 246 std::swap(Lo, Hi); 247 248 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, 249 EVT::getIntegerVT(*DAG.getContext(), 250 NOutVT.getSizeInBits()), 251 JoinIntegers(Lo, Hi)); 252 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); 253 } 254 case TargetLowering::TypeWidenVector: 255 if (OutVT.bitsEq(NInVT)) 256 // The input is widened to the same size. Convert to the widened value. 257 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp)); 258 } 259 260 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 261 CreateStackStoreLoad(InOp, OutVT)); 262} 263 264SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 265 SDValue Op = GetPromotedInteger(N->getOperand(0)); 266 EVT OVT = N->getValueType(0); 267 EVT NVT = Op.getValueType(); 268 DebugLoc dl = N->getDebugLoc(); 269 270 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 271 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 272 DAG.getConstant(DiffBits, TLI.getPointerTy())); 273} 274 275SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 276 // The pair element type may be legal, or may not promote to the same type as 277 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 278 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), 279 TLI.getTypeToTransformTo(*DAG.getContext(), 280 N->getValueType(0)), JoinIntegers(N->getOperand(0), 281 N->getOperand(1))); 282} 283 284SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 285 EVT VT = N->getValueType(0); 286 // FIXME there is no actual debug info here 287 DebugLoc dl = N->getDebugLoc(); 288 // Zero extend things like i1, sign extend everything else. It shouldn't 289 // matter in theory which one we pick, but this tends to give better code? 290 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 291 SDValue Result = DAG.getNode(Opc, dl, 292 TLI.getTypeToTransformTo(*DAG.getContext(), VT), 293 SDValue(N, 0)); 294 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 295 return Result; 296} 297 298SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 299 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 300 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 301 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 302 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 303 "can only promote integers"); 304 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 305 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0), 306 N->getOperand(1), N->getOperand(2), 307 N->getOperand(3), N->getOperand(4), CvtCode); 308} 309 310SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 311 // Zero extend to the promoted type and do the count there. 312 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 313 DebugLoc dl = N->getDebugLoc(); 314 EVT OVT = N->getValueType(0); 315 EVT NVT = Op.getValueType(); 316 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op); 317 // Subtract off the extra leading bits in the bigger type. 318 return DAG.getNode(ISD::SUB, dl, NVT, Op, 319 DAG.getConstant(NVT.getSizeInBits() - 320 OVT.getSizeInBits(), NVT)); 321} 322 323SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 324 // Zero extend to the promoted type and do the count there. 325 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 326 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op); 327} 328 329SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 330 SDValue Op = GetPromotedInteger(N->getOperand(0)); 331 EVT OVT = N->getValueType(0); 332 EVT NVT = Op.getValueType(); 333 DebugLoc dl = N->getDebugLoc(); 334 if (N->getOpcode() == ISD::CTTZ) { 335 // The count is the same in the promoted type except if the original 336 // value was zero. This can be handled by setting the bit just off 337 // the top of the original type. 338 APInt TopBit(NVT.getSizeInBits(), 0); 339 TopBit.setBit(OVT.getSizeInBits()); 340 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT)); 341 } 342 return DAG.getNode(N->getOpcode(), dl, NVT, Op); 343} 344 345SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 346 DebugLoc dl = N->getDebugLoc(); 347 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 348 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0), 349 N->getOperand(1)); 350} 351 352SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 353 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 354 unsigned NewOpc = N->getOpcode(); 355 DebugLoc dl = N->getDebugLoc(); 356 357 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is 358 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT 359 // and SINT conversions are Custom, there is no way to tell which is 360 // preferable. We choose SINT because that's the right thing on PPC.) 361 if (N->getOpcode() == ISD::FP_TO_UINT && 362 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 363 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) 364 NewOpc = ISD::FP_TO_SINT; 365 366 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); 367 368 // Assert that the converted value fits in the original type. If it doesn't 369 // (eg: because the value being converted is too big), then the result of the 370 // original operation was undefined anyway, so the assert is still correct. 371 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 372 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, 373 DAG.getValueType(N->getValueType(0).getScalarType())); 374} 375 376SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) { 377 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 378 DebugLoc dl = N->getDebugLoc(); 379 380 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 381 382 return DAG.getNode(ISD::AssertZext, dl, 383 NVT, Res, DAG.getValueType(N->getValueType(0))); 384} 385 386SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 387 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 388 DebugLoc dl = N->getDebugLoc(); 389 390 if (getTypeAction(N->getOperand(0).getValueType()) 391 == TargetLowering::TypePromoteInteger) { 392 SDValue Res = GetPromotedInteger(N->getOperand(0)); 393 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 394 395 // If the result and operand types are the same after promotion, simplify 396 // to an in-register extension. 397 if (NVT == Res.getValueType()) { 398 // The high bits are not guaranteed to be anything. Insert an extend. 399 if (N->getOpcode() == ISD::SIGN_EXTEND) 400 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 401 DAG.getValueType(N->getOperand(0).getValueType())); 402 if (N->getOpcode() == ISD::ZERO_EXTEND) 403 return DAG.getZeroExtendInReg(Res, dl, 404 N->getOperand(0).getValueType().getScalarType()); 405 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 406 return Res; 407 } 408 } 409 410 // Otherwise, just extend the original operand all the way to the larger type. 411 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 412} 413 414SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 415 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 416 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 417 ISD::LoadExtType ExtType = 418 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 419 DebugLoc dl = N->getDebugLoc(); 420 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), 421 N->getPointerInfo(), 422 N->getMemoryVT(), N->isVolatile(), 423 N->isNonTemporal(), N->getAlignment()); 424 425 // Legalized the chain result - switch anything that used the old chain to 426 // use the new one. 427 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 428 return Res; 429} 430 431/// Promote the overflow flag of an overflowing arithmetic node. 432SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { 433 // Simply change the return type of the boolean result. 434 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1)); 435 EVT ValueVTs[] = { N->getValueType(0), NVT }; 436 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; 437 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), 438 DAG.getVTList(ValueVTs, 2), Ops, 2); 439 440 // Modified the sum result - switch anything that used the old sum to use 441 // the new one. 442 ReplaceValueWith(SDValue(N, 0), Res); 443 444 return SDValue(Res.getNode(), 1); 445} 446 447SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { 448 if (ResNo == 1) 449 return PromoteIntRes_Overflow(N); 450 451 // The operation overflowed iff the result in the larger type is not the 452 // sign extension of its truncation to the original type. 453 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 454 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 455 EVT OVT = N->getOperand(0).getValueType(); 456 EVT NVT = LHS.getValueType(); 457 DebugLoc dl = N->getDebugLoc(); 458 459 // Do the arithmetic in the larger type. 460 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 461 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 462 463 // Calculate the overflow flag: sign extend the arithmetic result from 464 // the original type. 465 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 466 DAG.getValueType(OVT)); 467 // Overflowed if and only if this is not equal to Res. 468 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 469 470 // Use the calculated overflow everywhere. 471 ReplaceValueWith(SDValue(N, 1), Ofl); 472 473 return Res; 474} 475 476SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 477 // Sign extend the input. 478 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 479 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 480 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 481 LHS.getValueType(), LHS, RHS); 482} 483 484SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 485 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 486 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 487 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 488 LHS.getValueType(), N->getOperand(0),LHS,RHS); 489} 490 491SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) { 492 SDValue Mask = GetPromotedInteger(N->getOperand(0)); 493 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 494 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 495 return DAG.getNode(ISD::VSELECT, N->getDebugLoc(), 496 LHS.getValueType(), Mask, LHS, RHS); 497} 498 499SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 500 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 501 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 502 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 503 LHS.getValueType(), N->getOperand(0), 504 N->getOperand(1), LHS, RHS, N->getOperand(4)); 505} 506 507SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 508 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); 509 510 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 511 512 // Only use the result of getSetCCResultType if it is legal, 513 // otherwise just use the promoted result type (NVT). 514 if (!TLI.isTypeLegal(SVT)) 515 SVT = NVT; 516 517 DebugLoc dl = N->getDebugLoc(); 518 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() && 519 "Vector compare must return a vector result!"); 520 521 // Get the SETCC result using the canonical SETCC type. 522 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0), 523 N->getOperand(1), N->getOperand(2)); 524 525 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 526 // Convert to the expected type. 527 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 528} 529 530SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 531 return DAG.getNode(ISD::SHL, N->getDebugLoc(), 532 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)), 533 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 534} 535 536SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 537 SDValue Op = GetPromotedInteger(N->getOperand(0)); 538 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), 539 Op.getValueType(), Op, N->getOperand(1)); 540} 541 542SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 543 // The input may have strange things in the top bits of the registers, but 544 // these operations don't care. They may have weird bits going out, but 545 // that too is okay if they are integer operations. 546 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 547 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 548 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 549 LHS.getValueType(), LHS, RHS); 550} 551 552SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 553 // The input value must be properly sign extended. 554 SDValue Res = SExtPromotedInteger(N->getOperand(0)); 555 return DAG.getNode(ISD::SRA, N->getDebugLoc(), 556 Res.getValueType(), Res, N->getOperand(1)); 557} 558 559SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 560 // The input value must be properly zero extended. 561 EVT VT = N->getValueType(0); 562 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 563 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 564 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); 565} 566 567SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 568 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 569 SDValue Res; 570 SDValue InOp = N->getOperand(0); 571 DebugLoc dl = N->getDebugLoc(); 572 573 switch (getTypeAction(InOp.getValueType())) { 574 default: llvm_unreachable("Unknown type action!"); 575 case TargetLowering::TypeLegal: 576 case TargetLowering::TypeExpandInteger: 577 Res = InOp; 578 break; 579 case TargetLowering::TypePromoteInteger: 580 Res = GetPromotedInteger(InOp); 581 break; 582 case TargetLowering::TypeSplitVector: 583 EVT InVT = InOp.getValueType(); 584 assert(InVT.isVector() && "Cannot split scalar types"); 585 unsigned NumElts = InVT.getVectorNumElements(); 586 assert(NumElts == NVT.getVectorNumElements() && 587 "Dst and Src must have the same number of elements"); 588 EVT EltVT = InVT.getScalarType(); 589 assert(isPowerOf2_32(NumElts) && 590 "Promoted vector type must be a power of two"); 591 592 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts/2); 593 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(), 594 NumElts/2); 595 596 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp, 597 DAG.getIntPtrConstant(0)); 598 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp, 599 DAG.getIntPtrConstant(NumElts/2)); 600 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1); 601 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2); 602 603 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); 604 } 605 606 // Truncate to NVT instead of VT 607 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res); 608} 609 610SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { 611 if (ResNo == 1) 612 return PromoteIntRes_Overflow(N); 613 614 // The operation overflowed iff the result in the larger type is not the 615 // zero extension of its truncation to the original type. 616 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 617 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 618 EVT OVT = N->getOperand(0).getValueType(); 619 EVT NVT = LHS.getValueType(); 620 DebugLoc dl = N->getDebugLoc(); 621 622 // Do the arithmetic in the larger type. 623 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 624 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 625 626 // Calculate the overflow flag: zero extend the arithmetic result from 627 // the original type. 628 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); 629 // Overflowed if and only if this is not equal to Res. 630 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 631 632 // Use the calculated overflow everywhere. 633 ReplaceValueWith(SDValue(N, 1), Ofl); 634 635 return Res; 636} 637 638SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) { 639 // Promote the overflow bit trivially. 640 if (ResNo == 1) 641 return PromoteIntRes_Overflow(N); 642 643 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1); 644 DebugLoc DL = N->getDebugLoc(); 645 EVT SmallVT = LHS.getValueType(); 646 647 // To determine if the result overflowed in a larger type, we extend the 648 // input to the larger type, do the multiply, then check the high bits of 649 // the result to see if the overflow happened. 650 if (N->getOpcode() == ISD::SMULO) { 651 LHS = SExtPromotedInteger(LHS); 652 RHS = SExtPromotedInteger(RHS); 653 } else { 654 LHS = ZExtPromotedInteger(LHS); 655 RHS = ZExtPromotedInteger(RHS); 656 } 657 SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS); 658 659 // Overflow occurred iff the high part of the result does not 660 // zero/sign-extend the low part. 661 SDValue Overflow; 662 if (N->getOpcode() == ISD::UMULO) { 663 // Unsigned overflow occurred iff the high part is non-zero. 664 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, 665 DAG.getIntPtrConstant(SmallVT.getSizeInBits())); 666 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi, 667 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE); 668 } else { 669 // Signed overflow occurred iff the high part does not sign extend the low. 670 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), 671 Mul, DAG.getValueType(SmallVT)); 672 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE); 673 } 674 675 // Use the calculated overflow everywhere. 676 ReplaceValueWith(SDValue(N, 1), Overflow); 677 return Mul; 678} 679 680SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 681 // Zero extend the input. 682 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 683 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 684 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 685 LHS.getValueType(), LHS, RHS); 686} 687 688SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 689 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(), 690 N->getValueType(0))); 691} 692 693SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 694 SDValue Chain = N->getOperand(0); // Get the chain. 695 SDValue Ptr = N->getOperand(1); // Get the pointer. 696 EVT VT = N->getValueType(0); 697 DebugLoc dl = N->getDebugLoc(); 698 699 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); 700 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT); 701 // The argument is passed as NumRegs registers of type RegVT. 702 703 SmallVector<SDValue, 8> Parts(NumRegs); 704 for (unsigned i = 0; i < NumRegs; ++i) { 705 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), 706 N->getConstantOperandVal(3)); 707 Chain = Parts[i].getValue(1); 708 } 709 710 // Handle endianness of the load. 711 if (TLI.isBigEndian()) 712 std::reverse(Parts.begin(), Parts.end()); 713 714 // Assemble the parts in the promoted type. 715 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 716 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); 717 for (unsigned i = 1; i < NumRegs; ++i) { 718 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); 719 // Shift it to the right position and "or" it in. 720 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, 721 DAG.getConstant(i * RegVT.getSizeInBits(), 722 TLI.getPointerTy())); 723 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); 724 } 725 726 // Modified the chain result - switch anything that used the old chain to 727 // use the new one. 728 ReplaceValueWith(SDValue(N, 1), Chain); 729 730 return Res; 731} 732 733//===----------------------------------------------------------------------===// 734// Integer Operand Promotion 735//===----------------------------------------------------------------------===// 736 737/// PromoteIntegerOperand - This method is called when the specified operand of 738/// the specified node is found to need promotion. At this point, all of the 739/// result types of the node are known to be legal, but other operands of the 740/// node may need promotion or expansion as well as the specified one. 741bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 742 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n"); 743 SDValue Res = SDValue(); 744 745 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 746 return false; 747 748 switch (N->getOpcode()) { 749 default: 750 #ifndef NDEBUG 751 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": "; 752 N->dump(&DAG); dbgs() << "\n"; 753 #endif 754 llvm_unreachable("Do not know how to promote this operator's operand!"); 755 756 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 757 case ISD::ATOMIC_STORE: 758 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N)); 759 break; 760 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break; 761 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 762 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 763 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 764 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 765 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; 766 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break; 767 case ISD::CONVERT_RNDSAT: 768 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 769 case ISD::INSERT_VECTOR_ELT: 770 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 771 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 772 case ISD::SCALAR_TO_VECTOR: 773 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break; 774 case ISD::VSELECT: 775 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 776 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 777 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 778 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 779 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 780 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 781 OpNo); break; 782 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 783 case ISD::FP16_TO_FP32: 784 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; 785 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 786 787 case ISD::SHL: 788 case ISD::SRA: 789 case ISD::SRL: 790 case ISD::ROTL: 791 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; 792 } 793 794 // If the result is null, the sub-method took care of registering results etc. 795 if (!Res.getNode()) return false; 796 797 // If the result is N, the sub-method updated N in place. Tell the legalizer 798 // core about this. 799 if (Res.getNode() == N) 800 return true; 801 802 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 803 "Invalid operand expansion"); 804 805 ReplaceValueWith(SDValue(N, 0), Res); 806 return false; 807} 808 809/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 810/// shared among BR_CC, SELECT_CC, and SETCC handlers. 811void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 812 ISD::CondCode CCCode) { 813 // We have to insert explicit sign or zero extends. Note that we could 814 // insert sign extends for ALL conditions, but zero extend is cheaper on 815 // many machines (an AND instead of two shifts), so prefer it. 816 switch (CCCode) { 817 default: llvm_unreachable("Unknown integer comparison!"); 818 case ISD::SETEQ: 819 case ISD::SETNE: 820 case ISD::SETUGE: 821 case ISD::SETUGT: 822 case ISD::SETULE: 823 case ISD::SETULT: 824 // ALL of these operations will work if we either sign or zero extend 825 // the operands (including the unsigned comparisons!). Zero extend is 826 // usually a simpler/cheaper operation, so prefer it. 827 NewLHS = ZExtPromotedInteger(NewLHS); 828 NewRHS = ZExtPromotedInteger(NewRHS); 829 break; 830 case ISD::SETGE: 831 case ISD::SETGT: 832 case ISD::SETLT: 833 case ISD::SETLE: 834 NewLHS = SExtPromotedInteger(NewLHS); 835 NewRHS = SExtPromotedInteger(NewRHS); 836 break; 837 } 838} 839 840SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 841 SDValue Op = GetPromotedInteger(N->getOperand(0)); 842 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); 843} 844 845SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) { 846 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 847 return DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), N->getMemoryVT(), 848 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(), 849 N->getOrdering(), N->getSynchScope()); 850} 851 852SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) { 853 // This should only occur in unusual situations like bitcasting to an 854 // x86_fp80, so just turn it into a store+load 855 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0)); 856} 857 858SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 859 assert(OpNo == 2 && "Don't know how to promote this operand!"); 860 861 SDValue LHS = N->getOperand(2); 862 SDValue RHS = N->getOperand(3); 863 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 864 865 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 866 // legal types. 867 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 868 N->getOperand(1), LHS, RHS, N->getOperand(4)), 869 0); 870} 871 872SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 873 assert(OpNo == 1 && "only know how to promote condition"); 874 875 // Promote all the way up to the canonical SetCC type. 876 EVT SVT = TLI.getSetCCResultType(MVT::Other); 877 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT); 878 879 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 880 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond, 881 N->getOperand(2)), 0); 882} 883 884SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 885 // Since the result type is legal, the operands must promote to it. 886 EVT OVT = N->getOperand(0).getValueType(); 887 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); 888 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 889 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 890 DebugLoc dl = N->getDebugLoc(); 891 892 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, 893 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy())); 894 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); 895} 896 897SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 898 // The vector type is legal but the element type is not. This implies 899 // that the vector is a power-of-two in length and that the element 900 // type does not have a strange size (eg: it is not i1). 901 EVT VecVT = N->getValueType(0); 902 unsigned NumElts = VecVT.getVectorNumElements(); 903 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 904 905 // Promote the inserted value. The type does not need to match the 906 // vector element type. Check that any extra bits introduced will be 907 // truncated away. 908 assert(N->getOperand(0).getValueType().getSizeInBits() >= 909 N->getValueType(0).getVectorElementType().getSizeInBits() && 910 "Type of inserted value narrower than vector element type!"); 911 912 SmallVector<SDValue, 16> NewOps; 913 for (unsigned i = 0; i < NumElts; ++i) 914 NewOps.push_back(GetPromotedInteger(N->getOperand(i))); 915 916 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0); 917} 918 919SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 920 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 921 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 922 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 923 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 924 "can only promote integer arguments"); 925 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 926 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp, 927 N->getOperand(1), N->getOperand(2), 928 N->getOperand(3), N->getOperand(4), CvtCode); 929} 930 931SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 932 unsigned OpNo) { 933 if (OpNo == 1) { 934 // Promote the inserted value. This is valid because the type does not 935 // have to match the vector element type. 936 937 // Check that any extra bits introduced will be truncated away. 938 assert(N->getOperand(1).getValueType().getSizeInBits() >= 939 N->getValueType(0).getVectorElementType().getSizeInBits() && 940 "Type of inserted value narrower than vector element type!"); 941 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 942 GetPromotedInteger(N->getOperand(1)), 943 N->getOperand(2)), 944 0); 945 } 946 947 assert(OpNo == 2 && "Different operand and result vector types?"); 948 949 // Promote the index. 950 SDValue Idx = ZExtPromotedInteger(N->getOperand(2)); 951 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 952 N->getOperand(1), Idx), 0); 953} 954 955SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 956 SDValue NewOps[6]; 957 DebugLoc dl = N->getDebugLoc(); 958 NewOps[0] = N->getOperand(0); 959 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 960 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 961 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1); 962 } 963 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0); 964} 965 966SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) { 967 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote 968 // the operand in place. 969 return SDValue(DAG.UpdateNodeOperands(N, 970 GetPromotedInteger(N->getOperand(0))), 0); 971} 972 973SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 974 assert(OpNo == 0 && "Only know how to promote the condition!"); 975 SDValue Cond = N->getOperand(0); 976 EVT OpTy = N->getOperand(1).getValueType(); 977 978 // Promote all the way up to the canonical SetCC type. 979 EVT SVT = TLI.getSetCCResultType(N->getOpcode() == ISD::SELECT ? 980 OpTy.getScalarType() : OpTy); 981 Cond = PromoteTargetBoolean(Cond, SVT); 982 983 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1), 984 N->getOperand(2)), 0); 985} 986 987SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 988 assert(OpNo == 0 && "Don't know how to promote this operand!"); 989 990 SDValue LHS = N->getOperand(0); 991 SDValue RHS = N->getOperand(1); 992 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 993 994 // The CC (#4) and the possible return values (#2 and #3) have legal types. 995 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2), 996 N->getOperand(3), N->getOperand(4)), 0); 997} 998 999SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 1000 assert(OpNo == 0 && "Don't know how to promote this operand!"); 1001 1002 SDValue LHS = N->getOperand(0); 1003 SDValue RHS = N->getOperand(1); 1004 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 1005 1006 // The CC (#2) is always legal. 1007 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0); 1008} 1009 1010SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) { 1011 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 1012 ZExtPromotedInteger(N->getOperand(1))), 0); 1013} 1014 1015SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 1016 SDValue Op = GetPromotedInteger(N->getOperand(0)); 1017 DebugLoc dl = N->getDebugLoc(); 1018 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 1019 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), 1020 Op, DAG.getValueType(N->getOperand(0).getValueType())); 1021} 1022 1023SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { 1024 return SDValue(DAG.UpdateNodeOperands(N, 1025 SExtPromotedInteger(N->getOperand(0))), 0); 1026} 1027 1028SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 1029 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 1030 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 1031 unsigned Alignment = N->getAlignment(); 1032 bool isVolatile = N->isVolatile(); 1033 bool isNonTemporal = N->isNonTemporal(); 1034 DebugLoc dl = N->getDebugLoc(); 1035 1036 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 1037 1038 // Truncate the value and store the result. 1039 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(), 1040 N->getMemoryVT(), 1041 isVolatile, isNonTemporal, Alignment); 1042} 1043 1044SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 1045 SDValue Op = GetPromotedInteger(N->getOperand(0)); 1046 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op); 1047} 1048 1049SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { 1050 return SDValue(DAG.UpdateNodeOperands(N, 1051 ZExtPromotedInteger(N->getOperand(0))), 0); 1052} 1053 1054SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 1055 DebugLoc dl = N->getDebugLoc(); 1056 SDValue Op = GetPromotedInteger(N->getOperand(0)); 1057 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 1058 return DAG.getZeroExtendInReg(Op, dl, 1059 N->getOperand(0).getValueType().getScalarType()); 1060} 1061 1062 1063//===----------------------------------------------------------------------===// 1064// Integer Result Expansion 1065//===----------------------------------------------------------------------===// 1066 1067/// ExpandIntegerResult - This method is called when the specified result of the 1068/// specified node is found to need expansion. At this point, the node may also 1069/// have invalid operands or may have other results that need promotion, we just 1070/// know that (at least) one result needs expansion. 1071void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 1072 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n"); 1073 SDValue Lo, Hi; 1074 Lo = Hi = SDValue(); 1075 1076 // See if the target wants to custom expand this node. 1077 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 1078 return; 1079 1080 switch (N->getOpcode()) { 1081 default: 1082#ifndef NDEBUG 1083 dbgs() << "ExpandIntegerResult #" << ResNo << ": "; 1084 N->dump(&DAG); dbgs() << "\n"; 1085#endif 1086 llvm_unreachable("Do not know how to expand the result of this operator!"); 1087 1088 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 1089 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 1090 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 1091 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 1092 1093 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break; 1094 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 1095 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 1096 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 1097 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 1098 1099 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 1100 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 1101 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 1102 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 1103 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 1104 case ISD::CTLZ_ZERO_UNDEF: 1105 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 1106 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 1107 case ISD::CTTZ_ZERO_UNDEF: 1108 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 1109 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 1110 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 1111 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 1112 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 1113 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 1114 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 1115 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 1116 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 1117 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 1118 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 1119 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 1120 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 1121 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break; 1122 1123 case ISD::ATOMIC_LOAD_ADD: 1124 case ISD::ATOMIC_LOAD_SUB: 1125 case ISD::ATOMIC_LOAD_AND: 1126 case ISD::ATOMIC_LOAD_OR: 1127 case ISD::ATOMIC_LOAD_XOR: 1128 case ISD::ATOMIC_LOAD_NAND: 1129 case ISD::ATOMIC_LOAD_MIN: 1130 case ISD::ATOMIC_LOAD_MAX: 1131 case ISD::ATOMIC_LOAD_UMIN: 1132 case ISD::ATOMIC_LOAD_UMAX: 1133 case ISD::ATOMIC_SWAP: { 1134 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N); 1135 SplitInteger(Tmp.first, Lo, Hi); 1136 ReplaceValueWith(SDValue(N, 1), Tmp.second); 1137 break; 1138 } 1139 1140 case ISD::AND: 1141 case ISD::OR: 1142 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 1143 1144 case ISD::ADD: 1145 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1146 1147 case ISD::ADDC: 1148 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1149 1150 case ISD::ADDE: 1151 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1152 1153 case ISD::SHL: 1154 case ISD::SRA: 1155 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1156 1157 case ISD::SADDO: 1158 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break; 1159 case ISD::UADDO: 1160 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break; 1161 case ISD::UMULO: 1162 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; 1163 } 1164 1165 // If Lo/Hi is null, the sub-method took care of registering results etc. 1166 if (Lo.getNode()) 1167 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1168} 1169 1170/// Lower an atomic node to the appropriate builtin call. 1171std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) { 1172 unsigned Opc = Node->getOpcode(); 1173 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 1174 RTLIB::Libcall LC; 1175 1176 switch (Opc) { 1177 default: 1178 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 1179 break; 1180 case ISD::ATOMIC_SWAP: 1181 switch (VT.SimpleTy) { 1182 default: llvm_unreachable("Unexpected value type for atomic!"); 1183 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 1184 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 1185 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 1186 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 1187 } 1188 break; 1189 case ISD::ATOMIC_CMP_SWAP: 1190 switch (VT.SimpleTy) { 1191 default: llvm_unreachable("Unexpected value type for atomic!"); 1192 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 1193 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 1194 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 1195 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 1196 } 1197 break; 1198 case ISD::ATOMIC_LOAD_ADD: 1199 switch (VT.SimpleTy) { 1200 default: llvm_unreachable("Unexpected value type for atomic!"); 1201 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 1202 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 1203 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 1204 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 1205 } 1206 break; 1207 case ISD::ATOMIC_LOAD_SUB: 1208 switch (VT.SimpleTy) { 1209 default: llvm_unreachable("Unexpected value type for atomic!"); 1210 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 1211 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 1212 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 1213 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 1214 } 1215 break; 1216 case ISD::ATOMIC_LOAD_AND: 1217 switch (VT.SimpleTy) { 1218 default: llvm_unreachable("Unexpected value type for atomic!"); 1219 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 1220 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 1221 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 1222 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 1223 } 1224 break; 1225 case ISD::ATOMIC_LOAD_OR: 1226 switch (VT.SimpleTy) { 1227 default: llvm_unreachable("Unexpected value type for atomic!"); 1228 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 1229 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 1230 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 1231 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 1232 } 1233 break; 1234 case ISD::ATOMIC_LOAD_XOR: 1235 switch (VT.SimpleTy) { 1236 default: llvm_unreachable("Unexpected value type for atomic!"); 1237 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 1238 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 1239 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 1240 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 1241 } 1242 break; 1243 case ISD::ATOMIC_LOAD_NAND: 1244 switch (VT.SimpleTy) { 1245 default: llvm_unreachable("Unexpected value type for atomic!"); 1246 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 1247 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 1248 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 1249 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 1250 } 1251 break; 1252 } 1253 1254 return ExpandChainLibCall(LC, Node, false); 1255} 1256 1257/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1258/// and the shift amount is a constant 'Amt'. Expand the operation. 1259void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1260 SDValue &Lo, SDValue &Hi) { 1261 DebugLoc DL = N->getDebugLoc(); 1262 // Expand the incoming operand to be shifted, so that we have its parts 1263 SDValue InL, InH; 1264 GetExpandedInteger(N->getOperand(0), InL, InH); 1265 1266 EVT NVT = InL.getValueType(); 1267 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1268 unsigned NVTBits = NVT.getSizeInBits(); 1269 EVT ShTy = N->getOperand(1).getValueType(); 1270 1271 if (N->getOpcode() == ISD::SHL) { 1272 if (Amt > VTBits) { 1273 Lo = Hi = DAG.getConstant(0, NVT); 1274 } else if (Amt > NVTBits) { 1275 Lo = DAG.getConstant(0, NVT); 1276 Hi = DAG.getNode(ISD::SHL, DL, 1277 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy)); 1278 } else if (Amt == NVTBits) { 1279 Lo = DAG.getConstant(0, NVT); 1280 Hi = InL; 1281 } else if (Amt == 1 && 1282 TLI.isOperationLegalOrCustom(ISD::ADDC, 1283 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) { 1284 // Emit this X << 1 as X+X. 1285 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); 1286 SDValue LoOps[2] = { InL, InL }; 1287 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2); 1288 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1289 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3); 1290 } else { 1291 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1292 Hi = DAG.getNode(ISD::OR, DL, NVT, 1293 DAG.getNode(ISD::SHL, DL, NVT, InH, 1294 DAG.getConstant(Amt, ShTy)), 1295 DAG.getNode(ISD::SRL, DL, NVT, InL, 1296 DAG.getConstant(NVTBits-Amt, ShTy))); 1297 } 1298 return; 1299 } 1300 1301 if (N->getOpcode() == ISD::SRL) { 1302 if (Amt > VTBits) { 1303 Lo = DAG.getConstant(0, NVT); 1304 Hi = DAG.getConstant(0, NVT); 1305 } else if (Amt > NVTBits) { 1306 Lo = DAG.getNode(ISD::SRL, DL, 1307 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1308 Hi = DAG.getConstant(0, NVT); 1309 } else if (Amt == NVTBits) { 1310 Lo = InH; 1311 Hi = DAG.getConstant(0, NVT); 1312 } else { 1313 Lo = DAG.getNode(ISD::OR, DL, NVT, 1314 DAG.getNode(ISD::SRL, DL, NVT, InL, 1315 DAG.getConstant(Amt, ShTy)), 1316 DAG.getNode(ISD::SHL, DL, NVT, InH, 1317 DAG.getConstant(NVTBits-Amt, ShTy))); 1318 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1319 } 1320 return; 1321 } 1322 1323 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1324 if (Amt > VTBits) { 1325 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, 1326 DAG.getConstant(NVTBits-1, ShTy)); 1327 } else if (Amt > NVTBits) { 1328 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, 1329 DAG.getConstant(Amt-NVTBits, ShTy)); 1330 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, 1331 DAG.getConstant(NVTBits-1, ShTy)); 1332 } else if (Amt == NVTBits) { 1333 Lo = InH; 1334 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, 1335 DAG.getConstant(NVTBits-1, ShTy)); 1336 } else { 1337 Lo = DAG.getNode(ISD::OR, DL, NVT, 1338 DAG.getNode(ISD::SRL, DL, NVT, InL, 1339 DAG.getConstant(Amt, ShTy)), 1340 DAG.getNode(ISD::SHL, DL, NVT, InH, 1341 DAG.getConstant(NVTBits-Amt, ShTy))); 1342 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1343 } 1344} 1345 1346/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1347/// this shift based on knowledge of the high bit of the shift amount. If we 1348/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1349/// shift amount. 1350bool DAGTypeLegalizer:: 1351ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1352 SDValue Amt = N->getOperand(1); 1353 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1354 EVT ShTy = Amt.getValueType(); 1355 unsigned ShBits = ShTy.getScalarType().getSizeInBits(); 1356 unsigned NVTBits = NVT.getScalarType().getSizeInBits(); 1357 assert(isPowerOf2_32(NVTBits) && 1358 "Expanded integer type size not a power of two!"); 1359 DebugLoc dl = N->getDebugLoc(); 1360 1361 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1362 APInt KnownZero, KnownOne; 1363 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1364 1365 // If we don't know anything about the high bits, exit. 1366 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1367 return false; 1368 1369 // Get the incoming operand to be shifted. 1370 SDValue InL, InH; 1371 GetExpandedInteger(N->getOperand(0), InL, InH); 1372 1373 // If we know that any of the high bits of the shift amount are one, then we 1374 // can do this as a couple of simple shifts. 1375 if (KnownOne.intersects(HighBitMask)) { 1376 // Mask out the high bit, which we know is set. 1377 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, 1378 DAG.getConstant(~HighBitMask, ShTy)); 1379 1380 switch (N->getOpcode()) { 1381 default: llvm_unreachable("Unknown shift"); 1382 case ISD::SHL: 1383 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1384 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 1385 return true; 1386 case ISD::SRL: 1387 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1388 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 1389 return true; 1390 case ISD::SRA: 1391 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 1392 DAG.getConstant(NVTBits-1, ShTy)); 1393 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 1394 return true; 1395 } 1396 } 1397 1398#if 0 1399 // FIXME: This code is broken for shifts with a zero amount! 1400 // If we know that all of the high bits of the shift amount are zero, then we 1401 // can do this as a couple of simple shifts. 1402 if ((KnownZero & HighBitMask) == HighBitMask) { 1403 // Compute 32-amt. 1404 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1405 DAG.getConstant(NVTBits, ShTy), 1406 Amt); 1407 unsigned Op1, Op2; 1408 switch (N->getOpcode()) { 1409 default: llvm_unreachable("Unknown shift"); 1410 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1411 case ISD::SRL: 1412 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1413 } 1414 1415 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1416 Hi = DAG.getNode(ISD::OR, NVT, 1417 DAG.getNode(Op1, NVT, InH, Amt), 1418 DAG.getNode(Op2, NVT, InL, Amt2)); 1419 return true; 1420 } 1421#endif 1422 1423 return false; 1424} 1425 1426/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift 1427/// of any size. 1428bool DAGTypeLegalizer:: 1429ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1430 SDValue Amt = N->getOperand(1); 1431 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1432 EVT ShTy = Amt.getValueType(); 1433 unsigned NVTBits = NVT.getSizeInBits(); 1434 assert(isPowerOf2_32(NVTBits) && 1435 "Expanded integer type size not a power of two!"); 1436 DebugLoc dl = N->getDebugLoc(); 1437 1438 // Get the incoming operand to be shifted. 1439 SDValue InL, InH; 1440 GetExpandedInteger(N->getOperand(0), InL, InH); 1441 1442 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy); 1443 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode); 1444 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt); 1445 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy), 1446 Amt, NVBitsNode, ISD::SETULT); 1447 1448 SDValue LoS, HiS, LoL, HiL; 1449 switch (N->getOpcode()) { 1450 default: llvm_unreachable("Unknown shift"); 1451 case ISD::SHL: 1452 // Short: ShAmt < NVTBits 1453 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); 1454 HiS = DAG.getNode(ISD::OR, dl, NVT, 1455 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt), 1456 // FIXME: If Amt is zero, the following shift generates an undefined result 1457 // on some architectures. 1458 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack)); 1459 1460 // Long: ShAmt >= NVTBits 1461 LoL = DAG.getConstant(0, NVT); // Lo part is zero. 1462 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part. 1463 1464 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1465 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1466 return true; 1467 case ISD::SRL: 1468 // Short: ShAmt < NVTBits 1469 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); 1470 LoS = DAG.getNode(ISD::OR, dl, NVT, 1471 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1472 // FIXME: If Amt is zero, the following shift generates an undefined result 1473 // on some architectures. 1474 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); 1475 1476 // Long: ShAmt >= NVTBits 1477 HiL = DAG.getConstant(0, NVT); // Hi part is zero. 1478 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part. 1479 1480 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1481 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1482 return true; 1483 case ISD::SRA: 1484 // Short: ShAmt < NVTBits 1485 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); 1486 LoS = DAG.getNode(ISD::OR, dl, NVT, 1487 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1488 // FIXME: If Amt is zero, the following shift generates an undefined result 1489 // on some architectures. 1490 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); 1491 1492 // Long: ShAmt >= NVTBits 1493 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part. 1494 DAG.getConstant(NVTBits-1, ShTy)); 1495 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part. 1496 1497 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1498 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1499 return true; 1500 } 1501 1502 return false; 1503} 1504 1505void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1506 SDValue &Lo, SDValue &Hi) { 1507 DebugLoc dl = N->getDebugLoc(); 1508 // Expand the subcomponents. 1509 SDValue LHSL, LHSH, RHSL, RHSH; 1510 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1511 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1512 1513 EVT NVT = LHSL.getValueType(); 1514 SDValue LoOps[2] = { LHSL, RHSL }; 1515 SDValue HiOps[3] = { LHSH, RHSH }; 1516 1517 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1518 // them. TODO: Teach operation legalization how to expand unsupported 1519 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1520 // a carry of type MVT::Glue, but there doesn't seem to be any way to 1521 // generate a value of this type in the expanded code sequence. 1522 bool hasCarry = 1523 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? 1524 ISD::ADDC : ISD::SUBC, 1525 TLI.getTypeToExpandTo(*DAG.getContext(), NVT)); 1526 1527 if (hasCarry) { 1528 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); 1529 if (N->getOpcode() == ISD::ADD) { 1530 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1531 HiOps[2] = Lo.getValue(1); 1532 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1533 } else { 1534 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1535 HiOps[2] = Lo.getValue(1); 1536 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1537 } 1538 return; 1539 } 1540 1541 if (N->getOpcode() == ISD::ADD) { 1542 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); 1543 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); 1544 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0], 1545 ISD::SETULT); 1546 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, 1547 DAG.getConstant(1, NVT), 1548 DAG.getConstant(0, NVT)); 1549 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1], 1550 ISD::SETULT); 1551 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, 1552 DAG.getConstant(1, NVT), Carry1); 1553 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); 1554 } else { 1555 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 1556 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); 1557 SDValue Cmp = 1558 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()), 1559 LoOps[0], LoOps[1], ISD::SETULT); 1560 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, 1561 DAG.getConstant(1, NVT), 1562 DAG.getConstant(0, NVT)); 1563 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); 1564 } 1565} 1566 1567void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1568 SDValue &Lo, SDValue &Hi) { 1569 // Expand the subcomponents. 1570 SDValue LHSL, LHSH, RHSL, RHSH; 1571 DebugLoc dl = N->getDebugLoc(); 1572 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1573 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1574 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue); 1575 SDValue LoOps[2] = { LHSL, RHSL }; 1576 SDValue HiOps[3] = { LHSH, RHSH }; 1577 1578 if (N->getOpcode() == ISD::ADDC) { 1579 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1580 HiOps[2] = Lo.getValue(1); 1581 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1582 } else { 1583 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1584 HiOps[2] = Lo.getValue(1); 1585 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1586 } 1587 1588 // Legalized the flag result - switch anything that used the old flag to 1589 // use the new one. 1590 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1591} 1592 1593void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1594 SDValue &Lo, SDValue &Hi) { 1595 // Expand the subcomponents. 1596 SDValue LHSL, LHSH, RHSL, RHSH; 1597 DebugLoc dl = N->getDebugLoc(); 1598 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1599 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1600 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue); 1601 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1602 SDValue HiOps[3] = { LHSH, RHSH }; 1603 1604 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3); 1605 HiOps[2] = Lo.getValue(1); 1606 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); 1607 1608 // Legalized the flag result - switch anything that used the old flag to 1609 // use the new one. 1610 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1611} 1612 1613void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo, 1614 SDValue &Lo, SDValue &Hi) { 1615 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo); 1616 SplitInteger(Res, Lo, Hi); 1617} 1618 1619void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1620 SDValue &Lo, SDValue &Hi) { 1621 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1622 DebugLoc dl = N->getDebugLoc(); 1623 SDValue Op = N->getOperand(0); 1624 if (Op.getValueType().bitsLE(NVT)) { 1625 // The low part is any extension of the input (which degenerates to a copy). 1626 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); 1627 Hi = DAG.getUNDEF(NVT); // The high part is undefined. 1628 } else { 1629 // For example, extension of an i48 to an i64. The operand type necessarily 1630 // promotes to the result type, so will end up being expanded too. 1631 assert(getTypeAction(Op.getValueType()) == 1632 TargetLowering::TypePromoteInteger && 1633 "Only know how to promote this result!"); 1634 SDValue Res = GetPromotedInteger(Op); 1635 assert(Res.getValueType() == N->getValueType(0) && 1636 "Operand over promoted?"); 1637 // Split the promoted operand. This will simplify when it is expanded. 1638 SplitInteger(Res, Lo, Hi); 1639 } 1640} 1641 1642void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1643 SDValue &Lo, SDValue &Hi) { 1644 DebugLoc dl = N->getDebugLoc(); 1645 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1646 EVT NVT = Lo.getValueType(); 1647 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1648 unsigned NVTBits = NVT.getSizeInBits(); 1649 unsigned EVTBits = EVT.getSizeInBits(); 1650 1651 if (NVTBits < EVTBits) { 1652 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, 1653 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1654 EVTBits - NVTBits))); 1655 } else { 1656 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); 1657 // The high part replicates the sign bit of Lo, make it explicit. 1658 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1659 DAG.getConstant(NVTBits-1, TLI.getPointerTy())); 1660 } 1661} 1662 1663void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1664 SDValue &Lo, SDValue &Hi) { 1665 DebugLoc dl = N->getDebugLoc(); 1666 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1667 EVT NVT = Lo.getValueType(); 1668 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1669 unsigned NVTBits = NVT.getSizeInBits(); 1670 unsigned EVTBits = EVT.getSizeInBits(); 1671 1672 if (NVTBits < EVTBits) { 1673 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, 1674 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1675 EVTBits - NVTBits))); 1676 } else { 1677 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); 1678 // The high part must be zero, make it explicit. 1679 Hi = DAG.getConstant(0, NVT); 1680 } 1681} 1682 1683void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1684 SDValue &Lo, SDValue &Hi) { 1685 DebugLoc dl = N->getDebugLoc(); 1686 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1687 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo); 1688 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi); 1689} 1690 1691void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1692 SDValue &Lo, SDValue &Hi) { 1693 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1694 unsigned NBitWidth = NVT.getSizeInBits(); 1695 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1696 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT); 1697 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1698} 1699 1700void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1701 SDValue &Lo, SDValue &Hi) { 1702 DebugLoc dl = N->getDebugLoc(); 1703 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1704 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1705 EVT NVT = Lo.getValueType(); 1706 1707 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi, 1708 DAG.getConstant(0, NVT), ISD::SETNE); 1709 1710 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo); 1711 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi); 1712 1713 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ, 1714 DAG.getNode(ISD::ADD, dl, NVT, LoLZ, 1715 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1716 Hi = DAG.getConstant(0, NVT); 1717} 1718 1719void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1720 SDValue &Lo, SDValue &Hi) { 1721 DebugLoc dl = N->getDebugLoc(); 1722 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1723 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1724 EVT NVT = Lo.getValueType(); 1725 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), 1726 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); 1727 Hi = DAG.getConstant(0, NVT); 1728} 1729 1730void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1731 SDValue &Lo, SDValue &Hi) { 1732 DebugLoc dl = N->getDebugLoc(); 1733 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1734 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1735 EVT NVT = Lo.getValueType(); 1736 1737 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, 1738 DAG.getConstant(0, NVT), ISD::SETNE); 1739 1740 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo); 1741 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi); 1742 1743 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ, 1744 DAG.getNode(ISD::ADD, dl, NVT, HiLZ, 1745 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1746 Hi = DAG.getConstant(0, NVT); 1747} 1748 1749void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1750 SDValue &Hi) { 1751 DebugLoc dl = N->getDebugLoc(); 1752 EVT VT = N->getValueType(0); 1753 SDValue Op = N->getOperand(0); 1754 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1755 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1756 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi); 1757} 1758 1759void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1760 SDValue &Hi) { 1761 DebugLoc dl = N->getDebugLoc(); 1762 EVT VT = N->getValueType(0); 1763 SDValue Op = N->getOperand(0); 1764 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1765 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1766 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi); 1767} 1768 1769void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1770 SDValue &Lo, SDValue &Hi) { 1771 if (ISD::isNormalLoad(N)) { 1772 ExpandRes_NormalLoad(N, Lo, Hi); 1773 return; 1774 } 1775 1776 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1777 1778 EVT VT = N->getValueType(0); 1779 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1780 SDValue Ch = N->getChain(); 1781 SDValue Ptr = N->getBasePtr(); 1782 ISD::LoadExtType ExtType = N->getExtensionType(); 1783 unsigned Alignment = N->getAlignment(); 1784 bool isVolatile = N->isVolatile(); 1785 bool isNonTemporal = N->isNonTemporal(); 1786 bool isInvariant = N->isInvariant(); 1787 DebugLoc dl = N->getDebugLoc(); 1788 1789 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1790 1791 if (N->getMemoryVT().bitsLE(NVT)) { 1792 EVT MemVT = N->getMemoryVT(); 1793 1794 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), 1795 MemVT, isVolatile, isNonTemporal, Alignment); 1796 1797 // Remember the chain. 1798 Ch = Lo.getValue(1); 1799 1800 if (ExtType == ISD::SEXTLOAD) { 1801 // The high part is obtained by SRA'ing all but one of the bits of the 1802 // lo part. 1803 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1804 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1805 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1806 } else if (ExtType == ISD::ZEXTLOAD) { 1807 // The high part is just a zero. 1808 Hi = DAG.getConstant(0, NVT); 1809 } else { 1810 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1811 // The high part is undefined. 1812 Hi = DAG.getUNDEF(NVT); 1813 } 1814 } else if (TLI.isLittleEndian()) { 1815 // Little-endian - low bits are at low addresses. 1816 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(), 1817 isVolatile, isNonTemporal, isInvariant, Alignment); 1818 1819 unsigned ExcessBits = 1820 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1821 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits); 1822 1823 // Increment the pointer to the other half. 1824 unsigned IncrementSize = NVT.getSizeInBits()/8; 1825 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1826 DAG.getIntPtrConstant(IncrementSize)); 1827 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, 1828 N->getPointerInfo().getWithOffset(IncrementSize), NEVT, 1829 isVolatile, isNonTemporal, 1830 MinAlign(Alignment, IncrementSize)); 1831 1832 // Build a factor node to remember that this load is independent of the 1833 // other one. 1834 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1835 Hi.getValue(1)); 1836 } else { 1837 // Big-endian - high bits are at low addresses. Favor aligned loads at 1838 // the cost of some bit-fiddling. 1839 EVT MemVT = N->getMemoryVT(); 1840 unsigned EBytes = MemVT.getStoreSize(); 1841 unsigned IncrementSize = NVT.getSizeInBits()/8; 1842 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1843 1844 // Load both the high bits and maybe some of the low bits. 1845 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), 1846 EVT::getIntegerVT(*DAG.getContext(), 1847 MemVT.getSizeInBits() - ExcessBits), 1848 isVolatile, isNonTemporal, Alignment); 1849 1850 // Increment the pointer to the other half. 1851 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1852 DAG.getIntPtrConstant(IncrementSize)); 1853 // Load the rest of the low bits. 1854 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, 1855 N->getPointerInfo().getWithOffset(IncrementSize), 1856 EVT::getIntegerVT(*DAG.getContext(), ExcessBits), 1857 isVolatile, isNonTemporal, 1858 MinAlign(Alignment, IncrementSize)); 1859 1860 // Build a factor node to remember that this load is independent of the 1861 // other one. 1862 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1863 Hi.getValue(1)); 1864 1865 if (ExcessBits < NVT.getSizeInBits()) { 1866 // Transfer low bits from the bottom of Hi to the top of Lo. 1867 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, 1868 DAG.getNode(ISD::SHL, dl, NVT, Hi, 1869 DAG.getConstant(ExcessBits, 1870 TLI.getPointerTy()))); 1871 // Move high bits to the right position in Hi. 1872 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, 1873 NVT, Hi, 1874 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1875 TLI.getPointerTy())); 1876 } 1877 } 1878 1879 // Legalized the chain result - switch anything that used the old chain to 1880 // use the new one. 1881 ReplaceValueWith(SDValue(N, 1), Ch); 1882} 1883 1884void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1885 SDValue &Lo, SDValue &Hi) { 1886 DebugLoc dl = N->getDebugLoc(); 1887 SDValue LL, LH, RL, RH; 1888 GetExpandedInteger(N->getOperand(0), LL, LH); 1889 GetExpandedInteger(N->getOperand(1), RL, RH); 1890 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); 1891 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); 1892} 1893 1894void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1895 SDValue &Lo, SDValue &Hi) { 1896 EVT VT = N->getValueType(0); 1897 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1898 DebugLoc dl = N->getDebugLoc(); 1899 1900 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 1901 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 1902 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 1903 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 1904 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1905 SDValue LL, LH, RL, RH; 1906 GetExpandedInteger(N->getOperand(0), LL, LH); 1907 GetExpandedInteger(N->getOperand(1), RL, RH); 1908 unsigned OuterBitSize = VT.getSizeInBits(); 1909 unsigned InnerBitSize = NVT.getSizeInBits(); 1910 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1911 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1912 1913 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1914 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1915 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1916 // The inputs are both zero-extended. 1917 if (HasUMUL_LOHI) { 1918 // We can emit a umul_lohi. 1919 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1920 Hi = SDValue(Lo.getNode(), 1); 1921 return; 1922 } 1923 if (HasMULHU) { 1924 // We can emit a mulhu+mul. 1925 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1926 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1927 return; 1928 } 1929 } 1930 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1931 // The input values are both sign-extended. 1932 if (HasSMUL_LOHI) { 1933 // We can emit a smul_lohi. 1934 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1935 Hi = SDValue(Lo.getNode(), 1); 1936 return; 1937 } 1938 if (HasMULHS) { 1939 // We can emit a mulhs+mul. 1940 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1941 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); 1942 return; 1943 } 1944 } 1945 if (HasUMUL_LOHI) { 1946 // Lo,Hi = umul LHS, RHS. 1947 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 1948 DAG.getVTList(NVT, NVT), LL, RL); 1949 Lo = UMulLOHI; 1950 Hi = UMulLOHI.getValue(1); 1951 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1952 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1953 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1954 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1955 return; 1956 } 1957 if (HasMULHU) { 1958 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1959 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1960 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1961 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1962 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1963 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1964 return; 1965 } 1966 } 1967 1968 // If nothing else, we can make a libcall. 1969 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1970 if (VT == MVT::i16) 1971 LC = RTLIB::MUL_I16; 1972 else if (VT == MVT::i32) 1973 LC = RTLIB::MUL_I32; 1974 else if (VT == MVT::i64) 1975 LC = RTLIB::MUL_I64; 1976 else if (VT == MVT::i128) 1977 LC = RTLIB::MUL_I128; 1978 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1979 1980 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1981 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi); 1982} 1983 1984void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node, 1985 SDValue &Lo, SDValue &Hi) { 1986 SDValue LHS = Node->getOperand(0); 1987 SDValue RHS = Node->getOperand(1); 1988 DebugLoc dl = Node->getDebugLoc(); 1989 1990 // Expand the result by simply replacing it with the equivalent 1991 // non-overflow-checking operation. 1992 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 1993 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 1994 LHS, RHS); 1995 SplitInteger(Sum, Lo, Hi); 1996 1997 // Compute the overflow. 1998 // 1999 // LHSSign -> LHS >= 0 2000 // RHSSign -> RHS >= 0 2001 // SumSign -> Sum >= 0 2002 // 2003 // Add: 2004 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 2005 // Sub: 2006 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 2007 // 2008 EVT OType = Node->getValueType(1); 2009 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 2010 2011 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 2012 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 2013 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 2014 Node->getOpcode() == ISD::SADDO ? 2015 ISD::SETEQ : ISD::SETNE); 2016 2017 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 2018 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 2019 2020 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 2021 2022 // Use the calculated overflow everywhere. 2023 ReplaceValueWith(SDValue(Node, 1), Cmp); 2024} 2025 2026void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 2027 SDValue &Lo, SDValue &Hi) { 2028 EVT VT = N->getValueType(0); 2029 DebugLoc dl = N->getDebugLoc(); 2030 2031 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2032 if (VT == MVT::i16) 2033 LC = RTLIB::SDIV_I16; 2034 else if (VT == MVT::i32) 2035 LC = RTLIB::SDIV_I32; 2036 else if (VT == MVT::i64) 2037 LC = RTLIB::SDIV_I64; 2038 else if (VT == MVT::i128) 2039 LC = RTLIB::SDIV_I128; 2040 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 2041 2042 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2043 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 2044} 2045 2046void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 2047 SDValue &Lo, SDValue &Hi) { 2048 EVT VT = N->getValueType(0); 2049 DebugLoc dl = N->getDebugLoc(); 2050 2051 // If we can emit an efficient shift operation, do so now. Check to see if 2052 // the RHS is a constant. 2053 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2054 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 2055 2056 // If we can determine that the high bit of the shift is zero or one, even if 2057 // the low bits are variable, emit this shift in an optimized form. 2058 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 2059 return; 2060 2061 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 2062 unsigned PartsOpc; 2063 if (N->getOpcode() == ISD::SHL) { 2064 PartsOpc = ISD::SHL_PARTS; 2065 } else if (N->getOpcode() == ISD::SRL) { 2066 PartsOpc = ISD::SRL_PARTS; 2067 } else { 2068 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 2069 PartsOpc = ISD::SRA_PARTS; 2070 } 2071 2072 // Next check to see if the target supports this SHL_PARTS operation or if it 2073 // will custom expand it. 2074 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2075 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 2076 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 2077 Action == TargetLowering::Custom) { 2078 // Expand the subcomponents. 2079 SDValue LHSL, LHSH; 2080 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 2081 2082 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 2083 EVT VT = LHSL.getValueType(); 2084 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3); 2085 Hi = Lo.getValue(1); 2086 return; 2087 } 2088 2089 // Otherwise, emit a libcall. 2090 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2091 bool isSigned; 2092 if (N->getOpcode() == ISD::SHL) { 2093 isSigned = false; /*sign irrelevant*/ 2094 if (VT == MVT::i16) 2095 LC = RTLIB::SHL_I16; 2096 else if (VT == MVT::i32) 2097 LC = RTLIB::SHL_I32; 2098 else if (VT == MVT::i64) 2099 LC = RTLIB::SHL_I64; 2100 else if (VT == MVT::i128) 2101 LC = RTLIB::SHL_I128; 2102 } else if (N->getOpcode() == ISD::SRL) { 2103 isSigned = false; 2104 if (VT == MVT::i16) 2105 LC = RTLIB::SRL_I16; 2106 else if (VT == MVT::i32) 2107 LC = RTLIB::SRL_I32; 2108 else if (VT == MVT::i64) 2109 LC = RTLIB::SRL_I64; 2110 else if (VT == MVT::i128) 2111 LC = RTLIB::SRL_I128; 2112 } else { 2113 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 2114 isSigned = true; 2115 if (VT == MVT::i16) 2116 LC = RTLIB::SRA_I16; 2117 else if (VT == MVT::i32) 2118 LC = RTLIB::SRA_I32; 2119 else if (VT == MVT::i64) 2120 LC = RTLIB::SRA_I64; 2121 else if (VT == MVT::i128) 2122 LC = RTLIB::SRA_I128; 2123 } 2124 2125 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) { 2126 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2127 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi); 2128 return; 2129 } 2130 2131 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi)) 2132 llvm_unreachable("Unsupported shift!"); 2133} 2134 2135void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 2136 SDValue &Lo, SDValue &Hi) { 2137 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2138 DebugLoc dl = N->getDebugLoc(); 2139 SDValue Op = N->getOperand(0); 2140 if (Op.getValueType().bitsLE(NVT)) { 2141 // The low part is sign extension of the input (degenerates to a copy). 2142 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); 2143 // The high part is obtained by SRA'ing all but one of the bits of low part. 2144 unsigned LoSize = NVT.getSizeInBits(); 2145 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 2146 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 2147 } else { 2148 // For example, extension of an i48 to an i64. The operand type necessarily 2149 // promotes to the result type, so will end up being expanded too. 2150 assert(getTypeAction(Op.getValueType()) == 2151 TargetLowering::TypePromoteInteger && 2152 "Only know how to promote this result!"); 2153 SDValue Res = GetPromotedInteger(Op); 2154 assert(Res.getValueType() == N->getValueType(0) && 2155 "Operand over promoted?"); 2156 // Split the promoted operand. This will simplify when it is expanded. 2157 SplitInteger(Res, Lo, Hi); 2158 unsigned ExcessBits = 2159 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 2160 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 2161 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 2162 ExcessBits))); 2163 } 2164} 2165 2166void DAGTypeLegalizer:: 2167ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 2168 DebugLoc dl = N->getDebugLoc(); 2169 GetExpandedInteger(N->getOperand(0), Lo, Hi); 2170 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2171 2172 if (EVT.bitsLE(Lo.getValueType())) { 2173 // sext_inreg the low part if needed. 2174 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, 2175 N->getOperand(1)); 2176 2177 // The high part gets the sign extension from the lo-part. This handles 2178 // things like sextinreg V:i64 from i8. 2179 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, 2180 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 2181 TLI.getPointerTy())); 2182 } else { 2183 // For example, extension of an i48 to an i64. Leave the low part alone, 2184 // sext_inreg the high part. 2185 unsigned ExcessBits = 2186 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 2187 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 2188 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 2189 ExcessBits))); 2190 } 2191} 2192 2193void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 2194 SDValue &Lo, SDValue &Hi) { 2195 EVT VT = N->getValueType(0); 2196 DebugLoc dl = N->getDebugLoc(); 2197 2198 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2199 if (VT == MVT::i16) 2200 LC = RTLIB::SREM_I16; 2201 else if (VT == MVT::i32) 2202 LC = RTLIB::SREM_I32; 2203 else if (VT == MVT::i64) 2204 LC = RTLIB::SREM_I64; 2205 else if (VT == MVT::i128) 2206 LC = RTLIB::SREM_I128; 2207 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 2208 2209 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2210 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 2211} 2212 2213void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 2214 SDValue &Lo, SDValue &Hi) { 2215 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2216 DebugLoc dl = N->getDebugLoc(); 2217 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); 2218 Hi = DAG.getNode(ISD::SRL, dl, 2219 N->getOperand(0).getValueType(), N->getOperand(0), 2220 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy())); 2221 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); 2222} 2223 2224void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N, 2225 SDValue &Lo, SDValue &Hi) { 2226 SDValue LHS = N->getOperand(0); 2227 SDValue RHS = N->getOperand(1); 2228 DebugLoc dl = N->getDebugLoc(); 2229 2230 // Expand the result by simply replacing it with the equivalent 2231 // non-overflow-checking operation. 2232 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ? 2233 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2234 LHS, RHS); 2235 SplitInteger(Sum, Lo, Hi); 2236 2237 // Calculate the overflow: addition overflows iff a + b < a, and subtraction 2238 // overflows iff a - b > a. 2239 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, 2240 N->getOpcode () == ISD::UADDO ? 2241 ISD::SETULT : ISD::SETUGT); 2242 2243 // Use the calculated overflow everywhere. 2244 ReplaceValueWith(SDValue(N, 1), Ofl); 2245} 2246 2247void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N, 2248 SDValue &Lo, SDValue &Hi) { 2249 EVT VT = N->getValueType(0); 2250 Type *RetTy = VT.getTypeForEVT(*DAG.getContext()); 2251 EVT PtrVT = TLI.getPointerTy(); 2252 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext()); 2253 DebugLoc dl = N->getDebugLoc(); 2254 2255 // A divide for UMULO should be faster than a function call. 2256 if (N->getOpcode() == ISD::UMULO) { 2257 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1); 2258 DebugLoc DL = N->getDebugLoc(); 2259 2260 SDValue MUL = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS); 2261 SplitInteger(MUL, Lo, Hi); 2262 2263 // A divide for UMULO will be faster than a function call. Select to 2264 // make sure we aren't using 0. 2265 SDValue isZero = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2266 RHS, DAG.getConstant(0, VT), ISD::SETNE); 2267 SDValue NotZero = DAG.getNode(ISD::SELECT, dl, VT, isZero, 2268 DAG.getConstant(1, VT), RHS); 2269 SDValue DIV = DAG.getNode(ISD::UDIV, DL, LHS.getValueType(), MUL, NotZero); 2270 SDValue Overflow; 2271 Overflow = DAG.getSetCC(DL, N->getValueType(1), DIV, LHS, ISD::SETNE); 2272 ReplaceValueWith(SDValue(N, 1), Overflow); 2273 return; 2274 } 2275 2276 // Replace this with a libcall that will check overflow. 2277 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2278 if (VT == MVT::i32) 2279 LC = RTLIB::MULO_I32; 2280 else if (VT == MVT::i64) 2281 LC = RTLIB::MULO_I64; 2282 else if (VT == MVT::i128) 2283 LC = RTLIB::MULO_I128; 2284 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!"); 2285 2286 SDValue Temp = DAG.CreateStackTemporary(PtrVT); 2287 // Temporary for the overflow value, default it to zero. 2288 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, 2289 DAG.getConstant(0, PtrVT), Temp, 2290 MachinePointerInfo(), false, false, 0); 2291 2292 TargetLowering::ArgListTy Args; 2293 TargetLowering::ArgListEntry Entry; 2294 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 2295 EVT ArgVT = N->getOperand(i).getValueType(); 2296 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 2297 Entry.Node = N->getOperand(i); 2298 Entry.Ty = ArgTy; 2299 Entry.isSExt = true; 2300 Entry.isZExt = false; 2301 Args.push_back(Entry); 2302 } 2303 2304 // Also pass the address of the overflow check. 2305 Entry.Node = Temp; 2306 Entry.Ty = PtrTy->getPointerTo(); 2307 Entry.isSExt = true; 2308 Entry.isZExt = false; 2309 Args.push_back(Entry); 2310 2311 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT); 2312 std::pair<SDValue, SDValue> CallInfo = 2313 TLI.LowerCallTo(Chain, RetTy, true, false, false, false, 2314 0, TLI.getLibcallCallingConv(LC), false, 2315 true, Func, Args, DAG, dl); 2316 2317 SplitInteger(CallInfo.first, Lo, Hi); 2318 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp, 2319 MachinePointerInfo(), false, false, false, 0); 2320 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2, 2321 DAG.getConstant(0, PtrVT), 2322 ISD::SETNE); 2323 // Use the overflow from the libcall everywhere. 2324 ReplaceValueWith(SDValue(N, 1), Ofl); 2325} 2326 2327void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 2328 SDValue &Lo, SDValue &Hi) { 2329 EVT VT = N->getValueType(0); 2330 DebugLoc dl = N->getDebugLoc(); 2331 2332 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2333 if (VT == MVT::i16) 2334 LC = RTLIB::UDIV_I16; 2335 else if (VT == MVT::i32) 2336 LC = RTLIB::UDIV_I32; 2337 else if (VT == MVT::i64) 2338 LC = RTLIB::UDIV_I64; 2339 else if (VT == MVT::i128) 2340 LC = RTLIB::UDIV_I128; 2341 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 2342 2343 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2344 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 2345} 2346 2347void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 2348 SDValue &Lo, SDValue &Hi) { 2349 EVT VT = N->getValueType(0); 2350 DebugLoc dl = N->getDebugLoc(); 2351 2352 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2353 if (VT == MVT::i16) 2354 LC = RTLIB::UREM_I16; 2355 else if (VT == MVT::i32) 2356 LC = RTLIB::UREM_I32; 2357 else if (VT == MVT::i64) 2358 LC = RTLIB::UREM_I64; 2359 else if (VT == MVT::i128) 2360 LC = RTLIB::UREM_I128; 2361 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 2362 2363 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2364 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 2365} 2366 2367void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 2368 SDValue &Lo, SDValue &Hi) { 2369 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2370 DebugLoc dl = N->getDebugLoc(); 2371 SDValue Op = N->getOperand(0); 2372 if (Op.getValueType().bitsLE(NVT)) { 2373 // The low part is zero extension of the input (degenerates to a copy). 2374 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); 2375 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 2376 } else { 2377 // For example, extension of an i48 to an i64. The operand type necessarily 2378 // promotes to the result type, so will end up being expanded too. 2379 assert(getTypeAction(Op.getValueType()) == 2380 TargetLowering::TypePromoteInteger && 2381 "Only know how to promote this result!"); 2382 SDValue Res = GetPromotedInteger(Op); 2383 assert(Res.getValueType() == N->getValueType(0) && 2384 "Operand over promoted?"); 2385 // Split the promoted operand. This will simplify when it is expanded. 2386 SplitInteger(Res, Lo, Hi); 2387 unsigned ExcessBits = 2388 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 2389 Hi = DAG.getZeroExtendInReg(Hi, dl, 2390 EVT::getIntegerVT(*DAG.getContext(), 2391 ExcessBits)); 2392 } 2393} 2394 2395void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N, 2396 SDValue &Lo, SDValue &Hi) { 2397 DebugLoc dl = N->getDebugLoc(); 2398 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT(); 2399 SDValue Zero = DAG.getConstant(0, VT); 2400 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 2401 N->getOperand(0), 2402 N->getOperand(1), Zero, Zero, 2403 cast<AtomicSDNode>(N)->getMemOperand(), 2404 cast<AtomicSDNode>(N)->getOrdering(), 2405 cast<AtomicSDNode>(N)->getSynchScope()); 2406 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0)); 2407 ReplaceValueWith(SDValue(N, 1), Swap.getValue(1)); 2408} 2409 2410//===----------------------------------------------------------------------===// 2411// Integer Operand Expansion 2412//===----------------------------------------------------------------------===// 2413 2414/// ExpandIntegerOperand - This method is called when the specified operand of 2415/// the specified node is found to need expansion. At this point, all of the 2416/// result types of the node are known to be legal, but other operands of the 2417/// node may need promotion or expansion as well as the specified one. 2418bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 2419 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n"); 2420 SDValue Res = SDValue(); 2421 2422 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 2423 return false; 2424 2425 switch (N->getOpcode()) { 2426 default: 2427 #ifndef NDEBUG 2428 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": "; 2429 N->dump(&DAG); dbgs() << "\n"; 2430 #endif 2431 llvm_unreachable("Do not know how to expand this operator's operand!"); 2432 2433 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break; 2434 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 2435 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 2436 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 2437 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 2438 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; 2439 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 2440 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 2441 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 2442 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break; 2443 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 2444 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 2445 2446 case ISD::SHL: 2447 case ISD::SRA: 2448 case ISD::SRL: 2449 case ISD::ROTL: 2450 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break; 2451 case ISD::RETURNADDR: 2452 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break; 2453 2454 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break; 2455 } 2456 2457 // If the result is null, the sub-method took care of registering results etc. 2458 if (!Res.getNode()) return false; 2459 2460 // If the result is N, the sub-method updated N in place. Tell the legalizer 2461 // core about this. 2462 if (Res.getNode() == N) 2463 return true; 2464 2465 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2466 "Invalid operand expansion"); 2467 2468 ReplaceValueWith(SDValue(N, 0), Res); 2469 return false; 2470} 2471 2472/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 2473/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 2474void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 2475 SDValue &NewRHS, 2476 ISD::CondCode &CCCode, 2477 DebugLoc dl) { 2478 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 2479 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 2480 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 2481 2482 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 2483 if (RHSLo == RHSHi) { 2484 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 2485 if (RHSCST->isAllOnesValue()) { 2486 // Equality comparison to -1. 2487 NewLHS = DAG.getNode(ISD::AND, dl, 2488 LHSLo.getValueType(), LHSLo, LHSHi); 2489 NewRHS = RHSLo; 2490 return; 2491 } 2492 } 2493 } 2494 2495 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 2496 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 2497 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS); 2498 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2499 return; 2500 } 2501 2502 // If this is a comparison of the sign bit, just look at the top part. 2503 // X > -1, x < 0 2504 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 2505 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 2506 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 2507 NewLHS = LHSHi; 2508 NewRHS = RHSHi; 2509 return; 2510 } 2511 2512 // FIXME: This generated code sucks. 2513 ISD::CondCode LowCC; 2514 switch (CCCode) { 2515 default: llvm_unreachable("Unknown integer setcc!"); 2516 case ISD::SETLT: 2517 case ISD::SETULT: LowCC = ISD::SETULT; break; 2518 case ISD::SETGT: 2519 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2520 case ISD::SETLE: 2521 case ISD::SETULE: LowCC = ISD::SETULE; break; 2522 case ISD::SETGE: 2523 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2524 } 2525 2526 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2527 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2528 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2529 2530 // NOTE: on targets without efficient SELECT of bools, we can always use 2531 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2532 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL); 2533 SDValue Tmp1, Tmp2; 2534 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), 2535 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl); 2536 if (!Tmp1.getNode()) 2537 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 2538 LHSLo, RHSLo, LowCC); 2539 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2540 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl); 2541 if (!Tmp2.getNode()) 2542 Tmp2 = DAG.getNode(ISD::SETCC, dl, 2543 TLI.getSetCCResultType(LHSHi.getValueType()), 2544 LHSHi, RHSHi, DAG.getCondCode(CCCode)); 2545 2546 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2547 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2548 if ((Tmp1C && Tmp1C->isNullValue()) || 2549 (Tmp2C && Tmp2C->isNullValue() && 2550 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2551 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2552 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2553 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2554 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2555 // low part is known false, returns high part. 2556 // For LE / GE, if high part is known false, ignore the low part. 2557 // For LT / GT, if high part is known true, ignore the low part. 2558 NewLHS = Tmp2; 2559 NewRHS = SDValue(); 2560 return; 2561 } 2562 2563 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2564 LHSHi, RHSHi, ISD::SETEQ, false, 2565 DagCombineInfo, dl); 2566 if (!NewLHS.getNode()) 2567 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 2568 LHSHi, RHSHi, ISD::SETEQ); 2569 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), 2570 NewLHS, Tmp1, Tmp2); 2571 NewRHS = SDValue(); 2572} 2573 2574SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2575 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2576 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2577 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2578 2579 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2580 // against zero to select between true and false values. 2581 if (NewRHS.getNode() == 0) { 2582 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2583 CCCode = ISD::SETNE; 2584 } 2585 2586 // Update N to have the operands specified. 2587 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 2588 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2589 N->getOperand(4)), 0); 2590} 2591 2592SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2593 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2594 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2595 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2596 2597 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2598 // against zero to select between true and false values. 2599 if (NewRHS.getNode() == 0) { 2600 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2601 CCCode = ISD::SETNE; 2602 } 2603 2604 // Update N to have the operands specified. 2605 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, 2606 N->getOperand(2), N->getOperand(3), 2607 DAG.getCondCode(CCCode)), 0); 2608} 2609 2610SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2611 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2612 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2613 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2614 2615 // If ExpandSetCCOperands returned a scalar, use it. 2616 if (NewRHS.getNode() == 0) { 2617 assert(NewLHS.getValueType() == N->getValueType(0) && 2618 "Unexpected setcc expansion!"); 2619 return NewLHS; 2620 } 2621 2622 // Otherwise, update N to have the operands specified. 2623 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, 2624 DAG.getCondCode(CCCode)), 0); 2625} 2626 2627SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) { 2628 // The value being shifted is legal, but the shift amount is too big. 2629 // It follows that either the result of the shift is undefined, or the 2630 // upper half of the shift amount is zero. Just use the lower half. 2631 SDValue Lo, Hi; 2632 GetExpandedInteger(N->getOperand(1), Lo, Hi); 2633 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0); 2634} 2635 2636SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) { 2637 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This 2638 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this 2639 // constant to valid type. 2640 SDValue Lo, Hi; 2641 GetExpandedInteger(N->getOperand(0), Lo, Hi); 2642 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0); 2643} 2644 2645SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2646 SDValue Op = N->getOperand(0); 2647 EVT DstVT = N->getValueType(0); 2648 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2649 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2650 "Don't know how to expand this SINT_TO_FP!"); 2651 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc()); 2652} 2653 2654SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2655 if (ISD::isNormalStore(N)) 2656 return ExpandOp_NormalStore(N, OpNo); 2657 2658 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2659 assert(OpNo == 1 && "Can only expand the stored value so far"); 2660 2661 EVT VT = N->getOperand(1).getValueType(); 2662 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2663 SDValue Ch = N->getChain(); 2664 SDValue Ptr = N->getBasePtr(); 2665 unsigned Alignment = N->getAlignment(); 2666 bool isVolatile = N->isVolatile(); 2667 bool isNonTemporal = N->isNonTemporal(); 2668 DebugLoc dl = N->getDebugLoc(); 2669 SDValue Lo, Hi; 2670 2671 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2672 2673 if (N->getMemoryVT().bitsLE(NVT)) { 2674 GetExpandedInteger(N->getValue(), Lo, Hi); 2675 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), 2676 N->getMemoryVT(), isVolatile, isNonTemporal, 2677 Alignment); 2678 } 2679 2680 if (TLI.isLittleEndian()) { 2681 // Little-endian - low bits are at low addresses. 2682 GetExpandedInteger(N->getValue(), Lo, Hi); 2683 2684 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), 2685 isVolatile, isNonTemporal, Alignment); 2686 2687 unsigned ExcessBits = 2688 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2689 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits); 2690 2691 // Increment the pointer to the other half. 2692 unsigned IncrementSize = NVT.getSizeInBits()/8; 2693 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2694 DAG.getIntPtrConstant(IncrementSize)); 2695 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, 2696 N->getPointerInfo().getWithOffset(IncrementSize), 2697 NEVT, isVolatile, isNonTemporal, 2698 MinAlign(Alignment, IncrementSize)); 2699 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2700 } 2701 2702 // Big-endian - high bits are at low addresses. Favor aligned stores at 2703 // the cost of some bit-fiddling. 2704 GetExpandedInteger(N->getValue(), Lo, Hi); 2705 2706 EVT ExtVT = N->getMemoryVT(); 2707 unsigned EBytes = ExtVT.getStoreSize(); 2708 unsigned IncrementSize = NVT.getSizeInBits()/8; 2709 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2710 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(), 2711 ExtVT.getSizeInBits() - ExcessBits); 2712 2713 if (ExcessBits < NVT.getSizeInBits()) { 2714 // Transfer high bits from the top of Lo to the bottom of Hi. 2715 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, 2716 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2717 TLI.getPointerTy())); 2718 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, 2719 DAG.getNode(ISD::SRL, dl, NVT, Lo, 2720 DAG.getConstant(ExcessBits, 2721 TLI.getPointerTy()))); 2722 } 2723 2724 // Store both the high bits and maybe some of the low bits. 2725 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(), 2726 HiVT, isVolatile, isNonTemporal, Alignment); 2727 2728 // Increment the pointer to the other half. 2729 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2730 DAG.getIntPtrConstant(IncrementSize)); 2731 // Store the lowest ExcessBits bits in the second half. 2732 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, 2733 N->getPointerInfo().getWithOffset(IncrementSize), 2734 EVT::getIntegerVT(*DAG.getContext(), ExcessBits), 2735 isVolatile, isNonTemporal, 2736 MinAlign(Alignment, IncrementSize)); 2737 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2738} 2739 2740SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2741 SDValue InL, InH; 2742 GetExpandedInteger(N->getOperand(0), InL, InH); 2743 // Just truncate the low part of the source. 2744 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL); 2745} 2746 2747static const fltSemantics *EVTToAPFloatSemantics(EVT VT) { 2748 switch (VT.getSimpleVT().SimpleTy) { 2749 default: llvm_unreachable("Unknown FP format"); 2750 case MVT::f32: return &APFloat::IEEEsingle; 2751 case MVT::f64: return &APFloat::IEEEdouble; 2752 case MVT::f80: return &APFloat::x87DoubleExtended; 2753 case MVT::f128: return &APFloat::IEEEquad; 2754 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 2755 } 2756} 2757 2758SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2759 SDValue Op = N->getOperand(0); 2760 EVT SrcVT = Op.getValueType(); 2761 EVT DstVT = N->getValueType(0); 2762 DebugLoc dl = N->getDebugLoc(); 2763 2764 // The following optimization is valid only if every value in SrcVT (when 2765 // treated as signed) is representable in DstVT. Check that the mantissa 2766 // size of DstVT is >= than the number of bits in SrcVT -1. 2767 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT); 2768 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 && 2769 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2770 // Do a signed conversion then adjust the result. 2771 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); 2772 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2773 2774 // The result of the signed conversion needs adjusting if the 'sign bit' of 2775 // the incoming integer was set. To handle this, we dynamically test to see 2776 // if it is set, and, if so, add a fudge factor. 2777 2778 const uint64_t F32TwoE32 = 0x4F800000ULL; 2779 const uint64_t F32TwoE64 = 0x5F800000ULL; 2780 const uint64_t F32TwoE128 = 0x7F800000ULL; 2781 2782 APInt FF(32, 0); 2783 if (SrcVT == MVT::i32) 2784 FF = APInt(32, F32TwoE32); 2785 else if (SrcVT == MVT::i64) 2786 FF = APInt(32, F32TwoE64); 2787 else if (SrcVT == MVT::i128) 2788 FF = APInt(32, F32TwoE128); 2789 else 2790 assert(false && "Unsupported UINT_TO_FP!"); 2791 2792 // Check whether the sign bit is set. 2793 SDValue Lo, Hi; 2794 GetExpandedInteger(Op, Lo, Hi); 2795 SDValue SignSet = DAG.getSetCC(dl, 2796 TLI.getSetCCResultType(Hi.getValueType()), 2797 Hi, DAG.getConstant(0, Hi.getValueType()), 2798 ISD::SETLT); 2799 2800 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2801 SDValue FudgePtr = DAG.getConstantPool( 2802 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 2803 TLI.getPointerTy()); 2804 2805 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2806 SDValue Zero = DAG.getIntPtrConstant(0); 2807 SDValue Four = DAG.getIntPtrConstant(4); 2808 if (TLI.isBigEndian()) std::swap(Zero, Four); 2809 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 2810 Zero, Four); 2811 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2812 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset); 2813 Alignment = std::min(Alignment, 4u); 2814 2815 // Load the value out, extending it from f32 to the destination float type. 2816 // FIXME: Avoid the extend by constructing the right constant pool? 2817 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), 2818 FudgePtr, 2819 MachinePointerInfo::getConstantPool(), 2820 MVT::f32, 2821 false, false, Alignment); 2822 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); 2823 } 2824 2825 // Otherwise, use a libcall. 2826 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2827 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2828 "Don't know how to expand this UINT_TO_FP!"); 2829 return MakeLibCall(LC, DstVT, &Op, 1, true, dl); 2830} 2831 2832SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) { 2833 DebugLoc dl = N->getDebugLoc(); 2834 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 2835 cast<AtomicSDNode>(N)->getMemoryVT(), 2836 N->getOperand(0), 2837 N->getOperand(1), N->getOperand(2), 2838 cast<AtomicSDNode>(N)->getMemOperand(), 2839 cast<AtomicSDNode>(N)->getOrdering(), 2840 cast<AtomicSDNode>(N)->getSynchScope()); 2841 return Swap.getValue(1); 2842} 2843 2844 2845SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) { 2846 SDValue InOp0 = N->getOperand(0); 2847 EVT InVT = InOp0.getValueType(); 2848 2849 EVT OutVT = N->getValueType(0); 2850 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2851 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2852 unsigned OutNumElems = OutVT.getVectorNumElements(); 2853 EVT NOutVTElem = NOutVT.getVectorElementType(); 2854 2855 DebugLoc dl = N->getDebugLoc(); 2856 SDValue BaseIdx = N->getOperand(1); 2857 2858 SmallVector<SDValue, 8> Ops; 2859 Ops.reserve(OutNumElems); 2860 for (unsigned i = 0; i != OutNumElems; ++i) { 2861 2862 // Extract the element from the original vector. 2863 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(), 2864 BaseIdx, DAG.getIntPtrConstant(i)); 2865 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 2866 InVT.getVectorElementType(), N->getOperand(0), Index); 2867 2868 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext); 2869 // Insert the converted element to the new vector. 2870 Ops.push_back(Op); 2871 } 2872 2873 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size()); 2874} 2875 2876 2877SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) { 2878 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 2879 EVT VT = N->getValueType(0); 2880 DebugLoc dl = N->getDebugLoc(); 2881 2882 unsigned NumElts = VT.getVectorNumElements(); 2883 SmallVector<int, 8> NewMask; 2884 for (unsigned i = 0; i != NumElts; ++i) { 2885 NewMask.push_back(SV->getMaskElt(i)); 2886 } 2887 2888 SDValue V0 = GetPromotedInteger(N->getOperand(0)); 2889 SDValue V1 = GetPromotedInteger(N->getOperand(1)); 2890 EVT OutVT = V0.getValueType(); 2891 2892 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]); 2893} 2894 2895 2896SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) { 2897 EVT OutVT = N->getValueType(0); 2898 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2899 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2900 unsigned NumElems = N->getNumOperands(); 2901 EVT NOutVTElem = NOutVT.getVectorElementType(); 2902 2903 DebugLoc dl = N->getDebugLoc(); 2904 2905 SmallVector<SDValue, 8> Ops; 2906 Ops.reserve(NumElems); 2907 for (unsigned i = 0; i != NumElems; ++i) { 2908 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i)); 2909 Ops.push_back(Op); 2910 } 2911 2912 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size()); 2913} 2914 2915SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) { 2916 2917 DebugLoc dl = N->getDebugLoc(); 2918 2919 assert(!N->getOperand(0).getValueType().isVector() && 2920 "Input must be a scalar"); 2921 2922 EVT OutVT = N->getValueType(0); 2923 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2924 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2925 EVT NOutVTElem = NOutVT.getVectorElementType(); 2926 2927 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0)); 2928 2929 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op); 2930} 2931 2932SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) { 2933 DebugLoc dl = N->getDebugLoc(); 2934 2935 EVT OutVT = N->getValueType(0); 2936 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2937 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2938 2939 EVT InElemTy = OutVT.getVectorElementType(); 2940 EVT OutElemTy = NOutVT.getVectorElementType(); 2941 2942 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements(); 2943 unsigned NumOutElem = NOutVT.getVectorNumElements(); 2944 unsigned NumOperands = N->getNumOperands(); 2945 assert(NumElem * NumOperands == NumOutElem && 2946 "Unexpected number of elements"); 2947 2948 // Take the elements from the first vector. 2949 SmallVector<SDValue, 8> Ops(NumOutElem); 2950 for (unsigned i = 0; i < NumOperands; ++i) { 2951 SDValue Op = N->getOperand(i); 2952 for (unsigned j = 0; j < NumElem; ++j) { 2953 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 2954 InElemTy, Op, DAG.getIntPtrConstant(j)); 2955 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext); 2956 } 2957 } 2958 2959 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size()); 2960} 2961 2962SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) { 2963 EVT OutVT = N->getValueType(0); 2964 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2965 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2966 2967 EVT NOutVTElem = NOutVT.getVectorElementType(); 2968 2969 DebugLoc dl = N->getDebugLoc(); 2970 SDValue V0 = GetPromotedInteger(N->getOperand(0)); 2971 2972 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl, 2973 NOutVTElem, N->getOperand(1)); 2974 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT, 2975 V0, ConvElem, N->getOperand(2)); 2976} 2977 2978SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) { 2979 DebugLoc dl = N->getDebugLoc(); 2980 SDValue V0 = GetPromotedInteger(N->getOperand(0)); 2981 SDValue V1 = N->getOperand(1); 2982 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 2983 V0->getValueType(0).getScalarType(), V0, V1); 2984 2985 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming 2986 // element types. If this is the case then we need to expand the outgoing 2987 // value and not truncate it. 2988 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0)); 2989} 2990 2991SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) { 2992 DebugLoc dl = N->getDebugLoc(); 2993 unsigned NumElems = N->getNumOperands(); 2994 2995 EVT RetSclrTy = N->getValueType(0).getVectorElementType(); 2996 2997 SmallVector<SDValue, 8> NewOps; 2998 NewOps.reserve(NumElems); 2999 3000 // For each incoming vector 3001 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) { 3002 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx)); 3003 EVT SclrTy = Incoming->getValueType(0).getVectorElementType(); 3004 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements(); 3005 3006 for (unsigned i=0; i<NumElem; ++i) { 3007 // Extract element from incoming vector 3008 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, 3009 Incoming, DAG.getIntPtrConstant(i)); 3010 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex); 3011 NewOps.push_back(Tr); 3012 } 3013 } 3014 3015 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), 3016 &NewOps[0], NewOps.size()); 3017 } 3018