LegalizeIntegerTypes.cpp revision 6959b2bb6521baca57e5507ca039e51002d4a971
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22using namespace llvm; 23 24//===----------------------------------------------------------------------===// 25// Integer Result Promotion 26//===----------------------------------------------------------------------===// 27 28/// PromoteIntegerResult - This method is called when a result of a node is 29/// found to be in need of promotion to a larger type. At this point, the node 30/// may also have invalid operands or may have other results that need 31/// expansion, we just know that (at least) one result needs promotion. 32void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); 34 SDValue Result = SDValue(); 35 36 // See if the target wants to custom expand this node. 37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 38 TargetLowering::Custom) { 39 // If the target wants to, allow it to lower this itself. 40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 41 // Everything that once used N now uses P. We are guaranteed that the 42 // result value types of N and the result value types of P match. 43 ReplaceNodeWith(N, P); 44 return; 45 } 46 } 47 48 switch (N->getOpcode()) { 49 default: 50#ifndef NDEBUG 51 cerr << "PromoteIntegerResult #" << ResNo << ": "; 52 N->dump(&DAG); cerr << "\n"; 53#endif 54 assert(0 && "Do not know how to promote this operator!"); 55 abort(); 56 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break; 57 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break; 58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break; 59 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break; 60 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break; 61 case ISD::Constant: Result = PromoteIntRes_Constant(N); break; 62 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break; 63 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break; 64 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break; 65 case ISD::EXTRACT_VECTOR_ELT: 66 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 67 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 68 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break; 69 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break; 70 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break; 71 case ISD::SHL: Result = PromoteIntRes_SHL(N); break; 72 case ISD::SIGN_EXTEND_INREG: 73 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 74 case ISD::SRA: Result = PromoteIntRes_SRA(N); break; 75 case ISD::SRL: Result = PromoteIntRes_SRL(N); break; 76 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break; 77 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break; 78 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break; 79 80 case ISD::SIGN_EXTEND: 81 case ISD::ZERO_EXTEND: 82 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break; 83 84 case ISD::FP_TO_SINT: 85 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break; 86 87 case ISD::AND: 88 case ISD::OR: 89 case ISD::XOR: 90 case ISD::ADD: 91 case ISD::SUB: 92 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break; 93 94 case ISD::SDIV: 95 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break; 96 97 case ISD::UDIV: 98 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break; 99 100 case ISD::ATOMIC_LOAD_ADD_8: 101 case ISD::ATOMIC_LOAD_SUB_8: 102 case ISD::ATOMIC_LOAD_AND_8: 103 case ISD::ATOMIC_LOAD_OR_8: 104 case ISD::ATOMIC_LOAD_XOR_8: 105 case ISD::ATOMIC_LOAD_NAND_8: 106 case ISD::ATOMIC_LOAD_MIN_8: 107 case ISD::ATOMIC_LOAD_MAX_8: 108 case ISD::ATOMIC_LOAD_UMIN_8: 109 case ISD::ATOMIC_LOAD_UMAX_8: 110 case ISD::ATOMIC_SWAP_8: 111 case ISD::ATOMIC_LOAD_ADD_16: 112 case ISD::ATOMIC_LOAD_SUB_16: 113 case ISD::ATOMIC_LOAD_AND_16: 114 case ISD::ATOMIC_LOAD_OR_16: 115 case ISD::ATOMIC_LOAD_XOR_16: 116 case ISD::ATOMIC_LOAD_NAND_16: 117 case ISD::ATOMIC_LOAD_MIN_16: 118 case ISD::ATOMIC_LOAD_MAX_16: 119 case ISD::ATOMIC_LOAD_UMIN_16: 120 case ISD::ATOMIC_LOAD_UMAX_16: 121 case ISD::ATOMIC_SWAP_16: 122 case ISD::ATOMIC_LOAD_ADD_32: 123 case ISD::ATOMIC_LOAD_SUB_32: 124 case ISD::ATOMIC_LOAD_AND_32: 125 case ISD::ATOMIC_LOAD_OR_32: 126 case ISD::ATOMIC_LOAD_XOR_32: 127 case ISD::ATOMIC_LOAD_NAND_32: 128 case ISD::ATOMIC_LOAD_MIN_32: 129 case ISD::ATOMIC_LOAD_MAX_32: 130 case ISD::ATOMIC_LOAD_UMIN_32: 131 case ISD::ATOMIC_LOAD_UMAX_32: 132 case ISD::ATOMIC_SWAP_32: 133 case ISD::ATOMIC_LOAD_ADD_64: 134 case ISD::ATOMIC_LOAD_SUB_64: 135 case ISD::ATOMIC_LOAD_AND_64: 136 case ISD::ATOMIC_LOAD_OR_64: 137 case ISD::ATOMIC_LOAD_XOR_64: 138 case ISD::ATOMIC_LOAD_NAND_64: 139 case ISD::ATOMIC_LOAD_MIN_64: 140 case ISD::ATOMIC_LOAD_MAX_64: 141 case ISD::ATOMIC_LOAD_UMIN_64: 142 case ISD::ATOMIC_LOAD_UMAX_64: 143 case ISD::ATOMIC_SWAP_64: 144 Result = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 145 146 case ISD::ATOMIC_CMP_SWAP_8: 147 case ISD::ATOMIC_CMP_SWAP_16: 148 case ISD::ATOMIC_CMP_SWAP_32: 149 case ISD::ATOMIC_CMP_SWAP_64: 150 Result = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 151 } 152 153 // If Result is null, the sub-method took care of registering the result. 154 if (Result.getNode()) 155 SetPromotedInteger(SDValue(N, ResNo), Result); 156} 157 158SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 159 // Sign-extend the new bits, and continue the assertion. 160 MVT OldVT = N->getValueType(0); 161 SDValue Op = GetPromotedInteger(N->getOperand(0)); 162 return DAG.getNode(ISD::AssertSext, Op.getValueType(), 163 DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, 164 DAG.getValueType(OldVT)), N->getOperand(1)); 165} 166 167SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 168 // Zero the new bits, and continue the assertion. 169 MVT OldVT = N->getValueType(0); 170 SDValue Op = GetPromotedInteger(N->getOperand(0)); 171 return DAG.getNode(ISD::AssertZext, Op.getValueType(), 172 DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1)); 173} 174 175SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 176 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 177 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(), 178 Op2, N->getSrcValue(), N->getAlignment()); 179 // Legalized the chain result - switch anything that used the old chain to 180 // use the new one. 181 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 182 return Res; 183} 184 185SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 186 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 187 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 188 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(), 189 Op2, Op3, N->getSrcValue(), N->getAlignment()); 190 // Legalized the chain result - switch anything that used the old chain to 191 // use the new one. 192 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 193 return Res; 194} 195 196SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 197 SDValue InOp = N->getOperand(0); 198 MVT InVT = InOp.getValueType(); 199 MVT NInVT = TLI.getTypeToTransformTo(InVT); 200 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 201 202 switch (getTypeAction(InVT)) { 203 default: 204 assert(false && "Unknown type action!"); 205 break; 206 case Legal: 207 break; 208 case PromoteInteger: 209 if (OutVT.bitsEq(NInVT)) 210 // The input promotes to the same size. Convert the promoted value. 211 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp)); 212 break; 213 case SoftenFloat: 214 // Promote the integer operand by hand. 215 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp)); 216 case ExpandInteger: 217 case ExpandFloat: 218 break; 219 case ScalarizeVector: 220 // Convert the element to an integer and promote it by hand. 221 return DAG.getNode(ISD::ANY_EXTEND, OutVT, 222 BitConvertToInteger(GetScalarizedVector(InOp))); 223 case SplitVector: 224 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 225 // pieces of the input into integers and reassemble in the final type. 226 SDValue Lo, Hi; 227 GetSplitVector(N->getOperand(0), Lo, Hi); 228 Lo = BitConvertToInteger(Lo); 229 Hi = BitConvertToInteger(Hi); 230 231 if (TLI.isBigEndian()) 232 std::swap(Lo, Hi); 233 234 InOp = DAG.getNode(ISD::ANY_EXTEND, 235 MVT::getIntegerVT(OutVT.getSizeInBits()), 236 JoinIntegers(Lo, Hi)); 237 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp); 238 } 239 240 // Otherwise, lower the bit-convert to a store/load from the stack, then 241 // promote the load. 242 SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0)); 243 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode())); 244} 245 246SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 247 SDValue Op = GetPromotedInteger(N->getOperand(0)); 248 MVT OVT = N->getValueType(0); 249 MVT NVT = Op.getValueType(); 250 251 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 252 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op), 253 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 254} 255 256SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 257 // The pair element type may be legal, or may not promote to the same type as 258 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 259 return DAG.getNode(ISD::ANY_EXTEND, 260 TLI.getTypeToTransformTo(N->getValueType(0)), 261 JoinIntegers(N->getOperand(0), N->getOperand(1))); 262} 263 264SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 265 MVT VT = N->getValueType(0); 266 // Zero extend things like i1, sign extend everything else. It shouldn't 267 // matter in theory which one we pick, but this tends to give better code? 268 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 269 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), 270 SDValue(N, 0)); 271 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 272 return Result; 273} 274 275SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 276 SDValue Op = GetPromotedInteger(N->getOperand(0)); 277 MVT OVT = N->getValueType(0); 278 MVT NVT = Op.getValueType(); 279 // Zero extend to the promoted type and do the count there. 280 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT)); 281 // Subtract off the extra leading bits in the bigger type. 282 return DAG.getNode(ISD::SUB, NVT, Op, 283 DAG.getConstant(NVT.getSizeInBits() - 284 OVT.getSizeInBits(), NVT)); 285} 286 287SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 288 SDValue Op = GetPromotedInteger(N->getOperand(0)); 289 MVT OVT = N->getValueType(0); 290 MVT NVT = Op.getValueType(); 291 // Zero extend to the promoted type and do the count there. 292 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT)); 293} 294 295SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 296 SDValue Op = GetPromotedInteger(N->getOperand(0)); 297 MVT OVT = N->getValueType(0); 298 MVT NVT = Op.getValueType(); 299 // The count is the same in the promoted type except if the original 300 // value was zero. This can be handled by setting the bit just off 301 // the top of the original type. 302 APInt TopBit(NVT.getSizeInBits(), 0); 303 TopBit.set(OVT.getSizeInBits()); 304 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT)); 305 return DAG.getNode(ISD::CTTZ, NVT, Op); 306} 307 308SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 309 MVT OldVT = N->getValueType(0); 310 SDValue OldVec = N->getOperand(0); 311 unsigned OldElts = OldVec.getValueType().getVectorNumElements(); 312 313 if (OldElts == 1) { 314 assert(!isTypeLegal(OldVec.getValueType()) && 315 "Legal one-element vector of a type needing promotion!"); 316 // It is tempting to follow GetScalarizedVector by a call to 317 // GetPromotedInteger, but this would be wrong because the 318 // scalarized value may not yet have been processed. 319 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), 320 GetScalarizedVector(OldVec)); 321 } 322 323 // Convert to a vector half as long with an element type of twice the width, 324 // for example <4 x i16> -> <2 x i32>. 325 assert(!(OldElts & 1) && "Odd length vectors not supported!"); 326 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 327 assert(OldVT.isSimple() && NewVT.isSimple()); 328 329 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, 330 MVT::getVectorVT(NewVT, OldElts / 2), 331 OldVec); 332 333 // Extract the element at OldIdx / 2 from the new vector. 334 SDValue OldIdx = N->getOperand(1); 335 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx, 336 DAG.getConstant(1, TLI.getShiftAmountTy())); 337 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx); 338 339 // Select the appropriate half of the element: Lo if OldIdx was even, 340 // Hi if it was odd. 341 SDValue Lo = Elt; 342 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt, 343 DAG.getConstant(OldVT.getSizeInBits(), 344 TLI.getShiftAmountTy())); 345 if (TLI.isBigEndian()) 346 std::swap(Lo, Hi); 347 348 SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx); 349 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo); 350} 351 352SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 353 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 354 unsigned NewOpc = N->getOpcode(); 355 356 // If we're promoting a UINT to a larger size, check to see if the new node 357 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 358 // we can use that instead. This allows us to generate better code for 359 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 360 // legal, such as PowerPC. 361 if (N->getOpcode() == ISD::FP_TO_UINT && 362 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 363 TLI.isOperationLegal(ISD::FP_TO_SINT, NVT)) 364 NewOpc = ISD::FP_TO_SINT; 365 366 SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0)); 367 368 // Assert that the converted value fits in the original type. If it doesn't 369 // (eg: because the value being converted is too big), then the result of the 370 // original operation was undefined anyway, so the assert is still correct. 371 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 372 ISD::AssertZext : ISD::AssertSext, 373 NVT, Res, DAG.getValueType(N->getValueType(0))); 374} 375 376SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 377 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 378 379 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 380 SDValue Res = GetPromotedInteger(N->getOperand(0)); 381 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 382 383 // If the result and operand types are the same after promotion, simplify 384 // to an in-register extension. 385 if (NVT == Res.getValueType()) { 386 // The high bits are not guaranteed to be anything. Insert an extend. 387 if (N->getOpcode() == ISD::SIGN_EXTEND) 388 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, 389 DAG.getValueType(N->getOperand(0).getValueType())); 390 if (N->getOpcode() == ISD::ZERO_EXTEND) 391 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); 392 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 393 return Res; 394 } 395 } 396 397 // Otherwise, just extend the original operand all the way to the larger type. 398 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0)); 399} 400 401SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 402 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 403 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 404 ISD::LoadExtType ExtType = 405 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 406 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(), 407 N->getSrcValue(), N->getSrcValueOffset(), 408 N->getMemoryVT(), N->isVolatile(), 409 N->getAlignment()); 410 411 // Legalized the chain result - switch anything that used the old chain to 412 // use the new one. 413 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 414 return Res; 415} 416 417SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 418 // Sign extend the input. 419 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 420 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 421 MVT VT = N->getValueType(0); 422 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS, 423 DAG.getValueType(VT)); 424 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS, 425 DAG.getValueType(VT)); 426 427 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 428} 429 430SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 431 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 432 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 433 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS); 434} 435 436SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 437 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 438 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 439 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0), 440 N->getOperand(1), LHS, RHS, N->getOperand(4)); 441} 442 443SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 444 MVT SVT = TLI.getSetCCResultType(N->getOperand(0)); 445 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 446 447 // Get the SETCC result using the canonical SETCC type. 448 SDValue SetCC = DAG.getNode(ISD::SETCC, SVT, N->getOperand(0), 449 N->getOperand(1), N->getOperand(2)); 450 451 // Convert to the expected type. 452 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 453 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 454 return DAG.getNode(ISD::TRUNCATE, NVT, SetCC); 455} 456 457SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 458 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)), 459 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 460} 461 462SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 463 SDValue Op = GetPromotedInteger(N->getOperand(0)); 464 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, 465 N->getOperand(1)); 466} 467 468SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 469 // The input may have strange things in the top bits of the registers, but 470 // these operations don't care. They may have weird bits going out, but 471 // that too is okay if they are integer operations. 472 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 473 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 474 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 475} 476 477SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 478 // The input value must be properly sign extended. 479 MVT VT = N->getValueType(0); 480 MVT NVT = TLI.getTypeToTransformTo(VT); 481 SDValue Res = GetPromotedInteger(N->getOperand(0)); 482 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT)); 483 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1)); 484} 485 486SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 487 // The input value must be properly zero extended. 488 MVT VT = N->getValueType(0); 489 MVT NVT = TLI.getTypeToTransformTo(VT); 490 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 491 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1)); 492} 493 494SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 495 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 496 SDValue Res; 497 498 switch (getTypeAction(N->getOperand(0).getValueType())) { 499 default: assert(0 && "Unknown type action!"); 500 case Legal: 501 case ExpandInteger: 502 Res = N->getOperand(0); 503 break; 504 case PromoteInteger: 505 Res = GetPromotedInteger(N->getOperand(0)); 506 break; 507 } 508 509 // Truncate to NVT instead of VT 510 return DAG.getNode(ISD::TRUNCATE, NVT, Res); 511} 512 513SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 514 // Zero extend the input. 515 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 516 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 517 MVT VT = N->getValueType(0); 518 LHS = DAG.getZeroExtendInReg(LHS, VT); 519 RHS = DAG.getZeroExtendInReg(RHS, VT); 520 521 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 522} 523 524SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 525 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0))); 526} 527 528SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 529 SDValue Chain = N->getOperand(0); // Get the chain. 530 SDValue Ptr = N->getOperand(1); // Get the pointer. 531 MVT VT = N->getValueType(0); 532 533 MVT RegVT = TLI.getRegisterType(VT); 534 unsigned NumRegs = TLI.getNumRegisters(VT); 535 // The argument is passed as NumRegs registers of type RegVT. 536 537 SmallVector<SDValue, 8> Parts(NumRegs); 538 for (unsigned i = 0; i < NumRegs; ++i) { 539 Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2)); 540 Chain = Parts[i].getValue(1); 541 } 542 543 // Handle endianness of the load. 544 if (TLI.isBigEndian()) 545 std::reverse(Parts.begin(), Parts.end()); 546 547 // Assemble the parts in the promoted type. 548 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 549 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[0]); 550 for (unsigned i = 1; i < NumRegs; ++i) { 551 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[i]); 552 // Shift it to the right position and "or" it in. 553 Part = DAG.getNode(ISD::SHL, NVT, Part, 554 DAG.getConstant(i * RegVT.getSizeInBits(), 555 TLI.getShiftAmountTy())); 556 Res = DAG.getNode(ISD::OR, NVT, Res, Part); 557 } 558 559 // Modified the chain result - switch anything that used the old chain to 560 // use the new one. 561 ReplaceValueWith(SDValue(N, 1), Chain); 562 563 return Res; 564} 565 566 567//===----------------------------------------------------------------------===// 568// Integer Operand Promotion 569//===----------------------------------------------------------------------===// 570 571/// PromoteIntegerOperand - This method is called when the specified operand of 572/// the specified node is found to need promotion. At this point, all of the 573/// result types of the node are known to be legal, but other operands of the 574/// node may need promotion or expansion as well as the specified one. 575bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 576 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); 577 SDValue Res = SDValue(); 578 579 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 580 == TargetLowering::Custom) 581 Res = TLI.LowerOperation(SDValue(N, 0), DAG); 582 583 if (Res.getNode() == 0) { 584 switch (N->getOpcode()) { 585 default: 586 #ifndef NDEBUG 587 cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; 588 N->dump(&DAG); cerr << "\n"; 589 #endif 590 assert(0 && "Do not know how to promote this operator's operand!"); 591 abort(); 592 593 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 594 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 595 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 596 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 597 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 598 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break; 599 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break; 600 case ISD::INSERT_VECTOR_ELT: 601 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 602 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 603 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 604 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 605 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 606 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 607 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 608 OpNo); break; 609 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 610 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 611 612 case ISD::SINT_TO_FP: 613 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break; 614 } 615 } 616 617 // If the result is null, the sub-method took care of registering results etc. 618 if (!Res.getNode()) return false; 619 // If the result is N, the sub-method updated N in place. 620 if (Res.getNode() == N) { 621 // Mark N as new and remark N and its operands. This allows us to correctly 622 // revisit N if it needs another step of promotion and allows us to visit 623 // any new operands to N. 624 ReanalyzeNode(N); 625 return true; 626 } 627 628 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 629 "Invalid operand expansion"); 630 631 ReplaceValueWith(SDValue(N, 0), Res); 632 return false; 633} 634 635/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 636/// shared among BR_CC, SELECT_CC, and SETCC handlers. 637void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 638 ISD::CondCode CCCode) { 639 MVT VT = NewLHS.getValueType(); 640 641 // Get the promoted values. 642 NewLHS = GetPromotedInteger(NewLHS); 643 NewRHS = GetPromotedInteger(NewRHS); 644 645 // Otherwise, we have to insert explicit sign or zero extends. Note 646 // that we could insert sign extends for ALL conditions, but zero extend 647 // is cheaper on many machines (an AND instead of two shifts), so prefer 648 // it. 649 switch (CCCode) { 650 default: assert(0 && "Unknown integer comparison!"); 651 case ISD::SETEQ: 652 case ISD::SETNE: 653 case ISD::SETUGE: 654 case ISD::SETUGT: 655 case ISD::SETULE: 656 case ISD::SETULT: 657 // ALL of these operations will work if we either sign or zero extend 658 // the operands (including the unsigned comparisons!). Zero extend is 659 // usually a simpler/cheaper operation, so prefer it. 660 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT); 661 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT); 662 break; 663 case ISD::SETGE: 664 case ISD::SETGT: 665 case ISD::SETLT: 666 case ISD::SETLE: 667 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS, 668 DAG.getValueType(VT)); 669 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS, 670 DAG.getValueType(VT)); 671 break; 672 } 673} 674 675SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 676 SDValue Op = GetPromotedInteger(N->getOperand(0)); 677 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 678} 679 680SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 681 assert(OpNo == 2 && "Don't know how to promote this operand!"); 682 683 SDValue LHS = N->getOperand(2); 684 SDValue RHS = N->getOperand(3); 685 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 686 687 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 688 // legal types. 689 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 690 N->getOperand(1), LHS, RHS, N->getOperand(4)); 691} 692 693SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 694 assert(OpNo == 1 && "only know how to promote condition"); 695 SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition. 696 697 // Make sure the extra bits coming from type promotion conform to 698 // getSetCCResultContents. 699 unsigned CondBits = Cond.getValueSizeInBits(); 700 switch (TLI.getSetCCResultContents()) { 701 default: 702 assert(false && "Unknown SetCCResultValue!"); 703 case TargetLowering::UndefinedSetCCResult: 704 // The promoted value, which may contain rubbish in the upper bits, is fine. 705 break; 706 case TargetLowering::ZeroOrOneSetCCResult: 707 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1))) 708 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); 709 break; 710 case TargetLowering::ZeroOrNegativeOneSetCCResult: 711 if (DAG.ComputeNumSignBits(Cond) != CondBits) 712 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond, 713 DAG.getValueType(MVT::i1)); 714 break; 715 } 716 717 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 718 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, 719 N->getOperand(2)); 720} 721 722SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 723 // Since the result type is legal, the operands must promote to it. 724 MVT OVT = N->getOperand(0).getValueType(); 725 SDValue Lo = GetPromotedInteger(N->getOperand(0)); 726 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 727 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 728 729 Lo = DAG.getZeroExtendInReg(Lo, OVT); 730 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi, 731 DAG.getConstant(OVT.getSizeInBits(), 732 TLI.getShiftAmountTy())); 733 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi); 734} 735 736SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 737 // The vector type is legal but the element type is not. This implies 738 // that the vector is a power-of-two in length and that the element 739 // type does not have a strange size (eg: it is not i1). 740 MVT VecVT = N->getValueType(0); 741 unsigned NumElts = VecVT.getVectorNumElements(); 742 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 743 744 // Build a vector of half the length out of elements of twice the bitwidth. 745 // For example <4 x i16> -> <2 x i32>. 746 MVT OldVT = N->getOperand(0).getValueType(); 747 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 748 assert(OldVT.isSimple() && NewVT.isSimple()); 749 750 std::vector<SDValue> NewElts; 751 NewElts.reserve(NumElts/2); 752 753 for (unsigned i = 0; i < NumElts; i += 2) { 754 // Combine two successive elements into one promoted element. 755 SDValue Lo = N->getOperand(i); 756 SDValue Hi = N->getOperand(i+1); 757 if (TLI.isBigEndian()) 758 std::swap(Lo, Hi); 759 NewElts.push_back(JoinIntegers(Lo, Hi)); 760 } 761 762 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, 763 MVT::getVectorVT(NewVT, NewElts.size()), 764 &NewElts[0], NewElts.size()); 765 766 // Convert the new vector to the old vector type. 767 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); 768} 769 770SDValue DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) { 771 SDValue Op = GetPromotedInteger(N->getOperand(0)); 772 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op); 773} 774 775SDValue DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) { 776 SDValue Op = GetPromotedInteger(N->getOperand(0)); 777 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op, 778 DAG.getIntPtrConstant(0)); 779} 780 781SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 782 unsigned OpNo) { 783 if (OpNo == 1) { 784 // Promote the inserted value. This is valid because the type does not 785 // have to match the vector element type. 786 787 // Check that any extra bits introduced will be truncated away. 788 assert(N->getOperand(1).getValueType().getSizeInBits() >= 789 N->getValueType(0).getVectorElementType().getSizeInBits() && 790 "Type of inserted value narrower than vector element type!"); 791 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 792 GetPromotedInteger(N->getOperand(1)), 793 N->getOperand(2)); 794 } 795 796 assert(OpNo == 2 && "Different operand and result vector types?"); 797 798 // Promote the index. 799 SDValue Idx = N->getOperand(2); 800 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType()); 801 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 802 N->getOperand(1), Idx); 803} 804 805SDValue DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) { 806 SDValue In = GetPromotedInteger(N->getOperand(0)); 807 MVT OpVT = N->getOperand(0).getValueType(); 808 if (N->getOpcode() == ISD::UINT_TO_FP) 809 In = DAG.getZeroExtendInReg(In, OpVT); 810 else 811 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), 812 In, DAG.getValueType(OpVT)); 813 814 return DAG.UpdateNodeOperands(SDValue(N, 0), In); 815} 816 817SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 818 SDValue NewOps[6]; 819 NewOps[0] = N->getOperand(0); 820 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 821 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 822 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); 823 } 824 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, 825 array_lengthof(NewOps)); 826} 827 828SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 829 assert(OpNo == 0 && "Only know how to promote condition"); 830 SDValue Cond = GetPromotedInteger(N->getOperand(0)); 831 832 // Promote all the way up to SVT, the canonical SetCC type. 833 // FIXME: Not clear what value to pass to getSetCCResultType. 834 // [This only matters for CellSPU since all other targets 835 // ignore the argument.] We used to pass Cond, resulting in 836 // SVT = MVT::i8, but CellSPU has no select patterns for i8, 837 // causing an abort later. Passing the result type works 838 // around the problem. 839 MVT SVT = TLI.getSetCCResultType(N->getOperand(1)); 840 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 841 assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!"); 842 843 // Make sure the extra bits conform to getSetCCResultContents. There are 844 // two sets of extra bits: those in Cond, which come from type promotion, 845 // and those we need to add to have the final type be SVT (for most targets 846 // this last set of bits is empty). 847 unsigned CondBits = Cond.getValueSizeInBits(); 848 ISD::NodeType ExtendCode; 849 switch (TLI.getSetCCResultContents()) { 850 default: 851 assert(false && "Unknown SetCCResultValue!"); 852 case TargetLowering::UndefinedSetCCResult: 853 // Extend to SVT by adding rubbish. 854 ExtendCode = ISD::ANY_EXTEND; 855 break; 856 case TargetLowering::ZeroOrOneSetCCResult: 857 ExtendCode = ISD::ZERO_EXTEND; 858 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1))) 859 // All extra bits need to be cleared. Do this by zero extending the 860 // original condition value all the way to SVT. 861 Cond = N->getOperand(0); 862 break; 863 case TargetLowering::ZeroOrNegativeOneSetCCResult: { 864 ExtendCode = ISD::SIGN_EXTEND; 865 unsigned SignBits = DAG.ComputeNumSignBits(Cond); 866 if (SignBits != CondBits) 867 // All extra bits need to be sign extended. Do this by sign extending the 868 // original condition value all the way to SVT. 869 Cond = N->getOperand(0); 870 break; 871 } 872 } 873 Cond = DAG.getNode(ExtendCode, SVT, Cond); 874 875 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, 876 N->getOperand(1), N->getOperand(2)); 877} 878 879SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 880 assert(OpNo == 0 && "Don't know how to promote this operand!"); 881 882 SDValue LHS = N->getOperand(0); 883 SDValue RHS = N->getOperand(1); 884 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 885 886 // The CC (#4) and the possible return values (#2 and #3) have legal types. 887 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2), 888 N->getOperand(3), N->getOperand(4)); 889} 890 891SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 892 assert(OpNo == 0 && "Don't know how to promote this operand!"); 893 894 SDValue LHS = N->getOperand(0); 895 SDValue RHS = N->getOperand(1); 896 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 897 898 // The CC (#2) is always legal. 899 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); 900} 901 902SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 903 SDValue Op = GetPromotedInteger(N->getOperand(0)); 904 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 905 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), 906 Op, DAG.getValueType(N->getOperand(0).getValueType())); 907} 908 909SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 910 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 911 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 912 int SVOffset = N->getSrcValueOffset(); 913 unsigned Alignment = N->getAlignment(); 914 bool isVolatile = N->isVolatile(); 915 916 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 917 918 assert(!N->isTruncatingStore() && "Cannot promote this store operand!"); 919 920 // Truncate the value and store the result. 921 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(), 922 SVOffset, N->getMemoryVT(), 923 isVolatile, Alignment); 924} 925 926SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 927 SDValue Op = GetPromotedInteger(N->getOperand(0)); 928 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op); 929} 930 931SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 932 SDValue Op = GetPromotedInteger(N->getOperand(0)); 933 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 934 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); 935} 936 937 938//===----------------------------------------------------------------------===// 939// Integer Result Expansion 940//===----------------------------------------------------------------------===// 941 942/// ExpandIntegerResult - This method is called when the specified result of the 943/// specified node is found to need expansion. At this point, the node may also 944/// have invalid operands or may have other results that need promotion, we just 945/// know that (at least) one result needs expansion. 946void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 947 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n"); 948 SDValue Lo, Hi; 949 Lo = Hi = SDValue(); 950 951 // See if the target wants to custom expand this node. 952 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 953 TargetLowering::Custom) { 954 // If the target wants to, allow it to lower this itself. 955 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 956 // Everything that once used N now uses P. We are guaranteed that the 957 // result value types of N and the result value types of P match. 958 ReplaceNodeWith(N, P); 959 return; 960 } 961 } 962 963 switch (N->getOpcode()) { 964 default: 965#ifndef NDEBUG 966 cerr << "ExpandIntegerResult #" << ResNo << ": "; 967 N->dump(&DAG); cerr << "\n"; 968#endif 969 assert(0 && "Do not know how to expand the result of this operator!"); 970 abort(); 971 972 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 973 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 974 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 975 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 976 977 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 978 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 979 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 980 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 981 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 982 983 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 984 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 985 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 986 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 987 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 988 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 989 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 990 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 991 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 992 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 993 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 994 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 995 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 996 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 997 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 998 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 999 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 1000 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 1001 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 1002 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 1003 1004 case ISD::AND: 1005 case ISD::OR: 1006 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 1007 1008 case ISD::ADD: 1009 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1010 1011 case ISD::ADDC: 1012 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1013 1014 case ISD::ADDE: 1015 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1016 1017 case ISD::SHL: 1018 case ISD::SRA: 1019 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1020 } 1021 1022 // If Lo/Hi is null, the sub-method took care of registering results etc. 1023 if (Lo.getNode()) 1024 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1025} 1026 1027/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1028/// and the shift amount is a constant 'Amt'. Expand the operation. 1029void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1030 SDValue &Lo, SDValue &Hi) { 1031 // Expand the incoming operand to be shifted, so that we have its parts 1032 SDValue InL, InH; 1033 GetExpandedInteger(N->getOperand(0), InL, InH); 1034 1035 MVT NVT = InL.getValueType(); 1036 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1037 unsigned NVTBits = NVT.getSizeInBits(); 1038 MVT ShTy = N->getOperand(1).getValueType(); 1039 1040 if (N->getOpcode() == ISD::SHL) { 1041 if (Amt > VTBits) { 1042 Lo = Hi = DAG.getConstant(0, NVT); 1043 } else if (Amt > NVTBits) { 1044 Lo = DAG.getConstant(0, NVT); 1045 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1046 } else if (Amt == NVTBits) { 1047 Lo = DAG.getConstant(0, NVT); 1048 Hi = InL; 1049 } else if (Amt == 1) { 1050 // Emit this X << 1 as X+X. 1051 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1052 SDValue LoOps[2] = { InL, InL }; 1053 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1054 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1055 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1056 } else { 1057 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1058 Hi = DAG.getNode(ISD::OR, NVT, 1059 DAG.getNode(ISD::SHL, NVT, InH, 1060 DAG.getConstant(Amt, ShTy)), 1061 DAG.getNode(ISD::SRL, NVT, InL, 1062 DAG.getConstant(NVTBits-Amt, ShTy))); 1063 } 1064 return; 1065 } 1066 1067 if (N->getOpcode() == ISD::SRL) { 1068 if (Amt > VTBits) { 1069 Lo = DAG.getConstant(0, NVT); 1070 Hi = DAG.getConstant(0, NVT); 1071 } else if (Amt > NVTBits) { 1072 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1073 Hi = DAG.getConstant(0, NVT); 1074 } else if (Amt == NVTBits) { 1075 Lo = InH; 1076 Hi = DAG.getConstant(0, NVT); 1077 } else { 1078 Lo = DAG.getNode(ISD::OR, NVT, 1079 DAG.getNode(ISD::SRL, NVT, InL, 1080 DAG.getConstant(Amt, ShTy)), 1081 DAG.getNode(ISD::SHL, NVT, InH, 1082 DAG.getConstant(NVTBits-Amt, ShTy))); 1083 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1084 } 1085 return; 1086 } 1087 1088 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1089 if (Amt > VTBits) { 1090 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 1091 DAG.getConstant(NVTBits-1, ShTy)); 1092 } else if (Amt > NVTBits) { 1093 Lo = DAG.getNode(ISD::SRA, NVT, InH, 1094 DAG.getConstant(Amt-NVTBits, ShTy)); 1095 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1096 DAG.getConstant(NVTBits-1, ShTy)); 1097 } else if (Amt == NVTBits) { 1098 Lo = InH; 1099 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1100 DAG.getConstant(NVTBits-1, ShTy)); 1101 } else { 1102 Lo = DAG.getNode(ISD::OR, NVT, 1103 DAG.getNode(ISD::SRL, NVT, InL, 1104 DAG.getConstant(Amt, ShTy)), 1105 DAG.getNode(ISD::SHL, NVT, InH, 1106 DAG.getConstant(NVTBits-Amt, ShTy))); 1107 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy)); 1108 } 1109} 1110 1111/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1112/// this shift based on knowledge of the high bit of the shift amount. If we 1113/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1114/// shift amount. 1115bool DAGTypeLegalizer:: 1116ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1117 SDValue Amt = N->getOperand(1); 1118 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1119 MVT ShTy = Amt.getValueType(); 1120 unsigned ShBits = ShTy.getSizeInBits(); 1121 unsigned NVTBits = NVT.getSizeInBits(); 1122 assert(isPowerOf2_32(NVTBits) && 1123 "Expanded integer type size not a power of two!"); 1124 1125 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1126 APInt KnownZero, KnownOne; 1127 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1128 1129 // If we don't know anything about the high bits, exit. 1130 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1131 return false; 1132 1133 // Get the incoming operand to be shifted. 1134 SDValue InL, InH; 1135 GetExpandedInteger(N->getOperand(0), InL, InH); 1136 1137 // If we know that any of the high bits of the shift amount are one, then we 1138 // can do this as a couple of simple shifts. 1139 if (KnownOne.intersects(HighBitMask)) { 1140 // Mask out the high bit, which we know is set. 1141 Amt = DAG.getNode(ISD::AND, ShTy, Amt, 1142 DAG.getConstant(~HighBitMask, ShTy)); 1143 1144 switch (N->getOpcode()) { 1145 default: assert(0 && "Unknown shift"); 1146 case ISD::SHL: 1147 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1148 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 1149 return true; 1150 case ISD::SRL: 1151 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1152 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 1153 return true; 1154 case ISD::SRA: 1155 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 1156 DAG.getConstant(NVTBits-1, ShTy)); 1157 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 1158 return true; 1159 } 1160 } 1161 1162 // If we know that all of the high bits of the shift amount are zero, then we 1163 // can do this as a couple of simple shifts. 1164 if ((KnownZero & HighBitMask) == HighBitMask) { 1165 // Compute 32-amt. 1166 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1167 DAG.getConstant(NVTBits, ShTy), 1168 Amt); 1169 unsigned Op1, Op2; 1170 switch (N->getOpcode()) { 1171 default: assert(0 && "Unknown shift"); 1172 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1173 case ISD::SRL: 1174 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1175 } 1176 1177 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1178 Hi = DAG.getNode(ISD::OR, NVT, 1179 DAG.getNode(Op1, NVT, InH, Amt), 1180 DAG.getNode(Op2, NVT, InL, Amt2)); 1181 return true; 1182 } 1183 1184 return false; 1185} 1186 1187void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1188 SDValue &Lo, SDValue &Hi) { 1189 // Expand the subcomponents. 1190 SDValue LHSL, LHSH, RHSL, RHSH; 1191 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1192 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1193 1194 MVT NVT = LHSL.getValueType(); 1195 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1196 SDValue LoOps[2] = { LHSL, RHSL }; 1197 SDValue HiOps[3] = { LHSH, RHSH }; 1198 1199 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1200 // them. TODO: Teach operation legalization how to expand unsupported 1201 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1202 // a carry of type MVT::Flag, but there doesn't seem to be any way to 1203 // generate a value of this type in the expanded code sequence. 1204 bool hasCarry = 1205 TLI.isOperationLegal(N->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC, 1206 TLI.getTypeToExpandTo(NVT)); 1207 1208 if (hasCarry) { 1209 if (N->getOpcode() == ISD::ADD) { 1210 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1211 HiOps[2] = Lo.getValue(1); 1212 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1213 } else { 1214 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1215 HiOps[2] = Lo.getValue(1); 1216 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1217 } 1218 } else { 1219 if (N->getOpcode() == ISD::ADD) { 1220 Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2); 1221 Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2); 1222 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0], 1223 ISD::SETULT); 1224 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, 1225 DAG.getConstant(1, NVT), 1226 DAG.getConstant(0, NVT)); 1227 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[1], 1228 ISD::SETULT); 1229 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2, 1230 DAG.getConstant(1, NVT), Carry1); 1231 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2); 1232 } else { 1233 Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2); 1234 Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2); 1235 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT); 1236 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp, 1237 DAG.getConstant(1, NVT), 1238 DAG.getConstant(0, NVT)); 1239 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow); 1240 } 1241 } 1242} 1243 1244void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1245 SDValue &Lo, SDValue &Hi) { 1246 // Expand the subcomponents. 1247 SDValue LHSL, LHSH, RHSL, RHSH; 1248 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1249 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1250 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1251 SDValue LoOps[2] = { LHSL, RHSL }; 1252 SDValue HiOps[3] = { LHSH, RHSH }; 1253 1254 if (N->getOpcode() == ISD::ADDC) { 1255 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1256 HiOps[2] = Lo.getValue(1); 1257 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1258 } else { 1259 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1260 HiOps[2] = Lo.getValue(1); 1261 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1262 } 1263 1264 // Legalized the flag result - switch anything that used the old flag to 1265 // use the new one. 1266 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1267} 1268 1269void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1270 SDValue &Lo, SDValue &Hi) { 1271 // Expand the subcomponents. 1272 SDValue LHSL, LHSH, RHSL, RHSH; 1273 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1274 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1275 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1276 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1277 SDValue HiOps[3] = { LHSH, RHSH }; 1278 1279 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3); 1280 HiOps[2] = Lo.getValue(1); 1281 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3); 1282 1283 // Legalized the flag result - switch anything that used the old flag to 1284 // use the new one. 1285 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1286} 1287 1288void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1289 SDValue &Lo, SDValue &Hi) { 1290 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1291 SDValue Op = N->getOperand(0); 1292 if (Op.getValueType().bitsLE(NVT)) { 1293 // The low part is any extension of the input (which degenerates to a copy). 1294 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op); 1295 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined. 1296 } else { 1297 // For example, extension of an i48 to an i64. The operand type necessarily 1298 // promotes to the result type, so will end up being expanded too. 1299 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1300 "Only know how to promote this result!"); 1301 SDValue Res = GetPromotedInteger(Op); 1302 assert(Res.getValueType() == N->getValueType(0) && 1303 "Operand over promoted?"); 1304 // Split the promoted operand. This will simplify when it is expanded. 1305 SplitInteger(Res, Lo, Hi); 1306 } 1307} 1308 1309void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1310 SDValue &Lo, SDValue &Hi) { 1311 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1312 MVT NVT = Lo.getValueType(); 1313 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1314 unsigned NVTBits = NVT.getSizeInBits(); 1315 unsigned EVTBits = EVT.getSizeInBits(); 1316 1317 if (NVTBits < EVTBits) { 1318 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi, 1319 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1320 } else { 1321 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT)); 1322 // The high part replicates the sign bit of Lo, make it explicit. 1323 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1324 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy())); 1325 } 1326} 1327 1328void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1329 SDValue &Lo, SDValue &Hi) { 1330 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1331 MVT NVT = Lo.getValueType(); 1332 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1333 unsigned NVTBits = NVT.getSizeInBits(); 1334 unsigned EVTBits = EVT.getSizeInBits(); 1335 1336 if (NVTBits < EVTBits) { 1337 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, 1338 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1339 } else { 1340 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); 1341 // The high part must be zero, make it explicit. 1342 Hi = DAG.getConstant(0, NVT); 1343 } 1344} 1345 1346void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1347 SDValue &Lo, SDValue &Hi) { 1348 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1349 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo); 1350 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi); 1351} 1352 1353void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1354 SDValue &Lo, SDValue &Hi) { 1355 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1356 unsigned NBitWidth = NVT.getSizeInBits(); 1357 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1358 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 1359 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1360} 1361 1362void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1363 SDValue &Lo, SDValue &Hi) { 1364 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1365 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1366 MVT NVT = Lo.getValueType(); 1367 1368 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 1369 DAG.getConstant(0, NVT), ISD::SETNE); 1370 1371 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo); 1372 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 1373 1374 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ, 1375 DAG.getNode(ISD::ADD, NVT, LoLZ, 1376 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1377 Hi = DAG.getConstant(0, NVT); 1378} 1379 1380void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1381 SDValue &Lo, SDValue &Hi) { 1382 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1383 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1384 MVT NVT = Lo.getValueType(); 1385 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), 1386 DAG.getNode(ISD::CTPOP, NVT, Hi)); 1387 Hi = DAG.getConstant(0, NVT); 1388} 1389 1390void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1391 SDValue &Lo, SDValue &Hi) { 1392 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1393 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1394 MVT NVT = Lo.getValueType(); 1395 1396 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, 1397 DAG.getConstant(0, NVT), ISD::SETNE); 1398 1399 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 1400 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi); 1401 1402 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ, 1403 DAG.getNode(ISD::ADD, NVT, HiLZ, 1404 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1405 Hi = DAG.getConstant(0, NVT); 1406} 1407 1408void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1409 SDValue &Hi) { 1410 MVT VT = N->getValueType(0); 1411 SDValue Op = N->getOperand(0); 1412 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1413 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1414 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi); 1415} 1416 1417void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1418 SDValue &Hi) { 1419 MVT VT = N->getValueType(0); 1420 SDValue Op = N->getOperand(0); 1421 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1422 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1423 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi); 1424} 1425 1426void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1427 SDValue &Lo, SDValue &Hi) { 1428 if (ISD::isNormalLoad(N)) { 1429 ExpandRes_NormalLoad(N, Lo, Hi); 1430 return; 1431 } 1432 1433 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1434 1435 MVT VT = N->getValueType(0); 1436 MVT NVT = TLI.getTypeToTransformTo(VT); 1437 SDValue Ch = N->getChain(); 1438 SDValue Ptr = N->getBasePtr(); 1439 ISD::LoadExtType ExtType = N->getExtensionType(); 1440 int SVOffset = N->getSrcValueOffset(); 1441 unsigned Alignment = N->getAlignment(); 1442 bool isVolatile = N->isVolatile(); 1443 1444 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1445 1446 if (N->getMemoryVT().bitsLE(NVT)) { 1447 MVT EVT = N->getMemoryVT(); 1448 1449 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, 1450 isVolatile, Alignment); 1451 1452 // Remember the chain. 1453 Ch = Lo.getValue(1); 1454 1455 if (ExtType == ISD::SEXTLOAD) { 1456 // The high part is obtained by SRA'ing all but one of the bits of the 1457 // lo part. 1458 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1459 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1460 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1461 } else if (ExtType == ISD::ZEXTLOAD) { 1462 // The high part is just a zero. 1463 Hi = DAG.getConstant(0, NVT); 1464 } else { 1465 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1466 // The high part is undefined. 1467 Hi = DAG.getNode(ISD::UNDEF, NVT); 1468 } 1469 } else if (TLI.isLittleEndian()) { 1470 // Little-endian - low bits are at low addresses. 1471 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1472 isVolatile, Alignment); 1473 1474 unsigned ExcessBits = 1475 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1476 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1477 1478 // Increment the pointer to the other half. 1479 unsigned IncrementSize = NVT.getSizeInBits()/8; 1480 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1481 DAG.getIntPtrConstant(IncrementSize)); 1482 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), 1483 SVOffset+IncrementSize, NEVT, 1484 isVolatile, MinAlign(Alignment, IncrementSize)); 1485 1486 // Build a factor node to remember that this load is independent of the 1487 // other one. 1488 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1489 Hi.getValue(1)); 1490 } else { 1491 // Big-endian - high bits are at low addresses. Favor aligned loads at 1492 // the cost of some bit-fiddling. 1493 MVT EVT = N->getMemoryVT(); 1494 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1495 unsigned IncrementSize = NVT.getSizeInBits()/8; 1496 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1497 1498 // Load both the high bits and maybe some of the low bits. 1499 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1500 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1501 isVolatile, Alignment); 1502 1503 // Increment the pointer to the other half. 1504 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1505 DAG.getIntPtrConstant(IncrementSize)); 1506 // Load the rest of the low bits. 1507 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(), 1508 SVOffset+IncrementSize, 1509 MVT::getIntegerVT(ExcessBits), 1510 isVolatile, MinAlign(Alignment, IncrementSize)); 1511 1512 // Build a factor node to remember that this load is independent of the 1513 // other one. 1514 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1515 Hi.getValue(1)); 1516 1517 if (ExcessBits < NVT.getSizeInBits()) { 1518 // Transfer low bits from the bottom of Hi to the top of Lo. 1519 Lo = DAG.getNode(ISD::OR, NVT, Lo, 1520 DAG.getNode(ISD::SHL, NVT, Hi, 1521 DAG.getConstant(ExcessBits, 1522 TLI.getShiftAmountTy()))); 1523 // Move high bits to the right position in Hi. 1524 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi, 1525 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1526 TLI.getShiftAmountTy())); 1527 } 1528 } 1529 1530 // Legalized the chain result - switch anything that used the old chain to 1531 // use the new one. 1532 ReplaceValueWith(SDValue(N, 1), Ch); 1533} 1534 1535void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1536 SDValue &Lo, SDValue &Hi) { 1537 SDValue LL, LH, RL, RH; 1538 GetExpandedInteger(N->getOperand(0), LL, LH); 1539 GetExpandedInteger(N->getOperand(1), RL, RH); 1540 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL); 1541 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH); 1542} 1543 1544void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1545 SDValue &Lo, SDValue &Hi) { 1546 MVT VT = N->getValueType(0); 1547 MVT NVT = TLI.getTypeToTransformTo(VT); 1548 1549 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 1550 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 1551 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 1552 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 1553 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1554 SDValue LL, LH, RL, RH; 1555 GetExpandedInteger(N->getOperand(0), LL, LH); 1556 GetExpandedInteger(N->getOperand(1), RL, RH); 1557 unsigned OuterBitSize = VT.getSizeInBits(); 1558 unsigned InnerBitSize = NVT.getSizeInBits(); 1559 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1560 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1561 1562 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1563 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1564 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1565 // The inputs are both zero-extended. 1566 if (HasUMUL_LOHI) { 1567 // We can emit a umul_lohi. 1568 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1569 Hi = SDValue(Lo.getNode(), 1); 1570 return; 1571 } 1572 if (HasMULHU) { 1573 // We can emit a mulhu+mul. 1574 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1575 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1576 return; 1577 } 1578 } 1579 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1580 // The input values are both sign-extended. 1581 if (HasSMUL_LOHI) { 1582 // We can emit a smul_lohi. 1583 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1584 Hi = SDValue(Lo.getNode(), 1); 1585 return; 1586 } 1587 if (HasMULHS) { 1588 // We can emit a mulhs+mul. 1589 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1590 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 1591 return; 1592 } 1593 } 1594 if (HasUMUL_LOHI) { 1595 // Lo,Hi = umul LHS, RHS. 1596 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 1597 DAG.getVTList(NVT, NVT), LL, RL); 1598 Lo = UMulLOHI; 1599 Hi = UMulLOHI.getValue(1); 1600 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1601 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1602 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1603 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1604 return; 1605 } 1606 if (HasMULHU) { 1607 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1608 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1609 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1610 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1611 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1612 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1613 return; 1614 } 1615 } 1616 1617 // If nothing else, we can make a libcall. 1618 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1619 if (VT == MVT::i32) 1620 LC = RTLIB::MUL_I32; 1621 else if (VT == MVT::i64) 1622 LC = RTLIB::MUL_I64; 1623 else if (VT == MVT::i128) 1624 LC = RTLIB::MUL_I128; 1625 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1626 1627 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1628 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi); 1629} 1630 1631void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1632 SDValue &Lo, SDValue &Hi) { 1633 MVT VT = N->getValueType(0); 1634 1635 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1636 if (VT == MVT::i32) 1637 LC = RTLIB::SDIV_I32; 1638 else if (VT == MVT::i64) 1639 LC = RTLIB::SDIV_I64; 1640 else if (VT == MVT::i128) 1641 LC = RTLIB::SDIV_I128; 1642 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1643 1644 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1645 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1646} 1647 1648void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1649 SDValue &Lo, SDValue &Hi) { 1650 MVT VT = N->getValueType(0); 1651 1652 // If we can emit an efficient shift operation, do so now. Check to see if 1653 // the RHS is a constant. 1654 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1655 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1656 1657 // If we can determine that the high bit of the shift is zero or one, even if 1658 // the low bits are variable, emit this shift in an optimized form. 1659 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1660 return; 1661 1662 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1663 unsigned PartsOpc; 1664 if (N->getOpcode() == ISD::SHL) { 1665 PartsOpc = ISD::SHL_PARTS; 1666 } else if (N->getOpcode() == ISD::SRL) { 1667 PartsOpc = ISD::SRL_PARTS; 1668 } else { 1669 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1670 PartsOpc = ISD::SRA_PARTS; 1671 } 1672 1673 // Next check to see if the target supports this SHL_PARTS operation or if it 1674 // will custom expand it. 1675 MVT NVT = TLI.getTypeToTransformTo(VT); 1676 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1677 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1678 Action == TargetLowering::Custom) { 1679 // Expand the subcomponents. 1680 SDValue LHSL, LHSH; 1681 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1682 1683 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1684 MVT VT = LHSL.getValueType(); 1685 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 1686 Hi = Lo.getValue(1); 1687 return; 1688 } 1689 1690 // Otherwise, emit a libcall. 1691 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1692 bool isSigned; 1693 if (N->getOpcode() == ISD::SHL) { 1694 isSigned = false; /*sign irrelevant*/ 1695 if (VT == MVT::i32) 1696 LC = RTLIB::SHL_I32; 1697 else if (VT == MVT::i64) 1698 LC = RTLIB::SHL_I64; 1699 else if (VT == MVT::i128) 1700 LC = RTLIB::SHL_I128; 1701 } else if (N->getOpcode() == ISD::SRL) { 1702 isSigned = false; 1703 if (VT == MVT::i32) 1704 LC = RTLIB::SRL_I32; 1705 else if (VT == MVT::i64) 1706 LC = RTLIB::SRL_I64; 1707 else if (VT == MVT::i128) 1708 LC = RTLIB::SRL_I128; 1709 } else { 1710 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1711 isSigned = true; 1712 if (VT == MVT::i32) 1713 LC = RTLIB::SRA_I32; 1714 else if (VT == MVT::i64) 1715 LC = RTLIB::SRA_I64; 1716 else if (VT == MVT::i128) 1717 LC = RTLIB::SRA_I128; 1718 } 1719 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!"); 1720 1721 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1722 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi); 1723} 1724 1725void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 1726 SDValue &Lo, SDValue &Hi) { 1727 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1728 SDValue Op = N->getOperand(0); 1729 if (Op.getValueType().bitsLE(NVT)) { 1730 // The low part is sign extension of the input (degenerates to a copy). 1731 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); 1732 // The high part is obtained by SRA'ing all but one of the bits of low part. 1733 unsigned LoSize = NVT.getSizeInBits(); 1734 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1735 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1736 } else { 1737 // For example, extension of an i48 to an i64. The operand type necessarily 1738 // promotes to the result type, so will end up being expanded too. 1739 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1740 "Only know how to promote this result!"); 1741 SDValue Res = GetPromotedInteger(Op); 1742 assert(Res.getValueType() == N->getValueType(0) && 1743 "Operand over promoted?"); 1744 // Split the promoted operand. This will simplify when it is expanded. 1745 SplitInteger(Res, Lo, Hi); 1746 unsigned ExcessBits = 1747 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1748 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 1749 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1750 } 1751} 1752 1753void DAGTypeLegalizer:: 1754ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 1755 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1756 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1757 1758 if (EVT.bitsLE(Lo.getValueType())) { 1759 // sext_inreg the low part if needed. 1760 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo, 1761 N->getOperand(1)); 1762 1763 // The high part gets the sign extension from the lo-part. This handles 1764 // things like sextinreg V:i64 from i8. 1765 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo, 1766 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 1767 TLI.getShiftAmountTy())); 1768 } else { 1769 // For example, extension of an i48 to an i64. Leave the low part alone, 1770 // sext_inreg the high part. 1771 unsigned ExcessBits = 1772 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 1773 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 1774 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1775 } 1776} 1777 1778void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1779 SDValue &Lo, SDValue &Hi) { 1780 MVT VT = N->getValueType(0); 1781 1782 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1783 if (VT == MVT::i32) 1784 LC = RTLIB::SREM_I32; 1785 else if (VT == MVT::i64) 1786 LC = RTLIB::SREM_I64; 1787 else if (VT == MVT::i128) 1788 LC = RTLIB::SREM_I128; 1789 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1790 1791 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1792 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1793} 1794 1795void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 1796 SDValue &Lo, SDValue &Hi) { 1797 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1798 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); 1799 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), 1800 DAG.getConstant(NVT.getSizeInBits(), 1801 TLI.getShiftAmountTy())); 1802 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); 1803} 1804 1805void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1806 SDValue &Lo, SDValue &Hi) { 1807 MVT VT = N->getValueType(0); 1808 1809 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1810 if (VT == MVT::i32) 1811 LC = RTLIB::UDIV_I32; 1812 else if (VT == MVT::i64) 1813 LC = RTLIB::UDIV_I64; 1814 else if (VT == MVT::i128) 1815 LC = RTLIB::UDIV_I128; 1816 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 1817 1818 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1819 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1820} 1821 1822void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1823 SDValue &Lo, SDValue &Hi) { 1824 MVT VT = N->getValueType(0); 1825 1826 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1827 if (VT == MVT::i32) 1828 LC = RTLIB::UREM_I32; 1829 else if (VT == MVT::i64) 1830 LC = RTLIB::UREM_I64; 1831 else if (VT == MVT::i128) 1832 LC = RTLIB::UREM_I128; 1833 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 1834 1835 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1836 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1837} 1838 1839void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 1840 SDValue &Lo, SDValue &Hi) { 1841 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1842 SDValue Op = N->getOperand(0); 1843 if (Op.getValueType().bitsLE(NVT)) { 1844 // The low part is zero extension of the input (degenerates to a copy). 1845 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); 1846 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 1847 } else { 1848 // For example, extension of an i48 to an i64. The operand type necessarily 1849 // promotes to the result type, so will end up being expanded too. 1850 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1851 "Only know how to promote this result!"); 1852 SDValue Res = GetPromotedInteger(Op); 1853 assert(Res.getValueType() == N->getValueType(0) && 1854 "Operand over promoted?"); 1855 // Split the promoted operand. This will simplify when it is expanded. 1856 SplitInteger(Res, Lo, Hi); 1857 unsigned ExcessBits = 1858 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1859 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); 1860 } 1861} 1862 1863 1864//===----------------------------------------------------------------------===// 1865// Integer Operand Expansion 1866//===----------------------------------------------------------------------===// 1867 1868/// ExpandIntegerOperand - This method is called when the specified operand of 1869/// the specified node is found to need expansion. At this point, all of the 1870/// result types of the node are known to be legal, but other operands of the 1871/// node may need promotion or expansion as well as the specified one. 1872bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1873 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); 1874 SDValue Res = SDValue(); 1875 1876 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 1877 == TargetLowering::Custom) 1878 Res = TLI.LowerOperation(SDValue(N, 0), DAG); 1879 1880 if (Res.getNode() == 0) { 1881 switch (N->getOpcode()) { 1882 default: 1883 #ifndef NDEBUG 1884 cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; 1885 N->dump(&DAG); cerr << "\n"; 1886 #endif 1887 assert(0 && "Do not know how to expand this operator's operand!"); 1888 abort(); 1889 1890 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1891 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1892 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1893 1894 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1895 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1896 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1897 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 1898 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); 1899 break; 1900 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1901 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 1902 } 1903 } 1904 1905 // If the result is null, the sub-method took care of registering results etc. 1906 if (!Res.getNode()) return false; 1907 // If the result is N, the sub-method updated N in place. Check to see if any 1908 // operands are new, and if so, mark them. 1909 if (Res.getNode() == N) { 1910 // Mark N as new and remark N and its operands. This allows us to correctly 1911 // revisit N if it needs another step of expansion and allows us to visit 1912 // any new operands to N. 1913 ReanalyzeNode(N); 1914 return true; 1915 } 1916 1917 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1918 "Invalid operand expansion"); 1919 1920 ReplaceValueWith(SDValue(N, 0), Res); 1921 return false; 1922} 1923 1924/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 1925/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1926void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 1927 SDValue &NewRHS, 1928 ISD::CondCode &CCCode) { 1929 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 1930 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 1931 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 1932 1933 MVT VT = NewLHS.getValueType(); 1934 1935 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 1936 if (RHSLo == RHSHi) { 1937 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 1938 if (RHSCST->isAllOnesValue()) { 1939 // Equality comparison to -1. 1940 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1941 NewRHS = RHSLo; 1942 return; 1943 } 1944 } 1945 } 1946 1947 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1948 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1949 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS); 1950 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1951 return; 1952 } 1953 1954 // If this is a comparison of the sign bit, just look at the top part. 1955 // X > -1, x < 0 1956 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 1957 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 1958 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 1959 NewLHS = LHSHi; 1960 NewRHS = RHSHi; 1961 return; 1962 } 1963 1964 // FIXME: This generated code sucks. 1965 ISD::CondCode LowCC; 1966 switch (CCCode) { 1967 default: assert(0 && "Unknown integer setcc!"); 1968 case ISD::SETLT: 1969 case ISD::SETULT: LowCC = ISD::SETULT; break; 1970 case ISD::SETGT: 1971 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1972 case ISD::SETLE: 1973 case ISD::SETULE: LowCC = ISD::SETULE; break; 1974 case ISD::SETGE: 1975 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1976 } 1977 1978 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1979 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1980 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1981 1982 // NOTE: on targets without efficient SELECT of bools, we can always use 1983 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1984 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 1985 SDValue Tmp1, Tmp2; 1986 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC, 1987 false, DagCombineInfo); 1988 if (!Tmp1.getNode()) 1989 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 1990 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1991 CCCode, false, DagCombineInfo); 1992 if (!Tmp2.getNode()) 1993 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1994 DAG.getCondCode(CCCode)); 1995 1996 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 1997 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 1998 if ((Tmp1C && Tmp1C->isNullValue()) || 1999 (Tmp2C && Tmp2C->isNullValue() && 2000 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2001 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2002 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2003 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2004 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2005 // low part is known false, returns high part. 2006 // For LE / GE, if high part is known false, ignore the low part. 2007 // For LT / GT, if high part is known true, ignore the low part. 2008 NewLHS = Tmp2; 2009 NewRHS = SDValue(); 2010 return; 2011 } 2012 2013 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2014 ISD::SETEQ, false, DagCombineInfo); 2015 if (!NewLHS.getNode()) 2016 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2017 ISD::SETEQ); 2018 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 2019 NewLHS, Tmp1, Tmp2); 2020 NewRHS = SDValue(); 2021} 2022 2023SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2024 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2025 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2026 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2027 2028 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2029 // against zero to select between true and false values. 2030 if (NewRHS.getNode() == 0) { 2031 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2032 CCCode = ISD::SETNE; 2033 } 2034 2035 // Update N to have the operands specified. 2036 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 2037 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2038 N->getOperand(4)); 2039} 2040 2041SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2042 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2043 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2044 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2045 2046 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2047 // against zero to select between true and false values. 2048 if (NewRHS.getNode() == 0) { 2049 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2050 CCCode = ISD::SETNE; 2051 } 2052 2053 // Update N to have the operands specified. 2054 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2055 N->getOperand(2), N->getOperand(3), 2056 DAG.getCondCode(CCCode)); 2057} 2058 2059SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2060 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2061 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2062 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2063 2064 // If ExpandSetCCOperands returned a scalar, use it. 2065 if (NewRHS.getNode() == 0) { 2066 assert(NewLHS.getValueType() == N->getValueType(0) && 2067 "Unexpected setcc expansion!"); 2068 return NewLHS; 2069 } 2070 2071 // Otherwise, update N to have the operands specified. 2072 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2073 DAG.getCondCode(CCCode)); 2074} 2075 2076SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2077 SDValue Op = N->getOperand(0); 2078 MVT DstVT = N->getValueType(0); 2079 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2080 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2081 "Don't know how to expand this SINT_TO_FP!"); 2082 return MakeLibCall(LC, DstVT, &Op, 1, true); 2083} 2084 2085SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2086 if (ISD::isNormalStore(N)) 2087 return ExpandOp_NormalStore(N, OpNo); 2088 2089 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2090 assert(OpNo == 1 && "Can only expand the stored value so far"); 2091 2092 MVT VT = N->getOperand(1).getValueType(); 2093 MVT NVT = TLI.getTypeToTransformTo(VT); 2094 SDValue Ch = N->getChain(); 2095 SDValue Ptr = N->getBasePtr(); 2096 int SVOffset = N->getSrcValueOffset(); 2097 unsigned Alignment = N->getAlignment(); 2098 bool isVolatile = N->isVolatile(); 2099 SDValue Lo, Hi; 2100 2101 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2102 2103 if (N->getMemoryVT().bitsLE(NVT)) { 2104 GetExpandedInteger(N->getValue(), Lo, Hi); 2105 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 2106 N->getMemoryVT(), isVolatile, Alignment); 2107 } else if (TLI.isLittleEndian()) { 2108 // Little-endian - low bits are at low addresses. 2109 GetExpandedInteger(N->getValue(), Lo, Hi); 2110 2111 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 2112 isVolatile, Alignment); 2113 2114 unsigned ExcessBits = 2115 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2116 MVT NEVT = MVT::getIntegerVT(ExcessBits); 2117 2118 // Increment the pointer to the other half. 2119 unsigned IncrementSize = NVT.getSizeInBits()/8; 2120 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2121 DAG.getIntPtrConstant(IncrementSize)); 2122 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2123 SVOffset+IncrementSize, NEVT, 2124 isVolatile, MinAlign(Alignment, IncrementSize)); 2125 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2126 } else { 2127 // Big-endian - high bits are at low addresses. Favor aligned stores at 2128 // the cost of some bit-fiddling. 2129 GetExpandedInteger(N->getValue(), Lo, Hi); 2130 2131 MVT EVT = N->getMemoryVT(); 2132 unsigned EBytes = EVT.getStoreSizeInBits()/8; 2133 unsigned IncrementSize = NVT.getSizeInBits()/8; 2134 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2135 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 2136 2137 if (ExcessBits < NVT.getSizeInBits()) { 2138 // Transfer high bits from the top of Lo to the bottom of Hi. 2139 Hi = DAG.getNode(ISD::SHL, NVT, Hi, 2140 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2141 TLI.getShiftAmountTy())); 2142 Hi = DAG.getNode(ISD::OR, NVT, Hi, 2143 DAG.getNode(ISD::SRL, NVT, Lo, 2144 DAG.getConstant(ExcessBits, 2145 TLI.getShiftAmountTy()))); 2146 } 2147 2148 // Store both the high bits and maybe some of the low bits. 2149 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2150 SVOffset, HiVT, isVolatile, Alignment); 2151 2152 // Increment the pointer to the other half. 2153 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2154 DAG.getIntPtrConstant(IncrementSize)); 2155 // Store the lowest ExcessBits bits in the second half. 2156 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), 2157 SVOffset+IncrementSize, 2158 MVT::getIntegerVT(ExcessBits), 2159 isVolatile, MinAlign(Alignment, IncrementSize)); 2160 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2161 } 2162} 2163 2164SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2165 SDValue InL, InH; 2166 GetExpandedInteger(N->getOperand(0), InL, InH); 2167 // Just truncate the low part of the source. 2168 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL); 2169} 2170 2171SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2172 SDValue Op = N->getOperand(0); 2173 MVT SrcVT = Op.getValueType(); 2174 MVT DstVT = N->getValueType(0); 2175 2176 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2177 // Do a signed conversion then adjust the result. 2178 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op); 2179 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2180 2181 // The result of the signed conversion needs adjusting if the 'sign bit' of 2182 // the incoming integer was set. To handle this, we dynamically test to see 2183 // if it is set, and, if so, add a fudge factor. 2184 2185 const uint64_t F32TwoE32 = 0x4F800000ULL; 2186 const uint64_t F32TwoE64 = 0x5F800000ULL; 2187 const uint64_t F32TwoE128 = 0x7F800000ULL; 2188 2189 APInt FF(32, 0); 2190 if (SrcVT == MVT::i32) 2191 FF = APInt(32, F32TwoE32); 2192 else if (SrcVT == MVT::i64) 2193 FF = APInt(32, F32TwoE64); 2194 else if (SrcVT == MVT::i128) 2195 FF = APInt(32, F32TwoE128); 2196 else 2197 assert(false && "Unsupported UINT_TO_FP!"); 2198 2199 // Check whether the sign bit is set. 2200 SDValue Lo, Hi; 2201 GetExpandedInteger(Op, Lo, Hi); 2202 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 2203 DAG.getConstant(0, Hi.getValueType()), 2204 ISD::SETLT); 2205 2206 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2207 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)), 2208 TLI.getPointerTy()); 2209 2210 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2211 SDValue Zero = DAG.getIntPtrConstant(0); 2212 SDValue Four = DAG.getIntPtrConstant(4); 2213 if (TLI.isBigEndian()) std::swap(Zero, Four); 2214 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet, 2215 Zero, Four); 2216 unsigned Alignment = 2217 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2218 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset); 2219 Alignment = std::min(Alignment, 4u); 2220 2221 // Load the value out, extending it from f32 to the destination float type. 2222 // FIXME: Avoid the extend by constructing the right constant pool? 2223 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(), 2224 FudgePtr, NULL, 0, MVT::f32, 2225 false, Alignment); 2226 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge); 2227 } 2228 2229 // Otherwise, use a libcall. 2230 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2231 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2232 "Don't know how to expand this UINT_TO_FP!"); 2233 return MakeLibCall(LC, DstVT, &Op, 1, true); 2234} 2235