LegalizeIntegerTypes.cpp revision 71da6755c8b0a7444be5531798556c00f4dad101
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22#include "llvm/IR/DerivedTypes.h" 23#include "llvm/Support/ErrorHandling.h" 24#include "llvm/Support/raw_ostream.h" 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28// Integer Result Promotion 29//===----------------------------------------------------------------------===// 30 31/// PromoteIntegerResult - This method is called when a result of a node is 32/// found to be in need of promotion to a larger type. At this point, the node 33/// may also have invalid operands or may have other results that need 34/// expansion, we just know that (at least) one result needs promotion. 35void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n"); 37 SDValue Res = SDValue(); 38 39 // See if the target wants to custom expand this node. 40 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 41 return; 42 43 switch (N->getOpcode()) { 44 default: 45#ifndef NDEBUG 46 dbgs() << "PromoteIntegerResult #" << ResNo << ": "; 47 N->dump(&DAG); dbgs() << "\n"; 48#endif 49 llvm_unreachable("Do not know how to promote this operator!"); 50 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; 51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; 54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 57 case ISD::CONVERT_RNDSAT: 58 Res = PromoteIntRes_CONVERT_RNDSAT(N); break; 59 case ISD::CTLZ_ZERO_UNDEF: 60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; 61 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break; 62 case ISD::CTTZ_ZERO_UNDEF: 63 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; 64 case ISD::EXTRACT_VECTOR_ELT: 65 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 66 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 67 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break; 68 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break; 69 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; 70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 71 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 72 case ISD::SIGN_EXTEND_INREG: 73 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 75 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 76 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; 77 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; 78 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; 79 80 case ISD::EXTRACT_SUBVECTOR: 81 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break; 82 case ISD::VECTOR_SHUFFLE: 83 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break; 84 case ISD::INSERT_VECTOR_ELT: 85 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break; 86 case ISD::BUILD_VECTOR: 87 Res = PromoteIntRes_BUILD_VECTOR(N); break; 88 case ISD::SCALAR_TO_VECTOR: 89 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break; 90 case ISD::CONCAT_VECTORS: 91 Res = PromoteIntRes_CONCAT_VECTORS(N); break; 92 93 case ISD::SIGN_EXTEND: 94 case ISD::ZERO_EXTEND: 95 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; 96 97 case ISD::FP_TO_SINT: 98 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; 99 100 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break; 101 102 case ISD::AND: 103 case ISD::OR: 104 case ISD::XOR: 105 case ISD::ADD: 106 case ISD::SUB: 107 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break; 108 109 case ISD::SDIV: 110 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; 111 112 case ISD::UDIV: 113 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break; 114 115 case ISD::SADDO: 116 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; 117 case ISD::UADDO: 118 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; 119 case ISD::SMULO: 120 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; 121 122 case ISD::ATOMIC_LOAD: 123 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break; 124 125 case ISD::ATOMIC_LOAD_ADD: 126 case ISD::ATOMIC_LOAD_SUB: 127 case ISD::ATOMIC_LOAD_AND: 128 case ISD::ATOMIC_LOAD_OR: 129 case ISD::ATOMIC_LOAD_XOR: 130 case ISD::ATOMIC_LOAD_NAND: 131 case ISD::ATOMIC_LOAD_MIN: 132 case ISD::ATOMIC_LOAD_MAX: 133 case ISD::ATOMIC_LOAD_UMIN: 134 case ISD::ATOMIC_LOAD_UMAX: 135 case ISD::ATOMIC_SWAP: 136 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 137 138 case ISD::ATOMIC_CMP_SWAP: 139 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 140 } 141 142 // If the result is null then the sub-method took care of registering it. 143 if (Res.getNode()) 144 SetPromotedInteger(SDValue(N, ResNo), Res); 145} 146 147SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N, 148 unsigned ResNo) { 149 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); 150 return GetPromotedInteger(Op); 151} 152 153SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 154 // Sign-extend the new bits, and continue the assertion. 155 SDValue Op = SExtPromotedInteger(N->getOperand(0)); 156 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), 157 Op.getValueType(), Op, N->getOperand(1)); 158} 159 160SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 161 // Zero the new bits, and continue the assertion. 162 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 163 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), 164 Op.getValueType(), Op, N->getOperand(1)); 165} 166 167SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) { 168 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 169 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 170 N->getMemoryVT(), ResVT, 171 N->getChain(), N->getBasePtr(), 172 N->getMemOperand(), N->getOrdering(), 173 N->getSynchScope()); 174 // Legalized the chain result - switch anything that used the old chain to 175 // use the new one. 176 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 177 return Res; 178} 179 180SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 181 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 182 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 183 N->getMemoryVT(), 184 N->getChain(), N->getBasePtr(), 185 Op2, N->getMemOperand(), N->getOrdering(), 186 N->getSynchScope()); 187 // Legalized the chain result - switch anything that used the old chain to 188 // use the new one. 189 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 190 return Res; 191} 192 193SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 194 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 195 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 196 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 197 N->getMemoryVT(), N->getChain(), N->getBasePtr(), 198 Op2, Op3, N->getMemOperand(), N->getOrdering(), 199 N->getSynchScope()); 200 // Legalized the chain result - switch anything that used the old chain to 201 // use the new one. 202 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 203 return Res; 204} 205 206SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) { 207 SDValue InOp = N->getOperand(0); 208 EVT InVT = InOp.getValueType(); 209 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); 210 EVT OutVT = N->getValueType(0); 211 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 212 DebugLoc dl = N->getDebugLoc(); 213 214 switch (getTypeAction(InVT)) { 215 case TargetLowering::TypeLegal: 216 break; 217 case TargetLowering::TypePromoteInteger: 218 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector()) 219 // The input promotes to the same size. Convert the promoted value. 220 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); 221 break; 222 case TargetLowering::TypeSoftenFloat: 223 // Promote the integer operand by hand. 224 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); 225 case TargetLowering::TypeExpandInteger: 226 case TargetLowering::TypeExpandFloat: 227 break; 228 case TargetLowering::TypeScalarizeVector: 229 // Convert the element to an integer and promote it by hand. 230 if (!NOutVT.isVector()) 231 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 232 BitConvertToInteger(GetScalarizedVector(InOp))); 233 break; 234 case TargetLowering::TypeSplitVector: { 235 // For example, i32 = BITCAST v2i16 on alpha. Convert the split 236 // pieces of the input into integers and reassemble in the final type. 237 SDValue Lo, Hi; 238 GetSplitVector(N->getOperand(0), Lo, Hi); 239 Lo = BitConvertToInteger(Lo); 240 Hi = BitConvertToInteger(Hi); 241 242 if (TLI.isBigEndian()) 243 std::swap(Lo, Hi); 244 245 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, 246 EVT::getIntegerVT(*DAG.getContext(), 247 NOutVT.getSizeInBits()), 248 JoinIntegers(Lo, Hi)); 249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); 250 } 251 case TargetLowering::TypeWidenVector: 252 // The input is widened to the same size. Convert to the widened value. 253 // Make sure that the outgoing value is not a vector, because this would 254 // make us bitcast between two vectors which are legalized in different ways. 255 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector()) 256 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp)); 257 } 258 259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 260 CreateStackStoreLoad(InOp, OutVT)); 261} 262 263SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 264 SDValue Op = GetPromotedInteger(N->getOperand(0)); 265 EVT OVT = N->getValueType(0); 266 EVT NVT = Op.getValueType(); 267 DebugLoc dl = N->getDebugLoc(); 268 269 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 271 DAG.getConstant(DiffBits, TLI.getPointerTy())); 272} 273 274SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 275 // The pair element type may be legal, or may not promote to the same type as 276 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 277 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), 278 TLI.getTypeToTransformTo(*DAG.getContext(), 279 N->getValueType(0)), JoinIntegers(N->getOperand(0), 280 N->getOperand(1))); 281} 282 283SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 284 EVT VT = N->getValueType(0); 285 // FIXME there is no actual debug info here 286 DebugLoc dl = N->getDebugLoc(); 287 // Zero extend things like i1, sign extend everything else. It shouldn't 288 // matter in theory which one we pick, but this tends to give better code? 289 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 290 SDValue Result = DAG.getNode(Opc, dl, 291 TLI.getTypeToTransformTo(*DAG.getContext(), VT), 292 SDValue(N, 0)); 293 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 294 return Result; 295} 296 297SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 298 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 299 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 300 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 301 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 302 "can only promote integers"); 303 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 304 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0), 305 N->getOperand(1), N->getOperand(2), 306 N->getOperand(3), N->getOperand(4), CvtCode); 307} 308 309SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 310 // Zero extend to the promoted type and do the count there. 311 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 312 DebugLoc dl = N->getDebugLoc(); 313 EVT OVT = N->getValueType(0); 314 EVT NVT = Op.getValueType(); 315 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op); 316 // Subtract off the extra leading bits in the bigger type. 317 return DAG.getNode(ISD::SUB, dl, NVT, Op, 318 DAG.getConstant(NVT.getSizeInBits() - 319 OVT.getSizeInBits(), NVT)); 320} 321 322SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 323 // Zero extend to the promoted type and do the count there. 324 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 325 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op); 326} 327 328SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 329 SDValue Op = GetPromotedInteger(N->getOperand(0)); 330 EVT OVT = N->getValueType(0); 331 EVT NVT = Op.getValueType(); 332 DebugLoc dl = N->getDebugLoc(); 333 if (N->getOpcode() == ISD::CTTZ) { 334 // The count is the same in the promoted type except if the original 335 // value was zero. This can be handled by setting the bit just off 336 // the top of the original type. 337 APInt TopBit(NVT.getSizeInBits(), 0); 338 TopBit.setBit(OVT.getSizeInBits()); 339 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT)); 340 } 341 return DAG.getNode(N->getOpcode(), dl, NVT, Op); 342} 343 344SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 345 DebugLoc dl = N->getDebugLoc(); 346 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 347 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0), 348 N->getOperand(1)); 349} 350 351SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 352 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 353 unsigned NewOpc = N->getOpcode(); 354 DebugLoc dl = N->getDebugLoc(); 355 356 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is 357 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT 358 // and SINT conversions are Custom, there is no way to tell which is 359 // preferable. We choose SINT because that's the right thing on PPC.) 360 if (N->getOpcode() == ISD::FP_TO_UINT && 361 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 362 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) 363 NewOpc = ISD::FP_TO_SINT; 364 365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); 366 367 // Assert that the converted value fits in the original type. If it doesn't 368 // (eg: because the value being converted is too big), then the result of the 369 // original operation was undefined anyway, so the assert is still correct. 370 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 371 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, 372 DAG.getValueType(N->getValueType(0).getScalarType())); 373} 374 375SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) { 376 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 377 DebugLoc dl = N->getDebugLoc(); 378 379 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 380 381 return DAG.getNode(ISD::AssertZext, dl, 382 NVT, Res, DAG.getValueType(N->getValueType(0))); 383} 384 385SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 386 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 387 DebugLoc dl = N->getDebugLoc(); 388 389 if (getTypeAction(N->getOperand(0).getValueType()) 390 == TargetLowering::TypePromoteInteger) { 391 SDValue Res = GetPromotedInteger(N->getOperand(0)); 392 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 393 394 // If the result and operand types are the same after promotion, simplify 395 // to an in-register extension. 396 if (NVT == Res.getValueType()) { 397 // The high bits are not guaranteed to be anything. Insert an extend. 398 if (N->getOpcode() == ISD::SIGN_EXTEND) 399 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 400 DAG.getValueType(N->getOperand(0).getValueType())); 401 if (N->getOpcode() == ISD::ZERO_EXTEND) 402 return DAG.getZeroExtendInReg(Res, dl, 403 N->getOperand(0).getValueType().getScalarType()); 404 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 405 return Res; 406 } 407 } 408 409 // Otherwise, just extend the original operand all the way to the larger type. 410 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 411} 412 413SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 414 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 415 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 416 ISD::LoadExtType ExtType = 417 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 418 DebugLoc dl = N->getDebugLoc(); 419 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), 420 N->getPointerInfo(), 421 N->getMemoryVT(), N->isVolatile(), 422 N->isNonTemporal(), N->getAlignment()); 423 424 // Legalized the chain result - switch anything that used the old chain to 425 // use the new one. 426 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 427 return Res; 428} 429 430/// Promote the overflow flag of an overflowing arithmetic node. 431SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { 432 // Simply change the return type of the boolean result. 433 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1)); 434 EVT ValueVTs[] = { N->getValueType(0), NVT }; 435 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; 436 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), 437 DAG.getVTList(ValueVTs, 2), Ops, 2); 438 439 // Modified the sum result - switch anything that used the old sum to use 440 // the new one. 441 ReplaceValueWith(SDValue(N, 0), Res); 442 443 return SDValue(Res.getNode(), 1); 444} 445 446SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { 447 if (ResNo == 1) 448 return PromoteIntRes_Overflow(N); 449 450 // The operation overflowed iff the result in the larger type is not the 451 // sign extension of its truncation to the original type. 452 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 453 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 454 EVT OVT = N->getOperand(0).getValueType(); 455 EVT NVT = LHS.getValueType(); 456 DebugLoc dl = N->getDebugLoc(); 457 458 // Do the arithmetic in the larger type. 459 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 460 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 461 462 // Calculate the overflow flag: sign extend the arithmetic result from 463 // the original type. 464 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 465 DAG.getValueType(OVT)); 466 // Overflowed if and only if this is not equal to Res. 467 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 468 469 // Use the calculated overflow everywhere. 470 ReplaceValueWith(SDValue(N, 1), Ofl); 471 472 return Res; 473} 474 475SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 476 // Sign extend the input. 477 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 478 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 479 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 480 LHS.getValueType(), LHS, RHS); 481} 482 483SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 484 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 485 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 486 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 487 LHS.getValueType(), N->getOperand(0),LHS,RHS); 488} 489 490SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) { 491 SDValue Mask = N->getOperand(0); 492 EVT OpTy = N->getOperand(1).getValueType(); 493 494 // Promote all the way up to the canonical SetCC type. 495 Mask = PromoteTargetBoolean(Mask, TLI.getSetCCResultType(OpTy)); 496 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 497 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 498 return DAG.getNode(ISD::VSELECT, N->getDebugLoc(), 499 LHS.getValueType(), Mask, LHS, RHS); 500} 501 502SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 503 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 504 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 505 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 506 LHS.getValueType(), N->getOperand(0), 507 N->getOperand(1), LHS, RHS, N->getOperand(4)); 508} 509 510SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 511 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); 512 513 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 514 515 // Only use the result of getSetCCResultType if it is legal, 516 // otherwise just use the promoted result type (NVT). 517 if (!TLI.isTypeLegal(SVT)) 518 SVT = NVT; 519 520 DebugLoc dl = N->getDebugLoc(); 521 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() && 522 "Vector compare must return a vector result!"); 523 524 SDValue LHS = N->getOperand(0); 525 SDValue RHS = N->getOperand(1); 526 if (LHS.getValueType() != RHS.getValueType()) { 527 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger && 528 !LHS.getValueType().isVector()) 529 LHS = GetPromotedInteger(LHS); 530 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger && 531 !RHS.getValueType().isVector()) 532 RHS = GetPromotedInteger(RHS); 533 } 534 535 // Get the SETCC result using the canonical SETCC type. 536 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS, 537 N->getOperand(2)); 538 539 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 540 // Convert to the expected type. 541 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 542} 543 544SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 545 SDValue Res = GetPromotedInteger(N->getOperand(0)); 546 SDValue Amt = N->getOperand(1); 547 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt; 548 return DAG.getNode(ISD::SHL, N->getDebugLoc(), Res.getValueType(), Res, Amt); 549} 550 551SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 552 SDValue Op = GetPromotedInteger(N->getOperand(0)); 553 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), 554 Op.getValueType(), Op, N->getOperand(1)); 555} 556 557SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 558 // The input may have strange things in the top bits of the registers, but 559 // these operations don't care. They may have weird bits going out, but 560 // that too is okay if they are integer operations. 561 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 562 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 563 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 564 LHS.getValueType(), LHS, RHS); 565} 566 567SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 568 // The input value must be properly sign extended. 569 SDValue Res = SExtPromotedInteger(N->getOperand(0)); 570 SDValue Amt = N->getOperand(1); 571 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt; 572 return DAG.getNode(ISD::SRA, N->getDebugLoc(), Res.getValueType(), Res, Amt); 573} 574 575SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 576 // The input value must be properly zero extended. 577 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 578 SDValue Amt = N->getOperand(1); 579 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt; 580 return DAG.getNode(ISD::SRL, N->getDebugLoc(), Res.getValueType(), Res, Amt); 581} 582 583SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 584 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 585 SDValue Res; 586 SDValue InOp = N->getOperand(0); 587 DebugLoc dl = N->getDebugLoc(); 588 589 switch (getTypeAction(InOp.getValueType())) { 590 default: llvm_unreachable("Unknown type action!"); 591 case TargetLowering::TypeLegal: 592 case TargetLowering::TypeExpandInteger: 593 Res = InOp; 594 break; 595 case TargetLowering::TypePromoteInteger: 596 Res = GetPromotedInteger(InOp); 597 break; 598 case TargetLowering::TypeSplitVector: 599 EVT InVT = InOp.getValueType(); 600 assert(InVT.isVector() && "Cannot split scalar types"); 601 unsigned NumElts = InVT.getVectorNumElements(); 602 assert(NumElts == NVT.getVectorNumElements() && 603 "Dst and Src must have the same number of elements"); 604 assert(isPowerOf2_32(NumElts) && 605 "Promoted vector type must be a power of two"); 606 607 SDValue EOp1, EOp2; 608 GetSplitVector(InOp, EOp1, EOp2); 609 610 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(), 611 NumElts/2); 612 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1); 613 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2); 614 615 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); 616 } 617 618 // Truncate to NVT instead of VT 619 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res); 620} 621 622SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { 623 if (ResNo == 1) 624 return PromoteIntRes_Overflow(N); 625 626 // The operation overflowed iff the result in the larger type is not the 627 // zero extension of its truncation to the original type. 628 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 629 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 630 EVT OVT = N->getOperand(0).getValueType(); 631 EVT NVT = LHS.getValueType(); 632 DebugLoc dl = N->getDebugLoc(); 633 634 // Do the arithmetic in the larger type. 635 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 636 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 637 638 // Calculate the overflow flag: zero extend the arithmetic result from 639 // the original type. 640 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); 641 // Overflowed if and only if this is not equal to Res. 642 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 643 644 // Use the calculated overflow everywhere. 645 ReplaceValueWith(SDValue(N, 1), Ofl); 646 647 return Res; 648} 649 650SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) { 651 // Promote the overflow bit trivially. 652 if (ResNo == 1) 653 return PromoteIntRes_Overflow(N); 654 655 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1); 656 DebugLoc DL = N->getDebugLoc(); 657 EVT SmallVT = LHS.getValueType(); 658 659 // To determine if the result overflowed in a larger type, we extend the 660 // input to the larger type, do the multiply (checking if it overflows), 661 // then also check the high bits of the result to see if overflow happened 662 // there. 663 if (N->getOpcode() == ISD::SMULO) { 664 LHS = SExtPromotedInteger(LHS); 665 RHS = SExtPromotedInteger(RHS); 666 } else { 667 LHS = ZExtPromotedInteger(LHS); 668 RHS = ZExtPromotedInteger(RHS); 669 } 670 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1)); 671 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS); 672 673 // Overflow occurred if it occurred in the larger type, or if the high part 674 // of the result does not zero/sign-extend the low part. Check this second 675 // possibility first. 676 SDValue Overflow; 677 if (N->getOpcode() == ISD::UMULO) { 678 // Unsigned overflow occurred if the high part is non-zero. 679 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, 680 DAG.getIntPtrConstant(SmallVT.getSizeInBits())); 681 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi, 682 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE); 683 } else { 684 // Signed overflow occurred if the high part does not sign extend the low. 685 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), 686 Mul, DAG.getValueType(SmallVT)); 687 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE); 688 } 689 690 // The only other way for overflow to occur is if the multiplication in the 691 // larger type itself overflowed. 692 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow, 693 SDValue(Mul.getNode(), 1)); 694 695 // Use the calculated overflow everywhere. 696 ReplaceValueWith(SDValue(N, 1), Overflow); 697 return Mul; 698} 699 700SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 701 // Zero extend the input. 702 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 703 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 704 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 705 LHS.getValueType(), LHS, RHS); 706} 707 708SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 709 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(), 710 N->getValueType(0))); 711} 712 713SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 714 SDValue Chain = N->getOperand(0); // Get the chain. 715 SDValue Ptr = N->getOperand(1); // Get the pointer. 716 EVT VT = N->getValueType(0); 717 DebugLoc dl = N->getDebugLoc(); 718 719 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); 720 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT); 721 // The argument is passed as NumRegs registers of type RegVT. 722 723 SmallVector<SDValue, 8> Parts(NumRegs); 724 for (unsigned i = 0; i < NumRegs; ++i) { 725 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), 726 N->getConstantOperandVal(3)); 727 Chain = Parts[i].getValue(1); 728 } 729 730 // Handle endianness of the load. 731 if (TLI.isBigEndian()) 732 std::reverse(Parts.begin(), Parts.end()); 733 734 // Assemble the parts in the promoted type. 735 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 736 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); 737 for (unsigned i = 1; i < NumRegs; ++i) { 738 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); 739 // Shift it to the right position and "or" it in. 740 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, 741 DAG.getConstant(i * RegVT.getSizeInBits(), 742 TLI.getPointerTy())); 743 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); 744 } 745 746 // Modified the chain result - switch anything that used the old chain to 747 // use the new one. 748 ReplaceValueWith(SDValue(N, 1), Chain); 749 750 return Res; 751} 752 753//===----------------------------------------------------------------------===// 754// Integer Operand Promotion 755//===----------------------------------------------------------------------===// 756 757/// PromoteIntegerOperand - This method is called when the specified operand of 758/// the specified node is found to need promotion. At this point, all of the 759/// result types of the node are known to be legal, but other operands of the 760/// node may need promotion or expansion as well as the specified one. 761bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 762 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n"); 763 SDValue Res = SDValue(); 764 765 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 766 return false; 767 768 switch (N->getOpcode()) { 769 default: 770 #ifndef NDEBUG 771 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": "; 772 N->dump(&DAG); dbgs() << "\n"; 773 #endif 774 llvm_unreachable("Do not know how to promote this operator's operand!"); 775 776 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 777 case ISD::ATOMIC_STORE: 778 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N)); 779 break; 780 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break; 781 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 782 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 783 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 784 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 785 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; 786 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break; 787 case ISD::CONVERT_RNDSAT: 788 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 789 case ISD::INSERT_VECTOR_ELT: 790 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 791 case ISD::SCALAR_TO_VECTOR: 792 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break; 793 case ISD::VSELECT: 794 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 795 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 796 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 797 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 798 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 799 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 800 OpNo); break; 801 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 802 case ISD::FP16_TO_FP32: 803 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; 804 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 805 806 case ISD::SHL: 807 case ISD::SRA: 808 case ISD::SRL: 809 case ISD::ROTL: 810 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; 811 } 812 813 // If the result is null, the sub-method took care of registering results etc. 814 if (!Res.getNode()) return false; 815 816 // If the result is N, the sub-method updated N in place. Tell the legalizer 817 // core about this. 818 if (Res.getNode() == N) 819 return true; 820 821 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 822 "Invalid operand expansion"); 823 824 ReplaceValueWith(SDValue(N, 0), Res); 825 return false; 826} 827 828/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 829/// shared among BR_CC, SELECT_CC, and SETCC handlers. 830void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 831 ISD::CondCode CCCode) { 832 // We have to insert explicit sign or zero extends. Note that we could 833 // insert sign extends for ALL conditions, but zero extend is cheaper on 834 // many machines (an AND instead of two shifts), so prefer it. 835 switch (CCCode) { 836 default: llvm_unreachable("Unknown integer comparison!"); 837 case ISD::SETEQ: 838 case ISD::SETNE: 839 case ISD::SETUGE: 840 case ISD::SETUGT: 841 case ISD::SETULE: 842 case ISD::SETULT: 843 // ALL of these operations will work if we either sign or zero extend 844 // the operands (including the unsigned comparisons!). Zero extend is 845 // usually a simpler/cheaper operation, so prefer it. 846 NewLHS = ZExtPromotedInteger(NewLHS); 847 NewRHS = ZExtPromotedInteger(NewRHS); 848 break; 849 case ISD::SETGE: 850 case ISD::SETGT: 851 case ISD::SETLT: 852 case ISD::SETLE: 853 NewLHS = SExtPromotedInteger(NewLHS); 854 NewRHS = SExtPromotedInteger(NewRHS); 855 break; 856 } 857} 858 859SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 860 SDValue Op = GetPromotedInteger(N->getOperand(0)); 861 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); 862} 863 864SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) { 865 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 866 return DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), N->getMemoryVT(), 867 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(), 868 N->getOrdering(), N->getSynchScope()); 869} 870 871SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) { 872 // This should only occur in unusual situations like bitcasting to an 873 // x86_fp80, so just turn it into a store+load 874 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0)); 875} 876 877SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 878 assert(OpNo == 2 && "Don't know how to promote this operand!"); 879 880 SDValue LHS = N->getOperand(2); 881 SDValue RHS = N->getOperand(3); 882 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 883 884 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 885 // legal types. 886 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 887 N->getOperand(1), LHS, RHS, N->getOperand(4)), 888 0); 889} 890 891SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 892 assert(OpNo == 1 && "only know how to promote condition"); 893 894 // Promote all the way up to the canonical SetCC type. 895 EVT SVT = TLI.getSetCCResultType(MVT::Other); 896 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT); 897 898 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 899 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond, 900 N->getOperand(2)), 0); 901} 902 903SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 904 // Since the result type is legal, the operands must promote to it. 905 EVT OVT = N->getOperand(0).getValueType(); 906 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); 907 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 908 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 909 DebugLoc dl = N->getDebugLoc(); 910 911 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, 912 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy())); 913 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); 914} 915 916SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 917 // The vector type is legal but the element type is not. This implies 918 // that the vector is a power-of-two in length and that the element 919 // type does not have a strange size (eg: it is not i1). 920 EVT VecVT = N->getValueType(0); 921 unsigned NumElts = VecVT.getVectorNumElements(); 922 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 923 924 // Promote the inserted value. The type does not need to match the 925 // vector element type. Check that any extra bits introduced will be 926 // truncated away. 927 assert(N->getOperand(0).getValueType().getSizeInBits() >= 928 N->getValueType(0).getVectorElementType().getSizeInBits() && 929 "Type of inserted value narrower than vector element type!"); 930 931 SmallVector<SDValue, 16> NewOps; 932 for (unsigned i = 0; i < NumElts; ++i) 933 NewOps.push_back(GetPromotedInteger(N->getOperand(i))); 934 935 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0); 936} 937 938SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 939 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 940 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 941 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 942 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 943 "can only promote integer arguments"); 944 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 945 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp, 946 N->getOperand(1), N->getOperand(2), 947 N->getOperand(3), N->getOperand(4), CvtCode); 948} 949 950SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 951 unsigned OpNo) { 952 if (OpNo == 1) { 953 // Promote the inserted value. This is valid because the type does not 954 // have to match the vector element type. 955 956 // Check that any extra bits introduced will be truncated away. 957 assert(N->getOperand(1).getValueType().getSizeInBits() >= 958 N->getValueType(0).getVectorElementType().getSizeInBits() && 959 "Type of inserted value narrower than vector element type!"); 960 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 961 GetPromotedInteger(N->getOperand(1)), 962 N->getOperand(2)), 963 0); 964 } 965 966 assert(OpNo == 2 && "Different operand and result vector types?"); 967 968 // Promote the index. 969 SDValue Idx = ZExtPromotedInteger(N->getOperand(2)); 970 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 971 N->getOperand(1), Idx), 0); 972} 973 974SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) { 975 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote 976 // the operand in place. 977 return SDValue(DAG.UpdateNodeOperands(N, 978 GetPromotedInteger(N->getOperand(0))), 0); 979} 980 981SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 982 assert(OpNo == 0 && "Only know how to promote the condition!"); 983 SDValue Cond = N->getOperand(0); 984 EVT OpTy = N->getOperand(1).getValueType(); 985 986 // Promote all the way up to the canonical SetCC type. 987 EVT SVT = TLI.getSetCCResultType(N->getOpcode() == ISD::SELECT ? 988 OpTy.getScalarType() : OpTy); 989 Cond = PromoteTargetBoolean(Cond, SVT); 990 991 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1), 992 N->getOperand(2)), 0); 993} 994 995SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 996 assert(OpNo == 0 && "Don't know how to promote this operand!"); 997 998 SDValue LHS = N->getOperand(0); 999 SDValue RHS = N->getOperand(1); 1000 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 1001 1002 // The CC (#4) and the possible return values (#2 and #3) have legal types. 1003 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2), 1004 N->getOperand(3), N->getOperand(4)), 0); 1005} 1006 1007SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 1008 assert(OpNo == 0 && "Don't know how to promote this operand!"); 1009 1010 SDValue LHS = N->getOperand(0); 1011 SDValue RHS = N->getOperand(1); 1012 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 1013 1014 // The CC (#2) is always legal. 1015 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0); 1016} 1017 1018SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) { 1019 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 1020 ZExtPromotedInteger(N->getOperand(1))), 0); 1021} 1022 1023SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 1024 SDValue Op = GetPromotedInteger(N->getOperand(0)); 1025 DebugLoc dl = N->getDebugLoc(); 1026 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 1027 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), 1028 Op, DAG.getValueType(N->getOperand(0).getValueType())); 1029} 1030 1031SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { 1032 return SDValue(DAG.UpdateNodeOperands(N, 1033 SExtPromotedInteger(N->getOperand(0))), 0); 1034} 1035 1036SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 1037 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 1038 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 1039 unsigned Alignment = N->getAlignment(); 1040 bool isVolatile = N->isVolatile(); 1041 bool isNonTemporal = N->isNonTemporal(); 1042 DebugLoc dl = N->getDebugLoc(); 1043 1044 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 1045 1046 // Truncate the value and store the result. 1047 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(), 1048 N->getMemoryVT(), 1049 isVolatile, isNonTemporal, Alignment); 1050} 1051 1052SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 1053 SDValue Op = GetPromotedInteger(N->getOperand(0)); 1054 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op); 1055} 1056 1057SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { 1058 return SDValue(DAG.UpdateNodeOperands(N, 1059 ZExtPromotedInteger(N->getOperand(0))), 0); 1060} 1061 1062SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 1063 DebugLoc dl = N->getDebugLoc(); 1064 SDValue Op = GetPromotedInteger(N->getOperand(0)); 1065 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 1066 return DAG.getZeroExtendInReg(Op, dl, 1067 N->getOperand(0).getValueType().getScalarType()); 1068} 1069 1070 1071//===----------------------------------------------------------------------===// 1072// Integer Result Expansion 1073//===----------------------------------------------------------------------===// 1074 1075/// ExpandIntegerResult - This method is called when the specified result of the 1076/// specified node is found to need expansion. At this point, the node may also 1077/// have invalid operands or may have other results that need promotion, we just 1078/// know that (at least) one result needs expansion. 1079void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 1080 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n"); 1081 SDValue Lo, Hi; 1082 Lo = Hi = SDValue(); 1083 1084 // See if the target wants to custom expand this node. 1085 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 1086 return; 1087 1088 switch (N->getOpcode()) { 1089 default: 1090#ifndef NDEBUG 1091 dbgs() << "ExpandIntegerResult #" << ResNo << ": "; 1092 N->dump(&DAG); dbgs() << "\n"; 1093#endif 1094 llvm_unreachable("Do not know how to expand the result of this operator!"); 1095 1096 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; 1097 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 1098 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 1099 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 1100 1101 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break; 1102 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 1103 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 1104 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 1105 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 1106 1107 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 1108 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 1109 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 1110 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 1111 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 1112 case ISD::CTLZ_ZERO_UNDEF: 1113 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 1114 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 1115 case ISD::CTTZ_ZERO_UNDEF: 1116 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 1117 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 1118 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 1119 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 1120 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 1121 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 1122 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 1123 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 1124 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 1125 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 1126 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 1127 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 1128 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 1129 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break; 1130 1131 case ISD::ATOMIC_LOAD_ADD: 1132 case ISD::ATOMIC_LOAD_SUB: 1133 case ISD::ATOMIC_LOAD_AND: 1134 case ISD::ATOMIC_LOAD_OR: 1135 case ISD::ATOMIC_LOAD_XOR: 1136 case ISD::ATOMIC_LOAD_NAND: 1137 case ISD::ATOMIC_LOAD_MIN: 1138 case ISD::ATOMIC_LOAD_MAX: 1139 case ISD::ATOMIC_LOAD_UMIN: 1140 case ISD::ATOMIC_LOAD_UMAX: 1141 case ISD::ATOMIC_SWAP: { 1142 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N); 1143 SplitInteger(Tmp.first, Lo, Hi); 1144 ReplaceValueWith(SDValue(N, 1), Tmp.second); 1145 break; 1146 } 1147 1148 case ISD::AND: 1149 case ISD::OR: 1150 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 1151 1152 case ISD::ADD: 1153 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1154 1155 case ISD::ADDC: 1156 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1157 1158 case ISD::ADDE: 1159 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1160 1161 case ISD::SHL: 1162 case ISD::SRA: 1163 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1164 1165 case ISD::SADDO: 1166 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break; 1167 case ISD::UADDO: 1168 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break; 1169 case ISD::UMULO: 1170 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; 1171 } 1172 1173 // If Lo/Hi is null, the sub-method took care of registering results etc. 1174 if (Lo.getNode()) 1175 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1176} 1177 1178/// Lower an atomic node to the appropriate builtin call. 1179std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) { 1180 unsigned Opc = Node->getOpcode(); 1181 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 1182 RTLIB::Libcall LC; 1183 1184 switch (Opc) { 1185 default: 1186 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 1187 case ISD::ATOMIC_SWAP: 1188 switch (VT.SimpleTy) { 1189 default: llvm_unreachable("Unexpected value type for atomic!"); 1190 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 1191 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 1192 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 1193 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 1194 } 1195 break; 1196 case ISD::ATOMIC_CMP_SWAP: 1197 switch (VT.SimpleTy) { 1198 default: llvm_unreachable("Unexpected value type for atomic!"); 1199 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 1200 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 1201 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 1202 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 1203 } 1204 break; 1205 case ISD::ATOMIC_LOAD_ADD: 1206 switch (VT.SimpleTy) { 1207 default: llvm_unreachable("Unexpected value type for atomic!"); 1208 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 1209 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 1210 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 1211 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 1212 } 1213 break; 1214 case ISD::ATOMIC_LOAD_SUB: 1215 switch (VT.SimpleTy) { 1216 default: llvm_unreachable("Unexpected value type for atomic!"); 1217 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 1218 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 1219 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 1220 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 1221 } 1222 break; 1223 case ISD::ATOMIC_LOAD_AND: 1224 switch (VT.SimpleTy) { 1225 default: llvm_unreachable("Unexpected value type for atomic!"); 1226 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 1227 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 1228 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 1229 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 1230 } 1231 break; 1232 case ISD::ATOMIC_LOAD_OR: 1233 switch (VT.SimpleTy) { 1234 default: llvm_unreachable("Unexpected value type for atomic!"); 1235 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 1236 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 1237 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 1238 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 1239 } 1240 break; 1241 case ISD::ATOMIC_LOAD_XOR: 1242 switch (VT.SimpleTy) { 1243 default: llvm_unreachable("Unexpected value type for atomic!"); 1244 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 1245 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 1246 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 1247 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 1248 } 1249 break; 1250 case ISD::ATOMIC_LOAD_NAND: 1251 switch (VT.SimpleTy) { 1252 default: llvm_unreachable("Unexpected value type for atomic!"); 1253 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 1254 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 1255 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 1256 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 1257 } 1258 break; 1259 } 1260 1261 return ExpandChainLibCall(LC, Node, false); 1262} 1263 1264/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1265/// and the shift amount is a constant 'Amt'. Expand the operation. 1266void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1267 SDValue &Lo, SDValue &Hi) { 1268 DebugLoc DL = N->getDebugLoc(); 1269 // Expand the incoming operand to be shifted, so that we have its parts 1270 SDValue InL, InH; 1271 GetExpandedInteger(N->getOperand(0), InL, InH); 1272 1273 EVT NVT = InL.getValueType(); 1274 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1275 unsigned NVTBits = NVT.getSizeInBits(); 1276 EVT ShTy = N->getOperand(1).getValueType(); 1277 1278 if (N->getOpcode() == ISD::SHL) { 1279 if (Amt > VTBits) { 1280 Lo = Hi = DAG.getConstant(0, NVT); 1281 } else if (Amt > NVTBits) { 1282 Lo = DAG.getConstant(0, NVT); 1283 Hi = DAG.getNode(ISD::SHL, DL, 1284 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy)); 1285 } else if (Amt == NVTBits) { 1286 Lo = DAG.getConstant(0, NVT); 1287 Hi = InL; 1288 } else if (Amt == 1 && 1289 TLI.isOperationLegalOrCustom(ISD::ADDC, 1290 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) { 1291 // Emit this X << 1 as X+X. 1292 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); 1293 SDValue LoOps[2] = { InL, InL }; 1294 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2); 1295 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1296 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3); 1297 } else { 1298 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1299 Hi = DAG.getNode(ISD::OR, DL, NVT, 1300 DAG.getNode(ISD::SHL, DL, NVT, InH, 1301 DAG.getConstant(Amt, ShTy)), 1302 DAG.getNode(ISD::SRL, DL, NVT, InL, 1303 DAG.getConstant(NVTBits-Amt, ShTy))); 1304 } 1305 return; 1306 } 1307 1308 if (N->getOpcode() == ISD::SRL) { 1309 if (Amt > VTBits) { 1310 Lo = DAG.getConstant(0, NVT); 1311 Hi = DAG.getConstant(0, NVT); 1312 } else if (Amt > NVTBits) { 1313 Lo = DAG.getNode(ISD::SRL, DL, 1314 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1315 Hi = DAG.getConstant(0, NVT); 1316 } else if (Amt == NVTBits) { 1317 Lo = InH; 1318 Hi = DAG.getConstant(0, NVT); 1319 } else { 1320 Lo = DAG.getNode(ISD::OR, DL, NVT, 1321 DAG.getNode(ISD::SRL, DL, NVT, InL, 1322 DAG.getConstant(Amt, ShTy)), 1323 DAG.getNode(ISD::SHL, DL, NVT, InH, 1324 DAG.getConstant(NVTBits-Amt, ShTy))); 1325 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1326 } 1327 return; 1328 } 1329 1330 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1331 if (Amt > VTBits) { 1332 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, 1333 DAG.getConstant(NVTBits-1, ShTy)); 1334 } else if (Amt > NVTBits) { 1335 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, 1336 DAG.getConstant(Amt-NVTBits, ShTy)); 1337 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, 1338 DAG.getConstant(NVTBits-1, ShTy)); 1339 } else if (Amt == NVTBits) { 1340 Lo = InH; 1341 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, 1342 DAG.getConstant(NVTBits-1, ShTy)); 1343 } else { 1344 Lo = DAG.getNode(ISD::OR, DL, NVT, 1345 DAG.getNode(ISD::SRL, DL, NVT, InL, 1346 DAG.getConstant(Amt, ShTy)), 1347 DAG.getNode(ISD::SHL, DL, NVT, InH, 1348 DAG.getConstant(NVTBits-Amt, ShTy))); 1349 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1350 } 1351} 1352 1353/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1354/// this shift based on knowledge of the high bit of the shift amount. If we 1355/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1356/// shift amount. 1357bool DAGTypeLegalizer:: 1358ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1359 SDValue Amt = N->getOperand(1); 1360 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1361 EVT ShTy = Amt.getValueType(); 1362 unsigned ShBits = ShTy.getScalarType().getSizeInBits(); 1363 unsigned NVTBits = NVT.getScalarType().getSizeInBits(); 1364 assert(isPowerOf2_32(NVTBits) && 1365 "Expanded integer type size not a power of two!"); 1366 DebugLoc dl = N->getDebugLoc(); 1367 1368 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1369 APInt KnownZero, KnownOne; 1370 DAG.ComputeMaskedBits(N->getOperand(1), KnownZero, KnownOne); 1371 1372 // If we don't know anything about the high bits, exit. 1373 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1374 return false; 1375 1376 // Get the incoming operand to be shifted. 1377 SDValue InL, InH; 1378 GetExpandedInteger(N->getOperand(0), InL, InH); 1379 1380 // If we know that any of the high bits of the shift amount are one, then we 1381 // can do this as a couple of simple shifts. 1382 if (KnownOne.intersects(HighBitMask)) { 1383 // Mask out the high bit, which we know is set. 1384 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, 1385 DAG.getConstant(~HighBitMask, ShTy)); 1386 1387 switch (N->getOpcode()) { 1388 default: llvm_unreachable("Unknown shift"); 1389 case ISD::SHL: 1390 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1391 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 1392 return true; 1393 case ISD::SRL: 1394 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1395 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 1396 return true; 1397 case ISD::SRA: 1398 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 1399 DAG.getConstant(NVTBits-1, ShTy)); 1400 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 1401 return true; 1402 } 1403 } 1404 1405 // If we know that all of the high bits of the shift amount are zero, then we 1406 // can do this as a couple of simple shifts. 1407 if ((KnownZero & HighBitMask) == HighBitMask) { 1408 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined 1409 // shift if x is zero. We can use XOR here because x is known to be smaller 1410 // than 32. 1411 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt, 1412 DAG.getConstant(NVTBits-1, ShTy)); 1413 1414 unsigned Op1, Op2; 1415 switch (N->getOpcode()) { 1416 default: llvm_unreachable("Unknown shift"); 1417 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1418 case ISD::SRL: 1419 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1420 } 1421 1422 // When shifting right the arithmetic for Lo and Hi is swapped. 1423 if (N->getOpcode() != ISD::SHL) 1424 std::swap(InL, InH); 1425 1426 // Use a little trick to get the bits that move from Lo to Hi. First 1427 // shift by one bit. 1428 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy)); 1429 // Then compute the remaining shift with amount-1. 1430 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2); 1431 1432 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt); 1433 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2); 1434 1435 if (N->getOpcode() != ISD::SHL) 1436 std::swap(Hi, Lo); 1437 return true; 1438 } 1439 1440 return false; 1441} 1442 1443/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift 1444/// of any size. 1445bool DAGTypeLegalizer:: 1446ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1447 SDValue Amt = N->getOperand(1); 1448 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1449 EVT ShTy = Amt.getValueType(); 1450 unsigned NVTBits = NVT.getSizeInBits(); 1451 assert(isPowerOf2_32(NVTBits) && 1452 "Expanded integer type size not a power of two!"); 1453 DebugLoc dl = N->getDebugLoc(); 1454 1455 // Get the incoming operand to be shifted. 1456 SDValue InL, InH; 1457 GetExpandedInteger(N->getOperand(0), InL, InH); 1458 1459 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy); 1460 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode); 1461 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt); 1462 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy), 1463 Amt, NVBitsNode, ISD::SETULT); 1464 1465 SDValue LoS, HiS, LoL, HiL; 1466 switch (N->getOpcode()) { 1467 default: llvm_unreachable("Unknown shift"); 1468 case ISD::SHL: 1469 // Short: ShAmt < NVTBits 1470 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); 1471 HiS = DAG.getNode(ISD::OR, dl, NVT, 1472 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt), 1473 // FIXME: If Amt is zero, the following shift generates an undefined result 1474 // on some architectures. 1475 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack)); 1476 1477 // Long: ShAmt >= NVTBits 1478 LoL = DAG.getConstant(0, NVT); // Lo part is zero. 1479 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part. 1480 1481 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1482 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1483 return true; 1484 case ISD::SRL: 1485 // Short: ShAmt < NVTBits 1486 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); 1487 LoS = DAG.getNode(ISD::OR, dl, NVT, 1488 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1489 // FIXME: If Amt is zero, the following shift generates an undefined result 1490 // on some architectures. 1491 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); 1492 1493 // Long: ShAmt >= NVTBits 1494 HiL = DAG.getConstant(0, NVT); // Hi part is zero. 1495 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part. 1496 1497 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1498 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1499 return true; 1500 case ISD::SRA: 1501 // Short: ShAmt < NVTBits 1502 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); 1503 LoS = DAG.getNode(ISD::OR, dl, NVT, 1504 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1505 // FIXME: If Amt is zero, the following shift generates an undefined result 1506 // on some architectures. 1507 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); 1508 1509 // Long: ShAmt >= NVTBits 1510 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part. 1511 DAG.getConstant(NVTBits-1, ShTy)); 1512 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part. 1513 1514 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1515 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1516 return true; 1517 } 1518} 1519 1520void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1521 SDValue &Lo, SDValue &Hi) { 1522 DebugLoc dl = N->getDebugLoc(); 1523 // Expand the subcomponents. 1524 SDValue LHSL, LHSH, RHSL, RHSH; 1525 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1526 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1527 1528 EVT NVT = LHSL.getValueType(); 1529 SDValue LoOps[2] = { LHSL, RHSL }; 1530 SDValue HiOps[3] = { LHSH, RHSH }; 1531 1532 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1533 // them. TODO: Teach operation legalization how to expand unsupported 1534 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1535 // a carry of type MVT::Glue, but there doesn't seem to be any way to 1536 // generate a value of this type in the expanded code sequence. 1537 bool hasCarry = 1538 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? 1539 ISD::ADDC : ISD::SUBC, 1540 TLI.getTypeToExpandTo(*DAG.getContext(), NVT)); 1541 1542 if (hasCarry) { 1543 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); 1544 if (N->getOpcode() == ISD::ADD) { 1545 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1546 HiOps[2] = Lo.getValue(1); 1547 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1548 } else { 1549 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1550 HiOps[2] = Lo.getValue(1); 1551 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1552 } 1553 return; 1554 } 1555 1556 if (N->getOpcode() == ISD::ADD) { 1557 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); 1558 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); 1559 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0], 1560 ISD::SETULT); 1561 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, 1562 DAG.getConstant(1, NVT), 1563 DAG.getConstant(0, NVT)); 1564 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1], 1565 ISD::SETULT); 1566 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, 1567 DAG.getConstant(1, NVT), Carry1); 1568 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); 1569 } else { 1570 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 1571 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); 1572 SDValue Cmp = 1573 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()), 1574 LoOps[0], LoOps[1], ISD::SETULT); 1575 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, 1576 DAG.getConstant(1, NVT), 1577 DAG.getConstant(0, NVT)); 1578 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); 1579 } 1580} 1581 1582void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1583 SDValue &Lo, SDValue &Hi) { 1584 // Expand the subcomponents. 1585 SDValue LHSL, LHSH, RHSL, RHSH; 1586 DebugLoc dl = N->getDebugLoc(); 1587 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1588 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1589 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue); 1590 SDValue LoOps[2] = { LHSL, RHSL }; 1591 SDValue HiOps[3] = { LHSH, RHSH }; 1592 1593 if (N->getOpcode() == ISD::ADDC) { 1594 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1595 HiOps[2] = Lo.getValue(1); 1596 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1597 } else { 1598 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1599 HiOps[2] = Lo.getValue(1); 1600 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1601 } 1602 1603 // Legalized the flag result - switch anything that used the old flag to 1604 // use the new one. 1605 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1606} 1607 1608void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1609 SDValue &Lo, SDValue &Hi) { 1610 // Expand the subcomponents. 1611 SDValue LHSL, LHSH, RHSL, RHSH; 1612 DebugLoc dl = N->getDebugLoc(); 1613 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1614 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1615 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue); 1616 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1617 SDValue HiOps[3] = { LHSH, RHSH }; 1618 1619 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3); 1620 HiOps[2] = Lo.getValue(1); 1621 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); 1622 1623 // Legalized the flag result - switch anything that used the old flag to 1624 // use the new one. 1625 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1626} 1627 1628void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo, 1629 SDValue &Lo, SDValue &Hi) { 1630 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo); 1631 SplitInteger(Res, Lo, Hi); 1632} 1633 1634void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1635 SDValue &Lo, SDValue &Hi) { 1636 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1637 DebugLoc dl = N->getDebugLoc(); 1638 SDValue Op = N->getOperand(0); 1639 if (Op.getValueType().bitsLE(NVT)) { 1640 // The low part is any extension of the input (which degenerates to a copy). 1641 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); 1642 Hi = DAG.getUNDEF(NVT); // The high part is undefined. 1643 } else { 1644 // For example, extension of an i48 to an i64. The operand type necessarily 1645 // promotes to the result type, so will end up being expanded too. 1646 assert(getTypeAction(Op.getValueType()) == 1647 TargetLowering::TypePromoteInteger && 1648 "Only know how to promote this result!"); 1649 SDValue Res = GetPromotedInteger(Op); 1650 assert(Res.getValueType() == N->getValueType(0) && 1651 "Operand over promoted?"); 1652 // Split the promoted operand. This will simplify when it is expanded. 1653 SplitInteger(Res, Lo, Hi); 1654 } 1655} 1656 1657void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1658 SDValue &Lo, SDValue &Hi) { 1659 DebugLoc dl = N->getDebugLoc(); 1660 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1661 EVT NVT = Lo.getValueType(); 1662 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1663 unsigned NVTBits = NVT.getSizeInBits(); 1664 unsigned EVTBits = EVT.getSizeInBits(); 1665 1666 if (NVTBits < EVTBits) { 1667 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, 1668 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1669 EVTBits - NVTBits))); 1670 } else { 1671 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); 1672 // The high part replicates the sign bit of Lo, make it explicit. 1673 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1674 DAG.getConstant(NVTBits-1, TLI.getPointerTy())); 1675 } 1676} 1677 1678void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1679 SDValue &Lo, SDValue &Hi) { 1680 DebugLoc dl = N->getDebugLoc(); 1681 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1682 EVT NVT = Lo.getValueType(); 1683 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1684 unsigned NVTBits = NVT.getSizeInBits(); 1685 unsigned EVTBits = EVT.getSizeInBits(); 1686 1687 if (NVTBits < EVTBits) { 1688 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, 1689 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1690 EVTBits - NVTBits))); 1691 } else { 1692 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); 1693 // The high part must be zero, make it explicit. 1694 Hi = DAG.getConstant(0, NVT); 1695 } 1696} 1697 1698void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1699 SDValue &Lo, SDValue &Hi) { 1700 DebugLoc dl = N->getDebugLoc(); 1701 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1702 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo); 1703 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi); 1704} 1705 1706void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1707 SDValue &Lo, SDValue &Hi) { 1708 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1709 unsigned NBitWidth = NVT.getSizeInBits(); 1710 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1711 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT); 1712 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1713} 1714 1715void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1716 SDValue &Lo, SDValue &Hi) { 1717 DebugLoc dl = N->getDebugLoc(); 1718 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1719 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1720 EVT NVT = Lo.getValueType(); 1721 1722 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi, 1723 DAG.getConstant(0, NVT), ISD::SETNE); 1724 1725 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo); 1726 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi); 1727 1728 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ, 1729 DAG.getNode(ISD::ADD, dl, NVT, LoLZ, 1730 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1731 Hi = DAG.getConstant(0, NVT); 1732} 1733 1734void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1735 SDValue &Lo, SDValue &Hi) { 1736 DebugLoc dl = N->getDebugLoc(); 1737 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1738 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1739 EVT NVT = Lo.getValueType(); 1740 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), 1741 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); 1742 Hi = DAG.getConstant(0, NVT); 1743} 1744 1745void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1746 SDValue &Lo, SDValue &Hi) { 1747 DebugLoc dl = N->getDebugLoc(); 1748 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1749 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1750 EVT NVT = Lo.getValueType(); 1751 1752 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, 1753 DAG.getConstant(0, NVT), ISD::SETNE); 1754 1755 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo); 1756 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi); 1757 1758 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ, 1759 DAG.getNode(ISD::ADD, dl, NVT, HiLZ, 1760 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1761 Hi = DAG.getConstant(0, NVT); 1762} 1763 1764void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1765 SDValue &Hi) { 1766 DebugLoc dl = N->getDebugLoc(); 1767 EVT VT = N->getValueType(0); 1768 SDValue Op = N->getOperand(0); 1769 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1770 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1771 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, true/*irrelevant*/, dl), 1772 Lo, Hi); 1773} 1774 1775void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1776 SDValue &Hi) { 1777 DebugLoc dl = N->getDebugLoc(); 1778 EVT VT = N->getValueType(0); 1779 SDValue Op = N->getOperand(0); 1780 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1781 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1782 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, false/*irrelevant*/, dl), 1783 Lo, Hi); 1784} 1785 1786void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1787 SDValue &Lo, SDValue &Hi) { 1788 if (ISD::isNormalLoad(N)) { 1789 ExpandRes_NormalLoad(N, Lo, Hi); 1790 return; 1791 } 1792 1793 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1794 1795 EVT VT = N->getValueType(0); 1796 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1797 SDValue Ch = N->getChain(); 1798 SDValue Ptr = N->getBasePtr(); 1799 ISD::LoadExtType ExtType = N->getExtensionType(); 1800 unsigned Alignment = N->getAlignment(); 1801 bool isVolatile = N->isVolatile(); 1802 bool isNonTemporal = N->isNonTemporal(); 1803 bool isInvariant = N->isInvariant(); 1804 DebugLoc dl = N->getDebugLoc(); 1805 1806 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1807 1808 if (N->getMemoryVT().bitsLE(NVT)) { 1809 EVT MemVT = N->getMemoryVT(); 1810 1811 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), 1812 MemVT, isVolatile, isNonTemporal, Alignment); 1813 1814 // Remember the chain. 1815 Ch = Lo.getValue(1); 1816 1817 if (ExtType == ISD::SEXTLOAD) { 1818 // The high part is obtained by SRA'ing all but one of the bits of the 1819 // lo part. 1820 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1821 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1822 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1823 } else if (ExtType == ISD::ZEXTLOAD) { 1824 // The high part is just a zero. 1825 Hi = DAG.getConstant(0, NVT); 1826 } else { 1827 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1828 // The high part is undefined. 1829 Hi = DAG.getUNDEF(NVT); 1830 } 1831 } else if (TLI.isLittleEndian()) { 1832 // Little-endian - low bits are at low addresses. 1833 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(), 1834 isVolatile, isNonTemporal, isInvariant, Alignment); 1835 1836 unsigned ExcessBits = 1837 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1838 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits); 1839 1840 // Increment the pointer to the other half. 1841 unsigned IncrementSize = NVT.getSizeInBits()/8; 1842 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1843 DAG.getIntPtrConstant(IncrementSize)); 1844 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, 1845 N->getPointerInfo().getWithOffset(IncrementSize), NEVT, 1846 isVolatile, isNonTemporal, 1847 MinAlign(Alignment, IncrementSize)); 1848 1849 // Build a factor node to remember that this load is independent of the 1850 // other one. 1851 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1852 Hi.getValue(1)); 1853 } else { 1854 // Big-endian - high bits are at low addresses. Favor aligned loads at 1855 // the cost of some bit-fiddling. 1856 EVT MemVT = N->getMemoryVT(); 1857 unsigned EBytes = MemVT.getStoreSize(); 1858 unsigned IncrementSize = NVT.getSizeInBits()/8; 1859 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1860 1861 // Load both the high bits and maybe some of the low bits. 1862 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), 1863 EVT::getIntegerVT(*DAG.getContext(), 1864 MemVT.getSizeInBits() - ExcessBits), 1865 isVolatile, isNonTemporal, Alignment); 1866 1867 // Increment the pointer to the other half. 1868 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1869 DAG.getIntPtrConstant(IncrementSize)); 1870 // Load the rest of the low bits. 1871 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, 1872 N->getPointerInfo().getWithOffset(IncrementSize), 1873 EVT::getIntegerVT(*DAG.getContext(), ExcessBits), 1874 isVolatile, isNonTemporal, 1875 MinAlign(Alignment, IncrementSize)); 1876 1877 // Build a factor node to remember that this load is independent of the 1878 // other one. 1879 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1880 Hi.getValue(1)); 1881 1882 if (ExcessBits < NVT.getSizeInBits()) { 1883 // Transfer low bits from the bottom of Hi to the top of Lo. 1884 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, 1885 DAG.getNode(ISD::SHL, dl, NVT, Hi, 1886 DAG.getConstant(ExcessBits, 1887 TLI.getPointerTy()))); 1888 // Move high bits to the right position in Hi. 1889 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, 1890 NVT, Hi, 1891 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1892 TLI.getPointerTy())); 1893 } 1894 } 1895 1896 // Legalized the chain result - switch anything that used the old chain to 1897 // use the new one. 1898 ReplaceValueWith(SDValue(N, 1), Ch); 1899} 1900 1901void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1902 SDValue &Lo, SDValue &Hi) { 1903 DebugLoc dl = N->getDebugLoc(); 1904 SDValue LL, LH, RL, RH; 1905 GetExpandedInteger(N->getOperand(0), LL, LH); 1906 GetExpandedInteger(N->getOperand(1), RL, RH); 1907 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); 1908 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); 1909} 1910 1911void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1912 SDValue &Lo, SDValue &Hi) { 1913 EVT VT = N->getValueType(0); 1914 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1915 DebugLoc dl = N->getDebugLoc(); 1916 1917 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 1918 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 1919 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 1920 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 1921 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1922 SDValue LL, LH, RL, RH; 1923 GetExpandedInteger(N->getOperand(0), LL, LH); 1924 GetExpandedInteger(N->getOperand(1), RL, RH); 1925 unsigned OuterBitSize = VT.getSizeInBits(); 1926 unsigned InnerBitSize = NVT.getSizeInBits(); 1927 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1928 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1929 1930 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1931 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1932 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1933 // The inputs are both zero-extended. 1934 if (HasUMUL_LOHI) { 1935 // We can emit a umul_lohi. 1936 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1937 Hi = SDValue(Lo.getNode(), 1); 1938 return; 1939 } 1940 if (HasMULHU) { 1941 // We can emit a mulhu+mul. 1942 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1943 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1944 return; 1945 } 1946 } 1947 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1948 // The input values are both sign-extended. 1949 if (HasSMUL_LOHI) { 1950 // We can emit a smul_lohi. 1951 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1952 Hi = SDValue(Lo.getNode(), 1); 1953 return; 1954 } 1955 if (HasMULHS) { 1956 // We can emit a mulhs+mul. 1957 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1958 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); 1959 return; 1960 } 1961 } 1962 if (HasUMUL_LOHI) { 1963 // Lo,Hi = umul LHS, RHS. 1964 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 1965 DAG.getVTList(NVT, NVT), LL, RL); 1966 Lo = UMulLOHI; 1967 Hi = UMulLOHI.getValue(1); 1968 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1969 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1970 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1971 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1972 return; 1973 } 1974 if (HasMULHU) { 1975 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1976 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1977 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1978 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1979 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1980 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1981 return; 1982 } 1983 } 1984 1985 // If nothing else, we can make a libcall. 1986 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1987 if (VT == MVT::i16) 1988 LC = RTLIB::MUL_I16; 1989 else if (VT == MVT::i32) 1990 LC = RTLIB::MUL_I32; 1991 else if (VT == MVT::i64) 1992 LC = RTLIB::MUL_I64; 1993 else if (VT == MVT::i128) 1994 LC = RTLIB::MUL_I128; 1995 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1996 1997 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1998 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true/*irrelevant*/, dl), 1999 Lo, Hi); 2000} 2001 2002void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node, 2003 SDValue &Lo, SDValue &Hi) { 2004 SDValue LHS = Node->getOperand(0); 2005 SDValue RHS = Node->getOperand(1); 2006 DebugLoc dl = Node->getDebugLoc(); 2007 2008 // Expand the result by simply replacing it with the equivalent 2009 // non-overflow-checking operation. 2010 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 2011 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2012 LHS, RHS); 2013 SplitInteger(Sum, Lo, Hi); 2014 2015 // Compute the overflow. 2016 // 2017 // LHSSign -> LHS >= 0 2018 // RHSSign -> RHS >= 0 2019 // SumSign -> Sum >= 0 2020 // 2021 // Add: 2022 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 2023 // Sub: 2024 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 2025 // 2026 EVT OType = Node->getValueType(1); 2027 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 2028 2029 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 2030 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 2031 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 2032 Node->getOpcode() == ISD::SADDO ? 2033 ISD::SETEQ : ISD::SETNE); 2034 2035 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 2036 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 2037 2038 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 2039 2040 // Use the calculated overflow everywhere. 2041 ReplaceValueWith(SDValue(Node, 1), Cmp); 2042} 2043 2044void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 2045 SDValue &Lo, SDValue &Hi) { 2046 EVT VT = N->getValueType(0); 2047 DebugLoc dl = N->getDebugLoc(); 2048 2049 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2050 if (VT == MVT::i16) 2051 LC = RTLIB::SDIV_I16; 2052 else if (VT == MVT::i32) 2053 LC = RTLIB::SDIV_I32; 2054 else if (VT == MVT::i64) 2055 LC = RTLIB::SDIV_I64; 2056 else if (VT == MVT::i128) 2057 LC = RTLIB::SDIV_I128; 2058 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 2059 2060 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2061 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl), Lo, Hi); 2062} 2063 2064void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 2065 SDValue &Lo, SDValue &Hi) { 2066 EVT VT = N->getValueType(0); 2067 DebugLoc dl = N->getDebugLoc(); 2068 2069 // If we can emit an efficient shift operation, do so now. Check to see if 2070 // the RHS is a constant. 2071 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2072 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 2073 2074 // If we can determine that the high bit of the shift is zero or one, even if 2075 // the low bits are variable, emit this shift in an optimized form. 2076 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 2077 return; 2078 2079 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 2080 unsigned PartsOpc; 2081 if (N->getOpcode() == ISD::SHL) { 2082 PartsOpc = ISD::SHL_PARTS; 2083 } else if (N->getOpcode() == ISD::SRL) { 2084 PartsOpc = ISD::SRL_PARTS; 2085 } else { 2086 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 2087 PartsOpc = ISD::SRA_PARTS; 2088 } 2089 2090 // Next check to see if the target supports this SHL_PARTS operation or if it 2091 // will custom expand it. 2092 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2093 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 2094 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 2095 Action == TargetLowering::Custom) { 2096 // Expand the subcomponents. 2097 SDValue LHSL, LHSH; 2098 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 2099 EVT VT = LHSL.getValueType(); 2100 2101 // If the shift amount operand is coming from a vector legalization it may 2102 // have an illegal type. Fix that first by casting the operand, otherwise 2103 // the new SHL_PARTS operation would need further legalization. 2104 SDValue ShiftOp = N->getOperand(1); 2105 EVT ShiftTy = TLI.getShiftAmountTy(VT); 2106 assert(ShiftTy.getScalarType().getSizeInBits() >= 2107 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) && 2108 "ShiftAmountTy is too small to cover the range of this type!"); 2109 if (ShiftOp.getValueType() != ShiftTy) 2110 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); 2111 2112 SDValue Ops[] = { LHSL, LHSH, ShiftOp }; 2113 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3); 2114 Hi = Lo.getValue(1); 2115 return; 2116 } 2117 2118 // Otherwise, emit a libcall. 2119 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2120 bool isSigned; 2121 if (N->getOpcode() == ISD::SHL) { 2122 isSigned = false; /*sign irrelevant*/ 2123 if (VT == MVT::i16) 2124 LC = RTLIB::SHL_I16; 2125 else if (VT == MVT::i32) 2126 LC = RTLIB::SHL_I32; 2127 else if (VT == MVT::i64) 2128 LC = RTLIB::SHL_I64; 2129 else if (VT == MVT::i128) 2130 LC = RTLIB::SHL_I128; 2131 } else if (N->getOpcode() == ISD::SRL) { 2132 isSigned = false; 2133 if (VT == MVT::i16) 2134 LC = RTLIB::SRL_I16; 2135 else if (VT == MVT::i32) 2136 LC = RTLIB::SRL_I32; 2137 else if (VT == MVT::i64) 2138 LC = RTLIB::SRL_I64; 2139 else if (VT == MVT::i128) 2140 LC = RTLIB::SRL_I128; 2141 } else { 2142 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 2143 isSigned = true; 2144 if (VT == MVT::i16) 2145 LC = RTLIB::SRA_I16; 2146 else if (VT == MVT::i32) 2147 LC = RTLIB::SRA_I32; 2148 else if (VT == MVT::i64) 2149 LC = RTLIB::SRA_I64; 2150 else if (VT == MVT::i128) 2151 LC = RTLIB::SRA_I128; 2152 } 2153 2154 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) { 2155 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2156 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, isSigned, dl), Lo, Hi); 2157 return; 2158 } 2159 2160 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi)) 2161 llvm_unreachable("Unsupported shift!"); 2162} 2163 2164void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 2165 SDValue &Lo, SDValue &Hi) { 2166 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2167 DebugLoc dl = N->getDebugLoc(); 2168 SDValue Op = N->getOperand(0); 2169 if (Op.getValueType().bitsLE(NVT)) { 2170 // The low part is sign extension of the input (degenerates to a copy). 2171 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); 2172 // The high part is obtained by SRA'ing all but one of the bits of low part. 2173 unsigned LoSize = NVT.getSizeInBits(); 2174 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 2175 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 2176 } else { 2177 // For example, extension of an i48 to an i64. The operand type necessarily 2178 // promotes to the result type, so will end up being expanded too. 2179 assert(getTypeAction(Op.getValueType()) == 2180 TargetLowering::TypePromoteInteger && 2181 "Only know how to promote this result!"); 2182 SDValue Res = GetPromotedInteger(Op); 2183 assert(Res.getValueType() == N->getValueType(0) && 2184 "Operand over promoted?"); 2185 // Split the promoted operand. This will simplify when it is expanded. 2186 SplitInteger(Res, Lo, Hi); 2187 unsigned ExcessBits = 2188 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 2189 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 2190 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 2191 ExcessBits))); 2192 } 2193} 2194 2195void DAGTypeLegalizer:: 2196ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 2197 DebugLoc dl = N->getDebugLoc(); 2198 GetExpandedInteger(N->getOperand(0), Lo, Hi); 2199 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2200 2201 if (EVT.bitsLE(Lo.getValueType())) { 2202 // sext_inreg the low part if needed. 2203 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, 2204 N->getOperand(1)); 2205 2206 // The high part gets the sign extension from the lo-part. This handles 2207 // things like sextinreg V:i64 from i8. 2208 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, 2209 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 2210 TLI.getPointerTy())); 2211 } else { 2212 // For example, extension of an i48 to an i64. Leave the low part alone, 2213 // sext_inreg the high part. 2214 unsigned ExcessBits = 2215 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 2216 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 2217 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 2218 ExcessBits))); 2219 } 2220} 2221 2222void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 2223 SDValue &Lo, SDValue &Hi) { 2224 EVT VT = N->getValueType(0); 2225 DebugLoc dl = N->getDebugLoc(); 2226 2227 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2228 if (VT == MVT::i16) 2229 LC = RTLIB::SREM_I16; 2230 else if (VT == MVT::i32) 2231 LC = RTLIB::SREM_I32; 2232 else if (VT == MVT::i64) 2233 LC = RTLIB::SREM_I64; 2234 else if (VT == MVT::i128) 2235 LC = RTLIB::SREM_I128; 2236 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 2237 2238 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2239 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl), Lo, Hi); 2240} 2241 2242void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 2243 SDValue &Lo, SDValue &Hi) { 2244 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2245 DebugLoc dl = N->getDebugLoc(); 2246 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); 2247 Hi = DAG.getNode(ISD::SRL, dl, 2248 N->getOperand(0).getValueType(), N->getOperand(0), 2249 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy())); 2250 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); 2251} 2252 2253void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N, 2254 SDValue &Lo, SDValue &Hi) { 2255 SDValue LHS = N->getOperand(0); 2256 SDValue RHS = N->getOperand(1); 2257 DebugLoc dl = N->getDebugLoc(); 2258 2259 // Expand the result by simply replacing it with the equivalent 2260 // non-overflow-checking operation. 2261 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ? 2262 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2263 LHS, RHS); 2264 SplitInteger(Sum, Lo, Hi); 2265 2266 // Calculate the overflow: addition overflows iff a + b < a, and subtraction 2267 // overflows iff a - b > a. 2268 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, 2269 N->getOpcode () == ISD::UADDO ? 2270 ISD::SETULT : ISD::SETUGT); 2271 2272 // Use the calculated overflow everywhere. 2273 ReplaceValueWith(SDValue(N, 1), Ofl); 2274} 2275 2276void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N, 2277 SDValue &Lo, SDValue &Hi) { 2278 EVT VT = N->getValueType(0); 2279 DebugLoc dl = N->getDebugLoc(); 2280 2281 // A divide for UMULO should be faster than a function call. 2282 if (N->getOpcode() == ISD::UMULO) { 2283 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1); 2284 2285 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS); 2286 SplitInteger(MUL, Lo, Hi); 2287 2288 // A divide for UMULO will be faster than a function call. Select to 2289 // make sure we aren't using 0. 2290 SDValue isZero = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2291 RHS, DAG.getConstant(0, VT), ISD::SETEQ); 2292 SDValue NotZero = DAG.getNode(ISD::SELECT, dl, VT, isZero, 2293 DAG.getConstant(1, VT), RHS); 2294 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero); 2295 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS, 2296 ISD::SETNE); 2297 Overflow = DAG.getNode(ISD::SELECT, dl, N->getValueType(1), isZero, 2298 DAG.getConstant(0, N->getValueType(1)), 2299 Overflow); 2300 ReplaceValueWith(SDValue(N, 1), Overflow); 2301 return; 2302 } 2303 2304 Type *RetTy = VT.getTypeForEVT(*DAG.getContext()); 2305 EVT PtrVT = TLI.getPointerTy(); 2306 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext()); 2307 2308 // Replace this with a libcall that will check overflow. 2309 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2310 if (VT == MVT::i32) 2311 LC = RTLIB::MULO_I32; 2312 else if (VT == MVT::i64) 2313 LC = RTLIB::MULO_I64; 2314 else if (VT == MVT::i128) 2315 LC = RTLIB::MULO_I128; 2316 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!"); 2317 2318 SDValue Temp = DAG.CreateStackTemporary(PtrVT); 2319 // Temporary for the overflow value, default it to zero. 2320 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, 2321 DAG.getConstant(0, PtrVT), Temp, 2322 MachinePointerInfo(), false, false, 0); 2323 2324 TargetLowering::ArgListTy Args; 2325 TargetLowering::ArgListEntry Entry; 2326 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 2327 EVT ArgVT = N->getOperand(i).getValueType(); 2328 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 2329 Entry.Node = N->getOperand(i); 2330 Entry.Ty = ArgTy; 2331 Entry.isSExt = true; 2332 Entry.isZExt = false; 2333 Args.push_back(Entry); 2334 } 2335 2336 // Also pass the address of the overflow check. 2337 Entry.Node = Temp; 2338 Entry.Ty = PtrTy->getPointerTo(); 2339 Entry.isSExt = true; 2340 Entry.isZExt = false; 2341 Args.push_back(Entry); 2342 2343 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT); 2344 TargetLowering:: 2345 CallLoweringInfo CLI(Chain, RetTy, true, false, false, false, 2346 0, TLI.getLibcallCallingConv(LC), 2347 /*isTailCall=*/false, 2348 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2349 Func, Args, DAG, dl); 2350 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); 2351 2352 SplitInteger(CallInfo.first, Lo, Hi); 2353 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp, 2354 MachinePointerInfo(), false, false, false, 0); 2355 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2, 2356 DAG.getConstant(0, PtrVT), 2357 ISD::SETNE); 2358 // Use the overflow from the libcall everywhere. 2359 ReplaceValueWith(SDValue(N, 1), Ofl); 2360} 2361 2362void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 2363 SDValue &Lo, SDValue &Hi) { 2364 EVT VT = N->getValueType(0); 2365 DebugLoc dl = N->getDebugLoc(); 2366 2367 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2368 if (VT == MVT::i16) 2369 LC = RTLIB::UDIV_I16; 2370 else if (VT == MVT::i32) 2371 LC = RTLIB::UDIV_I32; 2372 else if (VT == MVT::i64) 2373 LC = RTLIB::UDIV_I64; 2374 else if (VT == MVT::i128) 2375 LC = RTLIB::UDIV_I128; 2376 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 2377 2378 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2379 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl), Lo, Hi); 2380} 2381 2382void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 2383 SDValue &Lo, SDValue &Hi) { 2384 EVT VT = N->getValueType(0); 2385 DebugLoc dl = N->getDebugLoc(); 2386 2387 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2388 if (VT == MVT::i16) 2389 LC = RTLIB::UREM_I16; 2390 else if (VT == MVT::i32) 2391 LC = RTLIB::UREM_I32; 2392 else if (VT == MVT::i64) 2393 LC = RTLIB::UREM_I64; 2394 else if (VT == MVT::i128) 2395 LC = RTLIB::UREM_I128; 2396 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 2397 2398 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2399 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl), Lo, Hi); 2400} 2401 2402void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 2403 SDValue &Lo, SDValue &Hi) { 2404 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2405 DebugLoc dl = N->getDebugLoc(); 2406 SDValue Op = N->getOperand(0); 2407 if (Op.getValueType().bitsLE(NVT)) { 2408 // The low part is zero extension of the input (degenerates to a copy). 2409 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); 2410 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 2411 } else { 2412 // For example, extension of an i48 to an i64. The operand type necessarily 2413 // promotes to the result type, so will end up being expanded too. 2414 assert(getTypeAction(Op.getValueType()) == 2415 TargetLowering::TypePromoteInteger && 2416 "Only know how to promote this result!"); 2417 SDValue Res = GetPromotedInteger(Op); 2418 assert(Res.getValueType() == N->getValueType(0) && 2419 "Operand over promoted?"); 2420 // Split the promoted operand. This will simplify when it is expanded. 2421 SplitInteger(Res, Lo, Hi); 2422 unsigned ExcessBits = 2423 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 2424 Hi = DAG.getZeroExtendInReg(Hi, dl, 2425 EVT::getIntegerVT(*DAG.getContext(), 2426 ExcessBits)); 2427 } 2428} 2429 2430void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N, 2431 SDValue &Lo, SDValue &Hi) { 2432 DebugLoc dl = N->getDebugLoc(); 2433 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT(); 2434 SDValue Zero = DAG.getConstant(0, VT); 2435 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 2436 N->getOperand(0), 2437 N->getOperand(1), Zero, Zero, 2438 cast<AtomicSDNode>(N)->getMemOperand(), 2439 cast<AtomicSDNode>(N)->getOrdering(), 2440 cast<AtomicSDNode>(N)->getSynchScope()); 2441 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0)); 2442 ReplaceValueWith(SDValue(N, 1), Swap.getValue(1)); 2443} 2444 2445//===----------------------------------------------------------------------===// 2446// Integer Operand Expansion 2447//===----------------------------------------------------------------------===// 2448 2449/// ExpandIntegerOperand - This method is called when the specified operand of 2450/// the specified node is found to need expansion. At this point, all of the 2451/// result types of the node are known to be legal, but other operands of the 2452/// node may need promotion or expansion as well as the specified one. 2453bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 2454 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n"); 2455 SDValue Res = SDValue(); 2456 2457 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 2458 return false; 2459 2460 switch (N->getOpcode()) { 2461 default: 2462 #ifndef NDEBUG 2463 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": "; 2464 N->dump(&DAG); dbgs() << "\n"; 2465 #endif 2466 llvm_unreachable("Do not know how to expand this operator's operand!"); 2467 2468 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break; 2469 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 2470 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 2471 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 2472 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 2473 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; 2474 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 2475 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 2476 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 2477 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break; 2478 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 2479 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 2480 2481 case ISD::SHL: 2482 case ISD::SRA: 2483 case ISD::SRL: 2484 case ISD::ROTL: 2485 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break; 2486 case ISD::RETURNADDR: 2487 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break; 2488 2489 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break; 2490 } 2491 2492 // If the result is null, the sub-method took care of registering results etc. 2493 if (!Res.getNode()) return false; 2494 2495 // If the result is N, the sub-method updated N in place. Tell the legalizer 2496 // core about this. 2497 if (Res.getNode() == N) 2498 return true; 2499 2500 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2501 "Invalid operand expansion"); 2502 2503 ReplaceValueWith(SDValue(N, 0), Res); 2504 return false; 2505} 2506 2507/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 2508/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 2509void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 2510 SDValue &NewRHS, 2511 ISD::CondCode &CCCode, 2512 DebugLoc dl) { 2513 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 2514 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 2515 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 2516 2517 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 2518 if (RHSLo == RHSHi) { 2519 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 2520 if (RHSCST->isAllOnesValue()) { 2521 // Equality comparison to -1. 2522 NewLHS = DAG.getNode(ISD::AND, dl, 2523 LHSLo.getValueType(), LHSLo, LHSHi); 2524 NewRHS = RHSLo; 2525 return; 2526 } 2527 } 2528 } 2529 2530 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 2531 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 2532 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS); 2533 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2534 return; 2535 } 2536 2537 // If this is a comparison of the sign bit, just look at the top part. 2538 // X > -1, x < 0 2539 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 2540 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 2541 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 2542 NewLHS = LHSHi; 2543 NewRHS = RHSHi; 2544 return; 2545 } 2546 2547 // FIXME: This generated code sucks. 2548 ISD::CondCode LowCC; 2549 switch (CCCode) { 2550 default: llvm_unreachable("Unknown integer setcc!"); 2551 case ISD::SETLT: 2552 case ISD::SETULT: LowCC = ISD::SETULT; break; 2553 case ISD::SETGT: 2554 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2555 case ISD::SETLE: 2556 case ISD::SETULE: LowCC = ISD::SETULE; break; 2557 case ISD::SETGE: 2558 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2559 } 2560 2561 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2562 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2563 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2564 2565 // NOTE: on targets without efficient SELECT of bools, we can always use 2566 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2567 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true, NULL); 2568 SDValue Tmp1, Tmp2; 2569 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), 2570 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl); 2571 if (!Tmp1.getNode()) 2572 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 2573 LHSLo, RHSLo, LowCC); 2574 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2575 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl); 2576 if (!Tmp2.getNode()) 2577 Tmp2 = DAG.getNode(ISD::SETCC, dl, 2578 TLI.getSetCCResultType(LHSHi.getValueType()), 2579 LHSHi, RHSHi, DAG.getCondCode(CCCode)); 2580 2581 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2582 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2583 if ((Tmp1C && Tmp1C->isNullValue()) || 2584 (Tmp2C && Tmp2C->isNullValue() && 2585 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2586 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2587 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2588 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2589 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2590 // low part is known false, returns high part. 2591 // For LE / GE, if high part is known false, ignore the low part. 2592 // For LT / GT, if high part is known true, ignore the low part. 2593 NewLHS = Tmp2; 2594 NewRHS = SDValue(); 2595 return; 2596 } 2597 2598 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2599 LHSHi, RHSHi, ISD::SETEQ, false, 2600 DagCombineInfo, dl); 2601 if (!NewLHS.getNode()) 2602 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 2603 LHSHi, RHSHi, ISD::SETEQ); 2604 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), 2605 NewLHS, Tmp1, Tmp2); 2606 NewRHS = SDValue(); 2607} 2608 2609SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2610 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2611 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2612 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2613 2614 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2615 // against zero to select between true and false values. 2616 if (NewRHS.getNode() == 0) { 2617 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2618 CCCode = ISD::SETNE; 2619 } 2620 2621 // Update N to have the operands specified. 2622 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 2623 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2624 N->getOperand(4)), 0); 2625} 2626 2627SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2628 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2629 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2630 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2631 2632 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2633 // against zero to select between true and false values. 2634 if (NewRHS.getNode() == 0) { 2635 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2636 CCCode = ISD::SETNE; 2637 } 2638 2639 // Update N to have the operands specified. 2640 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, 2641 N->getOperand(2), N->getOperand(3), 2642 DAG.getCondCode(CCCode)), 0); 2643} 2644 2645SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2646 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2647 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2648 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2649 2650 // If ExpandSetCCOperands returned a scalar, use it. 2651 if (NewRHS.getNode() == 0) { 2652 assert(NewLHS.getValueType() == N->getValueType(0) && 2653 "Unexpected setcc expansion!"); 2654 return NewLHS; 2655 } 2656 2657 // Otherwise, update N to have the operands specified. 2658 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, 2659 DAG.getCondCode(CCCode)), 0); 2660} 2661 2662SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) { 2663 // The value being shifted is legal, but the shift amount is too big. 2664 // It follows that either the result of the shift is undefined, or the 2665 // upper half of the shift amount is zero. Just use the lower half. 2666 SDValue Lo, Hi; 2667 GetExpandedInteger(N->getOperand(1), Lo, Hi); 2668 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0); 2669} 2670 2671SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) { 2672 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This 2673 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this 2674 // constant to valid type. 2675 SDValue Lo, Hi; 2676 GetExpandedInteger(N->getOperand(0), Lo, Hi); 2677 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0); 2678} 2679 2680SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2681 SDValue Op = N->getOperand(0); 2682 EVT DstVT = N->getValueType(0); 2683 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2684 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2685 "Don't know how to expand this SINT_TO_FP!"); 2686 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, N->getDebugLoc()); 2687} 2688 2689SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2690 if (ISD::isNormalStore(N)) 2691 return ExpandOp_NormalStore(N, OpNo); 2692 2693 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2694 assert(OpNo == 1 && "Can only expand the stored value so far"); 2695 2696 EVT VT = N->getOperand(1).getValueType(); 2697 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2698 SDValue Ch = N->getChain(); 2699 SDValue Ptr = N->getBasePtr(); 2700 unsigned Alignment = N->getAlignment(); 2701 bool isVolatile = N->isVolatile(); 2702 bool isNonTemporal = N->isNonTemporal(); 2703 DebugLoc dl = N->getDebugLoc(); 2704 SDValue Lo, Hi; 2705 2706 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2707 2708 if (N->getMemoryVT().bitsLE(NVT)) { 2709 GetExpandedInteger(N->getValue(), Lo, Hi); 2710 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), 2711 N->getMemoryVT(), isVolatile, isNonTemporal, 2712 Alignment); 2713 } 2714 2715 if (TLI.isLittleEndian()) { 2716 // Little-endian - low bits are at low addresses. 2717 GetExpandedInteger(N->getValue(), Lo, Hi); 2718 2719 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), 2720 isVolatile, isNonTemporal, Alignment); 2721 2722 unsigned ExcessBits = 2723 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2724 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits); 2725 2726 // Increment the pointer to the other half. 2727 unsigned IncrementSize = NVT.getSizeInBits()/8; 2728 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2729 DAG.getIntPtrConstant(IncrementSize)); 2730 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, 2731 N->getPointerInfo().getWithOffset(IncrementSize), 2732 NEVT, isVolatile, isNonTemporal, 2733 MinAlign(Alignment, IncrementSize)); 2734 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2735 } 2736 2737 // Big-endian - high bits are at low addresses. Favor aligned stores at 2738 // the cost of some bit-fiddling. 2739 GetExpandedInteger(N->getValue(), Lo, Hi); 2740 2741 EVT ExtVT = N->getMemoryVT(); 2742 unsigned EBytes = ExtVT.getStoreSize(); 2743 unsigned IncrementSize = NVT.getSizeInBits()/8; 2744 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2745 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(), 2746 ExtVT.getSizeInBits() - ExcessBits); 2747 2748 if (ExcessBits < NVT.getSizeInBits()) { 2749 // Transfer high bits from the top of Lo to the bottom of Hi. 2750 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, 2751 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2752 TLI.getPointerTy())); 2753 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, 2754 DAG.getNode(ISD::SRL, dl, NVT, Lo, 2755 DAG.getConstant(ExcessBits, 2756 TLI.getPointerTy()))); 2757 } 2758 2759 // Store both the high bits and maybe some of the low bits. 2760 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(), 2761 HiVT, isVolatile, isNonTemporal, Alignment); 2762 2763 // Increment the pointer to the other half. 2764 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2765 DAG.getIntPtrConstant(IncrementSize)); 2766 // Store the lowest ExcessBits bits in the second half. 2767 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, 2768 N->getPointerInfo().getWithOffset(IncrementSize), 2769 EVT::getIntegerVT(*DAG.getContext(), ExcessBits), 2770 isVolatile, isNonTemporal, 2771 MinAlign(Alignment, IncrementSize)); 2772 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2773} 2774 2775SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2776 SDValue InL, InH; 2777 GetExpandedInteger(N->getOperand(0), InL, InH); 2778 // Just truncate the low part of the source. 2779 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL); 2780} 2781 2782SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2783 SDValue Op = N->getOperand(0); 2784 EVT SrcVT = Op.getValueType(); 2785 EVT DstVT = N->getValueType(0); 2786 DebugLoc dl = N->getDebugLoc(); 2787 2788 // The following optimization is valid only if every value in SrcVT (when 2789 // treated as signed) is representable in DstVT. Check that the mantissa 2790 // size of DstVT is >= than the number of bits in SrcVT -1. 2791 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT); 2792 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 && 2793 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2794 // Do a signed conversion then adjust the result. 2795 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); 2796 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2797 2798 // The result of the signed conversion needs adjusting if the 'sign bit' of 2799 // the incoming integer was set. To handle this, we dynamically test to see 2800 // if it is set, and, if so, add a fudge factor. 2801 2802 const uint64_t F32TwoE32 = 0x4F800000ULL; 2803 const uint64_t F32TwoE64 = 0x5F800000ULL; 2804 const uint64_t F32TwoE128 = 0x7F800000ULL; 2805 2806 APInt FF(32, 0); 2807 if (SrcVT == MVT::i32) 2808 FF = APInt(32, F32TwoE32); 2809 else if (SrcVT == MVT::i64) 2810 FF = APInt(32, F32TwoE64); 2811 else if (SrcVT == MVT::i128) 2812 FF = APInt(32, F32TwoE128); 2813 else 2814 llvm_unreachable("Unsupported UINT_TO_FP!"); 2815 2816 // Check whether the sign bit is set. 2817 SDValue Lo, Hi; 2818 GetExpandedInteger(Op, Lo, Hi); 2819 SDValue SignSet = DAG.getSetCC(dl, 2820 TLI.getSetCCResultType(Hi.getValueType()), 2821 Hi, DAG.getConstant(0, Hi.getValueType()), 2822 ISD::SETLT); 2823 2824 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2825 SDValue FudgePtr = DAG.getConstantPool( 2826 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 2827 TLI.getPointerTy()); 2828 2829 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2830 SDValue Zero = DAG.getIntPtrConstant(0); 2831 SDValue Four = DAG.getIntPtrConstant(4); 2832 if (TLI.isBigEndian()) std::swap(Zero, Four); 2833 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 2834 Zero, Four); 2835 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2836 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset); 2837 Alignment = std::min(Alignment, 4u); 2838 2839 // Load the value out, extending it from f32 to the destination float type. 2840 // FIXME: Avoid the extend by constructing the right constant pool? 2841 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), 2842 FudgePtr, 2843 MachinePointerInfo::getConstantPool(), 2844 MVT::f32, 2845 false, false, Alignment); 2846 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); 2847 } 2848 2849 // Otherwise, use a libcall. 2850 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2851 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2852 "Don't know how to expand this UINT_TO_FP!"); 2853 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl); 2854} 2855 2856SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) { 2857 DebugLoc dl = N->getDebugLoc(); 2858 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 2859 cast<AtomicSDNode>(N)->getMemoryVT(), 2860 N->getOperand(0), 2861 N->getOperand(1), N->getOperand(2), 2862 cast<AtomicSDNode>(N)->getMemOperand(), 2863 cast<AtomicSDNode>(N)->getOrdering(), 2864 cast<AtomicSDNode>(N)->getSynchScope()); 2865 return Swap.getValue(1); 2866} 2867 2868 2869SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) { 2870 SDValue InOp0 = N->getOperand(0); 2871 EVT InVT = InOp0.getValueType(); 2872 2873 EVT OutVT = N->getValueType(0); 2874 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2875 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2876 unsigned OutNumElems = OutVT.getVectorNumElements(); 2877 EVT NOutVTElem = NOutVT.getVectorElementType(); 2878 2879 DebugLoc dl = N->getDebugLoc(); 2880 SDValue BaseIdx = N->getOperand(1); 2881 2882 SmallVector<SDValue, 8> Ops; 2883 Ops.reserve(OutNumElems); 2884 for (unsigned i = 0; i != OutNumElems; ++i) { 2885 2886 // Extract the element from the original vector. 2887 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(), 2888 BaseIdx, DAG.getIntPtrConstant(i)); 2889 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 2890 InVT.getVectorElementType(), N->getOperand(0), Index); 2891 2892 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext); 2893 // Insert the converted element to the new vector. 2894 Ops.push_back(Op); 2895 } 2896 2897 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size()); 2898} 2899 2900 2901SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) { 2902 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N); 2903 EVT VT = N->getValueType(0); 2904 DebugLoc dl = N->getDebugLoc(); 2905 2906 unsigned NumElts = VT.getVectorNumElements(); 2907 SmallVector<int, 8> NewMask; 2908 for (unsigned i = 0; i != NumElts; ++i) { 2909 NewMask.push_back(SV->getMaskElt(i)); 2910 } 2911 2912 SDValue V0 = GetPromotedInteger(N->getOperand(0)); 2913 SDValue V1 = GetPromotedInteger(N->getOperand(1)); 2914 EVT OutVT = V0.getValueType(); 2915 2916 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]); 2917} 2918 2919 2920SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) { 2921 EVT OutVT = N->getValueType(0); 2922 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2923 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2924 unsigned NumElems = N->getNumOperands(); 2925 EVT NOutVTElem = NOutVT.getVectorElementType(); 2926 2927 DebugLoc dl = N->getDebugLoc(); 2928 2929 SmallVector<SDValue, 8> Ops; 2930 Ops.reserve(NumElems); 2931 for (unsigned i = 0; i != NumElems; ++i) { 2932 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i)); 2933 Ops.push_back(Op); 2934 } 2935 2936 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size()); 2937} 2938 2939SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) { 2940 2941 DebugLoc dl = N->getDebugLoc(); 2942 2943 assert(!N->getOperand(0).getValueType().isVector() && 2944 "Input must be a scalar"); 2945 2946 EVT OutVT = N->getValueType(0); 2947 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2948 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2949 EVT NOutVTElem = NOutVT.getVectorElementType(); 2950 2951 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0)); 2952 2953 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op); 2954} 2955 2956SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) { 2957 DebugLoc dl = N->getDebugLoc(); 2958 2959 EVT OutVT = N->getValueType(0); 2960 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2961 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2962 2963 EVT InElemTy = OutVT.getVectorElementType(); 2964 EVT OutElemTy = NOutVT.getVectorElementType(); 2965 2966 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements(); 2967 unsigned NumOutElem = NOutVT.getVectorNumElements(); 2968 unsigned NumOperands = N->getNumOperands(); 2969 assert(NumElem * NumOperands == NumOutElem && 2970 "Unexpected number of elements"); 2971 2972 // Take the elements from the first vector. 2973 SmallVector<SDValue, 8> Ops(NumOutElem); 2974 for (unsigned i = 0; i < NumOperands; ++i) { 2975 SDValue Op = N->getOperand(i); 2976 for (unsigned j = 0; j < NumElem; ++j) { 2977 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 2978 InElemTy, Op, DAG.getIntPtrConstant(j)); 2979 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext); 2980 } 2981 } 2982 2983 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size()); 2984} 2985 2986SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) { 2987 EVT OutVT = N->getValueType(0); 2988 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 2989 assert(NOutVT.isVector() && "This type must be promoted to a vector type"); 2990 2991 EVT NOutVTElem = NOutVT.getVectorElementType(); 2992 2993 DebugLoc dl = N->getDebugLoc(); 2994 SDValue V0 = GetPromotedInteger(N->getOperand(0)); 2995 2996 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl, 2997 NOutVTElem, N->getOperand(1)); 2998 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT, 2999 V0, ConvElem, N->getOperand(2)); 3000} 3001 3002SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) { 3003 DebugLoc dl = N->getDebugLoc(); 3004 SDValue V0 = GetPromotedInteger(N->getOperand(0)); 3005 SDValue V1 = N->getOperand(1); 3006 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 3007 V0->getValueType(0).getScalarType(), V0, V1); 3008 3009 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming 3010 // element types. If this is the case then we need to expand the outgoing 3011 // value and not truncate it. 3012 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0)); 3013} 3014 3015SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) { 3016 DebugLoc dl = N->getDebugLoc(); 3017 unsigned NumElems = N->getNumOperands(); 3018 3019 EVT RetSclrTy = N->getValueType(0).getVectorElementType(); 3020 3021 SmallVector<SDValue, 8> NewOps; 3022 NewOps.reserve(NumElems); 3023 3024 // For each incoming vector 3025 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) { 3026 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx)); 3027 EVT SclrTy = Incoming->getValueType(0).getVectorElementType(); 3028 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements(); 3029 3030 for (unsigned i=0; i<NumElem; ++i) { 3031 // Extract element from incoming vector 3032 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, 3033 Incoming, DAG.getIntPtrConstant(i)); 3034 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex); 3035 NewOps.push_back(Tr); 3036 } 3037 } 3038 3039 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), 3040 &NewOps[0], NewOps.size()); 3041 } 3042