LegalizeIntegerTypes.cpp revision 81311d9869e1a94fb9f044b0b921d0d2b736823e
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22using namespace llvm; 23 24//===----------------------------------------------------------------------===// 25// Integer Result Promotion 26//===----------------------------------------------------------------------===// 27 28/// PromoteIntegerResult - This method is called when a result of a node is 29/// found to be in need of promotion to a larger type. At this point, the node 30/// may also have invalid operands or may have other results that need 31/// expansion, we just know that (at least) one result needs promotion. 32void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); 34 SDValue Result = SDValue(); 35 36 // See if the target wants to custom expand this node. 37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 38 TargetLowering::Custom) { 39 // If the target wants to, allow it to lower this itself. 40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 41 // Everything that once used N now uses P. We are guaranteed that the 42 // result value types of N and the result value types of P match. 43 ReplaceNodeWith(N, P); 44 return; 45 } 46 } 47 48 switch (N->getOpcode()) { 49 default: 50#ifndef NDEBUG 51 cerr << "PromoteIntegerResult #" << ResNo << ": "; 52 N->dump(&DAG); cerr << "\n"; 53#endif 54 assert(0 && "Do not know how to promote this operator!"); 55 abort(); 56 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break; 57 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break; 58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break; 59 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break; 60 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break; 61 case ISD::Constant: Result = PromoteIntRes_Constant(N); break; 62 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break; 63 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break; 64 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break; 65 case ISD::EXTRACT_VECTOR_ELT: 66 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 67 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 68 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break; 69 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break; 70 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break; 71 case ISD::SHL: Result = PromoteIntRes_SHL(N); break; 72 case ISD::SIGN_EXTEND_INREG: 73 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 74 case ISD::SRA: Result = PromoteIntRes_SRA(N); break; 75 case ISD::SRL: Result = PromoteIntRes_SRL(N); break; 76 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break; 77 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break; 78 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break; 79 80 case ISD::SIGN_EXTEND: 81 case ISD::ZERO_EXTEND: 82 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break; 83 84 case ISD::FP_TO_SINT: 85 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break; 86 87 case ISD::AND: 88 case ISD::OR: 89 case ISD::XOR: 90 case ISD::ADD: 91 case ISD::SUB: 92 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break; 93 94 case ISD::SDIV: 95 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break; 96 97 case ISD::UDIV: 98 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break; 99 100 case ISD::ATOMIC_LOAD_ADD_8: 101 case ISD::ATOMIC_LOAD_SUB_8: 102 case ISD::ATOMIC_LOAD_AND_8: 103 case ISD::ATOMIC_LOAD_OR_8: 104 case ISD::ATOMIC_LOAD_XOR_8: 105 case ISD::ATOMIC_LOAD_NAND_8: 106 case ISD::ATOMIC_LOAD_MIN_8: 107 case ISD::ATOMIC_LOAD_MAX_8: 108 case ISD::ATOMIC_LOAD_UMIN_8: 109 case ISD::ATOMIC_LOAD_UMAX_8: 110 case ISD::ATOMIC_SWAP_8: 111 case ISD::ATOMIC_LOAD_ADD_16: 112 case ISD::ATOMIC_LOAD_SUB_16: 113 case ISD::ATOMIC_LOAD_AND_16: 114 case ISD::ATOMIC_LOAD_OR_16: 115 case ISD::ATOMIC_LOAD_XOR_16: 116 case ISD::ATOMIC_LOAD_NAND_16: 117 case ISD::ATOMIC_LOAD_MIN_16: 118 case ISD::ATOMIC_LOAD_MAX_16: 119 case ISD::ATOMIC_LOAD_UMIN_16: 120 case ISD::ATOMIC_LOAD_UMAX_16: 121 case ISD::ATOMIC_SWAP_16: 122 case ISD::ATOMIC_LOAD_ADD_32: 123 case ISD::ATOMIC_LOAD_SUB_32: 124 case ISD::ATOMIC_LOAD_AND_32: 125 case ISD::ATOMIC_LOAD_OR_32: 126 case ISD::ATOMIC_LOAD_XOR_32: 127 case ISD::ATOMIC_LOAD_NAND_32: 128 case ISD::ATOMIC_LOAD_MIN_32: 129 case ISD::ATOMIC_LOAD_MAX_32: 130 case ISD::ATOMIC_LOAD_UMIN_32: 131 case ISD::ATOMIC_LOAD_UMAX_32: 132 case ISD::ATOMIC_SWAP_32: 133 case ISD::ATOMIC_LOAD_ADD_64: 134 case ISD::ATOMIC_LOAD_SUB_64: 135 case ISD::ATOMIC_LOAD_AND_64: 136 case ISD::ATOMIC_LOAD_OR_64: 137 case ISD::ATOMIC_LOAD_XOR_64: 138 case ISD::ATOMIC_LOAD_NAND_64: 139 case ISD::ATOMIC_LOAD_MIN_64: 140 case ISD::ATOMIC_LOAD_MAX_64: 141 case ISD::ATOMIC_LOAD_UMIN_64: 142 case ISD::ATOMIC_LOAD_UMAX_64: 143 case ISD::ATOMIC_SWAP_64: 144 Result = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 145 146 case ISD::ATOMIC_CMP_SWAP_8: 147 case ISD::ATOMIC_CMP_SWAP_16: 148 case ISD::ATOMIC_CMP_SWAP_32: 149 case ISD::ATOMIC_CMP_SWAP_64: 150 Result = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 151 } 152 153 // If Result is null, the sub-method took care of registering the result. 154 if (Result.getNode()) 155 SetPromotedInteger(SDValue(N, ResNo), Result); 156} 157 158SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 159 // Sign-extend the new bits, and continue the assertion. 160 MVT OldVT = N->getValueType(0); 161 SDValue Op = GetPromotedInteger(N->getOperand(0)); 162 return DAG.getNode(ISD::AssertSext, Op.getValueType(), 163 DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, 164 DAG.getValueType(OldVT)), N->getOperand(1)); 165} 166 167SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 168 // Zero the new bits, and continue the assertion. 169 MVT OldVT = N->getValueType(0); 170 SDValue Op = GetPromotedInteger(N->getOperand(0)); 171 return DAG.getNode(ISD::AssertZext, Op.getValueType(), 172 DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1)); 173} 174 175SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 176 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 177 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(), 178 Op2, N->getSrcValue(), N->getAlignment()); 179 // Legalized the chain result - switch anything that used the old chain to 180 // use the new one. 181 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 182 return Res; 183} 184 185SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 186 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 187 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 188 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(), 189 Op2, Op3, N->getSrcValue(), N->getAlignment()); 190 // Legalized the chain result - switch anything that used the old chain to 191 // use the new one. 192 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 193 return Res; 194} 195 196SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 197 SDValue InOp = N->getOperand(0); 198 MVT InVT = InOp.getValueType(); 199 MVT NInVT = TLI.getTypeToTransformTo(InVT); 200 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 201 202 switch (getTypeAction(InVT)) { 203 default: 204 assert(false && "Unknown type action!"); 205 break; 206 case Legal: 207 break; 208 case PromoteInteger: 209 if (OutVT.bitsEq(NInVT)) 210 // The input promotes to the same size. Convert the promoted value. 211 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp)); 212 break; 213 case SoftenFloat: 214 // Promote the integer operand by hand. 215 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp)); 216 case ExpandInteger: 217 case ExpandFloat: 218 break; 219 case ScalarizeVector: 220 // Convert the element to an integer and promote it by hand. 221 return DAG.getNode(ISD::ANY_EXTEND, OutVT, 222 BitConvertToInteger(GetScalarizedVector(InOp))); 223 case SplitVector: 224 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 225 // pieces of the input into integers and reassemble in the final type. 226 SDValue Lo, Hi; 227 GetSplitVector(N->getOperand(0), Lo, Hi); 228 Lo = BitConvertToInteger(Lo); 229 Hi = BitConvertToInteger(Hi); 230 231 if (TLI.isBigEndian()) 232 std::swap(Lo, Hi); 233 234 InOp = DAG.getNode(ISD::ANY_EXTEND, 235 MVT::getIntegerVT(OutVT.getSizeInBits()), 236 JoinIntegers(Lo, Hi)); 237 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp); 238 } 239 240 // Otherwise, lower the bit-convert to a store/load from the stack, then 241 // promote the load. 242 SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0)); 243 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode())); 244} 245 246SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 247 SDValue Op = GetPromotedInteger(N->getOperand(0)); 248 MVT OVT = N->getValueType(0); 249 MVT NVT = Op.getValueType(); 250 251 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 252 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op), 253 DAG.getConstant(DiffBits, TLI.getShiftAmountTy())); 254} 255 256SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 257 // The pair element type may be legal, or may not promote to the same type as 258 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 259 return DAG.getNode(ISD::ANY_EXTEND, 260 TLI.getTypeToTransformTo(N->getValueType(0)), 261 JoinIntegers(N->getOperand(0), N->getOperand(1))); 262} 263 264SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 265 MVT VT = N->getValueType(0); 266 // Zero extend things like i1, sign extend everything else. It shouldn't 267 // matter in theory which one we pick, but this tends to give better code? 268 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 269 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), 270 SDValue(N, 0)); 271 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 272 return Result; 273} 274 275SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 276 SDValue Op = GetPromotedInteger(N->getOperand(0)); 277 MVT OVT = N->getValueType(0); 278 MVT NVT = Op.getValueType(); 279 // Zero extend to the promoted type and do the count there. 280 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT)); 281 // Subtract off the extra leading bits in the bigger type. 282 return DAG.getNode(ISD::SUB, NVT, Op, 283 DAG.getConstant(NVT.getSizeInBits() - 284 OVT.getSizeInBits(), NVT)); 285} 286 287SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 288 SDValue Op = GetPromotedInteger(N->getOperand(0)); 289 MVT OVT = N->getValueType(0); 290 MVT NVT = Op.getValueType(); 291 // Zero extend to the promoted type and do the count there. 292 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT)); 293} 294 295SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 296 SDValue Op = GetPromotedInteger(N->getOperand(0)); 297 MVT OVT = N->getValueType(0); 298 MVT NVT = Op.getValueType(); 299 // The count is the same in the promoted type except if the original 300 // value was zero. This can be handled by setting the bit just off 301 // the top of the original type. 302 APInt TopBit(NVT.getSizeInBits(), 0); 303 TopBit.set(OVT.getSizeInBits()); 304 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT)); 305 return DAG.getNode(ISD::CTTZ, NVT, Op); 306} 307 308SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 309 MVT OldVT = N->getValueType(0); 310 SDValue OldVec = N->getOperand(0); 311 unsigned OldElts = OldVec.getValueType().getVectorNumElements(); 312 313 if (OldElts == 1) { 314 assert(!isTypeLegal(OldVec.getValueType()) && 315 "Legal one-element vector of a type needing promotion!"); 316 // It is tempting to follow GetScalarizedVector by a call to 317 // GetPromotedInteger, but this would be wrong because the 318 // scalarized value may not yet have been processed. 319 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), 320 GetScalarizedVector(OldVec)); 321 } 322 323 // Convert to a vector half as long with an element type of twice the width, 324 // for example <4 x i16> -> <2 x i32>. 325 assert(!(OldElts & 1) && "Odd length vectors not supported!"); 326 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 327 assert(OldVT.isSimple() && NewVT.isSimple()); 328 329 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, 330 MVT::getVectorVT(NewVT, OldElts / 2), 331 OldVec); 332 333 // Extract the element at OldIdx / 2 from the new vector. 334 SDValue OldIdx = N->getOperand(1); 335 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx, 336 DAG.getConstant(1, TLI.getShiftAmountTy())); 337 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx); 338 339 // Select the appropriate half of the element: Lo if OldIdx was even, 340 // Hi if it was odd. 341 SDValue Lo = Elt; 342 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt, 343 DAG.getConstant(OldVT.getSizeInBits(), 344 TLI.getShiftAmountTy())); 345 if (TLI.isBigEndian()) 346 std::swap(Lo, Hi); 347 348 SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx); 349 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo); 350} 351 352SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 353 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 354 unsigned NewOpc = N->getOpcode(); 355 356 // If we're promoting a UINT to a larger size, check to see if the new node 357 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 358 // we can use that instead. This allows us to generate better code for 359 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 360 // legal, such as PowerPC. 361 if (N->getOpcode() == ISD::FP_TO_UINT && 362 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 363 TLI.isOperationLegal(ISD::FP_TO_SINT, NVT)) 364 NewOpc = ISD::FP_TO_SINT; 365 366 SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0)); 367 368 // Assert that the converted value fits in the original type. If it doesn't 369 // (eg: because the value being converted is too big), then the result of the 370 // original operation was undefined anyway, so the assert is still correct. 371 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 372 ISD::AssertZext : ISD::AssertSext, 373 NVT, Res, DAG.getValueType(N->getValueType(0))); 374} 375 376SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 377 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 378 379 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 380 SDValue Res = GetPromotedInteger(N->getOperand(0)); 381 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 382 383 // If the result and operand types are the same after promotion, simplify 384 // to an in-register extension. 385 if (NVT == Res.getValueType()) { 386 // The high bits are not guaranteed to be anything. Insert an extend. 387 if (N->getOpcode() == ISD::SIGN_EXTEND) 388 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, 389 DAG.getValueType(N->getOperand(0).getValueType())); 390 if (N->getOpcode() == ISD::ZERO_EXTEND) 391 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); 392 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 393 return Res; 394 } 395 } 396 397 // Otherwise, just extend the original operand all the way to the larger type. 398 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0)); 399} 400 401SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 402 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 403 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 404 ISD::LoadExtType ExtType = 405 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 406 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(), 407 N->getSrcValue(), N->getSrcValueOffset(), 408 N->getMemoryVT(), N->isVolatile(), 409 N->getAlignment()); 410 411 // Legalized the chain result - switch anything that used the old chain to 412 // use the new one. 413 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 414 return Res; 415} 416 417SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 418 // Sign extend the input. 419 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 420 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 421 MVT VT = N->getValueType(0); 422 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS, 423 DAG.getValueType(VT)); 424 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS, 425 DAG.getValueType(VT)); 426 427 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 428} 429 430SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 431 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 432 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 433 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS); 434} 435 436SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 437 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 438 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 439 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0), 440 N->getOperand(1), LHS, RHS, N->getOperand(4)); 441} 442 443SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 444 MVT SVT = TLI.getSetCCResultType(N->getOperand(0)); 445 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 446 447 // Get the SETCC result using the canonical SETCC type. 448 SDValue SetCC = DAG.getNode(ISD::SETCC, SVT, N->getOperand(0), 449 N->getOperand(1), N->getOperand(2)); 450 451 // Convert to the expected type. 452 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 453 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 454 return DAG.getNode(ISD::TRUNCATE, NVT, SetCC); 455} 456 457SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 458 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)), 459 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 460} 461 462SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 463 SDValue Op = GetPromotedInteger(N->getOperand(0)); 464 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, 465 N->getOperand(1)); 466} 467 468SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 469 // The input may have strange things in the top bits of the registers, but 470 // these operations don't care. They may have weird bits going out, but 471 // that too is okay if they are integer operations. 472 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 473 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 474 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 475} 476 477SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 478 // The input value must be properly sign extended. 479 MVT VT = N->getValueType(0); 480 MVT NVT = TLI.getTypeToTransformTo(VT); 481 SDValue Res = GetPromotedInteger(N->getOperand(0)); 482 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT)); 483 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1)); 484} 485 486SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 487 // The input value must be properly zero extended. 488 MVT VT = N->getValueType(0); 489 MVT NVT = TLI.getTypeToTransformTo(VT); 490 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 491 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1)); 492} 493 494SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 495 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 496 SDValue Res; 497 498 switch (getTypeAction(N->getOperand(0).getValueType())) { 499 default: assert(0 && "Unknown type action!"); 500 case Legal: 501 case ExpandInteger: 502 Res = N->getOperand(0); 503 break; 504 case PromoteInteger: 505 Res = GetPromotedInteger(N->getOperand(0)); 506 break; 507 } 508 509 // Truncate to NVT instead of VT 510 return DAG.getNode(ISD::TRUNCATE, NVT, Res); 511} 512 513SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 514 // Zero extend the input. 515 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 516 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 517 MVT VT = N->getValueType(0); 518 LHS = DAG.getZeroExtendInReg(LHS, VT); 519 RHS = DAG.getZeroExtendInReg(RHS, VT); 520 521 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 522} 523 524SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 525 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0))); 526} 527 528SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 529 SDValue Chain = N->getOperand(0); // Get the chain. 530 SDValue Ptr = N->getOperand(1); // Get the pointer. 531 MVT VT = N->getValueType(0); 532 533 MVT RegVT = TLI.getRegisterType(VT); 534 unsigned NumRegs = TLI.getNumRegisters(VT); 535 // The argument is passed as NumRegs registers of type RegVT. 536 537 SmallVector<SDValue, 8> Parts(NumRegs); 538 for (unsigned i = 0; i < NumRegs; ++i) { 539 Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2)); 540 Chain = Parts[i].getValue(1); 541 } 542 543 // Handle endianness of the load. 544 if (TLI.isBigEndian()) 545 std::reverse(Parts.begin(), Parts.end()); 546 547 // Assemble the parts in the promoted type. 548 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 549 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[0]); 550 for (unsigned i = 1; i < NumRegs; ++i) { 551 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[i]); 552 // Shift it to the right position and "or" it in. 553 Part = DAG.getNode(ISD::SHL, NVT, Part, 554 DAG.getConstant(i * RegVT.getSizeInBits(), 555 TLI.getShiftAmountTy())); 556 Res = DAG.getNode(ISD::OR, NVT, Res, Part); 557 } 558 559 // Modified the chain result - switch anything that used the old chain to 560 // use the new one. 561 ReplaceValueWith(SDValue(N, 1), Chain); 562 563 return Res; 564} 565 566 567//===----------------------------------------------------------------------===// 568// Integer Operand Promotion 569//===----------------------------------------------------------------------===// 570 571/// PromoteIntegerOperand - This method is called when the specified operand of 572/// the specified node is found to need promotion. At this point, all of the 573/// result types of the node are known to be legal, but other operands of the 574/// node may need promotion or expansion as well as the specified one. 575bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 576 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); 577 SDValue Res = SDValue(); 578 579 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 580 == TargetLowering::Custom) 581 Res = TLI.LowerOperation(SDValue(N, 0), DAG); 582 583 if (Res.getNode() == 0) { 584 switch (N->getOpcode()) { 585 default: 586 #ifndef NDEBUG 587 cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; 588 N->dump(&DAG); cerr << "\n"; 589 #endif 590 assert(0 && "Do not know how to promote this operator's operand!"); 591 abort(); 592 593 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 594 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 595 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 596 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 597 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 598 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break; 599 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break; 600 case ISD::INSERT_VECTOR_ELT: 601 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 602 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 603 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 604 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 605 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 606 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 607 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 608 OpNo); break; 609 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 610 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 611 612 case ISD::SINT_TO_FP: 613 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break; 614 } 615 } 616 617 // If the result is null, the sub-method took care of registering results etc. 618 if (!Res.getNode()) return false; 619 // If the result is N, the sub-method updated N in place. 620 if (Res.getNode() == N) { 621 // Mark N as new and remark N and its operands. This allows us to correctly 622 // revisit N if it needs another step of promotion and allows us to visit 623 // any new operands to N. 624 ReanalyzeNode(N); 625 return true; 626 } 627 628 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 629 "Invalid operand expansion"); 630 631 ReplaceValueWith(SDValue(N, 0), Res); 632 return false; 633} 634 635/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 636/// shared among BR_CC, SELECT_CC, and SETCC handlers. 637void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 638 ISD::CondCode CCCode) { 639 MVT VT = NewLHS.getValueType(); 640 641 // Get the promoted values. 642 NewLHS = GetPromotedInteger(NewLHS); 643 NewRHS = GetPromotedInteger(NewRHS); 644 645 // We have to insert explicit sign or zero extends. Note that we could 646 // insert sign extends for ALL conditions, but zero extend is cheaper on 647 // many machines (an AND instead of two shifts), so prefer it. 648 switch (CCCode) { 649 default: assert(0 && "Unknown integer comparison!"); 650 case ISD::SETEQ: 651 case ISD::SETNE: 652 case ISD::SETUGE: 653 case ISD::SETUGT: 654 case ISD::SETULE: 655 case ISD::SETULT: 656 // ALL of these operations will work if we either sign or zero extend 657 // the operands (including the unsigned comparisons!). Zero extend is 658 // usually a simpler/cheaper operation, so prefer it. 659 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT); 660 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT); 661 break; 662 case ISD::SETGE: 663 case ISD::SETGT: 664 case ISD::SETLT: 665 case ISD::SETLE: 666 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS, 667 DAG.getValueType(VT)); 668 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS, 669 DAG.getValueType(VT)); 670 break; 671 } 672} 673 674SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 675 SDValue Op = GetPromotedInteger(N->getOperand(0)); 676 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 677} 678 679SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 680 assert(OpNo == 2 && "Don't know how to promote this operand!"); 681 682 SDValue LHS = N->getOperand(2); 683 SDValue RHS = N->getOperand(3); 684 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 685 686 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 687 // legal types. 688 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 689 N->getOperand(1), LHS, RHS, N->getOperand(4)); 690} 691 692SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 693 assert(OpNo == 1 && "only know how to promote condition"); 694 SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition. 695 696 // Make sure the extra bits coming from type promotion conform to 697 // getSetCCResultContents. 698 unsigned CondBits = Cond.getValueSizeInBits(); 699 switch (TLI.getSetCCResultContents()) { 700 default: 701 assert(false && "Unknown SetCCResultValue!"); 702 case TargetLowering::UndefinedSetCCResult: 703 // The promoted value, which may contain rubbish in the upper bits, is fine. 704 break; 705 case TargetLowering::ZeroOrOneSetCCResult: 706 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1))) 707 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); 708 break; 709 case TargetLowering::ZeroOrNegativeOneSetCCResult: 710 if (DAG.ComputeNumSignBits(Cond) != CondBits) 711 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond, 712 DAG.getValueType(MVT::i1)); 713 break; 714 } 715 716 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 717 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond, 718 N->getOperand(2)); 719} 720 721SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 722 // Since the result type is legal, the operands must promote to it. 723 MVT OVT = N->getOperand(0).getValueType(); 724 SDValue Lo = GetPromotedInteger(N->getOperand(0)); 725 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 726 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 727 728 Lo = DAG.getZeroExtendInReg(Lo, OVT); 729 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi, 730 DAG.getConstant(OVT.getSizeInBits(), 731 TLI.getShiftAmountTy())); 732 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi); 733} 734 735SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 736 // The vector type is legal but the element type is not. This implies 737 // that the vector is a power-of-two in length and that the element 738 // type does not have a strange size (eg: it is not i1). 739 MVT VecVT = N->getValueType(0); 740 unsigned NumElts = VecVT.getVectorNumElements(); 741 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 742 743 // Build a vector of half the length out of elements of twice the bitwidth. 744 // For example <4 x i16> -> <2 x i32>. 745 MVT OldVT = N->getOperand(0).getValueType(); 746 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 747 assert(OldVT.isSimple() && NewVT.isSimple()); 748 749 std::vector<SDValue> NewElts; 750 NewElts.reserve(NumElts/2); 751 752 for (unsigned i = 0; i < NumElts; i += 2) { 753 // Combine two successive elements into one promoted element. 754 SDValue Lo = N->getOperand(i); 755 SDValue Hi = N->getOperand(i+1); 756 if (TLI.isBigEndian()) 757 std::swap(Lo, Hi); 758 NewElts.push_back(JoinIntegers(Lo, Hi)); 759 } 760 761 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, 762 MVT::getVectorVT(NewVT, NewElts.size()), 763 &NewElts[0], NewElts.size()); 764 765 // Convert the new vector to the old vector type. 766 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); 767} 768 769SDValue DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) { 770 SDValue Op = GetPromotedInteger(N->getOperand(0)); 771 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op); 772} 773 774SDValue DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) { 775 SDValue Op = GetPromotedInteger(N->getOperand(0)); 776 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op, 777 DAG.getIntPtrConstant(0)); 778} 779 780SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 781 unsigned OpNo) { 782 if (OpNo == 1) { 783 // Promote the inserted value. This is valid because the type does not 784 // have to match the vector element type. 785 786 // Check that any extra bits introduced will be truncated away. 787 assert(N->getOperand(1).getValueType().getSizeInBits() >= 788 N->getValueType(0).getVectorElementType().getSizeInBits() && 789 "Type of inserted value narrower than vector element type!"); 790 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 791 GetPromotedInteger(N->getOperand(1)), 792 N->getOperand(2)); 793 } 794 795 assert(OpNo == 2 && "Different operand and result vector types?"); 796 797 // Promote the index. 798 SDValue Idx = N->getOperand(2); 799 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType()); 800 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 801 N->getOperand(1), Idx); 802} 803 804SDValue DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) { 805 SDValue In = GetPromotedInteger(N->getOperand(0)); 806 MVT OpVT = N->getOperand(0).getValueType(); 807 if (N->getOpcode() == ISD::UINT_TO_FP) 808 In = DAG.getZeroExtendInReg(In, OpVT); 809 else 810 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), 811 In, DAG.getValueType(OpVT)); 812 813 return DAG.UpdateNodeOperands(SDValue(N, 0), In); 814} 815 816SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 817 SDValue NewOps[6]; 818 NewOps[0] = N->getOperand(0); 819 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 820 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 821 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); 822 } 823 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, 824 array_lengthof(NewOps)); 825} 826 827SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 828 assert(OpNo == 0 && "Only know how to promote condition"); 829 SDValue Cond = GetPromotedInteger(N->getOperand(0)); 830 831 // Promote all the way up to SVT, the canonical SetCC type. 832 // FIXME: Not clear what value to pass to getSetCCResultType. 833 // [This only matters for CellSPU since all other targets 834 // ignore the argument.] We used to pass Cond, resulting in 835 // SVT = MVT::i8, but CellSPU has no select patterns for i8, 836 // causing an abort later. Passing the result type works 837 // around the problem. 838 MVT SVT = TLI.getSetCCResultType(N->getOperand(1)); 839 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 840 assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!"); 841 842 // Make sure the extra bits conform to getSetCCResultContents. There are 843 // two sets of extra bits: those in Cond, which come from type promotion, 844 // and those we need to add to have the final type be SVT (for most targets 845 // this last set of bits is empty). 846 unsigned CondBits = Cond.getValueSizeInBits(); 847 ISD::NodeType ExtendCode; 848 switch (TLI.getSetCCResultContents()) { 849 default: 850 assert(false && "Unknown SetCCResultValue!"); 851 case TargetLowering::UndefinedSetCCResult: 852 // Extend to SVT by adding rubbish. 853 ExtendCode = ISD::ANY_EXTEND; 854 break; 855 case TargetLowering::ZeroOrOneSetCCResult: 856 ExtendCode = ISD::ZERO_EXTEND; 857 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1))) 858 // All extra bits need to be cleared. Do this by zero extending the 859 // original condition value all the way to SVT. 860 Cond = N->getOperand(0); 861 break; 862 case TargetLowering::ZeroOrNegativeOneSetCCResult: { 863 ExtendCode = ISD::SIGN_EXTEND; 864 unsigned SignBits = DAG.ComputeNumSignBits(Cond); 865 if (SignBits != CondBits) 866 // All extra bits need to be sign extended. Do this by sign extending the 867 // original condition value all the way to SVT. 868 Cond = N->getOperand(0); 869 break; 870 } 871 } 872 Cond = DAG.getNode(ExtendCode, SVT, Cond); 873 874 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, 875 N->getOperand(1), N->getOperand(2)); 876} 877 878SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 879 assert(OpNo == 0 && "Don't know how to promote this operand!"); 880 881 SDValue LHS = N->getOperand(0); 882 SDValue RHS = N->getOperand(1); 883 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 884 885 // The CC (#4) and the possible return values (#2 and #3) have legal types. 886 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2), 887 N->getOperand(3), N->getOperand(4)); 888} 889 890SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 891 assert(OpNo == 0 && "Don't know how to promote this operand!"); 892 893 SDValue LHS = N->getOperand(0); 894 SDValue RHS = N->getOperand(1); 895 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 896 897 // The CC (#2) is always legal. 898 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2)); 899} 900 901SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 902 SDValue Op = GetPromotedInteger(N->getOperand(0)); 903 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 904 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), 905 Op, DAG.getValueType(N->getOperand(0).getValueType())); 906} 907 908SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 909 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 910 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 911 int SVOffset = N->getSrcValueOffset(); 912 unsigned Alignment = N->getAlignment(); 913 bool isVolatile = N->isVolatile(); 914 915 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 916 917 assert(!N->isTruncatingStore() && "Cannot promote this store operand!"); 918 919 // Truncate the value and store the result. 920 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(), 921 SVOffset, N->getMemoryVT(), 922 isVolatile, Alignment); 923} 924 925SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 926 SDValue Op = GetPromotedInteger(N->getOperand(0)); 927 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op); 928} 929 930SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 931 SDValue Op = GetPromotedInteger(N->getOperand(0)); 932 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 933 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); 934} 935 936 937//===----------------------------------------------------------------------===// 938// Integer Result Expansion 939//===----------------------------------------------------------------------===// 940 941/// ExpandIntegerResult - This method is called when the specified result of the 942/// specified node is found to need expansion. At this point, the node may also 943/// have invalid operands or may have other results that need promotion, we just 944/// know that (at least) one result needs expansion. 945void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 946 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n"); 947 SDValue Lo, Hi; 948 Lo = Hi = SDValue(); 949 950 // See if the target wants to custom expand this node. 951 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 952 TargetLowering::Custom) { 953 // If the target wants to, allow it to lower this itself. 954 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 955 // Everything that once used N now uses P. We are guaranteed that the 956 // result value types of N and the result value types of P match. 957 ReplaceNodeWith(N, P); 958 return; 959 } 960 } 961 962 switch (N->getOpcode()) { 963 default: 964#ifndef NDEBUG 965 cerr << "ExpandIntegerResult #" << ResNo << ": "; 966 N->dump(&DAG); cerr << "\n"; 967#endif 968 assert(0 && "Do not know how to expand the result of this operator!"); 969 abort(); 970 971 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 972 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 973 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 974 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 975 976 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 977 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 978 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 979 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 980 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 981 982 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 983 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 984 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 985 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 986 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 987 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 988 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 989 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 990 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 991 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 992 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 993 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 994 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 995 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 996 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 997 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 998 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 999 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 1000 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 1001 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 1002 1003 case ISD::AND: 1004 case ISD::OR: 1005 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 1006 1007 case ISD::ADD: 1008 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1009 1010 case ISD::ADDC: 1011 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1012 1013 case ISD::ADDE: 1014 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1015 1016 case ISD::SHL: 1017 case ISD::SRA: 1018 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1019 } 1020 1021 // If Lo/Hi is null, the sub-method took care of registering results etc. 1022 if (Lo.getNode()) 1023 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1024} 1025 1026/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1027/// and the shift amount is a constant 'Amt'. Expand the operation. 1028void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1029 SDValue &Lo, SDValue &Hi) { 1030 // Expand the incoming operand to be shifted, so that we have its parts 1031 SDValue InL, InH; 1032 GetExpandedInteger(N->getOperand(0), InL, InH); 1033 1034 MVT NVT = InL.getValueType(); 1035 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1036 unsigned NVTBits = NVT.getSizeInBits(); 1037 MVT ShTy = N->getOperand(1).getValueType(); 1038 1039 if (N->getOpcode() == ISD::SHL) { 1040 if (Amt > VTBits) { 1041 Lo = Hi = DAG.getConstant(0, NVT); 1042 } else if (Amt > NVTBits) { 1043 Lo = DAG.getConstant(0, NVT); 1044 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1045 } else if (Amt == NVTBits) { 1046 Lo = DAG.getConstant(0, NVT); 1047 Hi = InL; 1048 } else if (Amt == 1) { 1049 // Emit this X << 1 as X+X. 1050 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1051 SDValue LoOps[2] = { InL, InL }; 1052 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1053 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1054 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1055 } else { 1056 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1057 Hi = DAG.getNode(ISD::OR, NVT, 1058 DAG.getNode(ISD::SHL, NVT, InH, 1059 DAG.getConstant(Amt, ShTy)), 1060 DAG.getNode(ISD::SRL, NVT, InL, 1061 DAG.getConstant(NVTBits-Amt, ShTy))); 1062 } 1063 return; 1064 } 1065 1066 if (N->getOpcode() == ISD::SRL) { 1067 if (Amt > VTBits) { 1068 Lo = DAG.getConstant(0, NVT); 1069 Hi = DAG.getConstant(0, NVT); 1070 } else if (Amt > NVTBits) { 1071 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1072 Hi = DAG.getConstant(0, NVT); 1073 } else if (Amt == NVTBits) { 1074 Lo = InH; 1075 Hi = DAG.getConstant(0, NVT); 1076 } else { 1077 Lo = DAG.getNode(ISD::OR, NVT, 1078 DAG.getNode(ISD::SRL, NVT, InL, 1079 DAG.getConstant(Amt, ShTy)), 1080 DAG.getNode(ISD::SHL, NVT, InH, 1081 DAG.getConstant(NVTBits-Amt, ShTy))); 1082 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1083 } 1084 return; 1085 } 1086 1087 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1088 if (Amt > VTBits) { 1089 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 1090 DAG.getConstant(NVTBits-1, ShTy)); 1091 } else if (Amt > NVTBits) { 1092 Lo = DAG.getNode(ISD::SRA, NVT, InH, 1093 DAG.getConstant(Amt-NVTBits, ShTy)); 1094 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1095 DAG.getConstant(NVTBits-1, ShTy)); 1096 } else if (Amt == NVTBits) { 1097 Lo = InH; 1098 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1099 DAG.getConstant(NVTBits-1, ShTy)); 1100 } else { 1101 Lo = DAG.getNode(ISD::OR, NVT, 1102 DAG.getNode(ISD::SRL, NVT, InL, 1103 DAG.getConstant(Amt, ShTy)), 1104 DAG.getNode(ISD::SHL, NVT, InH, 1105 DAG.getConstant(NVTBits-Amt, ShTy))); 1106 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy)); 1107 } 1108} 1109 1110/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1111/// this shift based on knowledge of the high bit of the shift amount. If we 1112/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1113/// shift amount. 1114bool DAGTypeLegalizer:: 1115ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1116 SDValue Amt = N->getOperand(1); 1117 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1118 MVT ShTy = Amt.getValueType(); 1119 unsigned ShBits = ShTy.getSizeInBits(); 1120 unsigned NVTBits = NVT.getSizeInBits(); 1121 assert(isPowerOf2_32(NVTBits) && 1122 "Expanded integer type size not a power of two!"); 1123 1124 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1125 APInt KnownZero, KnownOne; 1126 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1127 1128 // If we don't know anything about the high bits, exit. 1129 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1130 return false; 1131 1132 // Get the incoming operand to be shifted. 1133 SDValue InL, InH; 1134 GetExpandedInteger(N->getOperand(0), InL, InH); 1135 1136 // If we know that any of the high bits of the shift amount are one, then we 1137 // can do this as a couple of simple shifts. 1138 if (KnownOne.intersects(HighBitMask)) { 1139 // Mask out the high bit, which we know is set. 1140 Amt = DAG.getNode(ISD::AND, ShTy, Amt, 1141 DAG.getConstant(~HighBitMask, ShTy)); 1142 1143 switch (N->getOpcode()) { 1144 default: assert(0 && "Unknown shift"); 1145 case ISD::SHL: 1146 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1147 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 1148 return true; 1149 case ISD::SRL: 1150 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1151 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 1152 return true; 1153 case ISD::SRA: 1154 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 1155 DAG.getConstant(NVTBits-1, ShTy)); 1156 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 1157 return true; 1158 } 1159 } 1160 1161 // If we know that all of the high bits of the shift amount are zero, then we 1162 // can do this as a couple of simple shifts. 1163 if ((KnownZero & HighBitMask) == HighBitMask) { 1164 // Compute 32-amt. 1165 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1166 DAG.getConstant(NVTBits, ShTy), 1167 Amt); 1168 unsigned Op1, Op2; 1169 switch (N->getOpcode()) { 1170 default: assert(0 && "Unknown shift"); 1171 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1172 case ISD::SRL: 1173 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1174 } 1175 1176 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1177 Hi = DAG.getNode(ISD::OR, NVT, 1178 DAG.getNode(Op1, NVT, InH, Amt), 1179 DAG.getNode(Op2, NVT, InL, Amt2)); 1180 return true; 1181 } 1182 1183 return false; 1184} 1185 1186void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1187 SDValue &Lo, SDValue &Hi) { 1188 // Expand the subcomponents. 1189 SDValue LHSL, LHSH, RHSL, RHSH; 1190 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1191 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1192 1193 MVT NVT = LHSL.getValueType(); 1194 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1195 SDValue LoOps[2] = { LHSL, RHSL }; 1196 SDValue HiOps[3] = { LHSH, RHSH }; 1197 1198 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1199 // them. TODO: Teach operation legalization how to expand unsupported 1200 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1201 // a carry of type MVT::Flag, but there doesn't seem to be any way to 1202 // generate a value of this type in the expanded code sequence. 1203 bool hasCarry = 1204 TLI.isOperationLegal(N->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC, 1205 TLI.getTypeToExpandTo(NVT)); 1206 1207 if (hasCarry) { 1208 if (N->getOpcode() == ISD::ADD) { 1209 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1210 HiOps[2] = Lo.getValue(1); 1211 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1212 } else { 1213 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1214 HiOps[2] = Lo.getValue(1); 1215 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1216 } 1217 } else { 1218 if (N->getOpcode() == ISD::ADD) { 1219 Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2); 1220 Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2); 1221 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0], 1222 ISD::SETULT); 1223 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1, 1224 DAG.getConstant(1, NVT), 1225 DAG.getConstant(0, NVT)); 1226 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[1], 1227 ISD::SETULT); 1228 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2, 1229 DAG.getConstant(1, NVT), Carry1); 1230 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2); 1231 } else { 1232 Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2); 1233 Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2); 1234 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT); 1235 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp, 1236 DAG.getConstant(1, NVT), 1237 DAG.getConstant(0, NVT)); 1238 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow); 1239 } 1240 } 1241} 1242 1243void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1244 SDValue &Lo, SDValue &Hi) { 1245 // Expand the subcomponents. 1246 SDValue LHSL, LHSH, RHSL, RHSH; 1247 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1248 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1249 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1250 SDValue LoOps[2] = { LHSL, RHSL }; 1251 SDValue HiOps[3] = { LHSH, RHSH }; 1252 1253 if (N->getOpcode() == ISD::ADDC) { 1254 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1255 HiOps[2] = Lo.getValue(1); 1256 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1257 } else { 1258 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1259 HiOps[2] = Lo.getValue(1); 1260 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1261 } 1262 1263 // Legalized the flag result - switch anything that used the old flag to 1264 // use the new one. 1265 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1266} 1267 1268void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1269 SDValue &Lo, SDValue &Hi) { 1270 // Expand the subcomponents. 1271 SDValue LHSL, LHSH, RHSL, RHSH; 1272 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1273 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1274 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1275 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1276 SDValue HiOps[3] = { LHSH, RHSH }; 1277 1278 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3); 1279 HiOps[2] = Lo.getValue(1); 1280 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3); 1281 1282 // Legalized the flag result - switch anything that used the old flag to 1283 // use the new one. 1284 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1285} 1286 1287void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1288 SDValue &Lo, SDValue &Hi) { 1289 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1290 SDValue Op = N->getOperand(0); 1291 if (Op.getValueType().bitsLE(NVT)) { 1292 // The low part is any extension of the input (which degenerates to a copy). 1293 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op); 1294 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined. 1295 } else { 1296 // For example, extension of an i48 to an i64. The operand type necessarily 1297 // promotes to the result type, so will end up being expanded too. 1298 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1299 "Only know how to promote this result!"); 1300 SDValue Res = GetPromotedInteger(Op); 1301 assert(Res.getValueType() == N->getValueType(0) && 1302 "Operand over promoted?"); 1303 // Split the promoted operand. This will simplify when it is expanded. 1304 SplitInteger(Res, Lo, Hi); 1305 } 1306} 1307 1308void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1309 SDValue &Lo, SDValue &Hi) { 1310 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1311 MVT NVT = Lo.getValueType(); 1312 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1313 unsigned NVTBits = NVT.getSizeInBits(); 1314 unsigned EVTBits = EVT.getSizeInBits(); 1315 1316 if (NVTBits < EVTBits) { 1317 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi, 1318 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1319 } else { 1320 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT)); 1321 // The high part replicates the sign bit of Lo, make it explicit. 1322 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1323 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy())); 1324 } 1325} 1326 1327void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1328 SDValue &Lo, SDValue &Hi) { 1329 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1330 MVT NVT = Lo.getValueType(); 1331 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1332 unsigned NVTBits = NVT.getSizeInBits(); 1333 unsigned EVTBits = EVT.getSizeInBits(); 1334 1335 if (NVTBits < EVTBits) { 1336 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, 1337 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 1338 } else { 1339 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); 1340 // The high part must be zero, make it explicit. 1341 Hi = DAG.getConstant(0, NVT); 1342 } 1343} 1344 1345void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1346 SDValue &Lo, SDValue &Hi) { 1347 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1348 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo); 1349 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi); 1350} 1351 1352void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1353 SDValue &Lo, SDValue &Hi) { 1354 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1355 unsigned NBitWidth = NVT.getSizeInBits(); 1356 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1357 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 1358 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1359} 1360 1361void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1362 SDValue &Lo, SDValue &Hi) { 1363 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1364 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1365 MVT NVT = Lo.getValueType(); 1366 1367 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 1368 DAG.getConstant(0, NVT), ISD::SETNE); 1369 1370 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo); 1371 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 1372 1373 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ, 1374 DAG.getNode(ISD::ADD, NVT, LoLZ, 1375 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1376 Hi = DAG.getConstant(0, NVT); 1377} 1378 1379void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1380 SDValue &Lo, SDValue &Hi) { 1381 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1382 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1383 MVT NVT = Lo.getValueType(); 1384 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), 1385 DAG.getNode(ISD::CTPOP, NVT, Hi)); 1386 Hi = DAG.getConstant(0, NVT); 1387} 1388 1389void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1390 SDValue &Lo, SDValue &Hi) { 1391 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1392 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1393 MVT NVT = Lo.getValueType(); 1394 1395 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, 1396 DAG.getConstant(0, NVT), ISD::SETNE); 1397 1398 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 1399 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi); 1400 1401 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ, 1402 DAG.getNode(ISD::ADD, NVT, HiLZ, 1403 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1404 Hi = DAG.getConstant(0, NVT); 1405} 1406 1407void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1408 SDValue &Hi) { 1409 MVT VT = N->getValueType(0); 1410 SDValue Op = N->getOperand(0); 1411 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1412 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1413 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi); 1414} 1415 1416void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1417 SDValue &Hi) { 1418 MVT VT = N->getValueType(0); 1419 SDValue Op = N->getOperand(0); 1420 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1421 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1422 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi); 1423} 1424 1425void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1426 SDValue &Lo, SDValue &Hi) { 1427 if (ISD::isNormalLoad(N)) { 1428 ExpandRes_NormalLoad(N, Lo, Hi); 1429 return; 1430 } 1431 1432 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1433 1434 MVT VT = N->getValueType(0); 1435 MVT NVT = TLI.getTypeToTransformTo(VT); 1436 SDValue Ch = N->getChain(); 1437 SDValue Ptr = N->getBasePtr(); 1438 ISD::LoadExtType ExtType = N->getExtensionType(); 1439 int SVOffset = N->getSrcValueOffset(); 1440 unsigned Alignment = N->getAlignment(); 1441 bool isVolatile = N->isVolatile(); 1442 1443 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1444 1445 if (N->getMemoryVT().bitsLE(NVT)) { 1446 MVT EVT = N->getMemoryVT(); 1447 1448 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, 1449 isVolatile, Alignment); 1450 1451 // Remember the chain. 1452 Ch = Lo.getValue(1); 1453 1454 if (ExtType == ISD::SEXTLOAD) { 1455 // The high part is obtained by SRA'ing all but one of the bits of the 1456 // lo part. 1457 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1458 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1459 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1460 } else if (ExtType == ISD::ZEXTLOAD) { 1461 // The high part is just a zero. 1462 Hi = DAG.getConstant(0, NVT); 1463 } else { 1464 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1465 // The high part is undefined. 1466 Hi = DAG.getNode(ISD::UNDEF, NVT); 1467 } 1468 } else if (TLI.isLittleEndian()) { 1469 // Little-endian - low bits are at low addresses. 1470 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1471 isVolatile, Alignment); 1472 1473 unsigned ExcessBits = 1474 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1475 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1476 1477 // Increment the pointer to the other half. 1478 unsigned IncrementSize = NVT.getSizeInBits()/8; 1479 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1480 DAG.getIntPtrConstant(IncrementSize)); 1481 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), 1482 SVOffset+IncrementSize, NEVT, 1483 isVolatile, MinAlign(Alignment, IncrementSize)); 1484 1485 // Build a factor node to remember that this load is independent of the 1486 // other one. 1487 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1488 Hi.getValue(1)); 1489 } else { 1490 // Big-endian - high bits are at low addresses. Favor aligned loads at 1491 // the cost of some bit-fiddling. 1492 MVT EVT = N->getMemoryVT(); 1493 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1494 unsigned IncrementSize = NVT.getSizeInBits()/8; 1495 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1496 1497 // Load both the high bits and maybe some of the low bits. 1498 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1499 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1500 isVolatile, Alignment); 1501 1502 // Increment the pointer to the other half. 1503 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1504 DAG.getIntPtrConstant(IncrementSize)); 1505 // Load the rest of the low bits. 1506 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(), 1507 SVOffset+IncrementSize, 1508 MVT::getIntegerVT(ExcessBits), 1509 isVolatile, MinAlign(Alignment, IncrementSize)); 1510 1511 // Build a factor node to remember that this load is independent of the 1512 // other one. 1513 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1514 Hi.getValue(1)); 1515 1516 if (ExcessBits < NVT.getSizeInBits()) { 1517 // Transfer low bits from the bottom of Hi to the top of Lo. 1518 Lo = DAG.getNode(ISD::OR, NVT, Lo, 1519 DAG.getNode(ISD::SHL, NVT, Hi, 1520 DAG.getConstant(ExcessBits, 1521 TLI.getShiftAmountTy()))); 1522 // Move high bits to the right position in Hi. 1523 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi, 1524 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1525 TLI.getShiftAmountTy())); 1526 } 1527 } 1528 1529 // Legalized the chain result - switch anything that used the old chain to 1530 // use the new one. 1531 ReplaceValueWith(SDValue(N, 1), Ch); 1532} 1533 1534void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1535 SDValue &Lo, SDValue &Hi) { 1536 SDValue LL, LH, RL, RH; 1537 GetExpandedInteger(N->getOperand(0), LL, LH); 1538 GetExpandedInteger(N->getOperand(1), RL, RH); 1539 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL); 1540 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH); 1541} 1542 1543void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1544 SDValue &Lo, SDValue &Hi) { 1545 MVT VT = N->getValueType(0); 1546 MVT NVT = TLI.getTypeToTransformTo(VT); 1547 1548 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 1549 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 1550 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 1551 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 1552 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1553 SDValue LL, LH, RL, RH; 1554 GetExpandedInteger(N->getOperand(0), LL, LH); 1555 GetExpandedInteger(N->getOperand(1), RL, RH); 1556 unsigned OuterBitSize = VT.getSizeInBits(); 1557 unsigned InnerBitSize = NVT.getSizeInBits(); 1558 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1559 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1560 1561 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1562 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1563 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1564 // The inputs are both zero-extended. 1565 if (HasUMUL_LOHI) { 1566 // We can emit a umul_lohi. 1567 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1568 Hi = SDValue(Lo.getNode(), 1); 1569 return; 1570 } 1571 if (HasMULHU) { 1572 // We can emit a mulhu+mul. 1573 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1574 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1575 return; 1576 } 1577 } 1578 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1579 // The input values are both sign-extended. 1580 if (HasSMUL_LOHI) { 1581 // We can emit a smul_lohi. 1582 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1583 Hi = SDValue(Lo.getNode(), 1); 1584 return; 1585 } 1586 if (HasMULHS) { 1587 // We can emit a mulhs+mul. 1588 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1589 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 1590 return; 1591 } 1592 } 1593 if (HasUMUL_LOHI) { 1594 // Lo,Hi = umul LHS, RHS. 1595 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 1596 DAG.getVTList(NVT, NVT), LL, RL); 1597 Lo = UMulLOHI; 1598 Hi = UMulLOHI.getValue(1); 1599 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1600 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1601 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1602 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1603 return; 1604 } 1605 if (HasMULHU) { 1606 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1607 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1608 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1609 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1610 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1611 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1612 return; 1613 } 1614 } 1615 1616 // If nothing else, we can make a libcall. 1617 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1618 if (VT == MVT::i32) 1619 LC = RTLIB::MUL_I32; 1620 else if (VT == MVT::i64) 1621 LC = RTLIB::MUL_I64; 1622 else if (VT == MVT::i128) 1623 LC = RTLIB::MUL_I128; 1624 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1625 1626 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1627 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi); 1628} 1629 1630void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1631 SDValue &Lo, SDValue &Hi) { 1632 MVT VT = N->getValueType(0); 1633 1634 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1635 if (VT == MVT::i32) 1636 LC = RTLIB::SDIV_I32; 1637 else if (VT == MVT::i64) 1638 LC = RTLIB::SDIV_I64; 1639 else if (VT == MVT::i128) 1640 LC = RTLIB::SDIV_I128; 1641 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1642 1643 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1644 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1645} 1646 1647void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1648 SDValue &Lo, SDValue &Hi) { 1649 MVT VT = N->getValueType(0); 1650 1651 // If we can emit an efficient shift operation, do so now. Check to see if 1652 // the RHS is a constant. 1653 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1654 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1655 1656 // If we can determine that the high bit of the shift is zero or one, even if 1657 // the low bits are variable, emit this shift in an optimized form. 1658 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1659 return; 1660 1661 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1662 unsigned PartsOpc; 1663 if (N->getOpcode() == ISD::SHL) { 1664 PartsOpc = ISD::SHL_PARTS; 1665 } else if (N->getOpcode() == ISD::SRL) { 1666 PartsOpc = ISD::SRL_PARTS; 1667 } else { 1668 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1669 PartsOpc = ISD::SRA_PARTS; 1670 } 1671 1672 // Next check to see if the target supports this SHL_PARTS operation or if it 1673 // will custom expand it. 1674 MVT NVT = TLI.getTypeToTransformTo(VT); 1675 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1676 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1677 Action == TargetLowering::Custom) { 1678 // Expand the subcomponents. 1679 SDValue LHSL, LHSH; 1680 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1681 1682 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1683 MVT VT = LHSL.getValueType(); 1684 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 1685 Hi = Lo.getValue(1); 1686 return; 1687 } 1688 1689 // Otherwise, emit a libcall. 1690 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1691 bool isSigned; 1692 if (N->getOpcode() == ISD::SHL) { 1693 isSigned = false; /*sign irrelevant*/ 1694 if (VT == MVT::i32) 1695 LC = RTLIB::SHL_I32; 1696 else if (VT == MVT::i64) 1697 LC = RTLIB::SHL_I64; 1698 else if (VT == MVT::i128) 1699 LC = RTLIB::SHL_I128; 1700 } else if (N->getOpcode() == ISD::SRL) { 1701 isSigned = false; 1702 if (VT == MVT::i32) 1703 LC = RTLIB::SRL_I32; 1704 else if (VT == MVT::i64) 1705 LC = RTLIB::SRL_I64; 1706 else if (VT == MVT::i128) 1707 LC = RTLIB::SRL_I128; 1708 } else { 1709 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1710 isSigned = true; 1711 if (VT == MVT::i32) 1712 LC = RTLIB::SRA_I32; 1713 else if (VT == MVT::i64) 1714 LC = RTLIB::SRA_I64; 1715 else if (VT == MVT::i128) 1716 LC = RTLIB::SRA_I128; 1717 } 1718 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!"); 1719 1720 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1721 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi); 1722} 1723 1724void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 1725 SDValue &Lo, SDValue &Hi) { 1726 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1727 SDValue Op = N->getOperand(0); 1728 if (Op.getValueType().bitsLE(NVT)) { 1729 // The low part is sign extension of the input (degenerates to a copy). 1730 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); 1731 // The high part is obtained by SRA'ing all but one of the bits of low part. 1732 unsigned LoSize = NVT.getSizeInBits(); 1733 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1734 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1735 } else { 1736 // For example, extension of an i48 to an i64. The operand type necessarily 1737 // promotes to the result type, so will end up being expanded too. 1738 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1739 "Only know how to promote this result!"); 1740 SDValue Res = GetPromotedInteger(Op); 1741 assert(Res.getValueType() == N->getValueType(0) && 1742 "Operand over promoted?"); 1743 // Split the promoted operand. This will simplify when it is expanded. 1744 SplitInteger(Res, Lo, Hi); 1745 unsigned ExcessBits = 1746 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1747 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 1748 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1749 } 1750} 1751 1752void DAGTypeLegalizer:: 1753ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 1754 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1755 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1756 1757 if (EVT.bitsLE(Lo.getValueType())) { 1758 // sext_inreg the low part if needed. 1759 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo, 1760 N->getOperand(1)); 1761 1762 // The high part gets the sign extension from the lo-part. This handles 1763 // things like sextinreg V:i64 from i8. 1764 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo, 1765 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 1766 TLI.getShiftAmountTy())); 1767 } else { 1768 // For example, extension of an i48 to an i64. Leave the low part alone, 1769 // sext_inreg the high part. 1770 unsigned ExcessBits = 1771 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 1772 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 1773 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 1774 } 1775} 1776 1777void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1778 SDValue &Lo, SDValue &Hi) { 1779 MVT VT = N->getValueType(0); 1780 1781 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1782 if (VT == MVT::i32) 1783 LC = RTLIB::SREM_I32; 1784 else if (VT == MVT::i64) 1785 LC = RTLIB::SREM_I64; 1786 else if (VT == MVT::i128) 1787 LC = RTLIB::SREM_I128; 1788 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1789 1790 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1791 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1792} 1793 1794void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 1795 SDValue &Lo, SDValue &Hi) { 1796 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1797 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); 1798 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), 1799 DAG.getConstant(NVT.getSizeInBits(), 1800 TLI.getShiftAmountTy())); 1801 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); 1802} 1803 1804void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1805 SDValue &Lo, SDValue &Hi) { 1806 MVT VT = N->getValueType(0); 1807 1808 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1809 if (VT == MVT::i32) 1810 LC = RTLIB::UDIV_I32; 1811 else if (VT == MVT::i64) 1812 LC = RTLIB::UDIV_I64; 1813 else if (VT == MVT::i128) 1814 LC = RTLIB::UDIV_I128; 1815 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 1816 1817 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1818 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1819} 1820 1821void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1822 SDValue &Lo, SDValue &Hi) { 1823 MVT VT = N->getValueType(0); 1824 1825 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1826 if (VT == MVT::i32) 1827 LC = RTLIB::UREM_I32; 1828 else if (VT == MVT::i64) 1829 LC = RTLIB::UREM_I64; 1830 else if (VT == MVT::i128) 1831 LC = RTLIB::UREM_I128; 1832 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 1833 1834 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1835 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1836} 1837 1838void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 1839 SDValue &Lo, SDValue &Hi) { 1840 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1841 SDValue Op = N->getOperand(0); 1842 if (Op.getValueType().bitsLE(NVT)) { 1843 // The low part is zero extension of the input (degenerates to a copy). 1844 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); 1845 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 1846 } else { 1847 // For example, extension of an i48 to an i64. The operand type necessarily 1848 // promotes to the result type, so will end up being expanded too. 1849 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1850 "Only know how to promote this result!"); 1851 SDValue Res = GetPromotedInteger(Op); 1852 assert(Res.getValueType() == N->getValueType(0) && 1853 "Operand over promoted?"); 1854 // Split the promoted operand. This will simplify when it is expanded. 1855 SplitInteger(Res, Lo, Hi); 1856 unsigned ExcessBits = 1857 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 1858 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); 1859 } 1860} 1861 1862 1863//===----------------------------------------------------------------------===// 1864// Integer Operand Expansion 1865//===----------------------------------------------------------------------===// 1866 1867/// ExpandIntegerOperand - This method is called when the specified operand of 1868/// the specified node is found to need expansion. At this point, all of the 1869/// result types of the node are known to be legal, but other operands of the 1870/// node may need promotion or expansion as well as the specified one. 1871bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1872 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); 1873 SDValue Res = SDValue(); 1874 1875 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 1876 == TargetLowering::Custom) 1877 Res = TLI.LowerOperation(SDValue(N, 0), DAG); 1878 1879 if (Res.getNode() == 0) { 1880 switch (N->getOpcode()) { 1881 default: 1882 #ifndef NDEBUG 1883 cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; 1884 N->dump(&DAG); cerr << "\n"; 1885 #endif 1886 assert(0 && "Do not know how to expand this operator's operand!"); 1887 abort(); 1888 1889 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1890 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1891 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1892 1893 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1894 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1895 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1896 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 1897 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); 1898 break; 1899 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1900 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 1901 } 1902 } 1903 1904 // If the result is null, the sub-method took care of registering results etc. 1905 if (!Res.getNode()) return false; 1906 // If the result is N, the sub-method updated N in place. Check to see if any 1907 // operands are new, and if so, mark them. 1908 if (Res.getNode() == N) { 1909 // Mark N as new and remark N and its operands. This allows us to correctly 1910 // revisit N if it needs another step of expansion and allows us to visit 1911 // any new operands to N. 1912 ReanalyzeNode(N); 1913 return true; 1914 } 1915 1916 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1917 "Invalid operand expansion"); 1918 1919 ReplaceValueWith(SDValue(N, 0), Res); 1920 return false; 1921} 1922 1923/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 1924/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1925void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 1926 SDValue &NewRHS, 1927 ISD::CondCode &CCCode) { 1928 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 1929 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 1930 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 1931 1932 MVT VT = NewLHS.getValueType(); 1933 1934 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 1935 if (RHSLo == RHSHi) { 1936 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 1937 if (RHSCST->isAllOnesValue()) { 1938 // Equality comparison to -1. 1939 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1940 NewRHS = RHSLo; 1941 return; 1942 } 1943 } 1944 } 1945 1946 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1947 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1948 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS); 1949 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1950 return; 1951 } 1952 1953 // If this is a comparison of the sign bit, just look at the top part. 1954 // X > -1, x < 0 1955 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 1956 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 1957 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 1958 NewLHS = LHSHi; 1959 NewRHS = RHSHi; 1960 return; 1961 } 1962 1963 // FIXME: This generated code sucks. 1964 ISD::CondCode LowCC; 1965 switch (CCCode) { 1966 default: assert(0 && "Unknown integer setcc!"); 1967 case ISD::SETLT: 1968 case ISD::SETULT: LowCC = ISD::SETULT; break; 1969 case ISD::SETGT: 1970 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1971 case ISD::SETLE: 1972 case ISD::SETULE: LowCC = ISD::SETULE; break; 1973 case ISD::SETGE: 1974 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 1975 } 1976 1977 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 1978 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 1979 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 1980 1981 // NOTE: on targets without efficient SELECT of bools, we can always use 1982 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 1983 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 1984 SDValue Tmp1, Tmp2; 1985 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC, 1986 false, DagCombineInfo); 1987 if (!Tmp1.getNode()) 1988 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 1989 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1990 CCCode, false, DagCombineInfo); 1991 if (!Tmp2.getNode()) 1992 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 1993 DAG.getCondCode(CCCode)); 1994 1995 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 1996 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 1997 if ((Tmp1C && Tmp1C->isNullValue()) || 1998 (Tmp2C && Tmp2C->isNullValue() && 1999 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2000 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2001 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2002 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2003 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2004 // low part is known false, returns high part. 2005 // For LE / GE, if high part is known false, ignore the low part. 2006 // For LT / GT, if high part is known true, ignore the low part. 2007 NewLHS = Tmp2; 2008 NewRHS = SDValue(); 2009 return; 2010 } 2011 2012 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2013 ISD::SETEQ, false, DagCombineInfo); 2014 if (!NewLHS.getNode()) 2015 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2016 ISD::SETEQ); 2017 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 2018 NewLHS, Tmp1, Tmp2); 2019 NewRHS = SDValue(); 2020} 2021 2022SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2023 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2024 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2025 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2026 2027 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2028 // against zero to select between true and false values. 2029 if (NewRHS.getNode() == 0) { 2030 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2031 CCCode = ISD::SETNE; 2032 } 2033 2034 // Update N to have the operands specified. 2035 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), 2036 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2037 N->getOperand(4)); 2038} 2039 2040SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2041 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2042 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2043 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2044 2045 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2046 // against zero to select between true and false values. 2047 if (NewRHS.getNode() == 0) { 2048 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2049 CCCode = ISD::SETNE; 2050 } 2051 2052 // Update N to have the operands specified. 2053 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2054 N->getOperand(2), N->getOperand(3), 2055 DAG.getCondCode(CCCode)); 2056} 2057 2058SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2059 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2060 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2061 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 2062 2063 // If ExpandSetCCOperands returned a scalar, use it. 2064 if (NewRHS.getNode() == 0) { 2065 assert(NewLHS.getValueType() == N->getValueType(0) && 2066 "Unexpected setcc expansion!"); 2067 return NewLHS; 2068 } 2069 2070 // Otherwise, update N to have the operands specified. 2071 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS, 2072 DAG.getCondCode(CCCode)); 2073} 2074 2075SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2076 SDValue Op = N->getOperand(0); 2077 MVT DstVT = N->getValueType(0); 2078 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2079 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2080 "Don't know how to expand this SINT_TO_FP!"); 2081 return MakeLibCall(LC, DstVT, &Op, 1, true); 2082} 2083 2084SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2085 if (ISD::isNormalStore(N)) 2086 return ExpandOp_NormalStore(N, OpNo); 2087 2088 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2089 assert(OpNo == 1 && "Can only expand the stored value so far"); 2090 2091 MVT VT = N->getOperand(1).getValueType(); 2092 MVT NVT = TLI.getTypeToTransformTo(VT); 2093 SDValue Ch = N->getChain(); 2094 SDValue Ptr = N->getBasePtr(); 2095 int SVOffset = N->getSrcValueOffset(); 2096 unsigned Alignment = N->getAlignment(); 2097 bool isVolatile = N->isVolatile(); 2098 SDValue Lo, Hi; 2099 2100 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2101 2102 if (N->getMemoryVT().bitsLE(NVT)) { 2103 GetExpandedInteger(N->getValue(), Lo, Hi); 2104 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 2105 N->getMemoryVT(), isVolatile, Alignment); 2106 } else if (TLI.isLittleEndian()) { 2107 // Little-endian - low bits are at low addresses. 2108 GetExpandedInteger(N->getValue(), Lo, Hi); 2109 2110 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 2111 isVolatile, Alignment); 2112 2113 unsigned ExcessBits = 2114 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2115 MVT NEVT = MVT::getIntegerVT(ExcessBits); 2116 2117 // Increment the pointer to the other half. 2118 unsigned IncrementSize = NVT.getSizeInBits()/8; 2119 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2120 DAG.getIntPtrConstant(IncrementSize)); 2121 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2122 SVOffset+IncrementSize, NEVT, 2123 isVolatile, MinAlign(Alignment, IncrementSize)); 2124 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2125 } else { 2126 // Big-endian - high bits are at low addresses. Favor aligned stores at 2127 // the cost of some bit-fiddling. 2128 GetExpandedInteger(N->getValue(), Lo, Hi); 2129 2130 MVT EVT = N->getMemoryVT(); 2131 unsigned EBytes = EVT.getStoreSizeInBits()/8; 2132 unsigned IncrementSize = NVT.getSizeInBits()/8; 2133 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2134 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 2135 2136 if (ExcessBits < NVT.getSizeInBits()) { 2137 // Transfer high bits from the top of Lo to the bottom of Hi. 2138 Hi = DAG.getNode(ISD::SHL, NVT, Hi, 2139 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2140 TLI.getShiftAmountTy())); 2141 Hi = DAG.getNode(ISD::OR, NVT, Hi, 2142 DAG.getNode(ISD::SRL, NVT, Lo, 2143 DAG.getConstant(ExcessBits, 2144 TLI.getShiftAmountTy()))); 2145 } 2146 2147 // Store both the high bits and maybe some of the low bits. 2148 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2149 SVOffset, HiVT, isVolatile, Alignment); 2150 2151 // Increment the pointer to the other half. 2152 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2153 DAG.getIntPtrConstant(IncrementSize)); 2154 // Store the lowest ExcessBits bits in the second half. 2155 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), 2156 SVOffset+IncrementSize, 2157 MVT::getIntegerVT(ExcessBits), 2158 isVolatile, MinAlign(Alignment, IncrementSize)); 2159 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2160 } 2161} 2162 2163SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2164 SDValue InL, InH; 2165 GetExpandedInteger(N->getOperand(0), InL, InH); 2166 // Just truncate the low part of the source. 2167 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL); 2168} 2169 2170SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2171 SDValue Op = N->getOperand(0); 2172 MVT SrcVT = Op.getValueType(); 2173 MVT DstVT = N->getValueType(0); 2174 2175 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2176 // Do a signed conversion then adjust the result. 2177 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op); 2178 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2179 2180 // The result of the signed conversion needs adjusting if the 'sign bit' of 2181 // the incoming integer was set. To handle this, we dynamically test to see 2182 // if it is set, and, if so, add a fudge factor. 2183 2184 const uint64_t F32TwoE32 = 0x4F800000ULL; 2185 const uint64_t F32TwoE64 = 0x5F800000ULL; 2186 const uint64_t F32TwoE128 = 0x7F800000ULL; 2187 2188 APInt FF(32, 0); 2189 if (SrcVT == MVT::i32) 2190 FF = APInt(32, F32TwoE32); 2191 else if (SrcVT == MVT::i64) 2192 FF = APInt(32, F32TwoE64); 2193 else if (SrcVT == MVT::i128) 2194 FF = APInt(32, F32TwoE128); 2195 else 2196 assert(false && "Unsupported UINT_TO_FP!"); 2197 2198 // Check whether the sign bit is set. 2199 SDValue Lo, Hi; 2200 GetExpandedInteger(Op, Lo, Hi); 2201 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 2202 DAG.getConstant(0, Hi.getValueType()), 2203 ISD::SETLT); 2204 2205 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2206 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)), 2207 TLI.getPointerTy()); 2208 2209 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2210 SDValue Zero = DAG.getIntPtrConstant(0); 2211 SDValue Four = DAG.getIntPtrConstant(4); 2212 if (TLI.isBigEndian()) std::swap(Zero, Four); 2213 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet, 2214 Zero, Four); 2215 unsigned Alignment = 2216 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2217 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset); 2218 Alignment = std::min(Alignment, 4u); 2219 2220 // Load the value out, extending it from f32 to the destination float type. 2221 // FIXME: Avoid the extend by constructing the right constant pool? 2222 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(), 2223 FudgePtr, NULL, 0, MVT::f32, 2224 false, Alignment); 2225 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge); 2226 } 2227 2228 // Otherwise, use a libcall. 2229 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2230 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2231 "Don't know how to expand this UINT_TO_FP!"); 2232 return MakeLibCall(LC, DstVT, &Op, 1, true); 2233} 2234