LegalizeIntegerTypes.cpp revision 81c5ef8649e12ac6083307bb149fd7006d9e0501
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22#include "llvm/CodeGen/PseudoSourceValue.h" 23#include "llvm/Support/ErrorHandling.h" 24#include "llvm/Support/raw_ostream.h" 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28// Integer Result Promotion 29//===----------------------------------------------------------------------===// 30 31/// PromoteIntegerResult - This method is called when a result of a node is 32/// found to be in need of promotion to a larger type. At this point, the node 33/// may also have invalid operands or may have other results that need 34/// expansion, we just know that (at least) one result needs promotion. 35void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n"); 37 SDValue Res = SDValue(); 38 39 // See if the target wants to custom expand this node. 40 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 41 return; 42 43 switch (N->getOpcode()) { 44 default: 45#ifndef NDEBUG 46 dbgs() << "PromoteIntegerResult #" << ResNo << ": "; 47 N->dump(&DAG); dbgs() << "\n"; 48#endif 49 llvm_unreachable("Do not know how to promote this operator!"); 50 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 51 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 52 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; 53 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 54 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 55 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 56 case ISD::CONVERT_RNDSAT: 57 Res = PromoteIntRes_CONVERT_RNDSAT(N); break; 58 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; 59 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break; 60 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; 61 case ISD::EXTRACT_VECTOR_ELT: 62 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 63 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 64 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break; 65 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; 66 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; 67 case ISD::SHL: Res = PromoteIntRes_SHL(N); break; 68 case ISD::SIGN_EXTEND_INREG: 69 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 70 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 71 case ISD::SRL: Res = PromoteIntRes_SRL(N); break; 72 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; 73 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; 74 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; 75 76 case ISD::SIGN_EXTEND: 77 case ISD::ZERO_EXTEND: 78 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; 79 80 case ISD::FP_TO_SINT: 81 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; 82 83 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break; 84 85 case ISD::AND: 86 case ISD::OR: 87 case ISD::XOR: 88 case ISD::ADD: 89 case ISD::SUB: 90 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break; 91 92 case ISD::SDIV: 93 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; 94 95 case ISD::UDIV: 96 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break; 97 98 case ISD::SADDO: 99 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; 100 case ISD::UADDO: 101 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; 102 case ISD::SMULO: 103 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; 104 105 case ISD::ATOMIC_LOAD_ADD: 106 case ISD::ATOMIC_LOAD_SUB: 107 case ISD::ATOMIC_LOAD_AND: 108 case ISD::ATOMIC_LOAD_OR: 109 case ISD::ATOMIC_LOAD_XOR: 110 case ISD::ATOMIC_LOAD_NAND: 111 case ISD::ATOMIC_LOAD_MIN: 112 case ISD::ATOMIC_LOAD_MAX: 113 case ISD::ATOMIC_LOAD_UMIN: 114 case ISD::ATOMIC_LOAD_UMAX: 115 case ISD::ATOMIC_SWAP: 116 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; 117 118 case ISD::ATOMIC_CMP_SWAP: 119 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; 120 } 121 122 // If the result is null then the sub-method took care of registering it. 123 if (Res.getNode()) 124 SetPromotedInteger(SDValue(N, ResNo), Res); 125} 126 127SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { 128 // Sign-extend the new bits, and continue the assertion. 129 SDValue Op = SExtPromotedInteger(N->getOperand(0)); 130 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(), 131 Op.getValueType(), Op, N->getOperand(1)); 132} 133 134SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) { 135 // Zero the new bits, and continue the assertion. 136 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 137 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), 138 Op.getValueType(), Op, N->getOperand(1)); 139} 140 141SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) { 142 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 143 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 144 N->getMemoryVT(), 145 N->getChain(), N->getBasePtr(), 146 Op2, N->getMemOperand()); 147 // Legalized the chain result - switch anything that used the old chain to 148 // use the new one. 149 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 150 return Res; 151} 152 153SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { 154 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); 155 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 156 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), 157 N->getMemoryVT(), N->getChain(), N->getBasePtr(), 158 Op2, Op3, N->getMemOperand()); 159 // Legalized the chain result - switch anything that used the old chain to 160 // use the new one. 161 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 162 return Res; 163} 164 165SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) { 166 SDValue InOp = N->getOperand(0); 167 EVT InVT = InOp.getValueType(); 168 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); 169 EVT OutVT = N->getValueType(0); 170 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); 171 DebugLoc dl = N->getDebugLoc(); 172 173 switch (getTypeAction(InVT)) { 174 default: 175 assert(false && "Unknown type action!"); 176 break; 177 case Legal: 178 break; 179 case PromoteInteger: 180 if (NOutVT.bitsEq(NInVT)) 181 // The input promotes to the same size. Convert the promoted value. 182 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); 183 break; 184 case SoftenFloat: 185 // Promote the integer operand by hand. 186 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); 187 case ExpandInteger: 188 case ExpandFloat: 189 break; 190 case ScalarizeVector: 191 // Convert the element to an integer and promote it by hand. 192 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 193 BitConvertToInteger(GetScalarizedVector(InOp))); 194 case SplitVector: { 195 // For example, i32 = BITCAST v2i16 on alpha. Convert the split 196 // pieces of the input into integers and reassemble in the final type. 197 SDValue Lo, Hi; 198 GetSplitVector(N->getOperand(0), Lo, Hi); 199 Lo = BitConvertToInteger(Lo); 200 Hi = BitConvertToInteger(Hi); 201 202 if (TLI.isBigEndian()) 203 std::swap(Lo, Hi); 204 205 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, 206 EVT::getIntegerVT(*DAG.getContext(), 207 NOutVT.getSizeInBits()), 208 JoinIntegers(Lo, Hi)); 209 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); 210 } 211 case WidenVector: 212 if (OutVT.bitsEq(NInVT)) 213 // The input is widened to the same size. Convert to the widened value. 214 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp)); 215 } 216 217 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, 218 CreateStackStoreLoad(InOp, OutVT)); 219} 220 221SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { 222 SDValue Op = GetPromotedInteger(N->getOperand(0)); 223 EVT OVT = N->getValueType(0); 224 EVT NVT = Op.getValueType(); 225 DebugLoc dl = N->getDebugLoc(); 226 227 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 228 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), 229 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT))); 230} 231 232SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 233 // The pair element type may be legal, or may not promote to the same type as 234 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 235 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), 236 TLI.getTypeToTransformTo(*DAG.getContext(), 237 N->getValueType(0)), JoinIntegers(N->getOperand(0), 238 N->getOperand(1))); 239} 240 241SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 242 EVT VT = N->getValueType(0); 243 // FIXME there is no actual debug info here 244 DebugLoc dl = N->getDebugLoc(); 245 // Zero extend things like i1, sign extend everything else. It shouldn't 246 // matter in theory which one we pick, but this tends to give better code? 247 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 248 SDValue Result = DAG.getNode(Opc, dl, 249 TLI.getTypeToTransformTo(*DAG.getContext(), VT), 250 SDValue(N, 0)); 251 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 252 return Result; 253} 254 255SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { 256 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 257 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 258 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 259 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && 260 "can only promote integers"); 261 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 262 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0), 263 N->getOperand(1), N->getOperand(2), 264 N->getOperand(3), N->getOperand(4), CvtCode); 265} 266 267SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 268 // Zero extend to the promoted type and do the count there. 269 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 270 DebugLoc dl = N->getDebugLoc(); 271 EVT OVT = N->getValueType(0); 272 EVT NVT = Op.getValueType(); 273 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op); 274 // Subtract off the extra leading bits in the bigger type. 275 return DAG.getNode(ISD::SUB, dl, NVT, Op, 276 DAG.getConstant(NVT.getSizeInBits() - 277 OVT.getSizeInBits(), NVT)); 278} 279 280SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 281 // Zero extend to the promoted type and do the count there. 282 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); 283 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op); 284} 285 286SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 287 SDValue Op = GetPromotedInteger(N->getOperand(0)); 288 EVT OVT = N->getValueType(0); 289 EVT NVT = Op.getValueType(); 290 DebugLoc dl = N->getDebugLoc(); 291 // The count is the same in the promoted type except if the original 292 // value was zero. This can be handled by setting the bit just off 293 // the top of the original type. 294 APInt TopBit(NVT.getSizeInBits(), 0); 295 TopBit.setBit(OVT.getSizeInBits()); 296 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT)); 297 return DAG.getNode(ISD::CTTZ, dl, NVT, Op); 298} 299 300SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 301 DebugLoc dl = N->getDebugLoc(); 302 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 303 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0), 304 N->getOperand(1)); 305} 306 307SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 308 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 309 unsigned NewOpc = N->getOpcode(); 310 DebugLoc dl = N->getDebugLoc(); 311 312 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is 313 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT 314 // and SINT conversions are Custom, there is no way to tell which is 315 // preferable. We choose SINT because that's the right thing on PPC.) 316 if (N->getOpcode() == ISD::FP_TO_UINT && 317 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 318 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) 319 NewOpc = ISD::FP_TO_SINT; 320 321 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0)); 322 323 // Assert that the converted value fits in the original type. If it doesn't 324 // (eg: because the value being converted is too big), then the result of the 325 // original operation was undefined anyway, so the assert is still correct. 326 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ? 327 ISD::AssertZext : ISD::AssertSext, dl, 328 NVT, Res, DAG.getValueType(N->getValueType(0))); 329} 330 331SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) { 332 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 333 DebugLoc dl = N->getDebugLoc(); 334 335 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 336 337 return DAG.getNode(ISD::AssertZext, dl, 338 NVT, Res, DAG.getValueType(N->getValueType(0))); 339} 340 341SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 342 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 343 DebugLoc dl = N->getDebugLoc(); 344 345 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 346 SDValue Res = GetPromotedInteger(N->getOperand(0)); 347 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); 348 349 // If the result and operand types are the same after promotion, simplify 350 // to an in-register extension. 351 if (NVT == Res.getValueType()) { 352 // The high bits are not guaranteed to be anything. Insert an extend. 353 if (N->getOpcode() == ISD::SIGN_EXTEND) 354 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 355 DAG.getValueType(N->getOperand(0).getValueType())); 356 if (N->getOpcode() == ISD::ZERO_EXTEND) 357 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType()); 358 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 359 return Res; 360 } 361 } 362 363 // Otherwise, just extend the original operand all the way to the larger type. 364 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); 365} 366 367SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 368 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 369 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 370 ISD::LoadExtType ExtType = 371 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 372 DebugLoc dl = N->getDebugLoc(); 373 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), 374 N->getPointerInfo(), 375 N->getMemoryVT(), N->isVolatile(), 376 N->isNonTemporal(), N->getAlignment()); 377 378 // Legalized the chain result - switch anything that used the old chain to 379 // use the new one. 380 ReplaceValueWith(SDValue(N, 1), Res.getValue(1)); 381 return Res; 382} 383 384/// Promote the overflow flag of an overflowing arithmetic node. 385SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { 386 // Simply change the return type of the boolean result. 387 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1)); 388 EVT ValueVTs[] = { N->getValueType(0), NVT }; 389 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; 390 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), 391 DAG.getVTList(ValueVTs, 2), Ops, 2); 392 393 // Modified the sum result - switch anything that used the old sum to use 394 // the new one. 395 ReplaceValueWith(SDValue(N, 0), Res); 396 397 return SDValue(Res.getNode(), 1); 398} 399 400SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { 401 if (ResNo == 1) 402 return PromoteIntRes_Overflow(N); 403 404 // The operation overflowed iff the result in the larger type is not the 405 // sign extension of its truncation to the original type. 406 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 407 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 408 EVT OVT = N->getOperand(0).getValueType(); 409 EVT NVT = LHS.getValueType(); 410 DebugLoc dl = N->getDebugLoc(); 411 412 // Do the arithmetic in the larger type. 413 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 414 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 415 416 // Calculate the overflow flag: sign extend the arithmetic result from 417 // the original type. 418 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res, 419 DAG.getValueType(OVT)); 420 // Overflowed if and only if this is not equal to Res. 421 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 422 423 // Use the calculated overflow everywhere. 424 ReplaceValueWith(SDValue(N, 1), Ofl); 425 426 return Res; 427} 428 429SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 430 // Sign extend the input. 431 SDValue LHS = SExtPromotedInteger(N->getOperand(0)); 432 SDValue RHS = SExtPromotedInteger(N->getOperand(1)); 433 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 434 LHS.getValueType(), LHS, RHS); 435} 436 437SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 438 SDValue LHS = GetPromotedInteger(N->getOperand(1)); 439 SDValue RHS = GetPromotedInteger(N->getOperand(2)); 440 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), 441 LHS.getValueType(), N->getOperand(0),LHS,RHS); 442} 443 444SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 445 SDValue LHS = GetPromotedInteger(N->getOperand(2)); 446 SDValue RHS = GetPromotedInteger(N->getOperand(3)); 447 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), 448 LHS.getValueType(), N->getOperand(0), 449 N->getOperand(1), LHS, RHS, N->getOperand(4)); 450} 451 452SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 453 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); 454 assert(isTypeLegal(SVT) && "Illegal SetCC type!"); 455 DebugLoc dl = N->getDebugLoc(); 456 457 // Get the SETCC result using the canonical SETCC type. 458 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0), 459 N->getOperand(1), N->getOperand(2)); 460 461 // Convert to the expected type. 462 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 463 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); 464 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); 465} 466 467SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 468 return DAG.getNode(ISD::SHL, N->getDebugLoc(), 469 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)), 470 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 471} 472 473SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 474 SDValue Op = GetPromotedInteger(N->getOperand(0)); 475 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), 476 Op.getValueType(), Op, N->getOperand(1)); 477} 478 479SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 480 // The input may have strange things in the top bits of the registers, but 481 // these operations don't care. They may have weird bits going out, but 482 // that too is okay if they are integer operations. 483 SDValue LHS = GetPromotedInteger(N->getOperand(0)); 484 SDValue RHS = GetPromotedInteger(N->getOperand(1)); 485 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 486 LHS.getValueType(), LHS, RHS); 487} 488 489SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 490 // The input value must be properly sign extended. 491 SDValue Res = SExtPromotedInteger(N->getOperand(0)); 492 return DAG.getNode(ISD::SRA, N->getDebugLoc(), 493 Res.getValueType(), Res, N->getOperand(1)); 494} 495 496SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 497 // The input value must be properly zero extended. 498 EVT VT = N->getValueType(0); 499 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 500 SDValue Res = ZExtPromotedInteger(N->getOperand(0)); 501 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); 502} 503 504SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 505 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 506 SDValue Res; 507 508 switch (getTypeAction(N->getOperand(0).getValueType())) { 509 default: llvm_unreachable("Unknown type action!"); 510 case Legal: 511 case ExpandInteger: 512 Res = N->getOperand(0); 513 break; 514 case PromoteInteger: 515 Res = GetPromotedInteger(N->getOperand(0)); 516 break; 517 } 518 519 // Truncate to NVT instead of VT 520 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res); 521} 522 523SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { 524 if (ResNo == 1) 525 return PromoteIntRes_Overflow(N); 526 527 // The operation overflowed iff the result in the larger type is not the 528 // zero extension of its truncation to the original type. 529 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 530 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 531 EVT OVT = N->getOperand(0).getValueType(); 532 EVT NVT = LHS.getValueType(); 533 DebugLoc dl = N->getDebugLoc(); 534 535 // Do the arithmetic in the larger type. 536 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 537 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS); 538 539 // Calculate the overflow flag: zero extend the arithmetic result from 540 // the original type. 541 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); 542 // Overflowed if and only if this is not equal to Res. 543 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); 544 545 // Use the calculated overflow everywhere. 546 ReplaceValueWith(SDValue(N, 1), Ofl); 547 548 return Res; 549} 550 551SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) { 552 // Promote the overflow bit trivially. 553 if (ResNo == 1) 554 return PromoteIntRes_Overflow(N); 555 556 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1); 557 DebugLoc DL = N->getDebugLoc(); 558 EVT SmallVT = LHS.getValueType(); 559 560 // To determine if the result overflowed in a larger type, we extend the input 561 // to the larger type, do the multiply, then check the high bits of the result 562 // to see if the overflow happened. 563 if (N->getOpcode() == ISD::SMULO) { 564 LHS = SExtPromotedInteger(LHS); 565 RHS = SExtPromotedInteger(RHS); 566 } else { 567 LHS = ZExtPromotedInteger(LHS); 568 RHS = ZExtPromotedInteger(RHS); 569 } 570 SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS); 571 572 // Overflow occurred iff the high part of the result does not zero/sign-extend 573 // the low part. 574 SDValue Overflow; 575 if (N->getOpcode() == ISD::UMULO) { 576 // Unsigned overflow occurred iff the high part is non-zero. 577 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul, 578 DAG.getIntPtrConstant(SmallVT.getSizeInBits())); 579 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi, 580 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE); 581 } else { 582 // Signed overflow occurred iff the high part does not sign extend the low. 583 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(), 584 Mul, DAG.getValueType(SmallVT)); 585 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE); 586 } 587 588 // Use the calculated overflow everywhere. 589 ReplaceValueWith(SDValue(N, 1), Overflow); 590 return Mul; 591} 592 593SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 594 // Zero extend the input. 595 SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); 596 SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); 597 return DAG.getNode(N->getOpcode(), N->getDebugLoc(), 598 LHS.getValueType(), LHS, RHS); 599} 600 601SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 602 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(), 603 N->getValueType(0))); 604} 605 606SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 607 SDValue Chain = N->getOperand(0); // Get the chain. 608 SDValue Ptr = N->getOperand(1); // Get the pointer. 609 EVT VT = N->getValueType(0); 610 DebugLoc dl = N->getDebugLoc(); 611 612 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); 613 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT); 614 // The argument is passed as NumRegs registers of type RegVT. 615 616 SmallVector<SDValue, 8> Parts(NumRegs); 617 for (unsigned i = 0; i < NumRegs; ++i) { 618 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), 619 N->getConstantOperandVal(3)); 620 Chain = Parts[i].getValue(1); 621 } 622 623 // Handle endianness of the load. 624 if (TLI.isBigEndian()) 625 std::reverse(Parts.begin(), Parts.end()); 626 627 // Assemble the parts in the promoted type. 628 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 629 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); 630 for (unsigned i = 1; i < NumRegs; ++i) { 631 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); 632 // Shift it to the right position and "or" it in. 633 Part = DAG.getNode(ISD::SHL, dl, NVT, Part, 634 DAG.getConstant(i * RegVT.getSizeInBits(), 635 TLI.getPointerTy())); 636 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part); 637 } 638 639 // Modified the chain result - switch anything that used the old chain to 640 // use the new one. 641 ReplaceValueWith(SDValue(N, 1), Chain); 642 643 return Res; 644} 645 646//===----------------------------------------------------------------------===// 647// Integer Operand Promotion 648//===----------------------------------------------------------------------===// 649 650/// PromoteIntegerOperand - This method is called when the specified operand of 651/// the specified node is found to need promotion. At this point, all of the 652/// result types of the node are known to be legal, but other operands of the 653/// node may need promotion or expansion as well as the specified one. 654bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 655 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n"); 656 SDValue Res = SDValue(); 657 658 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 659 return false; 660 661 switch (N->getOpcode()) { 662 default: 663 #ifndef NDEBUG 664 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": "; 665 N->dump(&DAG); dbgs() << "\n"; 666 #endif 667 llvm_unreachable("Do not know how to promote this operator's operand!"); 668 669 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 670 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break; 671 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 672 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 673 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 674 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 675 case ISD::CONVERT_RNDSAT: 676 Res = PromoteIntOp_CONVERT_RNDSAT(N); break; 677 case ISD::INSERT_VECTOR_ELT: 678 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 679 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 680 case ISD::SCALAR_TO_VECTOR: 681 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break; 682 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 683 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 684 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 685 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 686 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; 687 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 688 OpNo); break; 689 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 690 case ISD::FP16_TO_FP32: 691 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; 692 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 693 694 case ISD::SHL: 695 case ISD::SRA: 696 case ISD::SRL: 697 case ISD::ROTL: 698 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; 699 } 700 701 // If the result is null, the sub-method took care of registering results etc. 702 if (!Res.getNode()) return false; 703 704 // If the result is N, the sub-method updated N in place. Tell the legalizer 705 // core about this. 706 if (Res.getNode() == N) 707 return true; 708 709 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 710 "Invalid operand expansion"); 711 712 ReplaceValueWith(SDValue(N, 0), Res); 713 return false; 714} 715 716/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 717/// shared among BR_CC, SELECT_CC, and SETCC handlers. 718void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS, 719 ISD::CondCode CCCode) { 720 // We have to insert explicit sign or zero extends. Note that we could 721 // insert sign extends for ALL conditions, but zero extend is cheaper on 722 // many machines (an AND instead of two shifts), so prefer it. 723 switch (CCCode) { 724 default: llvm_unreachable("Unknown integer comparison!"); 725 case ISD::SETEQ: 726 case ISD::SETNE: 727 case ISD::SETUGE: 728 case ISD::SETUGT: 729 case ISD::SETULE: 730 case ISD::SETULT: 731 // ALL of these operations will work if we either sign or zero extend 732 // the operands (including the unsigned comparisons!). Zero extend is 733 // usually a simpler/cheaper operation, so prefer it. 734 NewLHS = ZExtPromotedInteger(NewLHS); 735 NewRHS = ZExtPromotedInteger(NewRHS); 736 break; 737 case ISD::SETGE: 738 case ISD::SETGT: 739 case ISD::SETLT: 740 case ISD::SETLE: 741 NewLHS = SExtPromotedInteger(NewLHS); 742 NewRHS = SExtPromotedInteger(NewRHS); 743 break; 744 } 745} 746 747SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 748 SDValue Op = GetPromotedInteger(N->getOperand(0)); 749 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op); 750} 751 752SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) { 753 // This should only occur in unusual situations like bitcasting to an 754 // x86_fp80, so just turn it into a store+load 755 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0)); 756} 757 758SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 759 assert(OpNo == 2 && "Don't know how to promote this operand!"); 760 761 SDValue LHS = N->getOperand(2); 762 SDValue RHS = N->getOperand(3); 763 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 764 765 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 766 // legal types. 767 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 768 N->getOperand(1), LHS, RHS, N->getOperand(4)), 769 0); 770} 771 772SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 773 assert(OpNo == 1 && "only know how to promote condition"); 774 775 // Promote all the way up to the canonical SetCC type. 776 EVT SVT = TLI.getSetCCResultType(MVT::Other); 777 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT); 778 779 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 780 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond, 781 N->getOperand(2)), 0); 782} 783 784SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 785 // Since the result type is legal, the operands must promote to it. 786 EVT OVT = N->getOperand(0).getValueType(); 787 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); 788 SDValue Hi = GetPromotedInteger(N->getOperand(1)); 789 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 790 DebugLoc dl = N->getDebugLoc(); 791 792 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi, 793 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy())); 794 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); 795} 796 797SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 798 // The vector type is legal but the element type is not. This implies 799 // that the vector is a power-of-two in length and that the element 800 // type does not have a strange size (eg: it is not i1). 801 EVT VecVT = N->getValueType(0); 802 unsigned NumElts = VecVT.getVectorNumElements(); 803 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 804 805 // Promote the inserted value. The type does not need to match the 806 // vector element type. Check that any extra bits introduced will be 807 // truncated away. 808 assert(N->getOperand(0).getValueType().getSizeInBits() >= 809 N->getValueType(0).getVectorElementType().getSizeInBits() && 810 "Type of inserted value narrower than vector element type!"); 811 812 SmallVector<SDValue, 16> NewOps; 813 for (unsigned i = 0; i < NumElts; ++i) 814 NewOps.push_back(GetPromotedInteger(N->getOperand(i))); 815 816 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0); 817} 818 819SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) { 820 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode(); 821 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU || 822 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || 823 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) && 824 "can only promote integer arguments"); 825 SDValue InOp = GetPromotedInteger(N->getOperand(0)); 826 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp, 827 N->getOperand(1), N->getOperand(2), 828 N->getOperand(3), N->getOperand(4), CvtCode); 829} 830 831SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 832 unsigned OpNo) { 833 if (OpNo == 1) { 834 // Promote the inserted value. This is valid because the type does not 835 // have to match the vector element type. 836 837 // Check that any extra bits introduced will be truncated away. 838 assert(N->getOperand(1).getValueType().getSizeInBits() >= 839 N->getValueType(0).getVectorElementType().getSizeInBits() && 840 "Type of inserted value narrower than vector element type!"); 841 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 842 GetPromotedInteger(N->getOperand(1)), 843 N->getOperand(2)), 844 0); 845 } 846 847 assert(OpNo == 2 && "Different operand and result vector types?"); 848 849 // Promote the index. 850 SDValue Idx = ZExtPromotedInteger(N->getOperand(2)); 851 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 852 N->getOperand(1), Idx), 0); 853} 854 855SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 856 SDValue NewOps[6]; 857 DebugLoc dl = N->getDebugLoc(); 858 NewOps[0] = N->getOperand(0); 859 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 860 SDValue Flag = GetPromotedInteger(N->getOperand(i)); 861 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1); 862 } 863 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0); 864} 865 866SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) { 867 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote 868 // the operand in place. 869 return SDValue(DAG.UpdateNodeOperands(N, 870 GetPromotedInteger(N->getOperand(0))), 0); 871} 872 873SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 874 assert(OpNo == 0 && "Only know how to promote condition"); 875 876 // Promote all the way up to the canonical SetCC type. 877 EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType()); 878 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT); 879 880 return SDValue(DAG.UpdateNodeOperands(N, Cond, 881 N->getOperand(1), N->getOperand(2)), 0); 882} 883 884SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 885 assert(OpNo == 0 && "Don't know how to promote this operand!"); 886 887 SDValue LHS = N->getOperand(0); 888 SDValue RHS = N->getOperand(1); 889 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 890 891 // The CC (#4) and the possible return values (#2 and #3) have legal types. 892 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2), 893 N->getOperand(3), N->getOperand(4)), 0); 894} 895 896SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 897 assert(OpNo == 0 && "Don't know how to promote this operand!"); 898 899 SDValue LHS = N->getOperand(0); 900 SDValue RHS = N->getOperand(1); 901 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 902 903 // The CC (#2) is always legal. 904 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0); 905} 906 907SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) { 908 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 909 ZExtPromotedInteger(N->getOperand(1))), 0); 910} 911 912SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 913 SDValue Op = GetPromotedInteger(N->getOperand(0)); 914 DebugLoc dl = N->getDebugLoc(); 915 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 916 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), 917 Op, DAG.getValueType(N->getOperand(0).getValueType())); 918} 919 920SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) { 921 return SDValue(DAG.UpdateNodeOperands(N, 922 SExtPromotedInteger(N->getOperand(0))), 0); 923} 924 925SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 926 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 927 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); 928 unsigned Alignment = N->getAlignment(); 929 bool isVolatile = N->isVolatile(); 930 bool isNonTemporal = N->isNonTemporal(); 931 DebugLoc dl = N->getDebugLoc(); 932 933 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value. 934 935 // Truncate the value and store the result. 936 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(), 937 N->getMemoryVT(), 938 isVolatile, isNonTemporal, Alignment); 939} 940 941SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 942 SDValue Op = GetPromotedInteger(N->getOperand(0)); 943 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op); 944} 945 946SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) { 947 return SDValue(DAG.UpdateNodeOperands(N, 948 ZExtPromotedInteger(N->getOperand(0))), 0); 949} 950 951SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 952 DebugLoc dl = N->getDebugLoc(); 953 SDValue Op = GetPromotedInteger(N->getOperand(0)); 954 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op); 955 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType()); 956} 957 958 959//===----------------------------------------------------------------------===// 960// Integer Result Expansion 961//===----------------------------------------------------------------------===// 962 963/// ExpandIntegerResult - This method is called when the specified result of the 964/// specified node is found to need expansion. At this point, the node may also 965/// have invalid operands or may have other results that need promotion, we just 966/// know that (at least) one result needs expansion. 967void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 968 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n"); 969 SDValue Lo, Hi; 970 Lo = Hi = SDValue(); 971 972 // See if the target wants to custom expand this node. 973 if (CustomLowerNode(N, N->getValueType(ResNo), true)) 974 return; 975 976 switch (N->getOpcode()) { 977 default: 978#ifndef NDEBUG 979 dbgs() << "ExpandIntegerResult #" << ResNo << ": "; 980 N->dump(&DAG); dbgs() << "\n"; 981#endif 982 llvm_unreachable("Do not know how to expand the result of this operator!"); 983 984 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 985 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 986 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 987 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 988 989 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break; 990 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 991 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 992 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 993 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break; 994 995 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 996 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break; 997 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 998 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 999 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 1000 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 1001 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 1002 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 1003 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 1004 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 1005 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 1006 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 1007 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 1008 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 1009 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 1010 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 1011 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 1012 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 1013 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 1014 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 1015 1016 case ISD::ATOMIC_LOAD_ADD: 1017 case ISD::ATOMIC_LOAD_SUB: 1018 case ISD::ATOMIC_LOAD_AND: 1019 case ISD::ATOMIC_LOAD_OR: 1020 case ISD::ATOMIC_LOAD_XOR: 1021 case ISD::ATOMIC_LOAD_NAND: 1022 case ISD::ATOMIC_LOAD_MIN: 1023 case ISD::ATOMIC_LOAD_MAX: 1024 case ISD::ATOMIC_LOAD_UMIN: 1025 case ISD::ATOMIC_LOAD_UMAX: 1026 case ISD::ATOMIC_SWAP: { 1027 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N); 1028 SplitInteger(Tmp.first, Lo, Hi); 1029 ReplaceValueWith(SDValue(N, 1), Tmp.second); 1030 break; 1031 } 1032 1033 case ISD::AND: 1034 case ISD::OR: 1035 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 1036 1037 case ISD::ADD: 1038 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1039 1040 case ISD::ADDC: 1041 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 1042 1043 case ISD::ADDE: 1044 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 1045 1046 case ISD::SHL: 1047 case ISD::SRA: 1048 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 1049 1050 case ISD::SADDO: 1051 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break; 1052 case ISD::UADDO: 1053 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break; 1054 } 1055 1056 // If Lo/Hi is null, the sub-method took care of registering results etc. 1057 if (Lo.getNode()) 1058 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); 1059} 1060 1061/// Lower an atomic node to the appropriate builtin call. 1062std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) { 1063 unsigned Opc = Node->getOpcode(); 1064 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 1065 RTLIB::Libcall LC; 1066 1067 switch (Opc) { 1068 default: 1069 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 1070 break; 1071 case ISD::ATOMIC_SWAP: 1072 switch (VT.SimpleTy) { 1073 default: llvm_unreachable("Unexpected value type for atomic!"); 1074 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 1075 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 1076 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 1077 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 1078 } 1079 break; 1080 case ISD::ATOMIC_CMP_SWAP: 1081 switch (VT.SimpleTy) { 1082 default: llvm_unreachable("Unexpected value type for atomic!"); 1083 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 1084 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 1085 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 1086 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 1087 } 1088 break; 1089 case ISD::ATOMIC_LOAD_ADD: 1090 switch (VT.SimpleTy) { 1091 default: llvm_unreachable("Unexpected value type for atomic!"); 1092 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 1093 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 1094 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 1095 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 1096 } 1097 break; 1098 case ISD::ATOMIC_LOAD_SUB: 1099 switch (VT.SimpleTy) { 1100 default: llvm_unreachable("Unexpected value type for atomic!"); 1101 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 1102 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 1103 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 1104 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 1105 } 1106 break; 1107 case ISD::ATOMIC_LOAD_AND: 1108 switch (VT.SimpleTy) { 1109 default: llvm_unreachable("Unexpected value type for atomic!"); 1110 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 1111 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 1112 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 1113 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 1114 } 1115 break; 1116 case ISD::ATOMIC_LOAD_OR: 1117 switch (VT.SimpleTy) { 1118 default: llvm_unreachable("Unexpected value type for atomic!"); 1119 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 1120 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 1121 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 1122 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 1123 } 1124 break; 1125 case ISD::ATOMIC_LOAD_XOR: 1126 switch (VT.SimpleTy) { 1127 default: llvm_unreachable("Unexpected value type for atomic!"); 1128 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 1129 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 1130 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 1131 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 1132 } 1133 break; 1134 case ISD::ATOMIC_LOAD_NAND: 1135 switch (VT.SimpleTy) { 1136 default: llvm_unreachable("Unexpected value type for atomic!"); 1137 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 1138 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 1139 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 1140 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 1141 } 1142 break; 1143 } 1144 1145 return ExpandChainLibCall(LC, Node, false); 1146} 1147 1148/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1149/// and the shift amount is a constant 'Amt'. Expand the operation. 1150void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1151 SDValue &Lo, SDValue &Hi) { 1152 DebugLoc DL = N->getDebugLoc(); 1153 // Expand the incoming operand to be shifted, so that we have its parts 1154 SDValue InL, InH; 1155 GetExpandedInteger(N->getOperand(0), InL, InH); 1156 1157 EVT NVT = InL.getValueType(); 1158 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1159 unsigned NVTBits = NVT.getSizeInBits(); 1160 EVT ShTy = N->getOperand(1).getValueType(); 1161 1162 if (N->getOpcode() == ISD::SHL) { 1163 if (Amt > VTBits) { 1164 Lo = Hi = DAG.getConstant(0, NVT); 1165 } else if (Amt > NVTBits) { 1166 Lo = DAG.getConstant(0, NVT); 1167 Hi = DAG.getNode(ISD::SHL, DL, 1168 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy)); 1169 } else if (Amt == NVTBits) { 1170 Lo = DAG.getConstant(0, NVT); 1171 Hi = InL; 1172 } else if (Amt == 1 && 1173 TLI.isOperationLegalOrCustom(ISD::ADDC, 1174 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) { 1175 // Emit this X << 1 as X+X. 1176 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); 1177 SDValue LoOps[2] = { InL, InL }; 1178 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2); 1179 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; 1180 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3); 1181 } else { 1182 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1183 Hi = DAG.getNode(ISD::OR, DL, NVT, 1184 DAG.getNode(ISD::SHL, DL, NVT, InH, 1185 DAG.getConstant(Amt, ShTy)), 1186 DAG.getNode(ISD::SRL, DL, NVT, InL, 1187 DAG.getConstant(NVTBits-Amt, ShTy))); 1188 } 1189 return; 1190 } 1191 1192 if (N->getOpcode() == ISD::SRL) { 1193 if (Amt > VTBits) { 1194 Lo = DAG.getConstant(0, NVT); 1195 Hi = DAG.getConstant(0, NVT); 1196 } else if (Amt > NVTBits) { 1197 Lo = DAG.getNode(ISD::SRL, DL, 1198 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1199 Hi = DAG.getConstant(0, NVT); 1200 } else if (Amt == NVTBits) { 1201 Lo = InH; 1202 Hi = DAG.getConstant(0, NVT); 1203 } else { 1204 Lo = DAG.getNode(ISD::OR, DL, NVT, 1205 DAG.getNode(ISD::SRL, DL, NVT, InL, 1206 DAG.getConstant(Amt, ShTy)), 1207 DAG.getNode(ISD::SHL, DL, NVT, InH, 1208 DAG.getConstant(NVTBits-Amt, ShTy))); 1209 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1210 } 1211 return; 1212 } 1213 1214 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1215 if (Amt > VTBits) { 1216 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, 1217 DAG.getConstant(NVTBits-1, ShTy)); 1218 } else if (Amt > NVTBits) { 1219 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, 1220 DAG.getConstant(Amt-NVTBits, ShTy)); 1221 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, 1222 DAG.getConstant(NVTBits-1, ShTy)); 1223 } else if (Amt == NVTBits) { 1224 Lo = InH; 1225 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, 1226 DAG.getConstant(NVTBits-1, ShTy)); 1227 } else { 1228 Lo = DAG.getNode(ISD::OR, DL, NVT, 1229 DAG.getNode(ISD::SRL, DL, NVT, InL, 1230 DAG.getConstant(Amt, ShTy)), 1231 DAG.getNode(ISD::SHL, DL, NVT, InH, 1232 DAG.getConstant(NVTBits-Amt, ShTy))); 1233 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1234 } 1235} 1236 1237/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1238/// this shift based on knowledge of the high bit of the shift amount. If we 1239/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1240/// shift amount. 1241bool DAGTypeLegalizer:: 1242ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1243 SDValue Amt = N->getOperand(1); 1244 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1245 EVT ShTy = Amt.getValueType(); 1246 unsigned ShBits = ShTy.getScalarType().getSizeInBits(); 1247 unsigned NVTBits = NVT.getScalarType().getSizeInBits(); 1248 assert(isPowerOf2_32(NVTBits) && 1249 "Expanded integer type size not a power of two!"); 1250 DebugLoc dl = N->getDebugLoc(); 1251 1252 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1253 APInt KnownZero, KnownOne; 1254 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1255 1256 // If we don't know anything about the high bits, exit. 1257 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1258 return false; 1259 1260 // Get the incoming operand to be shifted. 1261 SDValue InL, InH; 1262 GetExpandedInteger(N->getOperand(0), InL, InH); 1263 1264 // If we know that any of the high bits of the shift amount are one, then we 1265 // can do this as a couple of simple shifts. 1266 if (KnownOne.intersects(HighBitMask)) { 1267 // Mask out the high bit, which we know is set. 1268 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, 1269 DAG.getConstant(~HighBitMask, ShTy)); 1270 1271 switch (N->getOpcode()) { 1272 default: llvm_unreachable("Unknown shift"); 1273 case ISD::SHL: 1274 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1275 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. 1276 return true; 1277 case ISD::SRL: 1278 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1279 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part. 1280 return true; 1281 case ISD::SRA: 1282 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part. 1283 DAG.getConstant(NVTBits-1, ShTy)); 1284 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part. 1285 return true; 1286 } 1287 } 1288 1289#if 0 1290 // FIXME: This code is broken for shifts with a zero amount! 1291 // If we know that all of the high bits of the shift amount are zero, then we 1292 // can do this as a couple of simple shifts. 1293 if ((KnownZero & HighBitMask) == HighBitMask) { 1294 // Compute 32-amt. 1295 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1296 DAG.getConstant(NVTBits, ShTy), 1297 Amt); 1298 unsigned Op1, Op2; 1299 switch (N->getOpcode()) { 1300 default: llvm_unreachable("Unknown shift"); 1301 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1302 case ISD::SRL: 1303 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1304 } 1305 1306 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1307 Hi = DAG.getNode(ISD::OR, NVT, 1308 DAG.getNode(Op1, NVT, InH, Amt), 1309 DAG.getNode(Op2, NVT, InL, Amt2)); 1310 return true; 1311 } 1312#endif 1313 1314 return false; 1315} 1316 1317/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift 1318/// of any size. 1319bool DAGTypeLegalizer:: 1320ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { 1321 SDValue Amt = N->getOperand(1); 1322 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1323 EVT ShTy = Amt.getValueType(); 1324 unsigned NVTBits = NVT.getSizeInBits(); 1325 assert(isPowerOf2_32(NVTBits) && 1326 "Expanded integer type size not a power of two!"); 1327 DebugLoc dl = N->getDebugLoc(); 1328 1329 // Get the incoming operand to be shifted. 1330 SDValue InL, InH; 1331 GetExpandedInteger(N->getOperand(0), InL, InH); 1332 1333 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy); 1334 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode); 1335 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt); 1336 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy), 1337 Amt, NVBitsNode, ISD::SETULT); 1338 1339 SDValue LoS, HiS, LoL, HiL; 1340 switch (N->getOpcode()) { 1341 default: llvm_unreachable("Unknown shift"); 1342 case ISD::SHL: 1343 // Short: ShAmt < NVTBits 1344 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); 1345 HiS = DAG.getNode(ISD::OR, dl, NVT, 1346 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt), 1347 // FIXME: If Amt is zero, the following shift generates an undefined result 1348 // on some architectures. 1349 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack)); 1350 1351 // Long: ShAmt >= NVTBits 1352 LoL = DAG.getConstant(0, NVT); // Lo part is zero. 1353 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part. 1354 1355 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1356 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1357 return true; 1358 case ISD::SRL: 1359 // Short: ShAmt < NVTBits 1360 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); 1361 LoS = DAG.getNode(ISD::OR, dl, NVT, 1362 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1363 // FIXME: If Amt is zero, the following shift generates an undefined result 1364 // on some architectures. 1365 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); 1366 1367 // Long: ShAmt >= NVTBits 1368 HiL = DAG.getConstant(0, NVT); // Hi part is zero. 1369 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part. 1370 1371 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1372 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1373 return true; 1374 case ISD::SRA: 1375 // Short: ShAmt < NVTBits 1376 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); 1377 LoS = DAG.getNode(ISD::OR, dl, NVT, 1378 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt), 1379 // FIXME: If Amt is zero, the following shift generates an undefined result 1380 // on some architectures. 1381 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack)); 1382 1383 // Long: ShAmt >= NVTBits 1384 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part. 1385 DAG.getConstant(NVTBits-1, ShTy)); 1386 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part. 1387 1388 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL); 1389 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL); 1390 return true; 1391 } 1392 1393 return false; 1394} 1395 1396void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1397 SDValue &Lo, SDValue &Hi) { 1398 DebugLoc dl = N->getDebugLoc(); 1399 // Expand the subcomponents. 1400 SDValue LHSL, LHSH, RHSL, RHSH; 1401 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1402 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1403 1404 EVT NVT = LHSL.getValueType(); 1405 SDValue LoOps[2] = { LHSL, RHSL }; 1406 SDValue HiOps[3] = { LHSH, RHSH }; 1407 1408 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support 1409 // them. TODO: Teach operation legalization how to expand unsupported 1410 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate 1411 // a carry of type MVT::Glue, but there doesn't seem to be any way to 1412 // generate a value of this type in the expanded code sequence. 1413 bool hasCarry = 1414 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? 1415 ISD::ADDC : ISD::SUBC, 1416 TLI.getTypeToExpandTo(*DAG.getContext(), NVT)); 1417 1418 if (hasCarry) { 1419 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue); 1420 if (N->getOpcode() == ISD::ADD) { 1421 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1422 HiOps[2] = Lo.getValue(1); 1423 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1424 } else { 1425 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1426 HiOps[2] = Lo.getValue(1); 1427 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1428 } 1429 return; 1430 } 1431 1432 if (N->getOpcode() == ISD::ADD) { 1433 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2); 1434 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2); 1435 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0], 1436 ISD::SETULT); 1437 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1, 1438 DAG.getConstant(1, NVT), 1439 DAG.getConstant(0, NVT)); 1440 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1], 1441 ISD::SETULT); 1442 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2, 1443 DAG.getConstant(1, NVT), Carry1); 1444 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2); 1445 } else { 1446 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 1447 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2); 1448 SDValue Cmp = 1449 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()), 1450 LoOps[0], LoOps[1], ISD::SETULT); 1451 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, 1452 DAG.getConstant(1, NVT), 1453 DAG.getConstant(0, NVT)); 1454 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow); 1455 } 1456} 1457 1458void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1459 SDValue &Lo, SDValue &Hi) { 1460 // Expand the subcomponents. 1461 SDValue LHSL, LHSH, RHSL, RHSH; 1462 DebugLoc dl = N->getDebugLoc(); 1463 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1464 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1465 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue); 1466 SDValue LoOps[2] = { LHSL, RHSL }; 1467 SDValue HiOps[3] = { LHSH, RHSH }; 1468 1469 if (N->getOpcode() == ISD::ADDC) { 1470 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); 1471 HiOps[2] = Lo.getValue(1); 1472 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); 1473 } else { 1474 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2); 1475 HiOps[2] = Lo.getValue(1); 1476 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); 1477 } 1478 1479 // Legalized the flag result - switch anything that used the old flag to 1480 // use the new one. 1481 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1482} 1483 1484void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1485 SDValue &Lo, SDValue &Hi) { 1486 // Expand the subcomponents. 1487 SDValue LHSL, LHSH, RHSL, RHSH; 1488 DebugLoc dl = N->getDebugLoc(); 1489 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1490 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1491 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue); 1492 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1493 SDValue HiOps[3] = { LHSH, RHSH }; 1494 1495 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3); 1496 HiOps[2] = Lo.getValue(1); 1497 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3); 1498 1499 // Legalized the flag result - switch anything that used the old flag to 1500 // use the new one. 1501 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1)); 1502} 1503 1504void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 1505 SDValue &Lo, SDValue &Hi) { 1506 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1507 DebugLoc dl = N->getDebugLoc(); 1508 SDValue Op = N->getOperand(0); 1509 if (Op.getValueType().bitsLE(NVT)) { 1510 // The low part is any extension of the input (which degenerates to a copy). 1511 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op); 1512 Hi = DAG.getUNDEF(NVT); // The high part is undefined. 1513 } else { 1514 // For example, extension of an i48 to an i64. The operand type necessarily 1515 // promotes to the result type, so will end up being expanded too. 1516 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 1517 "Only know how to promote this result!"); 1518 SDValue Res = GetPromotedInteger(Op); 1519 assert(Res.getValueType() == N->getValueType(0) && 1520 "Operand over promoted?"); 1521 // Split the promoted operand. This will simplify when it is expanded. 1522 SplitInteger(Res, Lo, Hi); 1523 } 1524} 1525 1526void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, 1527 SDValue &Lo, SDValue &Hi) { 1528 DebugLoc dl = N->getDebugLoc(); 1529 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1530 EVT NVT = Lo.getValueType(); 1531 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1532 unsigned NVTBits = NVT.getSizeInBits(); 1533 unsigned EVTBits = EVT.getSizeInBits(); 1534 1535 if (NVTBits < EVTBits) { 1536 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, 1537 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1538 EVTBits - NVTBits))); 1539 } else { 1540 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); 1541 // The high part replicates the sign bit of Lo, make it explicit. 1542 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1543 DAG.getConstant(NVTBits-1, TLI.getPointerTy())); 1544 } 1545} 1546 1547void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 1548 SDValue &Lo, SDValue &Hi) { 1549 DebugLoc dl = N->getDebugLoc(); 1550 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1551 EVT NVT = Lo.getValueType(); 1552 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1553 unsigned NVTBits = NVT.getSizeInBits(); 1554 unsigned EVTBits = EVT.getSizeInBits(); 1555 1556 if (NVTBits < EVTBits) { 1557 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, 1558 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 1559 EVTBits - NVTBits))); 1560 } else { 1561 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); 1562 // The high part must be zero, make it explicit. 1563 Hi = DAG.getConstant(0, NVT); 1564 } 1565} 1566 1567void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1568 SDValue &Lo, SDValue &Hi) { 1569 DebugLoc dl = N->getDebugLoc(); 1570 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1571 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo); 1572 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi); 1573} 1574 1575void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 1576 SDValue &Lo, SDValue &Hi) { 1577 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 1578 unsigned NBitWidth = NVT.getSizeInBits(); 1579 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 1580 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT); 1581 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 1582} 1583 1584void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1585 SDValue &Lo, SDValue &Hi) { 1586 DebugLoc dl = N->getDebugLoc(); 1587 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1588 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1589 EVT NVT = Lo.getValueType(); 1590 1591 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi, 1592 DAG.getConstant(0, NVT), ISD::SETNE); 1593 1594 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo); 1595 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi); 1596 1597 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ, 1598 DAG.getNode(ISD::ADD, dl, NVT, LoLZ, 1599 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1600 Hi = DAG.getConstant(0, NVT); 1601} 1602 1603void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1604 SDValue &Lo, SDValue &Hi) { 1605 DebugLoc dl = N->getDebugLoc(); 1606 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1607 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1608 EVT NVT = Lo.getValueType(); 1609 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), 1610 DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); 1611 Hi = DAG.getConstant(0, NVT); 1612} 1613 1614void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1615 SDValue &Lo, SDValue &Hi) { 1616 DebugLoc dl = N->getDebugLoc(); 1617 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1618 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1619 EVT NVT = Lo.getValueType(); 1620 1621 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, 1622 DAG.getConstant(0, NVT), ISD::SETNE); 1623 1624 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); 1625 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); 1626 1627 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ, 1628 DAG.getNode(ISD::ADD, dl, NVT, HiLZ, 1629 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1630 Hi = DAG.getConstant(0, NVT); 1631} 1632 1633void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, 1634 SDValue &Hi) { 1635 DebugLoc dl = N->getDebugLoc(); 1636 EVT VT = N->getValueType(0); 1637 SDValue Op = N->getOperand(0); 1638 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); 1639 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1640 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi); 1641} 1642 1643void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, 1644 SDValue &Hi) { 1645 DebugLoc dl = N->getDebugLoc(); 1646 EVT VT = N->getValueType(0); 1647 SDValue Op = N->getOperand(0); 1648 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); 1649 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1650 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi); 1651} 1652 1653void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1654 SDValue &Lo, SDValue &Hi) { 1655 if (ISD::isNormalLoad(N)) { 1656 ExpandRes_NormalLoad(N, Lo, Hi); 1657 return; 1658 } 1659 1660 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1661 1662 EVT VT = N->getValueType(0); 1663 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1664 SDValue Ch = N->getChain(); 1665 SDValue Ptr = N->getBasePtr(); 1666 ISD::LoadExtType ExtType = N->getExtensionType(); 1667 unsigned Alignment = N->getAlignment(); 1668 bool isVolatile = N->isVolatile(); 1669 bool isNonTemporal = N->isNonTemporal(); 1670 DebugLoc dl = N->getDebugLoc(); 1671 1672 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1673 1674 if (N->getMemoryVT().bitsLE(NVT)) { 1675 EVT MemVT = N->getMemoryVT(); 1676 1677 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), 1678 MemVT, isVolatile, isNonTemporal, Alignment); 1679 1680 // Remember the chain. 1681 Ch = Lo.getValue(1); 1682 1683 if (ExtType == ISD::SEXTLOAD) { 1684 // The high part is obtained by SRA'ing all but one of the bits of the 1685 // lo part. 1686 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1687 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 1688 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 1689 } else if (ExtType == ISD::ZEXTLOAD) { 1690 // The high part is just a zero. 1691 Hi = DAG.getConstant(0, NVT); 1692 } else { 1693 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1694 // The high part is undefined. 1695 Hi = DAG.getUNDEF(NVT); 1696 } 1697 } else if (TLI.isLittleEndian()) { 1698 // Little-endian - low bits are at low addresses. 1699 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(), 1700 isVolatile, isNonTemporal, Alignment); 1701 1702 unsigned ExcessBits = 1703 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1704 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits); 1705 1706 // Increment the pointer to the other half. 1707 unsigned IncrementSize = NVT.getSizeInBits()/8; 1708 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1709 DAG.getIntPtrConstant(IncrementSize)); 1710 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, 1711 N->getPointerInfo().getWithOffset(IncrementSize), NEVT, 1712 isVolatile, isNonTemporal, 1713 MinAlign(Alignment, IncrementSize)); 1714 1715 // Build a factor node to remember that this load is independent of the 1716 // other one. 1717 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1718 Hi.getValue(1)); 1719 } else { 1720 // Big-endian - high bits are at low addresses. Favor aligned loads at 1721 // the cost of some bit-fiddling. 1722 EVT MemVT = N->getMemoryVT(); 1723 unsigned EBytes = MemVT.getStoreSize(); 1724 unsigned IncrementSize = NVT.getSizeInBits()/8; 1725 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1726 1727 // Load both the high bits and maybe some of the low bits. 1728 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), 1729 EVT::getIntegerVT(*DAG.getContext(), 1730 MemVT.getSizeInBits() - ExcessBits), 1731 isVolatile, isNonTemporal, Alignment); 1732 1733 // Increment the pointer to the other half. 1734 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1735 DAG.getIntPtrConstant(IncrementSize)); 1736 // Load the rest of the low bits. 1737 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, 1738 N->getPointerInfo().getWithOffset(IncrementSize), 1739 EVT::getIntegerVT(*DAG.getContext(), ExcessBits), 1740 isVolatile, isNonTemporal, 1741 MinAlign(Alignment, IncrementSize)); 1742 1743 // Build a factor node to remember that this load is independent of the 1744 // other one. 1745 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1746 Hi.getValue(1)); 1747 1748 if (ExcessBits < NVT.getSizeInBits()) { 1749 // Transfer low bits from the bottom of Hi to the top of Lo. 1750 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo, 1751 DAG.getNode(ISD::SHL, dl, NVT, Hi, 1752 DAG.getConstant(ExcessBits, 1753 TLI.getPointerTy()))); 1754 // Move high bits to the right position in Hi. 1755 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, 1756 NVT, Hi, 1757 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1758 TLI.getPointerTy())); 1759 } 1760 } 1761 1762 // Legalized the chain result - switch anything that used the old chain to 1763 // use the new one. 1764 ReplaceValueWith(SDValue(N, 1), Ch); 1765} 1766 1767void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1768 SDValue &Lo, SDValue &Hi) { 1769 DebugLoc dl = N->getDebugLoc(); 1770 SDValue LL, LH, RL, RH; 1771 GetExpandedInteger(N->getOperand(0), LL, LH); 1772 GetExpandedInteger(N->getOperand(1), RL, RH); 1773 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL); 1774 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH); 1775} 1776 1777void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1778 SDValue &Lo, SDValue &Hi) { 1779 EVT VT = N->getValueType(0); 1780 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1781 DebugLoc dl = N->getDebugLoc(); 1782 1783 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); 1784 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT); 1785 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT); 1786 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT); 1787 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1788 SDValue LL, LH, RL, RH; 1789 GetExpandedInteger(N->getOperand(0), LL, LH); 1790 GetExpandedInteger(N->getOperand(1), RL, RH); 1791 unsigned OuterBitSize = VT.getSizeInBits(); 1792 unsigned InnerBitSize = NVT.getSizeInBits(); 1793 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1794 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1795 1796 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1797 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1798 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1799 // The inputs are both zero-extended. 1800 if (HasUMUL_LOHI) { 1801 // We can emit a umul_lohi. 1802 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1803 Hi = SDValue(Lo.getNode(), 1); 1804 return; 1805 } 1806 if (HasMULHU) { 1807 // We can emit a mulhu+mul. 1808 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1809 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1810 return; 1811 } 1812 } 1813 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1814 // The input values are both sign-extended. 1815 if (HasSMUL_LOHI) { 1816 // We can emit a smul_lohi. 1817 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL); 1818 Hi = SDValue(Lo.getNode(), 1); 1819 return; 1820 } 1821 if (HasMULHS) { 1822 // We can emit a mulhs+mul. 1823 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1824 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL); 1825 return; 1826 } 1827 } 1828 if (HasUMUL_LOHI) { 1829 // Lo,Hi = umul LHS, RHS. 1830 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl, 1831 DAG.getVTList(NVT, NVT), LL, RL); 1832 Lo = UMulLOHI; 1833 Hi = UMulLOHI.getValue(1); 1834 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1835 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1836 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1837 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1838 return; 1839 } 1840 if (HasMULHU) { 1841 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL); 1842 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL); 1843 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH); 1844 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL); 1845 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH); 1846 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH); 1847 return; 1848 } 1849 } 1850 1851 // If nothing else, we can make a libcall. 1852 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1853 if (VT == MVT::i16) 1854 LC = RTLIB::MUL_I16; 1855 else if (VT == MVT::i32) 1856 LC = RTLIB::MUL_I32; 1857 else if (VT == MVT::i64) 1858 LC = RTLIB::MUL_I64; 1859 else if (VT == MVT::i128) 1860 LC = RTLIB::MUL_I128; 1861 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1862 1863 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1864 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi); 1865} 1866 1867void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node, 1868 SDValue &Lo, SDValue &Hi) { 1869 SDValue LHS = Node->getOperand(0); 1870 SDValue RHS = Node->getOperand(1); 1871 DebugLoc dl = Node->getDebugLoc(); 1872 1873 // Expand the result by simply replacing it with the equivalent 1874 // non-overflow-checking operation. 1875 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 1876 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 1877 LHS, RHS); 1878 SplitInteger(Sum, Lo, Hi); 1879 1880 // Compute the overflow. 1881 // 1882 // LHSSign -> LHS >= 0 1883 // RHSSign -> RHS >= 0 1884 // SumSign -> Sum >= 0 1885 // 1886 // Add: 1887 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 1888 // Sub: 1889 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 1890 // 1891 EVT OType = Node->getValueType(1); 1892 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 1893 1894 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 1895 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 1896 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 1897 Node->getOpcode() == ISD::SADDO ? 1898 ISD::SETEQ : ISD::SETNE); 1899 1900 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 1901 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 1902 1903 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 1904 1905 // Use the calculated overflow everywhere. 1906 ReplaceValueWith(SDValue(Node, 1), Cmp); 1907} 1908 1909void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1910 SDValue &Lo, SDValue &Hi) { 1911 EVT VT = N->getValueType(0); 1912 DebugLoc dl = N->getDebugLoc(); 1913 1914 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1915 if (VT == MVT::i16) 1916 LC = RTLIB::SDIV_I16; 1917 else if (VT == MVT::i32) 1918 LC = RTLIB::SDIV_I32; 1919 else if (VT == MVT::i64) 1920 LC = RTLIB::SDIV_I64; 1921 else if (VT == MVT::i128) 1922 LC = RTLIB::SDIV_I128; 1923 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1924 1925 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1926 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 1927} 1928 1929void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1930 SDValue &Lo, SDValue &Hi) { 1931 EVT VT = N->getValueType(0); 1932 DebugLoc dl = N->getDebugLoc(); 1933 1934 // If we can emit an efficient shift operation, do so now. Check to see if 1935 // the RHS is a constant. 1936 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1937 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi); 1938 1939 // If we can determine that the high bit of the shift is zero or one, even if 1940 // the low bits are variable, emit this shift in an optimized form. 1941 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1942 return; 1943 1944 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1945 unsigned PartsOpc; 1946 if (N->getOpcode() == ISD::SHL) { 1947 PartsOpc = ISD::SHL_PARTS; 1948 } else if (N->getOpcode() == ISD::SRL) { 1949 PartsOpc = ISD::SRL_PARTS; 1950 } else { 1951 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1952 PartsOpc = ISD::SRA_PARTS; 1953 } 1954 1955 // Next check to see if the target supports this SHL_PARTS operation or if it 1956 // will custom expand it. 1957 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 1958 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1959 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1960 Action == TargetLowering::Custom) { 1961 // Expand the subcomponents. 1962 SDValue LHSL, LHSH; 1963 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1964 1965 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1966 EVT VT = LHSL.getValueType(); 1967 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3); 1968 Hi = Lo.getValue(1); 1969 return; 1970 } 1971 1972 // Otherwise, emit a libcall. 1973 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1974 bool isSigned; 1975 if (N->getOpcode() == ISD::SHL) { 1976 isSigned = false; /*sign irrelevant*/ 1977 if (VT == MVT::i16) 1978 LC = RTLIB::SHL_I16; 1979 else if (VT == MVT::i32) 1980 LC = RTLIB::SHL_I32; 1981 else if (VT == MVT::i64) 1982 LC = RTLIB::SHL_I64; 1983 else if (VT == MVT::i128) 1984 LC = RTLIB::SHL_I128; 1985 } else if (N->getOpcode() == ISD::SRL) { 1986 isSigned = false; 1987 if (VT == MVT::i16) 1988 LC = RTLIB::SRL_I16; 1989 else if (VT == MVT::i32) 1990 LC = RTLIB::SRL_I32; 1991 else if (VT == MVT::i64) 1992 LC = RTLIB::SRL_I64; 1993 else if (VT == MVT::i128) 1994 LC = RTLIB::SRL_I128; 1995 } else { 1996 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1997 isSigned = true; 1998 if (VT == MVT::i16) 1999 LC = RTLIB::SRA_I16; 2000 else if (VT == MVT::i32) 2001 LC = RTLIB::SRA_I32; 2002 else if (VT == MVT::i64) 2003 LC = RTLIB::SRA_I64; 2004 else if (VT == MVT::i128) 2005 LC = RTLIB::SRA_I128; 2006 } 2007 2008 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) { 2009 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2010 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi); 2011 return; 2012 } 2013 2014 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi)) 2015 llvm_unreachable("Unsupported shift!"); 2016} 2017 2018void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 2019 SDValue &Lo, SDValue &Hi) { 2020 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2021 DebugLoc dl = N->getDebugLoc(); 2022 SDValue Op = N->getOperand(0); 2023 if (Op.getValueType().bitsLE(NVT)) { 2024 // The low part is sign extension of the input (degenerates to a copy). 2025 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0)); 2026 // The high part is obtained by SRA'ing all but one of the bits of low part. 2027 unsigned LoSize = NVT.getSizeInBits(); 2028 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo, 2029 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 2030 } else { 2031 // For example, extension of an i48 to an i64. The operand type necessarily 2032 // promotes to the result type, so will end up being expanded too. 2033 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 2034 "Only know how to promote this result!"); 2035 SDValue Res = GetPromotedInteger(Op); 2036 assert(Res.getValueType() == N->getValueType(0) && 2037 "Operand over promoted?"); 2038 // Split the promoted operand. This will simplify when it is expanded. 2039 SplitInteger(Res, Lo, Hi); 2040 unsigned ExcessBits = 2041 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 2042 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 2043 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 2044 ExcessBits))); 2045 } 2046} 2047 2048void DAGTypeLegalizer:: 2049ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { 2050 DebugLoc dl = N->getDebugLoc(); 2051 GetExpandedInteger(N->getOperand(0), Lo, Hi); 2052 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2053 2054 if (EVT.bitsLE(Lo.getValueType())) { 2055 // sext_inreg the low part if needed. 2056 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo, 2057 N->getOperand(1)); 2058 2059 // The high part gets the sign extension from the lo-part. This handles 2060 // things like sextinreg V:i64 from i8. 2061 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo, 2062 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 2063 TLI.getPointerTy())); 2064 } else { 2065 // For example, extension of an i48 to an i64. Leave the low part alone, 2066 // sext_inreg the high part. 2067 unsigned ExcessBits = 2068 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 2069 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, 2070 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), 2071 ExcessBits))); 2072 } 2073} 2074 2075void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 2076 SDValue &Lo, SDValue &Hi) { 2077 EVT VT = N->getValueType(0); 2078 DebugLoc dl = N->getDebugLoc(); 2079 2080 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2081 if (VT == MVT::i16) 2082 LC = RTLIB::SREM_I16; 2083 else if (VT == MVT::i32) 2084 LC = RTLIB::SREM_I32; 2085 else if (VT == MVT::i64) 2086 LC = RTLIB::SREM_I64; 2087 else if (VT == MVT::i128) 2088 LC = RTLIB::SREM_I128; 2089 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 2090 2091 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2092 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi); 2093} 2094 2095void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 2096 SDValue &Lo, SDValue &Hi) { 2097 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2098 DebugLoc dl = N->getDebugLoc(); 2099 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); 2100 Hi = DAG.getNode(ISD::SRL, dl, 2101 N->getOperand(0).getValueType(), N->getOperand(0), 2102 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy())); 2103 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi); 2104} 2105 2106void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N, 2107 SDValue &Lo, SDValue &Hi) { 2108 SDValue LHS = N->getOperand(0); 2109 SDValue RHS = N->getOperand(1); 2110 DebugLoc dl = N->getDebugLoc(); 2111 2112 // Expand the result by simply replacing it with the equivalent 2113 // non-overflow-checking operation. 2114 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ? 2115 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 2116 LHS, RHS); 2117 SplitInteger(Sum, Lo, Hi); 2118 2119 // Calculate the overflow: addition overflows iff a + b < a, and subtraction 2120 // overflows iff a - b > a. 2121 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, 2122 N->getOpcode () == ISD::UADDO ? 2123 ISD::SETULT : ISD::SETUGT); 2124 2125 // Use the calculated overflow everywhere. 2126 ReplaceValueWith(SDValue(N, 1), Ofl); 2127} 2128 2129void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 2130 SDValue &Lo, SDValue &Hi) { 2131 EVT VT = N->getValueType(0); 2132 DebugLoc dl = N->getDebugLoc(); 2133 2134 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2135 if (VT == MVT::i16) 2136 LC = RTLIB::UDIV_I16; 2137 else if (VT == MVT::i32) 2138 LC = RTLIB::UDIV_I32; 2139 else if (VT == MVT::i64) 2140 LC = RTLIB::UDIV_I64; 2141 else if (VT == MVT::i128) 2142 LC = RTLIB::UDIV_I128; 2143 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 2144 2145 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2146 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 2147} 2148 2149void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 2150 SDValue &Lo, SDValue &Hi) { 2151 EVT VT = N->getValueType(0); 2152 DebugLoc dl = N->getDebugLoc(); 2153 2154 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 2155 if (VT == MVT::i16) 2156 LC = RTLIB::UREM_I16; 2157 else if (VT == MVT::i32) 2158 LC = RTLIB::UREM_I32; 2159 else if (VT == MVT::i64) 2160 LC = RTLIB::UREM_I64; 2161 else if (VT == MVT::i128) 2162 LC = RTLIB::UREM_I128; 2163 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 2164 2165 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) }; 2166 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi); 2167} 2168 2169void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 2170 SDValue &Lo, SDValue &Hi) { 2171 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); 2172 DebugLoc dl = N->getDebugLoc(); 2173 SDValue Op = N->getOperand(0); 2174 if (Op.getValueType().bitsLE(NVT)) { 2175 // The low part is zero extension of the input (degenerates to a copy). 2176 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); 2177 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 2178 } else { 2179 // For example, extension of an i48 to an i64. The operand type necessarily 2180 // promotes to the result type, so will end up being expanded too. 2181 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 2182 "Only know how to promote this result!"); 2183 SDValue Res = GetPromotedInteger(Op); 2184 assert(Res.getValueType() == N->getValueType(0) && 2185 "Operand over promoted?"); 2186 // Split the promoted operand. This will simplify when it is expanded. 2187 SplitInteger(Res, Lo, Hi); 2188 unsigned ExcessBits = 2189 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 2190 Hi = DAG.getZeroExtendInReg(Hi, dl, 2191 EVT::getIntegerVT(*DAG.getContext(), 2192 ExcessBits)); 2193 } 2194} 2195 2196 2197//===----------------------------------------------------------------------===// 2198// Integer Operand Expansion 2199//===----------------------------------------------------------------------===// 2200 2201/// ExpandIntegerOperand - This method is called when the specified operand of 2202/// the specified node is found to need expansion. At this point, all of the 2203/// result types of the node are known to be legal, but other operands of the 2204/// node may need promotion or expansion as well as the specified one. 2205bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 2206 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n"); 2207 SDValue Res = SDValue(); 2208 2209 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) 2210 return false; 2211 2212 switch (N->getOpcode()) { 2213 default: 2214 #ifndef NDEBUG 2215 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": "; 2216 N->dump(&DAG); dbgs() << "\n"; 2217 #endif 2218 llvm_unreachable("Do not know how to expand this operator's operand!"); 2219 2220 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break; 2221 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 2222 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 2223 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 2224 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; 2225 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break; 2226 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 2227 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 2228 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 2229 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break; 2230 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 2231 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 2232 2233 case ISD::SHL: 2234 case ISD::SRA: 2235 case ISD::SRL: 2236 case ISD::ROTL: 2237 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break; 2238 case ISD::RETURNADDR: 2239 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break; 2240 } 2241 2242 // If the result is null, the sub-method took care of registering results etc. 2243 if (!Res.getNode()) return false; 2244 2245 // If the result is N, the sub-method updated N in place. Tell the legalizer 2246 // core about this. 2247 if (Res.getNode() == N) 2248 return true; 2249 2250 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 2251 "Invalid operand expansion"); 2252 2253 ReplaceValueWith(SDValue(N, 0), Res); 2254 return false; 2255} 2256 2257/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 2258/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 2259void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, 2260 SDValue &NewRHS, 2261 ISD::CondCode &CCCode, 2262 DebugLoc dl) { 2263 SDValue LHSLo, LHSHi, RHSLo, RHSHi; 2264 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 2265 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 2266 2267 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 2268 if (RHSLo == RHSHi) { 2269 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 2270 if (RHSCST->isAllOnesValue()) { 2271 // Equality comparison to -1. 2272 NewLHS = DAG.getNode(ISD::AND, dl, 2273 LHSLo.getValueType(), LHSLo, LHSHi); 2274 NewRHS = RHSLo; 2275 return; 2276 } 2277 } 2278 } 2279 2280 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo); 2281 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi); 2282 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS); 2283 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2284 return; 2285 } 2286 2287 // If this is a comparison of the sign bit, just look at the top part. 2288 // X > -1, x < 0 2289 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 2290 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 2291 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 2292 NewLHS = LHSHi; 2293 NewRHS = RHSHi; 2294 return; 2295 } 2296 2297 // FIXME: This generated code sucks. 2298 ISD::CondCode LowCC; 2299 switch (CCCode) { 2300 default: llvm_unreachable("Unknown integer setcc!"); 2301 case ISD::SETLT: 2302 case ISD::SETULT: LowCC = ISD::SETULT; break; 2303 case ISD::SETGT: 2304 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 2305 case ISD::SETLE: 2306 case ISD::SETULE: LowCC = ISD::SETULE; break; 2307 case ISD::SETGE: 2308 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2309 } 2310 2311 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2312 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2313 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2314 2315 // NOTE: on targets without efficient SELECT of bools, we can always use 2316 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2317 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL); 2318 SDValue Tmp1, Tmp2; 2319 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()), 2320 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl); 2321 if (!Tmp1.getNode()) 2322 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()), 2323 LHSLo, RHSLo, LowCC); 2324 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2325 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl); 2326 if (!Tmp2.getNode()) 2327 Tmp2 = DAG.getNode(ISD::SETCC, dl, 2328 TLI.getSetCCResultType(LHSHi.getValueType()), 2329 LHSHi, RHSHi, DAG.getCondCode(CCCode)); 2330 2331 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode()); 2332 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode()); 2333 if ((Tmp1C && Tmp1C->isNullValue()) || 2334 (Tmp2C && Tmp2C->isNullValue() && 2335 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2336 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2337 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2338 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2339 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2340 // low part is known false, returns high part. 2341 // For LE / GE, if high part is known false, ignore the low part. 2342 // For LT / GT, if high part is known true, ignore the low part. 2343 NewLHS = Tmp2; 2344 NewRHS = SDValue(); 2345 return; 2346 } 2347 2348 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()), 2349 LHSHi, RHSHi, ISD::SETEQ, false, 2350 DagCombineInfo, dl); 2351 if (!NewLHS.getNode()) 2352 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()), 2353 LHSHi, RHSHi, ISD::SETEQ); 2354 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(), 2355 NewLHS, Tmp1, Tmp2); 2356 NewRHS = SDValue(); 2357} 2358 2359SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 2360 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 2361 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 2362 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2363 2364 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2365 // against zero to select between true and false values. 2366 if (NewRHS.getNode() == 0) { 2367 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2368 CCCode = ISD::SETNE; 2369 } 2370 2371 // Update N to have the operands specified. 2372 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), 2373 DAG.getCondCode(CCCode), NewLHS, NewRHS, 2374 N->getOperand(4)), 0); 2375} 2376 2377SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 2378 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2379 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 2380 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2381 2382 // If ExpandSetCCOperands returned a scalar, we need to compare the result 2383 // against zero to select between true and false values. 2384 if (NewRHS.getNode() == 0) { 2385 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 2386 CCCode = ISD::SETNE; 2387 } 2388 2389 // Update N to have the operands specified. 2390 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, 2391 N->getOperand(2), N->getOperand(3), 2392 DAG.getCondCode(CCCode)), 0); 2393} 2394 2395SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 2396 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 2397 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 2398 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc()); 2399 2400 // If ExpandSetCCOperands returned a scalar, use it. 2401 if (NewRHS.getNode() == 0) { 2402 assert(NewLHS.getValueType() == N->getValueType(0) && 2403 "Unexpected setcc expansion!"); 2404 return NewLHS; 2405 } 2406 2407 // Otherwise, update N to have the operands specified. 2408 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS, 2409 DAG.getCondCode(CCCode)), 0); 2410} 2411 2412SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) { 2413 // The value being shifted is legal, but the shift amount is too big. 2414 // It follows that either the result of the shift is undefined, or the 2415 // upper half of the shift amount is zero. Just use the lower half. 2416 SDValue Lo, Hi; 2417 GetExpandedInteger(N->getOperand(1), Lo, Hi); 2418 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0); 2419} 2420 2421SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) { 2422 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This 2423 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this 2424 // constant to valid type. 2425 SDValue Lo, Hi; 2426 GetExpandedInteger(N->getOperand(0), Lo, Hi); 2427 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0); 2428} 2429 2430SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 2431 SDValue Op = N->getOperand(0); 2432 EVT DstVT = N->getValueType(0); 2433 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); 2434 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2435 "Don't know how to expand this SINT_TO_FP!"); 2436 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc()); 2437} 2438 2439SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2440 if (ISD::isNormalStore(N)) 2441 return ExpandOp_NormalStore(N, OpNo); 2442 2443 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2444 assert(OpNo == 1 && "Can only expand the stored value so far"); 2445 2446 EVT VT = N->getOperand(1).getValueType(); 2447 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); 2448 SDValue Ch = N->getChain(); 2449 SDValue Ptr = N->getBasePtr(); 2450 unsigned Alignment = N->getAlignment(); 2451 bool isVolatile = N->isVolatile(); 2452 bool isNonTemporal = N->isNonTemporal(); 2453 DebugLoc dl = N->getDebugLoc(); 2454 SDValue Lo, Hi; 2455 2456 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2457 2458 if (N->getMemoryVT().bitsLE(NVT)) { 2459 GetExpandedInteger(N->getValue(), Lo, Hi); 2460 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), 2461 N->getMemoryVT(), isVolatile, isNonTemporal, 2462 Alignment); 2463 } 2464 2465 if (TLI.isLittleEndian()) { 2466 // Little-endian - low bits are at low addresses. 2467 GetExpandedInteger(N->getValue(), Lo, Hi); 2468 2469 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), 2470 isVolatile, isNonTemporal, Alignment); 2471 2472 unsigned ExcessBits = 2473 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2474 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits); 2475 2476 // Increment the pointer to the other half. 2477 unsigned IncrementSize = NVT.getSizeInBits()/8; 2478 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2479 DAG.getIntPtrConstant(IncrementSize)); 2480 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, 2481 N->getPointerInfo().getWithOffset(IncrementSize), 2482 NEVT, isVolatile, isNonTemporal, 2483 MinAlign(Alignment, IncrementSize)); 2484 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2485 } 2486 2487 // Big-endian - high bits are at low addresses. Favor aligned stores at 2488 // the cost of some bit-fiddling. 2489 GetExpandedInteger(N->getValue(), Lo, Hi); 2490 2491 EVT ExtVT = N->getMemoryVT(); 2492 unsigned EBytes = ExtVT.getStoreSize(); 2493 unsigned IncrementSize = NVT.getSizeInBits()/8; 2494 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2495 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(), 2496 ExtVT.getSizeInBits() - ExcessBits); 2497 2498 if (ExcessBits < NVT.getSizeInBits()) { 2499 // Transfer high bits from the top of Lo to the bottom of Hi. 2500 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi, 2501 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2502 TLI.getPointerTy())); 2503 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi, 2504 DAG.getNode(ISD::SRL, dl, NVT, Lo, 2505 DAG.getConstant(ExcessBits, 2506 TLI.getPointerTy()))); 2507 } 2508 2509 // Store both the high bits and maybe some of the low bits. 2510 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(), 2511 HiVT, isVolatile, isNonTemporal, Alignment); 2512 2513 // Increment the pointer to the other half. 2514 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 2515 DAG.getIntPtrConstant(IncrementSize)); 2516 // Store the lowest ExcessBits bits in the second half. 2517 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, 2518 N->getPointerInfo().getWithOffset(IncrementSize), 2519 EVT::getIntegerVT(*DAG.getContext(), ExcessBits), 2520 isVolatile, isNonTemporal, 2521 MinAlign(Alignment, IncrementSize)); 2522 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 2523} 2524 2525SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 2526 SDValue InL, InH; 2527 GetExpandedInteger(N->getOperand(0), InL, InH); 2528 // Just truncate the low part of the source. 2529 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL); 2530} 2531 2532static const fltSemantics *EVTToAPFloatSemantics(EVT VT) { 2533 switch (VT.getSimpleVT().SimpleTy) { 2534 default: llvm_unreachable("Unknown FP format"); 2535 case MVT::f32: return &APFloat::IEEEsingle; 2536 case MVT::f64: return &APFloat::IEEEdouble; 2537 case MVT::f80: return &APFloat::x87DoubleExtended; 2538 case MVT::f128: return &APFloat::IEEEquad; 2539 case MVT::ppcf128: return &APFloat::PPCDoubleDouble; 2540 } 2541} 2542 2543SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 2544 SDValue Op = N->getOperand(0); 2545 EVT SrcVT = Op.getValueType(); 2546 EVT DstVT = N->getValueType(0); 2547 DebugLoc dl = N->getDebugLoc(); 2548 2549 // The following optimization is valid only if every value in SrcVT (when 2550 // treated as signed) is representable in DstVT. Check that the mantissa 2551 // size of DstVT is >= than the number of bits in SrcVT -1. 2552 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT); 2553 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 && 2554 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 2555 // Do a signed conversion then adjust the result. 2556 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); 2557 SignedConv = TLI.LowerOperation(SignedConv, DAG); 2558 2559 // The result of the signed conversion needs adjusting if the 'sign bit' of 2560 // the incoming integer was set. To handle this, we dynamically test to see 2561 // if it is set, and, if so, add a fudge factor. 2562 2563 const uint64_t F32TwoE32 = 0x4F800000ULL; 2564 const uint64_t F32TwoE64 = 0x5F800000ULL; 2565 const uint64_t F32TwoE128 = 0x7F800000ULL; 2566 2567 APInt FF(32, 0); 2568 if (SrcVT == MVT::i32) 2569 FF = APInt(32, F32TwoE32); 2570 else if (SrcVT == MVT::i64) 2571 FF = APInt(32, F32TwoE64); 2572 else if (SrcVT == MVT::i128) 2573 FF = APInt(32, F32TwoE128); 2574 else 2575 assert(false && "Unsupported UINT_TO_FP!"); 2576 2577 // Check whether the sign bit is set. 2578 SDValue Lo, Hi; 2579 GetExpandedInteger(Op, Lo, Hi); 2580 SDValue SignSet = DAG.getSetCC(dl, 2581 TLI.getSetCCResultType(Hi.getValueType()), 2582 Hi, DAG.getConstant(0, Hi.getValueType()), 2583 ISD::SETLT); 2584 2585 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 2586 SDValue FudgePtr = DAG.getConstantPool( 2587 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 2588 TLI.getPointerTy()); 2589 2590 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 2591 SDValue Zero = DAG.getIntPtrConstant(0); 2592 SDValue Four = DAG.getIntPtrConstant(4); 2593 if (TLI.isBigEndian()) std::swap(Zero, Four); 2594 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 2595 Zero, Four); 2596 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment(); 2597 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset); 2598 Alignment = std::min(Alignment, 4u); 2599 2600 // Load the value out, extending it from f32 to the destination float type. 2601 // FIXME: Avoid the extend by constructing the right constant pool? 2602 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), 2603 FudgePtr, 2604 MachinePointerInfo::getConstantPool(), 2605 MVT::f32, 2606 false, false, Alignment); 2607 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); 2608 } 2609 2610 // Otherwise, use a libcall. 2611 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); 2612 assert(LC != RTLIB::UNKNOWN_LIBCALL && 2613 "Don't know how to expand this UINT_TO_FP!"); 2614 return MakeLibCall(LC, DstVT, &Op, 1, true, dl); 2615} 2616