LegalizeIntegerTypes.cpp revision 8d56a6f4d8b010d4c582225a08ece971613f6fe3
1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements integer type expansion and promotion for LegalizeTypes. 11// Promotion is the act of changing a computation in an illegal type into a 12// computation in a larger type. For example, implementing i8 arithmetic in an 13// i32 register (often needed on powerpc). 14// Expansion is the act of changing a computation in an illegal type into a 15// computation in two identical registers of a smaller type. For example, 16// implementing i64 arithmetic in two i32 registers (often needed on 32-bit 17// targets). 18// 19//===----------------------------------------------------------------------===// 20 21#include "LegalizeTypes.h" 22using namespace llvm; 23 24//===----------------------------------------------------------------------===// 25// Integer Result Promotion 26//===----------------------------------------------------------------------===// 27 28/// PromoteIntegerResult - This method is called when a result of a node is 29/// found to be in need of promotion to a larger type. At this point, the node 30/// may also have invalid operands or may have other results that need 31/// expansion, we just know that (at least) one result needs promotion. 32void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { 33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); 34 SDOperand Result = SDOperand(); 35 36 // See if the target wants to custom expand this node. 37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 38 TargetLowering::Custom) { 39 // If the target wants to, allow it to lower this itself. 40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 41 // Everything that once used N now uses P. We are guaranteed that the 42 // result value types of N and the result value types of P match. 43 ReplaceNodeWith(N, P); 44 return; 45 } 46 } 47 48 switch (N->getOpcode()) { 49 default: 50#ifndef NDEBUG 51 cerr << "PromoteIntegerResult #" << ResNo << ": "; 52 N->dump(&DAG); cerr << "\n"; 53#endif 54 assert(0 && "Do not know how to promote this operator!"); 55 abort(); 56 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break; 57 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break; 58 case ISD::Constant: Result = PromoteIntRes_Constant(N); break; 59 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break; 60 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break; 61 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break; 62 case ISD::EXTRACT_VECTOR_ELT: 63 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; 64 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; 65 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break; 66 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break; 67 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break; 68 case ISD::SHL: Result = PromoteIntRes_SHL(N); break; 69 case ISD::SIGN_EXTEND_INREG: 70 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break; 71 case ISD::SRA: Result = PromoteIntRes_SRA(N); break; 72 case ISD::SRL: Result = PromoteIntRes_SRL(N); break; 73 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break; 74 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break; 75 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break; 76 77 case ISD::SIGN_EXTEND: 78 case ISD::ZERO_EXTEND: 79 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break; 80 81 case ISD::FP_TO_SINT: 82 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break; 83 84 case ISD::AND: 85 case ISD::OR: 86 case ISD::XOR: 87 case ISD::ADD: 88 case ISD::SUB: 89 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break; 90 91 case ISD::SDIV: 92 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break; 93 94 case ISD::UDIV: 95 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break; 96 } 97 98 // If Result is null, the sub-method took care of registering the result. 99 if (Result.Val) 100 SetPromotedInteger(SDOperand(N, ResNo), Result); 101} 102 103SDOperand DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { 104 SDOperand InOp = N->getOperand(0); 105 MVT InVT = InOp.getValueType(); 106 MVT NInVT = TLI.getTypeToTransformTo(InVT); 107 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); 108 109 switch (getTypeAction(InVT)) { 110 default: 111 assert(false && "Unknown type action!"); 112 break; 113 case Legal: 114 break; 115 case PromoteInteger: 116 if (OutVT.getSizeInBits() == NInVT.getSizeInBits()) 117 // The input promotes to the same size. Convert the promoted value. 118 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp)); 119 break; 120 case SoftenFloat: 121 // Promote the integer operand by hand. 122 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp)); 123 case ExpandInteger: 124 case ExpandFloat: 125 break; 126 case ScalarizeVector: 127 // Convert the element to an integer and promote it by hand. 128 return DAG.getNode(ISD::ANY_EXTEND, OutVT, 129 BitConvertToInteger(GetScalarizedVector(InOp))); 130 case SplitVector: 131 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split 132 // pieces of the input into integers and reassemble in the final type. 133 SDOperand Lo, Hi; 134 GetSplitVector(N->getOperand(0), Lo, Hi); 135 Lo = BitConvertToInteger(Lo); 136 Hi = BitConvertToInteger(Hi); 137 138 if (TLI.isBigEndian()) 139 std::swap(Lo, Hi); 140 141 InOp = DAG.getNode(ISD::ANY_EXTEND, 142 MVT::getIntegerVT(OutVT.getSizeInBits()), 143 JoinIntegers(Lo, Hi)); 144 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp); 145 } 146 147 // Otherwise, lower the bit-convert to a store/load from the stack, then 148 // promote the load. 149 SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0)); 150 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val)); 151} 152 153SDOperand DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { 154 // The pair element type may be legal, or may not promote to the same type as 155 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases. 156 return DAG.getNode(ISD::ANY_EXTEND, 157 TLI.getTypeToTransformTo(N->getValueType(0)), 158 JoinIntegers(N->getOperand(0), N->getOperand(1))); 159} 160 161SDOperand DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { 162 MVT VT = N->getValueType(0); 163 // Zero extend things like i1, sign extend everything else. It shouldn't 164 // matter in theory which one we pick, but this tends to give better code? 165 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 166 SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT), 167 SDOperand(N, 0)); 168 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"); 169 return Result; 170} 171 172SDOperand DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { 173 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 174 MVT OVT = N->getValueType(0); 175 MVT NVT = Op.getValueType(); 176 // Zero extend to the promoted type and do the count there. 177 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT)); 178 // Subtract off the extra leading bits in the bigger type. 179 return DAG.getNode(ISD::SUB, NVT, Op, 180 DAG.getConstant(NVT.getSizeInBits() - 181 OVT.getSizeInBits(), NVT)); 182} 183 184SDOperand DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { 185 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 186 MVT OVT = N->getValueType(0); 187 MVT NVT = Op.getValueType(); 188 // Zero extend to the promoted type and do the count there. 189 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT)); 190} 191 192SDOperand DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { 193 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 194 MVT OVT = N->getValueType(0); 195 MVT NVT = Op.getValueType(); 196 // The count is the same in the promoted type except if the original 197 // value was zero. This can be handled by setting the bit just off 198 // the top of the original type. 199 APInt TopBit(NVT.getSizeInBits(), 0); 200 TopBit.set(OVT.getSizeInBits()); 201 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT)); 202 return DAG.getNode(ISD::CTTZ, NVT, Op); 203} 204 205SDOperand DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { 206 MVT OldVT = N->getValueType(0); 207 SDOperand OldVec = N->getOperand(0); 208 unsigned OldElts = OldVec.getValueType().getVectorNumElements(); 209 210 if (OldElts == 1) { 211 assert(!isTypeLegal(OldVec.getValueType()) && 212 "Legal one-element vector of a type needing promotion!"); 213 // It is tempting to follow GetScalarizedVector by a call to 214 // GetPromotedInteger, but this would be wrong because the 215 // scalarized value may not yet have been processed. 216 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), 217 GetScalarizedVector(OldVec)); 218 } 219 220 // Convert to a vector half as long with an element type of twice the width, 221 // for example <4 x i16> -> <2 x i32>. 222 assert(!(OldElts & 1) && "Odd length vectors not supported!"); 223 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 224 assert(OldVT.isSimple() && NewVT.isSimple()); 225 226 SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT, 227 MVT::getVectorVT(NewVT, OldElts / 2), 228 OldVec); 229 230 // Extract the element at OldIdx / 2 from the new vector. 231 SDOperand OldIdx = N->getOperand(1); 232 SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx, 233 DAG.getConstant(1, TLI.getShiftAmountTy())); 234 SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx); 235 236 // Select the appropriate half of the element: Lo if OldIdx was even, 237 // Hi if it was odd. 238 SDOperand Lo = Elt; 239 SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt, 240 DAG.getConstant(OldVT.getSizeInBits(), 241 TLI.getShiftAmountTy())); 242 if (TLI.isBigEndian()) 243 std::swap(Lo, Hi); 244 245 SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx, 246 DAG.getConstant(1, TLI.getShiftAmountTy())); 247 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo); 248} 249 250SDOperand DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { 251 unsigned NewOpc = N->getOpcode(); 252 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 253 254 // If we're promoting a UINT to a larger size, check to see if the new node 255 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since 256 // we can use that instead. This allows us to generate better code for 257 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not 258 // legal, such as PowerPC. 259 if (N->getOpcode() == ISD::FP_TO_UINT) { 260 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) && 261 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) || 262 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)) 263 NewOpc = ISD::FP_TO_SINT; 264 } 265 266 return DAG.getNode(NewOpc, NVT, N->getOperand(0)); 267} 268 269SDOperand DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { 270 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 271 272 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { 273 SDOperand Res = GetPromotedInteger(N->getOperand(0)); 274 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() && 275 "Extension doesn't make sense!"); 276 277 // If the result and operand types are the same after promotion, simplify 278 // to an in-register extension. 279 if (NVT == Res.getValueType()) { 280 // The high bits are not guaranteed to be anything. Insert an extend. 281 if (N->getOpcode() == ISD::SIGN_EXTEND) 282 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, 283 DAG.getValueType(N->getOperand(0).getValueType())); 284 if (N->getOpcode() == ISD::ZERO_EXTEND) 285 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType()); 286 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"); 287 return Res; 288 } 289 } 290 291 // Otherwise, just extend the original operand all the way to the larger type. 292 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0)); 293} 294 295SDOperand DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { 296 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 297 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 298 ISD::LoadExtType ExtType = 299 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); 300 SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(), 301 N->getSrcValue(), N->getSrcValueOffset(), 302 N->getMemoryVT(), N->isVolatile(), 303 N->getAlignment()); 304 305 // Legalized the chain result - switch anything that used the old chain to 306 // use the new one. 307 ReplaceValueWith(SDOperand(N, 1), Res.getValue(1)); 308 return Res; 309} 310 311SDOperand DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) { 312 // Sign extend the input. 313 SDOperand LHS = GetPromotedInteger(N->getOperand(0)); 314 SDOperand RHS = GetPromotedInteger(N->getOperand(1)); 315 MVT VT = N->getValueType(0); 316 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS, 317 DAG.getValueType(VT)); 318 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS, 319 DAG.getValueType(VT)); 320 321 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 322} 323 324SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) { 325 SDOperand LHS = GetPromotedInteger(N->getOperand(1)); 326 SDOperand RHS = GetPromotedInteger(N->getOperand(2)); 327 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS); 328} 329 330SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { 331 SDOperand LHS = GetPromotedInteger(N->getOperand(2)); 332 SDOperand RHS = GetPromotedInteger(N->getOperand(3)); 333 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0), 334 N->getOperand(1), LHS, RHS, N->getOperand(4)); 335} 336 337SDOperand DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { 338 assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0))) 339 && "SetCC type is not legal??"); 340 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)), 341 N->getOperand(0), N->getOperand(1), N->getOperand(2)); 342} 343 344SDOperand DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) { 345 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)), 346 GetPromotedInteger(N->getOperand(0)), N->getOperand(1)); 347} 348 349SDOperand DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) { 350 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 351 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op, 352 N->getOperand(1)); 353} 354 355SDOperand DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) { 356 // The input may have strange things in the top bits of the registers, but 357 // these operations don't care. They may have weird bits going out, but 358 // that too is okay if they are integer operations. 359 SDOperand LHS = GetPromotedInteger(N->getOperand(0)); 360 SDOperand RHS = GetPromotedInteger(N->getOperand(1)); 361 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 362} 363 364SDOperand DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { 365 // The input value must be properly sign extended. 366 MVT VT = N->getValueType(0); 367 MVT NVT = TLI.getTypeToTransformTo(VT); 368 SDOperand Res = GetPromotedInteger(N->getOperand(0)); 369 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT)); 370 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1)); 371} 372 373SDOperand DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { 374 // The input value must be properly zero extended. 375 MVT VT = N->getValueType(0); 376 MVT NVT = TLI.getTypeToTransformTo(VT); 377 SDOperand Res = ZExtPromotedInteger(N->getOperand(0)); 378 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1)); 379} 380 381SDOperand DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { 382 SDOperand Res; 383 384 switch (getTypeAction(N->getOperand(0).getValueType())) { 385 default: assert(0 && "Unknown type action!"); 386 case Legal: 387 case ExpandInteger: 388 Res = N->getOperand(0); 389 break; 390 case PromoteInteger: 391 Res = GetPromotedInteger(N->getOperand(0)); 392 break; 393 } 394 395 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 396 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() && 397 "Truncation doesn't make sense!"); 398 if (Res.getValueType() == NVT) 399 return Res; 400 401 // Truncate to NVT instead of VT 402 return DAG.getNode(ISD::TRUNCATE, NVT, Res); 403} 404 405SDOperand DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) { 406 // Zero extend the input. 407 SDOperand LHS = GetPromotedInteger(N->getOperand(0)); 408 SDOperand RHS = GetPromotedInteger(N->getOperand(1)); 409 MVT VT = N->getValueType(0); 410 LHS = DAG.getZeroExtendInReg(LHS, VT); 411 RHS = DAG.getZeroExtendInReg(RHS, VT); 412 413 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS); 414} 415 416SDOperand DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { 417 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0))); 418} 419 420SDOperand DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { 421 SDOperand Chain = N->getOperand(0); // Get the chain. 422 SDOperand Ptr = N->getOperand(1); // Get the pointer. 423 MVT VT = N->getValueType(0); 424 425 const Value *V = cast<SrcValueSDNode>(N->getOperand(2))->getValue(); 426 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0); 427 428 // Increment the arg pointer, VAList, to the next vaarg 429 // FIXME: should the ABI size be used for the increment? Think of 430 // x86 long double (10 bytes long, but aligned on 4 or 8 bytes) or 431 // integers of unusual size (such MVT::i1, which gives an increment 432 // of zero here!). 433 unsigned Increment = VT.getSizeInBits() / 8; 434 SDOperand Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList, 435 DAG.getConstant(Increment, TLI.getPointerTy())); 436 437 // Store the incremented VAList to the pointer. 438 Tmp = DAG.getStore(VAList.getValue(1), Tmp, Ptr, V, 0); 439 440 // Load the actual argument out of the arg pointer VAList. 441 Tmp = DAG.getExtLoad(ISD::EXTLOAD, TLI.getTypeToTransformTo(VT), Tmp, 442 VAList, NULL, 0, VT); 443 444 // Legalized the chain result - switch anything that used the old chain to 445 // use the new one. 446 ReplaceValueWith(SDOperand(N, 1), Tmp.getValue(1)); 447 return Tmp; 448} 449 450 451//===----------------------------------------------------------------------===// 452// Integer Operand Promotion 453//===----------------------------------------------------------------------===// 454 455/// PromoteIntegerOperand - This method is called when the specified operand of 456/// the specified node is found to need promotion. At this point, all of the 457/// result types of the node are known to be legal, but other operands of the 458/// node may need promotion or expansion as well as the specified one. 459bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { 460 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); 461 SDOperand Res = SDOperand(); 462 463 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 464 == TargetLowering::Custom) 465 Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG); 466 467 if (Res.Val == 0) { 468 switch (N->getOpcode()) { 469 default: 470 #ifndef NDEBUG 471 cerr << "PromoteIntegerOperand Op #" << OpNo << ": "; 472 N->dump(&DAG); cerr << "\n"; 473 #endif 474 assert(0 && "Do not know how to promote this operator's operand!"); 475 abort(); 476 477 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break; 478 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break; 479 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break; 480 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; 481 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; 482 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break; 483 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break; 484 case ISD::INSERT_VECTOR_ELT: 485 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break; 486 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break; 487 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break; 488 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; 489 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break; 490 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; 491 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N), 492 OpNo); break; 493 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break; 494 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; 495 496 case ISD::SINT_TO_FP: 497 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break; 498 } 499 } 500 501 // If the result is null, the sub-method took care of registering results etc. 502 if (!Res.Val) return false; 503 // If the result is N, the sub-method updated N in place. 504 if (Res.Val == N) { 505 // Mark N as new and remark N and its operands. This allows us to correctly 506 // revisit N if it needs another step of promotion and allows us to visit 507 // any new operands to N. 508 ReanalyzeNode(N); 509 return true; 510 } 511 512 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 513 "Invalid operand expansion"); 514 515 ReplaceValueWith(SDOperand(N, 0), Res); 516 return false; 517} 518 519/// PromoteSetCCOperands - Promote the operands of a comparison. This code is 520/// shared among BR_CC, SELECT_CC, and SETCC handlers. 521void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS, 522 ISD::CondCode CCCode) { 523 MVT VT = NewLHS.getValueType(); 524 525 // Get the promoted values. 526 NewLHS = GetPromotedInteger(NewLHS); 527 NewRHS = GetPromotedInteger(NewRHS); 528 529 // Otherwise, we have to insert explicit sign or zero extends. Note 530 // that we could insert sign extends for ALL conditions, but zero extend 531 // is cheaper on many machines (an AND instead of two shifts), so prefer 532 // it. 533 switch (CCCode) { 534 default: assert(0 && "Unknown integer comparison!"); 535 case ISD::SETEQ: 536 case ISD::SETNE: 537 case ISD::SETUGE: 538 case ISD::SETUGT: 539 case ISD::SETULE: 540 case ISD::SETULT: 541 // ALL of these operations will work if we either sign or zero extend 542 // the operands (including the unsigned comparisons!). Zero extend is 543 // usually a simpler/cheaper operation, so prefer it. 544 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT); 545 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT); 546 break; 547 case ISD::SETGE: 548 case ISD::SETGT: 549 case ISD::SETLT: 550 case ISD::SETLE: 551 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS, 552 DAG.getValueType(VT)); 553 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS, 554 DAG.getValueType(VT)); 555 break; 556 } 557} 558 559SDOperand DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) { 560 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 561 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 562} 563 564SDOperand DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) { 565 assert(OpNo == 2 && "Don't know how to promote this operand!"); 566 567 SDOperand LHS = N->getOperand(2); 568 SDOperand RHS = N->getOperand(3); 569 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get()); 570 571 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always 572 // legal types. 573 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), 574 N->getOperand(1), LHS, RHS, N->getOperand(4)); 575} 576 577SDOperand DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { 578 assert(OpNo == 1 && "only know how to promote condition"); 579 SDOperand Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition. 580 581 // The top bits of the promoted condition are not necessarily zero, ensure 582 // that the value is properly zero extended. 583 unsigned BitWidth = Cond.getValueSizeInBits(); 584 if (!DAG.MaskedValueIsZero(Cond, 585 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 586 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); 587 588 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 589 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond, 590 N->getOperand(2)); 591} 592 593SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { 594 // Since the result type is legal, the operands must promote to it. 595 MVT OVT = N->getOperand(0).getValueType(); 596 SDOperand Lo = GetPromotedInteger(N->getOperand(0)); 597 SDOperand Hi = GetPromotedInteger(N->getOperand(1)); 598 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); 599 600 Lo = DAG.getZeroExtendInReg(Lo, OVT); 601 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi, 602 DAG.getConstant(OVT.getSizeInBits(), 603 TLI.getShiftAmountTy())); 604 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi); 605} 606 607SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { 608 // The vector type is legal but the element type is not. This implies 609 // that the vector is a power-of-two in length and that the element 610 // type does not have a strange size (eg: it is not i1). 611 MVT VecVT = N->getValueType(0); 612 unsigned NumElts = VecVT.getVectorNumElements(); 613 assert(!(NumElts & 1) && "Legal vector of one illegal element?"); 614 615 // Build a vector of half the length out of elements of twice the bitwidth. 616 // For example <4 x i16> -> <2 x i32>. 617 MVT OldVT = N->getOperand(0).getValueType(); 618 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits()); 619 assert(OldVT.isSimple() && NewVT.isSimple()); 620 621 std::vector<SDOperand> NewElts; 622 NewElts.reserve(NumElts/2); 623 624 for (unsigned i = 0; i < NumElts; i += 2) { 625 // Combine two successive elements into one promoted element. 626 SDOperand Lo = N->getOperand(i); 627 SDOperand Hi = N->getOperand(i+1); 628 if (TLI.isBigEndian()) 629 std::swap(Lo, Hi); 630 NewElts.push_back(JoinIntegers(Lo, Hi)); 631 } 632 633 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR, 634 MVT::getVectorVT(NewVT, NewElts.size()), 635 &NewElts[0], NewElts.size()); 636 637 // Convert the new vector to the old vector type. 638 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec); 639} 640 641SDOperand DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) { 642 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 643 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op); 644} 645 646SDOperand DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) { 647 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 648 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op, 649 DAG.getIntPtrConstant(0)); 650} 651 652SDOperand DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N, 653 unsigned OpNo) { 654 if (OpNo == 1) { 655 // Promote the inserted value. This is valid because the type does not 656 // have to match the vector element type. 657 658 // Check that any extra bits introduced will be truncated away. 659 assert(N->getOperand(1).getValueType().getSizeInBits() >= 660 N->getValueType(0).getVectorElementType().getSizeInBits() && 661 "Type of inserted value narrower than vector element type!"); 662 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), 663 GetPromotedInteger(N->getOperand(1)), 664 N->getOperand(2)); 665 } 666 667 assert(OpNo == 2 && "Different operand and result vector types?"); 668 669 // Promote the index. 670 SDOperand Idx = N->getOperand(2); 671 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType()); 672 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), 673 N->getOperand(1), Idx); 674} 675 676SDOperand DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) { 677 SDOperand In = GetPromotedInteger(N->getOperand(0)); 678 MVT OpVT = N->getOperand(0).getValueType(); 679 if (N->getOpcode() == ISD::UINT_TO_FP) 680 In = DAG.getZeroExtendInReg(In, OpVT); 681 else 682 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), 683 In, DAG.getValueType(OpVT)); 684 685 return DAG.UpdateNodeOperands(SDOperand(N, 0), In); 686} 687 688SDOperand DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { 689 SDOperand NewOps[6]; 690 NewOps[0] = N->getOperand(0); 691 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { 692 SDOperand Flag = GetPromotedInteger(N->getOperand(i)); 693 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1); 694 } 695 return DAG.UpdateNodeOperands(SDOperand (N, 0), NewOps, 696 array_lengthof(NewOps)); 697} 698 699SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { 700 assert(OpNo == 0 && "Only know how to promote condition"); 701 SDOperand Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition. 702 703 // The top bits of the promoted condition are not necessarily zero, ensure 704 // that the value is properly zero extended. 705 unsigned BitWidth = Cond.getValueSizeInBits(); 706 if (!DAG.MaskedValueIsZero(Cond, 707 APInt::getHighBitsSet(BitWidth, BitWidth-1))) 708 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1); 709 710 // The chain (Op#0) and basic block destination (Op#2) are always legal types. 711 return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1), 712 N->getOperand(2)); 713} 714 715SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) { 716 assert(OpNo == 0 && "Don't know how to promote this operand!"); 717 718 SDOperand LHS = N->getOperand(0); 719 SDOperand RHS = N->getOperand(1); 720 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get()); 721 722 // The CC (#4) and the possible return values (#2 and #3) have legal types. 723 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2), 724 N->getOperand(3), N->getOperand(4)); 725} 726 727SDOperand DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) { 728 assert(OpNo == 0 && "Don't know how to promote this operand!"); 729 730 SDOperand LHS = N->getOperand(0); 731 SDOperand RHS = N->getOperand(1); 732 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get()); 733 734 // The CC (#2) is always legal. 735 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2)); 736} 737 738SDOperand DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) { 739 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 740 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 741 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), 742 Op, DAG.getValueType(N->getOperand(0).getValueType())); 743} 744 745SDOperand DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){ 746 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 747 SDOperand Ch = N->getChain(), Ptr = N->getBasePtr(); 748 int SVOffset = N->getSrcValueOffset(); 749 unsigned Alignment = N->getAlignment(); 750 bool isVolatile = N->isVolatile(); 751 752 SDOperand Val = GetPromotedInteger(N->getValue()); // Get promoted value. 753 754 assert(!N->isTruncatingStore() && "Cannot promote this store operand!"); 755 756 // Truncate the value and store the result. 757 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(), 758 SVOffset, N->getMemoryVT(), 759 isVolatile, Alignment); 760} 761 762SDOperand DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) { 763 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 764 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op); 765} 766 767SDOperand DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) { 768 SDOperand Op = GetPromotedInteger(N->getOperand(0)); 769 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op); 770 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType()); 771} 772 773 774//===----------------------------------------------------------------------===// 775// Integer Result Expansion 776//===----------------------------------------------------------------------===// 777 778/// ExpandIntegerResult - This method is called when the specified result of the 779/// specified node is found to need expansion. At this point, the node may also 780/// have invalid operands or may have other results that need promotion, we just 781/// know that (at least) one result needs expansion. 782void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { 783 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n"); 784 SDOperand Lo, Hi; 785 Lo = Hi = SDOperand(); 786 787 // See if the target wants to custom expand this node. 788 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) == 789 TargetLowering::Custom) { 790 // If the target wants to, allow it to lower this itself. 791 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) { 792 // Everything that once used N now uses P. We are guaranteed that the 793 // result value types of N and the result value types of P match. 794 ReplaceNodeWith(N, P); 795 return; 796 } 797 } 798 799 switch (N->getOpcode()) { 800 default: 801#ifndef NDEBUG 802 cerr << "ExpandIntegerResult #" << ResNo << ": "; 803 N->dump(&DAG); cerr << "\n"; 804#endif 805 assert(0 && "Do not know how to expand the result of this operator!"); 806 abort(); 807 808 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break; 809 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; 810 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; 811 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; 812 813 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break; 814 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; 815 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; 816 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; 817 818 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break; 819 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break; 820 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; 821 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; 822 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; 823 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break; 824 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break; 825 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; 826 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break; 827 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break; 828 829 case ISD::AND: 830 case ISD::OR: 831 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break; 832 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break; 833 case ISD::ADD: 834 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 835 case ISD::ADDC: 836 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; 837 case ISD::ADDE: 838 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break; 839 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break; 840 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break; 841 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; 842 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; 843 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; 844 case ISD::SHL: 845 case ISD::SRA: 846 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break; 847 848 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; 849 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break; 850 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; 851 } 852 853 // If Lo/Hi is null, the sub-method took care of registering results etc. 854 if (Lo.Val) 855 SetExpandedInteger(SDOperand(N, ResNo), Lo, Hi); 856} 857 858void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, 859 SDOperand &Lo, SDOperand &Hi) { 860 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 861 unsigned NBitWidth = NVT.getSizeInBits(); 862 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); 863 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); 864 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT); 865} 866 867void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, 868 SDOperand &Lo, SDOperand &Hi) { 869 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 870 SDOperand Op = N->getOperand(0); 871 if (Op.getValueType().bitsLE(NVT)) { 872 // The low part is any extension of the input (which degenerates to a copy). 873 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op); 874 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined. 875 } else { 876 // For example, extension of an i48 to an i64. The operand type necessarily 877 // promotes to the result type, so will end up being expanded too. 878 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 879 "Only know how to promote this result!"); 880 SDOperand Res = GetPromotedInteger(Op); 881 assert(Res.getValueType() == N->getValueType(0) && 882 "Operand over promoted?"); 883 // Split the promoted operand. This will simplify when it is expanded. 884 SplitInteger(Res, Lo, Hi); 885 } 886} 887 888void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, 889 SDOperand &Lo, SDOperand &Hi) { 890 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 891 SDOperand Op = N->getOperand(0); 892 if (Op.getValueType().bitsLE(NVT)) { 893 // The low part is zero extension of the input (which degenerates to a copy). 894 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0)); 895 Hi = DAG.getConstant(0, NVT); // The high part is just a zero. 896 } else { 897 // For example, extension of an i48 to an i64. The operand type necessarily 898 // promotes to the result type, so will end up being expanded too. 899 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 900 "Only know how to promote this result!"); 901 SDOperand Res = GetPromotedInteger(Op); 902 assert(Res.getValueType() == N->getValueType(0) && 903 "Operand over promoted?"); 904 // Split the promoted operand. This will simplify when it is expanded. 905 SplitInteger(Res, Lo, Hi); 906 unsigned ExcessBits = 907 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 908 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits)); 909 } 910} 911 912void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, 913 SDOperand &Lo, SDOperand &Hi) { 914 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 915 SDOperand Op = N->getOperand(0); 916 if (Op.getValueType().bitsLE(NVT)) { 917 // The low part is sign extension of the input (which degenerates to a copy). 918 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0)); 919 // The high part is obtained by SRA'ing all but one of the bits of low part. 920 unsigned LoSize = NVT.getSizeInBits(); 921 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 922 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 923 } else { 924 // For example, extension of an i48 to an i64. The operand type necessarily 925 // promotes to the result type, so will end up being expanded too. 926 assert(getTypeAction(Op.getValueType()) == PromoteInteger && 927 "Only know how to promote this result!"); 928 SDOperand Res = GetPromotedInteger(Op); 929 assert(Res.getValueType() == N->getValueType(0) && 930 "Operand over promoted?"); 931 // Split the promoted operand. This will simplify when it is expanded. 932 SplitInteger(Res, Lo, Hi); 933 unsigned ExcessBits = 934 Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); 935 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 936 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 937 } 938} 939 940void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, 941 SDOperand &Lo, SDOperand &Hi) { 942 GetExpandedInteger(N->getOperand(0), Lo, Hi); 943 MVT NVT = Lo.getValueType(); 944 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 945 unsigned NVTBits = NVT.getSizeInBits(); 946 unsigned EVTBits = EVT.getSizeInBits(); 947 948 if (NVTBits < EVTBits) { 949 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi, 950 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); 951 } else { 952 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT)); 953 // The high part must be zero, make it explicit. 954 Hi = DAG.getConstant(0, NVT); 955 } 956} 957 958void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, 959 SDOperand &Lo, SDOperand &Hi) { 960 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 961 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0)); 962 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0), 963 DAG.getConstant(NVT.getSizeInBits(), 964 TLI.getShiftAmountTy())); 965 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi); 966} 967 968void DAGTypeLegalizer:: 969ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) { 970 GetExpandedInteger(N->getOperand(0), Lo, Hi); 971 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 972 973 if (EVT.bitsLE(Lo.getValueType())) { 974 // sext_inreg the low part if needed. 975 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo, 976 N->getOperand(1)); 977 978 // The high part gets the sign extension from the lo-part. This handles 979 // things like sextinreg V:i64 from i8. 980 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo, 981 DAG.getConstant(Hi.getValueType().getSizeInBits()-1, 982 TLI.getShiftAmountTy())); 983 } else { 984 // For example, extension of an i48 to an i64. Leave the low part alone, 985 // sext_inreg the high part. 986 unsigned ExcessBits = 987 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); 988 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi, 989 DAG.getValueType(MVT::getIntegerVT(ExcessBits))); 990 } 991} 992 993void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo, 994 SDOperand &Hi) { 995 MVT VT = N->getValueType(0); 996 SDOperand Op = N->getOperand(0); 997 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 998 999 if (VT == MVT::i32) { 1000 if (Op.getValueType() == MVT::f32) 1001 LC = RTLIB::FPTOSINT_F32_I32; 1002 else if (Op.getValueType() == MVT::f64) 1003 LC = RTLIB::FPTOSINT_F64_I32; 1004 else if (Op.getValueType() == MVT::f80) 1005 LC = RTLIB::FPTOSINT_F80_I32; 1006 else if (Op.getValueType() == MVT::ppcf128) 1007 LC = RTLIB::FPTOSINT_PPCF128_I32; 1008 } else if (VT == MVT::i64) { 1009 if (Op.getValueType() == MVT::f32) 1010 LC = RTLIB::FPTOSINT_F32_I64; 1011 else if (Op.getValueType() == MVT::f64) 1012 LC = RTLIB::FPTOSINT_F64_I64; 1013 else if (Op.getValueType() == MVT::f80) 1014 LC = RTLIB::FPTOSINT_F80_I64; 1015 else if (Op.getValueType() == MVT::ppcf128) 1016 LC = RTLIB::FPTOSINT_PPCF128_I64; 1017 } else if (VT == MVT::i128) { 1018 if (Op.getValueType() == MVT::f32) 1019 LC = RTLIB::FPTOSINT_F32_I128; 1020 else if (Op.getValueType() == MVT::f64) 1021 LC = RTLIB::FPTOSINT_F64_I128; 1022 else if (Op.getValueType() == MVT::f80) 1023 LC = RTLIB::FPTOSINT_F80_I128; 1024 else if (Op.getValueType() == MVT::ppcf128) 1025 LC = RTLIB::FPTOSINT_PPCF128_I128; 1026 } 1027 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); 1028 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi); 1029} 1030 1031void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo, 1032 SDOperand &Hi) { 1033 MVT VT = N->getValueType(0); 1034 SDOperand Op = N->getOperand(0); 1035 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1036 if (VT == MVT::i32) { 1037 if (Op.getValueType() == MVT::f32) 1038 LC = RTLIB::FPTOUINT_F32_I32; 1039 else if (Op.getValueType() == MVT::f64) 1040 LC = RTLIB::FPTOUINT_F64_I32; 1041 else if (Op.getValueType() == MVT::f80) 1042 LC = RTLIB::FPTOUINT_F80_I32; 1043 else if (Op.getValueType() == MVT::ppcf128) 1044 LC = RTLIB::FPTOUINT_PPCF128_I32; 1045 } else if (VT == MVT::i64) { 1046 if (Op.getValueType() == MVT::f32) 1047 LC = RTLIB::FPTOUINT_F32_I64; 1048 else if (Op.getValueType() == MVT::f64) 1049 LC = RTLIB::FPTOUINT_F64_I64; 1050 else if (Op.getValueType() == MVT::f80) 1051 LC = RTLIB::FPTOUINT_F80_I64; 1052 else if (Op.getValueType() == MVT::ppcf128) 1053 LC = RTLIB::FPTOUINT_PPCF128_I64; 1054 } else if (VT == MVT::i128) { 1055 if (Op.getValueType() == MVT::f32) 1056 LC = RTLIB::FPTOUINT_F32_I128; 1057 else if (Op.getValueType() == MVT::f64) 1058 LC = RTLIB::FPTOUINT_F64_I128; 1059 else if (Op.getValueType() == MVT::f80) 1060 LC = RTLIB::FPTOUINT_F80_I128; 1061 else if (Op.getValueType() == MVT::ppcf128) 1062 LC = RTLIB::FPTOUINT_PPCF128_I128; 1063 } 1064 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); 1065 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi); 1066} 1067 1068void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, 1069 SDOperand &Lo, SDOperand &Hi) { 1070 if (ISD::isNormalLoad(N)) { 1071 ExpandRes_NormalLoad(N, Lo, Hi); 1072 return; 1073 } 1074 1075 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); 1076 1077 MVT VT = N->getValueType(0); 1078 MVT NVT = TLI.getTypeToTransformTo(VT); 1079 SDOperand Ch = N->getChain(); 1080 SDOperand Ptr = N->getBasePtr(); 1081 ISD::LoadExtType ExtType = N->getExtensionType(); 1082 int SVOffset = N->getSrcValueOffset(); 1083 unsigned Alignment = N->getAlignment(); 1084 bool isVolatile = N->isVolatile(); 1085 1086 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 1087 1088 if (N->getMemoryVT().bitsLE(NVT)) { 1089 MVT EVT = N->getMemoryVT(); 1090 1091 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, 1092 isVolatile, Alignment); 1093 1094 // Remember the chain. 1095 Ch = Lo.getValue(1); 1096 1097 if (ExtType == ISD::SEXTLOAD) { 1098 // The high part is obtained by SRA'ing all but one of the bits of the 1099 // lo part. 1100 unsigned LoSize = Lo.getValueType().getSizeInBits(); 1101 Hi = DAG.getNode(ISD::SRA, NVT, Lo, 1102 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy())); 1103 } else if (ExtType == ISD::ZEXTLOAD) { 1104 // The high part is just a zero. 1105 Hi = DAG.getConstant(0, NVT); 1106 } else { 1107 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); 1108 // The high part is undefined. 1109 Hi = DAG.getNode(ISD::UNDEF, NVT); 1110 } 1111 } else if (TLI.isLittleEndian()) { 1112 // Little-endian - low bits are at low addresses. 1113 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1114 isVolatile, Alignment); 1115 1116 unsigned ExcessBits = 1117 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 1118 MVT NEVT = MVT::getIntegerVT(ExcessBits); 1119 1120 // Increment the pointer to the other half. 1121 unsigned IncrementSize = NVT.getSizeInBits()/8; 1122 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1123 DAG.getIntPtrConstant(IncrementSize)); 1124 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), 1125 SVOffset+IncrementSize, NEVT, 1126 isVolatile, MinAlign(Alignment, IncrementSize)); 1127 1128 // Build a factor node to remember that this load is independent of the 1129 // other one. 1130 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1131 Hi.getValue(1)); 1132 } else { 1133 // Big-endian - high bits are at low addresses. Favor aligned loads at 1134 // the cost of some bit-fiddling. 1135 MVT EVT = N->getMemoryVT(); 1136 unsigned EBytes = EVT.getStoreSizeInBits()/8; 1137 unsigned IncrementSize = NVT.getSizeInBits()/8; 1138 unsigned ExcessBits = (EBytes - IncrementSize)*8; 1139 1140 // Load both the high bits and maybe some of the low bits. 1141 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, 1142 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), 1143 isVolatile, Alignment); 1144 1145 // Increment the pointer to the other half. 1146 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 1147 DAG.getIntPtrConstant(IncrementSize)); 1148 // Load the rest of the low bits. 1149 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(), 1150 SVOffset+IncrementSize, 1151 MVT::getIntegerVT(ExcessBits), 1152 isVolatile, MinAlign(Alignment, IncrementSize)); 1153 1154 // Build a factor node to remember that this load is independent of the 1155 // other one. 1156 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1), 1157 Hi.getValue(1)); 1158 1159 if (ExcessBits < NVT.getSizeInBits()) { 1160 // Transfer low bits from the bottom of Hi to the top of Lo. 1161 Lo = DAG.getNode(ISD::OR, NVT, Lo, 1162 DAG.getNode(ISD::SHL, NVT, Hi, 1163 DAG.getConstant(ExcessBits, 1164 TLI.getShiftAmountTy()))); 1165 // Move high bits to the right position in Hi. 1166 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi, 1167 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 1168 TLI.getShiftAmountTy())); 1169 } 1170 } 1171 1172 // Legalized the chain result - switch anything that used the old chain to 1173 // use the new one. 1174 ReplaceValueWith(SDOperand(N, 1), Ch); 1175} 1176 1177void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, 1178 SDOperand &Lo, SDOperand &Hi) { 1179 SDOperand LL, LH, RL, RH; 1180 GetExpandedInteger(N->getOperand(0), LL, LH); 1181 GetExpandedInteger(N->getOperand(1), RL, RH); 1182 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL); 1183 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH); 1184} 1185 1186void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, 1187 SDOperand &Lo, SDOperand &Hi) { 1188 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands. 1189 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo); 1190 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi); 1191} 1192 1193void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, 1194 SDOperand &Lo, SDOperand &Hi) { 1195 // Expand the subcomponents. 1196 SDOperand LHSL, LHSH, RHSL, RHSH; 1197 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1198 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1199 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1200 SDOperand LoOps[2] = { LHSL, RHSL }; 1201 SDOperand HiOps[3] = { LHSH, RHSH }; 1202 1203 if (N->getOpcode() == ISD::ADD) { 1204 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1205 HiOps[2] = Lo.getValue(1); 1206 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1207 } else { 1208 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1209 HiOps[2] = Lo.getValue(1); 1210 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1211 } 1212} 1213 1214void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, 1215 SDOperand &Lo, SDOperand &Hi) { 1216 // Expand the subcomponents. 1217 SDOperand LHSL, LHSH, RHSL, RHSH; 1218 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1219 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1220 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1221 SDOperand LoOps[2] = { LHSL, RHSL }; 1222 SDOperand HiOps[3] = { LHSH, RHSH }; 1223 1224 if (N->getOpcode() == ISD::ADDC) { 1225 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1226 HiOps[2] = Lo.getValue(1); 1227 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1228 } else { 1229 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2); 1230 HiOps[2] = Lo.getValue(1); 1231 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3); 1232 } 1233 1234 // Legalized the flag result - switch anything that used the old flag to 1235 // use the new one. 1236 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1)); 1237} 1238 1239void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, 1240 SDOperand &Lo, SDOperand &Hi) { 1241 // Expand the subcomponents. 1242 SDOperand LHSL, LHSH, RHSL, RHSH; 1243 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1244 GetExpandedInteger(N->getOperand(1), RHSL, RHSH); 1245 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); 1246 SDOperand LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; 1247 SDOperand HiOps[3] = { LHSH, RHSH }; 1248 1249 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3); 1250 HiOps[2] = Lo.getValue(1); 1251 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3); 1252 1253 // Legalized the flag result - switch anything that used the old flag to 1254 // use the new one. 1255 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1)); 1256} 1257 1258void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, 1259 SDOperand &Lo, SDOperand &Hi) { 1260 MVT VT = N->getValueType(0); 1261 MVT NVT = TLI.getTypeToTransformTo(VT); 1262 1263 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT); 1264 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT); 1265 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT); 1266 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT); 1267 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) { 1268 SDOperand LL, LH, RL, RH; 1269 GetExpandedInteger(N->getOperand(0), LL, LH); 1270 GetExpandedInteger(N->getOperand(1), RL, RH); 1271 unsigned OuterBitSize = VT.getSizeInBits(); 1272 unsigned InnerBitSize = NVT.getSizeInBits(); 1273 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0)); 1274 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1)); 1275 1276 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize); 1277 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) && 1278 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) { 1279 // The inputs are both zero-extended. 1280 if (HasUMUL_LOHI) { 1281 // We can emit a umul_lohi. 1282 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1283 Hi = SDOperand(Lo.Val, 1); 1284 return; 1285 } 1286 if (HasMULHU) { 1287 // We can emit a mulhu+mul. 1288 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1289 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1290 return; 1291 } 1292 } 1293 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) { 1294 // The input values are both sign-extended. 1295 if (HasSMUL_LOHI) { 1296 // We can emit a smul_lohi. 1297 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL); 1298 Hi = SDOperand(Lo.Val, 1); 1299 return; 1300 } 1301 if (HasMULHS) { 1302 // We can emit a mulhs+mul. 1303 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1304 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL); 1305 return; 1306 } 1307 } 1308 if (HasUMUL_LOHI) { 1309 // Lo,Hi = umul LHS, RHS. 1310 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, 1311 DAG.getVTList(NVT, NVT), LL, RL); 1312 Lo = UMulLOHI; 1313 Hi = UMulLOHI.getValue(1); 1314 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1315 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1316 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1317 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1318 return; 1319 } 1320 if (HasMULHU) { 1321 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL); 1322 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL); 1323 RH = DAG.getNode(ISD::MUL, NVT, LL, RH); 1324 LH = DAG.getNode(ISD::MUL, NVT, LH, RL); 1325 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH); 1326 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH); 1327 return; 1328 } 1329 } 1330 1331 // If nothing else, we can make a libcall. 1332 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1333 if (VT == MVT::i32) 1334 LC = RTLIB::MUL_I32; 1335 else if (VT == MVT::i64) 1336 LC = RTLIB::MUL_I64; 1337 else if (VT == MVT::i128) 1338 LC = RTLIB::MUL_I128; 1339 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); 1340 1341 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1342 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi); 1343} 1344 1345void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, 1346 SDOperand &Lo, SDOperand &Hi) { 1347 MVT VT = N->getValueType(0); 1348 1349 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1350 if (VT == MVT::i32) 1351 LC = RTLIB::SDIV_I32; 1352 else if (VT == MVT::i64) 1353 LC = RTLIB::SDIV_I64; 1354 else if (VT == MVT::i128) 1355 LC = RTLIB::SDIV_I128; 1356 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1357 1358 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1359 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1360} 1361 1362void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, 1363 SDOperand &Lo, SDOperand &Hi) { 1364 MVT VT = N->getValueType(0); 1365 1366 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1367 if (VT == MVT::i32) 1368 LC = RTLIB::SREM_I32; 1369 else if (VT == MVT::i64) 1370 LC = RTLIB::SREM_I64; 1371 else if (VT == MVT::i128) 1372 LC = RTLIB::SREM_I128; 1373 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1374 1375 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1376 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi); 1377} 1378 1379void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, 1380 SDOperand &Lo, SDOperand &Hi) { 1381 MVT VT = N->getValueType(0); 1382 1383 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1384 if (VT == MVT::i32) 1385 LC = RTLIB::UDIV_I32; 1386 else if (VT == MVT::i64) 1387 LC = RTLIB::UDIV_I64; 1388 else if (VT == MVT::i128) 1389 LC = RTLIB::UDIV_I128; 1390 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); 1391 1392 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1393 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1394} 1395 1396void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, 1397 SDOperand &Lo, SDOperand &Hi) { 1398 MVT VT = N->getValueType(0); 1399 1400 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1401 if (VT == MVT::i32) 1402 LC = RTLIB::UREM_I32; 1403 else if (VT == MVT::i64) 1404 LC = RTLIB::UREM_I64; 1405 else if (VT == MVT::i128) 1406 LC = RTLIB::UREM_I128; 1407 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); 1408 1409 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1410 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi); 1411} 1412 1413void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, 1414 SDOperand &Lo, SDOperand &Hi) { 1415 MVT VT = N->getValueType(0); 1416 1417 // If we can emit an efficient shift operation, do so now. Check to see if 1418 // the RHS is a constant. 1419 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1420 return ExpandShiftByConstant(N, CN->getValue(), Lo, Hi); 1421 1422 // If we can determine that the high bit of the shift is zero or one, even if 1423 // the low bits are variable, emit this shift in an optimized form. 1424 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi)) 1425 return; 1426 1427 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc. 1428 unsigned PartsOpc; 1429 if (N->getOpcode() == ISD::SHL) { 1430 PartsOpc = ISD::SHL_PARTS; 1431 } else if (N->getOpcode() == ISD::SRL) { 1432 PartsOpc = ISD::SRL_PARTS; 1433 } else { 1434 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1435 PartsOpc = ISD::SRA_PARTS; 1436 } 1437 1438 // Next check to see if the target supports this SHL_PARTS operation or if it 1439 // will custom expand it. 1440 MVT NVT = TLI.getTypeToTransformTo(VT); 1441 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); 1442 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || 1443 Action == TargetLowering::Custom) { 1444 // Expand the subcomponents. 1445 SDOperand LHSL, LHSH; 1446 GetExpandedInteger(N->getOperand(0), LHSL, LHSH); 1447 1448 SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) }; 1449 MVT VT = LHSL.getValueType(); 1450 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3); 1451 Hi = Lo.getValue(1); 1452 return; 1453 } 1454 1455 // Otherwise, emit a libcall. 1456 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1457 bool isSigned; 1458 if (N->getOpcode() == ISD::SHL) { 1459 isSigned = false; /*sign irrelevant*/ 1460 if (VT == MVT::i32) 1461 LC = RTLIB::SHL_I32; 1462 else if (VT == MVT::i64) 1463 LC = RTLIB::SHL_I64; 1464 else if (VT == MVT::i128) 1465 LC = RTLIB::SHL_I128; 1466 } else if (N->getOpcode() == ISD::SRL) { 1467 isSigned = false; 1468 if (VT == MVT::i32) 1469 LC = RTLIB::SRL_I32; 1470 else if (VT == MVT::i64) 1471 LC = RTLIB::SRL_I64; 1472 else if (VT == MVT::i128) 1473 LC = RTLIB::SRL_I128; 1474 } else { 1475 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1476 isSigned = true; 1477 if (VT == MVT::i32) 1478 LC = RTLIB::SRA_I32; 1479 else if (VT == MVT::i64) 1480 LC = RTLIB::SRA_I64; 1481 else if (VT == MVT::i128) 1482 LC = RTLIB::SRA_I128; 1483 } 1484 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!"); 1485 1486 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) }; 1487 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi); 1488} 1489 1490void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, 1491 SDOperand &Lo, SDOperand &Hi) { 1492 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) 1493 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1494 MVT NVT = Lo.getValueType(); 1495 1496 SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 1497 DAG.getConstant(0, NVT), ISD::SETNE); 1498 1499 SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo); 1500 SDOperand HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi); 1501 1502 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ, 1503 DAG.getNode(ISD::ADD, NVT, LoLZ, 1504 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1505 Hi = DAG.getConstant(0, NVT); 1506} 1507 1508void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, 1509 SDOperand &Lo, SDOperand &Hi) { 1510 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) 1511 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1512 MVT NVT = Lo.getValueType(); 1513 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo), 1514 DAG.getNode(ISD::CTPOP, NVT, Hi)); 1515 Hi = DAG.getConstant(0, NVT); 1516} 1517 1518void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, 1519 SDOperand &Lo, SDOperand &Hi) { 1520 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) 1521 GetExpandedInteger(N->getOperand(0), Lo, Hi); 1522 MVT NVT = Lo.getValueType(); 1523 1524 SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, 1525 DAG.getConstant(0, NVT), ISD::SETNE); 1526 1527 SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo); 1528 SDOperand HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi); 1529 1530 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ, 1531 DAG.getNode(ISD::ADD, NVT, HiLZ, 1532 DAG.getConstant(NVT.getSizeInBits(), NVT))); 1533 Hi = DAG.getConstant(0, NVT); 1534} 1535 1536/// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, 1537/// and the shift amount is a constant 'Amt'. Expand the operation. 1538void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, 1539 SDOperand &Lo, SDOperand &Hi) { 1540 // Expand the incoming operand to be shifted, so that we have its parts 1541 SDOperand InL, InH; 1542 GetExpandedInteger(N->getOperand(0), InL, InH); 1543 1544 MVT NVT = InL.getValueType(); 1545 unsigned VTBits = N->getValueType(0).getSizeInBits(); 1546 unsigned NVTBits = NVT.getSizeInBits(); 1547 MVT ShTy = N->getOperand(1).getValueType(); 1548 1549 if (N->getOpcode() == ISD::SHL) { 1550 if (Amt > VTBits) { 1551 Lo = Hi = DAG.getConstant(0, NVT); 1552 } else if (Amt > NVTBits) { 1553 Lo = DAG.getConstant(0, NVT); 1554 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy)); 1555 } else if (Amt == NVTBits) { 1556 Lo = DAG.getConstant(0, NVT); 1557 Hi = InL; 1558 } else if (Amt == 1) { 1559 // Emit this X << 1 as X+X. 1560 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); 1561 SDOperand LoOps[2] = { InL, InL }; 1562 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2); 1563 SDOperand HiOps[3] = { InH, InH, Lo.getValue(1) }; 1564 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3); 1565 } else { 1566 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy)); 1567 Hi = DAG.getNode(ISD::OR, NVT, 1568 DAG.getNode(ISD::SHL, NVT, InH, 1569 DAG.getConstant(Amt, ShTy)), 1570 DAG.getNode(ISD::SRL, NVT, InL, 1571 DAG.getConstant(NVTBits-Amt, ShTy))); 1572 } 1573 return; 1574 } 1575 1576 if (N->getOpcode() == ISD::SRL) { 1577 if (Amt > VTBits) { 1578 Lo = DAG.getConstant(0, NVT); 1579 Hi = DAG.getConstant(0, NVT); 1580 } else if (Amt > NVTBits) { 1581 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy)); 1582 Hi = DAG.getConstant(0, NVT); 1583 } else if (Amt == NVTBits) { 1584 Lo = InH; 1585 Hi = DAG.getConstant(0, NVT); 1586 } else { 1587 Lo = DAG.getNode(ISD::OR, NVT, 1588 DAG.getNode(ISD::SRL, NVT, InL, 1589 DAG.getConstant(Amt, ShTy)), 1590 DAG.getNode(ISD::SHL, NVT, InH, 1591 DAG.getConstant(NVTBits-Amt, ShTy))); 1592 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy)); 1593 } 1594 return; 1595 } 1596 1597 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); 1598 if (Amt > VTBits) { 1599 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH, 1600 DAG.getConstant(NVTBits-1, ShTy)); 1601 } else if (Amt > NVTBits) { 1602 Lo = DAG.getNode(ISD::SRA, NVT, InH, 1603 DAG.getConstant(Amt-NVTBits, ShTy)); 1604 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1605 DAG.getConstant(NVTBits-1, ShTy)); 1606 } else if (Amt == NVTBits) { 1607 Lo = InH; 1608 Hi = DAG.getNode(ISD::SRA, NVT, InH, 1609 DAG.getConstant(NVTBits-1, ShTy)); 1610 } else { 1611 Lo = DAG.getNode(ISD::OR, NVT, 1612 DAG.getNode(ISD::SRL, NVT, InL, 1613 DAG.getConstant(Amt, ShTy)), 1614 DAG.getNode(ISD::SHL, NVT, InH, 1615 DAG.getConstant(NVTBits-Amt, ShTy))); 1616 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy)); 1617 } 1618} 1619 1620/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify 1621/// this shift based on knowledge of the high bit of the shift amount. If we 1622/// can tell this, we know that it is >= 32 or < 32, without knowing the actual 1623/// shift amount. 1624bool DAGTypeLegalizer:: 1625ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) { 1626 SDOperand Amt = N->getOperand(1); 1627 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); 1628 MVT ShTy = Amt.getValueType(); 1629 unsigned ShBits = ShTy.getSizeInBits(); 1630 unsigned NVTBits = NVT.getSizeInBits(); 1631 assert(isPowerOf2_32(NVTBits) && 1632 "Expanded integer type size not a power of two!"); 1633 1634 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); 1635 APInt KnownZero, KnownOne; 1636 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne); 1637 1638 // If we don't know anything about the high bits, exit. 1639 if (((KnownZero|KnownOne) & HighBitMask) == 0) 1640 return false; 1641 1642 // Get the incoming operand to be shifted. 1643 SDOperand InL, InH; 1644 GetExpandedInteger(N->getOperand(0), InL, InH); 1645 1646 // If we know that any of the high bits of the shift amount are one, then we 1647 // can do this as a couple of simple shifts. 1648 if (KnownOne.intersects(HighBitMask)) { 1649 // Mask out the high bit, which we know is set. 1650 Amt = DAG.getNode(ISD::AND, ShTy, Amt, 1651 DAG.getConstant(~HighBitMask, ShTy)); 1652 1653 switch (N->getOpcode()) { 1654 default: assert(0 && "Unknown shift"); 1655 case ISD::SHL: 1656 Lo = DAG.getConstant(0, NVT); // Low part is zero. 1657 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part. 1658 return true; 1659 case ISD::SRL: 1660 Hi = DAG.getConstant(0, NVT); // Hi part is zero. 1661 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part. 1662 return true; 1663 case ISD::SRA: 1664 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part. 1665 DAG.getConstant(NVTBits-1, ShTy)); 1666 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part. 1667 return true; 1668 } 1669 } 1670 1671 // If we know that all of the high bits of the shift amount are zero, then we 1672 // can do this as a couple of simple shifts. 1673 if ((KnownZero & HighBitMask) == HighBitMask) { 1674 // Compute 32-amt. 1675 SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy, 1676 DAG.getConstant(NVTBits, ShTy), 1677 Amt); 1678 unsigned Op1, Op2; 1679 switch (N->getOpcode()) { 1680 default: assert(0 && "Unknown shift"); 1681 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; 1682 case ISD::SRL: 1683 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break; 1684 } 1685 1686 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt); 1687 Hi = DAG.getNode(ISD::OR, NVT, 1688 DAG.getNode(Op1, NVT, InH, Amt), 1689 DAG.getNode(Op2, NVT, InL, Amt2)); 1690 return true; 1691 } 1692 1693 return false; 1694} 1695 1696 1697//===----------------------------------------------------------------------===// 1698// Integer Operand Expansion 1699//===----------------------------------------------------------------------===// 1700 1701/// ExpandIntegerOperand - This method is called when the specified operand of 1702/// the specified node is found to need expansion. At this point, all of the 1703/// result types of the node are known to be legal, but other operands of the 1704/// node may need promotion or expansion as well as the specified one. 1705bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { 1706 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); 1707 SDOperand Res = SDOperand(); 1708 1709 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType()) 1710 == TargetLowering::Custom) 1711 Res = TLI.LowerOperation(SDOperand(N, OpNo), DAG); 1712 1713 if (Res.Val == 0) { 1714 switch (N->getOpcode()) { 1715 default: 1716 #ifndef NDEBUG 1717 cerr << "ExpandIntegerOperand Op #" << OpNo << ": "; 1718 N->dump(&DAG); cerr << "\n"; 1719 #endif 1720 assert(0 && "Do not know how to expand this operator's operand!"); 1721 abort(); 1722 1723 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; 1724 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break; 1725 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break; 1726 1727 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break; 1728 1729 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; 1730 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break; 1731 1732 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break; 1733 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; 1734 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break; 1735 1736 case ISD::STORE: 1737 Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); 1738 break; 1739 } 1740 } 1741 1742 // If the result is null, the sub-method took care of registering results etc. 1743 if (!Res.Val) return false; 1744 // If the result is N, the sub-method updated N in place. Check to see if any 1745 // operands are new, and if so, mark them. 1746 if (Res.Val == N) { 1747 // Mark N as new and remark N and its operands. This allows us to correctly 1748 // revisit N if it needs another step of expansion and allows us to visit 1749 // any new operands to N. 1750 ReanalyzeNode(N); 1751 return true; 1752 } 1753 1754 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && 1755 "Invalid operand expansion"); 1756 1757 ReplaceValueWith(SDOperand(N, 0), Res); 1758 return false; 1759} 1760 1761SDOperand DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { 1762 SDOperand InL, InH; 1763 GetExpandedInteger(N->getOperand(0), InL, InH); 1764 // Just truncate the low part of the source. 1765 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL); 1766} 1767 1768SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { 1769 SDOperand Op = N->getOperand(0); 1770 MVT SrcVT = Op.getValueType(); 1771 MVT DstVT = N->getValueType(0); 1772 1773 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1774 if (SrcVT == MVT::i32) { 1775 if (DstVT == MVT::f32) 1776 LC = RTLIB::SINTTOFP_I32_F32; 1777 else if (DstVT == MVT::f64) 1778 LC = RTLIB::SINTTOFP_I32_F64; 1779 else if (DstVT == MVT::f80) 1780 LC = RTLIB::SINTTOFP_I32_F80; 1781 else if (DstVT == MVT::ppcf128) 1782 LC = RTLIB::SINTTOFP_I32_PPCF128; 1783 } else if (SrcVT == MVT::i64) { 1784 if (DstVT == MVT::f32) 1785 LC = RTLIB::SINTTOFP_I64_F32; 1786 else if (DstVT == MVT::f64) 1787 LC = RTLIB::SINTTOFP_I64_F64; 1788 else if (DstVT == MVT::f80) 1789 LC = RTLIB::SINTTOFP_I64_F80; 1790 else if (DstVT == MVT::ppcf128) 1791 LC = RTLIB::SINTTOFP_I64_PPCF128; 1792 } else if (SrcVT == MVT::i128) { 1793 if (DstVT == MVT::f32) 1794 LC = RTLIB::SINTTOFP_I128_F32; 1795 else if (DstVT == MVT::f64) 1796 LC = RTLIB::SINTTOFP_I128_F64; 1797 else if (DstVT == MVT::f80) 1798 LC = RTLIB::SINTTOFP_I128_F80; 1799 else if (DstVT == MVT::ppcf128) 1800 LC = RTLIB::SINTTOFP_I128_PPCF128; 1801 } 1802 assert(LC != RTLIB::UNKNOWN_LIBCALL && 1803 "Don't know how to expand this SINT_TO_FP!"); 1804 1805 return MakeLibCall(LC, DstVT, &Op, 1, true); 1806} 1807 1808SDOperand DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { 1809 SDOperand Op = N->getOperand(0); 1810 MVT SrcVT = Op.getValueType(); 1811 MVT DstVT = N->getValueType(0); 1812 1813 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ 1814 // Do a signed conversion then adjust the result. 1815 SDOperand SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op); 1816 SignedConv = TLI.LowerOperation(SignedConv, DAG); 1817 1818 // The result of the signed conversion needs adjusting if the 'sign bit' of 1819 // the incoming integer was set. To handle this, we dynamically test to see 1820 // if it is set, and, if so, add a fudge factor. 1821 1822 const uint64_t F32TwoE32 = 0x4F800000ULL; 1823 const uint64_t F32TwoE64 = 0x5F800000ULL; 1824 const uint64_t F32TwoE128 = 0x7F800000ULL; 1825 1826 APInt FF(32, 0); 1827 if (SrcVT == MVT::i32) 1828 FF = APInt(32, F32TwoE32); 1829 else if (SrcVT == MVT::i64) 1830 FF = APInt(32, F32TwoE64); 1831 else if (SrcVT == MVT::i128) 1832 FF = APInt(32, F32TwoE128); 1833 else 1834 assert(false && "Unsupported UINT_TO_FP!"); 1835 1836 // Check whether the sign bit is set. 1837 SDOperand Lo, Hi; 1838 GetExpandedInteger(Op, Lo, Hi); 1839 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi, 1840 DAG.getConstant(0, Hi.getValueType()), 1841 ISD::SETLT); 1842 1843 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 1844 SDOperand FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)), 1845 TLI.getPointerTy()); 1846 1847 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 1848 SDOperand Zero = DAG.getIntPtrConstant(0); 1849 SDOperand Four = DAG.getIntPtrConstant(4); 1850 if (TLI.isBigEndian()) std::swap(Zero, Four); 1851 SDOperand Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet, 1852 Zero, Four); 1853 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset); 1854 1855 // Load the value out, extending it from f32 to the destination float type. 1856 // FIXME: Avoid the extend by constructing the right constant pool? 1857 SDOperand Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(), 1858 FudgePtr, NULL, 0, MVT::f32); 1859 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge); 1860 } 1861 1862 // Otherwise, use a libcall. 1863 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1864 if (SrcVT == MVT::i32) { 1865 if (DstVT == MVT::f32) 1866 LC = RTLIB::UINTTOFP_I32_F32; 1867 else if (DstVT == MVT::f64) 1868 LC = RTLIB::UINTTOFP_I32_F64; 1869 else if (DstVT == MVT::f80) 1870 LC = RTLIB::UINTTOFP_I32_F80; 1871 else if (DstVT == MVT::ppcf128) 1872 LC = RTLIB::UINTTOFP_I32_PPCF128; 1873 } else if (SrcVT == MVT::i64) { 1874 if (DstVT == MVT::f32) 1875 LC = RTLIB::UINTTOFP_I64_F32; 1876 else if (DstVT == MVT::f64) 1877 LC = RTLIB::UINTTOFP_I64_F64; 1878 else if (DstVT == MVT::f80) 1879 LC = RTLIB::UINTTOFP_I64_F80; 1880 else if (DstVT == MVT::ppcf128) 1881 LC = RTLIB::UINTTOFP_I64_PPCF128; 1882 } else if (SrcVT == MVT::i128) { 1883 if (DstVT == MVT::f32) 1884 LC = RTLIB::UINTTOFP_I128_F32; 1885 else if (DstVT == MVT::f64) 1886 LC = RTLIB::UINTTOFP_I128_F64; 1887 else if (DstVT == MVT::f80) 1888 LC = RTLIB::UINTTOFP_I128_F80; 1889 else if (DstVT == MVT::ppcf128) 1890 LC = RTLIB::UINTTOFP_I128_PPCF128; 1891 } 1892 assert(LC != RTLIB::UNKNOWN_LIBCALL && 1893 "Don't know how to expand this UINT_TO_FP!"); 1894 1895 return MakeLibCall(LC, DstVT, &Op, 1, true); 1896} 1897 1898SDOperand DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) { 1899 SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3); 1900 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); 1901 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 1902 1903 // If ExpandSetCCOperands returned a scalar, we need to compare the result 1904 // against zero to select between true and false values. 1905 if (NewRHS.Val == 0) { 1906 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1907 CCCode = ISD::SETNE; 1908 } 1909 1910 // Update N to have the operands specified. 1911 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), 1912 DAG.getCondCode(CCCode), NewLHS, NewRHS, 1913 N->getOperand(4)); 1914} 1915 1916SDOperand DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) { 1917 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 1918 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); 1919 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 1920 1921 // If ExpandSetCCOperands returned a scalar, we need to compare the result 1922 // against zero to select between true and false values. 1923 if (NewRHS.Val == 0) { 1924 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1925 CCCode = ISD::SETNE; 1926 } 1927 1928 // Update N to have the operands specified. 1929 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS, 1930 N->getOperand(2), N->getOperand(3), 1931 DAG.getCondCode(CCCode)); 1932} 1933 1934SDOperand DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) { 1935 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1); 1936 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); 1937 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode); 1938 1939 // If ExpandSetCCOperands returned a scalar, use it. 1940 if (NewRHS.Val == 0) { 1941 assert(NewLHS.getValueType() == N->getValueType(0) && 1942 "Unexpected setcc expansion!"); 1943 return NewLHS; 1944 } 1945 1946 // Otherwise, update N to have the operands specified. 1947 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS, 1948 DAG.getCondCode(CCCode)); 1949} 1950 1951/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code 1952/// is shared among BR_CC, SELECT_CC, and SETCC handlers. 1953void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDOperand &NewLHS, 1954 SDOperand &NewRHS, 1955 ISD::CondCode &CCCode) { 1956 SDOperand LHSLo, LHSHi, RHSLo, RHSHi; 1957 GetExpandedInteger(NewLHS, LHSLo, LHSHi); 1958 GetExpandedInteger(NewRHS, RHSLo, RHSHi); 1959 1960 MVT VT = NewLHS.getValueType(); 1961 1962 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { 1963 if (RHSLo == RHSHi) { 1964 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) { 1965 if (RHSCST->isAllOnesValue()) { 1966 // Equality comparison to -1. 1967 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi); 1968 NewRHS = RHSLo; 1969 return; 1970 } 1971 } 1972 } 1973 1974 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo); 1975 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi); 1976 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS); 1977 NewRHS = DAG.getConstant(0, NewLHS.getValueType()); 1978 return; 1979 } 1980 1981 // If this is a comparison of the sign bit, just look at the top part. 1982 // X > -1, x < 0 1983 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS)) 1984 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0 1985 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1 1986 NewLHS = LHSHi; 1987 NewRHS = RHSHi; 1988 return; 1989 } 1990 1991 // FIXME: This generated code sucks. 1992 ISD::CondCode LowCC; 1993 switch (CCCode) { 1994 default: assert(0 && "Unknown integer setcc!"); 1995 case ISD::SETLT: 1996 case ISD::SETULT: LowCC = ISD::SETULT; break; 1997 case ISD::SETGT: 1998 case ISD::SETUGT: LowCC = ISD::SETUGT; break; 1999 case ISD::SETLE: 2000 case ISD::SETULE: LowCC = ISD::SETULE; break; 2001 case ISD::SETGE: 2002 case ISD::SETUGE: LowCC = ISD::SETUGE; break; 2003 } 2004 2005 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison 2006 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands 2007 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2; 2008 2009 // NOTE: on targets without efficient SELECT of bools, we can always use 2010 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3) 2011 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL); 2012 SDOperand Tmp1, Tmp2; 2013 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC, 2014 false, DagCombineInfo); 2015 if (!Tmp1.Val) 2016 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC); 2017 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2018 CCCode, false, DagCombineInfo); 2019 if (!Tmp2.Val) 2020 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2021 DAG.getCondCode(CCCode)); 2022 2023 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val); 2024 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val); 2025 if ((Tmp1C && Tmp1C->isNullValue()) || 2026 (Tmp2C && Tmp2C->isNullValue() && 2027 (CCCode == ISD::SETLE || CCCode == ISD::SETGE || 2028 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || 2029 (Tmp2C && Tmp2C->getAPIntValue() == 1 && 2030 (CCCode == ISD::SETLT || CCCode == ISD::SETGT || 2031 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { 2032 // low part is known false, returns high part. 2033 // For LE / GE, if high part is known false, ignore the low part. 2034 // For LT / GT, if high part is known true, ignore the low part. 2035 NewLHS = Tmp2; 2036 NewRHS = SDOperand(); 2037 return; 2038 } 2039 2040 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2041 ISD::SETEQ, false, DagCombineInfo); 2042 if (!NewLHS.Val) 2043 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, 2044 ISD::SETEQ); 2045 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), 2046 NewLHS, Tmp1, Tmp2); 2047 NewRHS = SDOperand(); 2048} 2049 2050SDOperand DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { 2051 if (ISD::isNormalStore(N)) 2052 return ExpandOp_NormalStore(N, OpNo); 2053 2054 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); 2055 assert(OpNo == 1 && "Can only expand the stored value so far"); 2056 2057 MVT VT = N->getOperand(1).getValueType(); 2058 MVT NVT = TLI.getTypeToTransformTo(VT); 2059 SDOperand Ch = N->getChain(); 2060 SDOperand Ptr = N->getBasePtr(); 2061 int SVOffset = N->getSrcValueOffset(); 2062 unsigned Alignment = N->getAlignment(); 2063 bool isVolatile = N->isVolatile(); 2064 SDOperand Lo, Hi; 2065 2066 assert(NVT.isByteSized() && "Expanded type not byte sized!"); 2067 2068 if (N->getMemoryVT().bitsLE(NVT)) { 2069 GetExpandedInteger(N->getValue(), Lo, Hi); 2070 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 2071 N->getMemoryVT(), isVolatile, Alignment); 2072 } else if (TLI.isLittleEndian()) { 2073 // Little-endian - low bits are at low addresses. 2074 GetExpandedInteger(N->getValue(), Lo, Hi); 2075 2076 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset, 2077 isVolatile, Alignment); 2078 2079 unsigned ExcessBits = 2080 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); 2081 MVT NEVT = MVT::getIntegerVT(ExcessBits); 2082 2083 // Increment the pointer to the other half. 2084 unsigned IncrementSize = NVT.getSizeInBits()/8; 2085 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2086 DAG.getIntPtrConstant(IncrementSize)); 2087 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2088 SVOffset+IncrementSize, NEVT, 2089 isVolatile, MinAlign(Alignment, IncrementSize)); 2090 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2091 } else { 2092 // Big-endian - high bits are at low addresses. Favor aligned stores at 2093 // the cost of some bit-fiddling. 2094 GetExpandedInteger(N->getValue(), Lo, Hi); 2095 2096 MVT EVT = N->getMemoryVT(); 2097 unsigned EBytes = EVT.getStoreSizeInBits()/8; 2098 unsigned IncrementSize = NVT.getSizeInBits()/8; 2099 unsigned ExcessBits = (EBytes - IncrementSize)*8; 2100 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); 2101 2102 if (ExcessBits < NVT.getSizeInBits()) { 2103 // Transfer high bits from the top of Lo to the bottom of Hi. 2104 Hi = DAG.getNode(ISD::SHL, NVT, Hi, 2105 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, 2106 TLI.getShiftAmountTy())); 2107 Hi = DAG.getNode(ISD::OR, NVT, Hi, 2108 DAG.getNode(ISD::SRL, NVT, Lo, 2109 DAG.getConstant(ExcessBits, 2110 TLI.getShiftAmountTy()))); 2111 } 2112 2113 // Store both the high bits and maybe some of the low bits. 2114 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(), 2115 SVOffset, HiVT, isVolatile, Alignment); 2116 2117 // Increment the pointer to the other half. 2118 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 2119 DAG.getIntPtrConstant(IncrementSize)); 2120 // Store the lowest ExcessBits bits in the second half. 2121 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), 2122 SVOffset+IncrementSize, 2123 MVT::getIntegerVT(ExcessBits), 2124 isVolatile, MinAlign(Alignment, IncrementSize)); 2125 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi); 2126 } 2127} 2128